Merge branch 'master' of git://www.denx.de/git/u-boot-mpc83xx

Conflicts:

	lib_ppc/board.c

Signed-off-by: Wolfgang Denk <wd@denx.de>

6 files changed, 114 insertions, 70 deletions

diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index b43dba3..9ccf7d6 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -74,7 +74,6 @@ typedef	struct	global_data {
 	u32 enc_clk;
 	u32 lbiu_clk;
 	u32 lclk_clk;
-	u32 ddr_clk;
 	u32 pci_clk;
 #if defined(CONFIG_MPC837X)
 	u32 pciexp1_clk;
@@ -84,7 +83,7 @@ typedef	struct	global_data {
 	u32 sata_clk;
 #endif
 #if defined(CONFIG_MPC8360)
-	u32  ddr_sec_clk;
+	u32  mem_sec_clk;
 #endif /* CONFIG_MPC8360 */
 #endif
 #if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index af78726..432fb31 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -349,6 +349,29 @@
 #define CONFIG_ETHPRIME		"eTSEC1"
 
 /*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CFG_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CFG_SATA1_OFFSET	0x18000
+#define CFG_SATA1		(CFG_IMMR + CFG_SATA1_OFFSET)
+#define CFG_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CFG_SATA2_OFFSET	0x19000
+#define CFG_SATA2		(CFG_IMMR + CFG_SATA2_OFFSET)
+#define CFG_SATA2_FLAGS		FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
  * Environment
  */
 #ifndef CFG_RAMBOOT
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 94c4c6b..92d7aa4 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -323,8 +323,11 @@
 /*
  * Config on-board EEPROM
  */
-#define CFG_I2C_EEPROM_ADDR     0x50
-#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_I2C_EEPROM_ADDR		0x50
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+#define CFG_EEPROM_PAGE_WRITE_BITS	6
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*
  * General PCI
@@ -341,7 +344,7 @@
 #define CFG_PCI1_IO_SIZE		0x04000000	/* 64M */
 
 #ifdef CONFIG_PCI
-
+#define CONFIG_PCI_SKIP_HOST_BRIDGE
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP		/* do pci plug-and-play */
 
@@ -549,6 +552,9 @@
 #define CONFIG_HAS_ETH1				/* add support for "eth1addr" */
 #define CONFIG_ETH1ADDR	00:04:9f:ef:03:02
 
+/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */
+#define CFG_I2C_MAC_OFFSET	0x7f00	/* MAC address offset in I2C EEPROM */
+
 #define CONFIG_IPADDR		10.0.0.2
 #define CONFIG_SERVERIP		10.0.0.1
 #define CONFIG_GATEWAYIP	10.0.0.1
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index b307bf7..7c4e76e 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -389,6 +389,34 @@
 /* Options are: TSEC[0-1] */
 #define CONFIG_ETHPRIME		"eTSEC1"
 
+/* SERDES */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+#define CONFIG_FSL_SERDES2	0xe3100
+
+/*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CFG_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CFG_SATA1_OFFSET	0x18000
+#define CFG_SATA1		(CFG_IMMR + CFG_SATA1_OFFSET)
+#define CFG_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CFG_SATA2_OFFSET	0x19000
+#define CFG_SATA2		(CFG_IMMR + CFG_SATA2_OFFSET)
+#define CFG_SATA2_FLAGS		FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
 /*
  * Environment
  */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 90812e9..eaac525 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -416,6 +416,29 @@
 #endif
 
 /*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CFG_SATA_MAX_DEVICE	2
+#define CONFIG_SATA1
+#define CFG_SATA1_OFFSET	0x18000
+#define CFG_SATA1		(CFG_IMMR + CFG_SATA1_OFFSET)
+#define CFG_SATA1_FLAGS		FLAGS_DMA
+#define CONFIG_SATA2
+#define CFG_SATA2_OFFSET	0x19000
+#define CFG_SATA2		(CFG_IMMR + CFG_SATA2_OFFSET)
+#define CFG_SATA2_FLAGS		FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
  * Environment
  */
 #ifndef CFG_RAMBOOT
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 4ee38aa..d2e1e2b 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -48,71 +48,36 @@
 
 /* SPRIDR - System Part and Revision ID Register
  */
-#define SPRIDR_PARTID			0xFFFF0000	/* Part Identification */
-#define SPRIDR_REVID			0x0000FFFF	/* Revision Identification */
-
-#define SPR_8349E_REV10			0x80300100
-#define SPR_8349_REV10			0x80310100
-#define SPR_8347E_REV10_TBGA		0x80320100
-#define SPR_8347_REV10_TBGA		0x80330100
-#define SPR_8347E_REV10_PBGA		0x80340100
-#define SPR_8347_REV10_PBGA		0x80350100
-#define SPR_8343E_REV10			0x80360100
-#define SPR_8343_REV10			0x80370100
-
-#define SPR_8349E_REV11			0x80300101
-#define SPR_8349_REV11			0x80310101
-#define SPR_8347E_REV11_TBGA		0x80320101
-#define SPR_8347_REV11_TBGA		0x80330101
-#define SPR_8347E_REV11_PBGA		0x80340101
-#define SPR_8347_REV11_PBGA		0x80350101
-#define SPR_8343E_REV11			0x80360101
-#define SPR_8343_REV11			0x80370101
-
-#define SPR_8349E_REV31			0x80300300
-#define SPR_8349_REV31			0x80310300
-#define SPR_8347E_REV31_TBGA		0x80320300
-#define SPR_8347_REV31_TBGA		0x80330300
-#define SPR_8347E_REV31_PBGA		0x80340300
-#define SPR_8347_REV31_PBGA		0x80350300
-#define SPR_8343E_REV31			0x80360300
-#define SPR_8343_REV31			0x80370300
-
-#define SPR_8360E_REV10			0x80480010
-#define SPR_8360_REV10			0x80490010
-#define SPR_8360E_REV11			0x80480011
-#define SPR_8360_REV11			0x80490011
-#define SPR_8360E_REV12			0x80480012
-#define SPR_8360_REV12			0x80490012
-#define SPR_8360E_REV20			0x80480020
-#define SPR_8360_REV20			0x80490020
-#define SPR_8360E_REV21			0x80480021
-#define SPR_8360_REV21			0x80490021
-
-#define SPR_8323E_REV10			0x80620010
-#define SPR_8323_REV10			0x80630010
-#define SPR_8321E_REV10			0x80660010
-#define SPR_8321_REV10			0x80670010
-#define SPR_8323E_REV11			0x80620011
-#define SPR_8323_REV11			0x80630011
-#define SPR_8321E_REV11			0x80660011
-#define SPR_8321_REV11			0x80670011
-
-#define SPR_8313E_REV10			0x80B00010
-#define SPR_8313_REV10			0x80B10010
-#define SPR_8311E_REV10			0x80B20010
-#define SPR_8311_REV10			0x80B30010
-#define SPR_8315E_REV10			0x80B40010
-#define SPR_8315_REV10			0x80B50010
-#define SPR_8314E_REV10			0x80B60010
-#define SPR_8314_REV10			0x80B70010
-
-#define SPR_8379E_REV10			0x80C20010
-#define SPR_8379_REV10			0x80C30010
-#define SPR_8378E_REV10			0x80C40010
-#define SPR_8378_REV10			0x80C50010
-#define SPR_8377E_REV10			0x80C60010
-#define SPR_8377_REV10			0x80C70010
+#define SPRIDR_PARTID			0xFFFF0000	/* Part Id */
+#define SPRIDR_REVID			0x0000FFFF	/* Revision Id */
+
+#if defined(CONFIG_MPC834X)
+#define REVID_MAJOR(spridr)		((spridr & 0x0000FF00) >> 8)
+#define REVID_MINOR(spridr)		(spridr & 0x000000FF)
+#else
+#define REVID_MAJOR(spridr)		((spridr & 0x000000F0) >> 4)
+#define REVID_MINOR(spridr)		(spridr & 0x0000000F)
+#endif
+
+#define PARTID_NO_E(spridr)		((spridr & 0xFFFE0000) >> 16)
+#define IS_E_PROCESSOR(spridr)		(!(spridr & 0x00010000)) /* has SEC */
+
+#define SPR_8311			0x80B2
+#define SPR_8313			0x80B0
+#define SPR_8314			0x80B6
+#define SPR_8315			0x80B4
+#define SPR_8321			0x8066
+#define SPR_8323			0x8062
+#define SPR_8343			0x8036
+#define SPR_8347_TBGA_			0x8032
+#define SPR_8347_PBGA_			0x8034
+#define SPR_8349			0x8030
+#define SPR_8358_TBGA_			0x804A
+#define SPR_8358_PBGA_			0x804E
+#define SPR_8360			0x8048
+#define SPR_8377			0x80C6
+#define SPR_8378			0x80C4
+#define SPR_8379			0x80C2
 
 /* SPCR - System Priority Configuration Register
  */