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authorStefan Roese <sr@denx.de>2009-09-24 11:59:57 (GMT)
committerStefan Roese <sr@denx.de>2009-09-28 08:45:54 (GMT)
commit95b602bab5fec2fffab07a01ea3947c70d1bacc1 (patch)
treeacee523787d213090cc592029f1d566473bc1fd7 /nand_spl
parent952e7760bfc5b0e3b142b9ce34e7fbb7d008c900 (diff)
downloadu-boot-95b602bab5fec2fffab07a01ea3947c70d1bacc1.tar.xz
ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case
The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'nand_spl')
-rw-r--r--nand_spl/board/amcc/bamboo/sdram.c26
1 files changed, 13 insertions, 13 deletions
diff --git a/nand_spl/board/amcc/bamboo/sdram.c b/nand_spl/board/amcc/bamboo/sdram.c
index df03afe..9fec5ca 100644
--- a/nand_spl/board/amcc/bamboo/sdram.c
+++ b/nand_spl/board/amcc/bamboo/sdram.c
@@ -31,7 +31,7 @@ static void wait_init_complete(void)
u32 val;
do {
- mfsdram(mem_mcsts, val);
+ mfsdram(SDRAM0_MCSTS, val);
} while (!(val & 0x80000000));
}
@@ -62,30 +62,30 @@ phys_size_t initdram(int board_type)
/*
* Disable memory controller.
*/
- mtsdram(mem_cfg0, 0x00000000);
+ mtsdram(SDRAM0_CFG0, 0x00000000);
/*
* Setup some default
*/
- mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
- mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
- mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
- mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
- mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
+ mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */
+ mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
+ mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */
+ mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */
+ mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
- mtsdram(mem_b0cr, 0x00082001);
- mtsdram(mem_tr0, 0x41094012);
- mtsdram(mem_tr1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
- mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
- mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
+ mtsdram(SDRAM0_B0CR, 0x00082001);
+ mtsdram(SDRAM0_TR0, 0x41094012);
+ mtsdram(SDRAM0_TR1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
+ mtsdram(SDRAM0_RTR, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
+ mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM*/
/*
* Enable the controller, then wait for DCEN to complete
*/
- mtsdram(mem_cfg0, 0x80000000); /* DCEN=1, PMUD=0*/
+ mtsdram(SDRAM0_CFG0, 0x80000000); /* DCEN=1, PMUD=0*/
wait_init_complete();
return CONFIG_SYS_MBYTES_SDRAM << 20;