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-rw-r--r--board/delta/nand.c42
-rw-r--r--config.mk7
-rw-r--r--cpu/pxa/config.mk1
-rw-r--r--include/configs/delta.h2
4 files changed, 48 insertions, 4 deletions
diff --git a/board/delta/nand.c b/board/delta/nand.c
index 9caddba..bd1bb4f 100644
--- a/board/delta/nand.c
+++ b/board/delta/nand.c
@@ -141,7 +141,7 @@ static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
switch (command) {
case NAND_CMD_READID:
printk("delta_cmdfunc: NAND_CMD_READID.\n");
- ndcb0 |= ((3 << 21) | (2 << 16));
+ ndcb0 |= ((3 << 21) | (1 << 16)); /* addr cycles*/
break;
case NAND_CMD_PAGEPROG:
case NAND_CMD_ERASE1:
@@ -161,6 +161,43 @@ static void delta_cmdfunc(struct mtd_info *mtd, unsigned command,
NDCB2 = ndcb2;
}
+void delta_dfc_gpio_init()
+{
+ printf("Setting up DFC GPIO's.\n");
+
+ /* no idea what is done here, see zylonite.c */
+ GPIO4 = 0x1;
+
+ DF_ALE_WE1 = 0x00000001;
+ DF_ALE_WE2 = 0x00000001;
+ DF_nCS0 = 0x00000001;
+ DF_nCS1 = 0x00000001;
+ DF_nWE = 0x00000001;
+ DF_nRE = 0x00000001;
+ DF_IO0 = 0x00000001;
+ DF_IO8 = 0x00000001;
+ DF_IO1 = 0x00000001;
+ DF_IO9 = 0x00000001;
+ DF_IO2 = 0x00000001;
+ DF_IO10 = 0x00000001;
+ DF_IO3 = 0x00000001;
+ DF_IO11 = 0x00000001;
+ DF_IO4 = 0x00000001;
+ DF_IO12 = 0x00000001;
+ DF_IO5 = 0x00000001;
+ DF_IO13 = 0x00000001;
+ DF_IO6 = 0x00000001;
+ DF_IO14 = 0x00000001;
+ DF_IO7 = 0x00000001;
+ DF_IO15 = 0x00000001;
+
+ DF_nWE = 0x1901;
+ DF_nRE = 0x1901;
+ DF_CLE_NOE = 0x1900;
+ DF_ALE_WE1 = 0x1901;
+ DF_INT_RnB = 0x1900;
+}
+
/*
* Board-specific NAND initialization. The following members of the
* argument are board-specific (per include/linux/mtd/nand_new.h):
@@ -184,7 +221,8 @@ void board_nand_init(struct nand_chip *nand)
unsigned long tCH, tCS, tWH, tWP, tRH, tRP, tRP_high, tR, tWHR, tAR;
/* set up GPIO Control Registers */
-
+ delta_dfc_gpio_init();
+
/* turn on the NAND Controller Clock (104 MHz @ D0) */
CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
diff --git a/config.mk b/config.mk
index 2c6cfb4..aef099e 100644
--- a/config.mk
+++ b/config.mk
@@ -132,9 +132,14 @@ CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes
endif
ifdef WILD_WILD_WEST
-CFLAGS := $(CFLAGS) -Werror
+CFLAGS := $(CPPFLAGS) -Werror
endif
+ifdef NO_JUMP
+CFLAGS := $(CPPFLAGS) -fno-schedule-insns -fno-schedule-insns2
+endif
+
+
# avoid trigraph warnings while parsing pci.h (produced by NIOS gcc-2.9)
# this option have to be placed behind -Wall -- that's why it is here
ifeq ($(ARCH),nios)
diff --git a/cpu/pxa/config.mk b/cpu/pxa/config.mk
index fb810ca..f30a1fe 100644
--- a/cpu/pxa/config.mk
+++ b/cpu/pxa/config.mk
@@ -33,4 +33,5 @@ PLATFORM_CPPFLAGS += -march=armv5 -mtune=xscale
#
# ========================================================================
PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+# for gcc-3x: PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/include/configs/delta.h b/include/configs/delta.h
index 9bc2954..ac412ee 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -164,7 +164,7 @@
*/
/* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */
#define CONFIG_NEW_NAND_CODE
-#define CFG_NAND0_BASE 0x10000000
+#define CFG_NAND0_BASE 0x43100040 /* 0x10000000 */
#undef CFG_NAND1_BASE
#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE }