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-rw-r--r--board/xilinx/zynq/board.c4
-rw-r--r--drivers/fpga/zynqpl.c6
-rw-r--r--include/zynqpl.h5
3 files changed, 14 insertions, 1 deletions
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 4bb140e..c173f0c 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -20,6 +20,7 @@ Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
#endif
int board_init(void)
@@ -42,6 +43,9 @@ int board_init(void)
case XILINX_ZYNQ_7045:
fpga = fpga045;
break;
+ case XILINX_ZYNQ_7100:
+ fpga = fpga100;
+ break;
}
#endif
diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 8cc16fd..14363c9 100644
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -23,6 +23,7 @@
#define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
#define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
#define DEVCFG_STATUS_PCFG_INIT 0x00000010
+#define DEVCFG_MCTRL_PCAP_LPBK 0x00000010
#define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
#define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
@@ -31,7 +32,7 @@
#endif
#ifndef CONFIG_SYS_FPGA_PROG_TIME
-#define CONFIG_SYS_FPGA_PROG_TIME CONFIG_SYS_HZ /* 1 s */
+#define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
#endif
int zynq_info(Xilinx_desc *desc)
@@ -200,6 +201,9 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
swap = SWAP_DONE;
}
+ /* Clear loopback bit */
+ clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
+
if (!partialbit) {
zynq_slcr_devcfg_disable();
diff --git a/include/zynqpl.h b/include/zynqpl.h
index f8211cd..6107cbf 100644
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -20,12 +20,14 @@ extern int zynq_info(Xilinx_desc *desc);
#define XILINX_ZYNQ_7020 0x7
#define XILINX_ZYNQ_7030 0xc
#define XILINX_ZYNQ_7045 0x11
+#define XILINX_ZYNQ_7100 0x16
/* Device Image Sizes */
#define XILINX_XC7Z010_SIZE 16669920/8
#define XILINX_XC7Z020_SIZE 32364512/8
#define XILINX_XC7Z030_SIZE 47839328/8
#define XILINX_XC7Z045_SIZE 106571232/8
+#define XILINX_XC7Z100_SIZE 139330784/8
/* Descriptor Macros */
#define XILINX_XC7Z010_DESC(cookie) \
@@ -40,4 +42,7 @@ extern int zynq_info(Xilinx_desc *desc);
#define XILINX_XC7Z045_DESC(cookie) \
{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }
+#define XILINX_XC7Z100_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, "7z100" }
+
#endif /* _ZYNQPL_H_ */