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-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c22
-rw-r--r--include/configs/mx6_common.h1
2 files changed, 20 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index d8ccf3a..0208cba 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -124,7 +124,7 @@ static void clear_ldo_ramp(void)
static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
- u32 val, reg = readl(&anatop->reg_core);
+ u32 val, step, old, reg = readl(&anatop->reg_core);
u8 shift;
if (mv < 725)
@@ -150,9 +150,20 @@ static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
return -EINVAL;
}
+ old = (reg & (0x1F << shift)) >> shift;
+ step = abs(val - old);
+ if (step == 0)
+ return 0;
+
reg = (reg & ~(0x1F << shift)) | (val << shift);
writel(reg, &anatop->reg_core);
+ /*
+ * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
+ * step
+ */
+ udelay(3 * step);
+
return 0;
}
@@ -170,8 +181,6 @@ int arch_cpu_init(void)
{
init_aips();
- set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
-
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
#ifdef CONFIG_APBH_DMA
@@ -182,6 +191,13 @@ int arch_cpu_init(void)
return 0;
}
+int board_postclk_init(void)
+{
+ set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
+
+ return 0;
+}
+
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 674bcd3..514d634 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -20,5 +20,6 @@
#define CONFIG_ARM_ERRATA_742230
#define CONFIG_ARM_ERRATA_743622
#define CONFIG_ARM_ERRATA_751472
+#define CONFIG_BOARD_POSTCLK_INIT
#endif