diff options
64 files changed, 5018 insertions, 1373 deletions
@@ -1351,7 +1351,8 @@ spl/u-boot-spl.sfp: spl/u-boot-spl spl/boot.bin: spl/u-boot-spl @: -tpl/u-boot-tpl.bin: tools prepare +tpl/u-boot-tpl.bin: tools prepare \ + $(if $(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) $(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all TAG_SUBDIRS := $(patsubst %,$(srctree)/%,$(u-boot-dirs) include) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 462c690..bc4dc2c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -29,17 +29,20 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3036-sdk.dtb \ + rk3288-evb.dtb \ + rk3288-fennec.dtb \ rk3288-firefly.dtb \ + rk3288-miqi.dtb \ + rk3288-popmetal.dtb \ + rk3188-radxarock.dtb \ + rk3288-rock2-square.dtb \ + rk3288-tinker.dtb \ rk3288-veyron-jerry.dtb \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ - rk3288-rock2-square.dtb \ - rk3288-evb.dtb \ - rk3288-fennec.dtb \ - rk3288-tinker.dtb \ - rk3288-popmetal.dtb \ rk3328-evb.dtb \ - rk3399-evb.dtb + rk3399-evb.dtb \ + rk3399-puma.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-odroidc2.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ diff --git a/arch/arm/dts/rk3188-radxarock.dts b/arch/arm/dts/rk3188-radxarock.dts new file mode 100644 index 0000000..5f5b5e9 --- /dev/null +++ b/arch/arm/dts/rk3188-radxarock.dts @@ -0,0 +1,382 @@ +/* + * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include "rk3188.dtsi" + +/ { + model = "Radxa Rock"; + compatible = "radxa,rock", "rockchip,rk3188"; + + chosen { +/* stdout-path = &uart2; */ + stdout-path = "serial2:115200n8"; + }; + + config { + u-boot,dm-pre-reloc; + u-boot,boot-led = "rock:red:power"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + power { + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + label = "GPIO Key Power"; + linux,input-type = <1>; + wakeup-source; + debounce-interval = <100>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + green { + label = "rock:green:user1"; + gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + blue { + label = "rock:blue:user2"; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + sleep { + label = "rock:red:power"; + gpios = <&gpio0 15 0>; + default-state = "off"; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ + cpu { sound-dai = <&spdif>; }; + codec { sound-dai = <&spdif_out>; }; + }; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + ir_recv: gpio-ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 10 1>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_recv_pin>; + }; + + vcc_otg: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sd0: sdmmc-regulator { + compatible = "regulator-fixed"; + regulator-name = "sdmmc-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 1 GPIO_ACTIVE_LOW>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_host: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "host-pwr"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vsys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&dmc { + rockchip,pctl-timing = <0x12c 0xc8 0x1f4 0x1e 0x4e 0x4 0x69 0x6 + 0x3 0x0 0x6 0x5 0xc 0x10 0x6 0x4 + 0x4 0x5 0x4 0x200 0x3 0xa 0x40 0x0 + 0x1 0x5 0x5 0x3 0xc 0x1e 0x100 0x0 + 0x4 0x0>; + rockchip,phy-timing = <0x208c6690 0x690878 0x10022a00 + 0x220 0x40 0x0 0x0>; + rockchip,sdram-params = <0x24716310 0 2 300000000 3 9 0>; +}; + +&emac { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; + + phy = <&phy0>; + phy-supply = <&vcc_rmii>; + + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_arm>; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + status = "okay"; + system-power-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&act8846_dvs0_ctl>; + + vp1-supply = <&vsys>; + vp2-supply = <&vsys>; + vp3-supply = <&vsys>; + vp4-supply = <&vsys>; + inl1-supply = <&vcc_io>; + inl2-supply = <&vsys>; + inl3-supply = <&vsys>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vdd_log: REG2 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vdd_arm: REG3 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vcc_io: REG4 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_10: REG5 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vdd_hdmi: REG6 { + regulator-name = "VDD_HDMI"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + vcc18: REG7 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcca_33: REG8 { + regulator-name = "VCCA_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_rmii: REG9 { + regulator-name = "VCC_RMII"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccio_wl: REG10 { + regulator-name = "VCCIO_WL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "VCC18_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc28: REG12 { + regulator-name = "VCC_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + }; + }; +}; + +&mmc0 { + num-slots = <1>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; + vmmc-supply = <&vcc_sd0>; + + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pinctrl { + pcfg_output_low: pcfg-output-low { + output-low; + }; + + act8846 { + act8846_dvs0_ctl: act8846-dvs0-ctl { + rockchip,pins = <RK_GPIO3 27 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lan8720a { + phy_int: phy-int { + rockchip,pins = <RK_GPIO3 26 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + ir-receiver { + ir_recv_pin: ir-recv-pin { + rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&spdif { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + u-boot,dm-spl; +}; + +&uart3 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts index 97568a3..59ff8bc 100644 --- a/arch/arm/dts/rk3288-firefly.dts +++ b/arch/arm/dts/rk3288-firefly.dts @@ -50,6 +50,11 @@ rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + usb_host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pwm1 { @@ -61,6 +66,11 @@ reg-shift = <2>; }; +&usb_host1 { + vbus-supply = <&vcc_host_5v>; + status = "okay"; +}; + &sdmmc { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/rk3288-miqi.dts b/arch/arm/dts/rk3288-miqi.dts new file mode 100644 index 0000000..7b92caf --- /dev/null +++ b/arch/arm/dts/rk3288-miqi.dts @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +#include "rk3288-miqi.dtsi" + +/ { + model = "mqmaker MiQi"; + compatible = "mqmaker,miqi", "rockchip,rk3288"; + + chosen { + stdout-path = "serial2:115200n8"; + }; +}; + +&dmc { + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; + + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; + reg-shift = <2>; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-miqi.dtsi b/arch/arm/dts/rk3288-miqi.dtsi new file mode 100644 index 0000000..47dc0f9 --- /dev/null +++ b/arch/arm/dts/rk3288-miqi.dtsi @@ -0,0 +1,423 @@ +/* + * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de> + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +#include "rk3288.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + io_domains: io-domains { + compatible = "rockchip,rk3288-io-voltage-domain"; + rockchip,grf = <&grf>; + + audio-supply = <&vcca_33>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_18>; + }; + + + leds { + u-boot,dm-pre-reloc; + compatible = "gpio-leds"; + + work { + u-boot,dm-pre-reloc; + gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; + label = "miqi:green:user"; + linux,default-trigger = "default-on"; + pinctrl-names = "default"; + pinctrl-0 = <&led_ctl>; + }; + }; + + vcc_flash: flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_host: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_flash>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + fcs,suspend-voltage-selector = <1>; + reg = <0x40>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <300>; + regulator-ramp-delay = <8000>; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + fcs,suspend-voltage-selector = <1>; + reg = <0x41>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_vsel>; + system-power-controller; + + vp1-supply = <&vcc_sys>; + vp2-supply = <&vcc_sys>; + vp3-supply = <&vcc_sys>; + vp4-supply = <&vcc_sys>; + inl1-supply = <&vcc_sys>; + inl2-supply = <&vcc_sys>; + inl3-supply = <&vcc_20>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "vcc_ddr"; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "vcc_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd10_lcd: REG6 { + regulator-name = "vdd10_lcd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcca_18: REG7 { + regulator-name = "vcca_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcca_33: REG8 { + regulator-name = "vcca_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_lan: REG9 { + regulator-name = "vcc_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_10: REG10 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc18_lcd: REG12 { + regulator-name = "vcc18_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + act8846 { + pmic_int: pmic-int { + rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pmic_sleep: pmic-sleep { + rockchip,pins = <0 0 RK_FUNC_GPIO &pcfg_output_low>; + }; + + pmic_vsel: pmic-vsel { + rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { + rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + leds { + led_ctl: led-ctl { + rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on firefly board so bump up to 12ma. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host1 { + vbus-supply = <&vcc_host>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index a959989..c3a7ca2 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -95,6 +95,7 @@ }; &dwc3_typec0 { + rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -107,6 +108,7 @@ }; &dwc3_typec1 { + rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/dts/rk3399-puma.dts b/arch/arm/dts/rk3399-puma.dts new file mode 100644 index 0000000..917df1e --- /dev/null +++ b/arch/arm/dts/rk3399-puma.dts @@ -0,0 +1,189 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include <dt-bindings/pwm/pwm.h> +#include "rk3399.dtsi" +#include "rk3399-sdram-ddr3-1333.dtsi" + +/ { + model = "Theobroma Systems RK3399-Q7 SoM"; + compatible = "tsd,puma", "rockchip,rk3399"; + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &spiflash, &sdhci, &sdmmc; + }; + + aliases { + spi0 = &spi1; + spi1 = &spi5; + }; + + vdd_center: vdd-center { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 25000 0>; + regulator-name = "vdd_center"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-init-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + status = "okay"; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_host: vcc5v0-host-en { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + bus-width = <4>; + fifo-mode; /* until we fix DMA in SPL */ + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&dwc3_typec0 { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&dwc3_typec1 { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pmic_dvs2: pmic-dvs2 { + rockchip,pins = + <1 18 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 16 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x10>; + rx_delay = <0x10>; + status = "okay"; +}; + +&spi1 { + u-boot,dm-pre-reloc; + + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + spiflash: w25q32dw@0 { + u-boot,dm-pre-reloc; + + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <5000000>; + spi-cpol; + spi-cpha; + }; +}; + +&spi5 { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi new file mode 100644 index 0000000..bed236d --- /dev/null +++ b/arch/arm/dts/rk3399-sdram-ddr3-1333.dtsi @@ -0,0 +1,1537 @@ +/* + * (C) 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xa + 0x3 + 0x2 + 0x1 + 0x0 + 0xf + 0xf + 1 + 0x80120e12 + 0x11030802 + 0x00000002 + 0x00006246 + 0x0000004c + 0x00000000 + 0x1 + 0xa + 0x3 + 0x2 + 0x1 + 0x0 + 0xf + 0xf + 1 + 0x80120e12 + 0x11030802 + 0x00000002 + 0x00006246 + 0x0000004c + 0x00000000 + 666 + 3 + 2 +/* 13 */ 9 + 1 + 0x00000600 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 +/* 0xaae60 */ 7 + 0x00000000 + 0x00000000 + 0x00000000 +/* 0xaae60 */ 7 + 0x00000000 + 0x00000000 + 0x00000000 +/* 0xaae60 */ 7 + 0x00000000 + 0x00000000 + 0x01000000 + 0x00000000 + 0x00000101 + 0x00020100 + 0x000208d6 + 0x00051616 + 0x02000200 + 0x07140200 + 0x00071400 + 0x04000714 + 0x20040004 + 0x18090517 + 0x17200400 + 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diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 456fdb6..dbe55f2 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -239,7 +239,6 @@ compatible = "rockchip,rk3399-xhci"; reg = <0x0 0xfe800000 0x0 0x100000>; status = "disabled"; - rockchip,vbus-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>; snps,dis-enblslpm-quirk; snps,phyif-utmi-bits = <16>; snps,dis-u2-freeclk-exists-quirk; @@ -261,7 +260,6 @@ compatible = "rockchip,rk3399-xhci"; reg = <0x0 0xfe900000 0x0 0x100000>; status = "disabled"; - rockchip,vbus-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; snps,dis-enblslpm-quirk; snps,phyif-utmi-bits = <16>; snps,dis-u2-freeclk-exists-quirk; @@ -600,6 +598,25 @@ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; }; + gmac: eth@fe300000 { + compatible = "rockchip,rk3399-gmac"; + reg = <0x0 0xfe300000 0x0 0x10000>; + rockchip,grf = <&grf>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, + <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, + <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac"; + resets = <&cru SRST_A_GMAC>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + spdif: spdif@ff870000 { compatible = "rockchip,rk3399-spdif"; reg = <0x0 0xff870000 0x0 0x1000>; @@ -865,6 +882,42 @@ }; }; + gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = + /* mac_txclk */ + <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_rxclk */ + <3 14 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdio */ + <3 13 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txen */ + <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_clk */ + <3 11 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxdv */ + <3 9 RK_FUNC_1 &pcfg_pull_none>, + /* mac_mdc */ + <3 8 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd1 */ + <3 7 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd0 */ + <3 6 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd1 */ + <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_txd0 */ + <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_rxd3 */ + <3 3 RK_FUNC_1 &pcfg_pull_none>, + /* mac_rxd2 */ + <3 2 RK_FUNC_1 &pcfg_pull_none>, + /* mac_txd3 */ + <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>, + /* mac_txd2 */ + <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>; + }; + }; + sdmmc { sdmmc_bus1: sdmmc-bus1 { rockchip,pins = diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h new file mode 100644 index 0000000..8d7bc9a --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/boot0.h @@ -0,0 +1,18 @@ +/* + * Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Execution starts on the instruction following this 4-byte header + * (containing the magic 'RK33'). + * + * To make life easier for everyone, we build the SPL binary with + * space for this 4-byte header already included in the binary. + */ + +#ifdef CONFIG_SPL_BUILD + .space 0x4 /* space for the 'RK33' */ +#endif + b reset diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h index 74f0fed..f5d6420 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h @@ -9,6 +9,7 @@ #define OSC_HZ (24 * 1000 * 1000) #define APLL_HZ (1608 * 1000000) +#define APLL_SAFE_HZ (600 * 1000000) #define GPLL_HZ (594 * 1000000) #define CPLL_HZ (384 * 1000000) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index aaffd19..1a7c819 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -720,20 +720,20 @@ enum { /* GRF_SOC_CON1 */ enum { - RMII_MODE_SHIFT = 0xe, - RMII_MODE_MASK = 1, - RMII_MODE = 1, + RK3288_RMII_MODE_SHIFT = 14, + RK3288_RMII_MODE_MASK = (1 << RK3288_RMII_MODE_SHIFT), + RK3288_RMII_MODE = (1 << RK3288_RMII_MODE_SHIFT), - GMAC_CLK_SEL_SHIFT = 0xc, - GMAC_CLK_SEL_MASK = 3, - GMAC_CLK_SEL_125M = 0, - GMAC_CLK_SEL_25M = 0x3, - GMAC_CLK_SEL_2_5M = 0x2, + RK3288_GMAC_CLK_SEL_SHIFT = 12, + RK3288_GMAC_CLK_SEL_MASK = (3 << RK3288_GMAC_CLK_SEL_SHIFT), + RK3288_GMAC_CLK_SEL_125M = (0 << RK3288_GMAC_CLK_SEL_SHIFT), + RK3288_GMAC_CLK_SEL_25M = (3 << RK3288_GMAC_CLK_SEL_SHIFT), + RK3288_GMAC_CLK_SEL_2_5M = (2 << RK3288_GMAC_CLK_SEL_SHIFT), - RMII_CLK_SEL_SHIFT = 0xb, - RMII_CLK_SEL_MASK = 1, - RMII_CLK_SEL_2_5M = 0, - RMII_CLK_SEL_25M, + RK3288_RMII_CLK_SEL_SHIFT = 11, + RK3288_RMII_CLK_SEL_MASK = (1 << RK3288_RMII_CLK_SEL_SHIFT), + RK3288_RMII_CLK_SEL_2_5M = (0 << RK3288_RMII_CLK_SEL_SHIFT), + RK3288_RMII_CLK_SEL_25M = (1 << RK3288_RMII_CLK_SEL_SHIFT), GMAC_SPEED_SHIFT = 0xa, GMAC_SPEED_MASK = 1, @@ -743,10 +743,10 @@ enum { GMAC_FLOWCTRL_SHIFT = 0x9, GMAC_FLOWCTRL_MASK = 1, - GMAC_PHY_INTF_SEL_SHIFT = 0x6, - GMAC_PHY_INTF_SEL_MASK = 0x7, - GMAC_PHY_INTF_SEL_RGMII = 0x1, - GMAC_PHY_INTF_SEL_RMII = 0x4, + RK3288_GMAC_PHY_INTF_SEL_SHIFT = 6, + RK3288_GMAC_PHY_INTF_SEL_MASK = (7 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), + RK3288_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), + RK3288_GMAC_PHY_INTF_SEL_RMII = (4 << RK3288_GMAC_PHY_INTF_SEL_SHIFT), HOST_REMAP_SHIFT = 0x5, HOST_REMAP_MASK = 1 @@ -801,21 +801,27 @@ enum { /* GRF_SOC_CON3 */ enum { - RXCLK_DLY_ENA_GMAC_SHIFT = 0xf, - RXCLK_DLY_ENA_GMAC_MASK = 1, - RXCLK_DLY_ENA_GMAC_DISABLE = 0, - RXCLK_DLY_ENA_GMAC_ENABLE, - - TXCLK_DLY_ENA_GMAC_SHIFT = 0xe, - TXCLK_DLY_ENA_GMAC_MASK = 1, - TXCLK_DLY_ENA_GMAC_DISABLE = 0, - TXCLK_DLY_ENA_GMAC_ENABLE, - - CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, - CLK_RX_DL_CFG_GMAC_MASK = 0x7f, - - CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, - CLK_TX_DL_CFG_GMAC_MASK = 0x7f, + RK3288_RXCLK_DLY_ENA_GMAC_SHIFT = 0xf, + RK3288_RXCLK_DLY_ENA_GMAC_MASK = + (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), + RK3288_RXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3288_RXCLK_DLY_ENA_GMAC_ENABLE = + (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), + + RK3288_TXCLK_DLY_ENA_GMAC_SHIFT = 0xe, + RK3288_TXCLK_DLY_ENA_GMAC_MASK = + (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), + RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3288_TXCLK_DLY_ENA_GMAC_ENABLE = + (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), + + RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, + RK3288_CLK_RX_DL_CFG_GMAC_MASK = + (0x7f << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT), + + RK3288_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0, + RK3288_CLK_TX_DL_CFG_GMAC_MASK = + (0x7f << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT), }; #endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index 62d8496..b340b05 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -144,7 +144,9 @@ struct rk3399_grf_regs { }; u32 gpio4d_iomux; u32 reserved21[4]; - u32 gpio2_p[3][4]; + u32 gpio2_p[4]; + u32 gpio3_p[4]; + u32 gpio4_p[4]; u32 reserved22[4]; u32 gpio2_sr[3][4]; u32 reserved23[4]; @@ -215,7 +217,9 @@ struct rk3399_pmugrf_regs { }; u32 gpio1d_iomux; u32 reserved1[8]; - u32 gpio0_p[2][4]; + u32 gpio0_p[2]; + u32 reserved2[2]; + u32 gpio1_p[4]; u32 reserved3[8]; u32 gpio0a_e; u32 reserved4; @@ -334,23 +338,60 @@ enum { GRF_SPI2TPM_CSN0 = 1, /* GRF_GPIO3A_IOMUX */ + GRF_GPIO3A0_SEL_SHIFT = 0, + GRF_GPIO3A0_SEL_MASK = 3 << GRF_GPIO3A0_SEL_SHIFT, + GRF_MAC_TXD2 = 1, + GRF_GPIO3A1_SEL_SHIFT = 2, + GRF_GPIO3A1_SEL_MASK = 3 << GRF_GPIO3A1_SEL_SHIFT, + GRF_MAC_TXD3 = 1, + GRF_GPIO3A2_SEL_SHIFT = 4, + GRF_GPIO3A2_SEL_MASK = 3 << GRF_GPIO3A2_SEL_SHIFT, + GRF_MAC_RXD2 = 1, + GRF_GPIO3A3_SEL_SHIFT = 6, + GRF_GPIO3A3_SEL_MASK = 3 << GRF_GPIO3A3_SEL_SHIFT, + GRF_MAC_RXD3 = 1, GRF_GPIO3A4_SEL_SHIFT = 8, GRF_GPIO3A4_SEL_MASK = 3 << GRF_GPIO3A4_SEL_SHIFT, + GRF_MAC_TXD0 = 1, GRF_SPI0NORCODEC_RXD = 2, GRF_GPIO3A5_SEL_SHIFT = 10, GRF_GPIO3A5_SEL_MASK = 3 << GRF_GPIO3A5_SEL_SHIFT, + GRF_MAC_TXD1 = 1, GRF_SPI0NORCODEC_TXD = 2, GRF_GPIO3A6_SEL_SHIFT = 12, GRF_GPIO3A6_SEL_MASK = 3 << GRF_GPIO3A6_SEL_SHIFT, + GRF_MAC_RXD0 = 1, GRF_SPI0NORCODEC_CLK = 2, GRF_GPIO3A7_SEL_SHIFT = 14, GRF_GPIO3A7_SEL_MASK = 3 << GRF_GPIO3A7_SEL_SHIFT, + GRF_MAC_RXD1 = 1, GRF_SPI0NORCODEC_CSN0 = 2, /* GRF_GPIO3B_IOMUX */ GRF_GPIO3B0_SEL_SHIFT = 0, GRF_GPIO3B0_SEL_MASK = 3 << GRF_GPIO3B0_SEL_SHIFT, + GRF_MAC_MDC = 1, GRF_SPI0NORCODEC_CSN1 = 2, + GRF_GPIO3B1_SEL_SHIFT = 2, + GRF_GPIO3B1_SEL_MASK = 3 << GRF_GPIO3B1_SEL_SHIFT, + GRF_MAC_RXDV = 1, + GRF_GPIO3B3_SEL_SHIFT = 6, + GRF_GPIO3B3_SEL_MASK = 3 << GRF_GPIO3B3_SEL_SHIFT, + GRF_MAC_CLK = 1, + GRF_GPIO3B4_SEL_SHIFT = 8, + GRF_GPIO3B4_SEL_MASK = 3 << GRF_GPIO3B4_SEL_SHIFT, + GRF_MAC_TXEN = 1, + GRF_GPIO3B5_SEL_SHIFT = 10, + GRF_GPIO3B5_SEL_MASK = 3 << GRF_GPIO3B5_SEL_SHIFT, + GRF_MAC_MDIO = 1, + GRF_GPIO3B6_SEL_SHIFT = 12, + GRF_GPIO3B6_SEL_MASK = 3 << GRF_GPIO3B6_SEL_SHIFT, + GRF_MAC_RXCLK = 1, + + /* GRF_GPIO3C_IOMUX */ + GRF_GPIO3C1_SEL_SHIFT = 2, + GRF_GPIO3C1_SEL_MASK = 3 << GRF_GPIO3C1_SEL_SHIFT, + GRF_MAC_TXCLK = 1, /* GRF_GPIO4B_IOMUX */ GRF_GPIO4B0_SEL_SHIFT = 0, @@ -436,4 +477,43 @@ enum { }; +/* GRF_SOC_CON5 */ +enum { + RK3399_GMAC_PHY_INTF_SEL_SHIFT = 9, + RK3399_GMAC_PHY_INTF_SEL_MASK = (7 << RK3399_GMAC_PHY_INTF_SEL_SHIFT), + RK3399_GMAC_PHY_INTF_SEL_RGMII = (1 << RK3399_GMAC_PHY_INTF_SEL_SHIFT), + RK3399_GMAC_PHY_INTF_SEL_RMII = (4 << RK3399_GMAC_PHY_INTF_SEL_SHIFT), + + RK3399_GMAC_CLK_SEL_SHIFT = 4, + RK3399_GMAC_CLK_SEL_MASK = (3 << RK3399_GMAC_CLK_SEL_SHIFT), + RK3399_GMAC_CLK_SEL_125M = (0 << RK3399_GMAC_CLK_SEL_SHIFT), + RK3399_GMAC_CLK_SEL_25M = (3 << RK3399_GMAC_CLK_SEL_SHIFT), + RK3399_GMAC_CLK_SEL_2_5M = (2 << RK3399_GMAC_CLK_SEL_SHIFT), +}; + +/* GRF_SOC_CON6 */ +enum { + RK3399_RXCLK_DLY_ENA_GMAC_SHIFT = 15, + RK3399_RXCLK_DLY_ENA_GMAC_MASK = + (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT), + RK3399_RXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3399_RXCLK_DLY_ENA_GMAC_ENABLE = + (1 << RK3399_RXCLK_DLY_ENA_GMAC_SHIFT), + + RK3399_TXCLK_DLY_ENA_GMAC_SHIFT = 7, + RK3399_TXCLK_DLY_ENA_GMAC_MASK = + (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT), + RK3399_TXCLK_DLY_ENA_GMAC_DISABLE = 0, + RK3399_TXCLK_DLY_ENA_GMAC_ENABLE = + (1 << RK3399_TXCLK_DLY_ENA_GMAC_SHIFT), + + RK3399_CLK_RX_DL_CFG_GMAC_SHIFT = 8, + RK3399_CLK_RX_DL_CFG_GMAC_MASK = + (0x7f << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT), + + RK3399_CLK_TX_DL_CFG_GMAC_SHIFT = 0, + RK3399_CLK_TX_DL_CFG_GMAC_MASK = + (0x7f << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT), +}; + #endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h b/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h deleted file mode 100644 index 0b51d40..0000000 --- a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h +++ /dev/null @@ -1,456 +0,0 @@ -/* - * Copyright (c) 2015 Google, Inc - * Copyright 2014 Rockchip Inc. - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_HDMI_H -#define _ASM_ARCH_HDMI_H - - -#define HDMI_EDID_BLOCK_SIZE 128 - -struct rk3288_hdmi { - u32 reserved0[0x100]; - u32 ih_fc_stat0; - u32 ih_fc_stat1; - u32 ih_fc_stat2; - u32 ih_as_stat0; - u32 ih_phy_stat0; - u32 ih_i2cm_stat0; - u32 ih_cec_stat0; - u32 ih_vp_stat0; - u32 ih_i2cmphy_stat0; - u32 ih_ahbdmaaud_stat0; - u32 reserved1[0x17f-0x109]; - u32 ih_mute_fc_stat0; - u32 ih_mute_fc_stat1; - u32 ih_mute_fc_stat2; - u32 ih_mute_as_stat0; - u32 ih_mute_phy_stat0; - u32 ih_mute_i2cm_stat0; - u32 ih_mute_cec_stat0; - u32 ih_mute_vp_stat0; - u32 ih_mute_i2cmphy_stat0; - u32 ih_mute_ahbdmaaud_stat0; - u32 reserved2[0x1fe - 0x189]; - u32 ih_mute; - u32 tx_invid0; - u32 tx_instuffing; - u32 tx_gydata0; - u32 tx_gydata1; - u32 tx_rcrdata0; - u32 tx_rcrdata1; - u32 tx_bcbdata0; - u32 tx_bcbdata1; - u32 reserved3[0x7ff-0x207]; - u32 vp_status; - u32 vp_pr_cd; - u32 vp_stuff; - u32 vp_remap; - u32 vp_conf; - u32 vp_stat; - u32 vp_int; - u32 vp_mask; - u32 vp_pol; - u32 reserved4[0xfff-0x808]; - u32 fc_invidconf; - u32 fc_inhactv0; - u32 fc_inhactv1; - u32 fc_inhblank0; - u32 fc_inhblank1; - u32 fc_invactv0; - u32 fc_invactv1; - u32 fc_invblank; - u32 fc_hsyncindelay0; - u32 fc_hsyncindelay1; - u32 fc_hsyncinwidth0; - u32 fc_hsyncinwidth1; - u32 fc_vsyncindelay; - u32 fc_vsyncinwidth; - u32 fc_infreq0; - u32 fc_infreq1; - u32 fc_infreq2; - u32 fc_ctrldur; - u32 fc_exctrldur; - u32 fc_exctrlspac; - u32 fc_ch0pream; - u32 fc_ch1pream; - u32 fc_ch2pream; - u32 fc_aviconf3; - u32 fc_gcp; - u32 fc_aviconf0; - u32 fc_aviconf1; - u32 fc_aviconf2; - u32 fc_avivid; - u32 fc_avietb0; - u32 fc_avietb1; - u32 fc_avisbb0; - u32 fc_avisbb1; - u32 fc_avielb0; - u32 fc_avielb1; - u32 fc_avisrb0; - u32 fc_avisrb1; - u32 fc_audiconf0; - u32 fc_audiconf1; - u32 fc_audiconf2; - u32 fc_audiconf3; - u32 fc_vsdieeeid0; - u32 fc_vsdsize; - u32 reserved7[0x2fff-0x102a]; - u32 phy_conf0; - u32 phy_tst0; - u32 phy_tst1; - u32 phy_tst2; - u32 phy_stat0; - u32 phy_int0; - u32 phy_mask0; - u32 phy_pol0; - u32 reserved8[0x301f-0x3007]; - u32 phy_i2cm_slave_addr; - u32 phy_i2cm_address_addr; - u32 phy_i2cm_datao_1_addr; - u32 phy_i2cm_datao_0_addr; - u32 phy_i2cm_datai_1_addr; - u32 phy_i2cm_datai_0_addr; - u32 phy_i2cm_operation_addr; - u32 phy_i2cm_int_addr; - u32 phy_i2cm_ctlint_addr; - u32 phy_i2cm_div_addr; - u32 phy_i2cm_softrstz_addr; - u32 phy_i2cm_ss_scl_hcnt_1_addr; - u32 phy_i2cm_ss_scl_hcnt_0_addr; - u32 phy_i2cm_ss_scl_lcnt_1_addr; - u32 phy_i2cm_ss_scl_lcnt_0_addr; - u32 phy_i2cm_fs_scl_hcnt_1_addr; - u32 phy_i2cm_fs_scl_hcnt_0_addr; - u32 phy_i2cm_fs_scl_lcnt_1_addr; - u32 phy_i2cm_fs_scl_lcnt_0_addr; - u32 reserved9[0x30ff-0x3032]; - u32 aud_conf0; - u32 aud_conf1; - u32 aud_int; - u32 aud_conf2; - u32 aud_int1; - u32 reserved32[0x31ff-0x3104]; - u32 aud_n1; - u32 aud_n2; - u32 aud_n3; - u32 aud_cts1; - u32 aud_cts2; - u32 aud_cts3; - u32 aud_inputclkfs; - u32 reserved12[0x3fff-0x3206]; - u32 mc_sfrdiv; - u32 mc_clkdis; - u32 mc_swrstz; - u32 mc_opctrl; - u32 mc_flowctrl; - u32 mc_phyrstz; - u32 mc_lockonclock; - u32 mc_heacphy_rst; - u32 reserved13[0x40ff-0x4007]; - u32 csc_cfg; - u32 csc_scale; - struct { - u32 msb; - u32 lsb; - } csc_coef[3][4]; - u32 reserved17[0x7dff-0x4119]; - u32 i2cm_slave; - u32 i2c_address; - u32 i2cm_datao; - u32 i2cm_datai; - u32 i2cm_operation; - u32 i2cm_int; - u32 i2cm_ctlint; - u32 i2cm_div; - u32 i2cm_segaddr; - u32 i2cm_softrstz; - u32 i2cm_segptr; - u32 i2cm_ss_scl_hcnt_1_addr; - u32 i2cm_ss_scl_hcnt_0_addr; - u32 i2cm_ss_scl_lcnt_1_addr; - u32 i2cm_ss_scl_lcnt_0_addr; - u32 i2cm_fs_scl_hcnt_1_addr; - u32 i2cm_fs_scl_hcnt_0_addr; - u32 i2cm_fs_scl_lcnt_1_addr; - u32 i2cm_fs_scl_lcnt_0_addr; - u32 reserved18[0x7e1f-0x7e12]; - u32 i2cm_buf0; -}; -check_member(rk3288_hdmi, i2cm_buf0, 0x1f880); - -enum { - /* HDMI PHY registers define */ - PHY_OPMODE_PLLCFG = 0x06, - PHY_CKCALCTRL = 0x05, - PHY_CKSYMTXCTRL = 0x09, - PHY_VLEVCTRL = 0x0e, - PHY_PLLCURRCTRL = 0x10, - PHY_PLLPHBYCTRL = 0x13, - PHY_PLLGMPCTRL = 0x15, - PHY_PLLCLKBISTPHASE = 0x17, - PHY_TXTERM = 0x19, - - /* ih_phy_stat0 field values */ - HDMI_IH_PHY_STAT0_HPD = 0x1, - - /* ih_mute field values */ - HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, - HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, - - /* tx_invid0 field values */ - HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, - HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f, - HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, - - /* tx_instuffing field values */ - HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, - HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, - HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, - - /* vp_pr_cd field values */ - HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0, - HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f, - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, - - /* vp_stuff field values */ - HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, - HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, - HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, - HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, - HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, - HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, - HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, - HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, - - /* vp_conf field values */ - HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, - HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, - HDMI_VP_CONF_PP_EN_ENMASK = 0x20, - HDMI_VP_CONF_PP_EN_DISABLE = 0x00, - HDMI_VP_CONF_PR_EN_MASK = 0x10, - HDMI_VP_CONF_PR_EN_DISABLE = 0x00, - HDMI_VP_CONF_YCC422_EN_MASK = 0x8, - HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, - HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, - HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, - HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, - HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, - - /* vp_remap field values */ - HDMI_VP_REMAP_YCC422_16BIT = 0x0, - - /* fc_invidconf field values */ - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, - HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, - HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, - HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, - HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, - HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, - HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, - HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, - HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, - HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, - - - /* fc_aviconf0-fc_aviconf3 field values */ - HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, - HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, - HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, - HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, - HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, - HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, - HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, - HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c, - HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, - HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, - HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, - HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c, - HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, - HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, - HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, - HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, - - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a, - HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, - HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, - HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0, - HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, - HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, - HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, - HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0, - - HDMI_FC_AVICONF2_SCALING_MASK = 0x03, - HDMI_FC_AVICONF2_SCALING_NONE = 0x00, - HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, - HDMI_FC_AVICONF2_SCALING_VERT = 0x02, - HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03, - HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c, - HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, - HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, - HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, - HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, - HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, - HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, - HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, - - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, - HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, - HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c, - HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, - HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, - - /* fc_gcp field values*/ - HDMI_FC_GCP_SET_AVMUTE = 0x02, - HDMI_FC_GCP_CLEAR_AVMUTE = 0x01, - - /* phy_conf0 field values */ - HDMI_PHY_CONF0_PDZ_MASK = 0x80, - HDMI_PHY_CONF0_PDZ_OFFSET = 7, - HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, - HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, - HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20, - HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5, - HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, - HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, - HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, - HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, - HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, - HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, - HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, - HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, - - /* phy_tst0 field values */ - HDMI_PHY_TST0_TSTCLR_MASK = 0x20, - HDMI_PHY_TST0_TSTCLR_OFFSET = 5, - - /* phy_stat0 field values */ - HDMI_PHY_HPD = 0x02, - HDMI_PHY_TX_PHY_LOCK = 0x01, - - /* phy_i2cm_slave_addr field values */ - HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, - - /* phy_i2cm_operation_addr field values */ - HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, - - /* hdmi_phy_i2cm_int_addr */ - HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, - - /* hdmi_phy_i2cm_ctlint_addr */ - HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, - HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, - - /* aud_conf0 field values */ - HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80, - HDMI_AUD_CONF0_I2S_SELECT = 0x20, - HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01, - HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02, - HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04, - HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08, - - /* aud_conf0 field values */ - HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0, - HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10, - - /* aud_n3 field values */ - HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80, - HDMI_AUD_N3_AUDN19_16_MASK = 0x0f, - - /* aud_cts3 field values */ - HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, - HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, - HDMI_AUD_CTS3_N_SHIFT_1 = 0, - HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, - HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, - HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, - HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, - HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, - HDMI_AUD_CTS3_CTS_MANUAL = 0x10, - HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, - - /* aud_inputclkfs filed values */ - HDMI_AUD_INPUTCLKFS_128 = 0x0, - - /* mc_clkdis field values */ - HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, - HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, - HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, - - /* mc_swrstz field values */ - HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08, - HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, - - /* mc_flowctrl field values */ - HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, - HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, - - /* mc_phyrstz field values */ - HDMI_MC_PHYRSTZ_ASSERT = 0x0, - HDMI_MC_PHYRSTZ_DEASSERT = 0x1, - - /* mc_heacphy_rst field values */ - HDMI_MC_HEACPHY_RST_ASSERT = 0x1, - - /* csc_cfg field values */ - HDMI_CSC_CFG_INTMODE_DISABLE = 0x00, - - /* csc_scale field values */ - HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xf0, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60, - HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70, - HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03, - - /* i2cm filed values */ - HDMI_I2CM_SLAVE_DDC_ADDR = 0x50, - HDMI_I2CM_SEGADDR_DDC = 0x30, - HDMI_I2CM_OPT_RD8_EXT = 0x8, - HDMI_I2CM_OPT_RD8 = 0x4, - HDMI_I2CM_DIV_FAST_STD_MODE = 0x8, - HDMI_I2CM_DIV_FAST_MODE = 0x8, - HDMI_I2CM_DIV_STD_MODE = 0x0, - HDMI_I2CM_SOFTRSTZ = 0x1, -}; - -/* -struct display_timing; -struct rk3288_grf; - -int rk_hdmi_init(struct rk3288_grf *grf, u32 vop_id); -int rk_hdmi_enable(const struct display_timing *edid); -int rk_hdmi_get_edid(struct rk3288_grf *grf, struct display_timing *edid); -*/ - -#endif diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h index fa6069b..239a274 100644 --- a/arch/arm/include/asm/arch-rockchip/periph.h +++ b/arch/arm/include/asm/arch-rockchip/periph.h @@ -38,6 +38,7 @@ enum periph_id { PERIPH_ID_SDMMC1, PERIPH_ID_SDMMC2, PERIPH_ID_HDMI, + PERIPH_ID_GMAC, PERIPH_ID_COUNT, diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index bf8e6be..af0796d 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -54,6 +54,7 @@ config ROCKCHIP_RK3399 select SUPPORT_SPL select SPL select SPL_SEPARATE_BSS + select ENABLE_ARM_SOC_BOOT0_HOOK help The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 and quad-core Cortex-A53. diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index f93feae..c3e174d 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <clk.h> #include <common.h> #include <debug_uart.h> #include <dm.h> @@ -76,6 +77,27 @@ u32 spl_boot_mode(const u32 boot_device) return MMCSD_MODE_RAW; } +static int setup_arm_clock(void) +{ + struct udevice *dev; + struct clk clk; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ret; + + clk.id = CLK_ARM; + ret = clk_request(dev, &clk); + if (ret < 0) + return ret; + + ret = clk_set_rate(&clk, 600000000); + + clk_free(&clk); + return ret; +} + void board_init_f(ulong dummy) { struct udevice *pinctrl, *dev; @@ -109,9 +131,9 @@ void board_init_f(ulong dummy) printch('\n'); #endif - ret = spl_init(); + ret = spl_early_init(); if (ret) { - debug("spl_init() failed: %d\n", ret); + debug("spl_early_init() failed: %d\n", ret); hang(); } @@ -144,6 +166,8 @@ void board_init_f(ulong dummy) return; } + setup_arm_clock(); + #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(); #endif diff --git a/arch/arm/mach-rockchip/rk3188-board-tpl.c b/arch/arm/mach-rockchip/rk3188-board-tpl.c index 442bfe7..b458ef6 100644 --- a/arch/arm/mach-rockchip/rk3188-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3188-board-tpl.c @@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR; static int rk3188_num_entries __attribute__ ((section(".data"))); #define PMU_BASE 0x20004000 -#define TPL_ENTRY 0x10080C00 +#define SPL_ENTRY 0x10080C00 static void jump_to_spl(void) { @@ -25,9 +25,9 @@ static void jump_to_spl(void) struct rk3188_pmu * const pmu = (void *)PMU_BASE; image_entry_noargs_t tpl_entry = - (image_entry_noargs_t)(unsigned long)TPL_ENTRY; + (image_entry_noargs_t)(unsigned long)SPL_ENTRY; - /* Store the SAVE_SP_ADDR in a location shared with TPL. */ + /* Store the SAVE_SP_ADDR in a location shared with SPL. */ writel(SAVE_SP_ADDR, &pmu->sys_reg[2]); tpl_entry(); } diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index 16f3855..c370156 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -56,8 +56,22 @@ err: int dram_init(void) { - /* FIXME: read back ram size from sys_reg2 */ - gd->ram_size = 0x40000000; + struct ram_info ram; + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + ret = ram_get_info(dev, &ram); + if (ret) { + debug("Cannot get DRAM size: %d\n", ret); + return ret; + } + debug("SDRAM base=%lx, size=%x\n", ram.base, ram.size); + gd->ram_size = ram.size; return 0; } diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig b/arch/arm/mach-rockchip/rk3188/Kconfig index f8e1d03..d129fcd 100644 --- a/arch/arm/mach-rockchip/rk3188/Kconfig +++ b/arch/arm/mach-rockchip/rk3188/Kconfig @@ -1,5 +1,14 @@ if ROCKCHIP_RK3188 +config TARGET_ROCK + bool "Radxa Rock" + help + Rock is a RK3188-based development board with 2 USB and 1 otg + ports, HDMI, TV-out, micro-SD card, audio, WiFi and 100MBit + Ethernet, It also includes on-board nand and 1GB of SDRAM. + Expansion connectors provide access to display pins, I2C, SPI, + UART and GPIOs. + config SYS_SOC default "rockchip" @@ -18,7 +27,12 @@ config SPL_SERIAL_SUPPORT config TPL_LIBCOMMON_SUPPORT default y +config TPL_LIBGENERIC_SUPPORT + default y + config TPL_SERIAL_SUPPORT default y +source "board/radxa/rock/Kconfig" + endif diff --git a/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c b/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c index 461cfcd..fea8007 100644 --- a/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c +++ b/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c @@ -955,7 +955,7 @@ static int rk3188_dmc_probe(struct udevice *dev) if (ret) return ret; #endif - priv->info.base = 0; + priv->info.base = CONFIG_SYS_SDRAM_BASE; priv->info.size = sdram_size_mb(priv->pmu) << 20; return 0; diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 738a20d..8e7355e 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -1,13 +1,34 @@ if ROCKCHIP_RK3288 -config TARGET_FIREFLY_RK3288 - bool "Firefly-RK3288" +config TARGET_CHROMEBOOK_JERRY + bool "Google/Rockchip Veyron-Jerry Chromebook" select BOARD_LATE_INIT help - Firefly is a RK3288-based development board with 2 USB ports, - HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It - also includes on-board eMMC and 1GB of SDRAM. Expansion connectors - provide access to display pins, I2C, SPI, UART and GPIOs. + Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports, + HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and + WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to + the keyboard and battery functions. + +config TARGET_CHROMEBIT_MICKEY + bool "Google/Rockchip Veyron-Mickey Chromebit" + select BOARD_LATE_INIT + help + Mickey is a small RK3288-based device with one USB 3.0 port, HDMI + and WiFi. It has a separate power port and is designed to connect + to the HDMI input of a monitor or TV. It has no internal battery. + Typically a USB hub or wireless keyboard/touchpad is used to get + keyboard and mouse access. + +config TARGET_CHROMEBOOK_MINNIE + bool "Google/Rockchip Veyron-Minnie Chromebook" + select BOARD_LATE_INIT + help + Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0 + ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card, + HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS + EC (Cortex-M3) to provide access to the keyboard and battery + functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of + internal MMC. The product name is ASUS Chromebook Flip. config TARGET_EVB_RK3288 bool "Evb-RK3288" @@ -27,6 +48,24 @@ config TARGET_FENNEC_RK3288 includes on-board eMMC and 2GB of SDRAM. Expansion connectors provide access to display pins, I2C, SPI, UART and GPIOs. +config TARGET_FIREFLY_RK3288 + bool "Firefly-RK3288" + select BOARD_LATE_INIT + help + Firefly is a RK3288-based development board with 2 USB ports, + HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It + also includes on-board eMMC and 1GB of SDRAM. Expansion connectors + provide access to display pins, I2C, SPI, UART and GPIOs. + +config TARGET_MIQI_RK3288 + bool "MiQi-RK3288" + select BOARD_LATE_INIT + help + MiQi-RK3288 is a RK3288-based development board with 4 USB 2.0 + ports, HDMI, micro-SD card, 16 GB eMMC and Gigabit Ethernet. It + has 1 or 2 GiB SDRAM. Expansion connectors provide access to + I2C, SPI, UART, GPIOs and fan control. + config TARGET_POPMETAL_RK3288 bool "PopMetal-RK3288" select BOARD_LATE_INIT @@ -37,45 +76,6 @@ config TARGET_POPMETAL_RK3288 2GB DDR3. Expansion connectors provide access to I2C, SPI, UART, GPIOs and display interface. -config TARGET_TINKER_RK3288 - bool "Tinker-RK3288" - select BOARD_LATE_INIT - help - Tinker is a RK3288-based development board with 2 USB ports, HDMI, - micro-SD card, audio, Gigabit Ethernet. It also includes on-board - 8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to - I2C, SPI, UART, GPIOs. - -config TARGET_CHROMEBOOK_JERRY - bool "Google/Rockchip Veyron-Jerry Chromebook" - select BOARD_LATE_INIT - help - Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports, - HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and - WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to - the keyboard and battery functions. - -config TARGET_CHROMEBIT_MICKEY - bool "Google/Rockchip Veyron-Mickey Chromebit" - select BOARD_LATE_INIT - help - Mickey is a small RK3288-based device with one USB 3.0 port, HDMI - and WiFi. It has a separate power port and is designed to connect - to the HDMI input of a monitor or TV. It has no internal battery. - Typically a USB hub or wireless keyboard/touchpad is used to get - keyboard and mouse access. - -config TARGET_CHROMEBOOK_MINNIE - bool "Google/Rockchip Veyron-Minnie Chromebook" - select BOARD_LATE_INIT - help - Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0 - ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card, - HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS - EC (Cortex-M3) to provide access to the keyboard and battery - functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of - internal MMC. The product name is ASUS Chromebook Flip. - config TARGET_ROCK2 bool "Radxa Rock 2" select BOARD_LATE_INIT @@ -85,6 +85,15 @@ config TARGET_ROCK2 space for a real-time-clock battery. There is also an expansion interface which provides access to many pins. +config TARGET_TINKER_RK3288 + bool "Tinker-RK3288" + select BOARD_LATE_INIT + help + Tinker is a RK3288-based development board with 2 USB ports, HDMI, + micro-SD card, audio, Gigabit Ethernet. It also includes on-board + 8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to + I2C, SPI, UART, GPIOs. + config ROCKCHIP_FAST_SPL bool "Change the CPU to full speed in SPL" depends on TARGET_CHROMEBOOK_JERRY @@ -118,6 +127,8 @@ source "board/firefly/firefly-rk3288/Kconfig" source "board/google/veyron/Kconfig" +source "board/mqmaker/miqi_rk3288/Kconfig" + source "board/radxa/rock2/Kconfig" source "board/rockchip/evb_rk3288/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 8ae3055..4f84ec1 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -10,6 +10,7 @@ #include <fdtdec.h> #include <led.h> #include <malloc.h> +#include <mmc.h> #include <ram.h> #include <spl.h> #include <asm/gpio.h> @@ -27,6 +28,104 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OF_CONTROL) +static int spl_node_to_boot_device(int node) +{ + struct udevice *parent; + + /* + * This should eventually move into the SPL code, once SPL becomes + * aware of the block-device layer. Until then (and to avoid unneeded + * delays in getting this feature out, it lives at the board-level). + */ + if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) { + struct udevice *dev; + struct blk_desc *desc = NULL; + + for (device_find_first_child(parent, &dev); + dev; + device_find_next_child(&dev)) { + if (device_get_uclass_id(dev) == UCLASS_BLK) { + desc = dev_get_uclass_platdata(dev); + break; + } + } + + if (!desc) + return -ENOENT; + + switch (desc->devnum) { + case 0: + return BOOT_DEVICE_MMC1; + case 1: + return BOOT_DEVICE_MMC2; + default: + return -ENOSYS; + } + } + + /* + * SPL doesn't differentiate SPI flashes, so we keep the detection + * brief and inaccurate... hopefully, the common SPL layer can be + * extended with awareness of the BLK layer (and matching OF_CONTROL) + * soon. + */ + if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) + return BOOT_DEVICE_SPI; + + return -1; +} + +void board_boot_order(u32 *spl_boot_list) +{ + const void *blob = gd->fdt_blob; + int chosen_node = fdt_path_offset(blob, "/chosen"); + int idx = 0; + int elem; + int boot_device; + int node; + const char *conf; + + if (chosen_node < 0) { + debug("%s: /chosen not found, using spl_boot_device()\n", + __func__); + spl_boot_list[0] = spl_boot_device(); + return; + } + + for (elem = 0; + (conf = fdt_stringlist_get(blob, chosen_node, + "u-boot,spl-boot-order", elem, NULL)); + elem++) { + /* First check if the list element is an alias */ + const char *alias = fdt_get_alias(blob, conf); + if (alias) + conf = alias; + + /* Try to resolve the config item (or alias) as a path */ + node = fdt_path_offset(blob, conf); + if (node < 0) { + debug("%s: could not find %s in FDT", __func__, conf); + continue; + } + + /* Try to map this back onto SPL boot devices */ + boot_device = spl_node_to_boot_device(node); + if (boot_device < 0) { + debug("%s: could not map node @%x to a boot-device\n", + __func__, node); + continue; + } + + spl_boot_list[idx++] = boot_device; + } + + /* If we had no matches, fall back to spl_boot_device */ + if (idx == 0) + spl_boot_list[0] = spl_boot_device(); +} +#endif + u32 spl_boot_device(void) { return BOOT_DEVICE_MMC1; @@ -96,9 +195,9 @@ void board_init_f(ulong dummy) /* Emmc clock generator: disable the clock multipilier */ rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff); - ret = spl_init(); + ret = spl_early_init(); if (ret) { - debug("spl_init() failed: %d\n", ret); + debug("spl_early_init() failed: %d\n", ret); hang(); } diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c index cbfd3fa..8bb950e 100644 --- a/arch/arm/mach-rockchip/rk3399/rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -40,6 +40,5 @@ int arch_cpu_init(void) /* Emmc clock generator: disable the clock multipilier */ rk_clrreg(GRF_EMMCCORE_CON11, 0x0ff); - printf("time %x, %x\n", readl(0xff8680a8), readl(0xff8680ac)); return 0; } diff --git a/board/mqmaker/miqi_rk3288/Kconfig b/board/mqmaker/miqi_rk3288/Kconfig new file mode 100644 index 0000000..232a112 --- /dev/null +++ b/board/mqmaker/miqi_rk3288/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MIQI_RK3288 + +config SYS_BOARD + default "miqi_rk3288" + +config SYS_VENDOR + default "mqmaker" + +config SYS_CONFIG_NAME + default "miqi_rk3288" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/mqmaker/miqi_rk3288/MAINTAINERS b/board/mqmaker/miqi_rk3288/MAINTAINERS new file mode 100644 index 0000000..053a5e6 --- /dev/null +++ b/board/mqmaker/miqi_rk3288/MAINTAINERS @@ -0,0 +1,6 @@ +MIQI +M: Jernej Skrabec <jernej.skrabec@siol.net> +S: Maintained +F: board/mqmaker/miqi_rk3288 +F: include/configs/miqi_rk3288.h +F: configs/miqi-rk3288_defconfig diff --git a/board/mqmaker/miqi_rk3288/Makefile b/board/mqmaker/miqi_rk3288/Makefile new file mode 100644 index 0000000..ec95aff --- /dev/null +++ b/board/mqmaker/miqi_rk3288/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += miqi-rk3288.o diff --git a/board/mqmaker/miqi_rk3288/miqi-rk3288.c b/board/mqmaker/miqi_rk3288/miqi-rk3288.c new file mode 100644 index 0000000..a82f0ae --- /dev/null +++ b/board/mqmaker/miqi_rk3288/miqi-rk3288.c @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> + +void board_boot_order(u32 *spl_boot_list) +{ + /* eMMC prior to sdcard. */ + spl_boot_list[0] = BOOT_DEVICE_MMC2; + spl_boot_list[1] = BOOT_DEVICE_MMC1; +} diff --git a/board/radxa/rock/Kconfig b/board/radxa/rock/Kconfig new file mode 100644 index 0000000..855b9b6 --- /dev/null +++ b/board/radxa/rock/Kconfig @@ -0,0 +1,15 @@ +if TARGET_ROCK + +config SYS_BOARD + default "rock" + +config SYS_VENDOR + default "radxa" + +config SYS_CONFIG_NAME + default "rock" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/radxa/rock/MAINTAINERS b/board/radxa/rock/MAINTAINERS new file mode 100644 index 0000000..c5f59c0 --- /dev/null +++ b/board/radxa/rock/MAINTAINERS @@ -0,0 +1,6 @@ +RADXA_ROCK +M: Heiko Stuebner <heiko@sntech.de> +S: Maintained +F: board/radxa/rock +F: include/configs/rock.h +F: configs/rock_defconfig diff --git a/board/radxa/rock/Makefile b/board/radxa/rock/Makefile new file mode 100644 index 0000000..fe94b60 --- /dev/null +++ b/board/radxa/rock/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Heiko Stuebner +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += rock.o diff --git a/board/radxa/rock/rock.c b/board/radxa/rock/rock.c new file mode 100644 index 0000000..5119e95 --- /dev/null +++ b/board/radxa/rock/rock.c @@ -0,0 +1,7 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index bedc1fd..50b0d74 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -12,6 +12,8 @@ CONFIG_SPL_ATF_TEXT_BASE=0x00010000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig new file mode 100644 index 0000000..203824b --- /dev/null +++ b/configs/miqi-rk3288_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3288=y +CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y +CONFIG_TARGET_MIQI_RK3288=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3288-miqi" +CONFIG_SILENT_CONSOLE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_SPL_PARTITION_UUIDS=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_ROCKCHIP_RK3288_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_ACT8846=y +CONFIG_REGULATOR_ACT8846=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_ROCKCHIP_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +CONFIG_CONSOLE_SCROLL_LINES=10 +CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig new file mode 100644 index 0000000..d4e12d7 --- /dev/null +++ b/configs/puma-rk3399_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ROCKCHIP_RK3399=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x80000 +CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma" +CONFIG_FIT=y +CONFIG_SPL_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_SOURCE="board/rockchip/evb_rk3399/fit_spl_atf.its" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200 +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ9031=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_ROCKCHIP_RK3399_PINCTRL=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=115200 +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0xFF180000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_ROCKCHIP_SPI=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_ERRNO_STR=y diff --git a/configs/rock_defconfig b/configs/rock_defconfig new file mode 100644 index 0000000..20a065a --- /dev/null +++ b/configs/rock_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +# CONFIG_SPL_USE_ARCH_MEMCPY is not set +# CONFIG_SPL_USE_ARCH_MEMSET is not set +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3188=y +CONFIG_ROCKCHIP_SPL_BACK_TO_BROM=y +CONFIG_TARGET_ROCK=y +CONFIG_SPL_STACK_R_ADDR=0x60080000 +CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_OF_PLATDATA=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_LED=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PINCTRL=y +CONFIG_ROCKCHIP_RK3188_PINCTRL=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_PMIC_ACT8846=y +CONFIG_REGULATOR_ACT8846=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_RAM=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x20064000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SYSRESET=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_CMD_DHRYSTONE=y +CONFIG_ERRNO_STR=y diff --git a/doc/README.rockchip b/doc/README.rockchip index 186a1a0..2d8cf9f 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -36,15 +36,16 @@ You will need: Building ======== -At present seven RK3288 boards are supported: +At present eight RK3288 boards are supported: - EVB RK3288 - use evb-rk3288 configuration - Fennec RK3288 - use fennec-rk3288 configuration - Firefly RK3288 - use firefly-rk3288 configuration - Hisense Chromebook - use chromebook_jerry configuration - - Tinker RK3288 - use tinker-rk3288 configuration + - MiQi RK3288 - use miqi-rk3288 configuration - PopMetal RK3288 - use popmetal-rk3288 configuration - Radxa Rock 2 - use rock2 configuration + - Tinker RK3288 - use tinker-rk3288 configuration Two RK3036 board are supported: @@ -147,6 +148,32 @@ For evb_rk3036 board: Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, the debug uart must be disabled + +Booting from an SD card on RK3188 +================================= + +For rk3188 boards the general storage onto the card stays the same as +described above, but the image creation needs a bit more care. + +The bootrom of rk3188 expects to find a small 1kb loader which returns +control to the bootrom, after which it will load the real loader, which +can then be up to 29kb in size and does the regular ddr init. + +Additionally the rk3188 requires everything the bootrom loads to be +rc4-encrypted. Except for the very first stage the bootrom always reads +and decodes 2kb pages, so files should be sized accordingly. + +# copy tpl, pad to 1020 bytes and append spl +cat tpl/u-boot-tpl.bin > tplspl.bin +truncate -s 1020 tplspl.bin +cat spl/u-boot-spl.bin >> tplspl.bin +tools/mkimage -n rk3188 -T rksd -d tplspl.bin out + +# truncate, encode and append u-boot.bin +truncate -s %2048 u-boot.bin +cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 7C4E0304550509072D2C7B38170D1711' >> out + + Using fastboot on rk3288 ======================== - Write GPT partition layout to mmc device which fastboot want to use it to diff --git a/doc/device-tree-bindings/chosen.txt b/doc/device-tree-bindings/chosen.txt index bf9a30a..5625d21 100644 --- a/doc/device-tree-bindings/chosen.txt +++ b/doc/device-tree-bindings/chosen.txt @@ -41,3 +41,25 @@ Example reg = <0xf00 0x10>; }; }; + +u-boot,spl-boot-order property +------------------------------ + +In a system using an SPL stage and having multiple boot sources +(e.g. SPI NOR flash, on-board eMMC and a removable SD-card), the boot +device may be probed by reading the image and verifying an image +signature. + +If the SPL is configured through the device-tree, the boot-order can +be configured with the spl-boot-order property under the /chosen node. +Each list element of the property should specify a device to be probed +in the order they are listed: references (i.e. implicit paths), a full +path or an alias is expected for each entry. + +Example +------- +/ { + chosen { + u-boot,spl-boot-order = &sdmmc, "/sdhci@fe330000"; + }; +}; diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index 459649f..d36cf8f 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -168,6 +168,65 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, return 0; } +static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf, + unsigned int hz, bool has_bwadj) +{ + static const struct pll_div apll_cfg[] = { + {.nf = 50, .nr = 1, .no = 2}, + {.nf = 67, .nr = 1, .no = 1}, + }; + int div_core_peri, div_aclk_core, cfg; + + /* + * We support two possible frequencies, the safe 600MHz + * which will work with default pmic settings and will + * be set in SPL to get away from the 24MHz default and + * the maximum of 1.6Ghz, which boards can set if they + * were able to get pmic support for it. + */ + switch (hz) { + case APLL_SAFE_HZ: + cfg = 0; + div_core_peri = 1; + div_aclk_core = 3; + break; + case APLL_HZ: + cfg = 1; + div_core_peri = 2; + div_aclk_core = 3; + break; + default: + debug("Unsupported ARMCLK frequency"); + return -EINVAL; + } + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, + APLL_MODE_SLOW << APLL_MODE_SHIFT); + + rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj); + + /* waiting for pll lock */ + while (!(readl(&grf->soc_status0) & SOCSTS_APLL_LOCK)) + udelay(1); + + /* Set divider for peripherals attached to the cpu core. */ + rk_clrsetreg(&cru->cru_clksel_con[0], + CORE_PERI_DIV_MASK << CORE_PERI_DIV_SHIFT, + div_core_peri << CORE_PERI_DIV_SHIFT); + + /* set up dependent divisor for aclk_core */ + rk_clrsetreg(&cru->cru_clksel_con[1], + CORE_ACLK_DIV_MASK << CORE_ACLK_DIV_SHIFT, + div_aclk_core << CORE_ACLK_DIV_SHIFT); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, + APLL_MODE_NORMAL << APLL_MODE_SHIFT); + + return hz; +} + /* Get pll rate by id */ static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru, enum rk_clk_id clk_id) @@ -435,6 +494,10 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate) ulong new_rate; switch (clk->id) { + case PLL_APLL: + new_rate = rkclk_configure_cpu(priv->cru, priv->grf, rate, + priv->has_bwadj); + break; case CLK_DDR: new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, priv->has_bwadj); diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 922ce7e..ff3cc37 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -47,9 +47,12 @@ struct pll_div { .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; +#if defined(CONFIG_SPL_BUILD) static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); +#else static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); +#endif static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); @@ -664,7 +667,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT == CLK_EMMC_PLL_SEL_24M) - return DIV_TO_RATE(24*1024*1024, div); + return DIV_TO_RATE(24*1000*1000, div); else return DIV_TO_RATE(GPLL_HZ, div); } @@ -682,7 +685,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, if (src_clk_div > 127) { /* use 24MHz source for 400KHz clock */ - src_clk_div = 24*1024*1024 / set_rate; + src_clk_div = 24*1000*1000 / set_rate; rk_clrsetreg(&cru->clksel_con[16], CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | @@ -799,6 +802,10 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case SCLK_EMMC: ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); break; + case SCLK_MAC: + /* nothing to do, as this is an external clock */ + ret = rate; + break; case SCLK_I2C1: case SCLK_I2C2: case SCLK_I2C3: @@ -1009,7 +1016,9 @@ static void pmuclk_init(struct rk3399_pmucru *pmucru) static int rk3399_pmuclk_probe(struct udevice *dev) { +#if CONFIG_IS_ENABLED(OF_PLATDATA) || !defined(CONFIG_SPL_BUILD) struct rk3399_pmuclk_priv *priv = dev_get_priv(dev); +#endif #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3399_pmuclk_plat *plat = dev_get_platdata(dev); diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c index 7c701cb..af925ce 100644 --- a/drivers/i2c/rk_i2c.c +++ b/drivers/i2c/rk_i2c.c @@ -380,6 +380,8 @@ static const struct dm_i2c_ops rockchip_i2c_ops = { }; static const struct udevice_id rockchip_i2c_ids[] = { + { .compatible = "rockchip,rk3066-i2c" }, + { .compatible = "rockchip,rk3188-i2c" }, { .compatible = "rockchip,rk3288-i2c" }, { } }; diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index e9b202a..5e2ca76 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -14,7 +14,9 @@ #include <asm/io.h> #include <asm/arch/periph.h> #include <asm/arch/clock.h> +#include <asm/arch/hardware.h> #include <asm/arch/grf_rk3288.h> +#include <asm/arch/grf_rk3399.h> #include <dm/pinctrl.h> #include <dt-bindings/clock/rk3288-cru.h> #include "designware.h" @@ -32,32 +34,45 @@ struct gmac_rockchip_platdata { int rx_delay; }; +struct rk_gmac_ops { + int (*fix_mac_speed)(struct dw_eth_dev *priv); + void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); +}; + + static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) { struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); + const void *blob = gd->fdt_blob; + int node = dev_of_offset(dev); + + /* Check the new naming-style first... */ + pdata->tx_delay = fdtdec_get_int(blob, node, "tx_delay", -ENOENT); + pdata->rx_delay = fdtdec_get_int(blob, node, "rx_delay", -ENOENT); - pdata->tx_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "tx-delay", 0x30); - pdata->rx_delay = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "rx-delay", 0x10); + /* ... and fall back to the old naming style or default, if necessary */ + if (pdata->tx_delay == -ENOENT) + pdata->tx_delay = fdtdec_get_int(blob, node, "tx-delay", 0x30); + if (pdata->rx_delay == -ENOENT) + pdata->rx_delay = fdtdec_get_int(blob, node, "rx-delay", 0x10); return designware_eth_ofdata_to_platdata(dev); } -static int gmac_rockchip_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) { struct rk3288_grf *grf; int clk; switch (priv->phydev->speed) { case 10: - clk = GMAC_CLK_SEL_2_5M; + clk = RK3288_GMAC_CLK_SEL_2_5M; break; case 100: - clk = GMAC_CLK_SEL_25M; + clk = RK3288_GMAC_CLK_SEL_25M; break; case 1000: - clk = GMAC_CLK_SEL_125M; + clk = RK3288_GMAC_CLK_SEL_125M; break; default: debug("Unknown phy speed: %d\n", priv->phydev->speed); @@ -65,17 +80,83 @@ static int gmac_rockchip_fix_mac_speed(struct dw_eth_dev *priv) } grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - rk_clrsetreg(&grf->soc_con1, - GMAC_CLK_SEL_MASK << GMAC_CLK_SEL_SHIFT, - clk << GMAC_CLK_SEL_SHIFT); + rk_clrsetreg(&grf->soc_con1, RK3288_GMAC_CLK_SEL_MASK, clk); + + return 0; +} + +static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) +{ + struct rk3399_grf_regs *grf; + int clk; + + switch (priv->phydev->speed) { + case 10: + clk = RK3399_GMAC_CLK_SEL_2_5M; + break; + case 100: + clk = RK3399_GMAC_CLK_SEL_25M; + break; + case 1000: + clk = RK3399_GMAC_CLK_SEL_125M; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->soc_con5, RK3399_GMAC_CLK_SEL_MASK, clk); return 0; } +static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) +{ + struct rk3288_grf *grf; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->soc_con1, + RK3288_RMII_MODE_MASK | RK3288_GMAC_PHY_INTF_SEL_MASK, + RK3288_GMAC_PHY_INTF_SEL_RGMII); + + rk_clrsetreg(&grf->soc_con3, + RK3288_RXCLK_DLY_ENA_GMAC_MASK | + RK3288_TXCLK_DLY_ENA_GMAC_MASK | + RK3288_CLK_RX_DL_CFG_GMAC_MASK | + RK3288_CLK_TX_DL_CFG_GMAC_MASK, + RK3288_RXCLK_DLY_ENA_GMAC_ENABLE | + RK3288_TXCLK_DLY_ENA_GMAC_ENABLE | + pdata->rx_delay << RK3288_CLK_RX_DL_CFG_GMAC_SHIFT | + pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); +} + +static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) +{ + struct rk3399_grf_regs *grf; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + rk_clrsetreg(&grf->soc_con5, + RK3399_GMAC_PHY_INTF_SEL_MASK, + RK3399_GMAC_PHY_INTF_SEL_RGMII); + + rk_clrsetreg(&grf->soc_con6, + RK3399_RXCLK_DLY_ENA_GMAC_MASK | + RK3399_TXCLK_DLY_ENA_GMAC_MASK | + RK3399_CLK_RX_DL_CFG_GMAC_MASK | + RK3399_CLK_TX_DL_CFG_GMAC_MASK, + RK3399_RXCLK_DLY_ENA_GMAC_ENABLE | + RK3399_TXCLK_DLY_ENA_GMAC_ENABLE | + pdata->rx_delay << RK3399_CLK_RX_DL_CFG_GMAC_SHIFT | + pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); +} + static int gmac_rockchip_probe(struct udevice *dev) { struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); - struct rk3288_grf *grf; + struct rk_gmac_ops *ops = + (struct rk_gmac_ops *)dev_get_driver_data(dev); struct clk clk; int ret; @@ -89,21 +170,7 @@ static int gmac_rockchip_probe(struct udevice *dev) return ret; /* Set to RGMII mode */ - grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - rk_clrsetreg(&grf->soc_con1, - RMII_MODE_MASK << RMII_MODE_SHIFT | - GMAC_PHY_INTF_SEL_MASK << GMAC_PHY_INTF_SEL_SHIFT, - GMAC_PHY_INTF_SEL_RGMII << GMAC_PHY_INTF_SEL_SHIFT); - - rk_clrsetreg(&grf->soc_con3, - RXCLK_DLY_ENA_GMAC_MASK << RXCLK_DLY_ENA_GMAC_SHIFT | - TXCLK_DLY_ENA_GMAC_MASK << TXCLK_DLY_ENA_GMAC_SHIFT | - CLK_RX_DL_CFG_GMAC_MASK << CLK_RX_DL_CFG_GMAC_SHIFT | - CLK_TX_DL_CFG_GMAC_MASK << CLK_TX_DL_CFG_GMAC_SHIFT, - RXCLK_DLY_ENA_GMAC_ENABLE << RXCLK_DLY_ENA_GMAC_SHIFT | - TXCLK_DLY_ENA_GMAC_ENABLE << TXCLK_DLY_ENA_GMAC_SHIFT | - pdata->rx_delay << CLK_RX_DL_CFG_GMAC_SHIFT | - pdata->tx_delay << CLK_TX_DL_CFG_GMAC_SHIFT); + ops->set_to_rgmii(pdata); return designware_eth_probe(dev); } @@ -112,12 +179,14 @@ static int gmac_rockchip_eth_start(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct dw_eth_dev *priv = dev_get_priv(dev); + struct rk_gmac_ops *ops = + (struct rk_gmac_ops *)dev_get_driver_data(dev); int ret; ret = designware_eth_init(priv, pdata->enetaddr); if (ret) return ret; - ret = gmac_rockchip_fix_mac_speed(priv); + ret = ops->fix_mac_speed(priv); if (ret) return ret; ret = designware_eth_enable(priv); @@ -136,8 +205,21 @@ const struct eth_ops gmac_rockchip_eth_ops = { .write_hwaddr = designware_eth_write_hwaddr, }; +const struct rk_gmac_ops rk3288_gmac_ops = { + .fix_mac_speed = rk3288_gmac_fix_mac_speed, + .set_to_rgmii = rk3288_gmac_set_to_rgmii, +}; + +const struct rk_gmac_ops rk3399_gmac_ops = { + .fix_mac_speed = rk3399_gmac_fix_mac_speed, + .set_to_rgmii = rk3399_gmac_set_to_rgmii, +}; + static const struct udevice_id rockchip_gmac_ids[] = { - { .compatible = "rockchip,rk3288-gmac" }, + { .compatible = "rockchip,rk3288-gmac", + .data = (ulong)&rk3288_gmac_ops }, + { .compatible = "rockchip,rk3399-gmac", + .data = (ulong)&rk3399_gmac_ops }, { } }; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 9e2736c..9d0f501 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -133,7 +133,7 @@ config ROCKCHIP_RK3036_PINCTRL function. config ROCKCHIP_RK3188_PINCTRL - bool "Rockchip pin control driver" + bool "Rockchip rk3188 pin control driver" depends on DM help Support pin multiplexing control on Rockchip rk3188 SoCs. The driver @@ -142,7 +142,7 @@ config ROCKCHIP_RK3188_PINCTRL function. config ROCKCHIP_RK3288_PINCTRL - bool "Rockchip pin control driver" + bool "Rockchip rk3288 pin control driver" depends on DM help Support pin multiplexing control on Rockchip rk3288 SoCs. The driver @@ -158,7 +158,7 @@ config PINCTRL_AT91PIO4 controller which is available on SAMA5D2 SoC. config ROCKCHIP_RK3328_PINCTRL - bool "Rockchip pin control driver" + bool "Rockchip rk3328 pin control driver" depends on DM help Support pin multiplexing control on Rockchip rk3328 SoCs. The driver @@ -167,7 +167,7 @@ config ROCKCHIP_RK3328_PINCTRL function. config ROCKCHIP_RK3399_PINCTRL - bool "Rockchip pin control driver" + bool "Rockchip rk3399 pin control driver" depends on DM help Support pin multiplexing control on Rockchip rk3399 SoCs. The driver diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c b/drivers/pinctrl/rockchip/pinctrl_rk3399.c index a74793a..507bec4 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3399.c @@ -202,6 +202,39 @@ static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs *grf, int mmc_id) } } +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) +static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id) +{ + rk_clrsetreg(&grf->gpio3a_iomux, + GRF_GPIO3A0_SEL_MASK | GRF_GPIO3A1_SEL_MASK | + GRF_GPIO3A2_SEL_MASK | GRF_GPIO3A3_SEL_MASK | + GRF_GPIO3A4_SEL_MASK | GRF_GPIO3A5_SEL_MASK | + GRF_GPIO3A6_SEL_MASK | GRF_GPIO3A7_SEL_MASK, + GRF_MAC_TXD2 << GRF_GPIO3A0_SEL_SHIFT | + GRF_MAC_TXD3 << GRF_GPIO3A1_SEL_SHIFT | + GRF_MAC_RXD2 << GRF_GPIO3A2_SEL_SHIFT | + GRF_MAC_RXD3 << GRF_GPIO3A3_SEL_SHIFT | + GRF_MAC_TXD0 << GRF_GPIO3A4_SEL_SHIFT | + GRF_MAC_TXD1 << GRF_GPIO3A5_SEL_SHIFT | + GRF_MAC_RXD0 << GRF_GPIO3A6_SEL_SHIFT | + GRF_MAC_RXD1 << GRF_GPIO3A7_SEL_SHIFT); + rk_clrsetreg(&grf->gpio3b_iomux, + GRF_GPIO3B0_SEL_MASK | GRF_GPIO3B1_SEL_MASK | + GRF_GPIO3B3_SEL_MASK | + GRF_GPIO3B4_SEL_MASK | GRF_GPIO3B5_SEL_MASK | + GRF_GPIO3B6_SEL_MASK, + GRF_MAC_MDC << GRF_GPIO3B0_SEL_SHIFT | + GRF_MAC_RXDV << GRF_GPIO3B1_SEL_SHIFT | + GRF_MAC_CLK << GRF_GPIO3B3_SEL_SHIFT | + GRF_MAC_TXEN << GRF_GPIO3B4_SEL_SHIFT | + GRF_MAC_MDIO << GRF_GPIO3B5_SEL_SHIFT | + GRF_MAC_RXCLK << GRF_GPIO3B6_SEL_SHIFT); + rk_clrsetreg(&grf->gpio3c_iomux, + GRF_GPIO3C1_SEL_MASK, + GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT); +} +#endif + static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) { struct rk3399_pinctrl_priv *priv = dev_get_priv(dev); @@ -243,6 +276,11 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_SDMMC1: pinctrl_rk3399_sdmmc_config(priv->grf, func); break; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case PERIPH_ID_GMAC: + pinctrl_rk3399_gmac_config(priv->grf, func); + break; +#endif default: return -EINVAL; } @@ -283,6 +321,10 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_I2C5; case 65: return PERIPH_ID_SDMMC1; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case 12: + return PERIPH_ID_GMAC; +#endif } #endif return -ENOENT; diff --git a/drivers/video/dw_hdmi.c b/drivers/video/dw_hdmi.c new file mode 100644 index 0000000..8a53109 --- /dev/null +++ b/drivers/video/dw_hdmi.c @@ -0,0 +1,764 @@ +/* + * Copyright (c) 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + * Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <asm/io.h> +#include "dw_hdmi.h" + +struct tmds_n_cts { + u32 tmds; + u32 cts; + u32 n; +}; + +static const struct tmds_n_cts n_cts_table[] = { + { + .tmds = 25175000, .n = 6144, .cts = 25175, + }, { + .tmds = 25200000, .n = 6144, .cts = 25200, + }, { + .tmds = 27000000, .n = 6144, .cts = 27000, + }, { + .tmds = 27027000, .n = 6144, .cts = 27027, + }, { + .tmds = 40000000, .n = 6144, .cts = 40000, + }, { + .tmds = 54000000, .n = 6144, .cts = 54000, + }, { + .tmds = 54054000, .n = 6144, .cts = 54054, + }, { + .tmds = 65000000, .n = 6144, .cts = 65000, + }, { + .tmds = 74176000, .n = 11648, .cts = 140625, + }, { + .tmds = 74250000, .n = 6144, .cts = 74250, + }, { + .tmds = 83500000, .n = 6144, .cts = 83500, + }, { + .tmds = 106500000, .n = 6144, .cts = 106500, + }, { + .tmds = 108000000, .n = 6144, .cts = 108000, + }, { + .tmds = 148352000, .n = 5824, .cts = 140625, + }, { + .tmds = 148500000, .n = 6144, .cts = 148500, + }, { + .tmds = 297000000, .n = 5120, .cts = 247500, + } +}; + +static void hdmi_write(struct dw_hdmi *hdmi, u8 val, int offset) +{ + switch (hdmi->reg_io_width) { + case 1: + writeb(val, hdmi->ioaddr + offset); + break; + case 4: + writel(val, hdmi->ioaddr + (offset << 2)); + break; + default: + debug("reg_io_width has unsupported width!\n"); + break; + } +} + +static u8 hdmi_read(struct dw_hdmi *hdmi, int offset) +{ + switch (hdmi->reg_io_width) { + case 1: + return readb(hdmi->ioaddr + offset); + case 4: + return readl(hdmi->ioaddr + (offset << 2)); + default: + debug("reg_io_width has unsupported width!\n"); + break; + } + + return 0; +} + +static void hdmi_mod(struct dw_hdmi *hdmi, unsigned reg, u8 mask, u8 data) +{ + u8 val = hdmi_read(hdmi, reg) & ~mask; + + val |= data & mask; + hdmi_write(hdmi, val, reg); +} + +static void hdmi_set_clock_regenerator(struct dw_hdmi *hdmi, u32 n, u32 cts) +{ + uint cts3; + uint n3; + + /* first set ncts_atomic_write (if present) */ + n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE; + hdmi_write(hdmi, n3, HDMI_AUD_N3); + + /* set cts_manual (if present) */ + cts3 = HDMI_AUD_CTS3_CTS_MANUAL; + + cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET; + cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK; + + /* write cts values; cts3 must be written first */ + hdmi_write(hdmi, cts3, HDMI_AUD_CTS3); + hdmi_write(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); + hdmi_write(hdmi, cts & 0xff, HDMI_AUD_CTS1); + + /* write n values; n1 must be written last */ + n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK; + hdmi_write(hdmi, n3, HDMI_AUD_N3); + hdmi_write(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); + hdmi_write(hdmi, n & 0xff, HDMI_AUD_N3); + + hdmi_write(hdmi, HDMI_AUD_INPUTCLKFS_128, HDMI_AUD_INPUTCLKFS); +} + +static int hdmi_lookup_n_cts(u32 pixel_clk) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(n_cts_table); i++) + if (pixel_clk <= n_cts_table[i].tmds) + break; + + if (i >= ARRAY_SIZE(n_cts_table)) + return -1; + + return i; +} + +static void hdmi_audio_set_samplerate(struct dw_hdmi *hdmi, u32 pixel_clk) +{ + u32 clk_n, clk_cts; + int index; + + index = hdmi_lookup_n_cts(pixel_clk); + if (index == -1) { + debug("audio not supported for pixel clk %d\n", pixel_clk); + return; + } + + clk_n = n_cts_table[index].n; + clk_cts = n_cts_table[index].cts; + hdmi_set_clock_regenerator(hdmi, clk_n, clk_cts); +} + +/* + * this submodule is responsible for the video data synchronization. + * for example, for rgb 4:4:4 input, the data map is defined as + * pin{47~40} <==> r[7:0] + * pin{31~24} <==> g[7:0] + * pin{15~8} <==> b[7:0] + */ +static void hdmi_video_sample(struct dw_hdmi *hdmi) +{ + u32 color_format = 0x01; + uint val; + + val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | + ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & + HDMI_TX_INVID0_VIDEO_MAPPING_MASK); + + hdmi_write(hdmi, val, HDMI_TX_INVID0); + + /* enable tx stuffing: when de is inactive, fix the output data to 0 */ + val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | + HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; + hdmi_write(hdmi, val, HDMI_TX_INSTUFFING); + hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA0); + hdmi_write(hdmi, 0x0, HDMI_TX_GYDATA1); + hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA0); + hdmi_write(hdmi, 0x0, HDMI_TX_RCRDATA1); + hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA0); + hdmi_write(hdmi, 0x0, HDMI_TX_BCBDATA1); +} + +static void hdmi_video_packetize(struct dw_hdmi *hdmi) +{ + u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; + u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT; + u32 color_depth = 0; + uint val, vp_conf; + + /* set the packetizer registers */ + val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & + HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | + ((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); + hdmi_write(hdmi, val, HDMI_VP_PR_CD); + + hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PR_STUFFING_MASK, + HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE); + + /* data from pixel repeater block */ + vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | + HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; + + hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_PR_EN_MASK | + HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf); + + hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, + 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET); + + hdmi_write(hdmi, remap_size, HDMI_VP_REMAP); + + vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | + HDMI_VP_CONF_PP_EN_DISABLE | + HDMI_VP_CONF_YCC422_EN_DISABLE; + + hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_BYPASS_EN_MASK | + HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK, + vp_conf); + + hdmi_mod(hdmi, HDMI_VP_STUFF, HDMI_VP_STUFF_PP_STUFFING_MASK | + HDMI_VP_STUFF_YCC422_STUFFING_MASK, + HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | + HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE); + + hdmi_mod(hdmi, HDMI_VP_CONF, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, + output_select); +} + +static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, uint bit) +{ + hdmi_mod(hdmi, HDMI_PHY_TST0, HDMI_PHY_TST0_TSTCLR_MASK, + bit << HDMI_PHY_TST0_TSTCLR_OFFSET); +} + +static int hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, u32 msec) +{ + ulong start; + u32 val; + + start = get_timer(0); + do { + val = hdmi_read(hdmi, HDMI_IH_I2CMPHY_STAT0); + if (val & 0x3) { + hdmi_write(hdmi, val, HDMI_IH_I2CMPHY_STAT0); + return 0; + } + + udelay(100); + } while (get_timer(start) < msec); + + return 1; +} + +static void hdmi_phy_i2c_write(struct dw_hdmi *hdmi, uint data, uint addr) +{ + hdmi_write(hdmi, 0xff, HDMI_IH_I2CMPHY_STAT0); + hdmi_write(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); + hdmi_write(hdmi, (u8)(data >> 8), HDMI_PHY_I2CM_DATAO_1_ADDR); + hdmi_write(hdmi, (u8)(data >> 0), HDMI_PHY_I2CM_DATAO_0_ADDR); + hdmi_write(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, + HDMI_PHY_I2CM_OPERATION_ADDR); + + hdmi_phy_wait_i2c_done(hdmi, 1000); +} + +static void hdmi_phy_enable_power(struct dw_hdmi *hdmi, uint enable) +{ + hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_PDZ_MASK, + enable << HDMI_PHY_CONF0_PDZ_OFFSET); +} + +static void hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, uint enable) +{ + hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_ENTMDS_MASK, + enable << HDMI_PHY_CONF0_ENTMDS_OFFSET); +} + +static void hdmi_phy_enable_spare(struct dw_hdmi *hdmi, uint enable) +{ + hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SPARECTRL_MASK, + enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET); +} + +static void hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, uint enable) +{ + hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK, + enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET); +} + +static void hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, uint enable) +{ + hdmi_mod(hdmi, HDMI_PHY_CONF0, + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK, + enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET); +} + +static void hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, uint enable) +{ + hdmi_mod(hdmi, HDMI_PHY_CONF0, + HDMI_PHY_CONF0_SELDATAENPOL_MASK, + enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET); +} + +static void hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, + uint enable) +{ + hdmi_mod(hdmi, HDMI_PHY_CONF0, HDMI_PHY_CONF0_SELDIPIF_MASK, + enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET); +} + +static int hdmi_phy_configure(struct dw_hdmi *hdmi, u32 mpixelclock) +{ + ulong start; + uint i, val; + + if (!hdmi->mpll_cfg || !hdmi->phy_cfg) + return -1; + + /* gen2 tx power off */ + hdmi_phy_gen2_txpwron(hdmi, 0); + + /* gen2 pddq */ + hdmi_phy_gen2_pddq(hdmi, 1); + + /* phy reset */ + hdmi_write(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ); + hdmi_write(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ); + hdmi_write(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); + + hdmi_phy_test_clear(hdmi, 1); + hdmi_write(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, + HDMI_PHY_I2CM_SLAVE_ADDR); + hdmi_phy_test_clear(hdmi, 0); + + /* pll/mpll cfg - always match on final entry */ + for (i = 0; hdmi->mpll_cfg[i].mpixelclock != (~0ul); i++) + if (mpixelclock <= hdmi->mpll_cfg[i].mpixelclock) + break; + + hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG); + hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].gmp, PHY_PLLGMPCTRL); + hdmi_phy_i2c_write(hdmi, hdmi->mpll_cfg[i].curr, PHY_PLLCURRCTRL); + + hdmi_phy_i2c_write(hdmi, 0x0000, PHY_PLLPHBYCTRL); + hdmi_phy_i2c_write(hdmi, 0x0006, PHY_PLLCLKBISTPHASE); + + for (i = 0; hdmi->phy_cfg[i].mpixelclock != (~0ul); i++) + if (mpixelclock <= hdmi->phy_cfg[i].mpixelclock) + break; + + /* + * resistance term 133ohm cfg + * preemp cgf 0.00 + * tx/ck lvl 10 + */ + hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].term, PHY_TXTERM); + hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].sym_ctr, PHY_CKSYMTXCTRL); + hdmi_phy_i2c_write(hdmi, hdmi->phy_cfg[i].vlev_ctr, PHY_VLEVCTRL); + + /* remove clk term */ + hdmi_phy_i2c_write(hdmi, 0x8000, PHY_CKCALCTRL); + + hdmi_phy_enable_power(hdmi, 1); + + /* toggle tmds enable */ + hdmi_phy_enable_tmds(hdmi, 0); + hdmi_phy_enable_tmds(hdmi, 1); + + /* gen2 tx power on */ + hdmi_phy_gen2_txpwron(hdmi, 1); + hdmi_phy_gen2_pddq(hdmi, 0); + + hdmi_phy_enable_spare(hdmi, 1); + + /* wait for phy pll lock */ + start = get_timer(0); + do { + val = hdmi_read(hdmi, HDMI_PHY_STAT0); + if (!(val & HDMI_PHY_TX_PHY_LOCK)) + return 0; + + udelay(100); + } while (get_timer(start) < 5); + + return -1; +} + +static void hdmi_av_composer(struct dw_hdmi *hdmi, + const struct display_timing *edid) +{ + bool mdataenablepolarity = true; + uint inv_val; + uint hbl; + uint vbl; + + hbl = edid->hback_porch.typ + edid->hfront_porch.typ + + edid->hsync_len.typ; + vbl = edid->vback_porch.typ + edid->vfront_porch.typ + + edid->vsync_len.typ; + + /* set up hdmi_fc_invidconf */ + inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE; + + inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ? + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW); + + inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ? + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW); + + inv_val |= (mdataenablepolarity ? + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); + + /* + * TODO(sjg@chromium.org>: Need to check for HDMI / DVI + * inv_val |= (edid->hdmi_monitor_detected ? + * HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : + * HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE); + */ + inv_val |= HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE; + + inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; + + inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; + + hdmi_write(hdmi, inv_val, HDMI_FC_INVIDCONF); + + /* set up horizontal active pixel width */ + hdmi_write(hdmi, edid->hactive.typ >> 8, HDMI_FC_INHACTV1); + hdmi_write(hdmi, edid->hactive.typ, HDMI_FC_INHACTV0); + + /* set up vertical active lines */ + hdmi_write(hdmi, edid->vactive.typ >> 8, HDMI_FC_INVACTV1); + hdmi_write(hdmi, edid->vactive.typ, HDMI_FC_INVACTV0); + + /* set up horizontal blanking pixel region width */ + hdmi_write(hdmi, hbl >> 8, HDMI_FC_INHBLANK1); + hdmi_write(hdmi, hbl, HDMI_FC_INHBLANK0); + + /* set up vertical blanking pixel region width */ + hdmi_write(hdmi, vbl, HDMI_FC_INVBLANK); + + /* set up hsync active edge delay width (in pixel clks) */ + hdmi_write(hdmi, edid->hfront_porch.typ >> 8, HDMI_FC_HSYNCINDELAY1); + hdmi_write(hdmi, edid->hfront_porch.typ, HDMI_FC_HSYNCINDELAY0); + + /* set up vsync active edge delay (in lines) */ + hdmi_write(hdmi, edid->vfront_porch.typ, HDMI_FC_VSYNCINDELAY); + + /* set up hsync active pulse width (in pixel clks) */ + hdmi_write(hdmi, edid->hsync_len.typ >> 8, HDMI_FC_HSYNCINWIDTH1); + hdmi_write(hdmi, edid->hsync_len.typ, HDMI_FC_HSYNCINWIDTH0); + + /* set up vsync active edge delay (in lines) */ + hdmi_write(hdmi, edid->vsync_len.typ, HDMI_FC_VSYNCINWIDTH); +} + +/* hdmi initialization step b.4 */ +static void hdmi_enable_video_path(struct dw_hdmi *hdmi) +{ + uint clkdis; + + /* control period minimum duration */ + hdmi_write(hdmi, 12, HDMI_FC_CTRLDUR); + hdmi_write(hdmi, 32, HDMI_FC_EXCTRLDUR); + hdmi_write(hdmi, 1, HDMI_FC_EXCTRLSPAC); + + /* set to fill tmds data channels */ + hdmi_write(hdmi, 0x0b, HDMI_FC_CH0PREAM); + hdmi_write(hdmi, 0x16, HDMI_FC_CH1PREAM); + hdmi_write(hdmi, 0x21, HDMI_FC_CH2PREAM); + + hdmi_write(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, + HDMI_MC_FLOWCTRL); + + /* enable pixel clock and tmds data path */ + clkdis = 0x7f; + clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; + hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS); + + clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; + hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS); + + clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; + hdmi_write(hdmi, clkdis, HDMI_MC_CLKDIS); +} + +/* workaround to clear the overflow condition */ +static void hdmi_clear_overflow(struct dw_hdmi *hdmi) +{ + uint val, count; + + /* tmds software reset */ + hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); + + val = hdmi_read(hdmi, HDMI_FC_INVIDCONF); + + for (count = 0; count < 4; count++) + hdmi_write(hdmi, val, HDMI_FC_INVIDCONF); +} + +static void hdmi_audio_set_format(struct dw_hdmi *hdmi) +{ + hdmi_write(hdmi, HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0, + HDMI_AUD_CONF0); + + + hdmi_write(hdmi, HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE | + HDMI_AUD_CONF1_I2S_WIDTH_16BIT, HDMI_AUD_CONF1); + + hdmi_write(hdmi, 0x00, HDMI_AUD_CONF2); +} + +static void hdmi_audio_fifo_reset(struct dw_hdmi *hdmi) +{ + hdmi_write(hdmi, (u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ, HDMI_MC_SWRSTZ); + hdmi_write(hdmi, HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST, HDMI_AUD_CONF0); + + hdmi_write(hdmi, 0x00, HDMI_AUD_INT); + hdmi_write(hdmi, 0x00, HDMI_AUD_INT1); +} + +static int hdmi_get_plug_in_status(struct dw_hdmi *hdmi) +{ + uint val = hdmi_read(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD; + + return !!val; +} + +static int hdmi_ddc_wait_i2c_done(struct dw_hdmi *hdmi, int msec) +{ + u32 val; + ulong start; + + start = get_timer(0); + do { + val = hdmi_read(hdmi, HDMI_IH_I2CM_STAT0); + if (val & 0x2) { + hdmi_write(hdmi, val, HDMI_IH_I2CM_STAT0); + return 0; + } + + udelay(100); + } while (get_timer(start) < msec); + + return 1; +} + +static void hdmi_ddc_reset(struct dw_hdmi *hdmi) +{ + hdmi_mod(hdmi, HDMI_I2CM_SOFTRSTZ, HDMI_I2CM_SOFTRSTZ_MASK, 0); +} + +static int hdmi_read_edid(struct dw_hdmi *hdmi, int block, u8 *buff) +{ + int shift = (block % 2) * 0x80; + int edid_read_err = 0; + u32 trytime = 5; + u32 n; + + /* set ddc i2c clk which devided from ddc_clk to 100khz */ + hdmi_write(hdmi, hdmi->i2c_clk_high, HDMI_I2CM_SS_SCL_HCNT_0_ADDR); + hdmi_write(hdmi, hdmi->i2c_clk_low, HDMI_I2CM_SS_SCL_LCNT_0_ADDR); + hdmi_mod(hdmi, HDMI_I2CM_DIV, HDMI_I2CM_DIV_FAST_STD_MODE, + HDMI_I2CM_DIV_STD_MODE); + + hdmi_write(hdmi, HDMI_I2CM_SLAVE_DDC_ADDR, HDMI_I2CM_SLAVE); + hdmi_write(hdmi, HDMI_I2CM_SEGADDR_DDC, HDMI_I2CM_SEGADDR); + hdmi_write(hdmi, block >> 1, HDMI_I2CM_SEGPTR); + + while (trytime--) { + edid_read_err = 0; + + for (n = 0; n < HDMI_EDID_BLOCK_SIZE; n++) { + hdmi_write(hdmi, shift + n, HDMI_I2CM_ADDRESS); + + if (block == 0) + hdmi_write(hdmi, HDMI_I2CM_OP_RD8, + HDMI_I2CM_OPERATION); + else + hdmi_write(hdmi, HDMI_I2CM_OP_RD8_EXT, + HDMI_I2CM_OPERATION); + + if (hdmi_ddc_wait_i2c_done(hdmi, 10)) { + hdmi_ddc_reset(hdmi); + edid_read_err = 1; + break; + } + + buff[n] = hdmi_read(hdmi, HDMI_I2CM_DATAI); + } + + if (!edid_read_err) + break; + } + + return edid_read_err; +} + +static const u8 pre_buf[] = { + 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, + 0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00, + 0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78, + 0x2a, 0xd9, 0x45, 0xa2, 0x55, 0x4d, 0xa0, 0x27, + 0x12, 0x50, 0x54, 0xb7, 0xef, 0x00, 0x71, 0x4f, + 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00, + 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x00, 0x02, 0x3a, + 0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c, + 0x45, 0x00, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, + 0x00, 0x00, 0x00, 0xff, 0x00, 0x44, 0x34, 0x4c, + 0x4d, 0x54, 0x46, 0x30, 0x37, 0x35, 0x39, 0x37, + 0x36, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x32, + 0x4b, 0x18, 0x53, 0x11, 0x00, 0x0a, 0x20, 0x20, + 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc, + 0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x53, + 0x32, 0x33, 0x38, 0x0a, 0x20, 0x20, 0x01, 0xb0, + 0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03, + 0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f, + 0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x17, 0x07, + 0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00, + 0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0, + 0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0xfd, 0x1e, + 0x11, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72, + 0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00, + 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 0x01, 0x1d, + 0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28, + 0x55, 0x40, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, + 0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20, + 0x0c, 0x40, 0x55, 0x00, 0xfd, 0x1e, 0x11, 0x00, + 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9, +}; + +int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock) +{ + int i, ret; + + /* hdmi phy spec says to do the phy initialization sequence twice */ + for (i = 0; i < 2; i++) { + hdmi_phy_sel_data_en_pol(hdmi, 1); + hdmi_phy_sel_interface_control(hdmi, 0); + hdmi_phy_enable_tmds(hdmi, 0); + hdmi_phy_enable_power(hdmi, 0); + + ret = hdmi_phy_configure(hdmi, mpixelclock); + if (ret) { + debug("hdmi phy config failure %d\n", ret); + return ret; + } + } + + return 0; +} + +int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi) +{ + ulong start; + + start = get_timer(0); + do { + if (hdmi_get_plug_in_status(hdmi)) + return 0; + udelay(100); + } while (get_timer(start) < 300); + + return -1; +} + +void dw_hdmi_phy_init(struct dw_hdmi *hdmi) +{ + /* enable phy i2cm done irq */ + hdmi_write(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, + HDMI_PHY_I2CM_INT_ADDR); + + /* enable phy i2cm nack & arbitration error irq */ + hdmi_write(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, + HDMI_PHY_I2CM_CTLINT_ADDR); + + /* enable cable hot plug irq */ + hdmi_write(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0); + + /* clear hotplug interrupts */ + hdmi_write(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0); +} + +int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size) +{ + u32 edid_size = HDMI_EDID_BLOCK_SIZE; + int ret; + + if (0) { + edid_size = sizeof(pre_buf); + memcpy(buf, pre_buf, edid_size); + } else { + ret = hdmi_read_edid(hdmi, 0, buf); + if (ret) { + debug("failed to read edid.\n"); + return -1; + } + + if (buf[0x7e] != 0) { + hdmi_read_edid(hdmi, 1, buf + HDMI_EDID_BLOCK_SIZE); + edid_size += HDMI_EDID_BLOCK_SIZE; + } + } + + return edid_size; +} + +int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid) +{ + int ret; + + debug("hdmi, mode info : clock %d hdis %d vdis %d\n", + edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ); + + hdmi_av_composer(hdmi, edid); + + ret = hdmi->phy_set(hdmi, edid->pixelclock.typ); + if (ret) + return ret; + + hdmi_enable_video_path(hdmi); + + hdmi_audio_fifo_reset(hdmi); + hdmi_audio_set_format(hdmi); + hdmi_audio_set_samplerate(hdmi, edid->pixelclock.typ); + + hdmi_video_packetize(hdmi); + hdmi_video_sample(hdmi); + + hdmi_clear_overflow(hdmi); + + return 0; +} + +void dw_hdmi_init(struct dw_hdmi *hdmi) +{ + uint ih_mute; + + /* + * boot up defaults are: + * hdmi_ih_mute = 0x03 (disabled) + * hdmi_ih_mute_* = 0x00 (enabled) + * + * disable top level interrupt bits in hdmi block + */ + ih_mute = /*hdmi_read(hdmi, HDMI_IH_MUTE) |*/ + HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | + HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; + + hdmi_write(hdmi, ih_mute, HDMI_IH_MUTE); + + /* enable i2c master done irq */ + hdmi_write(hdmi, ~0x04, HDMI_I2CM_INT); + + /* enable i2c client nack % arbitration error irq */ + hdmi_write(hdmi, ~0x44, HDMI_I2CM_CTLINT); +} diff --git a/drivers/video/rockchip/Makefile b/drivers/video/rockchip/Makefile index 7962f86..755350b 100644 --- a/drivers/video/rockchip/Makefile +++ b/drivers/video/rockchip/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o +obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o ../dw_hdmi.o diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index c8608db..db07588 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -9,6 +9,7 @@ #include <clk.h> #include <display.h> #include <dm.h> +#include <dw_hdmi.h> #include <edid.h> #include <regmap.h> #include <syscon.h> @@ -16,73 +17,13 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/grf_rk3288.h> -#include <asm/arch/hdmi_rk3288.h> #include <power/regulator.h> -struct tmds_n_cts { - u32 tmds; - u32 cts; - u32 n; -}; - struct rk_hdmi_priv { - struct rk3288_hdmi *regs; + struct dw_hdmi hdmi; struct rk3288_grf *grf; }; -static const struct tmds_n_cts n_cts_table[] = { - { - .tmds = 25175000, .n = 6144, .cts = 25175, - }, { - .tmds = 25200000, .n = 6144, .cts = 25200, - }, { - .tmds = 27000000, .n = 6144, .cts = 27000, - }, { - .tmds = 27027000, .n = 6144, .cts = 27027, - }, { - .tmds = 40000000, .n = 6144, .cts = 40000, - }, { - .tmds = 54000000, .n = 6144, .cts = 54000, - }, { - .tmds = 54054000, .n = 6144, .cts = 54054, - }, { - .tmds = 65000000, .n = 6144, .cts = 65000, - }, { - .tmds = 74176000, .n = 11648, .cts = 140625, - }, { - .tmds = 74250000, .n = 6144, .cts = 74250, - }, { - .tmds = 83500000, .n = 6144, .cts = 83500, - }, { - .tmds = 106500000, .n = 6144, .cts = 106500, - }, { - .tmds = 108000000, .n = 6144, .cts = 108000, - }, { - .tmds = 148352000, .n = 5824, .cts = 140625, - }, { - .tmds = 148500000, .n = 6144, .cts = 148500, - }, { - .tmds = 297000000, .n = 5120, .cts = 247500, - } -}; - -struct hdmi_mpll_config { - u64 mpixelclock; - /* Mode of Operation and PLL Dividers Control Register */ - u32 cpce; - /* PLL Gmp Control Register */ - u32 gmp; - /* PLL Current COntrol Register */ - u32 curr; -}; - -struct hdmi_phy_config { - u64 mpixelclock; - u32 sym_ctr; /* clock symbol and transmitter control */ - u32 term; /* transmission termination value */ - u32 vlev_ctr; /* voltage level control */ -}; - static const struct hdmi_phy_config rockchip_phy_config[] = { { .mpixelclock = 74250000, @@ -124,693 +65,41 @@ static const struct hdmi_mpll_config rockchip_mpll_cfg[] = { } }; -static void hdmi_set_clock_regenerator(struct rk3288_hdmi *regs, u32 n, u32 cts) -{ - uint cts3; - uint n3; - - /* first set ncts_atomic_write (if present) */ - n3 = HDMI_AUD_N3_NCTS_ATOMIC_WRITE; - writel(n3, ®s->aud_n3); - - /* set cts_manual (if present) */ - cts3 = HDMI_AUD_CTS3_CTS_MANUAL; - - cts3 |= HDMI_AUD_CTS3_N_SHIFT_1 << HDMI_AUD_CTS3_N_SHIFT_OFFSET; - cts3 |= (cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK; - - /* write cts values; cts3 must be written first */ - writel(cts3, ®s->aud_cts3); - writel((cts >> 8) & 0xff, ®s->aud_cts2); - writel(cts & 0xff, ®s->aud_cts1); - - /* write n values; n1 must be written last */ - n3 |= (n >> 16) & HDMI_AUD_N3_AUDN19_16_MASK; - writel(n3, ®s->aud_n3); - writel((n >> 8) & 0xff, ®s->aud_n2); - writel(n & 0xff, ®s->aud_n1); - - writel(HDMI_AUD_INPUTCLKFS_128, ®s->aud_inputclkfs); -} - -static int hdmi_lookup_n_cts(u32 pixel_clk) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(n_cts_table); i++) - if (pixel_clk <= n_cts_table[i].tmds) - break; - - if (i >= ARRAY_SIZE(n_cts_table)) - return -1; - - return i; -} - -static void hdmi_audio_set_samplerate(struct rk3288_hdmi *regs, u32 pixel_clk) -{ - u32 clk_n, clk_cts; - int index; - - index = hdmi_lookup_n_cts(pixel_clk); - if (index == -1) { - debug("audio not supported for pixel clk %d\n", pixel_clk); - return; - } - - clk_n = n_cts_table[index].n; - clk_cts = n_cts_table[index].cts; - hdmi_set_clock_regenerator(regs, clk_n, clk_cts); -} - -/* - * this submodule is responsible for the video data synchronization. - * for example, for rgb 4:4:4 input, the data map is defined as - * pin{47~40} <==> r[7:0] - * pin{31~24} <==> g[7:0] - * pin{15~8} <==> b[7:0] - */ -static void hdmi_video_sample(struct rk3288_hdmi *regs) -{ - u32 color_format = 0x01; - uint val; - - val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | - ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & - HDMI_TX_INVID0_VIDEO_MAPPING_MASK); - - writel(val, ®s->tx_invid0); - - /* enable tx stuffing: when de is inactive, fix the output data to 0 */ - val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | - HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | - HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; - writel(val, ®s->tx_instuffing); - writel(0x0, ®s->tx_gydata0); - writel(0x0, ®s->tx_gydata1); - writel(0x0, ®s->tx_rcrdata0); - writel(0x0, ®s->tx_rcrdata1); - writel(0x0, ®s->tx_bcbdata0); - writel(0x0, ®s->tx_bcbdata1); -} - -static void hdmi_video_packetize(struct rk3288_hdmi *regs) -{ - u32 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; - u32 remap_size = HDMI_VP_REMAP_YCC422_16BIT; - u32 color_depth = 0; - uint val, vp_conf; - - /* set the packetizer registers */ - val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & - HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | - ((0 << HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & - HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); - writel(val, ®s->vp_pr_cd); - - clrsetbits_le32(®s->vp_stuff, HDMI_VP_STUFF_PR_STUFFING_MASK, - HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE); - - /* data from pixel repeater block */ - vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | - HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; - - clrsetbits_le32(®s->vp_conf, HDMI_VP_CONF_PR_EN_MASK | - HDMI_VP_CONF_BYPASS_SELECT_MASK, vp_conf); - - clrsetbits_le32(®s->vp_stuff, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, - 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET); - - writel(remap_size, ®s->vp_remap); - - vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | - HDMI_VP_CONF_PP_EN_DISABLE | - HDMI_VP_CONF_YCC422_EN_DISABLE; - - clrsetbits_le32(®s->vp_conf, HDMI_VP_CONF_BYPASS_EN_MASK | - HDMI_VP_CONF_PP_EN_ENMASK | HDMI_VP_CONF_YCC422_EN_MASK, - vp_conf); - - clrsetbits_le32(®s->vp_stuff, HDMI_VP_STUFF_PP_STUFFING_MASK | - HDMI_VP_STUFF_YCC422_STUFFING_MASK, - HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | - HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE); - - clrsetbits_le32(®s->vp_conf, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, - output_select); -} - -static inline void hdmi_phy_test_clear(struct rk3288_hdmi *regs, uint bit) -{ - clrsetbits_le32(®s->phy_tst0, HDMI_PHY_TST0_TSTCLR_MASK, - bit << HDMI_PHY_TST0_TSTCLR_OFFSET); -} - -static int hdmi_phy_wait_i2c_done(struct rk3288_hdmi *regs, u32 msec) -{ - ulong start; - u32 val; - - start = get_timer(0); - do { - val = readl(®s->ih_i2cmphy_stat0); - if (val & 0x3) { - writel(val, ®s->ih_i2cmphy_stat0); - return 0; - } - - udelay(100); - } while (get_timer(start) < msec); - - return 1; -} - -static void hdmi_phy_i2c_write(struct rk3288_hdmi *regs, uint data, uint addr) -{ - writel(0xff, ®s->ih_i2cmphy_stat0); - writel(addr, ®s->phy_i2cm_address_addr); - writel((u8)(data >> 8), ®s->phy_i2cm_datao_1_addr); - writel((u8)(data >> 0), ®s->phy_i2cm_datao_0_addr); - writel(HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, - ®s->phy_i2cm_operation_addr); - - hdmi_phy_wait_i2c_done(regs, 1000); -} - -static void hdmi_phy_enable_power(struct rk3288_hdmi *regs, uint enable) -{ - clrsetbits_le32(®s->phy_conf0, HDMI_PHY_CONF0_PDZ_MASK, - enable << HDMI_PHY_CONF0_PDZ_OFFSET); -} - -static void hdmi_phy_enable_tmds(struct rk3288_hdmi *regs, uint enable) -{ - clrsetbits_le32(®s->phy_conf0, HDMI_PHY_CONF0_ENTMDS_MASK, - enable << HDMI_PHY_CONF0_ENTMDS_OFFSET); -} - -static void hdmi_phy_enable_spare(struct rk3288_hdmi *regs, uint enable) -{ - clrsetbits_le32(®s->phy_conf0, HDMI_PHY_CONF0_SPARECTRL_MASK, - enable << HDMI_PHY_CONF0_SPARECTRL_OFFSET); -} - -static void hdmi_phy_gen2_pddq(struct rk3288_hdmi *regs, uint enable) -{ - clrsetbits_le32(®s->phy_conf0, HDMI_PHY_CONF0_GEN2_PDDQ_MASK, - enable << HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET); -} - -static void hdmi_phy_gen2_txpwron(struct rk3288_hdmi *regs, uint enable) -{ - clrsetbits_le32(®s->phy_conf0, - HDMI_PHY_CONF0_GEN2_TXPWRON_MASK, - enable << HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET); -} - -static void hdmi_phy_sel_data_en_pol(struct rk3288_hdmi *regs, uint enable) -{ - clrsetbits_le32(®s->phy_conf0, - HDMI_PHY_CONF0_SELDATAENPOL_MASK, - enable << HDMI_PHY_CONF0_SELDATAENPOL_OFFSET); -} - -static void hdmi_phy_sel_interface_control(struct rk3288_hdmi *regs, - uint enable) -{ - clrsetbits_le32(®s->phy_conf0, HDMI_PHY_CONF0_SELDIPIF_MASK, - enable << HDMI_PHY_CONF0_SELDIPIF_OFFSET); -} - -static int hdmi_phy_configure(struct rk3288_hdmi *regs, u32 mpixelclock) -{ - ulong start; - uint i, val; - - writel(HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, - ®s->mc_flowctrl); - - /* gen2 tx power off */ - hdmi_phy_gen2_txpwron(regs, 0); - - /* gen2 pddq */ - hdmi_phy_gen2_pddq(regs, 1); - - /* phy reset */ - writel(HDMI_MC_PHYRSTZ_DEASSERT, ®s->mc_phyrstz); - writel(HDMI_MC_PHYRSTZ_ASSERT, ®s->mc_phyrstz); - writel(HDMI_MC_HEACPHY_RST_ASSERT, ®s->mc_heacphy_rst); - - hdmi_phy_test_clear(regs, 1); - writel(HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, ®s->phy_i2cm_slave_addr); - hdmi_phy_test_clear(regs, 0); - - /* pll/mpll cfg - always match on final entry */ - for (i = 0; rockchip_mpll_cfg[i].mpixelclock != (~0ul); i++) - if (mpixelclock <= rockchip_mpll_cfg[i].mpixelclock) - break; - - hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].cpce, PHY_OPMODE_PLLCFG); - hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].gmp, PHY_PLLGMPCTRL); - hdmi_phy_i2c_write(regs, rockchip_mpll_cfg[i].curr, PHY_PLLCURRCTRL); - - hdmi_phy_i2c_write(regs, 0x0000, PHY_PLLPHBYCTRL); - hdmi_phy_i2c_write(regs, 0x0006, PHY_PLLCLKBISTPHASE); - - for (i = 0; rockchip_phy_config[i].mpixelclock != (~0ul); i++) - if (mpixelclock <= rockchip_phy_config[i].mpixelclock) - break; - - /* - * resistance term 133ohm cfg - * preemp cgf 0.00 - * tx/ck lvl 10 - */ - hdmi_phy_i2c_write(regs, rockchip_phy_config[i].term, PHY_TXTERM); - hdmi_phy_i2c_write(regs, rockchip_phy_config[i].sym_ctr, - PHY_CKSYMTXCTRL); - hdmi_phy_i2c_write(regs, rockchip_phy_config[i].vlev_ctr, PHY_VLEVCTRL); - - /* remove clk term */ - hdmi_phy_i2c_write(regs, 0x8000, PHY_CKCALCTRL); - - hdmi_phy_enable_power(regs, 1); - - /* toggle tmds enable */ - hdmi_phy_enable_tmds(regs, 0); - hdmi_phy_enable_tmds(regs, 1); - - /* gen2 tx power on */ - hdmi_phy_gen2_txpwron(regs, 1); - hdmi_phy_gen2_pddq(regs, 0); - - hdmi_phy_enable_spare(regs, 1); - - /* wait for phy pll lock */ - start = get_timer(0); - do { - val = readl(®s->phy_stat0); - if (!(val & HDMI_PHY_TX_PHY_LOCK)) - return 0; - - udelay(100); - } while (get_timer(start) < 5); - - return -1; -} - -static int hdmi_phy_init(struct rk3288_hdmi *regs, uint mpixelclock) -{ - int i, ret; - - /* hdmi phy spec says to do the phy initialization sequence twice */ - for (i = 0; i < 2; i++) { - hdmi_phy_sel_data_en_pol(regs, 1); - hdmi_phy_sel_interface_control(regs, 0); - hdmi_phy_enable_tmds(regs, 0); - hdmi_phy_enable_power(regs, 0); - - ret = hdmi_phy_configure(regs, mpixelclock); - if (ret) { - debug("hdmi phy config failure %d\n", ret); - return ret; - } - } - - return 0; -} - -static void hdmi_av_composer(struct rk3288_hdmi *regs, - const struct display_timing *edid) -{ - bool mdataenablepolarity = true; - uint inv_val; - uint hbl; - uint vbl; - - hbl = edid->hback_porch.typ + edid->hfront_porch.typ + - edid->hsync_len.typ; - vbl = edid->vback_porch.typ + edid->vfront_porch.typ + - edid->vsync_len.typ; - - /* set up hdmi_fc_invidconf */ - inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE; - - inv_val |= (edid->flags & DISPLAY_FLAGS_HSYNC_HIGH ? - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : - HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW); - - inv_val |= (edid->flags & DISPLAY_FLAGS_VSYNC_HIGH ? - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : - HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW); - - inv_val |= (mdataenablepolarity ? - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : - HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); - - /* - * TODO(sjg@chromium.org>: Need to check for HDMI / DVI - * inv_val |= (edid->hdmi_monitor_detected ? - * HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : - * HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE); - */ - inv_val |= HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE; - - inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; - - inv_val |= HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; - - writel(inv_val, ®s->fc_invidconf); - - /* set up horizontal active pixel width */ - writel(edid->hactive.typ >> 8, ®s->fc_inhactv1); - writel(edid->hactive.typ, ®s->fc_inhactv0); - - /* set up vertical active lines */ - writel(edid->vactive.typ >> 8, ®s->fc_invactv1); - writel(edid->vactive.typ, ®s->fc_invactv0); - - /* set up horizontal blanking pixel region width */ - writel(hbl >> 8, ®s->fc_inhblank1); - writel(hbl, ®s->fc_inhblank0); - - /* set up vertical blanking pixel region width */ - writel(vbl, ®s->fc_invblank); - - /* set up hsync active edge delay width (in pixel clks) */ - writel(edid->hfront_porch.typ >> 8, ®s->fc_hsyncindelay1); - writel(edid->hfront_porch.typ, ®s->fc_hsyncindelay0); - - /* set up vsync active edge delay (in lines) */ - writel(edid->vfront_porch.typ, ®s->fc_vsyncindelay); - - /* set up hsync active pulse width (in pixel clks) */ - writel(edid->hsync_len.typ >> 8, ®s->fc_hsyncinwidth1); - writel(edid->hsync_len.typ, ®s->fc_hsyncinwidth0); - - /* set up vsync active edge delay (in lines) */ - writel(edid->vsync_len.typ, ®s->fc_vsyncinwidth); -} - -/* hdmi initialization step b.4 */ -static void hdmi_enable_video_path(struct rk3288_hdmi *regs) -{ - uint clkdis; - - /* control period minimum duration */ - writel(12, ®s->fc_ctrldur); - writel(32, ®s->fc_exctrldur); - writel(1, ®s->fc_exctrlspac); - - /* set to fill tmds data channels */ - writel(0x0b, ®s->fc_ch0pream); - writel(0x16, ®s->fc_ch1pream); - writel(0x21, ®s->fc_ch2pream); - - /* enable pixel clock and tmds data path */ - clkdis = 0x7f; - clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; - writel(clkdis, ®s->mc_clkdis); - - clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; - writel(clkdis, ®s->mc_clkdis); - - clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; - writel(clkdis, ®s->mc_clkdis); -} - -/* workaround to clear the overflow condition */ -static void hdmi_clear_overflow(struct rk3288_hdmi *regs) -{ - uint val, count; - - /* tmds software reset */ - writel((u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, ®s->mc_swrstz); - - val = readl(®s->fc_invidconf); - - for (count = 0; count < 4; count++) - writel(val, ®s->fc_invidconf); -} - -static void hdmi_audio_set_format(struct rk3288_hdmi *regs) -{ - writel(HDMI_AUD_CONF0_I2S_SELECT | HDMI_AUD_CONF0_I2S_IN_EN_0, - ®s->aud_conf0); - - - writel(HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE | - HDMI_AUD_CONF1_I2S_WIDTH_16BIT, ®s->aud_conf1); - - writel(0x00, ®s->aud_conf2); -} - -static void hdmi_audio_fifo_reset(struct rk3288_hdmi *regs) -{ - writel((u8)~HDMI_MC_SWRSTZ_II2SSWRST_REQ, ®s->mc_swrstz); - writel(HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST, ®s->aud_conf0); - - writel(0x00, ®s->aud_int); - writel(0x00, ®s->aud_int1); -} - -static void hdmi_init_interrupt(struct rk3288_hdmi *regs) -{ - uint ih_mute; - - /* - * boot up defaults are: - * hdmi_ih_mute = 0x03 (disabled) - * hdmi_ih_mute_* = 0x00 (enabled) - * - * disable top level interrupt bits in hdmi block - */ - ih_mute = readl(®s->ih_mute) | - HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | - HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; - - writel(ih_mute, ®s->ih_mute); - - /* enable i2c master done irq */ - writel(~0x04, ®s->i2cm_int); - - /* enable i2c client nack % arbitration error irq */ - writel(~0x44, ®s->i2cm_ctlint); - - /* enable phy i2cm done irq */ - writel(HDMI_PHY_I2CM_INT_ADDR_DONE_POL, ®s->phy_i2cm_int_addr); - - /* enable phy i2cm nack & arbitration error irq */ - writel(HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | - HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, - ®s->phy_i2cm_ctlint_addr); - - /* enable cable hot plug irq */ - writel((u8)~HDMI_PHY_HPD, ®s->phy_mask0); - - /* clear hotplug interrupts */ - writel(HDMI_IH_PHY_STAT0_HPD, ®s->ih_phy_stat0); -} - -static int hdmi_get_plug_in_status(struct rk3288_hdmi *regs) -{ - uint val = readl(®s->phy_stat0) & HDMI_PHY_HPD; - - return !!val; -} - -static int hdmi_wait_for_hpd(struct rk3288_hdmi *regs) -{ - ulong start; - - start = get_timer(0); - do { - if (hdmi_get_plug_in_status(regs)) - return 0; - udelay(100); - } while (get_timer(start) < 300); - - return -1; -} - -static int hdmi_ddc_wait_i2c_done(struct rk3288_hdmi *regs, int msec) -{ - u32 val; - ulong start; - - start = get_timer(0); - do { - val = readl(®s->ih_i2cm_stat0); - if (val & 0x2) { - writel(val, ®s->ih_i2cm_stat0); - return 0; - } - - udelay(100); - } while (get_timer(start) < msec); - - return 1; -} - -static void hdmi_ddc_reset(struct rk3288_hdmi *regs) -{ - clrbits_le32(®s->i2cm_softrstz, HDMI_I2CM_SOFTRSTZ); -} - -static int hdmi_read_edid(struct rk3288_hdmi *regs, int block, u8 *buff) -{ - int shift = (block % 2) * 0x80; - int edid_read_err = 0; - u32 trytime = 5; - u32 n, j, val; - - /* set ddc i2c clk which devided from ddc_clk to 100khz */ - writel(0x7a, ®s->i2cm_ss_scl_hcnt_0_addr); - writel(0x8d, ®s->i2cm_ss_scl_lcnt_0_addr); - - /* - * TODO(sjg@chromium.org): The above values don't work - these ones - * work better, but generate lots of errors in the data. - */ - writel(0x0d, ®s->i2cm_ss_scl_hcnt_0_addr); - writel(0x0d, ®s->i2cm_ss_scl_lcnt_0_addr); - clrsetbits_le32(®s->i2cm_div, HDMI_I2CM_DIV_FAST_STD_MODE, - HDMI_I2CM_DIV_STD_MODE); - - writel(HDMI_I2CM_SLAVE_DDC_ADDR, ®s->i2cm_slave); - writel(HDMI_I2CM_SEGADDR_DDC, ®s->i2cm_segaddr); - writel(block >> 1, ®s->i2cm_segptr); - - while (trytime--) { - edid_read_err = 0; - - for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) { - writel(shift + 8 * n, ®s->i2c_address); - - if (block == 0) - clrsetbits_le32(®s->i2cm_operation, - HDMI_I2CM_OPT_RD8, - HDMI_I2CM_OPT_RD8); - else - clrsetbits_le32(®s->i2cm_operation, - HDMI_I2CM_OPT_RD8_EXT, - HDMI_I2CM_OPT_RD8_EXT); - - if (hdmi_ddc_wait_i2c_done(regs, 10)) { - hdmi_ddc_reset(regs); - edid_read_err = 1; - break; - } - - for (j = 0; j < 8; j++) { - val = readl(®s->i2cm_buf0 + j); - buff[8 * n + j] = val; - } - } - - if (!edid_read_err) - break; - } - - return edid_read_err; -} - -static const u8 pre_buf[] = { - 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, - 0x04, 0x69, 0xfa, 0x23, 0xc8, 0x28, 0x01, 0x00, - 0x10, 0x17, 0x01, 0x03, 0x80, 0x33, 0x1d, 0x78, - 0x2a, 0xd9, 0x45, 0xa2, 0x55, 0x4d, 0xa0, 0x27, - 0x12, 0x50, 0x54, 0xb7, 0xef, 0x00, 0x71, 0x4f, - 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00, - 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x00, 0x02, 0x3a, - 0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c, - 0x45, 0x00, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, - 0x00, 0x00, 0x00, 0xff, 0x00, 0x44, 0x34, 0x4c, - 0x4d, 0x54, 0x46, 0x30, 0x37, 0x35, 0x39, 0x37, - 0x36, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x32, - 0x4b, 0x18, 0x53, 0x11, 0x00, 0x0a, 0x20, 0x20, - 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc, - 0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x53, - 0x32, 0x33, 0x38, 0x0a, 0x20, 0x20, 0x01, 0xb0, - 0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03, - 0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f, - 0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x17, 0x07, - 0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00, - 0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0, - 0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0xfd, 0x1e, - 0x11, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72, - 0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00, - 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, 0x01, 0x1d, - 0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28, - 0x55, 0x40, 0xfd, 0x1e, 0x11, 0x00, 0x00, 0x1e, - 0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20, - 0x0c, 0x40, 0x55, 0x00, 0xfd, 0x1e, 0x11, 0x00, - 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe9, -}; - static int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size) { struct rk_hdmi_priv *priv = dev_get_priv(dev); - u32 edid_size = HDMI_EDID_BLOCK_SIZE; - int ret; - - if (0) { - edid_size = sizeof(pre_buf); - memcpy(buf, pre_buf, edid_size); - } else { - ret = hdmi_read_edid(priv->regs, 0, buf); - if (ret) { - debug("failed to read edid.\n"); - return -1; - } - if (buf[0x7e] != 0) { - hdmi_read_edid(priv->regs, 1, - buf + HDMI_EDID_BLOCK_SIZE); - edid_size += HDMI_EDID_BLOCK_SIZE; - } - } - - return edid_size; + return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size); } static int rk_hdmi_enable(struct udevice *dev, int panel_bpp, const struct display_timing *edid) { struct rk_hdmi_priv *priv = dev_get_priv(dev); - struct rk3288_hdmi *regs = priv->regs; - int ret; - - debug("hdmi, mode info : clock %d hdis %d vdis %d\n", - edid->pixelclock.typ, edid->hactive.typ, edid->vactive.typ); - hdmi_av_composer(regs, edid); - - ret = hdmi_phy_init(regs, edid->pixelclock.typ); - if (ret) - return ret; - - hdmi_enable_video_path(regs); - - hdmi_audio_fifo_reset(regs); - hdmi_audio_set_format(regs); - hdmi_audio_set_samplerate(regs, edid->pixelclock.typ); - - hdmi_video_packetize(regs); - hdmi_video_sample(regs); - - hdmi_clear_overflow(regs); - - return 0; + return dw_hdmi_enable(&priv->hdmi, edid); } static int rk_hdmi_ofdata_to_platdata(struct udevice *dev) { struct rk_hdmi_priv *priv = dev_get_priv(dev); + struct dw_hdmi *hdmi = &priv->hdmi; + + hdmi->ioaddr = (ulong)dev_get_addr(dev); + hdmi->mpll_cfg = rockchip_mpll_cfg; + hdmi->phy_cfg = rockchip_phy_config; + hdmi->i2c_clk_high = 0x7a; + hdmi->i2c_clk_low = 0x8d; + + /* + * TODO(sjg@chromium.org): The above values don't work - these ones + * work better, but generate lots of errors in the data. + */ + hdmi->i2c_clk_high = 0x0d; + hdmi->i2c_clk_low = 0x0d; + hdmi->reg_io_width = 4; + hdmi->phy_set = dw_hdmi_phy_cfg; - priv->regs = (struct rk3288_hdmi *)dev_get_addr(dev); priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); return 0; @@ -820,6 +109,7 @@ static int rk_hdmi_probe(struct udevice *dev) { struct display_plat *uc_plat = dev_get_uclass_platdata(dev); struct rk_hdmi_priv *priv = dev_get_priv(dev); + struct dw_hdmi *hdmi = &priv->hdmi; struct udevice *reg; struct clk clk; int ret; @@ -863,13 +153,14 @@ static int rk_hdmi_probe(struct udevice *dev) rk_clrsetreg(&priv->grf->soc_con6, 1 << 4, (vop_id == 1) ? (1 << 4) : 0); - ret = hdmi_wait_for_hpd(priv->regs); + ret = dw_hdmi_phy_wait_for_hpd(hdmi); if (ret < 0) { debug("hdmi can not get hpd signal\n"); return -1; } - hdmi_init_interrupt(priv->regs); + dw_hdmi_init(hdmi); + dw_hdmi_phy_init(hdmi); return 0; } diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index aeecb58..bc02f80 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -20,7 +20,6 @@ #include <asm/arch/cru_rk3288.h> #include <asm/arch/grf_rk3288.h> #include <asm/arch/edp_rk3288.h> -#include <asm/arch/hdmi_rk3288.h> #include <asm/arch/vop_rk3288.h> #include <dm/device-internal.h> #include <dm/uclass-internal.h> diff --git a/include/configs/evb_rk3288.h b/include/configs/evb_rk3288.h index 6a068bb..bbd54a1 100644 --- a/include/configs/evb_rk3288.h +++ b/include/configs/evb_rk3288.h @@ -11,7 +11,7 @@ #include <configs/rk3288_common.h> #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_WHITE_ON_BLACK diff --git a/include/configs/fennec_rk3288.h b/include/configs/fennec_rk3288.h index 6a068bb..bbd54a1 100644 --- a/include/configs/fennec_rk3288.h +++ b/include/configs/fennec_rk3288.h @@ -11,7 +11,7 @@ #include <configs/rk3288_common.h> #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_WHITE_ON_BLACK diff --git a/include/configs/miqi_rk3288.h b/include/configs/miqi_rk3288.h new file mode 100644 index 0000000..f686042 --- /dev/null +++ b/include/configs/miqi_rk3288.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include <configs/rk3288_common.h> + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_SYS_WHITE_ON_BLACK + +#endif diff --git a/include/configs/popmetal_rk3288.h b/include/configs/popmetal_rk3288.h index 6a068bb..bbd54a1 100644 --- a/include/configs/popmetal_rk3288.h +++ b/include/configs/popmetal_rk3288.h @@ -11,7 +11,7 @@ #include <configs/rk3288_common.h> #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_WHITE_ON_BLACK diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index d7e96ec..c5e508e 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -18,7 +18,6 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) #define CONFIG_SYS_TIMER_BASE 0x2000e000 /* TIMER3 */ diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 4ba81ac..9d22e0c 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -17,17 +17,17 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_DRIVERS_MISC_SUPPORT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#define COUNTER_FREQUENCY 24000000 + #define CONFIG_SYS_NS16550_MEM32 #define CONFIG_SYS_TEXT_BASE 0x00200000 #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff8effff -#define CONFIG_SPL_TEXT_BASE 0xff8c2008 +#define CONFIG_SPL_TEXT_BASE 0xff8c2000 #define CONFIG_SPL_MAX_SIZE 0x30000 /* BSS setup */ #define CONFIG_SPL_BSS_START_ADDR 0xff8e0000 @@ -52,8 +52,6 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SPI_FLASH -#define CONFIG_SPI #define CONFIG_SF_DEFAULT_SPEED 20000000 #ifndef CONFIG_SPL_BUILD diff --git a/include/configs/rock.h b/include/configs/rock.h new file mode 100644 index 0000000..de5291c --- /dev/null +++ b/include/configs/rock.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include <configs/rk3188_common.h> + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +/* SPL @ 32k for 34k + * u-boot directly after @ 68k for 400k or so + * ENV @ 992k + */ +#define CONFIG_ENV_OFFSET ((1024-32) * 1024) +#else +/* SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) +#endif + +#endif diff --git a/include/configs/tinker_rk3288.h b/include/configs/tinker_rk3288.h index c398e07..5228528 100644 --- a/include/configs/tinker_rk3288.h +++ b/include/configs/tinker_rk3288.h @@ -16,7 +16,7 @@ func(MMC, mmc, 1) #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_DEV 1 #define CONFIG_SYS_WHITE_ON_BLACK diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h new file mode 100644 index 0000000..902abd4 --- /dev/null +++ b/include/dw_hdmi.h @@ -0,0 +1,486 @@ +/* + * Copyright (c) 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DW_HDMI_H +#define _DW_HDMI_H + +#include <edid.h> + +#define HDMI_EDID_BLOCK_SIZE 128 + +/* Identification Registers */ +#define HDMI_DESIGN_ID 0x0000 +#define HDMI_REVISION_ID 0x0001 +#define HDMI_PRODUCT_ID0 0x0002 +#define HDMI_PRODUCT_ID1 0x0003 +#define HDMI_CONFIG0_ID 0x0004 +#define HDMI_CONFIG1_ID 0x0005 +#define HDMI_CONFIG2_ID 0x0006 +#define HDMI_CONFIG3_ID 0x0007 + +/* Interrupt Registers */ +#define HDMI_IH_FC_STAT0 0x0100 +#define HDMI_IH_FC_STAT1 0x0101 +#define HDMI_IH_FC_STAT2 0x0102 +#define HDMI_IH_AS_STAT0 0x0103 +#define HDMI_IH_PHY_STAT0 0x0104 +#define HDMI_IH_I2CM_STAT0 0x0105 +#define HDMI_IH_CEC_STAT0 0x0106 +#define HDMI_IH_VP_STAT0 0x0107 +#define HDMI_IH_I2CMPHY_STAT0 0x0108 +#define HDMI_IH_AHBDMAAUD_STAT0 0x0109 + +#define HDMI_IH_MUTE_FC_STAT0 0x0180 +#define HDMI_IH_MUTE_FC_STAT1 0x0181 +#define HDMI_IH_MUTE_FC_STAT2 0x0182 +#define HDMI_IH_MUTE_AS_STAT0 0x0183 +#define HDMI_IH_MUTE_PHY_STAT0 0x0184 +#define HDMI_IH_MUTE_I2CM_STAT0 0x0185 +#define HDMI_IH_MUTE_CEC_STAT0 0x0186 +#define HDMI_IH_MUTE_VP_STAT0 0x0187 +#define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188 +#define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189 +#define HDMI_IH_MUTE 0x01FF + +/* Video Sample Registers */ +#define HDMI_TX_INVID0 0x0200 +#define HDMI_TX_INSTUFFING 0x0201 +#define HDMI_TX_GYDATA0 0x0202 +#define HDMI_TX_GYDATA1 0x0203 +#define HDMI_TX_RCRDATA0 0x0204 +#define HDMI_TX_RCRDATA1 0x0205 +#define HDMI_TX_BCBDATA0 0x0206 +#define HDMI_TX_BCBDATA1 0x0207 + +/* Video Packetizer Registers */ +#define HDMI_VP_STATUS 0x0800 +#define HDMI_VP_PR_CD 0x0801 +#define HDMI_VP_STUFF 0x0802 +#define HDMI_VP_REMAP 0x0803 +#define HDMI_VP_CONF 0x0804 +#define HDMI_VP_STAT 0x0805 +#define HDMI_VP_INT 0x0806 +#define HDMI_VP_MASK 0x0807 +#define HDMI_VP_POL 0x0808 + +/* Frame Composer Registers */ +#define HDMI_FC_INVIDCONF 0x1000 +#define HDMI_FC_INHACTV0 0x1001 +#define HDMI_FC_INHACTV1 0x1002 +#define HDMI_FC_INHBLANK0 0x1003 +#define HDMI_FC_INHBLANK1 0x1004 +#define HDMI_FC_INVACTV0 0x1005 +#define HDMI_FC_INVACTV1 0x1006 +#define HDMI_FC_INVBLANK 0x1007 +#define HDMI_FC_HSYNCINDELAY0 0x1008 +#define HDMI_FC_HSYNCINDELAY1 0x1009 +#define HDMI_FC_HSYNCINWIDTH0 0x100A +#define HDMI_FC_HSYNCINWIDTH1 0x100B +#define HDMI_FC_VSYNCINDELAY 0x100C +#define HDMI_FC_VSYNCINWIDTH 0x100D +#define HDMI_FC_INFREQ0 0x100E +#define HDMI_FC_INFREQ1 0x100F +#define HDMI_FC_INFREQ2 0x1010 +#define HDMI_FC_CTRLDUR 0x1011 +#define HDMI_FC_EXCTRLDUR 0x1012 +#define HDMI_FC_EXCTRLSPAC 0x1013 +#define HDMI_FC_CH0PREAM 0x1014 +#define HDMI_FC_CH1PREAM 0x1015 +#define HDMI_FC_CH2PREAM 0x1016 +#define HDMI_FC_AVICONF3 0x1017 +#define HDMI_FC_GCP 0x1018 +#define HDMI_FC_AVICONF0 0x1019 +#define HDMI_FC_AVICONF1 0x101A +#define HDMI_FC_AVICONF2 0x101B +#define HDMI_FC_AVIVID 0x101C +#define HDMI_FC_AVIETB0 0x101D +#define HDMI_FC_AVIETB1 0x101E +#define HDMI_FC_AVISBB0 0x101F +#define HDMI_FC_AVISBB1 0x1020 +#define HDMI_FC_AVIELB0 0x1021 +#define HDMI_FC_AVIELB1 0x1022 +#define HDMI_FC_AVISRB0 0x1023 +#define HDMI_FC_AVISRB1 0x1024 +#define HDMI_FC_AUDICONF0 0x1025 +#define HDMI_FC_AUDICONF1 0x1026 +#define HDMI_FC_AUDICONF2 0x1027 +#define HDMI_FC_AUDICONF3 0x1028 +#define HDMI_FC_VSDIEEEID0 0x1029 +#define HDMI_FC_VSDSIZE 0x102A + +/* HDMI Source PHY Registers */ +#define HDMI_PHY_CONF0 0x3000 +#define HDMI_PHY_TST0 0x3001 +#define HDMI_PHY_TST1 0x3002 +#define HDMI_PHY_TST2 0x3003 +#define HDMI_PHY_STAT0 0x3004 +#define HDMI_PHY_INT0 0x3005 +#define HDMI_PHY_MASK0 0x3006 +#define HDMI_PHY_POL0 0x3007 + +/* HDMI Master PHY Registers */ +#define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020 +#define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021 +#define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022 +#define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023 +#define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024 +#define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025 +#define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026 +#define HDMI_PHY_I2CM_INT_ADDR 0x3027 +#define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028 +#define HDMI_PHY_I2CM_DIV_ADDR 0x3029 +#define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a +#define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b +#define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c +#define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d +#define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e +#define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f +#define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030 +#define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031 +#define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032 + +/* Audio Sampler Registers */ +#define HDMI_AUD_CONF0 0x3100 +#define HDMI_AUD_CONF1 0x3101 +#define HDMI_AUD_INT 0x3102 +#define HDMI_AUD_CONF2 0x3103 +#define HDMI_AUD_INT1 0x3104 +#define HDMI_AUD_N1 0x3200 +#define HDMI_AUD_N2 0x3201 +#define HDMI_AUD_N3 0x3202 +#define HDMI_AUD_CTS1 0x3203 +#define HDMI_AUD_CTS2 0x3204 +#define HDMI_AUD_CTS3 0x3205 +#define HDMI_AUD_INPUTCLKFS 0x3206 +#define HDMI_AUD_SPDIFINT 0x3302 +#define HDMI_AUD_CONF0_HBR 0x3400 +#define HDMI_AUD_HBR_STATUS 0x3401 +#define HDMI_AUD_HBR_INT 0x3402 +#define HDMI_AUD_HBR_POL 0x3403 +#define HDMI_AUD_HBR_MASK 0x3404 + +/* Main Controller Registers */ +#define HDMI_MC_SFRDIV 0x4000 +#define HDMI_MC_CLKDIS 0x4001 +#define HDMI_MC_SWRSTZ 0x4002 +#define HDMI_MC_OPCTRL 0x4003 +#define HDMI_MC_FLOWCTRL 0x4004 +#define HDMI_MC_PHYRSTZ 0x4005 +#define HDMI_MC_LOCKONCLOCK 0x4006 +#define HDMI_MC_HEACPHY_RST 0x4007 + +/* I2C Master Registers (E-DDC) */ +#define HDMI_I2CM_SLAVE 0x7E00 +#define HDMI_I2CM_ADDRESS 0x7E01 +#define HDMI_I2CM_DATAO 0x7E02 +#define HDMI_I2CM_DATAI 0x7E03 +#define HDMI_I2CM_OPERATION 0x7E04 +#define HDMI_I2CM_INT 0x7E05 +#define HDMI_I2CM_CTLINT 0x7E06 +#define HDMI_I2CM_DIV 0x7E07 +#define HDMI_I2CM_SEGADDR 0x7E08 +#define HDMI_I2CM_SOFTRSTZ 0x7E09 +#define HDMI_I2CM_SEGPTR 0x7E0A +#define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B +#define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C +#define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D +#define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E +#define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F +#define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10 +#define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11 +#define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12 +#define HDMI_I2CM_BUF0 0x7E20 + +enum { + /* HDMI PHY registers define */ + PHY_OPMODE_PLLCFG = 0x06, + PHY_CKCALCTRL = 0x05, + PHY_CKSYMTXCTRL = 0x09, + PHY_VLEVCTRL = 0x0e, + PHY_PLLCURRCTRL = 0x10, + PHY_PLLPHBYCTRL = 0x13, + PHY_PLLGMPCTRL = 0x15, + PHY_PLLCLKBISTPHASE = 0x17, + PHY_TXTERM = 0x19, + + /* ih_phy_stat0 field values */ + HDMI_IH_PHY_STAT0_HPD = 0x1, + + /* ih_mute field values */ + HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2, + HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1, + + /* tx_invid0 field values */ + HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00, + HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f, + HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0, + + /* tx_instuffing field values */ + HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4, + HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2, + HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1, + + /* vp_pr_cd field values */ + HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0, + HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4, + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f, + HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0, + + /* vp_stuff field values */ + HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20, + HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5, + HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4, + HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4, + HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2, + HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2, + HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1, + HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1, + + /* vp_conf field values */ + HDMI_VP_CONF_BYPASS_EN_MASK = 0x40, + HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40, + HDMI_VP_CONF_PP_EN_ENMASK = 0x20, + HDMI_VP_CONF_PP_EN_DISABLE = 0x00, + HDMI_VP_CONF_PR_EN_MASK = 0x10, + HDMI_VP_CONF_PR_EN_DISABLE = 0x00, + HDMI_VP_CONF_YCC422_EN_MASK = 0x8, + HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0, + HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4, + HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4, + HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3, + HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3, + + /* vp_remap field values */ + HDMI_VP_REMAP_YCC422_16BIT = 0x0, + + /* fc_invidconf field values */ + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80, + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80, + HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40, + HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20, + HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10, + HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00, + HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8, + HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8, + HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2, + HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0, + HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1, + HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1, + HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0, + + + /* fc_aviconf0-fc_aviconf3 field values */ + HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03, + HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00, + HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01, + HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02, + HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40, + HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40, + HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00, + HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c, + HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00, + HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04, + HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08, + HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c, + HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30, + HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10, + HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20, + HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00, + + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a, + HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10, + HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20, + HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0, + HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00, + HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40, + HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80, + HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0, + + HDMI_FC_AVICONF2_SCALING_MASK = 0x03, + HDMI_FC_AVICONF2_SCALING_NONE = 0x00, + HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01, + HDMI_FC_AVICONF2_SCALING_VERT = 0x02, + HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03, + HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c, + HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00, + HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04, + HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30, + HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40, + HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80, + HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00, + HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80, + + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02, + HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03, + HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c, + HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00, + HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04, + + /* fc_gcp field values*/ + HDMI_FC_GCP_SET_AVMUTE = 0x02, + HDMI_FC_GCP_CLEAR_AVMUTE = 0x01, + + /* phy_conf0 field values */ + HDMI_PHY_CONF0_PDZ_MASK = 0x80, + HDMI_PHY_CONF0_PDZ_OFFSET = 7, + HDMI_PHY_CONF0_ENTMDS_MASK = 0x40, + HDMI_PHY_CONF0_ENTMDS_OFFSET = 6, + HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20, + HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5, + HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10, + HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4, + HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8, + HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3, + HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2, + HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1, + HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1, + HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0, + + /* phy_tst0 field values */ + HDMI_PHY_TST0_TSTCLR_MASK = 0x20, + HDMI_PHY_TST0_TSTCLR_OFFSET = 5, + + /* phy_stat0 field values */ + HDMI_PHY_HPD = 0x02, + HDMI_PHY_TX_PHY_LOCK = 0x01, + + /* phy_i2cm_slave_addr field values */ + HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, + + /* phy_i2cm_operation_addr field values */ + HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10, + + /* hdmi_phy_i2cm_int_addr */ + HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08, + + /* hdmi_phy_i2cm_ctlint_addr */ + HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80, + HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08, + + /* aud_conf0 field values */ + HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80, + HDMI_AUD_CONF0_I2S_SELECT = 0x20, + HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01, + HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02, + HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04, + HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08, + + /* aud_conf0 field values */ + HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0, + HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10, + + /* aud_n3 field values */ + HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80, + HDMI_AUD_N3_AUDN19_16_MASK = 0x0f, + + /* aud_cts3 field values */ + HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5, + HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0, + HDMI_AUD_CTS3_N_SHIFT_1 = 0, + HDMI_AUD_CTS3_N_SHIFT_16 = 0x20, + HDMI_AUD_CTS3_N_SHIFT_32 = 0x40, + HDMI_AUD_CTS3_N_SHIFT_64 = 0x60, + HDMI_AUD_CTS3_N_SHIFT_128 = 0x80, + HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0, + HDMI_AUD_CTS3_CTS_MANUAL = 0x10, + HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f, + + /* aud_inputclkfs filed values */ + HDMI_AUD_INPUTCLKFS_128 = 0x0, + + /* mc_clkdis field values */ + HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8, + HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2, + HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1, + + /* mc_swrstz field values */ + HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08, + HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02, + + /* mc_flowctrl field values */ + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1, + HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0, + + /* mc_phyrstz field values */ + HDMI_MC_PHYRSTZ_ASSERT = 0x0, + HDMI_MC_PHYRSTZ_DEASSERT = 0x1, + + /* mc_heacphy_rst field values */ + HDMI_MC_HEACPHY_RST_ASSERT = 0x1, + + /* i2cm filed values */ + HDMI_I2CM_SLAVE_DDC_ADDR = 0x50, + HDMI_I2CM_SEGADDR_DDC = 0x30, + HDMI_I2CM_OP_RD8_EXT = 0x2, + HDMI_I2CM_OP_RD8 = 0x1, + HDMI_I2CM_DIV_FAST_STD_MODE = 0x8, + HDMI_I2CM_DIV_FAST_MODE = 0x8, + HDMI_I2CM_DIV_STD_MODE = 0x0, + HDMI_I2CM_SOFTRSTZ_MASK = 0x1, +}; + +struct hdmi_mpll_config { + u64 mpixelclock; + /* Mode of Operation and PLL Dividers Control Register */ + u32 cpce; + /* PLL Gmp Control Register */ + u32 gmp; + /* PLL Current Control Register */ + u32 curr; +}; + +struct hdmi_phy_config { + u64 mpixelclock; + u32 sym_ctr; /* clock symbol and transmitter control */ + u32 term; /* transmission termination value */ + u32 vlev_ctr; /* voltage level control */ +}; + +struct dw_hdmi { + ulong ioaddr; + const struct hdmi_mpll_config *mpll_cfg; + const struct hdmi_phy_config *phy_cfg; + u8 i2c_clk_high; + u8 i2c_clk_low; + u8 reg_io_width; + + int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock); +}; + +int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock); +int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi); +void dw_hdmi_phy_init(struct dw_hdmi *hdmi); + +int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid); +int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size); +void dw_hdmi_init(struct dw_hdmi *hdmi); + +#endif diff --git a/lib/Kconfig b/lib/Kconfig index 65c0157..5115d04 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -52,6 +52,15 @@ config LIB_RAND help This library provides pseudo-random number generator functions. +config SPL_TINY_MEMSET + bool "Use a very small memset() in SPL" + help + The faster memset() is the arch-specific one (if available) enabled + by CONFIG_USE_ARCH_MEMSET. If that is not enabled, we can still get + better performance by writing a word at a time. But in very + size-constrained envrionments even this may be too big. Enable this + option to reduce code size slightly at the cost of some speed. + source lib/dhry/Kconfig source lib/rsa/Kconfig diff --git a/lib/string.c b/lib/string.c index 67d5f6a..c1a28c1 100644 --- a/lib/string.c +++ b/lib/string.c @@ -437,8 +437,10 @@ char *strswab(const char *s) void * memset(void * s,int c,size_t count) { unsigned long *sl = (unsigned long *) s; - unsigned long cl = 0; char *s8; + +#if !CONFIG_IS_ENABLED(TINY_MEMSET) + unsigned long cl = 0; int i; /* do it one word at a time (32 bits or 64 bits) while possible */ @@ -452,7 +454,7 @@ void * memset(void * s,int c,size_t count) count -= sizeof(*sl); } } - /* fill 8 bits at a time */ +#endif /* fill 8 bits at a time */ s8 = (char *)sl; while (count--) *s8++ = c; diff --git a/tools/rkcommon.c b/tools/rkcommon.c index 6595e02..6cdb749 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -41,25 +41,37 @@ struct header0_info { }; /** + * struct header1_info + */ +struct header1_info { + uint32_t magic; +}; + +/** * struct spl_info - spl info for each chip * * @imagename: Image name(passed by "mkimage -n") * @spl_hdr: Boot ROM requires a 4-bytes spl header * @spl_size: Spl size(include extra 4-bytes spl header) * @spl_rc4: RC4 encode the SPL binary (same key as header) + * @spl_boot0: A new-style (ARM_SOC_BOOT0_HOOK) image that should + * have the boot magic (e.g. 'RK33') written to its first + * word. */ + struct spl_info { const char *imagename; const char *spl_hdr; const uint32_t spl_size; const bool spl_rc4; + const bool spl_boot0; }; static struct spl_info spl_infos[] = { - { "rk3036", "RK30", 0x1000, false }, - { "rk3188", "RK31", 0x8000 - 0x800, true }, - { "rk3288", "RK32", 0x8000, false }, - { "rk3399", "RK33", 0x20000, false }, + { "rk3036", "RK30", 0x1000, false, false }, + { "rk3188", "RK31", 0x8000 - 0x800, true, false }, + { "rk3288", "RK32", 0x8000, false, false }, + { "rk3399", "RK33", 0x20000, false, true }, }; static unsigned char rc4_key[16] = { @@ -106,6 +118,7 @@ const char *rkcommon_get_spl_hdr(struct image_tool_params *params) return info->spl_hdr; } + int rkcommon_get_spl_size(struct image_tool_params *params) { struct spl_info *info = rkcommon_get_spl_info(params->imagename); @@ -126,16 +139,22 @@ bool rkcommon_need_rc4_spl(struct image_tool_params *params) return info->spl_rc4; } -int rkcommon_set_header(void *buf, uint file_size, - struct image_tool_params *params) +bool rkcommon_spl_is_boot0(struct image_tool_params *params) { - struct header0_info *hdr; + struct spl_info *info = rkcommon_get_spl_info(params->imagename); - if (file_size > rkcommon_get_spl_size(params)) - return -ENOSPC; + /* + * info would not be NULL, because of we checked params before. + */ + return info->spl_boot0; +} + +static void rkcommon_set_header0(void *buf, uint file_size, + struct image_tool_params *params) +{ + struct header0_info *hdr = buf; - memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE); - hdr = (struct header0_info *)buf; + memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE); hdr->signature = RK_SIGNATURE; hdr->disable_rc4 = !rkcommon_need_rc4_spl(params); hdr->init_offset = RK_INIT_OFFSET; @@ -145,6 +164,24 @@ int rkcommon_set_header(void *buf, uint file_size, hdr->init_boot_size = hdr->init_size + RK_MAX_BOOT_SIZE / RK_BLK_SIZE; rc4_encode(buf, RK_BLK_SIZE, rc4_key); +} + +int rkcommon_set_header(void *buf, uint file_size, + struct image_tool_params *params) +{ + struct header1_info *hdr = buf + RK_SPL_HDR_START; + + if (file_size > rkcommon_get_spl_size(params)) + return -ENOSPC; + + rkcommon_set_header0(buf, file_size, params); + + /* Set up the SPL name and add the AArch64 'nop' padding, if needed */ + memcpy(&hdr->magic, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE); + + if (rkcommon_need_rc4_spl(params)) + rkcommon_rc4_encode_spl(buf, RK_SPL_HDR_START, + params->file_size - RK_SPL_HDR_START); return 0; } @@ -161,3 +198,34 @@ void rkcommon_rc4_encode_spl(void *buf, unsigned int offset, unsigned int size) remaining -= step; } } + +void rkcommon_vrec_header(struct image_tool_params *params, + struct image_type_params *tparams) +{ + /* + * The SPL image looks as follows: + * + * 0x0 header0 (see rkcommon.c) + * 0x800 spl_name ('RK30', ..., 'RK33') + * 0x804 first instruction to be executed + * (image start for AArch32, 'nop' for AArch64)) + * 0x808 second instruction to be executed + * (image start for AArch64) + * + * For AArch64 (ARMv8) payloads, we receive an input file that + * needs to start on an 8-byte boundary (natural alignment), so + * we need to put a NOP at 0x804. + * + * Depending on this, the header is either 0x804 or 0x808 bytes + * in length. + */ + if (rkcommon_spl_is_boot0(params)) + tparams->header_size = RK_SPL_HDR_START; + else + tparams->header_size = RK_SPL_HDR_START + 4; + + /* Allocate, clear and install the header */ + tparams->hdr = malloc(tparams->header_size); + memset(tparams->hdr, 0, tparams->header_size); + tparams->header_size = tparams->header_size; +} diff --git a/tools/rkcommon.h b/tools/rkcommon.h index b4f6f32..cc161a6 100644 --- a/tools/rkcommon.h +++ b/tools/rkcommon.h @@ -77,4 +77,14 @@ bool rkcommon_need_rc4_spl(struct image_tool_params *params); */ void rkcommon_rc4_encode_spl(void *buf, unsigned int offset, unsigned int size); +/** + * rkcommon_vrec_header() - allocate memory for the header + * + * @params: Pointer to the tool params structure + * @tparams: Pointer tot the image type structure (for setting + * the header and header_size) + */ +void rkcommon_vrec_header(struct image_tool_params *params, + struct image_type_params *tparams); + #endif diff --git a/tools/rksd.c b/tools/rksd.c index ff2233f..ac8a67d 100644 --- a/tools/rksd.c +++ b/tools/rksd.c @@ -13,8 +13,6 @@ #include "mkimage.h" #include "rkcommon.h" -static char dummy_hdr[RK_IMAGE_HEADER_LEN]; - static int rksd_verify_header(unsigned char *buf, int size, struct image_tool_params *params) { @@ -38,13 +36,6 @@ static void rksd_set_header(void *buf, struct stat *sbuf, int ifd, printf("Warning: SPL image is too large (size %#x) and will not boot\n", size); } - - memcpy(buf + RK_SPL_HDR_START, rkcommon_get_spl_hdr(params), - RK_SPL_HDR_SIZE); - - if (rkcommon_need_rc4_spl(params)) - rkcommon_rc4_encode_spl(buf, RK_SPL_START - 4, - params->file_size - RK_SPL_START + 4); } static int rksd_extract_subimage(void *buf, struct image_tool_params *params) @@ -66,10 +57,12 @@ static int rksd_vrec_header(struct image_tool_params *params, { int pad_size; + rkcommon_vrec_header(params, tparams); + pad_size = RK_SPL_HDR_START + rkcommon_get_spl_size(params); debug("pad_size %x\n", pad_size); - return pad_size - params->file_size; + return pad_size - params->file_size - tparams->header_size; } /* @@ -78,8 +71,8 @@ static int rksd_vrec_header(struct image_tool_params *params, U_BOOT_IMAGE_TYPE( rksd, "Rockchip SD Boot Image support", - RK_IMAGE_HEADER_LEN, - dummy_hdr, + 0, + NULL, rkcommon_check_params, rksd_verify_header, rksd_print_header, diff --git a/tools/rkspi.c b/tools/rkspi.c index 0271d2e..d2d3fdd 100644 --- a/tools/rkspi.c +++ b/tools/rkspi.c @@ -17,8 +17,6 @@ enum { RKSPI_SECT_LEN = RK_BLK_SIZE * 4, }; -static char dummy_hdr[RK_IMAGE_HEADER_LEN]; - static int rkspi_verify_header(unsigned char *buf, int size, struct image_tool_params *params) { @@ -45,13 +43,6 @@ static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd, size); } - memcpy(buf + RK_SPL_HDR_START, rkcommon_get_spl_hdr(params), - RK_SPL_HDR_SIZE); - - if (rkcommon_need_rc4_spl(params)) - rkcommon_rc4_encode_spl(buf, RK_SPL_START - 4, - params->file_size - RK_SPL_START + 4); - /* * Spread the image out so we only use the first 2KB of each 4KB * region. This is a feature of the SPI format required by the Rockchip @@ -86,6 +77,8 @@ static int rkspi_vrec_header(struct image_tool_params *params, { int pad_size; + rkcommon_vrec_header(params, tparams); + pad_size = (rkcommon_get_spl_size(params) + 0x7ff) / 0x800 * 0x800; params->orig_file_size = pad_size; @@ -94,7 +87,7 @@ static int rkspi_vrec_header(struct image_tool_params *params, pad_size += RK_SPL_HDR_START; debug("pad_size %x\n", pad_size); - return pad_size - params->file_size; + return pad_size - params->file_size - tparams->header_size; } /* @@ -103,8 +96,8 @@ static int rkspi_vrec_header(struct image_tool_params *params, U_BOOT_IMAGE_TYPE( rkspi, "Rockchip SPI Boot Image support", - RK_IMAGE_HEADER_LEN, - dummy_hdr, + 0, + NULL, rkcommon_check_params, rkspi_verify_header, rkspi_print_header, |