diff options
| -rw-r--r-- | drivers/spi/cadence_qspi.c | 4 | ||||
| -rw-r--r-- | drivers/spi/cadence_qspi.h | 3 | ||||
| -rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 7 |
3 files changed, 5 insertions, 9 deletions
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 1051afb..55192d6 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -170,14 +170,12 @@ static int cadence_spi_probe(struct udevice *bus) static int cadence_spi_set_mode(struct udevice *bus, uint mode) { struct cadence_spi_priv *priv = dev_get_priv(bus); - unsigned int clk_pol = (mode & SPI_CPOL) ? 1 : 0; - unsigned int clk_pha = (mode & SPI_CPHA) ? 1 : 0; /* Disable QSPI */ cadence_qspi_apb_controller_disable(priv->regbase); /* Set SPI mode */ - cadence_qspi_apb_set_clk_mode(priv->regbase, clk_pol, clk_pha); + cadence_qspi_apb_set_clk_mode(priv->regbase, mode); /* Enable QSPI */ cadence_qspi_apb_controller_enable(priv->regbase); diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index a849f7b..d1927a4 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -63,8 +63,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, void cadence_qspi_apb_chipselect(void *reg_base, unsigned int chip_select, unsigned int decoder_enable); -void cadence_qspi_apb_set_clk_mode(void *reg_base_addr, - unsigned int clk_pol, unsigned int clk_pha); +void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode); void cadence_qspi_apb_config_baudrate_div(void *reg_base, unsigned int ref_clk_hz, unsigned int sclk_hz); void cadence_qspi_apb_delay(void *reg_base, diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 634a857..e81d678 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -294,8 +294,7 @@ void cadence_qspi_apb_config_baudrate_div(void *reg_base, return; } -void cadence_qspi_apb_set_clk_mode(void *reg_base, - unsigned int clk_pol, unsigned int clk_pha) +void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode) { unsigned int reg; @@ -303,9 +302,9 @@ void cadence_qspi_apb_set_clk_mode(void *reg_base, reg = readl(reg_base + CQSPI_REG_CONFIG); reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA); - if (clk_pol) + if (mode & SPI_CPOL) reg |= CQSPI_REG_CONFIG_CLK_POL; - if (clk_pha) + if (mode & SPI_CPHA) reg |= CQSPI_REG_CONFIG_CLK_PHA; writel(reg, reg_base + CQSPI_REG_CONFIG); |