diff options
869 files changed, 27318 insertions, 12098 deletions
diff --git a/.checkpatch.conf b/.checkpatch.conf index 977db9e..d88af57 100644 --- a/.checkpatch.conf +++ b/.checkpatch.conf @@ -12,3 +12,9 @@ # For min/max --ignore MINMAX + +# enable more tests +--strict + +# Not Linux, so we don't recommend usleep_range() over udelay() +--ignore USLEEP_RANGE @@ -25,10 +25,13 @@ # /MLO +/SPL /System.map /u-boot /u-boot.hex /u-boot.imx +/u-boot-with-spl.imx +/u-boot-with-nand-spl.imx /u-boot.map /u-boot.srec /u-boot.ldr diff --git a/MAINTAINERS b/MAINTAINERS index 0f19078..bbab5fe 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -150,9 +150,6 @@ Wolfgang Denk <wd@denx.de> P3G4 MPC7410 - PCIPPC2 MPC750 - PCIPPC6 MPC750 - Phil Edworthy <phil.edworthy@renesas.com> rsk7264 SH7264 @@ -234,6 +231,7 @@ Wolfgang Grandegger <wg@denx.de> Anatolij Gustschin <agust@denx.de> + ac14xx MPC5121e O2D MPC5200 O2D300 MPC5200 O2DNT2 MPC5200 @@ -397,6 +395,7 @@ Ricardo Ribalda <ricardo.ribalda@uam.es> Stefan Roese <sr@denx.de> a3m071 MPC5200 + a4m2k MPC5200 P3M7448 MPC7448 @@ -690,6 +689,10 @@ Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net> dns325 ARM926EJS (Kirkwood SoC) +Lauri Hintsala <lauri.hintsala@bluegiga.com> + + apx4devkit i.MX28 + Vaibhav Hiremath <hvaibhav@ti.com> am3517_evm ARM ARMV7 (AM35x SoC) @@ -808,10 +811,6 @@ Linus Walleij <linus.walleij@linaro.org> integratorap various integratorcp various -Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com> - - apx4devkit i.MX28 - Luka Perkov <luka@openwrt.org> ib62x0 ARM926EJS @@ -835,6 +834,10 @@ Stelian Pop <stelian@popies.net> at91sam9263ek ARM926EJS (AT91SAM9263 SoC) at91sam9rlek ARM926EJS (AT91SAM9RL SoC) +Matt Porter <mporter@ti.com> + + ti814x_evm ARM ARMV7 (TI814x Soc) + Dave Purdy <david.c.purdy@gmail.com> pogo_e02 ARM926EJS (Kirkwood SoC) @@ -912,6 +915,10 @@ Matt Sealey <matt@genesi-usa.com> Bo Shen <voice.shen@atmel.com> at91sam9x5ek ARM926EJS (AT91SAM9G15,G25,G35,X25,X35 SoC) +Rajeshwari Shinde <rajeshwari.s@samsung.com> + + snow ARM ARMV7 (EXYNOS5250 SoC) + Michal Simek <monstr@monstr.eu> zynq ARM ARMV7 (Zynq SoC) @@ -1023,10 +1030,6 @@ Vladimir Zapolskiy <vz@mleia.com> devkit3250 lpc32xx -Zhong Hongbo <bocui107@gmail.com> - - SMDK6400 ARM1176 (S3C6400 SoC) - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Tetsuyuki Kobayashi <koba@kmckk.co.jp> @@ -104,9 +104,9 @@ while true ; do -s|--soc) # echo "Option SoC: argument \`$2'" if [ "$opt_s" ] ; then - opt_s="${opt_s%)} || \$6 == \"$2\")" + opt_s="${opt_s%)} || \$6 == \"$2\" || \$6 ~ /$2/)" else - opt_s="(\$6 == \"$2\")" + opt_s="(\$6 == \"$2\" || \$6 ~ /$2/)" fi SELECTED='y' shift 2 ;; @@ -664,7 +664,7 @@ build_target() { export BUILD_DIR="${output_dir}" target_arch=$(get_target_arch ${target}) - eval cross_toolchain=\$CROSS_COMPILE_${target_arch^^} + eval cross_toolchain=\$CROSS_COMPILE_`echo $target_arch | tr '[:lower:]' '[:upper:]'` if [ "${cross_toolchain}" ] ; then MAKE="make CROSS_COMPILE=${cross_toolchain}" elif [ "${CROSS_COMPILE}" ] ; then @@ -802,8 +802,20 @@ build_targets() { #----------------------------------------------------------------------- kill_children() { - local pgid=`ps -p $$ --no-headers -o "%r" | tr -d ' '` - local children=`pgrep -g $pgid | grep -v $$ | grep -v $pgid` + local OS=$(uname -s) + local children="" + case "${OS}" in + "Darwin") + # Mac OS X is known to have BSD style ps + local pgid=$(ps -p $$ -o pgid | sed -e "/PGID/d") + children=$(ps -g $pgid -o pid | sed -e "/PID\|$$\|$pgid/d") + ;; + *) + # everything else tries the GNU style + local pgid=$(ps -p $$ --no-headers -o "%r" | tr -d ' ') + children=$(pgrep -g $pgid | sed -e "/$$\|$pgid/d") + ;; + esac kill $children 2> /dev/null wait $children 2> /dev/null @@ -24,7 +24,7 @@ VERSION = 2013 PATCHLEVEL = 04 SUBLEVEL = -EXTRAVERSION = -rc1 +EXTRAVERSION = -rc2 ifneq "$(SUBLEVEL)" "" U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else @@ -46,12 +46,7 @@ HOSTARCH := $(shell uname -m | \ HOSTOS := $(shell uname -s | tr '[:upper:]' '[:lower:]' | \ sed -e 's/\(cygwin\).*/cygwin/') -# Set shell to bash if possible, otherwise fall back to sh -SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ - else if [ -x /bin/bash ]; then echo /bin/bash; \ - else echo sh; fi; fi) - -export HOSTARCH HOSTOS SHELL +export HOSTARCH HOSTOS # Deal with colliding definitions from tcsh etc. VENDOR= @@ -273,6 +268,7 @@ LIBS-y += disk/libdisk.o LIBS-y += drivers/bios_emulator/libatibiosemu.o LIBS-y += drivers/block/libblock.o LIBS-$(CONFIG_BOOTCOUNT_LIMIT) += drivers/bootcount/libbootcount.o +LIBS-y += drivers/crypto/libcrypto.o LIBS-y += drivers/dma/libdma.o LIBS-y += drivers/fpga/libfpga.o LIBS-y += drivers/gpio/libgpio.o @@ -331,7 +327,7 @@ LIBS-y += api/libapi.o LIBS-y += post/libpost.o LIBS-y += test/libtest.o -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif @@ -406,8 +402,10 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin -ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET)) ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin +ifneq ($(CONFIG_SPL_TARGET),) +ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET)) +endif # enable combined SPL/u-boot/dtb rules for tegra ifneq ($(CONFIG_TEGRA),) @@ -485,12 +483,19 @@ $(obj)u-boot.dis: $(obj)u-boot $(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(or $(CONFIG_SPL_PAD_TO),0) \ - -O binary $(obj)spl/u-boot-spl \ - $(obj)spl/u-boot-spl-pad.bin + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \ + -I binary -O binary $< $(obj)spl/u-boot-spl-pad.bin cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@ rm $(obj)spl/u-boot-spl-pad.bin +$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin + $(MAKE) -C $(SRCTREE)/arch/arm/imx-common \ + $(OBJTREE)/u-boot-with-spl.imx + +$(obj)u-boot-with-nand-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin + $(MAKE) -C $(SRCTREE)/arch/arm/imx-common \ + $(OBJTREE)/u-boot-with-nand-spl.imx + $(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \ -e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl @@ -781,23 +786,6 @@ lcname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\L\1/') ucname = $(shell echo $(1) | sed -e 's/\(.*\)_config/\U\1/') ######################################################################### -## ARM1176 Systems -######################################################################### -smdk6400_noUSB_config \ -smdk6400_config : unconfig - @mkdir -p $(obj)include $(obj)board/samsung/smdk6400 - @mkdir -p $(obj)nand_spl/board/samsung/smdk6400 - @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h - @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk - @if [ -z "$(findstring smdk6400_noUSB_config,$@)" ]; then \ - echo "RAM_TEXT = 0x57e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\ - else \ - echo "RAM_TEXT = 0xc7e00000" >> $(obj)board/samsung/smdk6400/config.tmp;\ - fi - @$(MKCONFIG) smdk6400 arm arm1176 smdk6400 samsung s3c64xx - @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk - -######################################################################### ######################################################################### clean: @@ -855,6 +843,8 @@ clobber: tidy @rm -f $(obj)u-boot.kwb @rm -f $(obj)u-boot.pbl @rm -f $(obj)u-boot.imx + @rm -f $(obj)u-boot-with-spl.imx + @rm -f $(obj)u-boot-with-nand-spl.imx @rm -f $(obj)u-boot.ubl @rm -f $(obj)u-boot.ais @rm -f $(obj)u-boot.dtb @@ -485,6 +485,7 @@ The following options need to be configured: Thumb2 this flag will result in Thumb2 code generated by GCC. + CONFIG_ARM_ERRATA_716044 CONFIG_ARM_ERRATA_742230 CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 @@ -495,6 +496,13 @@ The following options need to be configured: exists, unlike the similar options in the Linux kernel. Do not set these options unless they apply! +- CPU timer options: + CONFIG_SYS_HZ + + The frequency of the timer returned by get_timer(). + get_timer() must operate in milliseconds and this CONFIG + option must be set to 1000. + - Linux Kernel Interface: CONFIG_CLOCKS_IN_MHZ @@ -626,14 +634,6 @@ The following options need to be configured: boot loader that has already initialized the UART. Define this variable to flush the UART at init time. - CONFIG_SYS_NS16550_BROKEN_TEMT - - 16550 UART set the Transmitter Empty (TEMT) Bit when all output - has finished and the transmitter is totally empty. U-Boot waits - for this bit to be set to initialize the serial console. On some - broken platforms this bit is not set in SPL making U-Boot to - hang while waiting for TEMT. Define this option to avoid it. - - Console Interface: Depending on board, define exactly one serial port @@ -870,7 +870,8 @@ The following options need to be configured: (requires CONFIG_CMD_MEMORY and CONFIG_MD5) CONFIG_CMD_MEMINFO * Display detailed memory information CONFIG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base, - loop, loopw, mtest + loop, loopw + CONFIG_CMD_MEMTEST mtest CONFIG_CMD_MISC Misc functions like sleep etc CONFIG_CMD_MMC * MMC memory mapped support CONFIG_CMD_MII * MII utility commands @@ -1335,6 +1336,29 @@ The following options need to be configured: CONFIG_SH_MMCIF_CLK Define the clock frequency for MMCIF +- USB Device Firmware Update (DFU) class support: + CONFIG_DFU_FUNCTION + This enables the USB portion of the DFU USB class + + CONFIG_CMD_DFU + This enables the command "dfu" which is used to have + U-Boot create a DFU class device via USB. This command + requires that the "dfu_alt_info" environment variable be + set and define the alt settings to expose to the host. + + CONFIG_DFU_MMC + This enables support for exposing (e)MMC devices via DFU. + + CONFIG_DFU_NAND + This enables support for exposing NAND devices via DFU. + + CONFIG_SYS_DFU_MAX_FILE_SIZE + When updating files rather than the raw storage device, + we use a static buffer to copy the file into and then write + the buffer once we've been given the whole file. Define + this to the maximum filesize (in bytes) for the buffer. + Default is 4 MiB if undefined. + - Journaling Flash filesystem support: CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE, CONFIG_JFFS2_NAND_DEV @@ -1936,15 +1960,15 @@ CBFS (Coreboot Filesystem) support I2C_READ - Code that returns TRUE if the I2C data line is high, - FALSE if it is low. + Code that returns true if the I2C data line is high, + false if it is low. eg: #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) I2C_SDA(bit) - If <bit> is TRUE, sets the I2C data line high. If it - is FALSE, it clears it (low). + If <bit> is true, sets the I2C data line high. If it + is false, it clears it (low). eg: #define I2C_SDA(bit) \ if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ @@ -1952,8 +1976,8 @@ CBFS (Coreboot Filesystem) support I2C_SCL(bit) - If <bit> is TRUE, sets the I2C clock line high. If it - is FALSE, it clears it (low). + If <bit> is true, sets the I2C clock line high. If it + is false, it clears it (low). eg: #define I2C_SCL(bit) \ if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ @@ -2774,6 +2798,32 @@ FIT uImage format: Adds the MTD partitioning infrastructure from the Linux kernel. Needed for UBI support. +- UBI support + CONFIG_CMD_UBI + + Adds commands for interacting with MTD partitions formatted + with the UBI flash translation layer + + Requires also defining CONFIG_RBTREE + + CONFIG_UBI_SILENCE_MSG + + Make the verbose messages from UBI stop printing. This leaves + warnings and errors enabled. + +- UBIFS support + CONFIG_CMD_UBIFS + + Adds commands for interacting with UBI volumes formatted as + UBIFS. UBIFS is read-only in u-boot. + + Requires UBI support as well as CONFIG_LZO + + CONFIG_UBIFS_SILENCE_MSG + + Make the verbose messages from UBIFS stop printing. This leaves + warnings and errors enabled. + - SPL framework CONFIG_SPL Enable building of SPL globally. @@ -2914,8 +2964,11 @@ FIT uImage format: Support for lib/libgeneric.o in SPL binary CONFIG_SPL_PAD_TO - Linker address to which the SPL should be padded before - appending the SPL payload. + Image offset to which the SPL should be padded before appending + the SPL payload. By default, this is defined as + CONFIG_SPL_MAX_SIZE, or 0 if CONFIG_SPL_MAX_SIZE is undefined. + CONFIG_SPL_PAD_TO must be either 0, meaning to append the SPL + payload without any padding, or >= CONFIG_SPL_MAX_SIZE. CONFIG_SPL_TARGET Final target image containing SPL and payload. Some SPLs @@ -3240,6 +3293,23 @@ Configuration Settings: If defined, don't allow the -f switch to env set override variable access flags. +- CONFIG_SYS_GENERIC_BOARD + This selects the architecture-generic board system instead of the + architecture-specific board files. It is intended to move boards + to this new framework over time. Defining this will disable the + arch/foo/lib/board.c file and use common/board_f.c and + common/board_r.c instead. To use this option your architecture + must support it (i.e. must define __HAVE_ARCH_GENERIC_BOARD in + its config.mk file). If you find problems enabling this option on + your board please report the problem and send patches! + +- CONFIG_SYS_SYM_OFFSETS + This is set by architectures that use offsets for link symbols + instead of absolute values. So bss_start is obtained using an + offset _bss_start_ofs from CONFIG_SYS_TEXT_BASE, rather than + directly. You should not need to touch this setting. + + The following definitions that deal with the placement and management of environment data (variable area); in general, we support the following configurations: @@ -3473,6 +3543,33 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface. environment. If redundant environment is used, it will be copied to CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE. +- CONFIG_ENV_IS_IN_UBI: + + Define this if you have an UBI volume that you want to use for the + environment. This has the benefit of wear-leveling the environment + accesses, which is important on NAND. + + - CONFIG_ENV_UBI_PART: + + Define this to a string that is the mtd partition containing the UBI. + + - CONFIG_ENV_UBI_VOLUME: + + Define this to the name of the volume that you want to store the + environment in. + + - CONFIG_ENV_UBI_VOLUME_REDUND: + + Define this to the name of another volume to store a second copy of + the environment in. This will enable redundant environments in UBI. + It is assumed that both volumes are in the same MTD partition. + + - CONFIG_UBI_SILENCE_MSG + - CONFIG_UBIFS_SILENCE_MSG + + You will probably want to define these to avoid a really noisy system + when storing the env in UBI. + - CONFIG_SYS_SPI_INIT_OFFSET Defines offset to the initial SPI buffer area in DPRAM. The @@ -3744,9 +3841,13 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_SRIOn_MEM_SIZE: Size of SRIO port 'n' memory region -- CONFIG_SYS_NDFC_16 - Defined to tell the NDFC that the NAND chip is using a - 16 bit bus. +- CONFIG_SYS_NAND_BUSWIDTH_16BIT + Defined to tell the NAND controller that the NAND chip is using + a 16 bit bus. + Not all NAND drivers use this symbol. + Example of drivers that use it: + - drivers/mtd/nand/ndfc.c + - drivers/mtd/nand/mxc_nand.c - CONFIG_SYS_NDFC_EBC0_CFG Sets the EBC0_CFG register for the NDFC. If not defined @@ -3860,6 +3961,10 @@ Low Level (hardware related) configuration options: If defined, the x86 reset vector code is included. This is not needed when U-Boot is running from Coreboot. +- CONFIG_SYS_MPUCLK + Defines the MPU clock speed (in MHz). + + NOTE : currently only supported on AM335x platforms. Freescale QE/FMAN Firmware Support: ----------------------------------- diff --git a/api/api_display.c b/api/api_display.c index 6439170..c167db7 100644 --- a/api/api_display.c +++ b/api/api_display.c @@ -45,8 +45,8 @@ int display_get_info(int type, struct display_info *di) case DISPLAY_TYPE_LCD: di->pixel_width = panel_info.vl_col; di->pixel_height = panel_info.vl_row; - di->screen_rows = CONSOLE_ROWS; - di->screen_cols = CONSOLE_COLS; + di->screen_rows = lcd_get_screen_rows(); + di->screen_cols = lcd_get_screen_columns(); break; #endif } diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 24b9d7c..461899e 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -24,13 +24,16 @@ CROSS_COMPILE ?= arm-linux- ifndef CONFIG_STANDALONE_LOAD_ADDR -ifeq ($(SOC),omap3) +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) CONFIG_STANDALONE_LOAD_ADDR = 0x80300000 else CONFIG_STANDALONE_LOAD_ADDR = 0xc100000 endif endif +# Support generic board on ARM +__HAVE_ARCH_GENERIC_BOARD := y + PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ # Choose between ARM/Thumb instruction sets @@ -84,9 +87,7 @@ endif endif # needed for relocation -ifndef CONFIG_NAND_SPL LDFLAGS_u-boot += -pie -endif # # FIXME: binutils versions < 2.22 have a bug in the assembler where diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk index 9092d91..797d122 100644 --- a/arch/arm/cpu/arm1136/config.mk +++ b/arch/arm/cpu/arm1136/config.mk @@ -31,6 +31,13 @@ PLATFORM_CPPFLAGS += -march=armv5 # ========================================================================= PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) + +ifneq ($(CONFIG_IMX_CONFIG),) +ifdef CONFIG_SPL ifdef CONFIG_SPL_BUILD ALL-y += $(OBJTREE)/SPL endif +else +ALL-y += $(obj)u-boot.imx +endif +endif diff --git a/arch/arm/cpu/arm1136/omap24xx/timer.c b/arch/arm/cpu/arm1136/omap24xx/timer.c index 53015cb..3b6666b 100644 --- a/arch/arm/cpu/arm1136/omap24xx/timer.c +++ b/arch/arm/cpu/arm1136/omap24xx/timer.c @@ -31,13 +31,16 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/bits.h> #include <asm/arch/omap2420.h> +#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV)) #define TIMER_LOAD_VAL 0 /* macro to read the 32 bit timer */ -#define READ_TIMER (*((volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR))) +#define READ_TIMER readl(CONFIG_SYS_TIMERBASE+TCRR) \ + / (TIMER_CLOCK / CONFIG_SYS_HZ) DECLARE_GLOBAL_DATA_PTR; @@ -99,7 +102,8 @@ ulong get_timer_masked (void) gd->arch.tbl += (now - gd->arch.lastinc); } else { /* we have rollover of incrementer */ - gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now; + gd->arch.tbl += ((0xFFFFFFFF / (TIMER_CLOCK / CONFIG_SYS_HZ)) + - gd->arch.lastinc) + now; } gd->arch.lastinc = now; return gd->arch.tbl; diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index a067b8a..ccea2d5 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -88,7 +88,11 @@ _end_vect: .globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. @@ -100,13 +104,13 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start -.global _image_copy_end_ofs +.globl _image_copy_end_ofs _image_copy_end_ofs: - .word __image_copy_end - _start + .word __image_copy_end - _start .globl _bss_end_ofs _bss_end_ofs: - .word __bss_end__ - _start + .word __bss_end - _start .globl _end_ofs _end_ofs: @@ -170,29 +174,24 @@ next: /*------------------------------------------------------------------------------*/ /* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. + * void relocate_code(addr_moni) * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start - cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ + subs r9, r6, r0 /* r9 <- relocation offset */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r1!, {r9-r10} /* copy to target address [r1] */ + ldmia r0!, {r10-r11} /* copy from source address [r0] */ + stmia r1!, {r10-r11} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop @@ -201,7 +200,6 @@ copy_loop: * fix .rel.dyn relocations */ ldr r0, _TEXT_BASE /* r0 <- Text base */ - sub r9, r6, r0 /* r9 <- relocation offset */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ add r10, r10, r0 /* r10 <- sym table in FLASH */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ @@ -235,8 +233,6 @@ fixnext: add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 blo fixloop - bx lr - #endif relocate_done: @@ -392,8 +388,9 @@ cpu_init_crit: str r0, [r13] @ save R0's value. ldr r0, IRQ_STACK_START_IN @ get data regions start str lr, [r0] @ save caller lr in position 0 of saved stack - mrs r0, spsr @ get the spsr + mrs lr, spsr @ get the spsr str lr, [r0, #4] @ save spsr in position 1 of saved stack + ldr lr, [r0] @ restore lr ldr r0, [r13] @ restore r0 add r13, r13, #4 @ pop stack entry .endm diff --git a/arch/arm/cpu/arm1136/u-boot-spl.lds b/arch/arm/cpu/arm1136/u-boot-spl.lds index a0462ab..8296e5d 100644 --- a/arch/arm/cpu/arm1136/u-boot-spl.lds +++ b/arch/arm/cpu/arm1136/u-boot-spl.lds @@ -38,7 +38,7 @@ SECTIONS .text : { __start = .; - arch/arm/cpu/arm1136/start.o (.text) + arch/arm/cpu/arm1136/start.o (.text*) *(.text*) } >.sram @@ -57,6 +57,6 @@ SECTIONS __bss_start = .; *(.bss*) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } >.sdram } diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/cpu/arm1176/bcm2835/Makefile index 95da6a8..135de42 100644 --- a/arch/arm/cpu/arm1176/bcm2835/Makefile +++ b/arch/arm/cpu/arm1176/bcm2835/Makefile @@ -17,7 +17,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -COBJS := init.o reset.o timer.o +COBJS := init.o reset.o timer.o mbox.o SRCS := $(SOBJS:.o=.c) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/arch/arm/cpu/arm1176/bcm2835/mbox.c b/arch/arm/cpu/arm1176/bcm2835/mbox.c new file mode 100644 index 0000000..fd65e33 --- /dev/null +++ b/arch/arm/cpu/arm1176/bcm2835/mbox.c @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2012 Stephen Warren + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mbox.h> + +#define TIMEOUT (100 * 1000) /* 100mS in uS */ + +int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv) +{ + struct bcm2835_mbox_regs *regs = + (struct bcm2835_mbox_regs *)BCM2835_MBOX_PHYSADDR; + ulong endtime = get_timer(0) + TIMEOUT; + u32 val; + + debug("time: %lu timeout: %lu\n", get_timer(0), endtime); + + if (send & BCM2835_CHAN_MASK) { + printf("mbox: Illegal mbox data 0x%08x\n", send); + return -1; + } + + /* Drain any stale responses */ + + for (;;) { + val = readl(®s->status); + if (val & BCM2835_MBOX_STATUS_RD_EMPTY) + break; + if (get_timer(0) >= endtime) { + printf("mbox: Timeout draining stale responses\n"); + return -1; + } + val = readl(®s->read); + } + + /* Wait for space to send */ + + for (;;) { + val = readl(®s->status); + if (!(val & BCM2835_MBOX_STATUS_WR_FULL)) + break; + if (get_timer(0) >= endtime) { + printf("mbox: Timeout waiting for send space\n"); + return -1; + } + } + + /* Send the request */ + + val = BCM2835_MBOX_PACK(chan, send); + debug("mbox: TX raw: 0x%08x\n", val); + writel(val, ®s->write); + + /* Wait for the response */ + + for (;;) { + val = readl(®s->status); + if (!(val & BCM2835_MBOX_STATUS_RD_EMPTY)) + break; + if (get_timer(0) >= endtime) { + printf("mbox: Timeout waiting for response\n"); + return -1; + } + } + + /* Read the response */ + + val = readl(®s->read); + debug("mbox: RX raw: 0x%08x\n", val); + + /* Validate the response */ + + if (BCM2835_MBOX_UNPACK_CHAN(val) != chan) { + printf("mbox: Response channel mismatch\n"); + return -1; + } + + *recv = BCM2835_MBOX_UNPACK_DATA(val); + + return 0; +} + +#ifdef DEBUG +void dump_buf(struct bcm2835_mbox_hdr *buffer) +{ + u32 *p; + u32 words; + int i; + + p = (u32 *)buffer; + words = buffer->buf_size / 4; + for (i = 0; i < words; i++) + printf(" 0x%04x: 0x%08x\n", i * 4, p[i]); +} +#endif + +int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer) +{ + int ret; + u32 rbuffer; + struct bcm2835_mbox_tag_hdr *tag; + int tag_index; + +#ifdef DEBUG + printf("mbox: TX buffer\n"); + dump_buf(buffer); +#endif + + ret = bcm2835_mbox_call_raw(chan, (u32)buffer, &rbuffer); + if (ret) + return ret; + if (rbuffer != (u32)buffer) { + printf("mbox: Response buffer mismatch\n"); + return -1; + } + +#ifdef DEBUG + printf("mbox: RX buffer\n"); + dump_buf(buffer); +#endif + + /* Validate overall response status */ + + if (buffer->code != BCM2835_MBOX_RESP_CODE_SUCCESS) { + printf("mbox: Header response code invalid\n"); + return -1; + } + + /* Validate each tag's response status */ + + tag = (void *)(buffer + 1); + tag_index = 0; + while (tag->tag) { + if (!(tag->val_len & BCM2835_MBOX_TAG_VAL_LEN_RESPONSE)) { + printf("mbox: Tag %d missing val_len response bit\n", + tag_index); + return -1; + } + /* + * Clear the reponse bit so clients can just look right at the + * length field without extra processing + */ + tag->val_len &= ~BCM2835_MBOX_TAG_VAL_LEN_RESPONSE; + tag = (void *)(((u8 *)tag) + sizeof(*tag) + tag->val_buf_size); + tag_index++; + } + + return 0; +} diff --git a/arch/arm/cpu/arm1176/bcm2835/timer.c b/arch/arm/cpu/arm1176/bcm2835/timer.c index d232d7e..2edd671 100644 --- a/arch/arm/cpu/arm1176/bcm2835/timer.c +++ b/arch/arm/cpu/arm1176/bcm2835/timer.c @@ -23,7 +23,7 @@ int timer_init(void) return 0; } -ulong get_timer(ulong base) +ulong get_timer_us(ulong base) { struct bcm2835_timer_regs *regs = (struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR; @@ -31,6 +31,14 @@ ulong get_timer(ulong base) return readl(®s->clo) - base; } +ulong get_timer(ulong base) +{ + ulong us = get_timer_us(0); + us /= (1000000 / CONFIG_SYS_HZ); + us -= base; + return us; +} + unsigned long long get_ticks(void) { return get_timer(0); @@ -46,10 +54,10 @@ void __udelay(unsigned long usec) ulong endtime; signed long diff; - endtime = get_timer(0) + usec; + endtime = get_timer_us(0) + usec; do { - ulong now = get_timer(0); + ulong now = get_timer_us(0); diff = endtime - now; } while (diff >= 0); } diff --git a/arch/arm/cpu/arm1176/s3c64xx/config.mk b/arch/arm/cpu/arm1176/s3c64xx/config.mk deleted file mode 100644 index 222d352..0000000 --- a/arch/arm/cpu/arm1176/s3c64xx/config.mk +++ /dev/null @@ -1,34 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float - -# Make ARMv5 to allow more compilers to work, even though its v6. -PLATFORM_CPPFLAGS += -march=armv5t -# ========================================================================= -# -# Supply options according to compiler version -# -# ========================================================================= -PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\ - $(call cc-option,-malignment-traps,)) -PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S b/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S deleted file mode 100644 index df88cba..0000000 --- a/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400 - * - * Copyright (C) 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/s3c6400.h> - - .globl mem_ctrl_asm_init -mem_ctrl_asm_init: - /* DMC1 base address 0x7e001000 */ - ldr r0, =ELFIN_DMC1_BASE - - ldr r1, =0x4 - str r1, [r0, #INDEX_DMC_MEMC_CMD] - - ldr r1, =DMC_DDR_REFRESH_PRD - str r1, [r0, #INDEX_DMC_REFRESH_PRD] - - ldr r1, =DMC_DDR_CAS_LATENCY - str r1, [r0, #INDEX_DMC_CAS_LATENCY] - - ldr r1, =DMC_DDR_t_DQSS - str r1, [r0, #INDEX_DMC_T_DQSS] - - ldr r1, =DMC_DDR_t_MRD - str r1, [r0, #INDEX_DMC_T_MRD] - - ldr r1, =DMC_DDR_t_RAS - str r1, [r0, #INDEX_DMC_T_RAS] - - ldr r1, =DMC_DDR_t_RC - str r1, [r0, #INDEX_DMC_T_RC] - - ldr r1, =DMC_DDR_t_RCD - ldr r2, =DMC_DDR_schedule_RCD - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RCD] - - ldr r1, =DMC_DDR_t_RFC - ldr r2, =DMC_DDR_schedule_RFC - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RFC] - - ldr r1, =DMC_DDR_t_RP - ldr r2, =DMC_DDR_schedule_RP - orr r1, r1, r2 - str r1, [r0, #INDEX_DMC_T_RP] - - ldr r1, =DMC_DDR_t_RRD - str r1, [r0, #INDEX_DMC_T_RRD] - - ldr r1, =DMC_DDR_t_WR - str r1, [r0, #INDEX_DMC_T_WR] - - ldr r1, =DMC_DDR_t_WTR - str r1, [r0, #INDEX_DMC_T_WTR] - - ldr r1, =DMC_DDR_t_XP - str r1, [r0, #INDEX_DMC_T_XP] - - ldr r1, =DMC_DDR_t_XSR - str r1, [r0, #INDEX_DMC_T_XSR] - - ldr r1, =DMC_DDR_t_ESR - str r1, [r0, #INDEX_DMC_T_ESR] - - ldr r1, =DMC1_MEM_CFG - str r1, [r0, #INDEX_DMC_MEMORY_CFG] - - ldr r1, =DMC1_MEM_CFG2 - str r1, [r0, #INDEX_DMC_MEMORY_CFG2] - - ldr r1, =DMC1_CHIP0_CFG - str r1, [r0, #INDEX_DMC_CHIP_0_CFG] - - ldr r1, =DMC_DDR_32_CFG - str r1, [r0, #INDEX_DMC_USER_CONFIG] - - /* DMC0 DDR Chip 0 configuration direct command reg */ - ldr r1, =DMC_NOP0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Precharge All */ - ldr r1, =DMC_PA0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Auto Refresh 2 time */ - ldr r1, =DMC_AR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* MRS */ - ldr r1, =DMC_mDDR_EMR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Mode Reg */ - ldr r1, =DMC_mDDR_MR0 - str r1, [r0, #INDEX_DMC_DIRECT_CMD] - - /* Enable DMC1 */ - mov r1, #0x0 - str r1, [r0, #INDEX_DMC_MEMC_CMD] - -check_dmc1_ready: - ldr r1, [r0, #INDEX_DMC_MEMC_STATUS] - mov r2, #0x3 - and r1, r1, r2 - cmp r1, #0x1 - bne check_dmc1_ready - nop - - mov pc, lr - - .ltorg diff --git a/arch/arm/cpu/arm1176/s3c64xx/speed.c b/arch/arm/cpu/arm1176/s3c64xx/speed.c deleted file mode 100644 index 11962ac..0000000 --- a/arch/arm/cpu/arm1176/s3c64xx/speed.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, d.mueller@elsoft.ch - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This code should work for both the S3C2400 and the S3C2410 - * as they seem to have the same PLL and clock machinery inside. - * The different address mapping is handled by the s3c24xx.h files below. - */ - -#include <common.h> -#include <asm/arch/s3c6400.h> - -#define APLL 0 -#define MPLL 1 -#define EPLL 2 - -/* ------------------------------------------------------------------------- */ -/* - * NOTE: This describes the proper use of this file. - * - * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL. - * - * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of - * the specified bus in HZ. - */ -/* ------------------------------------------------------------------------- */ - -static ulong get_PLLCLK(int pllreg) -{ - ulong r, m, p, s; - - switch (pllreg) { - case APLL: - r = APLL_CON_REG; - break; - case MPLL: - r = MPLL_CON_REG; - break; - case EPLL: - r = EPLL_CON0_REG; - break; - default: - hang(); - } - - m = (r >> 16) & 0x3ff; - p = (r >> 8) & 0x3f; - s = r & 0x7; - - return m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s))); -} - -/* return ARMCORE frequency */ -ulong get_ARMCLK(void) -{ - ulong div; - - div = CLK_DIV0_REG; - - return get_PLLCLK(APLL) / ((div & 0x7) + 1); -} - -/* return FCLK frequency */ -ulong get_FCLK(void) -{ - return get_PLLCLK(APLL); -} - -/* return HCLK frequency */ -ulong get_HCLK(void) -{ - ulong fclk; - - uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1; - uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1; - - /* - * Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on - * s3c6400 and is always 0, and it is indeed running in ASYNC mode - */ - if (OTHERS_REG & 0x80) - fclk = get_FCLK(); /* SYNC Mode */ - else - fclk = get_PLLCLK(MPLL); /* ASYNC Mode */ - - return fclk / (hclk_div * hclkx2_div); -} - -/* return PCLK frequency */ -ulong get_PCLK(void) -{ - ulong fclk; - uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1; - uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1; - - if (OTHERS_REG & 0x80) - fclk = get_FCLK(); /* SYNC Mode */ - else - fclk = get_PLLCLK(MPLL); /* ASYNC Mode */ - - return fclk / (hclkx2_div * pre_div); -} - -/* return UCLK frequency */ -ulong get_UCLK(void) -{ - return get_PLLCLK(EPLL); -} - -int print_cpuinfo(void) -{ - printf("\nCPU: S3C6400@%luMHz\n", get_ARMCLK() / 1000000); - printf(" Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ", - get_FCLK() / 1000000, get_HCLK() / 1000000, - get_PCLK() / 1000000); - - if (OTHERS_REG & 0x80) - printf("(SYNC Mode) \n"); - else - printf("(ASYNC Mode) \n"); - return 0; -} diff --git a/arch/arm/cpu/arm1176/s3c64xx/timer.c b/arch/arm/cpu/arm1176/s3c64xx/timer.c deleted file mode 100644 index f16a37b..0000000 --- a/arch/arm/cpu/arm1176/s3c64xx/timer.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments <www.ti.com> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. <philippe.robin@arm.com> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/proc-armv/ptrace.h> -#include <asm/arch/s3c6400.h> -#include <div64.h> - -static ulong timer_load_val; - -#define PRESCALER 167 - -static s3c64xx_timers *s3c64xx_get_base_timers(void) -{ - return (s3c64xx_timers *)ELFIN_TIMER_BASE; -} - -/* macro to read the 16 bit timer */ -static inline ulong read_timer(void) -{ - s3c64xx_timers *const timers = s3c64xx_get_base_timers(); - - return timers->TCNTO4; -} - -/* Internal tick units */ -/* Last decremneter snapshot */ -static unsigned long lastdec; -/* Monotonic incrementing timer */ -static unsigned long long timestamp; - -int timer_init(void) -{ - s3c64xx_timers *const timers = s3c64xx_get_base_timers(); - - /* use PWM Timer 4 because it has no output */ - /* - * We use the following scheme for the timer: - * Prescaler is hard fixed at 167, divider at 1/4. - * This gives at PCLK frequency 66MHz approx. 10us ticks - * The timer is set to wrap after 100s, at 66MHz this obviously - * happens after 10,000,000 ticks. A long variable can thus - * keep values up to 40,000s, i.e., 11 hours. This should be - * enough for most uses:-) Possible optimizations: select a - * binary-friendly frequency, e.g., 1ms / 128. Also calculate - * the prescaler automatically for other PCLK frequencies. - */ - timers->TCFG0 = PRESCALER << 8; - if (timer_load_val == 0) { - timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */ - timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000; - } - - /* load value for 10 ms timeout */ - lastdec = timers->TCNTB4 = timer_load_val; - /* auto load, manual update of Timer 4 */ - timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | - TCON_4_UPDATE; - - /* auto load, start Timer 4 */ - timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON; - timestamp = 0; - - return 0; -} - -/* - * timer without interrupts - */ - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - ulong now = read_timer(); - - if (lastdec >= now) { - /* normal mode */ - timestamp += lastdec - now; - } else { - /* we have an overflow ... */ - timestamp += lastdec + timer_load_val - now; - } - lastdec = now; - - return timestamp; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - /* We overrun in 100s */ - return (ulong)(timer_load_val / 100); -} - -ulong get_timer_masked(void) -{ - unsigned long long res = get_ticks(); - do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ))); - return res; -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = (usec + 9) / 10; - tmp = get_ticks() + tmo; /* get current timestamp */ - - while (get_ticks() < tmp)/* loop till event */ - /*NOP*/; -} diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 40df4b1..f20da8e 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -33,11 +33,8 @@ #include <asm-offsets.h> #include <config.h> #include <version.h> -#ifdef CONFIG_ENABLE_MMU -#include <asm/proc/domain.h> -#endif -#if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE) +#ifndef CONFIG_SYS_PHY_UBOOT_BASE #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE #endif @@ -51,7 +48,7 @@ .globl _start _start: b reset -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -98,15 +95,11 @@ _end_vect: .globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE - -/* - * Below variable is very important because we use MMU in U-Boot. - * Without it, we cannot run code correctly before MMU is ON. - * by scsuh. - */ -_TEXT_PHY_BASE: - .word CONFIG_SYS_PHY_UBOOT_BASE +#endif /* * These are defined in the board-specific linker script. @@ -119,9 +112,13 @@ _TEXT_PHY_BASE: _bss_start_ofs: .word __bss_start - _start +.globl _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: - .word __bss_end__ - _start + .word __bss_end - _start .globl _end_ofs _end_ofs: @@ -164,7 +161,7 @@ cpu_init_crit: * When booting from NAND - it has definitely been a reset, so, no need * to flush caches and disable the MMU */ -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD /* * flush v4 I/D caches */ @@ -229,29 +226,24 @@ skip_tcmdisable: /*------------------------------------------------------------------------------*/ /* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. + * void relocate_code(addr_moni) * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start - cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ + subs r9, r6, r0 /* r9 <- relocation offset */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r1!, {r9-r10} /* copy to target address [r1] */ + ldmia r0!, {r10-r11} /* copy from source address [r0] */ + stmia r1!, {r10-r11} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop @@ -260,7 +252,6 @@ copy_loop: * fix .rel.dyn relocations */ ldr r0, _TEXT_BASE /* r0 <- Text base */ - sub r9, r6, r0 /* r9 <- relocation offset */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ add r10, r10, r0 /* r10 <- sym table in FLASH */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ @@ -296,44 +287,6 @@ fixnext: blo fixloop #endif -#ifdef CONFIG_ENABLE_MMU -enable_mmu: - /* enable domain access */ - ldr r5, =0x0000ffff - mcr p15, 0, r5, c3, c0, 0 /* load domain access register */ - - /* Set the TTB register */ - ldr r0, _mmu_table_base - ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE - ldr r2, =0xfff00000 - bic r0, r0, r2 - orr r1, r0, r1 - mcr p15, 0, r1, c2, c0, 0 - - /* Enable the MMU */ - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #1 /* Set CR_M to enable MMU */ - - /* Prepare to enable the MMU */ - adr r1, skip_hw_init - and r1, r1, #0x3fc - ldr r2, _TEXT_BASE - ldr r3, =0xfff00000 - and r2, r2, r3 - orr r2, r2, r1 - b mmu_enable - - .align 5 - /* Run in a single cache-line */ -mmu_enable: - - mcr p15, 0, r0, c1, c0, 0 - nop - nop - mov pc, r2 -skip_hw_init: -#endif - relocate_done: bx lr @@ -345,52 +298,12 @@ _rel_dyn_end_ofs: _dynsym_start_ofs: .word __dynsym_start - _start -#ifdef CONFIG_ENABLE_MMU -_mmu_table_base: - .word mmu_table -#endif - .globl c_runtime_cpu_setup c_runtime_cpu_setup: mov pc, lr -#ifndef CONFIG_NAND_SPL -/* - * we assume that cache operation is done before. (eg. cleanup_before_linux()) - * actually, we don't need to do anything about cache if not use d-cache in - * U-Boot. So, in this function we clean only MMU. by scsuh - * - * void theLastJump(void *kernel, int arch_num, uint boot_params); - */ -#ifdef CONFIG_ENABLE_MMU - .globl theLastJump -theLastJump: - mov r9, r0 - ldr r3, =0xfff00000 - ldr r4, _TEXT_PHY_BASE - adr r5, phy_last_jump - bic r5, r5, r3 - orr r5, r5, r4 - mov pc, r5 -phy_last_jump: - /* - * disable MMU stuff - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */ - bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */ - orr r0, r0, #0x00000002 /* set bit 2 (A) Align */ - orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */ - mcr p15, 0, r0, c1, c0, 0 - - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - mov r0, #0 - mov pc, r9 -#endif - - +#ifndef CONFIG_SPL_BUILD /* ************************************************************************* * @@ -480,9 +393,11 @@ phy_last_jump: /* save caller lr in position 0 of saved stack */ str lr, [r0] /* get the spsr */ - mrs r0, spsr + mrs lr, spsr /* save spsr in position 1 of saved stack */ str lr, [r0, #4] + /* restore lr */ + ldr lr, [r0] /* restore r0 */ ldr r0, [r13] /* pop stack entry */ @@ -533,4 +448,4 @@ fiq: get_bad_stack bad_save_user_regs bl do_fiq -#endif /* CONFIG_NAND_SPL */ +#endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index 771d386..9facc7e 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -85,7 +85,7 @@ _pad: .word 0x12345678 /* now 16*4=64 */ .globl _TEXT_BASE _TEXT_BASE: -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) .word CONFIG_SPL_TEXT_BASE #else .word CONFIG_SYS_TEXT_BASE @@ -101,9 +101,13 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start +.globl _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: - .word __bss_end__ - _start + .word __bss_end - _start .globl _end_ofs _end_ofs: @@ -152,29 +156,24 @@ reset: /*------------------------------------------------------------------------------*/ /* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. + * void relocate_code(addr_moni) * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start - cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ + subs r9, r6, r0 /* r9 <- relocation offset */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r1!, {r9-r10} /* copy to target address [r1] */ + ldmia r0!, {r10-r11} /* copy from source address [r0] */ + stmia r1!, {r10-r11} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop @@ -183,7 +182,6 @@ copy_loop: * fix .rel.dyn relocations */ ldr r0, _TEXT_BASE /* r0 <- Text base */ - sub r9, r6, r0 /* r9 <- relocation offset */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ add r10, r10, r0 /* r10 <- sym table in FLASH */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds index c19285d..cf55bf7 100644 --- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds +++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds @@ -31,18 +31,18 @@ SECTIONS . = ALIGN(4); .text : { - arch/arm/cpu/arm920t/start.o (.text) + arch/arm/cpu/arm920t/start.o (.text*) /* the EP93xx expects to find the pattern 'CRUS' at 0x1000 */ . = 0x1000; LONG(0x53555243) - *(.text) + *(.text*) } . = ALIGN(4); - .rodata : { *(.rodata) } + .rodata : { *(.rodata*) } . = ALIGN(4); - .data : { *(.data) } + .data : { *(.data*) } . = ALIGN(4); .got : { *(.got) } @@ -55,9 +55,12 @@ SECTIONS } . = ALIGN(4); + + __image_copy_end = .; + __bss_start = .; - .bss : { *(.bss) } - __bss_end__ = .; + .bss : { *(.bss*) } + __bss_end = .; _end = .; } diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index 511d21d..6250025 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -73,7 +73,11 @@ _fiq: .word fiq .globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. @@ -85,9 +89,13 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start +.globl _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: - .word __bss_end__ - _start + .word __bss_end - _start .globl _end_ofs _end_ofs: @@ -187,29 +195,24 @@ copyex: /*------------------------------------------------------------------------------*/ /* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. + * void relocate_code(addr_moni) * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start - cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ + subs r9, r6, r0 /* r9 <- relocation offset */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r1!, {r9-r10} /* copy to target address [r1] */ + ldmia r0!, {r10-r11} /* copy from source address [r0] */ + stmia r1!, {r10-r11} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop @@ -218,7 +221,6 @@ copy_loop: * fix .rel.dyn relocations */ ldr r0, _TEXT_BASE /* r0 <- Text base */ - sub r9, r6, r0 /* r9 <- relocation offset */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ add r10, r10, r0 /* r10 <- sym table in FLASH */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index e8d6d71..021e241 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -79,7 +79,11 @@ _fiq: .word fiq .globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. @@ -91,9 +95,13 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start +.globl _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: - .word __bss_end__ - _start + .word __bss_end - _start .globl _end_ofs _end_ofs: @@ -177,29 +185,24 @@ poll1: /*------------------------------------------------------------------------------*/ /* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. + * void relocate_code(addr_moni) * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start - cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ + subs r9, r6, r0 /* r9 <- relocation offset */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r1!, {r9-r10} /* copy to target address [r1] */ + ldmia r0!, {r10-r11} /* copy from source address [r0] */ + stmia r1!, {r10-r11} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop @@ -208,7 +211,6 @@ copy_loop: * fix .rel.dyn relocations */ ldr r0, _TEXT_BASE /* r0 <- Text base */ - sub r9, r6, r0 /* r9 <- relocation offset */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ add r10, r10, r0 /* r10 <- sym table in FLASH */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index 6a3a1bb..f0e31d1 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -33,7 +33,11 @@ PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-mali PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) ifneq ($(CONFIG_IMX_CONFIG),) - +ifdef CONFIG_SPL +ifdef CONFIG_SPL_BUILD +ALL-y += $(OBJTREE)/SPL +endif +else ALL-y += $(obj)u-boot.imx - +endif endif diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c b/arch/arm/cpu/arm926ejs/davinci/spl.c index 714fa92..ca8a412 100644 --- a/arch/arm/cpu/arm926ejs/davinci/spl.c +++ b/arch/arm/cpu/arm926ejs/davinci/spl.c @@ -64,7 +64,7 @@ void board_init_f(ulong dummy) #endif /* Third, we clear the BSS. */ - memset(__bss_start, 0, __bss_end__ - __bss_start); + memset(__bss_start, 0, __bss_end - __bss_start); /* Finally, setup gd and move to the next step. */ gd = &gdata; diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 7ccd337..bf54423 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -119,7 +119,11 @@ fiq: .globl _TEXT_BASE _TEXT_BASE: +#ifdef CONFIG_SPL_TEXT_BASE + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. @@ -133,7 +137,7 @@ _bss_start_ofs: .globl _bss_end_ofs _bss_end_ofs: - .word __bss_end__ - _start + .word __bss_end - _start .globl _end_ofs _end_ofs: diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index 0f3222c..673c725 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -37,8 +37,8 @@ SECTIONS . = ALIGN(4); .text : { - arch/arm/cpu/arm926ejs/mxs/start.o (.text) - *(.text) + arch/arm/cpu/arm926ejs/mxs/start.o (.text*) + *(.text*) } . = ALIGN(4); @@ -46,7 +46,7 @@ SECTIONS . = ALIGN(4); .data : { - *(.data) + *(.data*) } . = ALIGN(4); @@ -67,7 +67,7 @@ SECTIONS __bss_start = .; *(.bss*) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } _end = .; diff --git a/arch/arm/cpu/arm926ejs/omap/timer.c b/arch/arm/cpu/arm926ejs/omap/timer.c index 34ec7b2..16530b0 100644 --- a/arch/arm/cpu/arm926ejs/omap/timer.c +++ b/arch/arm/cpu/arm926ejs/omap/timer.c @@ -36,11 +36,14 @@ */ #include <common.h> +#include <asm/io.h> -#define TIMER_LOAD_VAL 0xffffffff +#define TIMER_CLOCK (CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV)) +#define TIMER_LOAD_VAL 0xffffffff /* macro to read the 32 bit timer */ -#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8)) +#define READ_TIMER readl(CONFIG_SYS_TIMERBASE+8) \ + / (TIMER_CLOCK / CONFIG_SYS_HZ) DECLARE_GLOBAL_DATA_PTR; @@ -114,7 +117,8 @@ ulong get_timer_masked (void) * (TLV-now) amount of time after passing though -1 * nts = new "advancing time stamp"...it could also roll and cause problems. */ - timestamp += lastdec + TIMER_LOAD_VAL - now; + timestamp += lastdec + (TIMER_LOAD_VAL / (TIMER_CLOCK / + CONFIG_SYS_HZ)) - now; } lastdec = now; @@ -160,8 +164,5 @@ unsigned long long get_ticks(void) */ ulong get_tbclk (void) { - ulong tbclk; - - tbclk = CONFIG_SYS_HZ; - return tbclk; + return CONFIG_SYS_HZ; } diff --git a/arch/arm/cpu/arm926ejs/spear/spear600.c b/arch/arm/cpu/arm926ejs/spear/spear600.c index ff52131..9f0c1d1 100644 --- a/arch/arm/cpu/arm926ejs/spear/spear600.c +++ b/arch/arm/cpu/arm926ejs/spear/spear600.c @@ -28,9 +28,6 @@ #include <asm/arch/spr_misc.h> #include <asm/arch/spr_defs.h> -#define FALSE 0 -#define TRUE (!FALSE) - static void sel_1v8(void) { struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; @@ -133,8 +130,8 @@ void soc_init(void) /* * xxx_boot_selected: * - * return TRUE if the particular booting option is selected - * return FALSE otherwise + * return true if the particular booting option is selected + * return false otherwise */ static u32 read_bootstrap(void) { @@ -150,18 +147,18 @@ int snor_boot_selected(void) /* Check whether SNOR boot is selected */ if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) == CONFIG_SPEAR_ONLYSNORBOOT) - return TRUE; + return true; if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == CONFIG_SPEAR_NORNAND8BOOT) - return TRUE; + return true; if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == CONFIG_SPEAR_NORNAND16BOOT) - return TRUE; + return true; } - return FALSE; + return false; } int nand_boot_selected(void) @@ -172,20 +169,20 @@ int nand_boot_selected(void) /* Check whether NAND boot is selected */ if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == CONFIG_SPEAR_NORNAND8BOOT) - return TRUE; + return true; if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) == CONFIG_SPEAR_NORNAND16BOOT) - return TRUE; + return true; } - return FALSE; + return false; } int pnor_boot_selected(void) { /* Parallel NOR boot is not selected in any SPEAr600 revision */ - return FALSE; + return false; } int usb_boot_selected(void) @@ -195,39 +192,39 @@ int usb_boot_selected(void) if (USB_BOOT_SUPPORTED) { /* Check whether USB boot is selected */ if (!(bootstrap & CONFIG_SPEAR_USBBOOT)) - return TRUE; + return true; } - return FALSE; + return false; } int tftp_boot_selected(void) { /* TFTP boot is not selected in any SPEAr600 revision */ - return FALSE; + return false; } int uart_boot_selected(void) { /* UART boot is not selected in any SPEAr600 revision */ - return FALSE; + return false; } int spi_boot_selected(void) { /* SPI boot is not selected in any SPEAr600 revision */ - return FALSE; + return false; } int i2c_boot_selected(void) { /* I2C boot is not selected in any SPEAr600 revision */ - return FALSE; + return false; } int mmc_boot_selected(void) { - return FALSE; + return false; } void plat_late_init(void) diff --git a/arch/arm/cpu/arm926ejs/spear/spl_boot.c b/arch/arm/cpu/arm926ejs/spear/spl_boot.c index f2f9a49..3e2953c 100644 --- a/arch/arm/cpu/arm926ejs/spear/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/spear/spl_boot.c @@ -120,7 +120,7 @@ u32 spl_boot(void) /* * All the supported booting devices are listed here. Each of * the booting type supported by the platform would define the - * macro xxx_BOOT_SUPPORTED to TRUE. + * macro xxx_BOOT_SUPPORTED to true. */ if (SNOR_BOOT_SUPPORTED && snor_boot_selected()) { diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds index 0af3e0a..967a135 100644 --- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -37,8 +37,8 @@ SECTIONS . = ALIGN(4); .text : { - arch/arm/cpu/arm926ejs/spear/start.o (.text) - *(.text) + arch/arm/cpu/arm926ejs/spear/start.o (.text*) + *(.text*) } . = ALIGN(4); @@ -46,7 +46,7 @@ SECTIONS . = ALIGN(4); .data : { - *(.data) + *(.data*) } . = ALIGN(4); @@ -67,7 +67,7 @@ SECTIONS __bss_start = .; *(.bss*) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } _end = .; diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 66a8b65..4c567110 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -120,15 +120,11 @@ _fiq: .globl _TEXT_BASE _TEXT_BASE: -#ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */ - .word CONFIG_SYS_TEXT_BASE -#else -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) .word CONFIG_SPL_TEXT_BASE #else .word CONFIG_SYS_TEXT_BASE #endif -#endif /* * These are defined in the board-specific linker script. @@ -140,20 +136,18 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start +.globl _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: - .word __bss_end__ - _start + .word __bss_end - _start .globl _end_ofs _end_ofs: .word _end - _start -#ifdef CONFIG_NAND_U_BOOT -.globl _end -_end: - .word __bss_end__ -#endif - #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START @@ -196,32 +190,25 @@ reset: /*------------------------------------------------------------------------------*/ -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL) /* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. + * void relocate_code(addr_moni) * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start - sub r9, r6, r0 /* r9 <- relocation offset */ - cmp r0, r6 - moveq r9, #0 /* no relocation. offset(r9) = 0 */ + subs r9, r6, r0 /* r9 <- relocation offset */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r1!, {r9-r10} /* copy to target address [r1] */ + ldmia r0!, {r10-r11} /* copy from source address [r0] */ + stmia r1!, {r10-r11} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop @@ -230,7 +217,6 @@ copy_loop: * fix .rel.dyn relocations */ ldr r0, _TEXT_BASE /* r0 <- Text base */ - sub r9, r6, r0 /* r9 <- relocation offset */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ add r10, r10, r0 /* r10 <- sym table in FLASH */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ @@ -270,6 +256,8 @@ relocate_done: bx lr +#ifndef CONFIG_SPL_BUILD + _rel_dyn_start_ofs: .word __rel_dyn_start - _start _rel_dyn_end_ofs: diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index a7a98a4..9c2b70d 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -89,7 +89,11 @@ _vectors_end: .globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. @@ -101,9 +105,13 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start +.globl _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: - .word __bss_end__ - _start + .word __bss_end - _start .globl _end_ofs _end_ofs: @@ -152,29 +160,24 @@ reset: /*------------------------------------------------------------------------------*/ /* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. + * void relocate_code(addr_moni) * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start - cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ + subs r9, r6, r0 /* r9 <- relocation offset */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r1!, {r9-r10} /* copy to target address [r1] */ + ldmia r0!, {r10-r11} /* copy from source address [r0] */ + stmia r1!, {r10-r11} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop @@ -183,7 +186,6 @@ copy_loop: * fix .rel.dyn relocations */ ldr r0, _TEXT_BASE /* r0 <- Text base */ - sub r9, r6, r0 /* r9 <- relocation offset */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ add r10, r10, r0 /* r10 <- sym table in FLASH */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index c189849..5e8c528 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -85,7 +85,11 @@ _fiq: .globl _TEXT_BASE _TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* address of _start in the linked image */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else + .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. @@ -97,9 +101,13 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start +.globl _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: - .word __bss_end__ - _start + .word __bss_end - _start .globl _end_ofs _end_ofs: @@ -148,29 +156,24 @@ reset: /*------------------------------------------------------------------------------*/ /* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. + * void relocate_code(addr_moni) * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start - cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ + subs r9, r6, r0 /* r9 <- relocation offset */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r1!, {r9-r10} /* copy to target address [r1] */ + ldmia r0!, {r10-r11} /* copy from source address [r0] */ + stmia r1!, {r10-r11} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop @@ -179,7 +182,6 @@ copy_loop: * fix .rel.dyn relocations */ ldr r0, _TEXT_BASE /* r0 <- Text base */ - sub r9, r6, r0 /* r9 <- relocation offset */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ add r10, r10, r0 /* r10 <- sym table in FLASH */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 4668b3c..7a8c2d0 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -32,7 +32,7 @@ COBJS += cache_v7.o COBJS += cpu.o COBJS += syslib.o -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6),) +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI814X),) SOBJS += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index 70c443e..c97e30d 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -16,7 +16,8 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS += clock.o +COBJS-$(CONFIG_AM33XX) += clock_am33xx.o +COBJS-$(CONFIG_TI814X) += clock_ti814x.o COBJS += sys_info.o COBJS += mem.o COBJS += ddr.o diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index e35a3e3..885fb2d 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -141,11 +141,11 @@ int arch_misc_init(void) { #ifdef CONFIG_AM335X_USB0 musb_register(&otg0_plat, &otg0_board_data, - (void *)AM335X_USB0_OTG_BASE); + (void *)USB0_OTG_BASE); #endif #ifdef CONFIG_AM335X_USB1 musb_register(&otg1_plat, &otg1_board_data, - (void *)AM335X_USB1_OTG_BASE); + (void *)USB1_OTG_BASE); #endif return 0; } diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index d7d98d1..a1efc75 100644 --- a/arch/arm/cpu/armv7/am33xx/clock.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -1,9 +1,9 @@ /* - * clock.c + * clock_am33xx.c * * clocks for AM33XX based boards * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -42,6 +42,35 @@ #define CPGMAC0_IDLE 0x30000 #define DPLL_CLKDCOLDO_GATE_CTRL 0x300 +#define OSC (V_OSCK/1000000) + +#define MPUPLL_M CONFIG_SYS_MPUCLK +#define MPUPLL_N (OSC-1) +#define MPUPLL_M2 1 + +/* Core PLL Fdll = 1 GHZ, */ +#define COREPLL_M 1000 +#define COREPLL_N (OSC-1) + +#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ +#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ +#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */ + +/* + * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll + * frequency needs to be set to 960 MHZ. Hence, + * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below + */ +#define PERPLL_M 960 +#define PERPLL_N (OSC-1) +#define PERPLL_M2 5 + +/* DDR Freq is 266 MHZ for now */ +/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ +#define DDRPLL_M 266 +#define DDRPLL_N (OSC-1) +#define DDRPLL_M2 1 + const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; @@ -166,6 +195,11 @@ static void enable_per_clocks(void) while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN) ; + /* MMC1 */ + writel(PRCM_MOD_EN, &cmper->mmc1clkctrl); + while (readl(&cmper->mmc1clkctrl) != PRCM_MOD_EN) + ; + /* i2c0 */ writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl); while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN) diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c new file mode 100644 index 0000000..cb4210f --- /dev/null +++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c @@ -0,0 +1,406 @@ +/* + * clock_ti814x.c + * + * Clocks for TI814X based boards + * + * Copyright (C) 2013, Texas Instruments, Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clock.h> +#include <asm/arch/hardware.h> +#include <asm/io.h> + +/* PRCM */ +#define PRCM_MOD_EN 0x2 + +/* CLK_SRC */ +#define OSC_SRC0 0 +#define OSC_SRC1 1 + +#define L3_OSC_SRC OSC_SRC0 + +#define OSC_0_FREQ 20 + +#define DCO_HS2_MIN 500 +#define DCO_HS2_MAX 1000 +#define DCO_HS1_MIN 1000 +#define DCO_HS1_MAX 2000 + +#define SELFREQDCO_HS2 0x00000801 +#define SELFREQDCO_HS1 0x00001001 + +#define MPU_N 0x1 +#define MPU_M 0x3C +#define MPU_M2 1 +#define MPU_CLKCTRL 0x1 + +#define L3_N 19 +#define L3_M 880 +#define L3_M2 4 +#define L3_CLKCTRL 0x801 + +#define DDR_N 19 +#define DDR_M 666 +#define DDR_M2 2 +#define DDR_CLKCTRL 0x801 + +/* ADPLLJ register values */ +#define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */ +#define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */ +#define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29) +#define ADPLLJ_CLKCTRL_IDLE (1 << 23) +#define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20) +#define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19) +#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17) +#define ADPLLJ_CLKCTRL_LPMODE (1 << 12) +#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11) +#define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10) +#define ADPLLJ_CLKCTRL_TINITZ (1 << 0) +#define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \ + ADPLLJ_CLKCTRL_CLKOUTEN | \ + ADPLLJ_CLKCTRL_CLKOUTLDOEN | \ + ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ) + +#define ADPLLJ_STATUS_PHASELOCK (1 << 10) +#define ADPLLJ_STATUS_FREQLOCK (1 << 9) +#define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \ + ADPLLJ_STATUS_FREQLOCK) +#define ADPLLJ_STATUS_BYPASSACK (1 << 8) +#define ADPLLJ_STATUS_BYPASS (1 << 0) +#define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \ + ADPLLJ_STATUS_BYPASS) + +#define ADPLLJ_TENABLE_ENB (1 << 0) +#define ADPLLJ_TENABLEDIV_ENB (1 << 0) + +#define ADPLLJ_M2NDIV_M2SHIFT 16 + +#define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048) +#define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110) +#define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290) + +struct ad_pll { + unsigned int pwrctrl; + unsigned int clkctrl; + unsigned int tenable; + unsigned int tenablediv; + unsigned int m2ndiv; + unsigned int mn2div; + unsigned int fracdiv; + unsigned int bwctrl; + unsigned int fracctrl; + unsigned int status; + unsigned int m3div; + unsigned int rampctrl; +}; + +#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0) + +/* PRCM */ +#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) + +struct cm_def { + unsigned int resv0[2]; + unsigned int l3fastclkstctrl; + unsigned int resv1[1]; + unsigned int pciclkstctrl; + unsigned int resv2[1]; + unsigned int ducaticlkstctrl; + unsigned int resv3[1]; + unsigned int emif0clkctrl; + unsigned int emif1clkctrl; + unsigned int dmmclkctrl; + unsigned int fwclkctrl; + unsigned int resv4[10]; + unsigned int usbclkctrl; + unsigned int resv5[1]; + unsigned int sataclkctrl; + unsigned int resv6[4]; + unsigned int ducaticlkctrl; + unsigned int pciclkctrl; +}; + +#define CM_ALWON_BASE (PRCM_BASE + 0x1400) + +struct cm_alwon { + unsigned int l3slowclkstctrl; + unsigned int ethclkstctrl; + unsigned int l3medclkstctrl; + unsigned int mmu_clkstctrl; + unsigned int mmucfg_clkstctrl; + unsigned int ocmc0clkstctrl; + unsigned int vcpclkstctrl; + unsigned int mpuclkstctrl; + unsigned int sysclk4clkstctrl; + unsigned int sysclk5clkstctrl; + unsigned int sysclk6clkstctrl; + unsigned int rtcclkstctrl; + unsigned int l3fastclkstctrl; + unsigned int resv0[67]; + unsigned int mcasp0clkctrl; + unsigned int mcasp1clkctrl; + unsigned int mcasp2clkctrl; + unsigned int mcbspclkctrl; + unsigned int uart0clkctrl; + unsigned int uart1clkctrl; + unsigned int uart2clkctrl; + unsigned int gpio0clkctrl; + unsigned int gpio1clkctrl; + unsigned int i2c0clkctrl; + unsigned int i2c1clkctrl; + unsigned int mcasp345clkctrl; + unsigned int atlclkctrl; + unsigned int mlbclkctrl; + unsigned int pataclkctrl; + unsigned int resv1[1]; + unsigned int uart3clkctrl; + unsigned int uart4clkctrl; + unsigned int uart5clkctrl; + unsigned int wdtimerclkctrl; + unsigned int spiclkctrl; + unsigned int mailboxclkctrl; + unsigned int spinboxclkctrl; + unsigned int mmudataclkctrl; + unsigned int resv2[2]; + unsigned int mmucfgclkctrl; + unsigned int resv3[2]; + unsigned int ocmc0clkctrl; + unsigned int vcpclkctrl; + unsigned int resv4[2]; + unsigned int controlclkctrl; + unsigned int resv5[2]; + unsigned int gpmcclkctrl; + unsigned int ethernet0clkctrl; + unsigned int resv6[1]; + unsigned int mpuclkctrl; + unsigned int debugssclkctrl; + unsigned int l3clkctrl; + unsigned int l4hsclkctrl; + unsigned int l4lsclkctrl; + unsigned int rtcclkctrl; + unsigned int tpccclkctrl; + unsigned int tptc0clkctrl; + unsigned int tptc1clkctrl; + unsigned int tptc2clkctrl; + unsigned int tptc3clkctrl; + unsigned int resv7[4]; + unsigned int dcan01clkctrl; + unsigned int mmchs0clkctrl; + unsigned int mmchs1clkctrl; + unsigned int mmchs2clkctrl; + unsigned int custefuseclkctrl; +}; + + +const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; +const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; + +/* + * Enable the peripheral clock for required peripherals + */ +static void enable_per_clocks(void) +{ + /* UART0 */ + writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); + while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) + ; + + /* HSMMC1 */ + writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl); + while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN) + ; +} + +/* + * select the HS1 or HS2 for DCO Freq + * return : CLKCTRL + */ +static u32 pll_dco_freq_sel(u32 clkout_dco) +{ + if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX) + return SELFREQDCO_HS2; + else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX) + return SELFREQDCO_HS1; + else + return -1; +} + +/* + * select the sigma delta config + * return: sigma delta val + */ +static u32 pll_sigma_delta_val(u32 clkout_dco) +{ + u32 sig_val = 0; + float frac_div; + + frac_div = (float) clkout_dco / 250; + frac_div = frac_div + 0.90; + sig_val = (int)frac_div; + sig_val = sig_val << 24; + + return sig_val; +} + +/* + * configure individual ADPLLJ + */ +static void pll_config(u32 base, u32 n, u32 m, u32 m2, + u32 clkctrl_val, int adpllj) +{ + const struct ad_pll *adpll = (struct ad_pll *)base; + u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0; + u32 sig_val = 0, hs_mod = 0; + + m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n; + mn2val = m; + + /* calculate clkout_dco */ + clkout_dco = ((OSC_0_FREQ / (n+1)) * m); + + /* sigma delta & Hs mode selection skip for ADPLLS*/ + if (adpllj) { + sig_val = pll_sigma_delta_val(clkout_dco); + hs_mod = pll_dco_freq_sel(clkout_dco); + } + + /* by-pass pll */ + read_clkctrl = readl(&adpll->clkctrl); + writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl); + while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK) + != ADPLLJ_STATUS_BYPASSANDACK) + ; + + /* clear TINITZ */ + read_clkctrl = readl(&adpll->clkctrl); + writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl); + + /* + * ref_clk = 20/(n + 1); + * clkout_dco = ref_clk * m; + * clk_out = clkout_dco/m2; + */ + read_clkctrl = readl(&adpll->clkctrl) & + ~(ADPLLJ_CLKCTRL_LPMODE | + ADPLLJ_CLKCTRL_DRIFTGUARDIAN | + ADPLLJ_CLKCTRL_REGM4XEN); + writel(m2nval, &adpll->m2ndiv); + writel(mn2val, &adpll->mn2div); + + /* Skip for modena(ADPLLS) */ + if (adpllj) { + writel(sig_val, &adpll->fracdiv); + writel((read_clkctrl | hs_mod), &adpll->clkctrl); + } + + /* Load M2, N2 dividers of ADPLL */ + writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv); + writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv); + + /* Load M, N dividers of ADPLL */ + writel(ADPLLJ_TENABLE_ENB, &adpll->tenable); + writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable); + + /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */ + read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO; + if (adpllj) + writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO), + &adpll->clkctrl); + + /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */ + read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE; + writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl); + + /* Wait for phase and freq lock */ + while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) != + ADPLLJ_STATUS_PHSFRQLOCK) + ; +} + +static void unlock_pll_control_mmr(void) +{ + /* TRM 2.10.1.4 and 3.2.7-3.2.11 */ + writel(0x1EDA4C3D, 0x481C5040); + writel(0x2FF1AC2B, 0x48140060); + writel(0xF757FDC0, 0x48140064); + writel(0xE2BC3A6D, 0x48140068); + writel(0x1EBF131D, 0x4814006c); + writel(0x6F361E05, 0x48140070); +} + +static void mpu_pll_config(void) +{ + pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0); +} + +static void l3_pll_config(void) +{ + u32 l3_osc_src, rd_osc_src = 0; + + l3_osc_src = L3_OSC_SRC; + rd_osc_src = readl(OSC_SRC_CTRL); + + if (OSC_SRC0 == l3_osc_src) + writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL); + else + writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL); + + pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1); +} + +void ddr_pll_config(unsigned int ddrpll_m) +{ + pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1); +} + +void enable_emif_clocks(void) {}; + +void enable_dmm_clocks(void) +{ + writel(PRCM_MOD_EN, &cmdef->fwclkctrl); + writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); + writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); + while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN) + ; + writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); + while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN) + ; + while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) + ; + writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); + while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN) + ; + writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); + while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) + ; +} + +/* + * Configure the PLL/PRCM for necessary peripherals + */ +void pll_init() +{ + unlock_pll_control_mmr(); + + /* Enable the control module */ + writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); + + mpu_pll_config(); + + l3_pll_config(); + + /* Enable the required peripherals */ + enable_per_clocks(); +} diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 448cc40..d1e2fd3 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -24,15 +24,20 @@ http://www.ti.com/ /** * Base address for EMIF instances */ -static struct emif_reg_struct *emif_reg = { - (struct emif_reg_struct *)EMIF4_0_CFG_BASE}; +static struct emif_reg_struct *emif_reg[2] = { + (struct emif_reg_struct *)EMIF4_0_CFG_BASE, + (struct emif_reg_struct *)EMIF4_1_CFG_BASE}; /** - * Base address for DDR instance + * Base addresses for DDR PHY cmd/data regs */ -static struct ddr_regs *ddr_reg[2] = { - (struct ddr_regs *)DDR_PHY_BASE_ADDR, - (struct ddr_regs *)DDR_PHY_BASE_ADDR2}; +static struct ddr_cmd_regs *ddr_cmd_reg[2] = { + (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR, + (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2}; + +static struct ddr_data_regs *ddr_data_reg[2] = { + (struct ddr_data_regs *)DDR_PHY_DATA_ADDR, + (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2}; /** * Base address for ddr io control instances @@ -43,7 +48,7 @@ static struct ddr_cmdtctrl *ioctrl_reg = { /** * Configure SDRAM */ -void config_sdram(const struct emif_regs *regs) +void config_sdram(const struct emif_regs *regs, int nr) { if (regs->zq_config) { /* @@ -51,68 +56,85 @@ void config_sdram(const struct emif_regs *regs) * about 570us for a delay, which will be long enough * to configure things. */ - writel(0x2800, &emif_reg->emif_sdram_ref_ctrl); - writel(regs->zq_config, &emif_reg->emif_zq_config); + writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); } - writel(regs->sdram_config, &emif_reg->emif_sdram_config); - writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl); - writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); + writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); } /** * Set SDRAM timings */ -void set_sdram_timings(const struct emif_regs *regs) +void set_sdram_timings(const struct emif_regs *regs, int nr) { - writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1); - writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw); - writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2); - writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw); - writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3); - writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw); + writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1); + writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw); + writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2); + writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw); + writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3); + writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw); } /** * Configure DDR PHY */ -void config_ddr_phy(const struct emif_regs *regs) +void config_ddr_phy(const struct emif_regs *regs, int nr) { - writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1); - writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw); + writel(regs->emif_ddr_phy_ctlr_1, + &emif_reg[nr]->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, + &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); } /** * Configure DDR CMD control registers */ -void config_cmd_ctrl(const struct cmd_control *cmd) +void config_cmd_ctrl(const struct cmd_control *cmd, int nr) { - writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio); - writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff); - writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout); + writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio); + writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff); + writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout); - writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio); - writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff); - writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout); + writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio); + writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff); + writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout); - writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio); - writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff); - writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout); + writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio); + writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff); + writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout); } /** * Configure DDR DATA registers */ -void config_ddr_data(int macrono, const struct ddr_data *data) +void config_ddr_data(const struct ddr_data *data, int nr) { - writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0); - writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0); - writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0); - writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0); - writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0); - writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0); - writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0); - writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0); + int i; + + for (i = 0; i < DDR_DATA_REGS_NR; i++) { + writel(data->datardsratio0, + &(ddr_data_reg[nr]+i)->dt0rdsratio0); + writel(data->datawdsratio0, + &(ddr_data_reg[nr]+i)->dt0wdsratio0); + writel(data->datawiratio0, + &(ddr_data_reg[nr]+i)->dt0wiratio0); + writel(data->datagiratio0, + &(ddr_data_reg[nr]+i)->dt0giratio0); + writel(data->datafwsratio0, + &(ddr_data_reg[nr]+i)->dt0fwsratio0); + writel(data->datawrsratio0, + &(ddr_data_reg[nr]+i)->dt0wrsratio0); + writel(data->datauserank0delay, + &(ddr_data_reg[nr]+i)->dt0rdelays0); + writel(data->datadldiff0, + &(ddr_data_reg[nr]+i)->dt0dldiff0); + } } void config_io_ctrl(unsigned long val) diff --git a/arch/arm/cpu/armv7/am33xx/elm.c b/arch/arm/cpu/armv7/am33xx/elm.c index 9eed23d..41df612 100644 --- a/arch/arm/cpu/armv7/am33xx/elm.c +++ b/arch/arm/cpu/armv7/am33xx/elm.c @@ -33,7 +33,7 @@ #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/cpu.h> -#include <asm/arch/omap_gpmc.h> +#include <asm/omap_gpmc.h> #include <asm/arch/elm.h> #define ELM_DEFAULT_POLY (0) diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 01e3a52..aa84e96 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -44,44 +44,65 @@ void dram_init_banksize(void) #ifdef CONFIG_SPL_BUILD -static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR; +static struct dmm_lisa_map_regs *hw_lisa_map_regs = + (struct dmm_lisa_map_regs *)DMM_BASE; +static struct vtp_reg *vtpreg[2] = { + (struct vtp_reg *)VTP0_CTRL_ADDR, + (struct vtp_reg *)VTP1_CTRL_ADDR}; +#ifdef CONFIG_AM33XX static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR; +#endif + +void config_dmm(const struct dmm_lisa_map_regs *regs) +{ + enable_dmm_clocks(); + + writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); + writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); -static void config_vtp(void) + writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3); + writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2); + writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); + writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); +} + +static void config_vtp(int nr) { - writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE, - &vtpreg->vtp0ctrlreg); - writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN), - &vtpreg->vtp0ctrlreg); - writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN, - &vtpreg->vtp0ctrlreg); + writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE, + &vtpreg[nr]->vtp0ctrlreg); + writel(readl(&vtpreg[nr]->vtp0ctrlreg) & (~VTP_CTRL_START_EN), + &vtpreg[nr]->vtp0ctrlreg); + writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_START_EN, + &vtpreg[nr]->vtp0ctrlreg); /* Poll for READY */ - while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) != + while ((readl(&vtpreg[nr]->vtp0ctrlreg) & VTP_CTRL_READY) != VTP_CTRL_READY) ; } void config_ddr(unsigned int pll, unsigned int ioctrl, const struct ddr_data *data, const struct cmd_control *ctrl, - const struct emif_regs *regs) + const struct emif_regs *regs, int nr) { enable_emif_clocks(); ddr_pll_config(pll); - config_vtp(); - config_cmd_ctrl(ctrl); - - config_ddr_data(0, data); - config_ddr_data(1, data); + config_vtp(nr); + config_cmd_ctrl(ctrl, nr); + config_ddr_data(data, nr); +#ifdef CONFIG_AM33XX config_io_ctrl(ioctrl); /* Set CKE to be controlled by EMIF/DDR PHY */ writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); +#endif /* Program EMIF instance */ - config_ddr_phy(regs); - set_sdram_timings(regs); - config_sdram(regs); + config_ddr_phy(regs, nr); + set_sdram_timings(regs, nr); + config_sdram(regs, nr); } #endif diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c index b8f54ab..b86b0de 100644 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -83,7 +83,7 @@ void gpmc_init(void) /* global settings */ writel(0x00000008, &gpmc_cfg->sysconfig); writel(0x00000100, &gpmc_cfg->irqstatus); - writel(0x00000200, &gpmc_cfg->irqenable); + writel(0x00000100, &gpmc_cfg->irqenable); writel(0x00000012, &gpmc_cfg->config); /* * Disable the GPMC0 config set by ROM code diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index 507b618..5fd8b47 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -98,6 +98,9 @@ int print_cpuinfo(void) case AM335X: cpu_s = "AM335X"; break; + case TI81XX: + cpu_s = "TI81XX"; + break; default: cpu_s = "Unknown cpu type"; break; @@ -120,7 +123,7 @@ int print_cpuinfo(void) sec_s = "?"; } - printf("AM%s-%s rev %d\n", + printf("%s-%s rev %d\n", cpu_s, sec_s, get_cpu_rev()); /* TODO: Print ARM and DDR frequencies */ diff --git a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds index 69f6d48..b6a929f 100644 --- a/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/am33xx/u-boot-spl.lds @@ -62,6 +62,6 @@ SECTIONS __bss_start = .; *(.bss*) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } >.sdram } diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 5f6d039..8748c14 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -340,6 +340,9 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop) { } +void arm_init_domains(void) +{ +} #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */ #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index 9c3e2f3..56b8053 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -40,5 +40,11 @@ PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,) PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED) ifneq ($(CONFIG_IMX_CONFIG),) +ifdef CONFIG_SPL +ifdef CONFIG_SPL_BUILD +ALL-y += $(OBJTREE)/SPL +endif +else ALL-y += $(obj)u-boot.imx endif +endif diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 956427c..223660a 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -27,6 +27,49 @@ #include <asm/arch/clk.h> #include <asm/arch/periph.h> +/* * + * This structure is to store the src bit, div bit and prediv bit + * positions of the peripheral clocks of the src and div registers + */ +struct clk_bit_info { + int8_t src_bit; + int8_t div_bit; + int8_t prediv_bit; +}; + +/* src_bit div_bit prediv_bit */ +static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = { + {0, 0, -1}, + {4, 4, -1}, + {8, 8, -1}, + {12, 12, -1}, + {0, 0, 8}, + {4, 16, 24}, + {8, 0, 8}, + {12, 16, 24}, + {-1, -1, -1}, + {16, 0, 8}, + {20, 16, 24}, + {24, 0, 8}, + {0, 0, 4}, + {4, 12, 16}, + {-1, -1, -1}, + {-1, -1, -1}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {-1, 24, 0}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, + {24, 0, -1}, +}; + /* Epll Clock division values to achive different frequency output */ static struct set_epll_con_val exynos5_epll_div[] = { { 192000000, 0, 48, 3, 1, 0 }, @@ -201,6 +244,107 @@ static unsigned long exynos5_get_pll_clk(int pllreg) return fout; } +static unsigned long exynos5_get_periph_rate(int peripheral) +{ + struct clk_bit_info *bit_info = &clk_bit_info[peripheral]; + unsigned long sclk, sub_clk; + unsigned int src, div, sub_div; + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + src = readl(&clk->src_peric0); + div = readl(&clk->div_peric0); + break; + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + case PERIPH_ID_PWM4: + src = readl(&clk->src_peric0); + div = readl(&clk->div_peric3); + break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + src = readl(&clk->src_peric1); + div = readl(&clk->div_peric1); + break; + case PERIPH_ID_SPI2: + src = readl(&clk->src_peric1); + div = readl(&clk->div_peric2); + break; + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + src = readl(&clk->sclk_src_isp); + div = readl(&clk->sclk_div_isp); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + src = readl(&clk->src_fsys); + div = readl(&clk->div_fsys1); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + case PERIPH_ID_I2C6: + case PERIPH_ID_I2C7: + sclk = exynos5_get_pll_clk(MPLL); + sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit) + & 0x7) + 1; + div = ((readl(&clk->div_top0) >> bit_info->prediv_bit) + & 0x7) + 1; + return (sclk / sub_div) / div; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + }; + + src = (src >> bit_info->src_bit) & 0xf; + + switch (src) { + case EXYNOS_SRC_MPLL: + sclk = exynos5_get_pll_clk(MPLL); + break; + case EXYNOS_SRC_EPLL: + sclk = exynos5_get_pll_clk(EPLL); + break; + case EXYNOS_SRC_VPLL: + sclk = exynos5_get_pll_clk(VPLL); + break; + default: + return 0; + } + + /* Ratio clock division for this peripheral */ + sub_div = (div >> bit_info->div_bit) & 0xf; + sub_clk = sclk / (sub_div + 1); + + /* Pre-ratio clock division for SDMMC0 and 2 */ + if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) { + div = (div >> bit_info->prediv_bit) & 0xff; + return sub_clk / (div + 1); + } + + return sub_clk; +} + +unsigned long clock_get_periph_rate(int peripheral) +{ + if (cpu_is_exynos5()) + return exynos5_get_periph_rate(peripheral); + else + return 0; +} + /* exynos4: return ARM clock frequency */ static unsigned long exynos4_get_arm_clk(void) { @@ -324,27 +468,6 @@ static unsigned long exynos4x12_get_pwm_clk(void) return pclk; } -/* exynos5: return pwm clock frequency */ -static unsigned long exynos5_get_pwm_clk(void) -{ - struct exynos5_clock *clk = - (struct exynos5_clock *)samsung_get_base_clock(); - unsigned long pclk, sclk; - unsigned int ratio; - - /* - * CLK_DIV_PERIC3 - * PWM_RATIO [3:0] - */ - ratio = readl(&clk->div_peric3); - ratio = ratio & 0xf; - sclk = get_pll_clk(MPLL); - - pclk = sclk / (ratio + 1); - - return pclk; -} - /* exynos4: return uart clock frequency */ static unsigned long exynos4_get_uart_clk(int dev_index) { @@ -1210,7 +1333,7 @@ unsigned long get_i2c_clk(void) unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) - return exynos5_get_pwm_clk(); + return clock_get_periph_rate(PERIPH_ID_PWM0); else { if (proid_is_exynos4412()) return exynos4x12_get_pwm_clk(); diff --git a/arch/arm/cpu/armv7/exynos/power.c b/arch/arm/cpu/armv7/exynos/power.c index d4bce6d..6375a81 100644 --- a/arch/arm/cpu/armv7/exynos/power.c +++ b/arch/arm/cpu/armv7/exynos/power.c @@ -95,3 +95,48 @@ void set_dp_phy_ctrl(unsigned int enable) if (cpu_is_exynos5()) exynos5_dp_phy_control(enable); } + +static void exynos5_set_ps_hold_ctrl(void) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + /* Set PS-Hold high */ + setbits_le32(&power->ps_hold_control, + EXYNOS_PS_HOLD_CONTROL_DATA_HIGH); +} + +void set_ps_hold_ctrl(void) +{ + if (cpu_is_exynos5()) + exynos5_set_ps_hold_ctrl(); +} + + +static void exynos5_set_xclkout(void) +{ + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + /* use xxti for xclk out */ + clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, + PMU_DEBUG_XXTI); +} + +void set_xclkout(void) +{ + if (cpu_is_exynos5()) + exynos5_set_xclkout(); +} + +/* Enables hardware tripping to power off the system when TMU fails */ +void set_hw_thermal_trip(void) +{ + if (cpu_is_exynos5()) { + struct exynos5_power *power = + (struct exynos5_power *)samsung_get_base_power(); + + /* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/ + setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP); + } +} diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c index ab65b8d..e948e4c 100644 --- a/arch/arm/cpu/armv7/exynos/soc.c +++ b/arch/arm/cpu/armv7/exynos/soc.c @@ -23,6 +23,14 @@ #include <common.h> #include <asm/io.h> +#include <asm/system.h> + +enum l2_cache_params { + CACHE_TAG_RAM_SETUP = (1 << 9), + CACHE_DATA_RAM_SETUP = (1 << 5), + CACHE_TAG_RAM_LATENCY = (2 << 6), + CACHE_DATA_RAM_LATENCY = (2 << 0) +}; void reset_cpu(ulong addr) { @@ -36,3 +44,31 @@ void enable_caches(void) dcache_enable(); } #endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +/* + * Set L2 cache parameters + */ +static void exynos5_set_l2cache_params(void) +{ + unsigned int val = 0; + + asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val)); + + val |= CACHE_TAG_RAM_SETUP | + CACHE_DATA_RAM_SETUP | + CACHE_TAG_RAM_LATENCY | + CACHE_DATA_RAM_LATENCY; + + asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val)); +} + +/* + * Sets L2 cache related parameters before enabling data cache + */ +void v7_outer_cache_enable(void) +{ + if (cpu_is_exynos5()) + exynos5_set_l2cache_params(); +} +#endif diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 6d9396a9..dfce0ca 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -309,8 +309,7 @@ setup_pll_func: ldr r0, =CCM_BASE_ADDR ldr r1, =0x00015154 str r1, [r0, #CLKCTL_CBCMR] - ldr r1, =0x02888945 - orr r1, r1, #(1 << 16) + ldr r1, =0x02898945 str r1, [r0, #CLKCTL_CBCDR] /* make sure change is effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] @@ -321,10 +320,7 @@ setup_pll_func: /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR - ldr r1, =0x00808145 - orr r1, r1, #(2 << 10) - orr r1, r1, #(0 << 16) - orr r1, r1, #(1 << 19) + ldr r1, =0x00888945 str r1, [r0, #CLKCTL_CBCDR] ldr r1, =0x00016154 diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 0efc80d..55e82ba 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -36,7 +36,7 @@ COBJS += emif-common.o COBJS += vc.o endif -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) COBJS += boot-common.o SOBJS += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 9ed1899..2b955c7 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -612,7 +612,7 @@ void freq_update_core(void) /* * Putting EMIF in HW_AUTO is seen to be causing issues with - * EMIF clocks and the master DLL. Put EMIF in SW_WKUP + * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP * in OMAP5430 ES1.0 silicon */ if (omap_rev != OMAP5430_ES1_0) { @@ -659,7 +659,7 @@ void setup_clocks_for_console(void) MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << MODULE_CLKCTRL_MODULEMODE_SHIFT); - clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl, + clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl, MODULE_CLKCTRL_MODULEMODE_MASK, MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << MODULE_CLKCTRL_MODULEMODE_SHIFT); diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 9eb1279..cdb4439 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -655,20 +655,27 @@ static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) return phy; } -static u32 get_emif_mem_size(struct emif_device_details *devices) +static u32 get_emif_mem_size(u32 base) { u32 size_mbytes = 0, temp; + struct emif_device_details dev_details; + struct lpddr2_device_details cs0_dev_details, cs1_dev_details; + u32 emif_nr = emif_num(base); - if (!devices) - return 0; + emif_reset_phy(base); + dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, + &cs0_dev_details); + dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, + &cs1_dev_details); + emif_reset_phy(base); - if (devices->cs0_device_details) { - temp = devices->cs0_device_details->density; + if (dev_details.cs0_device_details) { + temp = dev_details.cs0_device_details->density; size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; } - if (devices->cs1_device_details) { - temp = devices->cs1_device_details->density; + if (dev_details.cs1_device_details) { + temp = dev_details.cs1_device_details->density; size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; } /* convert to bytes */ @@ -1040,13 +1047,9 @@ static void do_sdram_init(u32 base) /* Return if no devices on this EMIF */ if (!dev_details.cs0_device_details && !dev_details.cs1_device_details) { - emif_sizes[emif_nr - 1] = 0; return; } - if (!in_sdram) - emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details); - /* * Get device timings: * - Default timings specified by JESD209-2 if @@ -1108,8 +1111,8 @@ void dmm_init(u32 base) mapped_size = 0; section_cnt = 3; sys_addr = CONFIG_SYS_SDRAM_BASE; - emif1_size = emif_sizes[0]; - emif2_size = emif_sizes[1]; + emif1_size = get_emif_mem_size(EMIF1_BASE); + emif2_size = get_emif_mem_size(EMIF2_BASE); debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); if (!emif1_size && !emif2_size) diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 05ff2e8..70d16a8 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -34,6 +34,12 @@ #include <asm/emif.h> #include <asm/omap_common.h> #include <linux/compiler.h> +#include <asm/cache.h> +#include <asm/system.h> + +#define ARMV7_DCACHE_WRITEBACK 0xe +#define ARMV7_DOMAIN_CLIENT 1 +#define ARMV7_DOMAIN_MASK (0x3 << 0) DECLARE_GLOBAL_DATA_PTR; @@ -269,4 +275,33 @@ void enable_caches(void) /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } + +void dram_bank_mmu_setup(int bank) +{ + bd_t *bd = gd->bd; + int i; + + u32 start = bd->bi_dram[bank].start >> 20; + u32 size = bd->bi_dram[bank].size >> 20; + u32 end = start + size; + + debug("%s: bank: %d\n", __func__, bank); + for (i = start; i < end; i++) + set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); + +} + +void arm_init_domains(void) +{ + u32 reg; + + reg = get_dacr(); + /* + * Set DOMAIN to client access so that all permissions + * set in pagetables are validated by the mmu. + */ + reg &= ~ARMV7_DOMAIN_MASK; + reg |= ARMV7_DOMAIN_CLIENT; + set_dacr(reg); +} #endif diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 3581077..90b3c8a 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -26,6 +26,7 @@ * MA 02111-1307 USA */ +#include <config.h> #include <asm/arch/omap.h> #include <asm/arch/spl.h> #include <linux/linkage.h> @@ -59,10 +60,14 @@ ENTRY(save_boot_params) ldr r3, =boot_params strb r2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r1 - /* boot mode is passed only for devices that can raw/fat mode */ - cmp r2, #BOOT_DEVICE_XIP + /* + * boot mode is only valid for device that can be raw or FAT booted. + * in other cases it may be fatal to look. While platforms differ + * in the values used for each MMC slot, they are contiguous. + */ + cmp r2, #MMC_BOOT_DEVICES_START blt 2f - cmp r2, #BOOT_DEVICE_MMC2 + cmp r2, #MMC_BOOT_DEVICES_END bgt 2f /* Store the boot mode (raw/FAT) in omap_bootmode */ ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c index 36bea5f..507f687 100644 --- a/arch/arm/cpu/armv7/omap-common/timer.c +++ b/arch/arm/cpu/armv7/omap-common/timer.c @@ -34,6 +34,7 @@ #include <common.h> #include <asm/io.h> +#include <asm/arch/cpu.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds index 88f4069..bd218c0 100644 --- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds @@ -38,7 +38,7 @@ SECTIONS .text : { __start = .; - arch/arm/cpu/armv7/start.o (.text) + arch/arm/cpu/armv7/start.o (.text*) *(.text*) } >.sram @@ -58,6 +58,6 @@ SECTIONS __bss_start = .; *(.bss*) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } >.sdram } diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index c6d9a42..b72fadc 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -328,14 +328,25 @@ void abort(void) *****************************************************************************/ static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { - if (argc != 2) + if (argc < 2 || argc > 3) goto usage; - if (strncmp(argv[1], "hw", 2) == 0) - omap_nand_switch_ecc(1); - else if (strncmp(argv[1], "sw", 2) == 0) - omap_nand_switch_ecc(0); - else + + if (strncmp(argv[1], "hw", 2) == 0) { + if (argc == 2) { + omap_nand_switch_ecc(1, 1); + } else { + if (strncmp(argv[2], "hamming", 7) == 0) + omap_nand_switch_ecc(1, 1); + else if (strncmp(argv[2], "bch8", 4) == 0) + omap_nand_switch_ecc(1, 8); + else + goto usage; + } + } else if (strncmp(argv[1], "sw", 2) == 0) { + omap_nand_switch_ecc(0, 0); + } else { goto usage; + } return 0; @@ -345,9 +356,13 @@ usage: } U_BOOT_CMD( - nandecc, 2, 1, do_switch_ecc, + nandecc, 3, 1, do_switch_ecc, "switch OMAP3 NAND ECC calculation algorithm", - "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm" + "hw [hamming|bch8] - Switch between NAND hardware 1-bit hamming and" + " 8-bit BCH\n" + " ecc calculation (second parameter may" + " be omitted).\n" + "nandecc sw - Switch to NAND software ecc algorithm." ); #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */ diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c index 3c80113..08a63d2 100644 --- a/arch/arm/cpu/armv7/omap3/sys_info.c +++ b/arch/arm/cpu/armv7/omap3/sys_info.c @@ -299,9 +299,9 @@ int print_cpuinfo (void) } if ((get_cpu_rev() >= CPU_3XX_ES31) && (get_sku_id() == SKUID_CLK_720MHZ)) - max_clk = "720 mHz"; + max_clk = "720 MHz"; else - max_clk = "600 mHz"; + max_clk = "600 MHz"; break; case CPU_AM35XX: diff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c index ca4823d..53f6063 100644 --- a/arch/arm/cpu/armv7/omap4/emif.c +++ b/arch/arm/cpu/armv7/omap4/emif.c @@ -33,7 +33,6 @@ #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS u32 *const T_num = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_NUM; u32 *const T_den = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_T_DEN; -u32 *const emif_sizes = (u32 *)OMAP4_SRAM_SCRATCH_EMIF_SIZE; #endif #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 7551b98..04977b4 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -216,14 +216,14 @@ struct dplls omap4460_dplls = { struct pmic_data twl6030_4430es1 = { .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV, - .step = 12660, /* 10 mV represented in uV */ + .step = 12660, /* 12.66 mV represented in uV */ /* The code starts at 1 not 0 */ .start_code = 1, }; struct pmic_data twl6030 = { .base_offset = PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV, - .step = 12660, /* 10 mV represented in uV */ + .step = 12660, /* 12.66 mV represented in uV */ /* The code starts at 1 not 0 */ .start_code = 1, }; @@ -271,11 +271,11 @@ struct vcores_data omap4460_volts = { .core.value = 1200, .core.addr = SMPS_REG_ADDR_VCORE1, - .core.pmic = &tps62361, + .core.pmic = &twl6030, .mm.value = 1200, .mm.addr = SMPS_REG_ADDR_VCORE2, - .mm.pmic = &tps62361, + .mm.pmic = &twl6030, }; /* diff --git a/arch/arm/cpu/armv7/omap5/emif.c b/arch/arm/cpu/armv7/omap5/emif.c index 8019ffe..3f37abd 100644 --- a/arch/arm/cpu/armv7/omap5/emif.c +++ b/arch/arm/cpu/armv7/omap5/emif.c @@ -34,7 +34,6 @@ #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) static u32 *const T_num = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_NUM; static u32 *const T_den = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_T_DEN; -static u32 *const emif_sizes = (u32 *)OMAP5_SRAM_SCRATCH_EMIF_SIZE; #endif #ifdef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS diff --git a/arch/arm/cpu/armv7/s5p-common/pwm.c b/arch/arm/cpu/armv7/s5p-common/pwm.c index 44d7bc3..6f401b8 100644 --- a/arch/arm/cpu/armv7/s5p-common/pwm.c +++ b/arch/arm/cpu/armv7/s5p-common/pwm.c @@ -70,7 +70,7 @@ static unsigned long pwm_calc_tin(int pwm_id, unsigned long freq) return tin_parent_rate / 16; } -#define NS_IN_HZ (1000000000UL) +#define NS_IN_SEC 1000000000UL int pwm_config(int pwm_id, int duty_ns, int period_ns) { @@ -79,7 +79,7 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns) unsigned int offset; unsigned long tin_rate; unsigned long tin_ns; - unsigned long period; + unsigned long frequency; unsigned long tcon; unsigned long tcnt; unsigned long tcmp; @@ -89,34 +89,24 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns) * fact that anything faster than 1GHz is easily representable * by 32bits. */ - if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ) + if (period_ns > NS_IN_SEC || duty_ns > NS_IN_SEC || period_ns == 0) return -ERANGE; if (duty_ns > period_ns) return -EINVAL; - period = NS_IN_HZ / period_ns; + frequency = NS_IN_SEC / period_ns; /* Check to see if we are changing the clock rate of the PWM */ - tin_rate = pwm_calc_tin(pwm_id, period); + tin_rate = pwm_calc_tin(pwm_id, frequency); - tin_ns = NS_IN_HZ / tin_rate; + tin_ns = NS_IN_SEC / tin_rate; tcnt = period_ns / tin_ns; /* Note, counters count down */ tcmp = duty_ns / tin_ns; tcmp = tcnt - tcmp; - /* - * the pwm hw only checks the compare register after a decrement, - * so the pin never toggles if tcmp = tcnt - */ - if (tcmp == tcnt) - tcmp--; - - if (tcmp < 0) - tcmp = 0; - /* Update the PWM register block. */ offset = pwm_id * 3; if (pwm_id < 4) { @@ -143,7 +133,7 @@ int pwm_init(int pwm_id, int div, int invert) u32 val; const struct s5p_timer *pwm = (struct s5p_timer *)samsung_get_base_timer(); - unsigned long timer_rate_hz; + unsigned long ticks_per_period; unsigned int offset, prescaler; /* @@ -167,14 +157,24 @@ int pwm_init(int pwm_id, int div, int invert) val |= (div & 0xf) << MUX_DIV_SHIFT(pwm_id); writel(val, &pwm->tcfg1); - timer_rate_hz = get_pwm_clk() / ((prescaler + 1) * - (div + 1)); + if (pwm_id == 4) { + /* + * TODO(sjg): Use this as a countdown timer for now. We count + * down from the maximum value to 0, then reset. + */ + ticks_per_period = -1UL; + } else { + const unsigned long pwm_hz = 1000; + unsigned long timer_rate_hz = get_pwm_clk() / + ((prescaler + 1) * (1 << div)); - timer_rate_hz = timer_rate_hz / CONFIG_SYS_HZ; + ticks_per_period = timer_rate_hz / pwm_hz; + } /* set count value */ offset = pwm_id * 3; - writel(timer_rate_hz, &pwm->tcntb0 + offset); + + writel(ticks_per_period, &pwm->tcntb0 + offset); val = readl(&pwm->tcon) & ~(0xf << TCON_OFFSET(pwm_id)); if (invert && (pwm_id < 4)) diff --git a/arch/arm/cpu/armv7/s5p-common/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index e78c716..6a0fa58 100644 --- a/arch/arm/cpu/armv7/s5p-common/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -39,13 +39,33 @@ static inline struct s5p_timer *s5p_get_base_timer(void) return (struct s5p_timer *)samsung_get_base_timer(); } +/** + * Read the countdown timer. + * + * This operates at 1MHz and counts downwards. It will wrap about every + * hour (2^32 microseconds). + * + * @return current value of timer + */ +static unsigned long timer_get_us_down(void) +{ + struct s5p_timer *const timer = s5p_get_base_timer(); + + return readl(&timer->tcnto4); +} + int timer_init(void) { /* PWM Timer 4 */ - pwm_init(4, MUX_DIV_2, 0); - pwm_config(4, 0, 0); + pwm_init(4, MUX_DIV_4, 0); + pwm_config(4, 100000, 100000); pwm_enable(4); + /* Use this as the current monotonic time in us */ + gd->arch.timer_reset_value = 0; + + /* Use this as the last timer value we saw */ + gd->arch.lastinc = timer_get_us_down(); reset_timer_masked(); return 0; @@ -56,81 +76,52 @@ int timer_init(void) */ unsigned long get_timer(unsigned long base) { - return get_timer_masked() - base; -} + ulong now = timer_get_us_down(); + + /* + * Increment the time by the amount elapsed since the last read. + * The timer may have wrapped around, but it makes no difference to + * our arithmetic here. + */ + gd->arch.timer_reset_value += gd->arch.lastinc - now; + gd->arch.lastinc = now; -/* delay x useconds */ -void __udelay(unsigned long usec) -{ - struct s5p_timer *const timer = s5p_get_base_timer(); - unsigned long tmo, tmp, count_value; - - count_value = readl(&timer->tcntb4); - - if (usec >= 1000) { - /* - * if "big" number, spread normalization - * to seconds - * 1. start to normalize for usec to ticks per sec - * 2. find number of "ticks" to wait to achieve target - * 3. finish normalize. - */ - tmo = usec / 1000; - tmo *= (CONFIG_SYS_HZ * count_value); - tmo /= 1000; - } else { - /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ * count_value; - tmo /= (1000 * 1000); - } - - /* get current timestamp */ - tmp = get_current_tick(); - - /* if setting this fordward will roll time stamp */ - /* reset "advancing" timestamp to 0, set lastinc value */ - /* else, set advancing stamp wake up time */ - if ((tmo + tmp + 1) < tmp) - reset_timer_masked(); - else - tmo += tmp; - - /* loop till event */ - while (get_current_tick() < tmo) - ; /* nop */ + /* Divide by 1000 to convert from us to ms */ + return gd->arch.timer_reset_value / 1000 - base; } -void reset_timer_masked(void) +unsigned long timer_get_us(void) { - struct s5p_timer *const timer = s5p_get_base_timer(); + static unsigned long base_time_us; - /* reset time */ - gd->arch.lastinc = readl(&timer->tcnto4); - gd->arch.tbl = 0; + struct s5p_timer *const timer = + (struct s5p_timer *)samsung_get_base_timer(); + unsigned long now_downward_us = readl(&timer->tcnto4); + + if (!base_time_us) + base_time_us = now_downward_us; + + /* Note that this timer counts downward. */ + return base_time_us - now_downward_us; } -unsigned long get_timer_masked(void) +/* delay x useconds */ +void __udelay(unsigned long usec) { - struct s5p_timer *const timer = s5p_get_base_timer(); - unsigned long count_value = readl(&timer->tcntb4); + unsigned long count_value; - return get_current_tick() / count_value; + count_value = timer_get_us_down(); + while ((int)(count_value - timer_get_us_down()) < (int)usec) + ; } -unsigned long get_current_tick(void) +void reset_timer_masked(void) { struct s5p_timer *const timer = s5p_get_base_timer(); - unsigned long now = readl(&timer->tcnto4); - unsigned long count_value = readl(&timer->tcntb4); - - if (gd->arch.lastinc >= now) - gd->arch.tbl += gd->arch.lastinc - now; - else - gd->arch.tbl += gd->arch.lastinc + count_value - now; - - gd->arch.lastinc = now; - return gd->arch.tbl; + /* reset time */ + gd->arch.lastinc = readl(&timer->tcnto4); + gd->arch.tbl = 0; } /* diff --git a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds index 7cd409c..15f8c01 100644 --- a/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds +++ b/arch/arm/cpu/armv7/socfpga/u-boot-spl.lds @@ -27,7 +27,7 @@ SECTIONS . = ALIGN(4); .text : { - arch/arm/cpu/armv7/start.o (.text) + arch/arm/cpu/armv7/start.o (.text*) *(.text*) } >.sdram @@ -46,7 +46,7 @@ SECTIONS __bss_start = .; *(.bss*) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } >.sdram . = ALIGN(8); diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 30f02d3..61da7ac 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -81,7 +81,11 @@ _end_vect: .globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. @@ -90,13 +94,13 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start -.global _image_copy_end_ofs +.globl _image_copy_end_ofs _image_copy_end_ofs: - .word __image_copy_end - _start + .word __image_copy_end - _start .globl _bss_end_ofs _bss_end_ofs: - .word __bss_end__ - _start + .word __bss_end - _start .globl _end_ofs _end_ofs: @@ -161,28 +165,23 @@ reset: #ifndef CONFIG_SPL_BUILD /* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. + * void relocate_code(addr_moni) * + * This function relocates the monitor code. */ ENTRY(relocate_code) - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start - cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ + subs r9, r6, r0 /* r9 <- relocation offset */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r1!, {r9-r10} /* copy to target address [r1] */ + ldmia r0!, {r10-r11} /* copy from source address [r0] */ + stmia r1!, {r10-r11} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop @@ -190,7 +189,6 @@ copy_loop: * fix .rel.dyn relocations */ ldr r0, _TEXT_BASE /* r0 <- Text base */ - sub r9, r6, r0 /* r9 <- relocation offset */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ add r10, r10, r0 /* r10 <- sym table in FLASH */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ @@ -254,7 +252,6 @@ ENTRY(c_runtime_cpu_setup) #if !defined(CONFIG_TEGRA) /* Set vector address in CP15 VBAR register */ ldr r0, =_start - add r0, r0, r9 mcr p15, 0, r0, c12, c0, 0 @Set VBAR #endif /* !Tegra */ @@ -310,6 +307,12 @@ ENTRY(cpu_init_cp15) #endif mcr p15, 0, r0, c1, c0, 0 +#ifdef CONFIG_ARM_ERRATA_716044 + mrc p15, 0, r0, c1, c0, 0 @ read system control register + orr r0, r0, #1 << 11 @ set bit #11 + mcr p15, 0, r0, c1, c0, 0 @ write system control register +#endif + #ifdef CONFIG_ARM_ERRATA_742230 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register orr r0, r0, #1 << 4 @ set bit #4 @@ -460,9 +463,10 @@ ENDPROC(cpu_init_crit) @ spots for abort stack str lr, [r0] @ save caller lr in position 0 @ of saved stack - mrs r0, spsr @ get the spsr + mrs lr, spsr @ get the spsr str lr, [r0, #4] @ save spsr in position 1 of @ saved stack + ldr lr, [r0] @ restore lr ldr r0, [r13] @ restore r0 add r13, r13, #4 @ pop stack entry .endm diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index efb5a40..69ef8aa 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -98,7 +98,11 @@ _fiq: .word fiq .globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. @@ -110,9 +114,13 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start +.globl _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: - .word __bss_end__ - _start + .word __bss_end - _start .globl _end_ofs _end_ofs: @@ -250,29 +258,24 @@ reset: /*------------------------------------------------------------------------------*/ /* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. + * void relocate_code(addr_moni) * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start - cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ + subs r9, r6, r0 /* r9 <- relocation offset */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r1!, {r9-r10} /* copy to target address [r1] */ + ldmia r0!, {r10-r11} /* copy from source address [r0] */ + stmia r1!, {r10-r11} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop @@ -281,7 +284,6 @@ copy_loop: * fix .rel.dyn relocations */ ldr r0, _TEXT_BASE /* r0 <- Text base */ - sub r9, r6, r0 /* r9 <- relocation offset */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ add r10, r10, r0 /* r10 <- sym table in FLASH */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds index 5e66dd1..553589c 100644 --- a/arch/arm/cpu/ixp/u-boot.lds +++ b/arch/arm/cpu/ixp/u-boot.lds @@ -54,6 +54,8 @@ SECTIONS . = ALIGN(4); + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) @@ -67,17 +69,23 @@ SECTIONS _end = .; +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + .bss_start __rel_dyn_start (OVERLAY) : { KEEP(*(.__bss_start)); + __bss_base = .; } - .bss __bss_start (OVERLAY) : { + .bss __bss_base (OVERLAY) : { *(.bss*) . = ALIGN(4); - ___bssend___ = .; + __bss_limit = .; } - .bss_end ___bssend___ (OVERLAY) : { - KEEP(*(.__bss_end__)); + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); } /DISCARD/ : { *(.dynstr*) } diff --git a/arch/arm/cpu/pxa/Makefile b/arch/arm/cpu/pxa/Makefile index e088832..9f63c34 100644 --- a/arch/arm/cpu/pxa/Makefile +++ b/arch/arm/cpu/pxa/Makefile @@ -33,7 +33,6 @@ COBJS-$(CONFIG_CPU_PXA27X) = pxa2xx.o COBJS-y += cpuinfo.o COBJS = $(COBJS-y) -COBJS += pxafb.o COBJS += timer.o COBJS += usb.o diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index e71803e..ada91a6 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -102,7 +102,7 @@ _end_vect: .globl _TEXT_BASE _TEXT_BASE: -#ifdef CONFIG_SPL_BUILD +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) .word CONFIG_SPL_TEXT_BASE #else .word CONFIG_SYS_TEXT_BASE @@ -118,9 +118,13 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start +.globl _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: - .word __bss_end__ - _start + .word __bss_end - _start .globl _end_ofs _end_ofs: @@ -169,17 +173,13 @@ reset: /*------------------------------------------------------------------------------*/ #ifndef CONFIG_SPL_BUILD /* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. + * void relocate_code(addr_moni) * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ /* Disable the Dcache RAM lock for stack now */ #ifdef CONFIG_CPU_PXA25X @@ -189,16 +189,15 @@ relocate_code: #endif adr r0, _start - cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ + subs r9, r6, r0 /* r9 <- relocation offset */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r1!, {r9-r10} /* copy to target address [r1] */ + ldmia r0!, {r10-r11} /* copy from source address [r0] */ + stmia r1!, {r10-r11} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop @@ -207,7 +206,6 @@ copy_loop: * fix .rel.dyn relocations */ ldr r0, _TEXT_BASE /* r0 <- Text base */ - sub r9, r6, r0 /* r9 <- relocation offset */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ add r10, r10, r0 /* r10 <- sym table in FLASH */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ @@ -387,8 +385,9 @@ cpu_init_crit: str r0, [r13] @ save R0's value. ldr r0, IRQ_STACK_START_IN @ get data regions start str lr, [r0] @ save caller lr in position 0 of saved stack - mrs r0, spsr @ get the spsr + mrs lr, spsr @ get the spsr str lr, [r0, #4] @ save spsr in position 1 of saved stack + ldr lr, [r0] @ restore lr ldr r0, [r13] @ restore r0 add r13, r13, #4 @ pop stack entry .endm diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index 4528c91..7361aa2 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -64,7 +64,11 @@ _start: b reset .globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. @@ -76,9 +80,13 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start +.globl _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: - .word __bss_end__ - _start + .word __bss_end - _start .globl _end_ofs _end_ofs: @@ -133,29 +141,24 @@ reset: /*------------------------------------------------------------------------------*/ /* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. + * void relocate_code(addr_moni) * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start - cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ + subs r9, r6, r0 /* r9 <- relocation offset */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r1!, {r9-r10} /* copy to target address [r1] */ + ldmia r0!, {r10-r11} /* copy from source address [r0] */ + stmia r1!, {r10-r11} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop @@ -164,7 +167,6 @@ copy_loop: * fix .rel.dyn relocations */ ldr r0, _TEXT_BASE /* r0 <- Text base */ - sub r9, r6, r0 /* r9 <- relocation offset */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ add r10, r10, r0 /* r10 <- sym table in FLASH */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index 3144299..8a2eafd 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -74,7 +74,11 @@ _fiq: .word fiq .globl _TEXT_BASE _TEXT_BASE: +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) + .word CONFIG_SPL_TEXT_BASE +#else .word CONFIG_SYS_TEXT_BASE +#endif /* * These are defined in the board-specific linker script. @@ -86,9 +90,13 @@ _TEXT_BASE: _bss_start_ofs: .word __bss_start - _start +.globl _image_copy_end_ofs +_image_copy_end_ofs: + .word __image_copy_end - _start + .globl _bss_end_ofs _bss_end_ofs: - .word __bss_end__ - _start + .word __bss_end - _start .globl _end_ofs _end_ofs: @@ -137,29 +145,24 @@ reset: /*------------------------------------------------------------------------------*/ /* - * void relocate_code (addr_sp, gd, addr_moni) - * - * This "function" does not return, instead it continues in RAM - * after relocating the monitor code. + * void relocate_code(addr_moni) * + * This function relocates the monitor code. */ .globl relocate_code relocate_code: - mov r4, r0 /* save addr_sp */ - mov r5, r1 /* save addr of gd */ - mov r6, r2 /* save addr of destination */ + mov r6, r0 /* save addr of destination */ adr r0, _start - cmp r0, r6 - moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */ + subs r9, r6, r0 /* r9 <- relocation offset */ beq relocate_done /* skip relocation */ mov r1, r6 /* r1 <- scratch for copy_loop */ - ldr r3, _bss_start_ofs + ldr r3, _image_copy_end_ofs add r2, r0, r3 /* r2 <- source end address */ copy_loop: - ldmia r0!, {r9-r10} /* copy from source address [r0] */ - stmia r1!, {r9-r10} /* copy to target address [r1] */ + ldmia r0!, {r10-r11} /* copy from source address [r0] */ + stmia r1!, {r10-r11} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ blo copy_loop @@ -168,7 +171,6 @@ copy_loop: * fix .rel.dyn relocations */ ldr r0, _TEXT_BASE /* r0 <- Text base */ - sub r9, r6, r0 /* r9 <- relocation offset */ ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ add r10, r10, r0 /* r10 <- sym table in FLASH */ ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 8321afb..3c0d99ca 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -78,7 +78,7 @@ SECTIONS __bss_start = .; *(.bss*) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } /DISCARD/ : { *(.dynstr*) } @@ -89,5 +89,5 @@ SECTIONS } #if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE) -ASSERT(__bss_end__ < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big"); +ASSERT(__bss_end < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big"); #endif diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index d4ad352..d5e42d3a 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -81,17 +81,24 @@ SECTIONS *(.mmutable) } +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + .bss_start __rel_dyn_start (OVERLAY) : { KEEP(*(.__bss_start)); + __bss_base = .; } - .bss __bss_start (OVERLAY) : { + .bss __bss_base (OVERLAY) : { *(.bss*) . = ALIGN(4); - ___bssend___ = .; + __bss_limit = .; } - .bss_end ___bssend___ (OVERLAY) : { - KEEP(*(.__bss_end__)); + + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); } /DISCARD/ : { *(.dynstr*) } @@ -102,5 +109,5 @@ SECTIONS } #if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE) -ASSERT(__bss_end__ < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big"); +ASSERT(__bss_end < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big"); #endif diff --git a/arch/arm/dts/exynos5250.dtsi b/arch/arm/dts/exynos5250.dtsi index ed8c8dd..df4b231 100644 --- a/arch/arm/dts/exynos5250.dtsi +++ b/arch/arm/dts/exynos5250.dtsi @@ -151,4 +151,22 @@ }; }; + tmu@10060000 { + compatible = "samsung,exynos-tmu"; + reg = <0x10060000 0x10000>; + }; + + fimd@14400000 { + compatible = "samsung,exynos-fimd"; + reg = <0x14400000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + dp@145b0000 { + compatible = "samsung,exynos5-dp"; + reg = <0x145b0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; }; diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index 701c0f9..f86d18d 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -9,6 +9,43 @@ #clock-cells = <1>; }; + apbdma: dma { + compatible = "nvidia,tegra114-apbdma", "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; + reg = <0x6000a000 0x1400>; + interrupts = <0 104 0x04 + 0 105 0x04 + 0 106 0x04 + 0 107 0x04 + 0 108 0x04 + 0 109 0x04 + 0 110 0x04 + 0 111 0x04 + 0 112 0x04 + 0 113 0x04 + 0 114 0x04 + 0 115 0x04 + 0 116 0x04 + 0 117 0x04 + 0 118 0x04 + 0 119 0x04 + 0 128 0x04 + 0 129 0x04 + 0 130 0x04 + 0 131 0x04 + 0 132 0x04 + 0 133 0x04 + 0 134 0x04 + 0 135 0x04 + 0 136 0x04 + 0 137 0x04 + 0 138 0x04 + 0 139 0x04 + 0 140 0x04 + 0 141 0x04 + 0 142 0x04 + 0 143 0x04>; + }; + gpio: gpio { compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; reg = <0x6000d000 0x1000>; @@ -75,4 +112,108 @@ clocks = <&tegra_car 47>; status = "disabled"; }; + + spi@7000d400 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d400 0x200>; + interrupts = <0 59 0x04>; + nvidia,dma-request-selector = <&apbdma 15>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + /* PERIPH_ID_SBC1, PLLP_OUT0 */ + clocks = <&tegra_car 41>; + }; + + spi@7000d600 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d600 0x200>; + interrupts = <0 82 0x04>; + nvidia,dma-request-selector = <&apbdma 16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + /* PERIPH_ID_SBC2, PLLP_OUT0 */ + clocks = <&tegra_car 44>; + }; + + spi@7000d800 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000d480 0x200>; + interrupts = <0 83 0x04>; + nvidia,dma-request-selector = <&apbdma 17>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + /* PERIPH_ID_SBC3, PLLP_OUT0 */ + clocks = <&tegra_car 46>; + }; + + spi@7000da00 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000da00 0x200>; + interrupts = <0 93 0x04>; + nvidia,dma-request-selector = <&apbdma 18>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + /* PERIPH_ID_SBC4, PLLP_OUT0 */ + clocks = <&tegra_car 68>; + }; + + spi@7000dc00 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000dc00 0x200>; + interrupts = <0 94 0x04>; + nvidia,dma-request-selector = <&apbdma 27>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + /* PERIPH_ID_SBC5, PLLP_OUT0 */ + clocks = <&tegra_car 104>; + }; + + spi@7000de00 { + compatible = "nvidia,tegra114-spi"; + reg = <0x7000de00 0x200>; + interrupts = <0 79 0x04>; + nvidia,dma-request-selector = <&apbdma 28>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + /* PERIPH_ID_SBC6, PLLP_OUT0 */ + clocks = <&tegra_car 105>; + }; + + sdhci@78000000 { + compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; + reg = <0x78000000 0x200>; + interrupts = <0 14 0x04>; + clocks = <&tegra_car 14>; + status = "disable"; + }; + + sdhci@78000200 { + compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; + reg = <0x78000200 0x200>; + interrupts = <0 15 0x04>; + clocks = <&tegra_car 9>; + status = "disable"; + }; + + sdhci@78000400 { + compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; + reg = <0x78000400 0x200>; + interrupts = <0 19 0x04>; + clocks = <&tegra_car 69>; + status = "disable"; + }; + + sdhci@78000600 { + compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; + reg = <0x78000600 0x200>; + interrupts = <0 31 0x04>; + clocks = <&tegra_car 15>; + status = "disable"; + }; }; diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 428a57e..44b6822 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -55,6 +55,23 @@ $(OBJTREE)/SPL: $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/$(patsubst "%",%,$(CONF $(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \ -e $(CONFIG_SPL_TEXT_BASE) -d $< $@ +$(OBJTREE)/u-boot-with-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \ + -I binary -O binary $< $(OBJTREE)/spl/u-boot-spl-pad.imx + cat $(OBJTREE)/spl/u-boot-spl-pad.imx $(OBJTREE)/u-boot.bin > $@ + rm $(OBJTREE)/spl/u-boot-spl-pad.imx + +$(OBJTREE)/u-boot-with-nand-spl.imx: $(OBJTREE)/SPL $(OBJTREE)/u-boot.bin + (echo -ne '\x00\x00\x00\x00\x46\x43\x42\x20\x01' && \ + dd bs=1015 count=1 if=/dev/zero 2>/dev/null) | \ + cat - $< > $(OBJTREE)/spl/u-boot-nand-spl.imx + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \ + -I binary -O binary $(OBJTREE)/spl/u-boot-nand-spl.imx \ + $(OBJTREE)/spl/u-boot-nand-spl-pad.imx + rm $(OBJTREE)/spl/u-boot-nand-spl.imx + cat $(OBJTREE)/spl/u-boot-nand-spl-pad.imx $(OBJTREE)/u-boot.bin > $@ + rm $(OBJTREE)/spl/u-boot-nand-spl-pad.imx + ######################################################################### diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 872ff82..ecb5901 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -3,7 +3,7 @@ * * clock header * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2011, Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index d748dd2..89b63d9 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -3,7 +3,7 @@ * * AM33xx clock define * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,37 +19,13 @@ #ifndef _CLOCKS_AM33XX_H_ #define _CLOCKS_AM33XX_H_ -#define OSC (V_OSCK/1000000) - -/* MAIN PLL Fdll = 550 MHZ, */ -#define MPUPLL_M 550 -#define MPUPLL_N (OSC-1) -#define MPUPLL_M2 1 - -/* Core PLL Fdll = 1 GHZ, */ -#define COREPLL_M 1000 -#define COREPLL_N (OSC-1) - -#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */ -#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */ -#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */ - -/* - * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll - * frequency needs to be set to 960 MHZ. Hence, - * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below - */ -#define PERPLL_M 960 -#define PERPLL_N (OSC-1) -#define PERPLL_M2 5 - -/* DDR Freq is 266 MHZ for now */ -/* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ -#define DDRPLL_M 266 -#define DDRPLL_N (OSC-1) -#define DDRPLL_M2 1 +/* MAIN PLL Fdll = 550 MHz, by default */ +#ifndef CONFIG_SYS_MPUCLK +#define CONFIG_SYS_MPUCLK 550 +#endif extern void pll_init(void); extern void enable_emif_clocks(void); +extern void enable_dmm_clocks(void); #endif /* endif _CLOCKS_AM33XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 16e8a80..3d3a7c8 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -42,9 +42,10 @@ #define HS_DEVICE 0x2 #define GP_DEVICE 0x3 -/* cpu-id for AM33XX family */ +/* cpu-id for AM33XX and TI81XX family */ #define AM335X 0xB944 -#define DEVICE_ID 0x44E10600 +#define TI81XX 0xB81E +#define DEVICE_ID (CTRL_BASE + 0x0600) /* This gives the status of the boot mode pins on the evm */ #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ @@ -52,9 +53,11 @@ /* Reset control */ #ifdef CONFIG_AM33XX -#define PRM_RSTCTRL 0x44E00F00 -#define PRM_RSTST 0x44E00F08 +#define PRM_RSTCTRL (PRCM_BASE + 0x0F00) +#elif defined(CONFIG_TI814X) +#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) #endif +#define PRM_RSTST (PRM_RSTCTRL + 8) #define PRM_RSTCTRL_RESET 0x01 #define PRM_RSTST_WARM_RESET_MASK 0x232 diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index ae43ef8..fb4e78e 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -28,6 +28,7 @@ #define VTP_CTRL_START_EN (0x1) #define PHY_DLL_LOCK_DIFF 0x0 #define DDR_CKE_CTRL_NORMAL 0x1 +#define PHY_EN_DYN_PWRDN (0x1 << 20) /* Micron MT47H128M16RT-25E */ #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005 @@ -82,6 +83,23 @@ #define MT41J256M8HX15E_PHY_FIFO_WE 0x100 #define MT41J256M8HX15E_IOCTRL_VALUE 0x18B +/* Micron MT41K256M16HA-125E */ +#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007 +#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB +#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA +#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F +#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 +#define MT41K256M16HA125E_EMIF_SDREF 0xC30 +#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 +#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1 +#define MT41K256M16HA125E_RATIO 0x80 +#define MT41K256M16HA125E_INVERT_CLKOUT 0x0 +#define MT41K256M16HA125E_RD_DQS 0x38 +#define MT41K256M16HA125E_WR_DQS 0x44 +#define MT41K256M16HA125E_PHY_WR_DATA 0x7D +#define MT41K256M16HA125E_PHY_FIFO_WE 0x94 +#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B + /* Micron MT41J512M8RH-125 on EVM v1.5 */ #define MT41J512M8RH125_EMIF_READ_LATENCY 0x06 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B @@ -100,19 +118,64 @@ #define MT41J512M8RH125_IOCTRL_VALUE 0x18B /** + * Configure DMM + */ +void config_dmm(const struct dmm_lisa_map_regs *regs); + +/** * Configure SDRAM */ -void config_sdram(const struct emif_regs *regs); +void config_sdram(const struct emif_regs *regs, int nr); /** * Set SDRAM timings */ -void set_sdram_timings(const struct emif_regs *regs); +void set_sdram_timings(const struct emif_regs *regs, int nr); /** * Configure DDR PHY */ -void config_ddr_phy(const struct emif_regs *regs); +void config_ddr_phy(const struct emif_regs *regs, int nr); + +struct ddr_cmd_regs { + unsigned int resv0[7]; + unsigned int cm0csratio; /* offset 0x01C */ + unsigned int resv1[2]; + unsigned int cm0dldiff; /* offset 0x028 */ + unsigned int cm0iclkout; /* offset 0x02C */ + unsigned int resv2[8]; + unsigned int cm1csratio; /* offset 0x050 */ + unsigned int resv3[2]; + unsigned int cm1dldiff; /* offset 0x05C */ + unsigned int cm1iclkout; /* offset 0x060 */ + unsigned int resv4[8]; + unsigned int cm2csratio; /* offset 0x084 */ + unsigned int resv5[2]; + unsigned int cm2dldiff; /* offset 0x090 */ + unsigned int cm2iclkout; /* offset 0x094 */ + unsigned int resv6[3]; +}; + +struct ddr_data_regs { + unsigned int dt0rdsratio0; /* offset 0x0C8 */ + unsigned int resv1[4]; + unsigned int dt0wdsratio0; /* offset 0x0DC */ + unsigned int resv2[4]; + unsigned int dt0wiratio0; /* offset 0x0F0 */ + unsigned int resv3; + unsigned int dt0wimode0; /* offset 0x0F8 */ + unsigned int dt0giratio0; /* offset 0x0FC */ + unsigned int resv4; + unsigned int dt0gimode0; /* offset 0x104 */ + unsigned int dt0fwsratio0; /* offset 0x108 */ + unsigned int resv5[4]; + unsigned int dt0dqoffset; /* offset 0x11C */ + unsigned int dt0wrsratio0; /* offset 0x120 */ + unsigned int resv6[4]; + unsigned int dt0rdelays0; /* offset 0x134 */ + unsigned int dt0dldiff0; /* offset 0x138 */ + unsigned int resv7[12]; +}; /** * This structure represents the DDR registers on AM33XX devices. @@ -193,12 +256,12 @@ struct ddr_data { /** * Configure DDR CMD control registers */ -void config_cmd_ctrl(const struct cmd_control *cmd); +void config_cmd_ctrl(const struct cmd_control *cmd, int nr); /** * Configure DDR DATA registers */ -void config_ddr_data(int data_macrono, const struct ddr_data *data); +void config_ddr_data(const struct ddr_data *data, int nr); /** * This structure represents the DDR io control on AM33XX devices. @@ -226,6 +289,6 @@ struct ddr_ctrl { void config_ddr(unsigned int pll, unsigned int ioctrl, const struct ddr_data *data, const struct cmd_control *ctrl, - const struct emif_regs *regs); + const struct emif_regs *regs, int nr); #endif /* _DDR_DEFS_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 6dd3296..5a27f9c 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -3,7 +3,7 @@ * * hardware specific header * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,10 +19,17 @@ #ifndef __AM33XX_HARDWARE_H #define __AM33XX_HARDWARE_H +#include <config.h> #include <asm/arch/omap.h> +#ifdef CONFIG_AM33XX +#include <asm/arch/hardware_am33xx.h> +#elif defined(CONFIG_TI814X) +#include <asm/arch/hardware_ti814x.h> +#endif -/* Module base addresses */ -#define UART0_BASE 0x44E09000 +/* + * Common hardware definitions + */ /* DM Timer base addresses */ #define DM_TIMER0_BASE 0x4802C000 @@ -37,21 +44,10 @@ /* GPIO Base address */ #define GPIO0_BASE 0x48032000 #define GPIO1_BASE 0x4804C000 -#define GPIO2_BASE 0x481AC000 /* BCH Error Location Module */ #define ELM_BASE 0x48080000 -/* Watchdog Timer */ -#define WDT_BASE 0x44E35000 - -/* Control Module Base Address */ -#define CTRL_BASE 0x44E10000 -#define CTRL_DEVICE_BASE 0x44E10600 - -/* PRCM Base Address */ -#define PRCM_BASE 0x44E00000 - /* EMIF Base address */ #define EMIF4_0_CFG_BASE 0x4C000000 #define EMIF4_1_CFG_BASE 0x4D000000 @@ -66,13 +62,13 @@ #define PRM_DEVICE 0x44E00F00 /* VTP Base address */ -#define VTP0_CTRL_ADDR 0x44E10E0C +#define VTP1_CTRL_ADDR 0x48140E10 /* DDR Base address */ #define DDR_CTRL_ADDR 0x44E10E04 #define DDR_CONTROL_BASE_ADDR 0x44E11404 -#define DDR_PHY_BASE_ADDR 0x44E12000 -#define DDR_PHY_BASE_ADDR2 0x44E120A4 +#define DDR_PHY_CMD_ADDR2 0x47C0C800 +#define DDR_PHY_DATA_ADDR2 0x47C0C8C8 /* UART */ #define DEFAULT_UART_BASE UART0_BASE @@ -84,14 +80,10 @@ #define GPMC_BASE 0x50000000 /* CPSW Config space */ -#define AM335X_CPSW_BASE 0x4A100000 -#define AM335X_CPSW_MDIO_BASE 0x4A101000 - -/* RTC base address */ -#define AM335X_RTC_BASE 0x44E3E000 +#define CPSW_BASE 0x4A100000 /* OTG */ -#define AM335X_USB0_OTG_BASE 0x47401000 -#define AM335X_USB1_OTG_BASE 0x47401800 +#define USB0_OTG_BASE 0x47401000 +#define USB1_OTG_BASE 0x47401800 #endif /* __AM33XX_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h new file mode 100644 index 0000000..fa02f19 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -0,0 +1,54 @@ +/* + * hardware_am33xx.h + * + * AM33xx hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AM33XX_HARDWARE_AM33XX_H +#define __AM33XX_HARDWARE_AM33XX_H + +/* Module base addresses */ + +/* UART Base Address */ +#define UART0_BASE 0x44E09000 + +/* GPIO Base address */ +#define GPIO2_BASE 0x481AC000 + +/* Watchdog Timer */ +#define WDT_BASE 0x44E35000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x44E10000 +#define CTRL_DEVICE_BASE 0x44E10600 + +/* PRCM Base Address */ +#define PRCM_BASE 0x44E00000 + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x44E10E0C + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x44E12000 +#define DDR_PHY_DATA_ADDR 0x44E120C8 +#define DDR_DATA_REGS_NR 2 + +/* CPSW Config space */ +#define CPSW_MDIO_BASE 0x4A101000 + +/* RTC base address */ +#define RTC_BASE 0x44E3E000 + +#endif /* __AM33XX_HARDWARE_AM33XX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h new file mode 100644 index 0000000..a950ac3 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/hardware_ti814x.h @@ -0,0 +1,53 @@ +/* + * hardware_ti814x.h + * + * TI814x hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AM33XX_HARDWARE_TI814X_H +#define __AM33XX_HARDWARE_TI814X_H + +/* Module base addresses */ + +/* UART Base Address */ +#define UART0_BASE 0x48020000 + +/* Watchdog Timer */ +#define WDT_BASE 0x481C7000 + +/* Control Module Base Address */ +#define CTRL_BASE 0x48140000 + +/* PRCM Base Address */ +#define PRCM_BASE 0x48180000 + +/* PLL Subsystem Base Address */ +#define PLL_SUBSYS_BASE 0x481C5000 + +/* VTP Base address */ +#define VTP0_CTRL_ADDR 0x48140E0C + +/* DDR Base address */ +#define DDR_PHY_CMD_ADDR 0x47C0C400 +#define DDR_PHY_DATA_ADDR 0x47C0C4C8 +#define DDR_DATA_REGS_NR 4 + +/* CPSW Config space */ +#define CPSW_MDIO_BASE 0x4A100800 + +/* RTC base address */ +#define RTC_BASE 0x480C0000 + +#endif /* __AM33XX_HARDWARE_TI814X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index 33c9c83..51ba791 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -24,4 +24,9 @@ #define OMAP_HSMMC1_BASE 0x48060100 #define OMAP_HSMMC2_BASE 0x481D8100 +#if defined(CONFIG_TI814X) +#undef MMC_CLOCK_REFERENCE +#define MMC_CLOCK_REFERENCE 192 /* MHz */ +#endif + #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h index 460ac1c..1c6b65f 100644 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -1,7 +1,7 @@ /* * mux.h * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -19,234 +19,15 @@ #include <common.h> #include <asm/io.h> -#define MUX_CFG(value, offset) \ - __raw_writel(value, (CTRL_BASE + offset)); - -/* PAD Control Fields */ -#define SLEWCTRL (0x1 << 6) -#define RXACTIVE (0x1 << 5) -#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ -#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ -#define PULLUDEN (0x0 << 3) /* Pull up enabled */ -#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ -#define MODE(val) val /* used for Readability */ - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -struct pad_signals { - int gpmc_ad0; - int gpmc_ad1; - int gpmc_ad2; - int gpmc_ad3; - int gpmc_ad4; - int gpmc_ad5; - int gpmc_ad6; - int gpmc_ad7; - int gpmc_ad8; - int gpmc_ad9; - int gpmc_ad10; - int gpmc_ad11; - int gpmc_ad12; - int gpmc_ad13; - int gpmc_ad14; - int gpmc_ad15; - int gpmc_a0; - int gpmc_a1; - int gpmc_a2; - int gpmc_a3; - int gpmc_a4; - int gpmc_a5; - int gpmc_a6; - int gpmc_a7; - int gpmc_a8; - int gpmc_a9; - int gpmc_a10; - int gpmc_a11; - int gpmc_wait0; - int gpmc_wpn; - int gpmc_be1n; - int gpmc_csn0; - int gpmc_csn1; - int gpmc_csn2; - int gpmc_csn3; - int gpmc_clk; - int gpmc_advn_ale; - int gpmc_oen_ren; - int gpmc_wen; - int gpmc_be0n_cle; - int lcd_data0; - int lcd_data1; - int lcd_data2; - int lcd_data3; - int lcd_data4; - int lcd_data5; - int lcd_data6; - int lcd_data7; - int lcd_data8; - int lcd_data9; - int lcd_data10; - int lcd_data11; - int lcd_data12; - int lcd_data13; - int lcd_data14; - int lcd_data15; - int lcd_vsync; - int lcd_hsync; - int lcd_pclk; - int lcd_ac_bias_en; - int mmc0_dat3; - int mmc0_dat2; - int mmc0_dat1; - int mmc0_dat0; - int mmc0_clk; - int mmc0_cmd; - int mii1_col; - int mii1_crs; - int mii1_rxerr; - int mii1_txen; - int mii1_rxdv; - int mii1_txd3; - int mii1_txd2; - int mii1_txd1; - int mii1_txd0; - int mii1_txclk; - int mii1_rxclk; - int mii1_rxd3; - int mii1_rxd2; - int mii1_rxd1; - int mii1_rxd0; - int rmii1_refclk; - int mdio_data; - int mdio_clk; - int spi0_sclk; - int spi0_d0; - int spi0_d1; - int spi0_cs0; - int spi0_cs1; - int ecap0_in_pwm0_out; - int uart0_ctsn; - int uart0_rtsn; - int uart0_rxd; - int uart0_txd; - int uart1_ctsn; - int uart1_rtsn; - int uart1_rxd; - int uart1_txd; - int i2c0_sda; - int i2c0_scl; - int mcasp0_aclkx; - int mcasp0_fsx; - int mcasp0_axr0; - int mcasp0_ahclkr; - int mcasp0_aclkr; - int mcasp0_fsr; - int mcasp0_axr1; - int mcasp0_ahclkx; - int xdma_event_intr0; - int xdma_event_intr1; - int nresetin_out; - int porz; - int nnmi; - int osc0_in; - int osc0_out; - int rsvd1; - int tms; - int tdi; - int tdo; - int tck; - int ntrst; - int emu0; - int emu1; - int osc1_in; - int osc1_out; - int pmic_power_en; - int rtc_porz; - int rsvd2; - int ext_wakeup; - int enz_kaldo_1p8v; - int usb0_dm; - int usb0_dp; - int usb0_ce; - int usb0_id; - int usb0_vbus; - int usb0_drvvbus; - int usb1_dm; - int usb1_dp; - int usb1_ce; - int usb1_id; - int usb1_vbus; - int usb1_drvvbus; - int ddr_resetn; - int ddr_csn0; - int ddr_cke; - int ddr_ck; - int ddr_nck; - int ddr_casn; - int ddr_rasn; - int ddr_wen; - int ddr_ba0; - int ddr_ba1; - int ddr_ba2; - int ddr_a0; - int ddr_a1; - int ddr_a2; - int ddr_a3; - int ddr_a4; - int ddr_a5; - int ddr_a6; - int ddr_a7; - int ddr_a8; - int ddr_a9; - int ddr_a10; - int ddr_a11; - int ddr_a12; - int ddr_a13; - int ddr_a14; - int ddr_a15; - int ddr_odt; - int ddr_d0; - int ddr_d1; - int ddr_d2; - int ddr_d3; - int ddr_d4; - int ddr_d5; - int ddr_d6; - int ddr_d7; - int ddr_d8; - int ddr_d9; - int ddr_d10; - int ddr_d11; - int ddr_d12; - int ddr_d13; - int ddr_d14; - int ddr_d15; - int ddr_dqm0; - int ddr_dqm1; - int ddr_dqs0; - int ddr_dqsn0; - int ddr_dqs1; - int ddr_dqsn1; - int ddr_vref; - int ddr_vtp; - int ddr_strben0; - int ddr_strben1; - int ain7; - int ain6; - int ain5; - int ain4; - int ain3; - int ain2; - int ain1; - int ain0; - int vrefp; - int vrefn; -}; +#ifdef CONFIG_AM33XX +#include <asm/arch/mux_am33xx.h> +#elif defined(CONFIG_TI814X) +#include <asm/arch/mux_ti814x.h> +#endif struct module_pin_mux { short reg_offset; - unsigned char val; + unsigned int val; }; /* Pad control register offset */ @@ -259,4 +40,4 @@ struct module_pin_mux { */ void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux); -#endif +#endif /* endif _MUX_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mux_am33xx.h b/arch/arm/include/asm/arch-am33xx/mux_am33xx.h new file mode 100644 index 0000000..d5cab3e --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux_am33xx.h @@ -0,0 +1,247 @@ +/* + * mux_am33xx.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_AM33XX_H_ +#define _MUX_AM33XX_H_ + +#include <common.h> +#include <asm/io.h> + +#define MUX_CFG(value, offset) \ + __raw_writel(value, (CTRL_BASE + offset)); + +/* PAD Control Fields */ +#define SLEWCTRL (0x1 << 6) +#define RXACTIVE (0x1 << 5) +#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ +#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) val /* used for Readability */ + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int gpmc_ad0; + int gpmc_ad1; + int gpmc_ad2; + int gpmc_ad3; + int gpmc_ad4; + int gpmc_ad5; + int gpmc_ad6; + int gpmc_ad7; + int gpmc_ad8; + int gpmc_ad9; + int gpmc_ad10; + int gpmc_ad11; + int gpmc_ad12; + int gpmc_ad13; + int gpmc_ad14; + int gpmc_ad15; + int gpmc_a0; + int gpmc_a1; + int gpmc_a2; + int gpmc_a3; + int gpmc_a4; + int gpmc_a5; + int gpmc_a6; + int gpmc_a7; + int gpmc_a8; + int gpmc_a9; + int gpmc_a10; + int gpmc_a11; + int gpmc_wait0; + int gpmc_wpn; + int gpmc_be1n; + int gpmc_csn0; + int gpmc_csn1; + int gpmc_csn2; + int gpmc_csn3; + int gpmc_clk; + int gpmc_advn_ale; + int gpmc_oen_ren; + int gpmc_wen; + int gpmc_be0n_cle; + int lcd_data0; + int lcd_data1; + int lcd_data2; + int lcd_data3; + int lcd_data4; + int lcd_data5; + int lcd_data6; + int lcd_data7; + int lcd_data8; + int lcd_data9; + int lcd_data10; + int lcd_data11; + int lcd_data12; + int lcd_data13; + int lcd_data14; + int lcd_data15; + int lcd_vsync; + int lcd_hsync; + int lcd_pclk; + int lcd_ac_bias_en; + int mmc0_dat3; + int mmc0_dat2; + int mmc0_dat1; + int mmc0_dat0; + int mmc0_clk; + int mmc0_cmd; + int mii1_col; + int mii1_crs; + int mii1_rxerr; + int mii1_txen; + int mii1_rxdv; + int mii1_txd3; + int mii1_txd2; + int mii1_txd1; + int mii1_txd0; + int mii1_txclk; + int mii1_rxclk; + int mii1_rxd3; + int mii1_rxd2; + int mii1_rxd1; + int mii1_rxd0; + int rmii1_refclk; + int mdio_data; + int mdio_clk; + int spi0_sclk; + int spi0_d0; + int spi0_d1; + int spi0_cs0; + int spi0_cs1; + int ecap0_in_pwm0_out; + int uart0_ctsn; + int uart0_rtsn; + int uart0_rxd; + int uart0_txd; + int uart1_ctsn; + int uart1_rtsn; + int uart1_rxd; + int uart1_txd; + int i2c0_sda; + int i2c0_scl; + int mcasp0_aclkx; + int mcasp0_fsx; + int mcasp0_axr0; + int mcasp0_ahclkr; + int mcasp0_aclkr; + int mcasp0_fsr; + int mcasp0_axr1; + int mcasp0_ahclkx; + int xdma_event_intr0; + int xdma_event_intr1; + int nresetin_out; + int porz; + int nnmi; + int osc0_in; + int osc0_out; + int rsvd1; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int pmic_power_en; + int rtc_porz; + int rsvd2; + int ext_wakeup; + int enz_kaldo_1p8v; + int usb0_dm; + int usb0_dp; + int usb0_ce; + int usb0_id; + int usb0_vbus; + int usb0_drvvbus; + int usb1_dm; + int usb1_dp; + int usb1_ce; + int usb1_id; + int usb1_vbus; + int usb1_drvvbus; + int ddr_resetn; + int ddr_csn0; + int ddr_cke; + int ddr_ck; + int ddr_nck; + int ddr_casn; + int ddr_rasn; + int ddr_wen; + int ddr_ba0; + int ddr_ba1; + int ddr_ba2; + int ddr_a0; + int ddr_a1; + int ddr_a2; + int ddr_a3; + int ddr_a4; + int ddr_a5; + int ddr_a6; + int ddr_a7; + int ddr_a8; + int ddr_a9; + int ddr_a10; + int ddr_a11; + int ddr_a12; + int ddr_a13; + int ddr_a14; + int ddr_a15; + int ddr_odt; + int ddr_d0; + int ddr_d1; + int ddr_d2; + int ddr_d3; + int ddr_d4; + int ddr_d5; + int ddr_d6; + int ddr_d7; + int ddr_d8; + int ddr_d9; + int ddr_d10; + int ddr_d11; + int ddr_d12; + int ddr_d13; + int ddr_d14; + int ddr_d15; + int ddr_dqm0; + int ddr_dqm1; + int ddr_dqs0; + int ddr_dqsn0; + int ddr_dqs1; + int ddr_dqsn1; + int ddr_vref; + int ddr_vtp; + int ddr_strben0; + int ddr_strben1; + int ain7; + int ain6; + int ain5; + int ain4; + int ain3; + int ain2; + int ain1; + int ain0; + int vrefp; + int vrefn; +}; + +#endif /* endif _MUX_AM33XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti814x.h b/arch/arm/include/asm/arch-am33xx/mux_ti814x.h new file mode 100644 index 0000000..a26e503 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/mux_ti814x.h @@ -0,0 +1,311 @@ +/* + * mux_ti814x.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MUX_TI814X_H_ +#define _MUX_TI814X_H_ + +/* PAD Control Fields */ +#define PINCNTL_RSV_MSK (0x3 << 18) /* Reserved bitmask */ +#define PULLUP_EN (0x1 << 17) /* Pull UP Selection */ +#define PULLUDEN (0x0 << 16) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 16) /* Pull up disabled */ +#define MODE(val) val /* used for Readability */ + +#define MUX_CFG(value, offset) \ +{ \ + int tmp; \ + tmp = __raw_readl(CTRL_BASE + offset); \ + tmp &= PINCNTL_RSV_MSK; \ + __raw_writel(tmp | value, (CTRL_BASE + offset));\ +} + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int pincntl1; + int pincntl2; + int pincntl3; + int pincntl4; + int pincntl5; + int pincntl6; + int pincntl7; + int pincntl8; + int pincntl9; + int pincntl10; + int pincntl11; + int pincntl12; + int pincntl13; + int pincntl14; + int pincntl15; + int pincntl16; + int pincntl17; + int pincntl18; + int pincntl19; + int pincntl20; + int pincntl21; + int pincntl22; + int pincntl23; + int pincntl24; + int pincntl25; + int pincntl26; + int pincntl27; + int pincntl28; + int pincntl29; + int pincntl30; + int pincntl31; + int pincntl32; + int pincntl33; + int pincntl34; + int pincntl35; + int pincntl36; + int pincntl37; + int pincntl38; + int pincntl39; + int pincntl40; + int pincntl41; + int pincntl42; + int pincntl43; + int pincntl44; + int pincntl45; + int pincntl46; + int pincntl47; + int pincntl48; + int pincntl49; + int pincntl50; + int pincntl51; + int pincntl52; + int pincntl53; + int pincntl54; + int pincntl55; + int pincntl56; + int pincntl57; + int pincntl58; + int pincntl59; + int pincntl60; + int pincntl61; + int pincntl62; + int pincntl63; + int pincntl64; + int pincntl65; + int pincntl66; + int pincntl67; + int pincntl68; + int pincntl69; + int pincntl70; + int pincntl71; + int pincntl72; + int pincntl73; + int pincntl74; + int pincntl75; + int pincntl76; + int pincntl77; + int pincntl78; + int pincntl79; + int pincntl80; + int pincntl81; + int pincntl82; + int pincntl83; + int pincntl84; + int pincntl85; + int pincntl86; + int pincntl87; + int pincntl88; + int pincntl89; + int pincntl90; + int pincntl91; + int pincntl92; + int pincntl93; + int pincntl94; + int pincntl95; + int pincntl96; + int pincntl97; + int pincntl98; + int pincntl99; + int pincntl100; + int pincntl101; + int pincntl102; + int pincntl103; + int pincntl104; + int pincntl105; + int pincntl106; + int pincntl107; + int pincntl108; + int pincntl109; + int pincntl110; + int pincntl111; + int pincntl112; + int pincntl113; + int pincntl114; + int pincntl115; + int pincntl116; + int pincntl117; + int pincntl118; + int pincntl119; + int pincntl120; + int pincntl121; + int pincntl122; + int pincntl123; + int pincntl124; + int pincntl125; + int pincntl126; + int pincntl127; + int pincntl128; + int pincntl129; + int pincntl130; + int pincntl131; + int pincntl132; + int pincntl133; + int pincntl134; + int pincntl135; + int pincntl136; + int pincntl137; + int pincntl138; + int pincntl139; + int pincntl140; + int pincntl141; + int pincntl142; + int pincntl143; + int pincntl144; + int pincntl145; + int pincntl146; + int pincntl147; + int pincntl148; + int pincntl149; + int pincntl150; + int pincntl151; + int pincntl152; + int pincntl153; + int pincntl154; + int pincntl155; + int pincntl156; + int pincntl157; + int pincntl158; + int pincntl159; + int pincntl160; + int pincntl161; + int pincntl162; + int pincntl163; + int pincntl164; + int pincntl165; + int pincntl166; + int pincntl167; + int pincntl168; + int pincntl169; + int pincntl170; + int pincntl171; + int pincntl172; + int pincntl173; + int pincntl174; + int pincntl175; + int pincntl176; + int pincntl177; + int pincntl178; + int pincntl179; + int pincntl180; + int pincntl181; + int pincntl182; + int pincntl183; + int pincntl184; + int pincntl185; + int pincntl186; + int pincntl187; + int pincntl188; + int pincntl189; + int pincntl190; + int pincntl191; + int pincntl192; + int pincntl193; + int pincntl194; + int pincntl195; + int pincntl196; + int pincntl197; + int pincntl198; + int pincntl199; + int pincntl200; + int pincntl201; + int pincntl202; + int pincntl203; + int pincntl204; + int pincntl205; + int pincntl206; + int pincntl207; + int pincntl208; + int pincntl209; + int pincntl210; + int pincntl211; + int pincntl212; + int pincntl213; + int pincntl214; + int pincntl215; + int pincntl216; + int pincntl217; + int pincntl218; + int pincntl219; + int pincntl220; + int pincntl221; + int pincntl222; + int pincntl223; + int pincntl224; + int pincntl225; + int pincntl226; + int pincntl227; + int pincntl228; + int pincntl229; + int pincntl230; + int pincntl231; + int pincntl232; + int pincntl233; + int pincntl234; + int pincntl235; + int pincntl236; + int pincntl237; + int pincntl238; + int pincntl239; + int pincntl240; + int pincntl241; + int pincntl242; + int pincntl243; + int pincntl244; + int pincntl245; + int pincntl246; + int pincntl247; + int pincntl248; + int pincntl249; + int pincntl250; + int pincntl251; + int pincntl252; + int pincntl253; + int pincntl254; + int pincntl255; + int pincntl256; + int pincntl257; + int pincntl258; + int pincntl259; + int pincntl260; + int pincntl261; + int pincntl262; + int pincntl263; + int pincntl264; + int pincntl265; + int pincntl266; + int pincntl267; + int pincntl268; + int pincntl269; + int pincntl270; +}; + +#endif /* endif _MUX_TI814X_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 850f8a5..d28f9a8 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -28,8 +28,13 @@ * Non-secure RAM starts at 0x40300000 for GP devices. But we keep SRAM_BASE * at 0x40304000(EMU base) so that our code works for both EMU and GP */ +#ifdef CONFIG_AM33XX #define NON_SECURE_SRAM_START 0x40304000 #define NON_SECURE_SRAM_END 0x4030E000 +#elif defined(CONFIG_TI814X) +#define NON_SECURE_SRAM_START 0x40300000 +#define NON_SECURE_SRAM_END 0x40320000 +#endif /* ROM code defines */ /* Boot device */ diff --git a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h b/arch/arm/include/asm/arch-am33xx/omap_gpmc.h index 572f9d0..d03f1db 100644 --- a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h +++ b/arch/arm/include/asm/arch-am33xx/omap_gpmc.h @@ -23,63 +23,7 @@ #ifndef __ASM_ARCH_OMAP_GPMC_H #define __ASM_ARCH_OMAP_GPMC_H -#define GPMC_BUF_EMPTY 0 -#define GPMC_BUF_FULL 1 - -#define ECCCLEAR (0x1 << 8) -#define ECCRESULTREG1 (0x1 << 0) -#define ECCSIZE512BYTE 0xFF -#define ECCSIZE1 (ECCSIZE512BYTE << 22) -#define ECCSIZE0 (ECCSIZE512BYTE << 12) -#define ECCSIZE0SEL (0x000 << 0) - -/* Generic ECC Layouts */ -/* Large Page x8 NAND device Layout */ -#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 12,\ - .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\ - 9, 10, 11, 12},\ - .oobfree = {\ - {.offset = 13,\ - .length = 51 } } \ -} -#endif - -/* Large Page x16 NAND device Layout */ -#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 12,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13},\ - .oobfree = {\ - {.offset = 14,\ - .length = 50 } } \ -} -#endif - -/* Small Page x8 NAND device Layout */ -#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 3,\ - .eccpos = {1, 2, 3},\ - .oobfree = {\ - {.offset = 4,\ - .length = 12 } } \ -} -#endif - -/* Small Page x16 NAND device Layout */ -#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 3,\ - .eccpos = {2, 3, 4},\ - .oobfree = {\ - {.offset = 5,\ - .length = 11 } } \ -} -#endif - +/* These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines are based on AM33xx ELM */ #define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\ .eccbytes = 32,\ .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\ diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index e961ce0..4c23b27 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -25,11 +25,24 @@ #define BOOT_DEVICE_XIP 2 #define BOOT_DEVICE_NAND 5 +#ifdef CONFIG_AM33XX #define BOOT_DEVICE_MMC1 8 #define BOOT_DEVICE_MMC2 9 /* eMMC or daughter card */ +#elif defined(CONFIG_TI814X) +#define BOOT_DEVICE_MMC1 9 +#define BOOT_DEVICE_MMC2 8 /* ROM only supports 2nd instance */ +#endif #define BOOT_DEVICE_SPI 11 #define BOOT_DEVICE_UART 65 #define BOOT_DEVICE_USBETH 68 #define BOOT_DEVICE_CPGMAC 70 #define BOOT_DEVICE_MMC2_2 0xFF + +#ifdef CONFIG_AM33XX +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 +#elif defined(CONFIG_TI814X) +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 +#endif #endif diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 97ab60d..c913b5f 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -34,8 +34,10 @@ void setup_clocks_for_console(void); void ddr_pll_config(unsigned int ddrpll_M); void sdelay(unsigned long); + +struct gpmc_cs; void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size); -void omap_nand_switch_ecc(int); +void omap_nand_switch_ecc(uint32_t, uint32_t); #endif diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h new file mode 100644 index 0000000..b07c4a0 --- /dev/null +++ b/arch/arm/include/asm/arch-bcm2835/mbox.h @@ -0,0 +1,433 @@ +/* + * (C) Copyright 2012 Stephen Warren + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _BCM2835_MBOX_H +#define _BCM2835_MBOX_H + +#include <linux/compiler.h> + +/* + * The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU") + * and the ARM CPU. The ARM CPU is often thought of as the main CPU. + * However, the VideoCore actually controls the initial SoC boot, and hides + * much of the hardware behind a protocol. This protocol is transported + * using the SoC's mailbox hardware module. + * + * The mailbox hardware supports passing 32-bit values back and forth. + * Presumably by software convention of the firmware, the bottom 4 bits of the + * value are used to indicate a logical channel, and the upper 28 bits are the + * actual payload. Various channels exist using these simple raw messages. See + * https://github.com/raspberrypi/firmware/wiki/Mailboxes for a list. As an + * example, the messages on the power management channel are a bitmask of + * devices whose power should be enabled. + * + * The property mailbox channel passes messages that contain the (16-byte + * aligned) ARM physical address of a memory buffer. This buffer is passed to + * the VC for processing, is modified in-place by the VC, and the address then + * passed back to the ARM CPU as the response mailbox message to indicate + * request completion. The buffers have a generic and extensible format; each + * buffer contains a standard header, a list of "tags", and a terminating zero + * entry. Each tag contains an ID indicating its type, and length fields for + * generic parsing. With some limitations, an arbitrary set of tags may be + * combined together into a single message buffer. This file defines structs + * representing the header and many individual tag layouts and IDs. + */ + +/* Raw mailbox HW */ + +#define BCM2835_MBOX_PHYSADDR 0x2000b880 + +struct bcm2835_mbox_regs { + u32 read; + u32 rsvd0[5]; + u32 status; + u32 config; + u32 write; +}; + +#define BCM2835_MBOX_STATUS_WR_FULL 0x80000000 +#define BCM2835_MBOX_STATUS_RD_EMPTY 0x40000000 + +/* Lower 4-bits are channel ID */ +#define BCM2835_CHAN_MASK 0xf +#define BCM2835_MBOX_PACK(chan, data) (((data) & (~BCM2835_CHAN_MASK)) | \ + (chan & BCM2835_CHAN_MASK)) +#define BCM2835_MBOX_UNPACK_CHAN(val) ((val) & BCM2835_CHAN_MASK) +#define BCM2835_MBOX_UNPACK_DATA(val) ((val) & (~BCM2835_CHAN_MASK)) + +/* Property mailbox buffer structures */ + +#define BCM2835_MBOX_PROP_CHAN 8 + +/* All message buffers must start with this header */ +struct bcm2835_mbox_hdr { + u32 buf_size; + u32 code; +}; + +#define BCM2835_MBOX_REQ_CODE 0 +#define BCM2835_MBOX_RESP_CODE_SUCCESS 0x80000000 + +#define BCM2835_MBOX_INIT_HDR(_m_) { \ + memset((_m_), 0, sizeof(*(_m_))); \ + (_m_)->hdr.buf_size = sizeof(*(_m_)); \ + (_m_)->hdr.code = 0; \ + (_m_)->end_tag = 0; \ + } + +/* + * A message buffer contains a list of tags. Each tag must also start with + * a standardized header. + */ +struct bcm2835_mbox_tag_hdr { + u32 tag; + u32 val_buf_size; + u32 val_len; +}; + +#define BCM2835_MBOX_INIT_TAG(_t_, _id_) { \ + (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \ + (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \ + (_t_)->tag_hdr.val_len = sizeof((_t_)->body.req); \ + } + +#define BCM2835_MBOX_INIT_TAG_NO_REQ(_t_, _id_) { \ + (_t_)->tag_hdr.tag = BCM2835_MBOX_TAG_##_id_; \ + (_t_)->tag_hdr.val_buf_size = sizeof((_t_)->body); \ + (_t_)->tag_hdr.val_len = 0; \ + } + +/* When responding, the VC sets this bit in val_len to indicate a response */ +#define BCM2835_MBOX_TAG_VAL_LEN_RESPONSE 0x80000000 + +/* + * Below we define the ID and struct for many possible tags. This header only + * defines individual tag structs, not entire message structs, since in + * general an arbitrary set of tags may be combined into a single message. + * Clients of the mbox API are expected to define their own overall message + * structures by combining the header, a set of tags, and a terminating + * entry. For example, + * + * struct msg { + * struct bcm2835_mbox_hdr hdr; + * struct bcm2835_mbox_tag_get_arm_mem get_arm_mem; + * ... perhaps other tags here ... + * u32 end_tag; + * }; + */ + +#define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005 + +struct bcm2835_mbox_tag_get_arm_mem { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + } req; + struct { + u32 mem_base; + u32 mem_size; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_GET_CLOCK_RATE 0x00030002 + +#define BCM2835_MBOX_CLOCK_ID_EMMC 1 +#define BCM2835_MBOX_CLOCK_ID_UART 2 +#define BCM2835_MBOX_CLOCK_ID_ARM 3 +#define BCM2835_MBOX_CLOCK_ID_CORE 4 +#define BCM2835_MBOX_CLOCK_ID_V3D 5 +#define BCM2835_MBOX_CLOCK_ID_H264 6 +#define BCM2835_MBOX_CLOCK_ID_ISP 7 +#define BCM2835_MBOX_CLOCK_ID_SDRAM 8 +#define BCM2835_MBOX_CLOCK_ID_PIXEL 9 +#define BCM2835_MBOX_CLOCK_ID_PWM 10 + +struct bcm2835_mbox_tag_get_clock_rate { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + u32 clock_id; + } req; + struct { + u32 clock_id; + u32 rate_hz; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_ALLOCATE_BUFFER 0x00040001 + +struct bcm2835_mbox_tag_allocate_buffer { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + u32 alignment; + } req; + struct { + u32 fb_address; + u32 fb_size; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_RELEASE_BUFFER 0x00048001 + +struct bcm2835_mbox_tag_release_buffer { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + } req; + struct { + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_BLANK_SCREEN 0x00040002 + +struct bcm2835_mbox_tag_blank_screen { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + /* bit 0 means on, other bots reserved */ + u32 state; + } req; + struct { + u32 state; + } resp; + } body; +}; + +/* Physical means output signal */ +#define BCM2835_MBOX_TAG_GET_PHYSICAL_W_H 0x00040003 +#define BCM2835_MBOX_TAG_TEST_PHYSICAL_W_H 0x00044003 +#define BCM2835_MBOX_TAG_SET_PHYSICAL_W_H 0x00048003 + +struct bcm2835_mbox_tag_physical_w_h { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + /* req not used for get */ + struct { + u32 width; + u32 height; + } req; + struct { + u32 width; + u32 height; + } resp; + } body; +}; + +/* Virtual means display buffer */ +#define BCM2835_MBOX_TAG_GET_VIRTUAL_W_H 0x00040004 +#define BCM2835_MBOX_TAG_TEST_VIRTUAL_W_H 0x00044004 +#define BCM2835_MBOX_TAG_SET_VIRTUAL_W_H 0x00048004 + +struct bcm2835_mbox_tag_virtual_w_h { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + /* req not used for get */ + struct { + u32 width; + u32 height; + } req; + struct { + u32 width; + u32 height; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_GET_DEPTH 0x00040005 +#define BCM2835_MBOX_TAG_TEST_DEPTH 0x00044005 +#define BCM2835_MBOX_TAG_SET_DEPTH 0x00048005 + +struct bcm2835_mbox_tag_depth { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + /* req not used for get */ + struct { + u32 bpp; + } req; + struct { + u32 bpp; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_GET_PIXEL_ORDER 0x00040006 +#define BCM2835_MBOX_TAG_TEST_PIXEL_ORDER 0x00044005 +#define BCM2835_MBOX_TAG_SET_PIXEL_ORDER 0x00048006 + +#define BCM2835_MBOX_PIXEL_ORDER_BGR 0 +#define BCM2835_MBOX_PIXEL_ORDER_RGB 1 + +struct bcm2835_mbox_tag_pixel_order { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + /* req not used for get */ + struct { + u32 order; + } req; + struct { + u32 order; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_GET_ALPHA_MODE 0x00040007 +#define BCM2835_MBOX_TAG_TEST_ALPHA_MODE 0x00044007 +#define BCM2835_MBOX_TAG_SET_ALPHA_MODE 0x00048007 + +#define BCM2835_MBOX_ALPHA_MODE_0_OPAQUE 0 +#define BCM2835_MBOX_ALPHA_MODE_0_TRANSPARENT 1 +#define BCM2835_MBOX_ALPHA_MODE_IGNORED 2 + +struct bcm2835_mbox_tag_alpha_mode { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + /* req not used for get */ + struct { + u32 alpha; + } req; + struct { + u32 alpha; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_GET_PITCH 0x00040008 + +struct bcm2835_mbox_tag_pitch { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + } req; + struct { + u32 pitch; + } resp; + } body; +}; + +/* Offset of display window within buffer */ +#define BCM2835_MBOX_TAG_GET_VIRTUAL_OFFSET 0x00040009 +#define BCM2835_MBOX_TAG_TEST_VIRTUAL_OFFSET 0x00044009 +#define BCM2835_MBOX_TAG_SET_VIRTUAL_OFFSET 0x00048009 + +struct bcm2835_mbox_tag_virtual_offset { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + /* req not used for get */ + struct { + u32 x; + u32 y; + } req; + struct { + u32 x; + u32 y; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_GET_OVERSCAN 0x0004000a +#define BCM2835_MBOX_TAG_TEST_OVERSCAN 0x0004400a +#define BCM2835_MBOX_TAG_SET_OVERSCAN 0x0004800a + +struct bcm2835_mbox_tag_overscan { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + /* req not used for get */ + struct { + u32 top; + u32 bottom; + u32 left; + u32 right; + } req; + struct { + u32 top; + u32 bottom; + u32 left; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_GET_PALETTE 0x0004000b + +struct bcm2835_mbox_tag_get_palette { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + } req; + struct { + u32 data[1024]; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_TEST_PALETTE 0x0004400b + +struct bcm2835_mbox_tag_test_palette { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + u32 offset; + u32 num_entries; + u32 data[256]; + } req; + struct { + u32 is_invalid; + } resp; + } body; +}; + +#define BCM2835_MBOX_TAG_SET_PALETTE 0x0004800b + +struct bcm2835_mbox_tag_set_palette { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + u32 offset; + u32 num_entries; + u32 data[256]; + } req; + struct { + u32 is_invalid; + } resp; + } body; +}; + +/* + * Pass a raw u32 message to the VC, and receive a raw u32 back. + * + * Returns 0 for success, any other value for error. + */ +int bcm2835_mbox_call_raw(u32 chan, u32 send, u32 *recv); + +/* + * Pass a complete property-style buffer to the VC, and wait until it has + * been processed. + * + * This function expects a pointer to the mbox_hdr structure in an attempt + * to ensure some degree of type safety. However, some number of tags and + * a termination value are expected to immediately follow the header in + * memory, as required by the property protocol. + * + * Returns 0 for success, any other value for error. + */ +int bcm2835_mbox_call_prop(u32 chan, struct bcm2835_mbox_hdr *buffer); + +#endif diff --git a/arch/arm/include/asm/arch-bcm2835/sdhci.h b/arch/arm/include/asm/arch-bcm2835/sdhci.h new file mode 100644 index 0000000..a4f867b --- /dev/null +++ b/arch/arm/include/asm/arch-bcm2835/sdhci.h @@ -0,0 +1,24 @@ +/* + * (C) Copyright 2012 Stephen Warren + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _BCM2835_SDHCI_H_ +#define _BCM2835_SDHCI_H_ + +#define BCM2835_SDHCI_BASE 0x20300000 + +int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq); + +#endif diff --git a/arch/arm/include/asm/arch-bcm2835/timer.h b/arch/arm/include/asm/arch-bcm2835/timer.h index 30c70e0..c2001b6 100644 --- a/arch/arm/include/asm/arch-bcm2835/timer.h +++ b/arch/arm/include/asm/arch-bcm2835/timer.h @@ -34,4 +34,6 @@ struct bcm2835_timer_regs { #define BCM2835_TIMER_CS_M1 (1 << 1) #define BCM2835_TIMER_CS_M0 (1 << 0) +extern ulong get_timer_us(ulong base); + #endif diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 1935b0b..73f8063 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -29,6 +29,12 @@ #define VPLL 4 #define BPLL 5 +enum pll_src_bit { + EXYNOS_SRC_MPLL = 6, + EXYNOS_SRC_EPLL, + EXYNOS_SRC_VPLL, +}; + unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_i2c_clk(void); @@ -44,4 +50,13 @@ int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq); int set_epll_clk(unsigned long rate); int set_spi_clk(int periph_id, unsigned int rate); +/** + * get the clk frequency of the required peripheral + * + * @param peripheral Peripheral id + * + * @return frequency of the peripheral clk + */ +unsigned long clock_get_periph_rate(int peripheral); + #endif diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index eb34422..f76e489 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -62,6 +62,7 @@ #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE /* EXYNOS4X12 */ #define EXYNOS4X12_GPIO_PART3_BASE 0x03860000 @@ -92,9 +93,10 @@ #define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE #define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE -#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE /* EXYNOS5 Common*/ #define EXYNOS5_I2C_SPACING 0x10000 @@ -106,6 +108,7 @@ #define EXYNOS5_SWRESET 0x10040400 #define EXYNOS5_SYSREG_BASE 0x10050000 #define EXYNOS5_WATCHDOG_BASE 0x101D0000 +#define EXYNOS5_ACE_SFR_BASE 0x10830000 #define EXYNOS5_DMC_PHY0_BASE 0x10C00000 #define EXYNOS5_DMC_PHY1_BASE 0x10C10000 #define EXYNOS5_GPIO_PART3_BASE 0x10D10000 @@ -205,6 +208,7 @@ static inline unsigned int samsung_get_base_##device(void) \ SAMSUNG_BASE(adc, ADC_BASE) SAMSUNG_BASE(clock, CLOCK_BASE) +SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE) SAMSUNG_BASE(dp, DP_BASE) SAMSUNG_BASE(sysreg, SYSREG_BASE) SAMSUNG_BASE(fimd, FIMD_BASE) diff --git a/arch/arm/include/asm/arch-exynos/dp_info.h b/arch/arm/include/asm/arch-exynos/dp_info.h index 102b709..ff16361 100644 --- a/arch/arm/include/asm/arch-exynos/dp_info.h +++ b/arch/arm/include/asm/arch-exynos/dp_info.h @@ -199,7 +199,6 @@ enum { struct exynos_dp_platform_data { struct edp_device_info *edp_dev_info; - void (*phy_enable)(unsigned int); }; #ifdef CONFIG_EXYNOS_DP diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 89bcdfc..e5aed4b 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -61,6 +61,11 @@ enum periph_id { PERIPH_ID_SPI3, PERIPH_ID_SPI4, PERIPH_ID_SDMMC4, + PERIPH_ID_PWM0, + PERIPH_ID_PWM1, + PERIPH_ID_PWM2, + PERIPH_ID_PWM3, + PERIPH_ID_PWM4, PERIPH_ID_COUNT, PERIPH_ID_NONE = -1, diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h index d2fdb59..3549667 100644 --- a/arch/arm/include/asm/arch-exynos/power.h +++ b/arch/arm/include/asm/arch-exynos/power.h @@ -857,6 +857,9 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable); void set_usbhost_phy_ctrl(unsigned int enable); +/* Enables hardware tripping to power off the system when TMU fails */ +void set_hw_thermal_trip(void); + #define POWER_USB_HOST_PHY_CTRL_EN (1 << 0) #define POWER_USB_HOST_PHY_CTRL_DISABLE (0 << 0) @@ -864,4 +867,25 @@ void set_dp_phy_ctrl(unsigned int enable); #define EXYNOS_DP_PHY_ENABLE (1 << 0) +#define EXYNOS_PS_HOLD_CONTROL_DATA_HIGH (1 << 8) +#define POWER_ENABLE_HW_TRIP (1UL << 31) + +/* + * Set ps_hold data driving value high + * This enables the machine to stay powered on + * after the initial power-on condition goes away + * (e.g. power button). + */ +void set_ps_hold_ctrl(void); + +/* PMU_DEBUG bits [12:8] = 0x1000 selects XXTI clock source */ +#define PMU_DEBUG_XXTI 0x1000 +/* Mask bit[12:8] for xxti clock selection */ +#define PMU_DEBUG_CLKOUT_SEL_MASK 0x1f00 + +/* + * Pmu debug is used for xclkout, enable xclkout with + * source as XXTI + */ +void set_xclkout(void); #endif diff --git a/arch/arm/include/asm/arch-exynos/spl.h b/arch/arm/include/asm/arch-exynos/spl.h index 306b41d..46b25a6 100644 --- a/arch/arm/include/asm/arch-exynos/spl.h +++ b/arch/arm/include/asm/arch-exynos/spl.h @@ -78,11 +78,12 @@ struct spl_machine_param { */ u32 uboot_size; enum boot_mode boot_source; /* Boot device */ - enum mem_manuf mem_manuf; /* Memory Manufacturer */ unsigned frequency_mhz; /* Frequency of memory in MHz */ unsigned arm_freq_mhz; /* ARM Frequency in MHz */ u32 serial_base; /* Serial base address */ u32 i2c_base; /* i2c base address */ + u32 board_rev_gpios; /* Board revision GPIOs */ + enum mem_manuf mem_manuf; /* Memory Manufacturer */ } __attribute__((__packed__)); #endif diff --git a/arch/arm/include/asm/arch-exynos/tmu.h b/arch/arm/include/asm/arch-exynos/tmu.h new file mode 100644 index 0000000..7e0158e --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/tmu.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Akshay Saraswat <akshay.s@samsung.com> + * + * EXYNOS - Thermal Management Unit + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_TMU_H +#define __ASM_ARCH_TMU_H + +struct exynos5_tmu_reg { + unsigned triminfo; + unsigned rsvd1; + unsigned rsvd2; + unsigned rsvd3; + unsigned rsvd4; + unsigned triminfo_control; + unsigned rsvd5; + unsigned rsvd6; + unsigned tmu_control; + unsigned rsvd7; + unsigned tmu_status; + unsigned sampling_internal; + unsigned counter_value0; + unsigned counter_value1; + unsigned rsvd8; + unsigned rsvd9; + unsigned current_temp; + unsigned rsvd10; + unsigned rsvd11; + unsigned rsvd12; + unsigned threshold_temp_rise; + unsigned threshold_temp_fall; + unsigned rsvd13; + unsigned rsvd14; + unsigned past_temp3_0; + unsigned past_temp7_4; + unsigned past_temp11_8; + unsigned past_temp15_12; + unsigned inten; + unsigned intstat; + unsigned intclear; + unsigned rsvd15; + unsigned emul_con; +}; +#endif /* __ASM_ARCH_TMU_H */ diff --git a/arch/arm/include/asm/arch-omap24xx/omap2420.h b/arch/arm/include/asm/arch-omap24xx/omap2420.h index d8d5647..5724f5d 100644 --- a/arch/arm/include/asm/arch-omap24xx/omap2420.h +++ b/arch/arm/include/asm/arch-omap24xx/omap2420.h @@ -212,9 +212,9 @@ # define H4_CS1_BASE 0x04000000 /* debug board */ # define H4_CS2_BASE 0x0A000000 /* wifi board */ #else -# define H4_CS0_BASE 0x04000000 /* flash (64 Meg aligned) */ -# define H4_CS1_BASE 0x08000000 /* debug board */ -# define H4_CS2_BASE 0x0A000000 /* wifi board */ +# define H4_CS0_BASE 0x08000000 /* flash (64 Meg aligned) */ +# define H4_CS1_BASE 0x04000000 /* debug board */ +# define H4_CS2_BASE 0x0C000000 /* wifi board */ #endif /* base address for indirect vectors (internal boot mode) */ diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 5683e16..c601873 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -109,6 +109,10 @@ struct gpmc_cs { u8 res[8]; /* blow up to 0x30 byte */ }; +struct bch_res_0_3 { + u32 bch_result_x[4]; +}; + struct gpmc { u8 res1[0x10]; u32 sysconfig; /* 0x10 */ @@ -135,6 +139,8 @@ struct gpmc { u32 ecc7_result; /* 0x218 */ u32 ecc8_result; /* 0x21C */ u32 ecc9_result; /* 0x220 */ + u8 res7[0x1C]; /* fill up to 0x240 */ + struct bch_res_0_3 bch_result_0_3[7]; /* 0x240 */ }; /* Used for board specific gpmc initialization */ diff --git a/arch/arm/include/asm/arch-omap3/omap_gpmc.h b/arch/arm/include/asm/arch-omap3/omap_gpmc.h index 800e4ee..6441281 100644 --- a/arch/arm/include/asm/arch-omap3/omap_gpmc.h +++ b/arch/arm/include/asm/arch-omap3/omap_gpmc.h @@ -23,62 +23,22 @@ #ifndef __ASM_ARCH_OMAP_GPMC_H #define __ASM_ARCH_OMAP_GPMC_H -#define GPMC_BUF_EMPTY 0 -#define GPMC_BUF_FULL 1 - -#define ECCCLEAR (0x1 << 8) -#define ECCRESULTREG1 (0x1 << 0) -#define ECCSIZE512BYTE 0xFF -#define ECCSIZE1 (ECCSIZE512BYTE << 22) -#define ECCSIZE0 (ECCSIZE512BYTE << 12) -#define ECCSIZE0SEL (0x000 << 0) - -/* Generic ECC Layouts */ -/* Large Page x8 NAND device Layout */ -#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 12,\ - .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\ - 9, 10, 11, 12},\ - .oobfree = {\ - {.offset = 13,\ - .length = 51 } } \ -} -#endif - -/* Large Page x16 NAND device Layout */ -#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 12,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13},\ - .oobfree = {\ - {.offset = 14,\ - .length = 50 } } \ -} -#endif - -/* Small Page x8 NAND device Layout */ -#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 3,\ - .eccpos = {1, 2, 3},\ - .oobfree = {\ - {.offset = 4,\ - .length = 12 } } \ -} -#endif - -/* Small Page x16 NAND device Layout */ -#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 3,\ - .eccpos = {2, 3, 4},\ +/* + * These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines using the BCH library. + * The OOB layout was first defined by linx kernel in commit + * 0e618ef0a6a33cf7ef96c2c824402088dd8ef48c, we have to reuse it here cause + * we want to be compatible. + */ +#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\ + .eccbytes = 56,\ + .eccpos = {12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\ + 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\ + 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,\ + 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63},\ .oobfree = {\ - {.offset = 5,\ - .length = 11 } } \ + {.offset = 2,\ + .length = 10 } } \ } -#endif /* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ #define NET_LAN9221_GPMC_CONFIG1 0x00001000 diff --git a/arch/arm/include/asm/arch-omap3/spl.h b/arch/arm/include/asm/arch-omap3/spl.h index dec4dac..84e6d7b 100644 --- a/arch/arm/include/asm/arch-omap3/spl.h +++ b/arch/arm/include/asm/arch-omap3/spl.h @@ -31,4 +31,7 @@ #define BOOT_DEVICE_MMC1 6 #define BOOT_DEVICE_XIPWAIT 7 #define BOOT_DEVICE_MMC2_2 0xFF + +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 #endif diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index d60f2ad..dae1312 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -78,7 +78,7 @@ void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long); void make_cs1_contiguous(void); -void omap_nand_switch_ecc(int); +void omap_nand_switch_ecc(uint32_t, uint32_t); void power_init_r(void); void dieid_num_r(void); void do_omap3_emu_romcode_call(u32 service_id, u32 parameters); diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index 5f321fe..ad984da 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -147,7 +147,6 @@ struct s32ktimer { #define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START /* SRAM scratch space entries */ #define OMAP4_SRAM_SCRATCH_OMAP4_REV SRAM_SCRATCH_SPACE_ADDR -#define OMAP4_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) #define OMAP4_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) diff --git a/arch/arm/include/asm/arch-omap4/spl.h b/arch/arm/include/asm/arch-omap4/spl.h index 4e094f9..f61627f 100644 --- a/arch/arm/include/asm/arch-omap4/spl.h +++ b/arch/arm/include/asm/arch-omap4/spl.h @@ -32,4 +32,6 @@ #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 0xFF +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2 #endif diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index b632635..887fcaa 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -196,7 +196,6 @@ struct s32ktimer { * SRAM scratch space entries */ #define OMAP5_SRAM_SCRATCH_OMAP5_REV SRAM_SCRATCH_SPACE_ADDR -#define OMAP5_SRAM_SCRATCH_EMIF_SIZE (SRAM_SCRATCH_SPACE_ADDR + 0x4) #define OMAP5_SRAM_SCRATCH_EMIF_T_NUM (SRAM_SCRATCH_SPACE_ADDR + 0xC) #define OMAP5_SRAM_SCRATCH_EMIF_T_DEN (SRAM_SCRATCH_SPACE_ADDR + 0x10) #define OMAP_SRAM_SCRATCH_PRCM_PTR (SRAM_SCRATCH_SPACE_ADDR + 0x14) diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h index 323cd63..d4d353c 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ b/arch/arm/include/asm/arch-omap5/spl.h @@ -32,4 +32,6 @@ #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 7 +#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 +#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 #endif diff --git a/arch/arm/include/asm/arch-s3c64xx/hardware.h b/arch/arm/include/asm/arch-s3c64xx/hardware.h deleted file mode 100644 index 84d24c9..0000000 --- a/arch/arm/include/asm/arch-s3c64xx/hardware.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400 - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ARCH_HARDWARE_H_ -#define _ARCH_HARDWARE_H_ - -#include <asm/sizes.h> - -#ifndef __ASSEMBLY__ -#define UData(Data) ((unsigned long) (Data)) - -#define __REG(x) (*(vu_long *)(x)) -#define __REGl(x) (*(vu_long *)(x)) -#define __REGw(x) (*(vu_short *)(x)) -#define __REGb(x) (*(vu_char *)(x)) -#define __REG2(x, y) (*(vu_long *)((x) + (y))) -#else -#define UData(Data) (Data) - -#define __REG(x) (x) -#define __REGl(x) (x) -#define __REGw(x) (x) -#define __REGb(x) (x) -#define __REG2(x, y) ((x) + (y)) -#endif - -#define Fld(Size, Shft) (((Size) << 16) + (Shft)) - -#define FSize(Field) ((Field) >> 16) -#define FShft(Field) ((Field) & 0x0000FFFF) -#define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field)) -#define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1) -#define F1stBit(Field) (UData (1) << FShft (Field)) - -#define FClrBit(Data, Bit) (Data = (Data & ~(Bit))) -#define FClrFld(Data, Field) (Data = (Data & ~FMsk(Field))) - -#define FInsrt(Value, Field) \ - (UData (Value) << FShft (Field)) - -#define FExtr(Data, Field) \ - ((UData (Data) >> FShft (Field)) & FAlnMsk (Field)) - -#endif /* _ARCH_HARDWARE_H_ */ diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h b/arch/arm/include/asm/arch-s3c64xx/s3c6400.h deleted file mode 100644 index 10b3324..0000000 --- a/arch/arm/include/asm/arch-s3c64xx/s3c6400.h +++ /dev/null @@ -1,895 +0,0 @@ -/* - * (C) Copyright 2007 - * Byungjae Lee, Samsung Erectronics, bjlee@samsung.com. - * - only support for S3C6400 - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : s3c6400.h - * - * Based on S3C6400 User's manual Rev 0.0 - ************************************************/ - -#ifndef __S3C6400_H__ -#define __S3C6400_H__ - -#define S3C64XX_UART_CHANNELS 3 -#define S3C64XX_SPI_CHANNELS 2 - -#include <asm/hardware.h> - -#define ELFIN_CLOCK_POWER_BASE 0x7e00f000 - -/* Clock & Power Controller for mDirac3*/ -#define APLL_LOCK_OFFSET 0x00 -#define MPLL_LOCK_OFFSET 0x04 -#define EPLL_LOCK_OFFSET 0x08 -#define APLL_CON_OFFSET 0x0C -#define MPLL_CON_OFFSET 0x10 -#define EPLL_CON0_OFFSET 0x14 -#define EPLL_CON1_OFFSET 0x18 -#define CLK_SRC_OFFSET 0x1C -#define CLK_DIV0_OFFSET 0x20 -#define CLK_DIV1_OFFSET 0x24 -#define CLK_DIV2_OFFSET 0x28 -#define CLK_OUT_OFFSET 0x2C -#define HCLK_GATE_OFFSET 0x30 -#define PCLK_GATE_OFFSET 0x34 -#define SCLK_GATE_OFFSET 0x38 -#define AHB_CON0_OFFSET 0x100 -#define AHB_CON1_OFFSET 0x104 -#define AHB_CON2_OFFSET 0x108 -#define SELECT_DMA_OFFSET 0x110 -#define SW_RST_OFFSET 0x114 -#define SYS_ID_OFFSET 0x118 -#define MEM_SYS_CFG_OFFSET 0x120 -#define QOS_OVERRIDE0_OFFSET 0x124 -#define QOS_OVERRIDE1_OFFSET 0x128 -#define MEM_CFG_STAT_OFFSET 0x12C -#define PWR_CFG_OFFSET 0x804 -#define EINT_MASK_OFFSET 0x808 -#define NOR_CFG_OFFSET 0x810 -#define STOP_CFG_OFFSET 0x814 -#define SLEEP_CFG_OFFSET 0x818 -#define OSC_FREQ_OFFSET 0x820 -#define OSC_STABLE_OFFSET 0x824 -#define PWR_STABLE_OFFSET 0x828 -#define FPC_STABLE_OFFSET 0x82C -#define MTC_STABLE_OFFSET 0x830 -#define OTHERS_OFFSET 0x900 -#define RST_STAT_OFFSET 0x904 -#define WAKEUP_STAT_OFFSET 0x908 -#define BLK_PWR_STAT_OFFSET 0x90C -#define INF_REG0_OFFSET 0xA00 -#define INF_REG1_OFFSET 0xA04 -#define INF_REG2_OFFSET 0xA08 -#define INF_REG3_OFFSET 0xA0C -#define INF_REG4_OFFSET 0xA10 -#define INF_REG5_OFFSET 0xA14 -#define INF_REG6_OFFSET 0xA18 -#define INF_REG7_OFFSET 0xA1C - -#define OSC_CNT_VAL_OFFSET 0x824 -#define PWR_CNT_VAL_OFFSET 0x828 -#define FPC_CNT_VAL_OFFSET 0x82C -#define MTC_CNT_VAL_OFFSET 0x830 - -#define APLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) -#define MPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) -#define EPLL_LOCK_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) -#define APLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) -#define MPLL_CON_REG __REG(ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) -#define EPLL_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) -#define EPLL_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) -#define CLK_SRC_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) -#define CLK_DIV0_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) -#define CLK_DIV1_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) -#define CLK_DIV2_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) -#define CLK_OUT_REG __REG(ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) -#define HCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) -#define PCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) -#define SCLK_GATE_REG __REG(ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) -#define AHB_CON0_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) -#define AHB_CON1_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) -#define AHB_CON2_REG __REG(ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) -#define SELECT_DMA_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - SELECT_DMA_OFFSET) -#define SW_RST_REG __REG(ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) -#define SYS_ID_REG __REG(ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) -#define MEM_SYS_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MEM_SYS_CFG_OFFSET) -#define QOS_OVERRIDE0_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - QOS_OVERRIDE0_OFFSET) -#define QOS_OVERRIDE1_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - QOS_OVERRIDE1_OFFSET) -#define MEM_CFG_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MEM_CFG_STAT_OFFSET) -#define PWR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) -#define EINT_MASK_REG __REG(ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) -#define NOR_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) -#define STOP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) -#define SLEEP_CFG_REG __REG(ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) -#define OSC_FREQ_REG __REG(ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) -#define OSC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - OSC_CNT_VAL_OFFSET) -#define PWR_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - PWR_CNT_VAL_OFFSET) -#define FPC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - FPC_CNT_VAL_OFFSET) -#define MTC_CNT_VAL_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - MTC_CNT_VAL_OFFSET) -#define OTHERS_REG __REG(ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) -#define RST_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) -#define WAKEUP_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - WAKEUP_STAT_OFFSET) -#define BLK_PWR_STAT_REG __REG(ELFIN_CLOCK_POWER_BASE + \ - BLK_PWR_STAT_OFFSET) -#define INF_REG0_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) -#define INF_REG1_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) -#define INF_REG2_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) -#define INF_REG3_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) -#define INF_REG4_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) -#define INF_REG5_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) -#define INF_REG6_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) -#define INF_REG7_REG __REG(ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) - -#define APLL_LOCK (ELFIN_CLOCK_POWER_BASE + APLL_LOCK_OFFSET) -#define MPLL_LOCK (ELFIN_CLOCK_POWER_BASE + MPLL_LOCK_OFFSET) -#define EPLL_LOCK (ELFIN_CLOCK_POWER_BASE + EPLL_LOCK_OFFSET) -#define APLL_CON (ELFIN_CLOCK_POWER_BASE + APLL_CON_OFFSET) -#define MPLL_CON (ELFIN_CLOCK_POWER_BASE + MPLL_CON_OFFSET) -#define EPLL_CON0 (ELFIN_CLOCK_POWER_BASE + EPLL_CON0_OFFSET) -#define EPLL_CON1 (ELFIN_CLOCK_POWER_BASE + EPLL_CON1_OFFSET) -#define CLK_SRC (ELFIN_CLOCK_POWER_BASE + CLK_SRC_OFFSET) -#define CLK_DIV0 (ELFIN_CLOCK_POWER_BASE + CLK_DIV0_OFFSET) -#define CLK_DIV1 (ELFIN_CLOCK_POWER_BASE + CLK_DIV1_OFFSET) -#define CLK_DIV2 (ELFIN_CLOCK_POWER_BASE + CLK_DIV2_OFFSET) -#define CLK_OUT (ELFIN_CLOCK_POWER_BASE + CLK_OUT_OFFSET) -#define HCLK_GATE (ELFIN_CLOCK_POWER_BASE + HCLK_GATE_OFFSET) -#define PCLK_GATE (ELFIN_CLOCK_POWER_BASE + PCLK_GATE_OFFSET) -#define SCLK_GATE (ELFIN_CLOCK_POWER_BASE + SCLK_GATE_OFFSET) -#define AHB_CON0 (ELFIN_CLOCK_POWER_BASE + AHB_CON0_OFFSET) -#define AHB_CON1 (ELFIN_CLOCK_POWER_BASE + AHB_CON1_OFFSET) -#define AHB_CON2 (ELFIN_CLOCK_POWER_BASE + AHB_CON2_OFFSET) -#define SELECT_DMA (ELFIN_CLOCK_POWER_BASE + SELECT_DMA_OFFSET) -#define SW_RST (ELFIN_CLOCK_POWER_BASE + SW_RST_OFFSET) -#define SYS_ID (ELFIN_CLOCK_POWER_BASE + SYS_ID_OFFSET) -#define MEM_SYS_CFG (ELFIN_CLOCK_POWER_BASE + MEM_SYS_CFG_OFFSET) -#define QOS_OVERRIDE0 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE0_OFFSET) -#define QOS_OVERRIDE1 (ELFIN_CLOCK_POWER_BASE + QOS_OVERRIDE1_OFFSET) -#define MEM_CFG_STAT (ELFIN_CLOCK_POWER_BASE + MEM_CFG_STAT_OFFSET) -#define PWR_CFG (ELFIN_CLOCK_POWER_BASE + PWR_CFG_OFFSET) -#define EINT_MASK (ELFIN_CLOCK_POWER_BASE + EINT_MASK_OFFSET) -#define NOR_CFG (ELFIN_CLOCK_POWER_BASE + NOR_CFG_OFFSET) -#define STOP_CFG (ELFIN_CLOCK_POWER_BASE + STOP_CFG_OFFSET) -#define SLEEP_CFG (ELFIN_CLOCK_POWER_BASE + SLEEP_CFG_OFFSET) -#define OSC_FREQ (ELFIN_CLOCK_POWER_BASE + OSC_FREQ_OFFSET) -#define OSC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + OSC_CNT_VAL_OFFSET) -#define PWR_CNT_VAL (ELFIN_CLOCK_POWER_BASE + PWR_CNT_VAL_OFFSET) -#define FPC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + FPC_CNT_VAL_OFFSET) -#define MTC_CNT_VAL (ELFIN_CLOCK_POWER_BASE + MTC_CNT_VAL_OFFSET) -#define OTHERS (ELFIN_CLOCK_POWER_BASE + OTHERS_OFFSET) -#define RST_STAT (ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) -#define WAKEUP_STAT (ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET) -#define BLK_PWR_STAT (ELFIN_CLOCK_POWER_BASE + BLK_PWR_STAT_OFFSET) -#define INF_REG0 (ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) -#define INF_REG1 (ELFIN_CLOCK_POWER_BASE + INF_REG1_OFFSET) -#define INF_REG2 (ELFIN_CLOCK_POWER_BASE + INF_REG2_OFFSET) -#define INF_REG3 (ELFIN_CLOCK_POWER_BASE + INF_REG3_OFFSET) -#define INF_REG4 (ELFIN_CLOCK_POWER_BASE + INF_REG4_OFFSET) -#define INF_REG5 (ELFIN_CLOCK_POWER_BASE + INF_REG5_OFFSET) -#define INF_REG6 (ELFIN_CLOCK_POWER_BASE + INF_REG6_OFFSET) -#define INF_REG7 (ELFIN_CLOCK_POWER_BASE + INF_REG7_OFFSET) - - -/* - * GPIO - */ -#define ELFIN_GPIO_BASE 0x7f008000 - -#define GPACON_OFFSET 0x00 -#define GPADAT_OFFSET 0x04 -#define GPAPUD_OFFSET 0x08 -#define GPACONSLP_OFFSET 0x0C -#define GPAPUDSLP_OFFSET 0x10 -#define GPBCON_OFFSET 0x20 -#define GPBDAT_OFFSET 0x24 -#define GPBPUD_OFFSET 0x28 -#define GPBCONSLP_OFFSET 0x2C -#define GPBPUDSLP_OFFSET 0x30 -#define GPCCON_OFFSET 0x40 -#define GPCDAT_OFFSET 0x44 -#define GPCPUD_OFFSET 0x48 -#define GPCCONSLP_OFFSET 0x4C -#define GPCPUDSLP_OFFSET 0x50 -#define GPDCON_OFFSET 0x60 -#define GPDDAT_OFFSET 0x64 -#define GPDPUD_OFFSET 0x68 -#define GPDCONSLP_OFFSET 0x6C -#define GPDPUDSLP_OFFSET 0x70 -#define GPECON_OFFSET 0x80 -#define GPEDAT_OFFSET 0x84 -#define GPEPUD_OFFSET 0x88 -#define GPECONSLP_OFFSET 0x8C -#define GPEPUDSLP_OFFSET 0x90 -#define GPFCON_OFFSET 0xA0 -#define GPFDAT_OFFSET 0xA4 -#define GPFPUD_OFFSET 0xA8 -#define GPFCONSLP_OFFSET 0xAC -#define GPFPUDSLP_OFFSET 0xB0 -#define GPGCON_OFFSET 0xC0 -#define GPGDAT_OFFSET 0xC4 -#define GPGPUD_OFFSET 0xC8 -#define GPGCONSLP_OFFSET 0xCC -#define GPGPUDSLP_OFFSET 0xD0 -#define GPHCON0_OFFSET 0xE0 -#define GPHCON1_OFFSET 0xE4 -#define GPHDAT_OFFSET 0xE8 -#define GPHPUD_OFFSET 0xEC -#define GPHCONSLP_OFFSET 0xF0 -#define GPHPUDSLP_OFFSET 0xF4 -#define GPICON_OFFSET 0x100 -#define GPIDAT_OFFSET 0x104 -#define GPIPUD_OFFSET 0x108 -#define GPICONSLP_OFFSET 0x10C -#define GPIPUDSLP_OFFSET 0x110 -#define GPJCON_OFFSET 0x120 -#define GPJDAT_OFFSET 0x124 -#define GPJPUD_OFFSET 0x128 -#define GPJCONSLP_OFFSET 0x12C -#define GPJPUDSLP_OFFSET 0x130 -#define MEM0DRVCON_OFFSET 0x1D0 -#define MEM1DRVCON_OFFSET 0x1D4 -#define GPKCON0_OFFSET 0x800 -#define GPKCON1_OFFSET 0x804 -#define GPKDAT_OFFSET 0x808 -#define GPKPUD_OFFSET 0x80C -#define GPLCON0_OFFSET 0x810 -#define GPLCON1_OFFSET 0x814 -#define GPLDAT_OFFSET 0x818 -#define GPLPUD_OFFSET 0x81C -#define GPMCON_OFFSET 0x820 -#define GPMDAT_OFFSET 0x824 -#define GPMPUD_OFFSET 0x828 -#define GPNCON_OFFSET 0x830 -#define GPNDAT_OFFSET 0x834 -#define GPNPUD_OFFSET 0x838 -#define GPOCON_OFFSET 0x140 -#define GPODAT_OFFSET 0x144 -#define GPOPUD_OFFSET 0x148 -#define GPOCONSLP_OFFSET 0x14C -#define GPOPUDSLP_OFFSET 0x150 -#define GPPCON_OFFSET 0x160 -#define GPPDAT_OFFSET 0x164 -#define GPPPUD_OFFSET 0x168 -#define GPPCONSLP_OFFSET 0x16C -#define GPPPUDSLP_OFFSET 0x170 -#define GPQCON_OFFSET 0x180 -#define GPQDAT_OFFSET 0x184 -#define GPQPUD_OFFSET 0x188 -#define GPQCONSLP_OFFSET 0x18C -#define GPQPUDSLP_OFFSET 0x190 - -#define EINTPEND_OFFSET 0x924 - -#define GPACON_REG __REG(ELFIN_GPIO_BASE + GPACON_OFFSET) -#define GPADAT_REG __REG(ELFIN_GPIO_BASE + GPADAT_OFFSET) -#define GPAPUD_REG __REG(ELFIN_GPIO_BASE + GPAPUD_OFFSET) -#define GPACONSLP_REG __REG(ELFIN_GPIO_BASE + GPACONSLP_OFFSET) -#define GPAPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) -#define GPBCON_REG __REG(ELFIN_GPIO_BASE + GPBCON_OFFSET) -#define GPBDAT_REG __REG(ELFIN_GPIO_BASE + GPBDAT_OFFSET) -#define GPBPUD_REG __REG(ELFIN_GPIO_BASE + GPBPUD_OFFSET) -#define GPBCONSLP_REG __REG(ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) -#define GPBPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) -#define GPCCON_REG __REG(ELFIN_GPIO_BASE + GPCCON_OFFSET) -#define GPCDAT_REG __REG(ELFIN_GPIO_BASE + GPCDAT_OFFSET) -#define GPCPUD_REG __REG(ELFIN_GPIO_BASE + GPCPUD_OFFSET) -#define GPCCONSLP_REG __REG(ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) -#define GPCPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) -#define GPDCON_REG __REG(ELFIN_GPIO_BASE + GPDCON_OFFSET) -#define GPDDAT_REG __REG(ELFIN_GPIO_BASE + GPDDAT_OFFSET) -#define GPDPUD_REG __REG(ELFIN_GPIO_BASE + GPDPUD_OFFSET) -#define GPDCONSLP_REG __REG(ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) -#define GPDPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) -#define GPECON_REG __REG(ELFIN_GPIO_BASE + GPECON_OFFSET) -#define GPEDAT_REG __REG(ELFIN_GPIO_BASE + GPEDAT_OFFSET) -#define GPEPUD_REG __REG(ELFIN_GPIO_BASE + GPEPUD_OFFSET) -#define GPECONSLP_REG __REG(ELFIN_GPIO_BASE + GPECONSLP_OFFSET) -#define GPEPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) -#define GPFCON_REG __REG(ELFIN_GPIO_BASE + GPFCON_OFFSET) -#define GPFDAT_REG __REG(ELFIN_GPIO_BASE + GPFDAT_OFFSET) -#define GPFPUD_REG __REG(ELFIN_GPIO_BASE + GPFPUD_OFFSET) -#define GPFCONSLP_REG __REG(ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) -#define GPFPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) -#define GPGCON_REG __REG(ELFIN_GPIO_BASE + GPGCON_OFFSET) -#define GPGDAT_REG __REG(ELFIN_GPIO_BASE + GPGDAT_OFFSET) -#define GPGPUD_REG __REG(ELFIN_GPIO_BASE + GPGPUD_OFFSET) -#define GPGCONSLP_REG __REG(ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) -#define GPGPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) -#define GPHCON0_REG __REG(ELFIN_GPIO_BASE + GPHCON0_OFFSET) -#define GPHCON1_REG __REG(ELFIN_GPIO_BASE + GPHCON1_OFFSET) -#define GPHDAT_REG __REG(ELFIN_GPIO_BASE + GPHDAT_OFFSET) -#define GPHPUD_REG __REG(ELFIN_GPIO_BASE + GPHPUD_OFFSET) -#define GPHCONSLP_REG __REG(ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) -#define GPHPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) -#define GPICON_REG __REG(ELFIN_GPIO_BASE + GPICON_OFFSET) -#define GPIDAT_REG __REG(ELFIN_GPIO_BASE + GPIDAT_OFFSET) -#define GPIPUD_REG __REG(ELFIN_GPIO_BASE + GPIPUD_OFFSET) -#define GPICONSLP_REG __REG(ELFIN_GPIO_BASE + GPICONSLP_OFFSET) -#define GPIPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) -#define GPJCON_REG __REG(ELFIN_GPIO_BASE + GPJCON_OFFSET) -#define GPJDAT_REG __REG(ELFIN_GPIO_BASE + GPJDAT_OFFSET) -#define GPJPUD_REG __REG(ELFIN_GPIO_BASE + GPJPUD_OFFSET) -#define GPJCONSLP_REG __REG(ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) -#define GPJPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) -#define GPKCON0_REG __REG(ELFIN_GPIO_BASE + GPKCON0_OFFSET) -#define GPKCON1_REG __REG(ELFIN_GPIO_BASE + GPKCON1_OFFSET) -#define GPKDAT_REG __REG(ELFIN_GPIO_BASE + GPKDAT_OFFSET) -#define GPKPUD_REG __REG(ELFIN_GPIO_BASE + GPKPUD_OFFSET) -#define GPLCON0_REG __REG(ELFIN_GPIO_BASE + GPLCON0_OFFSET) -#define GPLCON1_REG __REG(ELFIN_GPIO_BASE + GPLCON1_OFFSET) -#define GPLDAT_REG __REG(ELFIN_GPIO_BASE + GPLDAT_OFFSET) -#define GPLPUD_REG __REG(ELFIN_GPIO_BASE + GPLPUD_OFFSET) -#define GPMCON_REG __REG(ELFIN_GPIO_BASE + GPMCON_OFFSET) -#define GPMDAT_REG __REG(ELFIN_GPIO_BASE + GPMDAT_OFFSET) -#define GPMPUD_REG __REG(ELFIN_GPIO_BASE + GPMPUD_OFFSET) -#define GPNCON_REG __REG(ELFIN_GPIO_BASE + GPNCON_OFFSET) -#define GPNDAT_REG __REG(ELFIN_GPIO_BASE + GPNDAT_OFFSET) -#define GPNPUD_REG __REG(ELFIN_GPIO_BASE + GPNPUD_OFFSET) -#define GPOCON_REG __REG(ELFIN_GPIO_BASE + GPOCON_OFFSET) -#define GPODAT_REG __REG(ELFIN_GPIO_BASE + GPODAT_OFFSET) -#define GPOPUD_REG __REG(ELFIN_GPIO_BASE + GPOPUD_OFFSET) -#define GPOCONSLP_REG __REG(ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) -#define GPOPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) -#define GPPCON_REG __REG(ELFIN_GPIO_BASE + GPPCON_OFFSET) -#define GPPDAT_REG __REG(ELFIN_GPIO_BASE + GPPDAT_OFFSET) -#define GPPPUD_REG __REG(ELFIN_GPIO_BASE + GPPPUD_OFFSET) -#define GPPCONSLP_REG __REG(ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) -#define GPPPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) -#define GPQCON_REG __REG(ELFIN_GPIO_BASE + GPQCON_OFFSET) -#define GPQDAT_REG __REG(ELFIN_GPIO_BASE + GPQDAT_OFFSET) -#define GPQPUD_REG __REG(ELFIN_GPIO_BASE + GPQPUD_OFFSET) -#define GPQCONSLP_REG __REG(ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) -#define GPQPUDSLP_REG __REG(ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) - -/* - * Bus Matrix - */ -#define ELFIN_MEM_SYS_CFG 0x7e00f120 - -#define S3C64XX_MEM_SYS_CFG_16BIT (1 << 12) - -#define S3C64XX_MEM_SYS_CFG_NAND 0x0008 -#define S3C64XX_MEM_SYS_CFG_ONENAND S3C64XX_MEM_SYS_CFG_16BIT - -#define GPACON (ELFIN_GPIO_BASE + GPACON_OFFSET) -#define GPADAT (ELFIN_GPIO_BASE + GPADAT_OFFSET) -#define GPAPUD (ELFIN_GPIO_BASE + GPAPUD_OFFSET) -#define GPACONSLP (ELFIN_GPIO_BASE + GPACONSLP_OFFSET) -#define GPAPUDSLP (ELFIN_GPIO_BASE + GPAPUDSLP_OFFSET) -#define GPBCON (ELFIN_GPIO_BASE + GPBCON_OFFSET) -#define GPBDAT (ELFIN_GPIO_BASE + GPBDAT_OFFSET) -#define GPBPUD (ELFIN_GPIO_BASE + GPBPUD_OFFSET) -#define GPBCONSLP (ELFIN_GPIO_BASE + GPBCONSLP_OFFSET) -#define GPBPUDSLP (ELFIN_GPIO_BASE + GPBPUDSLP_OFFSET) -#define GPCCON (ELFIN_GPIO_BASE + GPCCON_OFFSET) -#define GPCDAT (ELFIN_GPIO_BASE + GPCDAT_OFFSET) -#define GPCPUD (ELFIN_GPIO_BASE + GPCPUD_OFFSET) -#define GPCCONSLP (ELFIN_GPIO_BASE + GPCCONSLP_OFFSET) -#define GPCPUDSLP (ELFIN_GPIO_BASE + GPCPUDSLP_OFFSET) -#define GPDCON (ELFIN_GPIO_BASE + GPDCON_OFFSET) -#define GPDDAT (ELFIN_GPIO_BASE + GPDDAT_OFFSET) -#define GPDPUD (ELFIN_GPIO_BASE + GPDPUD_OFFSET) -#define GPDCONSLP (ELFIN_GPIO_BASE + GPDCONSLP_OFFSET) -#define GPDPUDSLP (ELFIN_GPIO_BASE + GPDPUDSLP_OFFSET) -#define GPECON (ELFIN_GPIO_BASE + GPECON_OFFSET) -#define GPEDAT (ELFIN_GPIO_BASE + GPEDAT_OFFSET) -#define GPEPUD (ELFIN_GPIO_BASE + GPEPUD_OFFSET) -#define GPECONSLP (ELFIN_GPIO_BASE + GPECONSLP_OFFSET) -#define GPEPUDSLP (ELFIN_GPIO_BASE + GPEPUDSLP_OFFSET) -#define GPFCON (ELFIN_GPIO_BASE + GPFCON_OFFSET) -#define GPFDAT (ELFIN_GPIO_BASE + GPFDAT_OFFSET) -#define GPFPUD (ELFIN_GPIO_BASE + GPFPUD_OFFSET) -#define GPFCONSLP (ELFIN_GPIO_BASE + GPFCONSLP_OFFSET) -#define GPFPUDSLP (ELFIN_GPIO_BASE + GPFPUDSLP_OFFSET) -#define GPGCON (ELFIN_GPIO_BASE + GPGCON_OFFSET) -#define GPGDAT (ELFIN_GPIO_BASE + GPGDAT_OFFSET) -#define GPGPUD (ELFIN_GPIO_BASE + GPGPUD_OFFSET) -#define GPGCONSLP (ELFIN_GPIO_BASE + GPGCONSLP_OFFSET) -#define GPGPUDSLP (ELFIN_GPIO_BASE + GPGPUDSLP_OFFSET) -#define GPHCON0 (ELFIN_GPIO_BASE + GPHCON0_OFFSET) -#define GPHCON1 (ELFIN_GPIO_BASE + GPHCON1_OFFSET) -#define GPHDAT (ELFIN_GPIO_BASE + GPHDAT_OFFSET) -#define GPHPUD (ELFIN_GPIO_BASE + GPHPUD_OFFSET) -#define GPHCONSLP (ELFIN_GPIO_BASE + GPHCONSLP_OFFSET) -#define GPHPUDSLP (ELFIN_GPIO_BASE + GPHPUDSLP_OFFSET) -#define GPICON (ELFIN_GPIO_BASE + GPICON_OFFSET) -#define GPIDAT (ELFIN_GPIO_BASE + GPIDAT_OFFSET) -#define GPIPUD (ELFIN_GPIO_BASE + GPIPUD_OFFSET) -#define GPICONSLP (ELFIN_GPIO_BASE + GPICONSLP_OFFSET) -#define GPIPUDSLP (ELFIN_GPIO_BASE + GPIPUDSLP_OFFSET) -#define GPJCON (ELFIN_GPIO_BASE + GPJCON_OFFSET) -#define GPJDAT (ELFIN_GPIO_BASE + GPJDAT_OFFSET) -#define GPJPUD (ELFIN_GPIO_BASE + GPJPUD_OFFSET) -#define GPJCONSLP (ELFIN_GPIO_BASE + GPJCONSLP_OFFSET) -#define GPJPUDSLP (ELFIN_GPIO_BASE + GPJPUDSLP_OFFSET) -#define GPKCON0 (ELFIN_GPIO_BASE + GPKCON0_OFFSET) -#define GPKCON1 (ELFIN_GPIO_BASE + GPKCON1_OFFSET) -#define GPKDAT (ELFIN_GPIO_BASE + GPKDAT_OFFSET) -#define GPKPUD (ELFIN_GPIO_BASE + GPKPUD_OFFSET) -#define GPLCON0 (ELFIN_GPIO_BASE + GPLCON0_OFFSET) -#define GPLCON1 (ELFIN_GPIO_BASE + GPLCON1_OFFSET) -#define GPLDAT (ELFIN_GPIO_BASE + GPLDAT_OFFSET) -#define GPLPUD (ELFIN_GPIO_BASE + GPLPUD_OFFSET) -#define GPMCON (ELFIN_GPIO_BASE + GPMCON_OFFSET) -#define GPMDAT (ELFIN_GPIO_BASE + GPMDAT_OFFSET) -#define GPMPUD (ELFIN_GPIO_BASE + GPMPUD_OFFSET) -#define GPNCON (ELFIN_GPIO_BASE + GPNCON_OFFSET) -#define GPNDAT (ELFIN_GPIO_BASE + GPNDAT_OFFSET) -#define GPNPUD (ELFIN_GPIO_BASE + GPNPUD_OFFSET) -#define GPOCON (ELFIN_GPIO_BASE + GPOCON_OFFSET) -#define GPODAT (ELFIN_GPIO_BASE + GPODAT_OFFSET) -#define GPOPUD (ELFIN_GPIO_BASE + GPOPUD_OFFSET) -#define GPOCONSLP (ELFIN_GPIO_BASE + GPOCONSLP_OFFSET) -#define GPOPUDSLP (ELFIN_GPIO_BASE + GPOPUDSLP_OFFSET) -#define GPPCON (ELFIN_GPIO_BASE + GPPCON_OFFSET) -#define GPPDAT (ELFIN_GPIO_BASE + GPPDAT_OFFSET) -#define GPPPUD (ELFIN_GPIO_BASE + GPPPUD_OFFSET) -#define GPPCONSLP (ELFIN_GPIO_BASE + GPPCONSLP_OFFSET) -#define GPPPUDSLP (ELFIN_GPIO_BASE + GPPPUDSLP_OFFSET) -#define GPQCON (ELFIN_GPIO_BASE + GPQCON_OFFSET) -#define GPQDAT (ELFIN_GPIO_BASE + GPQDAT_OFFSET) -#define GPQPUD (ELFIN_GPIO_BASE + GPQPUD_OFFSET) -#define GPQCONSLP (ELFIN_GPIO_BASE + GPQCONSLP_OFFSET) -#define GPQPUDSLP (ELFIN_GPIO_BASE + GPQPUDSLP_OFFSET) - -/* - * Memory controller - */ -#define ELFIN_SROM_BASE 0x70000000 - -#define SROM_BW_REG __REG(ELFIN_SROM_BASE + 0x0) -#define SROM_BC0_REG __REG(ELFIN_SROM_BASE + 0x4) -#define SROM_BC1_REG __REG(ELFIN_SROM_BASE + 0x8) -#define SROM_BC2_REG __REG(ELFIN_SROM_BASE + 0xC) -#define SROM_BC3_REG __REG(ELFIN_SROM_BASE + 0x10) -#define SROM_BC4_REG __REG(ELFIN_SROM_BASE + 0x14) -#define SROM_BC5_REG __REG(ELFIN_SROM_BASE + 0x18) - -/* - * SDRAM Controller - */ -#define ELFIN_DMC0_BASE 0x7e000000 -#define ELFIN_DMC1_BASE 0x7e001000 - -#define INDEX_DMC_MEMC_STATUS 0x00 -#define INDEX_DMC_MEMC_CMD 0x04 -#define INDEX_DMC_DIRECT_CMD 0x08 -#define INDEX_DMC_MEMORY_CFG 0x0C -#define INDEX_DMC_REFRESH_PRD 0x10 -#define INDEX_DMC_CAS_LATENCY 0x14 -#define INDEX_DMC_T_DQSS 0x18 -#define INDEX_DMC_T_MRD 0x1C -#define INDEX_DMC_T_RAS 0x20 -#define INDEX_DMC_T_RC 0x24 -#define INDEX_DMC_T_RCD 0x28 -#define INDEX_DMC_T_RFC 0x2C -#define INDEX_DMC_T_RP 0x30 -#define INDEX_DMC_T_RRD 0x34 -#define INDEX_DMC_T_WR 0x38 -#define INDEX_DMC_T_WTR 0x3C -#define INDEX_DMC_T_XP 0x40 -#define INDEX_DMC_T_XSR 0x44 -#define INDEX_DMC_T_ESR 0x48 -#define INDEX_DMC_MEMORY_CFG2 0x4C -#define INDEX_DMC_CHIP_0_CFG 0x200 -#define INDEX_DMC_CHIP_1_CFG 0x204 -#define INDEX_DMC_CHIP_2_CFG 0x208 -#define INDEX_DMC_CHIP_3_CFG 0x20C -#define INDEX_DMC_USER_STATUS 0x300 -#define INDEX_DMC_USER_CONFIG 0x304 - -/* - * Memory Chip direct command - */ -#define DMC_NOP0 0x0c0000 -#define DMC_NOP1 0x1c0000 -#define DMC_PA0 0x000000 /* Precharge all */ -#define DMC_PA1 0x100000 -#define DMC_AR0 0x040000 /* Autorefresh */ -#define DMC_AR1 0x140000 -#define DMC_SDR_MR0 0x080032 /* MRS, CAS 3, Burst Length 4 */ -#define DMC_SDR_MR1 0x180032 -#define DMC_DDR_MR0 0x080162 -#define DMC_DDR_MR1 0x180162 -#define DMC_mDDR_MR0 0x080032 /* CAS 3, Burst Length 4 */ -#define DMC_mDDR_MR1 0x180032 -#define DMC_mSDR_EMR0 0x0a0000 /* EMRS, DS:Full, PASR:Full Array */ -#define DMC_mSDR_EMR1 0x1a0000 -#define DMC_DDR_EMR0 0x090000 -#define DMC_DDR_EMR1 0x190000 -#define DMC_mDDR_EMR0 0x0a0000 /* DS:Full, PASR:Full Array */ -#define DMC_mDDR_EMR1 0x1a0000 - -/* - * Definitions for memory configuration - * Set memory configuration - * active_chips = 1'b0 (1 chip) - * qos_master_chip = 3'b000(ARID[3:0]) - * memory burst = 3'b010(burst 4) - * stop_mem_clock = 1'b0(disable dynamical stop) - * auto_power_down = 1'b0(disable auto power-down mode) - * power_down_prd = 6'b00_0000(0 cycle for auto power-down) - * ap_bit = 1'b0 (bit position of auto-precharge is 10) - * row_bits = 3'b010(# row address 13) - * column_bits = 3'b010(# column address 10 ) - * - * Set user configuration - * 2'b10=SDRAM/mSDRAM, 2'b11=DDR, 2'b01=mDDR - * - * Set chip select for chip [n] - * row bank control, bank address 0x3000_0000 ~ 0x37ff_ffff - * CHIP_[n]_CFG=0x30F8, 30: ADDR[31:24], F8: Mask[31:24] - */ - -/* - * Nand flash controller - */ -#define ELFIN_NAND_BASE 0x70200000 - -#define NFCONF_OFFSET 0x00 -#define NFCONT_OFFSET 0x04 -#define NFCMMD_OFFSET 0x08 -#define NFADDR_OFFSET 0x0c -#define NFDATA_OFFSET 0x10 -#define NFMECCDATA0_OFFSET 0x14 -#define NFMECCDATA1_OFFSET 0x18 -#define NFSECCDATA0_OFFSET 0x1c -#define NFSBLK_OFFSET 0x20 -#define NFEBLK_OFFSET 0x24 -#define NFSTAT_OFFSET 0x28 -#define NFESTAT0_OFFSET 0x2c -#define NFESTAT1_OFFSET 0x30 -#define NFMECC0_OFFSET 0x34 -#define NFMECC1_OFFSET 0x38 -#define NFSECC_OFFSET 0x3c -#define NFMLCBITPT_OFFSET 0x40 - -#define NFCONF (ELFIN_NAND_BASE + NFCONF_OFFSET) -#define NFCONT (ELFIN_NAND_BASE + NFCONT_OFFSET) -#define NFCMMD (ELFIN_NAND_BASE + NFCMMD_OFFSET) -#define NFADDR (ELFIN_NAND_BASE + NFADDR_OFFSET) -#define NFDATA (ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFMECCDATA0 (ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) -#define NFMECCDATA1 (ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) -#define NFSECCDATA0 (ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) -#define NFSBLK (ELFIN_NAND_BASE + NFSBLK_OFFSET) -#define NFEBLK (ELFIN_NAND_BASE + NFEBLK_OFFSET) -#define NFSTAT (ELFIN_NAND_BASE + NFSTAT_OFFSET) -#define NFESTAT0 (ELFIN_NAND_BASE + NFESTAT0_OFFSET) -#define NFESTAT1 (ELFIN_NAND_BASE + NFESTAT1_OFFSET) -#define NFMECC0 (ELFIN_NAND_BASE + NFMECC0_OFFSET) -#define NFMECC1 (ELFIN_NAND_BASE + NFMECC1_OFFSET) -#define NFSECC (ELFIN_NAND_BASE + NFSECC_OFFSET) -#define NFMLCBITPT (ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) - -#define NFCONF_REG __REG(ELFIN_NAND_BASE + NFCONF_OFFSET) -#define NFCONT_REG __REG(ELFIN_NAND_BASE + NFCONT_OFFSET) -#define NFCMD_REG __REG(ELFIN_NAND_BASE + NFCMMD_OFFSET) -#define NFADDR_REG __REG(ELFIN_NAND_BASE + NFADDR_OFFSET) -#define NFDATA_REG __REG(ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFDATA8_REG __REGb(ELFIN_NAND_BASE + NFDATA_OFFSET) -#define NFMECCDATA0_REG __REG(ELFIN_NAND_BASE + NFMECCDATA0_OFFSET) -#define NFMECCDATA1_REG __REG(ELFIN_NAND_BASE + NFMECCDATA1_OFFSET) -#define NFSECCDATA0_REG __REG(ELFIN_NAND_BASE + NFSECCDATA0_OFFSET) -#define NFSBLK_REG __REG(ELFIN_NAND_BASE + NFSBLK_OFFSET) -#define NFEBLK_REG __REG(ELFIN_NAND_BASE + NFEBLK_OFFSET) -#define NFSTAT_REG __REG(ELFIN_NAND_BASE + NFSTAT_OFFSET) -#define NFESTAT0_REG __REG(ELFIN_NAND_BASE + NFESTAT0_OFFSET) -#define NFESTAT1_REG __REG(ELFIN_NAND_BASE + NFESTAT1_OFFSET) -#define NFMECC0_REG __REG(ELFIN_NAND_BASE + NFMECC0_OFFSET) -#define NFMECC1_REG __REG(ELFIN_NAND_BASE + NFMECC1_OFFSET) -#define NFSECC_REG __REG(ELFIN_NAND_BASE + NFSECC_OFFSET) -#define NFMLCBITPT_REG __REG(ELFIN_NAND_BASE + NFMLCBITPT_OFFSET) - -#define NFCONF_ECC_4BIT (1<<24) - -#define NFCONT_ECC_ENC (1<<18) -#define NFCONT_WP (1<<16) -#define NFCONT_MECCLOCK (1<<7) -#define NFCONT_SECCLOCK (1<<6) -#define NFCONT_INITMECC (1<<5) -#define NFCONT_INITSECC (1<<4) -#define NFCONT_INITECC (NFCONT_INITMECC | NFCONT_INITSECC) -#define NFCONT_CS_ALT (1<<2) -#define NFCONT_CS (1<<1) -#define NFCONT_ENABLE (1<<0) - -#define NFSTAT_ECCENCDONE (1<<7) -#define NFSTAT_ECCDECDONE (1<<6) -#define NFSTAT_RnB (1<<0) - -#define NFESTAT0_ECCBUSY (1<<31) - -/* - * Interrupt - */ -#define ELFIN_VIC0_BASE_ADDR 0x71200000 -#define ELFIN_VIC1_BASE_ADDR 0x71300000 -#define oINTMOD 0x0C /* VIC INT SELECT (IRQ or FIQ) */ -#define oINTUNMSK 0x10 /* VIC INT EN (write 1 to unmask) */ -#define oINTMSK 0x14 /* VIC INT EN CLEAR (write 1 to mask) */ -#define oINTSUBMSK 0x1C /* VIC SOFT INT CLEAR */ -#define oVECTADDR 0xF00 /* VIC ADDRESS */ - -/* - * Watchdog timer - */ -#define ELFIN_WATCHDOG_BASE 0x7E004000 - -#define WTCON_REG __REG(0x7E004004) -#define WTDAT_REG __REG(0x7E004008) -#define WTCNT_REG __REG(0x7E00400C) - - -/* - * UART - */ -#define ELFIN_UART_BASE 0x7F005000 - -#define ELFIN_UART0_OFFSET 0x0000 -#define ELFIN_UART1_OFFSET 0x0400 -#define ELFIN_UART2_OFFSET 0x0800 - -#define ULCON_OFFSET 0x00 -#define UCON_OFFSET 0x04 -#define UFCON_OFFSET 0x08 -#define UMCON_OFFSET 0x0C -#define UTRSTAT_OFFSET 0x10 -#define UERSTAT_OFFSET 0x14 -#define UFSTAT_OFFSET 0x18 -#define UMSTAT_OFFSET 0x1C -#define UTXH_OFFSET 0x20 -#define URXH_OFFSET 0x24 -#define UBRDIV_OFFSET 0x28 -#define UDIVSLOT_OFFSET 0x2C -#define UINTP_OFFSET 0x30 -#define UINTSP_OFFSET 0x34 -#define UINTM_OFFSET 0x38 - -#define ULCON0_REG __REG(0x7F005000) -#define UCON0_REG __REG(0x7F005004) -#define UFCON0_REG __REG(0x7F005008) -#define UMCON0_REG __REG(0x7F00500C) -#define UTRSTAT0_REG __REG(0x7F005010) -#define UERSTAT0_REG __REG(0x7F005014) -#define UFSTAT0_REG __REG(0x7F005018) -#define UMSTAT0_REG __REG(0x7F00501c) -#define UTXH0_REG __REG(0x7F005020) -#define URXH0_REG __REG(0x7F005024) -#define UBRDIV0_REG __REG(0x7F005028) -#define UDIVSLOT0_REG __REG(0x7F00502c) -#define UINTP0_REG __REG(0x7F005030) -#define UINTSP0_REG __REG(0x7F005034) -#define UINTM0_REG __REG(0x7F005038) - -#define ULCON1_REG __REG(0x7F005400) -#define UCON1_REG __REG(0x7F005404) -#define UFCON1_REG __REG(0x7F005408) -#define UMCON1_REG __REG(0x7F00540C) -#define UTRSTAT1_REG __REG(0x7F005410) -#define UERSTAT1_REG __REG(0x7F005414) -#define UFSTAT1_REG __REG(0x7F005418) -#define UMSTAT1_REG __REG(0x7F00541c) -#define UTXH1_REG __REG(0x7F005420) -#define URXH1_REG __REG(0x7F005424) -#define UBRDIV1_REG __REG(0x7F005428) -#define UDIVSLOT1_REG __REG(0x7F00542c) -#define UINTP1_REG __REG(0x7F005430) -#define UINTSP1_REG __REG(0x7F005434) -#define UINTM1_REG __REG(0x7F005438) - -#define UTRSTAT_TX_EMPTY (1 << 2) -#define UTRSTAT_RX_READY (1 << 0) -#define UART_ERR_MASK 0xF - -/* - * PWM timer - */ -#define ELFIN_TIMER_BASE 0x7F006000 - -#define TCFG0_REG __REG(0x7F006000) -#define TCFG1_REG __REG(0x7F006004) -#define TCON_REG __REG(0x7F006008) -#define TCNTB0_REG __REG(0x7F00600c) -#define TCMPB0_REG __REG(0x7F006010) -#define TCNTO0_REG __REG(0x7F006014) -#define TCNTB1_REG __REG(0x7F006018) -#define TCMPB1_REG __REG(0x7F00601c) -#define TCNTO1_REG __REG(0x7F006020) -#define TCNTB2_REG __REG(0x7F006024) -#define TCMPB2_REG __REG(0x7F006028) -#define TCNTO2_REG __REG(0x7F00602c) -#define TCNTB3_REG __REG(0x7F006030) -#define TCMPB3_REG __REG(0x7F006034) -#define TCNTO3_REG __REG(0x7F006038) -#define TCNTB4_REG __REG(0x7F00603c) -#define TCNTO4_REG __REG(0x7F006040) - -/* Fields */ -#define fTCFG0_DZONE Fld(8, 16) /* the dead zone length (=timer 0) */ -#define fTCFG0_PRE1 Fld(8, 8) /* prescaler value for time 2,3,4 */ -#define fTCFG0_PRE0 Fld(8, 0) /* prescaler value for time 0,1 */ -#define fTCFG1_MUX4 Fld(4, 16) -/* bits */ -#define TCFG0_DZONE(x) FInsrt((x), fTCFG0_DZONE) -#define TCFG0_PRE1(x) FInsrt((x), fTCFG0_PRE1) -#define TCFG0_PRE0(x) FInsrt((x), fTCFG0_PRE0) -#define TCON_4_AUTO (1 << 22) /* auto reload on/off for Timer 4 */ -#define TCON_4_UPDATE (1 << 21) /* manual Update TCNTB4 */ -#define TCON_4_ONOFF (1 << 20) /* 0: Stop, 1: start Timer 4 */ -#define COUNT_4_ON (TCON_4_ONOFF * 1) -#define COUNT_4_OFF (TCON_4_ONOFF * 0) -#define TCON_3_AUTO (1 << 19) /* auto reload on/off for Timer 3 */ -#define TIMER3_ATLOAD_ON (TCON_3_AUTO * 1) -#define TIMER3_ATLAOD_OFF FClrBit(TCON, TCON_3_AUTO) -#define TCON_3_INVERT (1 << 18) /* 1: Inverter on for TOUT3 */ -#define TIMER3_IVT_ON (TCON_3_INVERT * 1) -#define TIMER3_IVT_OFF (FClrBit(TCON, TCON_3_INVERT)) -#define TCON_3_MAN (1 << 17) /* manual Update TCNTB3,TCMPB3 */ -#define TIMER3_MANUP (TCON_3_MAN*1) -#define TIMER3_NOP (FClrBit(TCON, TCON_3_MAN)) -#define TCON_3_ONOFF (1 << 16) /* 0: Stop, 1: start Timer 3 */ -#define TIMER3_ON (TCON_3_ONOFF * 1) -#define TIMER3_OFF (FClrBit(TCON, TCON_3_ONOFF)) - -#if defined(CONFIG_CLK_400_100_50) -#define STARTUP_AMDIV 400 -#define STARTUP_MDIV 400 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_400_133_66) -#define STARTUP_AMDIV 400 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_533_133_66) -#define STARTUP_AMDIV 533 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#elif defined(CONFIG_CLK_667_133_66) -#define STARTUP_AMDIV 667 -#define STARTUP_MDIV 533 -#define STARTUP_PDIV 6 -#define STARTUP_SDIV 1 -#endif - -#define STARTUP_PCLKDIV 3 -#define STARTUP_HCLKX2DIV 1 -#define STARTUP_HCLKDIV 1 -#define STARTUP_MPLLDIV 1 -#define STARTUP_APLLDIV 0 - -#define CLK_DIV_VAL ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \ - (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV) -#define MPLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_MPLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_MDIV) - -#if defined(CONFIG_SYNC_MODE) -#define APLL_VAL ((1 << 31) | (STARTUP_MDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_MDIV) -#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ - (STARTUP_HCLKDIV + 1)) -#else -#define APLL_VAL ((1 << 31) | (STARTUP_AMDIV << 16) | \ - (STARTUP_PDIV << 8) | STARTUP_SDIV) -#define STARTUP_APLL (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \ - STARTUP_PDIV) * STARTUP_AMDIV) -#define STARTUP_HCLK (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \ - (STARTUP_HCLKDIV + 1)) -#endif - - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */ -#define DMC1_MEM_CFG2 0xB45 -#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) */ -#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ - -/* Memory Parameters */ -/* DDR Parameters */ -#define DDR_tREFRESH 7800 /* ns */ -#define DDR_tRAS 45 /* ns (min: 45ns)*/ -#define DDR_tRC 68 /* ns (min: 67.5ns)*/ -#define DDR_tRCD 23 /* ns (min: 22.5ns)*/ -#define DDR_tRFC 80 /* ns (min: 80ns)*/ -#define DDR_tRP 23 /* ns (min: 22.5ns)*/ -#define DDR_tRRD 15 /* ns (min: 15ns)*/ -#define DDR_tWR 15 /* ns (min: 15ns)*/ -#define DDR_tXSR 120 /* ns (min: 120ns)*/ -#define DDR_CASL 3 /* CAS Latency 3 */ - -/* - * mDDR memory configuration - */ - -#define NS_TO_CLK(t) ((STARTUP_HCLK / 1000 * (t) - 1) / 1000000) - -#define DMC_DDR_BA_EMRS 2 -#define DMC_DDR_MEM_CASLAT 3 -/* 6 Set Cas Latency to 3 */ -#define DMC_DDR_CAS_LATENCY (DDR_CASL << 1) -/* Min 0.75 ~ 1.25 */ -#define DMC_DDR_t_DQSS 1 -/* Min 2 tck */ -#define DMC_DDR_t_MRD 2 -/* 7, Min 45ns */ -#define DMC_DDR_t_RAS (NS_TO_CLK(DDR_tRAS) + 1) -/* 10, Min 67.5ns */ -#define DMC_DDR_t_RC (NS_TO_CLK(DDR_tRC) + 1) -/* 4,5(TRM), Min 22.5ns */ -#define DMC_DDR_t_RCD (NS_TO_CLK(DDR_tRCD) + 1) -#define DMC_DDR_schedule_RCD ((DMC_DDR_t_RCD - 3) << 3) -/* 11,18(TRM) Min 80ns */ -#define DMC_DDR_t_RFC (NS_TO_CLK(DDR_tRFC) + 1) -#define DMC_DDR_schedule_RFC ((DMC_DDR_t_RFC - 3) << 5) -/* 4, 5(TRM) Min 22.5ns */ -#define DMC_DDR_t_RP (NS_TO_CLK(DDR_tRP) + 1) -#define DMC_DDR_schedule_RP ((DMC_DDR_t_RP - 3) << 3) -/* 3, Min 15ns */ -#define DMC_DDR_t_RRD (NS_TO_CLK(DDR_tRRD) + 1) -/* Min 15ns */ -#define DMC_DDR_t_WR (NS_TO_CLK(DDR_tWR) + 1) -#define DMC_DDR_t_WTR 2 -/* 1tck + tIS(1.5ns) */ -#define DMC_DDR_t_XP 2 -/* 17, Min 120ns */ -#define DMC_DDR_t_XSR (NS_TO_CLK(DDR_tXSR) + 1) -#define DMC_DDR_t_ESR DMC_DDR_t_XSR -/* TRM 2656 */ -#define DMC_DDR_REFRESH_PRD (NS_TO_CLK(DDR_tREFRESH)) -/* 2b01 : mDDR */ -#define DMC_DDR_USER_CONFIG 1 - -#ifndef __ASSEMBLY__ -enum s3c64xx_uarts_nr { - S3C64XX_UART0, - S3C64XX_UART1, - S3C64XX_UART2, -}; - -#include "s3c64x0.h" - -static inline s3c64xx_uart *s3c64xx_get_base_uart(enum s3c64xx_uarts_nr nr) -{ - return (s3c64xx_uart *)(ELFIN_UART_BASE + (nr * 0x400)); -} -#endif - -#endif /*__S3C6400_H__*/ diff --git a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h b/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h deleted file mode 100644 index 0bbf1d0..0000000 --- a/arch/arm/include/asm/arch-s3c64xx/s3c64x0.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * (C) Copyright 2003 - * David MÃŒller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/************************************************ - * NAME : S3C64XX.h - * Version : 31.3.2003 - * - * common stuff for SAMSUNG S3C64XX SoC - ************************************************/ - -#ifndef __S3C64XX_H__ -#define __S3C64XX_H__ - -#if defined(CONFIG_SYNC_MODE) && defined(CONFIG_S3C6400) -#error CONFIG_SYNC_MODE unavailable on S3C6400, please, fix your configuration! -#endif - -#include <asm/types.h> - -/* UART (see manual chapter 11) */ -typedef struct { - volatile u32 ULCON; - volatile u32 UCON; - volatile u32 UFCON; - volatile u32 UMCON; - volatile u32 UTRSTAT; - volatile u32 UERSTAT; - volatile u32 UFSTAT; - volatile u32 UMSTAT; -#ifdef __BIG_ENDIAN - volatile u8 res1[3]; - volatile u8 UTXH; - volatile u8 res2[3]; - volatile u8 URXH; -#else /* Little Endian */ - volatile u8 UTXH; - volatile u8 res1[3]; - volatile u8 URXH; - volatile u8 res2[3]; -#endif - volatile u32 UBRDIV; -#ifdef __BIG_ENDIAN - volatile u8 res3[2]; - volatile u16 UDIVSLOT; -#else - volatile u16 UDIVSLOT; - volatile u8 res3[2]; -#endif -} s3c64xx_uart; - -/* PWM TIMER (see manual chapter 10) */ -typedef struct { - volatile u32 TCNTB; - volatile u32 TCMPB; - volatile u32 TCNTO; -} s3c64xx_timer; - -typedef struct { - volatile u32 TCFG0; - volatile u32 TCFG1; - volatile u32 TCON; - s3c64xx_timer ch[4]; - volatile u32 TCNTB4; - volatile u32 TCNTO4; -} s3c64xx_timers; - -#endif /*__S3C64XX_H__*/ diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h index 3db0d93..1a66990 100644 --- a/arch/arm/include/asm/arch-tegra/board.h +++ b/arch/arm/include/asm/arch-tegra/board.h @@ -25,8 +25,7 @@ #define _TEGRA_BOARD_H_ /* Set up pinmux to make UART usable */ -void gpio_config_uart(void); /* CONFIG_SPI_UART_SWITCH */ -void gpio_early_init_uart(void); /*!CONFIG_SPI_UART_SWITCH */ +void gpio_early_init_uart(void); /* Set up early UART output */ void board_init_uart_f(void); diff --git a/arch/arm/include/asm/arch-tegra/tegra_slink.h b/arch/arm/include/asm/arch-tegra/tegra_slink.h deleted file mode 100644 index 74804b5..0000000 --- a/arch/arm/include/asm/arch-tegra/tegra_slink.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * NVIDIA Tegra SPI-SLINK controller - * - * Copyright 2010-2013 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA_SLINK_H_ -#define _TEGRA_SLINK_H_ - -#include <asm/types.h> - -struct slink_tegra { - u32 command; /* SLINK_COMMAND_0 register */ - u32 command2; /* SLINK_COMMAND2_0 reg */ - u32 status; /* SLINK_STATUS_0 register */ - u32 reserved; /* Reserved offset 0C */ - u32 mas_data; /* SLINK_MAS_DATA_0 reg */ - u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */ - u32 dma_ctl; /* SLINK_DMA_CTL_0 register */ - u32 status2; /* SLINK_STATUS2_0 reg */ - u32 rsvd[56]; /* 0x20 to 0xFF reserved */ - u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */ - u32 rsvd2[31]; /* 0x104 to 0x17F reserved */ - u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */ -}; - -/* COMMAND */ -#define SLINK_CMD_ENB (1 << 31) -#define SLINK_CMD_GO (1 << 30) -#define SLINK_CMD_M_S (1 << 28) -#define SLINK_CMD_CK_SDA (1 << 21) -#define SLINK_CMD_CS_POL (1 << 13) -#define SLINK_CMD_CS_VAL (1 << 12) -#define SLINK_CMD_CS_SOFT (1 << 11) -#define SLINK_CMD_BIT_LENGTH (1 << 4) -#define SLINK_CMD_BIT_LENGTH_MASK 0x0000001F -/* COMMAND2 */ -#define SLINK_CMD2_TXEN (1 << 30) -#define SLINK_CMD2_RXEN (1 << 31) -#define SLINK_CMD2_SS_EN (1 << 18) -#define SLINK_CMD2_SS_EN_SHIFT 18 -#define SLINK_CMD2_SS_EN_MASK 0x000C0000 -#define SLINK_CMD2_CS_ACTIVE_BETWEEN (1 << 17) -/* STATUS */ -#define SLINK_STAT_BSY (1 << 31) -#define SLINK_STAT_RDY (1 << 30) -#define SLINK_STAT_ERR (1 << 29) -#define SLINK_STAT_RXF_FLUSH (1 << 27) -#define SLINK_STAT_TXF_FLUSH (1 << 26) -#define SLINK_STAT_RXF_OVF (1 << 25) -#define SLINK_STAT_TXF_UNR (1 << 24) -#define SLINK_STAT_RXF_EMPTY (1 << 23) -#define SLINK_STAT_RXF_FULL (1 << 22) -#define SLINK_STAT_TXF_EMPTY (1 << 21) -#define SLINK_STAT_TXF_FULL (1 << 20) -#define SLINK_STAT_TXF_OVF (1 << 19) -#define SLINK_STAT_RXF_UNR (1 << 18) -#define SLINK_STAT_CUR_BLKCNT (1 << 15) -/* STATUS2 */ -#define SLINK_STAT2_RXF_FULL_CNT (1 << 16) -#define SLINK_STAT2_TXF_FULL_CNT (1 << 0) - -#define SPI_TIMEOUT 1000 -#define TEGRA_SPI_MAX_FREQ 52000000 - -#endif /* _TEGRA_SLINK_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/tegra_spi.h b/arch/arm/include/asm/arch-tegra/tegra_spi.h deleted file mode 100644 index d53a93f..0000000 --- a/arch/arm/include/asm/arch-tegra/tegra_spi.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * NVIDIA Tegra20 SPI-FLASH controller - * - * Copyright 2010-2012 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA_SPI_H_ -#define _TEGRA_SPI_H_ - -#include <asm/types.h> - -struct spi_tegra { - u32 command; /* SPI_COMMAND_0 register */ - u32 status; /* SPI_STATUS_0 register */ - u32 rx_cmp; /* SPI_RX_CMP_0 register */ - u32 dma_ctl; /* SPI_DMA_CTL_0 register */ - u32 tx_fifo; /* SPI_TX_FIFO_0 register */ - u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */ - u32 rx_fifo; /* SPI_RX_FIFO_0 register */ -}; - -#define SPI_CMD_GO (1 << 30) -#define SPI_CMD_ACTIVE_SCLK_SHIFT 26 -#define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT) -#define SPI_CMD_CK_SDA (1 << 21) -#define SPI_CMD_ACTIVE_SDA_SHIFT 18 -#define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT) -#define SPI_CMD_CS_POL (1 << 16) -#define SPI_CMD_TXEN (1 << 15) -#define SPI_CMD_RXEN (1 << 14) -#define SPI_CMD_CS_VAL (1 << 13) -#define SPI_CMD_CS_SOFT (1 << 12) -#define SPI_CMD_CS_DELAY (1 << 9) -#define SPI_CMD_CS3_EN (1 << 8) -#define SPI_CMD_CS2_EN (1 << 7) -#define SPI_CMD_CS1_EN (1 << 6) -#define SPI_CMD_CS0_EN (1 << 5) -#define SPI_CMD_BIT_LENGTH (1 << 4) -#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F - -#define SPI_STAT_BSY (1 << 31) -#define SPI_STAT_RDY (1 << 30) -#define SPI_STAT_RXF_FLUSH (1 << 29) -#define SPI_STAT_TXF_FLUSH (1 << 28) -#define SPI_STAT_RXF_UNR (1 << 27) -#define SPI_STAT_TXF_OVF (1 << 26) -#define SPI_STAT_RXF_EMPTY (1 << 25) -#define SPI_STAT_RXF_FULL (1 << 24) -#define SPI_STAT_TXF_EMPTY (1 << 23) -#define SPI_STAT_TXF_FULL (1 << 22) -#define SPI_STAT_SEL_TXRX_N (1 << 16) -#define SPI_STAT_CUR_BLKCNT (1 << 15) - -#define SPI_TIMEOUT 1000 -#define TEGRA_SPI_MAX_FREQ 52000000 - -#endif /* _TEGRA_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h index 1ef1a14..41ce677 100644 --- a/arch/arm/include/asm/arch-tegra114/gp_padctrl.h +++ b/arch/arm/include/asm/arch-tegra114/gp_padctrl.h @@ -74,4 +74,10 @@ struct apb_misc_gp_ctlr { u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */ }; +/* SDMMC1/3 settings from section 27.5 of T114 TRM */ +#define SDIOCFG_DRVUP_SLWF 0 +#define SDIOCFG_DRVDN_SLWR 0 +#define SDIOCFG_DRVUP 0x24 +#define SDIOCFG_DRVDN 0x14 + #endif /* _TEGRA114_GP_PADCTRL_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h b/arch/arm/include/asm/arch-tegra114/tegra114_spi.h new file mode 100644 index 0000000..48197bc --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/tegra114_spi.h @@ -0,0 +1,41 @@ +/* + * NVIDIA Tegra SPI controller + * + * Copyright 2010-2013 NVIDIA Corporation + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA114_SPI_H_ +#define _TEGRA114_SPI_H_ + +#include <asm/types.h> + +int tegra114_spi_init(int *node_list, int count); +int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs); +struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); +void tegra114_spi_free_slave(struct spi_slave *slave); +int tegra114_spi_claim_bus(struct spi_slave *slave); +void tegra114_spi_cs_activate(struct spi_slave *slave); +void tegra114_spi_cs_deactivate(struct spi_slave *slave); +int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags); + +#endif /* _TEGRA114_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h new file mode 100644 index 0000000..e8cc68c --- /dev/null +++ b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h @@ -0,0 +1,41 @@ +/* + * NVIDIA Tegra20 SPI-FLASH controller + * + * Copyright 2010-2012 NVIDIA Corporation + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA20_SPI_H_ +#define _TEGRA20_SPI_H_ + +#include <asm/types.h> + +int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs); +struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); +void tegra20_spi_free_slave(struct spi_slave *slave); +int tegra20_spi_init(int *node_list, int count); +int tegra20_spi_claim_bus(struct spi_slave *slave); +void tegra20_spi_cs_activate(struct spi_slave *slave); +void tegra20_spi_cs_deactivate(struct spi_slave *slave); +int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags); + +#endif /* _TEGRA20_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h new file mode 100644 index 0000000..5aa74dd --- /dev/null +++ b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h @@ -0,0 +1,41 @@ +/* + * NVIDIA Tegra SPI-SLINK controller + * + * Copyright 2010-2013 NVIDIA Corporation + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA30_SPI_H_ +#define _TEGRA30_SPI_H_ + +#include <asm/types.h> + +int tegra30_spi_init(int *node_list, int count); +int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs); +struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); +void tegra30_spi_free_slave(struct spi_slave *slave); +int tegra30_spi_claim_bus(struct spi_slave *slave); +void tegra30_spi_cs_activate(struct spi_slave *slave); +void tegra30_spi_cs_deactivate(struct spi_slave *slave); +int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags); + +#endif /* _TEGRA30_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/uart-spi-switch.h b/arch/arm/include/asm/arch-tegra20/uart-spi-switch.h deleted file mode 100644 index 82ac180..0000000 --- a/arch/arm/include/asm/arch-tegra20/uart-spi-switch.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _UART_SPI_SWITCH_H -#define _UART_SPI_SWITCH_H - -#if defined(CONFIG_SPI_UART_SWITCH) -/* - * Signal that we are about to use the UART. This unfortunate hack is - * required by Seaboard, which cannot use its console and SPI at the same - * time! If the board file provides this, the board config will declare it. - * Let this be a lesson for others. - */ -void pinmux_select_uart(void); - -/* - * Signal that we are about the use the SPI bus. - */ -void pinmux_select_spi(void); - -#else /* not CONFIG_SPI_UART_SWITCH */ - -static inline void pinmux_select_uart(void) {} -static inline void pinmux_select_spi(void) {} - -#endif - -#endif diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index eef6a5a..8153484 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -41,7 +41,9 @@ static inline void invalidate_l2_cache(void) void l2_cache_enable(void); void l2_cache_disable(void); +void set_section_dcache(int section, enum dcache_option option); +void dram_bank_mmu_setup(int bank); /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We * use that value for aligning DMA buffers unless the board config has specified diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index c5d1e6c..5f11d7b 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -1165,7 +1165,6 @@ void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs); #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS extern u32 *const T_num; extern u32 *const T_den; -extern u32 *const emif_sizes; #endif void config_data_eye_leveling_samples(u32 emif_base); diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index a676b6d..440b041 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -223,7 +223,6 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_MIOA701 1257 #define MACH_TYPE_ARMADILLO5X0 1260 #define MACH_TYPE_CC9P9360JS 1264 -#define MACH_TYPE_SMDK6400 1270 #define MACH_TYPE_NOKIA_N800 1271 #define MACH_TYPE_EP80219 1281 #define MACH_TYPE_GORAMO_MLR 1292 @@ -3640,18 +3639,6 @@ extern unsigned int __machine_arch_type; # define machine_is_cc9p9360js() (0) #endif -#ifdef CONFIG_MACH_SMDK6400 -# ifdef machine_arch_type -# undef machine_arch_type -# define machine_arch_type __machine_arch_type -# else -# define machine_arch_type MACH_TYPE_SMDK6400 -# endif -# define machine_is_smdk6400() (machine_arch_type == MACH_TYPE_SMDK6400) -#else -# define machine_is_smdk6400() (0) -#endif - #ifdef CONFIG_MACH_NOKIA_N800 # ifdef machine_arch_type # undef machine_arch_type diff --git a/arch/arm/include/asm/omap_gpmc.h b/arch/arm/include/asm/omap_gpmc.h new file mode 100644 index 0000000..5cb1df1 --- /dev/null +++ b/arch/arm/include/asm/omap_gpmc.h @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com> + * Rohit Choraria <rohitkc@ti.com> + * + * (C) Copyright 2013 Andreas Bießmann <andreas.devel@googlemail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_OMAP_GPMC_H +#define __ASM_OMAP_GPMC_H + +#include <asm/arch/omap_gpmc.h> + +#define GPMC_BUF_EMPTY 0 +#define GPMC_BUF_FULL 1 + +#define ECCCLEAR (0x1 << 8) +#define ECCRESULTREG1 (0x1 << 0) +#define ECCSIZE512BYTE 0xFF +#define ECCSIZE1 (ECCSIZE512BYTE << 22) +#define ECCSIZE0 (ECCSIZE512BYTE << 12) +#define ECCSIZE0SEL (0x000 << 0) + +/* Generic ECC Layouts */ +/* Large Page x8 NAND device Layout */ +#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT {\ + .eccbytes = 12,\ + .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\ + 9, 10, 11, 12},\ + .oobfree = {\ + {.offset = 13,\ + .length = 51 } } \ +} +#endif + +/* Large Page x16 NAND device Layout */ +#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT {\ + .eccbytes = 12,\ + .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13},\ + .oobfree = {\ + {.offset = 14,\ + .length = 50 } } \ +} +#endif + +/* Small Page x8 NAND device Layout */ +#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT {\ + .eccbytes = 3,\ + .eccpos = {1, 2, 3},\ + .oobfree = {\ + {.offset = 4,\ + .length = 12 } } \ +} +#endif + +/* Small Page x16 NAND device Layout */ +#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT {\ + .eccbytes = 3,\ + .eccpos = {2, 3, 4},\ + .oobfree = {\ + {.offset = 5,\ + .length = 11 } } \ +} +#endif + +#endif /* __ASM_OMAP_GPMC_H */ diff --git a/board/pcippc2/i2c.h b/arch/arm/include/asm/sections.h index 1224b42..c042cb6 100644 --- a/board/pcippc2/i2c.h +++ b/arch/arm/include/asm/sections.h @@ -1,7 +1,5 @@ /* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * + * Copyright (c) 2012 The Chromium OS Authors. * See file CREDITS for list of people who contributed to this * project. * @@ -12,7 +10,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -21,16 +19,9 @@ * MA 02111-1307 USA */ -#ifndef _I2C_H_ -#define _I2C_H_ - -#include <common.h> - -extern int i2c_read_byte (u8 * data, - u8 dev, - u8 offset); - -extern unsigned int i2c_reset (void); +#ifndef __ASM_ARM_SECTIONS_H +#define __ASM_ARM_SECTIONS_H +#include <asm-generic/sections.h> #endif diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 62011aa..2b7218e 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -27,7 +27,7 @@ #include <asm/arch/spl.h> /* Linker symbols. */ -extern char __bss_start[], __bss_end__[]; +extern char __bss_start[], __bss_end[]; extern gd_t gdata; diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 1918492..760345f 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -81,6 +81,20 @@ static inline void set_cr(unsigned int val) isb(); } +static inline unsigned int get_dacr(void) +{ + unsigned int val; + asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); + return val; +} + +static inline void set_dacr(unsigned int val) +{ + asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" + : : "r" (val) : "cc"); + isb(); +} + /* options available for data cache on each page */ enum dcache_option { DCACHE_OFF = 0x12, diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index 9f3cae5..f16861a 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -30,12 +30,8 @@ #define _U_BOOT_ARM_H_ 1 /* for the following variables, see start.S */ -extern ulong _bss_start_ofs; /* BSS start relative to _start */ -extern ulong _bss_end_ofs; /* BSS end relative to _start */ -extern ulong _end_ofs; /* end of image relative to _start */ extern ulong IRQ_STACK_START; /* top of IRQ stack */ extern ulong FIQ_STACK_START; /* top of FIQ stack */ -extern ulong _TEXT_BASE; /* code start */ extern ulong _datarel_start_ofs; extern ulong _datarelrolocal_start_ofs; extern ulong _datarellocal_start_ofs; diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h index 2ba98bc..a33fefa 100644 --- a/arch/arm/include/asm/u-boot.h +++ b/arch/arm/include/asm/u-boot.h @@ -36,6 +36,12 @@ #ifndef _U_BOOT_H_ #define _U_BOOT_H_ 1 +#ifdef CONFIG_SYS_GENERIC_BOARD +/* Use the generic board which requires a unified bd_info */ +#include <asm-generic/u-boot.h> +#else + +#ifndef __ASSEMBLY__ typedef struct bd_info { unsigned int bi_baudrate; /* serial console baudrate */ ulong bi_arch_number; /* unique id for this board */ @@ -49,6 +55,9 @@ typedef struct bd_info { ulong size; } bi_dram[CONFIG_NR_DRAM_BANKS]; } bd_t; +#endif + +#endif /* !CONFIG_SYS_GENERIC_BOARD */ /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_ARM diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 11c2674..6ae161a 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -39,8 +39,11 @@ GLCOBJS += div0.o SOBJS-y += crt0.o ifndef CONFIG_SPL_BUILD -COBJS-y += bss.o +ifndef CONFIG_SYS_GENERIC_BOARD COBJS-y += board.o +endif +COBJS-y += bss.o + COBJS-y += bootm.o COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 162e2cc..0521178 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -53,6 +53,7 @@ #include <fdtdec.h> #include <post.h> #include <logbuff.h> +#include <asm/sections.h> #ifdef CONFIG_BITBANGMII #include <miiphy.h> diff --git a/arch/arm/lib/bss.c b/arch/arm/lib/bss.c index 7c0b154..99eda59 100644 --- a/arch/arm/lib/bss.c +++ b/arch/arm/lib/bss.c @@ -36,4 +36,4 @@ */ char __bss_start[0] __attribute__((used, section(".__bss_start"))); -char __bss_end__[0] __attribute__((used, section(".__bss_end__"))); +char __bss_end[0] __attribute__((used, section(".__bss_end"))); diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index b6e5e95..4abe1cf 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -23,6 +23,8 @@ #include <common.h> #include <asm/system.h> +#include <asm/cache.h> +#include <linux/compiler.h> #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) @@ -34,6 +36,10 @@ void __arm_init_before_mmu(void) void arm_init_before_mmu(void) __attribute__((weak, alias("__arm_init_before_mmu"))); +__weak void arm_init_domains(void) +{ +} + static void cp_delay (void) { volatile int i; @@ -77,7 +83,7 @@ void mmu_set_region_dcache_behaviour(u32 start, int size, mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); } -static inline void dram_bank_mmu_setup(int bank) +__weak void dram_bank_mmu_setup(int bank) { bd_t *bd = gd->bd; int i; @@ -115,6 +121,9 @@ static inline void mmu_setup(void) /* Set the access control to all-supervisor */ asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (~0)); + + arm_init_domains(); + /* and enable the mmu */ reg = get_cr(); /* get control reg. */ cp_delay(); diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 4f60958..a9657d1 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -24,6 +24,7 @@ #include <config.h> #include <asm-offsets.h> +#include <linux/linkage.h> /* * This file handles the target-independent stages of the U-Boot @@ -63,46 +64,20 @@ * have some work left to do at this point regarding memory, so * call c_runtime_cpu_setup. * - * 6. Branch to either nand_boot() or board_init_r(). + * 6. Branch to board_init_r(). */ /* - * declare nand_boot() or board_init_r() to jump to at end of crt0 - */ - -#if defined(CONFIG_NAND_SPL) - -.globl nand_boot - -#elif ! defined(CONFIG_SPL_BUILD) - -.globl board_init_r - -#endif - -/* - * start and end of BSS - */ - -.globl __bss_start -.globl __bss_end__ - -/* * entry point of crt0 sequence */ -.global _main - -_main: +ENTRY(_main) /* * Set up initial C runtime environment and call board_init_f(0). */ -#if defined(CONFIG_NAND_SPL) - /* deprecated, use instead CONFIG_SPL_BUILD */ - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) -#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr sp, =(CONFIG_SPL_STACK) #else ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) @@ -118,8 +93,8 @@ _main: /* * Set up intermediate environment (new sp and gd) and call - * relocate_code(addr_sp, gd, addr_moni). Trick here is that - * we'll return 'here' but relocated. + * relocate_code(addr_moni). Trick here is that we'll return + * 'here' but relocated. */ ldr sp, [r8, #GD_START_ADDR_SP] /* r8 = gd->start_addr_sp */ @@ -130,9 +105,7 @@ _main: adr lr, here ldr r0, [r8, #GD_RELOC_OFF] /* lr = gd->start_addr_sp */ add lr, lr, r0 - ldr r0, [r8, #GD_START_ADDR_SP] /* r0 = gd->start_addr_sp */ - mov r1, r8 /* r1 = gd */ - ldr r2, [r8, #GD_RELOCADDR] /* r2 = gd->relocaddr */ + ldr r0, [r8, #GD_RELOCADDR] /* r0 = gd->relocaddr */ b relocate_code here: @@ -141,7 +114,7 @@ here: bl c_runtime_cpu_setup /* we still call old routine here */ ldr r0, =__bss_start /* this is auto-relocated! */ - ldr r1, =__bss_end__ /* this is auto-relocated! */ + ldr r1, =__bss_end /* this is auto-relocated! */ mov r2, #0x00000000 /* prepare zero to clear BSS */ @@ -153,21 +126,14 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */ bl coloured_LED_init bl red_led_on -#if defined(CONFIG_NAND_SPL) - - /* call _nand_boot() */ - ldr pc, =nand_boot - -#else - /* call board_init_r(gd_t *id, ulong dest_addr) */ mov r0, r8 /* gd_t */ ldr r1, [r8, #GD_RELOCADDR] /* dest_addr */ /* call board_init_r */ ldr pc, =board_init_r /* this is auto-relocated! */ -#endif - /* we should not return here. */ #endif + +ENDPROC(_main) diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index f568f61..301f082 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -45,7 +45,7 @@ void __weak board_init_f(ulong dummy) asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK)); /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end__ - __bss_start); + memset(__bss_start, 0, __bss_end - __bss_start); /* Set global data pointer. */ gd = &gdata; diff --git a/arch/avr32/cpu/start.S b/arch/avr32/cpu/start.S index 71cbc52..c8decea 100644 --- a/arch/avr32/cpu/start.S +++ b/arch/avr32/cpu/start.S @@ -244,7 +244,7 @@ relocate_code: /* zero out .bss */ mov r0, 0 mov r1, 0 - lda.w r9, __bss_end__ + lda.w r9, __bss_end sub r9, r8 1: st.d r10++, r0 sub r9, 8 diff --git a/arch/avr32/cpu/u-boot.lds b/arch/avr32/cpu/u-boot.lds index 4a3fc2a..4e4a436 100644 --- a/arch/avr32/cpu/u-boot.lds +++ b/arch/avr32/cpu/u-boot.lds @@ -68,5 +68,5 @@ SECTIONS *(.bss.*) } . = ALIGN(8); - __bss_end__ = .; + __bss_end = .; } diff --git a/arch/avr32/include/asm/sections.h b/arch/avr32/include/asm/sections.h index 3f15788..056d7a0 100644 --- a/arch/avr32/include/asm/sections.h +++ b/arch/avr32/include/asm/sections.h @@ -22,11 +22,11 @@ #ifndef __ASM_AVR32_SECTIONS_H #define __ASM_AVR32_SECTIONS_H +#include <asm-generic/sections.h> + /* References to section boundaries */ -extern char _text[], _etext[]; -extern char _data[], __data_lma[], _edata[], __edata_lma[]; +extern char __data_lma[], __edata_lma[]; extern char __got_start[], __got_lma[], __got_end[]; -extern char __bss_end__[]; #endif /* __ASM_AVR32_SECTIONS_H */ diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index bd1be73..57e07df 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -116,7 +116,7 @@ static int display_banner (void) printf ("\n\n%s\n\n", version_string); printf ("U-Boot code: %08lx -> %08lx data: %08lx -> %08lx\n", (unsigned long)_text, (unsigned long)_etext, - (unsigned long)_data, (unsigned long)__bss_end__); + (unsigned long)_data, (unsigned long)__bss_end); return 0; } @@ -188,7 +188,7 @@ void board_init_f(ulong board_type) * - stack */ addr = CONFIG_SYS_SDRAM_BASE + sdram_size; - monitor_len = __bss_end__ - _text; + monitor_len = (char *)__bss_end - _text; /* * Reserve memory for u-boot code, data and bss. @@ -211,11 +211,11 @@ void board_init_f(ulong board_type) #ifdef CONFIG_FB_ADDR printf("LCD: Frame buffer allocated at preset 0x%08x\n", CONFIG_FB_ADDR); - gd->fb_base = (void *)CONFIG_FB_ADDR; + gd->fb_base = CONFIG_FB_ADDR; #else addr = lcd_setmem(addr); printf("LCD: Frame buffer allocated at 0x%08lx\n", addr); - gd->fb_base = (void *)addr; + gd->fb_base = addr; #endif /* CONFIG_FB_ADDR */ #endif /* CONFIG_LCD */ diff --git a/arch/blackfin/cpu/cpu.c b/arch/blackfin/cpu/cpu.c index b9fdb07..0be2e2b 100644 --- a/arch/blackfin/cpu/cpu.c +++ b/arch/blackfin/cpu/cpu.c @@ -23,7 +23,6 @@ ulong bfin_poweron_retx; -__attribute__ ((__noreturn__)) void cpu_init_f(ulong bootflag, ulong loaded_from_ldr) { #ifndef CONFIG_BFIN_BOOTROM_USES_EVT1 diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h index c2c4d4d..44245b4 100644 --- a/arch/blackfin/include/asm/global_data.h +++ b/arch/blackfin/include/asm/global_data.h @@ -32,6 +32,7 @@ /* Architecture-specific global data */ struct arch_global_data { + unsigned long board_type; }; #include <asm-generic/global_data.h> diff --git a/arch/blackfin/include/asm/posix_types.h b/arch/blackfin/include/asm/posix_types.h index 000ffe5..1f28b36 100644 --- a/arch/blackfin/include/asm/posix_types.h +++ b/arch/blackfin/include/asm/posix_types.h @@ -61,9 +61,6 @@ typedef unsigned int __kernel_gid32_t; typedef unsigned short __kernel_old_uid_t; typedef unsigned short __kernel_old_gid_t; -#define BOOL_WAS_DEFINED -typedef enum { false = 0, true = 1 } bool; - #ifdef __GNUC__ typedef long long __kernel_loff_t; #endif diff --git a/board/pcippc2/fpga_serial.h b/arch/blackfin/include/asm/sections.h index 106fbf7..85af42c 100644 --- a/board/pcippc2/fpga_serial.h +++ b/arch/blackfin/include/asm/sections.h @@ -1,7 +1,5 @@ /* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * + * Copyright (c) 2012 The Chromium OS Authors. * See file CREDITS for list of people who contributed to this * project. * @@ -12,7 +10,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -21,13 +19,9 @@ * MA 02111-1307 USA */ -#ifndef _FPGA_SERIAL_H_ -#define _FPGA_SERIAL_H_ +#ifndef __ASM_BLACKFIN_SECTIONS_H +#define __ASM_BLACKFIN_SECTIONS_H -extern void fpga_serial_init (int); -extern void fpga_serial_putc (char); -extern int fpga_serial_getc (void); -extern int fpga_serial_tstc (void); -extern void fpga_serial_setbrg (void); +#include <asm-generic/sections.h> #endif diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 288dc82..75b6c46 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -77,7 +77,7 @@ static void display_global_data(void) bd = gd->bd; printf(" gd: %p\n", gd); printf(" |-flags: %lx\n", gd->flags); - printf(" |-board_type: %lx\n", gd->board_type); + printf(" |-board_type: %lx\n", gd->arch.board_type); printf(" |-baudrate: %u\n", gd->baudrate); printf(" |-have_console: %lx\n", gd->have_console); printf(" |-ram_size: %lx\n", gd->ram_size); diff --git a/arch/m68k/include/asm/sections.h b/arch/m68k/include/asm/sections.h new file mode 100644 index 0000000..9228987 --- /dev/null +++ b/arch/m68k/include/asm/sections.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_M68K_SECTIONS_H +#define __ASM_M68K_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index 33acffe..adaccfe 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -77,9 +77,10 @@ static char *failed = "*** failed ***\n"; #include <environment.h> extern ulong __init_end; -extern ulong __bss_end__; +extern ulong __bss_end; #if defined(CONFIG_WATCHDOG) +# undef INIT_FUNC_WATCHDOG_INIT # define INIT_FUNC_WATCHDOG_INIT watchdog_init, # define WATCHDOG_DISABLE watchdog_disable @@ -244,7 +245,7 @@ board_init_f (ulong bootflag) * - monitor code * - board info struct */ - len = (ulong)&__bss_end__ - CONFIG_SYS_MONITOR_BASE; + len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size; diff --git a/arch/m68k/lib/interrupts.c b/arch/m68k/lib/interrupts.c index 133494f..9751db4 100644 --- a/arch/m68k/lib/interrupts.c +++ b/arch/m68k/lib/interrupts.c @@ -96,7 +96,7 @@ int disable_interrupts (void) sr = get_sr (); set_sr (sr | 0x0700); - return ((sr & 0x0700) == 0); /* return TRUE, if interrupts were enabled before */ + return ((sr & 0x0700) == 0); /* return true, if interrupts were enabled before */ } void int_handler (struct pt_regs *fp) diff --git a/arch/microblaze/include/asm/sections.h b/arch/microblaze/include/asm/sections.h new file mode 100644 index 0000000..156c149 --- /dev/null +++ b/arch/microblaze/include/asm/sections.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_MICROBLAZE_SECTIONS_H +#define __ASM_MICROBLAZE_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif diff --git a/arch/mips/include/asm/sections.h b/arch/mips/include/asm/sections.h new file mode 100644 index 0000000..54cd8b3 --- /dev/null +++ b/arch/mips/include/asm/sections.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_MIPS_SECTIONS_H +#define __ASM_MIPS_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h index a483166..e77636e 100644 --- a/arch/mips/include/asm/u-boot-mips.h +++ b/arch/mips/include/asm/u-boot-mips.h @@ -7,7 +7,7 @@ static inline unsigned long bss_start(void) { - extern ulong __bss_start; + extern char __bss_start[]; return (unsigned long) &__bss_start; } @@ -19,7 +19,7 @@ static inline unsigned long bss_end(void) static inline unsigned long image_copy_end(void) { - extern ulong __image_copy_end; + extern char __image_copy_end[]; return (unsigned long) &__image_copy_end; } diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S index 889bf8b..558fd0e 100644 --- a/arch/nds32/cpu/n1213/start.S +++ b/arch/nds32/cpu/n1213/start.S @@ -240,7 +240,7 @@ fix_got_loop: clear_bss: la $r0, __bss_start /* r0 <- rel __bss_start in FLASH */ add $r0, $r0, $r9 /* r0 <- rel __bss_start in FLASH */ - la $r1, __bss_end__ /* r1 <- rel __bss_end in RAM */ + la $r1, __bss_end /* r1 <- rel __bss_end in RAM */ add $r1, $r1, $r9 /* r0 <- rel __bss_end in RAM */ li $r2, 0x00000000 /* clear */ diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds index 5790948..e9fbcd3 100644 --- a/arch/nds32/cpu/n1213/u-boot.lds +++ b/arch/nds32/cpu/n1213/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS __bss_start = .; *(.bss) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } } diff --git a/arch/nds32/include/asm/sections.h b/arch/nds32/include/asm/sections.h new file mode 100644 index 0000000..a65735e --- /dev/null +++ b/arch/nds32/include/asm/sections.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_NDS32_SECTIONS_H +#define __ASM_NDS32_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif diff --git a/arch/nds32/include/asm/u-boot-nds32.h b/arch/nds32/include/asm/u-boot-nds32.h index ae1918d..f3c7b27 100644 --- a/arch/nds32/include/asm/u-boot-nds32.h +++ b/arch/nds32/include/asm/u-boot-nds32.h @@ -30,10 +30,10 @@ #define _U_BOOT_NDS32_H_ 1 /* for the following variables, see start.S */ -extern ulong __bss_start; /* BSS start relative to _start */ -extern ulong __bss_end__; /* BSS end relative to _start */ -extern ulong _end; /* end of image relative to _start */ -extern ulong _start; /* start of image relative to _start */ +extern char __bss_start[]; /* BSS start relative to _start */ +extern ulong __bss_end; /* BSS end relative to _start */ +extern char _end[]; /* end of image relative to _start */ +extern void _start(void); /* start of image relative to _start */ extern ulong _TEXT_BASE; /* code start */ extern ulong IRQ_STACK_START; /* top of IRQ stack */ extern ulong FIQ_STACK_START; /* top of FIQ stack */ diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c index c919928..a7d27fc 100644 --- a/arch/nds32/lib/board.c +++ b/arch/nds32/lib/board.c @@ -192,7 +192,7 @@ void board_init_f(ulong bootflag) memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE); - gd->mon_len = (unsigned int)(&__bss_end__) - (unsigned int)(&_start); + gd->mon_len = (unsigned int)(&__bss_end) - (unsigned int)(&_start); for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr)() != 0) diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c index ca8c227..b4d0adc 100644 --- a/arch/nds32/lib/interrupts.c +++ b/arch/nds32/lib/interrupts.c @@ -59,7 +59,7 @@ void enable_interrupts(void) /* * disable interrupts - * Return TRUE if GIE is enabled before we disable it. + * Return true if GIE is enabled before we disable it. */ int disable_interrupts(void) { diff --git a/arch/nios2/cpu/start.S b/arch/nios2/cpu/start.S index 0f4ab28..1787b65 100644 --- a/arch/nios2/cpu/start.S +++ b/arch/nios2/cpu/start.S @@ -99,12 +99,12 @@ _cur: movhi r5, %hi(_cur - _start) 3: /* ZERO BSS/SBSS -- bss and sbss are assumed to be adjacent - * and between __bss_start and __bss_end__. + * and between __bss_start and __bss_end. */ movhi r5, %hi(__bss_start) ori r5, r5, %lo(__bss_start) - movhi r6, %hi(__bss_end__) - ori r6, r6, %lo(__bss_end__) + movhi r6, %hi(__bss_end) + ori r6, r6, %lo(__bss_end) beq r5, r6, 5f 4: stwio r0, 0(r5) diff --git a/arch/nios2/cpu/u-boot.lds b/arch/nios2/cpu/u-boot.lds index f937396..4c45336 100644 --- a/arch/nios2/cpu/u-boot.lds +++ b/arch/nios2/cpu/u-boot.lds @@ -101,7 +101,7 @@ SECTIONS *(.scommon) } . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; PROVIDE (end = .); /* DEBUG -- symbol table, string table, etc. etc. diff --git a/arch/nios2/include/asm/sections.h b/arch/nios2/include/asm/sections.h new file mode 100644 index 0000000..d813563 --- /dev/null +++ b/arch/nios2/include/asm/sections.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_NIOS2_SECTIONS_H +#define __ASM_NIOS2_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif diff --git a/arch/openrisc/include/asm/sections.h b/arch/openrisc/include/asm/sections.h new file mode 100644 index 0000000..6eb5a66 --- /dev/null +++ b/arch/openrisc/include/asm/sections.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_OPENRISC_SECTIONS_H +#define __ASM_OPENRISC_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index b706281..e32d2bf 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -29,6 +29,9 @@ PLATFORM_RELFLAGS += -fpic -mrelocatable -ffunction-sections -fdata-sections PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ PLATFORM_LDFLAGS += -n +# Support generic board on PPC +__HAVE_ARCH_GENERIC_BOARD := y + # # When cross-compiling on NetBSD, we have to define __PPC__ or else we # will pick up a va_list declaration that is incompatible with the diff --git a/arch/powerpc/cpu/74xx_7xx/cpu.c b/arch/powerpc/cpu/74xx_7xx/cpu.c index b6a31b4..17694a1 100644 --- a/arch/powerpc/cpu/74xx_7xx/cpu.c +++ b/arch/powerpc/cpu/74xx_7xx/cpu.c @@ -229,8 +229,7 @@ soft_restart(unsigned long addr) } -#if !defined(CONFIG_PCIPPC2) && \ - !defined(CONFIG_BAB7xx) && \ +#if !defined(CONFIG_BAB7xx) && \ !defined(CONFIG_ELPPC) && \ !defined(CONFIG_PPMC7XX) /* no generic way to do board reset. simply call soft_reset. */ @@ -288,13 +287,13 @@ unsigned long get_tbclk(void) /* ------------------------------------------------------------------------- */ #if defined(CONFIG_WATCHDOG) -#if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx) +#if !defined(CONFIG_BAB7xx) void watchdog_reset(void) { } -#endif /* !CONFIG_PCIPPC2 && !CONFIG_BAB7xx */ +#endif /* !CONFIG_BAB7xx */ #endif /* CONFIG_WATCHDOG */ /* ------------------------------------------------------------------------- */ diff --git a/arch/powerpc/cpu/74xx_7xx/start.S b/arch/powerpc/cpu/74xx_7xx/start.S index 75fb773..cd8dea8 100644 --- a/arch/powerpc/cpu/74xx_7xx/start.S +++ b/arch/powerpc/cpu/74xx_7xx/start.S @@ -72,7 +72,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT @@ -715,7 +715,7 @@ in_ram: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/74xx_7xx/u-boot.lds b/arch/powerpc/cpu/74xx_7xx/u-boot.lds index c58d979..40b89ab 100644 --- a/arch/powerpc/cpu/74xx_7xx/u-boot.lds +++ b/arch/powerpc/cpu/74xx_7xx/u-boot.lds @@ -89,6 +89,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc512x/cpu_init.c b/arch/powerpc/cpu/mpc512x/cpu_init.c index 32ade1b..b308cb4 100644 --- a/arch/powerpc/cpu/mpc512x/cpu_init.c +++ b/arch/powerpc/cpu/mpc512x/cpu_init.c @@ -26,6 +26,7 @@ #include <common.h> #include <asm/io.h> +#include <asm/mpc512x.h> #include <asm/processor.h> DECLARE_GLOBAL_DATA_PTR; @@ -43,6 +44,101 @@ void cpu_init_f (volatile immap_t * im) /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); + /* Local Window and chip select configuration */ +#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE) + out_be32(&im->sysconf.lpcs0aw, + CSAW_START(CONFIG_SYS_CS0_START) | + CSAW_STOP(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE)); + sync_law(&im->sysconf.lpcs0aw); +#endif +#if defined(CONFIG_SYS_CS0_CFG) + out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); +#endif + +#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE) + out_be32(&im->sysconf.lpcs1aw, + CSAW_START(CONFIG_SYS_CS1_START) | + CSAW_STOP(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE)); + sync_law(&im->sysconf.lpcs1aw); +#endif +#if defined(CONFIG_SYS_CS1_CFG) + out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG); +#endif + +#if defined(CONFIG_SYS_CS2_START) && (defined CONFIG_SYS_CS2_SIZE) + out_be32(&im->sysconf.lpcs2aw, + CSAW_START(CONFIG_SYS_CS2_START) | + CSAW_STOP(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE)); + sync_law(&im->sysconf.lpcs2aw); +#endif +#if defined(CONFIG_SYS_CS2_CFG) + out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); +#endif + +#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE) + out_be32(&im->sysconf.lpcs3aw, + CSAW_START(CONFIG_SYS_CS3_START) | + CSAW_STOP(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE)); + sync_law(&im->sysconf.lpcs3aw); +#endif +#if defined(CONFIG_SYS_CS3_CFG) + out_be32(&im->lpc.cs_cfg[3], CONFIG_SYS_CS3_CFG); +#endif + +#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE) + out_be32(&im->sysconf.lpcs4aw, + CSAW_START(CONFIG_SYS_CS4_START) | + CSAW_STOP(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE)); + sync_law(&im->sysconf.lpcs4aw); +#endif +#if defined(CONFIG_SYS_CS4_CFG) + out_be32(&im->lpc.cs_cfg[4], CONFIG_SYS_CS4_CFG); +#endif + +#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE) + out_be32(&im->sysconf.lpcs5aw, + CSAW_START(CONFIG_SYS_CS5_START) | + CSAW_STOP(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE)); + sync_law(&im->sysconf.lpcs5aw); +#endif +#if defined(CONFIG_SYS_CS5_CFG) + out_be32(&im->lpc.cs_cfg[5], CONFIG_SYS_CS5_CFG); +#endif + +#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE) + out_be32(&im->sysconf.lpcs6aw, + CSAW_START(CONFIG_SYS_CS6_START) | + CSAW_STOP(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE)); + sync_law(&im->sysconf.lpcs6aw); +#endif +#if defined(CONFIG_SYS_CS6_CFG) + out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG); +#endif + +#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE) + out_be32(&im->sysconf.lpcs7aw, + CSAW_START(CONFIG_SYS_CS7_START) | + CSAW_STOP(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE)); + sync_law(&im->sysconf.lpcs7aw); +#endif +#if defined(CONFIG_SYS_CS7_CFG) + out_be32(&im->lpc.cs_cfg[7], CONFIG_SYS_CS7_CFG); +#endif + +#if defined CONFIG_SYS_CS_ALETIMING + if (SVR_MJREV(in_be32(&im->sysconf.spridr)) >= 2) + out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); +#endif +#if defined CONFIG_SYS_CS_BURST + out_be32(&im->lpc.cs_bcr, CONFIG_SYS_CS_BURST); +#endif +#if defined CONFIG_SYS_CS_DEADCYCLE + out_be32(&im->lpc.cs_dccr, CONFIG_SYS_CS_DEADCYCLE); +#endif +#if defined CONFIG_SYS_CS_HOLDCYCLE + out_be32(&im->lpc.cs_hccr, CONFIG_SYS_CS_HOLDCYCLE); +#endif + /* system performance tweaking */ #ifdef CONFIG_SYS_ACR_PIPE_DEP @@ -76,6 +172,21 @@ void cpu_init_f (volatile immap_t * im) ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT; out_be32(&im->clk.scfr[0], ips_div); +#ifdef SCFR1_LPC_DIV + clrsetbits_be32(&im->clk.scfr[0], SCFR1_LPC_DIV_MASK, + SCFR1_LPC_DIV << SCFR1_LPC_DIV_SHIFT); +#endif + +#ifdef SCFR1_NFC_DIV + clrsetbits_be32(&im->clk.scfr[0], SCFR1_NFC_DIV_MASK, + SCFR1_NFC_DIV << SCFR1_NFC_DIV_SHIFT); +#endif + +#ifdef SCFR1_DIU_DIV + clrsetbits_be32(&im->clk.scfr[0], SCFR1_DIU_DIV_MASK, + SCFR1_DIU_DIV << SCFR1_DIU_DIV_SHIFT); +#endif + /* * Enable Time Base/Decrementer * @@ -84,6 +195,15 @@ void cpu_init_f (volatile immap_t * im) * during FLASH chip identification etc. */ setbits_be32(&im->sysconf.spcr, SPCR_TBEN); + + /* + * Enable clocks + */ + out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN); + out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN); +#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) + setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); +#endif } int cpu_init_r (void) diff --git a/arch/powerpc/cpu/mpc512x/fixed_sdram.c b/arch/powerpc/cpu/mpc512x/fixed_sdram.c index 550cbd0..6635fb0 100644 --- a/arch/powerpc/cpu/mpc512x/fixed_sdram.c +++ b/arch/powerpc/cpu/mpc512x/fixed_sdram.c @@ -99,7 +99,19 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config, sync_law(&im->sysconf.ddrlaw.ar); /* DDR Enable */ - out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN); + /* + * the "enable" combination: DRAM controller out of reset, + * clock enabled, command mode -- BUT leave CKE low for now + */ + i = MDDRC_SYS_CFG_EN & ~MDDRC_SYS_CFG_CKE_MASK; + out_be32(&im->mddrc.ddr_sys_config, i); + /* maintain 200 microseconds of stable power and clock */ + udelay(200); + /* apply a NOP, it shouldn't harm */ + out_be32(&im->mddrc.ddr_command, CONFIG_SYS_DDRCMD_NOP); + /* now assert CKE (high) */ + i |= MDDRC_SYS_CFG_CKE_MASK; + out_be32(&im->mddrc.ddr_sys_config, i); /* Initialize DDR Priority Manager */ out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1); @@ -148,6 +160,9 @@ long int fixed_sdram(ddr512x_config_t *mddrc_config, out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0); out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config); + /* Allow for the DLL to startup before accessing data */ + udelay(10); + msize = get_ram_size(CONFIG_SYS_DDR_BASE, CONFIG_SYS_MAX_RAM_SIZE); /* Fix DDR Local Window for new size */ out_be32(&im->sysconf.ddrlaw.ar, __ilog2(msize) - 1); diff --git a/arch/powerpc/cpu/mpc512x/iopin.c b/arch/powerpc/cpu/mpc512x/iopin.c index be20947..1a39101 100644 --- a/arch/powerpc/cpu/mpc512x/iopin.c +++ b/arch/powerpc/cpu/mpc512x/iopin.c @@ -47,3 +47,57 @@ void iopin_initialize(iopin_t *ioregs_init, int len) } return; } + +void iopin_initialize_bits(iopin_t *ioregs_init, int len) +{ + short i, j, p; + u32 *reg, mask; + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + + reg = (u32 *)&(im->io_ctrl); + + /* iterate over table entries */ + for (i = 0; i < len; i++) { + /* iterate over pins within a table entry */ + for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long); + p < ioregs_init[i].nr_pins; p++, j++) { + if (ioregs_init[i].bit_or & IO_PIN_OVER_EACH) { + /* replace all settings at once */ + out_be32(reg + j, ioregs_init[i].val); + } else { + /* + * only replace individual parts, but + * REPLACE them instead of just ORing + * them in and "inheriting" previously + * set bits which we don't want + */ + mask = 0; + if (ioregs_init[i].bit_or & IO_PIN_OVER_FMUX) + mask |= IO_PIN_FMUX(3); + + if (ioregs_init[i].bit_or & IO_PIN_OVER_HOLD) + mask |= IO_PIN_HOLD(3); + + if (ioregs_init[i].bit_or & IO_PIN_OVER_PULL) + mask |= IO_PIN_PUD(1) | IO_PIN_PUE(1); + + if (ioregs_init[i].bit_or & IO_PIN_OVER_STRIG) + mask |= IO_PIN_ST(1); + + if (ioregs_init[i].bit_or & IO_PIN_OVER_DRVSTR) + mask |= IO_PIN_DS(3); + /* + * DON'T do the "mask, then insert" + * in place on the register, it may + * break access to external hardware + * (like boot ROMs) when configuring + * LPB related pins, while the code to + * configure the pin is read from this + * very address region + */ + clrsetbits_be32(reg + j, mask, + ioregs_init[i].val & mask); + } + } + } +} diff --git a/arch/powerpc/cpu/mpc512x/start.S b/arch/powerpc/cpu/mpc512x/start.S index ed362d8..6d1a99a 100644 --- a/arch/powerpc/cpu/mpc512x/start.S +++ b/arch/powerpc/cpu/mpc512x/start.S @@ -77,7 +77,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT @@ -622,7 +622,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc512x/u-boot.lds b/arch/powerpc/cpu/mpc512x/u-boot.lds index a34501b..0d86979 100644 --- a/arch/powerpc/cpu/mpc512x/u-boot.lds +++ b/arch/powerpc/cpu/mpc512x/u-boot.lds @@ -84,7 +84,7 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } ENTRY(_start) diff --git a/arch/powerpc/cpu/mpc5xx/start.S b/arch/powerpc/cpu/mpc5xx/start.S index cc4c33e..1b275c6 100644 --- a/arch/powerpc/cpu/mpc5xx/start.S +++ b/arch/powerpc/cpu/mpc5xx/start.S @@ -65,7 +65,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT @@ -459,7 +459,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc5xx/u-boot.lds b/arch/powerpc/cpu/mpc5xx/u-boot.lds index 0d87c8c..8385a29 100644 --- a/arch/powerpc/cpu/mpc5xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xx/u-boot.lds @@ -93,7 +93,7 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); . = env_start; .ppcenv : diff --git a/arch/powerpc/cpu/mpc5xxx/spl_boot.c b/arch/powerpc/cpu/mpc5xxx/spl_boot.c index 9f14127..35611cc 100644 --- a/arch/powerpc/cpu/mpc5xxx/spl_boot.c +++ b/arch/powerpc/cpu/mpc5xxx/spl_boot.c @@ -41,13 +41,12 @@ void board_init_f(ulong bootflag) end_align = (u32)__spl_flash_end; /* - * First we need to initialize the SDRAM, so that the real - * U-Boot or the OS (Linux) can be loaded + * On MPC5200, the initial RAM (and gd) is located in the internal + * SRAM. So we can actually call the preloader console init code + * before calling initdram(). This makes serial output (printf) + * available very early, even before SDRAM init, which has been + * an U-Boot priciple from day 1. */ - initdram(0); - - /* Clear bss */ - memset(__bss_start, '\0', __bss_end__ - __bss_start); /* * Init global_data pointer. Has to be done before calling @@ -71,6 +70,15 @@ void board_init_f(ulong bootflag) preloader_console_init(); /* + * First we need to initialize the SDRAM, so that the real + * U-Boot or the OS (Linux) can be loaded + */ + initdram(0); + + /* Clear bss */ + memset(__bss_start, '\0', __bss_end - __bss_start); + + /* * Call board_init_r() (SPL framework version) to load and boot * real U-Boot or OS */ diff --git a/arch/powerpc/cpu/mpc5xxx/start.S b/arch/powerpc/cpu/mpc5xxx/start.S index ad5bc0a..2b6a800 100644 --- a/arch/powerpc/cpu/mpc5xxx/start.S +++ b/arch/powerpc/cpu/mpc5xxx/start.S @@ -66,7 +66,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT #endif @@ -694,7 +694,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds index cdb36c0..590952f 100644 --- a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds +++ b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds @@ -91,6 +91,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds index cab9b92..0500739 100644 --- a/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds @@ -52,6 +52,6 @@ SECTIONS __bss_start = .; *(.bss*) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } > sdram } diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds b/arch/powerpc/cpu/mpc5xxx/u-boot.lds index 6bd646b..06ece78 100644 --- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds +++ b/arch/powerpc/cpu/mpc5xxx/u-boot.lds @@ -87,6 +87,6 @@ SECTIONS *(.sbss*) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc8220/start.S b/arch/powerpc/cpu/mpc8220/start.S index a1a2dc5..6295631 100644 --- a/arch/powerpc/cpu/mpc8220/start.S +++ b/arch/powerpc/cpu/mpc8220/start.S @@ -64,7 +64,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT @@ -647,7 +647,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc8220/u-boot.lds b/arch/powerpc/cpu/mpc8220/u-boot.lds index 6e9967c..dc63d20 100644 --- a/arch/powerpc/cpu/mpc8220/u-boot.lds +++ b/arch/powerpc/cpu/mpc8220/u-boot.lds @@ -86,6 +86,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S index 076df70..0b9d898 100644 --- a/arch/powerpc/cpu/mpc824x/start.S +++ b/arch/powerpc/cpu/mpc824x/start.S @@ -72,7 +72,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) #if defined(CONFIG_FADS) GOT_ENTRY(environment) @@ -584,7 +584,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc824x/u-boot.lds b/arch/powerpc/cpu/mpc824x/u-boot.lds index 699fb85..4590fab 100644 --- a/arch/powerpc/cpu/mpc824x/u-boot.lds +++ b/arch/powerpc/cpu/mpc824x/u-boot.lds @@ -87,6 +87,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc8260/start.S b/arch/powerpc/cpu/mpc8260/start.S index 3299d72..bd8d7ac 100644 --- a/arch/powerpc/cpu/mpc8260/start.S +++ b/arch/powerpc/cpu/mpc8260/start.S @@ -65,7 +65,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) #if defined(CONFIG_HYMOD) GOT_ENTRY(environment) @@ -920,7 +920,7 @@ clear_bss: */ lwz r4,GOT(environment) #else - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) #endif cmplw 0, r3, r4 diff --git a/arch/powerpc/cpu/mpc8260/u-boot.lds b/arch/powerpc/cpu/mpc8260/u-boot.lds index 2709f37..eb1c611 100644 --- a/arch/powerpc/cpu/mpc8260/u-boot.lds +++ b/arch/powerpc/cpu/mpc8260/u-boot.lds @@ -86,6 +86,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index 44a64b7..1bfc971 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -76,7 +76,7 @@ START_GOT GOT_ENTRY(_GOT2_TABLE_) GOT_ENTRY(__bss_start) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) #ifndef MINIMAL_SPL GOT_ENTRY(_FIXUP_TABLE_) @@ -980,7 +980,7 @@ clear_bss: */ lwz r4,GOT(environment) #else - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) #endif cmplw 0, r3, r4 diff --git a/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds index d140453..870b47d 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot-spl.lds @@ -49,7 +49,7 @@ SECTIONS .bss (NOLOAD) : { *(.*bss) } - __bss_end__ = .; + __bss_end = .; } ENTRY(_start) -ASSERT(__bss_end__ <= 0xfff01000, "NAND bootstrap too big"); +ASSERT(__bss_end <= 0xfff01000, "NAND bootstrap too big"); diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds index 905823c..a9d8598 100644 --- a/arch/powerpc/cpu/mpc83xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds @@ -85,7 +85,7 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } ENTRY(_start) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 5495dc5..825a292 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -513,7 +513,7 @@ void fsl_serdes_init(void) size_t arglen; #endif #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 - int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */ + int need_serdes_a001; /* true == need work-around for SERDES A001 */ #endif #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8 char buffer[HWCONFIG_BUFFER_SIZE]; diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index fb67469..3f76ee6 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -70,7 +70,7 @@ #endif GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT @@ -1784,7 +1784,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0,r3,r4 beq 6f diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds index 3bb7572..65106f5 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds @@ -103,6 +103,6 @@ SECTIONS } :bss . = ALIGN(4); - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds index 87522b8..80cd980 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds @@ -80,6 +80,6 @@ SECTIONS *(.sbss*) *(.bss*) } - __bss_end__ = .; + __bss_end = .; } ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big"); diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 1c408e2..f2b7bff 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -83,5 +83,5 @@ SECTIONS *(.sbss*) *(.bss*) } - __bss_end__ = .; + __bss_end = .; } diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds index 8c6e66e..0503dce 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds @@ -127,6 +127,6 @@ SECTIONS } :bss . = ALIGN(4); - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc86xx/start.S b/arch/powerpc/cpu/mpc86xx/start.S index ef80ecf..20dfb9e 100644 --- a/arch/powerpc/cpu/mpc86xx/start.S +++ b/arch/powerpc/cpu/mpc86xx/start.S @@ -61,7 +61,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT @@ -800,7 +800,7 @@ in_ram: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc86xx/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds index 81804e3..7e357ba 100644 --- a/arch/powerpc/cpu/mpc86xx/u-boot.lds +++ b/arch/powerpc/cpu/mpc86xx/u-boot.lds @@ -90,6 +90,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile index 0d1a12c..ef10e2d 100644 --- a/arch/powerpc/cpu/mpc8xx/Makefile +++ b/arch/powerpc/cpu/mpc8xx/Makefile @@ -37,7 +37,6 @@ COBJS-y += fec.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-y += i2c.o COBJS-y += interrupts.o -COBJS-y += lcd.o COBJS-y += scc.o COBJS-y += serial.o COBJS-y += speed.o diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index ebca3ac..5aa50c5 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -72,7 +72,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT @@ -590,7 +590,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 6f diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 2847094..2db9045 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -167,6 +167,11 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) } } + if (mode_idx < 0 || phy_idx < 0) { + puts("ERROR: wrong usb mode/phy defined!!\n"); + return; + } + dr_mode_type = modes[mode_idx]; dr_phy_type = phys[phy_idx]; diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c index 8a20a2b..161d274 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c @@ -88,8 +88,6 @@ void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")) #define NUMMEMTESTS 8 #define NUMMEMWORDS 8 #define MAXBXCR 4 -#define TRUE 1 -#define FALSE 0 /* * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory @@ -298,7 +296,7 @@ static void get_spd_info(unsigned long *dimm_populated, unsigned char num_of_bytes; unsigned char total_size; - dimm_found = FALSE; + dimm_found = false; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { num_of_bytes = 0; total_size = 0; @@ -307,16 +305,16 @@ static void get_spd_info(unsigned long *dimm_populated, total_size = spd_read(iic0_dimm_addr[dimm_num], 1); if ((num_of_bytes != 0) && (total_size != 0)) { - dimm_populated[dimm_num] = TRUE; - dimm_found = TRUE; + dimm_populated[dimm_num] = true; + dimm_found = true; debug("DIMM slot %lu: populated\n", dimm_num); } else { - dimm_populated[dimm_num] = FALSE; + dimm_populated[dimm_num] = false; debug("DIMM slot %lu: Not populated\n", dimm_num); } } - if (dimm_found == FALSE) { + if (dimm_found == false) { printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); spd_ddr_init_hang (); } @@ -330,7 +328,7 @@ static void check_mem_type(unsigned long *dimm_populated, unsigned char dimm_type; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); switch (dimm_type) { case 7: @@ -356,7 +354,7 @@ static void check_volt_type(unsigned long *dimm_populated, unsigned long voltage_type; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8); if (voltage_type != 0x04) { printf("ERROR: DIMM %lu with unsupported voltage level.\n", @@ -398,12 +396,12 @@ static void program_cfg0(unsigned long *dimm_populated, /* * FIXME: assume the DDR SDRAMs in both banks are the same */ - ecc_enabled = TRUE; + ecc_enabled = true; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { ecc = spd_read(iic0_dimm_addr[dimm_num], 11); if (ecc != 0x02) { - ecc_enabled = FALSE; + ecc_enabled = false; } /* @@ -437,7 +435,7 @@ static void program_cfg0(unsigned long *dimm_populated, /* * program Memory Data Error Checking */ - if (ecc_enabled == TRUE) { + if (ecc_enabled == true) { cfg0 |= SDRAM_CFG0_MCHK_GEN; } else { cfg0 |= SDRAM_CFG0_MCHK_NON; @@ -493,7 +491,7 @@ static void program_rtr(unsigned long *dimm_populated, bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10); for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12); switch (refresh_rate_type) { case 0x00: @@ -585,15 +583,15 @@ static void program_tr0(unsigned long *dimm_populated, t_rp_ns = 0; t_rcd_ns = 0; t_ras_ns = 0; - cas_2_0_available = TRUE; - cas_2_5_available = TRUE; - cas_3_0_available = TRUE; + cas_2_0_available = true; + cas_2_5_available = true; + cas_3_0_available = true; tcyc_2_0_ns_x_10 = 0; tcyc_2_5_ns_x_10 = 0; tcyc_3_0_ns_x_10 = 0; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15); t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2; t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2; @@ -640,7 +638,7 @@ static void program_tr0(unsigned long *dimm_populated, if (cas_index != 0) { cas_index++; } - cas_3_0_available = FALSE; + cas_3_0_available = false; } if (((cas_bit & 0x08) != 0) || (cas_index < 3)) { @@ -650,7 +648,7 @@ static void program_tr0(unsigned long *dimm_populated, if (cas_index != 0) { cas_index++; } - cas_2_5_available = FALSE; + cas_2_5_available = false; } if (((cas_bit & 0x04) != 0) || (cas_index < 3)) { @@ -660,7 +658,7 @@ static void program_tr0(unsigned long *dimm_populated, if (cas_index != 0) { cas_index++; } - cas_2_0_available = FALSE; + cas_2_0_available = false; } break; @@ -683,13 +681,13 @@ static void program_tr0(unsigned long *dimm_populated, /* * Program SD_CASL field */ - if ((cas_2_0_available == TRUE) && + if ((cas_2_0_available == true) && (bus_period_x_10 >= tcyc_2_0_ns_x_10)) { tr0 |= SDRAM_TR0_SDCL_2_0_CLK; - } else if ((cas_2_5_available == TRUE) && + } else if ((cas_2_5_available == true) && (bus_period_x_10 >= tcyc_2_5_ns_x_10)) { tr0 |= SDRAM_TR0_SDCL_2_5_CLK; - } else if ((cas_3_0_available == TRUE) && + } else if ((cas_3_0_available == true) && (bus_period_x_10 >= tcyc_3_0_ns_x_10)) { tr0 |= SDRAM_TR0_SDCL_3_0_CLK; } else { @@ -950,9 +948,9 @@ static void program_tr1(void) current_fail_length = 0; current_start = 0; rdclt_offset = 0; - window_found = FALSE; - fail_found = FALSE; - pass_found = FALSE; + window_found = false; + fail_found = false; + pass_found = false; debug("Starting memory test "); for (k = 0; k < NUMHALFCYCLES; k++) { @@ -963,8 +961,8 @@ static void program_tr1(void) mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt))); if (short_mem_test()) { - if (fail_found == TRUE) { - pass_found = TRUE; + if (fail_found == true) { + pass_found = true; if (current_pass_length == 0) { current_start = rdclt_offset + rdclt; } @@ -983,10 +981,10 @@ static void program_tr1(void) current_fail_length++; if (current_fail_length >= (dly_val>>2)) { - if (fail_found == FALSE) { - fail_found = TRUE; - } else if (pass_found == TRUE) { - window_found = TRUE; + if (fail_found == false) { + fail_found = true; + } else if (pass_found == true) { + window_found = true; break; } } @@ -994,9 +992,8 @@ static void program_tr1(void) } debug("."); - if (window_found == TRUE) { + if (window_found == true) break; - } tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK; rdclt_offset += dly_val; @@ -1006,7 +1003,7 @@ static void program_tr1(void) /* * make sure we find the window */ - if (window_found == FALSE) { + if (window_found == false) { printf("ERROR: Cannot determine a common read delay.\n"); spd_ddr_init_hang (); } @@ -1115,7 +1112,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, bank_base_addr = CONFIG_SYS_SDRAM_BASE; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3); num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4); num_banks = spd_read(iic0_dimm_addr[dimm_num], 5); diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index 85217ea..def7ebf 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -241,13 +241,6 @@ void board_add_ram_info(int use_default) /*-----------------------------------------------------------------------------+ * Defines *-----------------------------------------------------------------------------*/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - #define SDRAM_DDR1 1 #define SDRAM_DDR2 2 #define SDRAM_NONE 0 @@ -683,7 +676,7 @@ static void get_spd_info(unsigned long *dimm_populated, unsigned char num_of_bytes; unsigned char total_size; - dimm_found = FALSE; + dimm_found = false; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { num_of_bytes = 0; total_size = 0; @@ -696,16 +689,16 @@ static void get_spd_info(unsigned long *dimm_populated, iic0_dimm_addr[dimm_num], total_size); if ((num_of_bytes != 0) && (total_size != 0)) { - dimm_populated[dimm_num] = TRUE; - dimm_found = TRUE; + dimm_populated[dimm_num] = true; + dimm_found = true; debug("DIMM slot %lu: populated\n", dimm_num); } else { - dimm_populated[dimm_num] = FALSE; + dimm_populated[dimm_num] = false; debug("DIMM slot %lu: Not populated\n", dimm_num); } } - if (dimm_found == FALSE) { + if (dimm_found == false) { printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); spd_ddr_init_hang (); } @@ -724,7 +717,7 @@ static void check_mem_type(unsigned long *dimm_populated, unsigned long dimm_type; for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { - if (dimm_populated[dimm_num] == TRUE) { + if (dimm_populated[dimm_num] == true) { dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2); switch (dimm_type) { case 1: @@ -994,14 +987,14 @@ static void program_copt1(unsigned long *dimm_populated, unsigned long val; #ifdef CONFIG_DDR_ECC - ecc_enabled = TRUE; + ecc_enabled = true; #else - ecc_enabled = FALSE; + ecc_enabled = false; #endif - dimm_32bit = FALSE; - dimm_64bit = FALSE; - buf0 = FALSE; - buf1 = FALSE; + dimm_32bit = false; + dimm_64bit = false; + buf0 = false; + buf1 = false; /*------------------------------------------------------------------ * Set memory controller options reg 1, SDRAM_MCOPT1. @@ -1026,7 +1019,7 @@ static void program_copt1(unsigned long *dimm_populated, /* test ecc support */ ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11); if (ecc != 0x02) /* ecc not supported */ - ecc_enabled = FALSE; + ecc_enabled = false; /* test bank count */ bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17); @@ -1048,15 +1041,15 @@ static void program_copt1(unsigned long *dimm_populated, if (registered == 1) { /* DDR2 always buffered */ /* TODO: what about above comments ? */ mcopt1 |= SDRAM_MCOPT1_RDEN; - buf0 = TRUE; + buf0 = true; } else { /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */ if ((attribute & 0x02) == 0x00) { /* buffered not supported */ - buf0 = FALSE; + buf0 = false; } else { mcopt1 |= SDRAM_MCOPT1_RDEN; - buf0 = TRUE; + buf0 = true; } } } @@ -1068,14 +1061,14 @@ static void program_copt1(unsigned long *dimm_populated, if (registered == 1) { /* DDR2 always buffered */ mcopt1 |= SDRAM_MCOPT1_RDEN; - buf1 = TRUE; + buf1 = true; } else { if ((attribute & 0x02) == 0x00) { /* buffered not supported */ - buf1 = FALSE; + buf1 = false; } else { mcopt1 |= SDRAM_MCOPT1_RDEN; - buf1 = TRUE; + buf1 = true; } } } @@ -1087,11 +1080,11 @@ static void program_copt1(unsigned long *dimm_populated, switch (data_width) { case 72: case 64: - dimm_64bit = TRUE; + dimm_64bit = true; break; case 40: case 32: - dimm_32bit = TRUE; + dimm_32bit = true; break; default: printf("WARNING: Detected a DIMM with a data width of %lu bits.\n", @@ -1110,20 +1103,19 @@ static void program_copt1(unsigned long *dimm_populated, } } - if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) { + if ((dimm_64bit == true) && (dimm_32bit == true)) { printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n"); spd_ddr_init_hang (); - } - else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) { + } else if ((dimm_64bit == true) && (dimm_32bit == false)) { mcopt1 |= SDRAM_MCOPT1_DMWD_64; - } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) { + } else if ((dimm_64bit == false) && (dimm_32bit == true)) { mcopt1 |= SDRAM_MCOPT1_DMWD_32; } else { printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n"); spd_ddr_init_hang (); } - if (ecc_enabled == TRUE) + if (ecc_enabled == true) mcopt1 |= SDRAM_MCOPT1_MCHK_GEN; else mcopt1 |= SDRAM_MCOPT1_MCHK_NON; @@ -1171,14 +1163,14 @@ static void program_codt(unsigned long *dimm_populated, total_rank += dimm_rank; total_dimm++; if ((dimm_num == 0) && (total_dimm == 1)) - firstSlot = TRUE; + firstSlot = true; else - firstSlot = FALSE; + firstSlot = false; } } if (dimm_type == SDRAM_DDR2) { codt |= SDRAM_CODT_DQS_1_8_V_DDR2; - if ((total_dimm == 1) && (firstSlot == TRUE)) { + if ((total_dimm == 1) && (firstSlot == true)) { if (total_rank == 1) { /* PUUU */ codt |= CALC_ODT_R(0); modt0 = CALC_ODT_W(0); @@ -1193,7 +1185,7 @@ static void program_codt(unsigned long *dimm_populated, modt2 = 0x00000000; modt3 = 0x00000000; } - } else if ((total_dimm == 1) && (firstSlot != TRUE)) { + } else if ((total_dimm == 1) && (firstSlot != true)) { if (total_rank == 1) { /* UUPU */ codt |= CALC_ODT_R(2); modt0 = 0x00000000; @@ -1467,26 +1459,26 @@ static void program_mode(unsigned long *dimm_populated, * the dimm modules installed. *-----------------------------------------------------------------*/ t_wr_ns = 0; - cas_2_0_available = TRUE; - cas_2_5_available = TRUE; - cas_3_0_available = TRUE; - cas_4_0_available = TRUE; - cas_5_0_available = TRUE; + cas_2_0_available = true; + cas_2_5_available = true; + cas_3_0_available = true; + cas_4_0_available = true; + cas_5_0_available = true; max_2_0_tcyc_ns_x_100 = 10; max_2_5_tcyc_ns_x_100 = 10; max_3_0_tcyc_ns_x_100 = 10; max_4_0_tcyc_ns_x_100 = 10; max_5_0_tcyc_ns_x_100 = 10; - sdram_ddr1 = TRUE; + sdram_ddr1 = true; /* loop through all the DIMM slots on the board */ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_populated[dimm_num] != SDRAM_NONE) { if (dimm_populated[dimm_num] == SDRAM_DDR1) - sdram_ddr1 = TRUE; + sdram_ddr1 = true; else - sdram_ddr1 = FALSE; + sdram_ddr1 = false; cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18); debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit); @@ -1543,7 +1535,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_4_0_available = FALSE; + cas_4_0_available = false; } if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && @@ -1554,7 +1546,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_3_0_available = FALSE; + cas_3_0_available = false; } if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && @@ -1565,7 +1557,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_2_5_available = FALSE; + cas_2_5_available = false; } if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) && @@ -1576,7 +1568,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_2_0_available = FALSE; + cas_2_0_available = false; } } else { /* @@ -1592,7 +1584,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_5_0_available = FALSE; + cas_5_0_available = false; } if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) && @@ -1603,7 +1595,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_4_0_available = FALSE; + cas_4_0_available = false; } if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) && @@ -1614,7 +1606,7 @@ static void program_mode(unsigned long *dimm_populated, } else { if (cas_index != 0) cas_index++; - cas_3_0_available = FALSE; + cas_3_0_available = false; } } } @@ -1636,14 +1628,17 @@ static void program_mode(unsigned long *dimm_populated, debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk); debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk); - if (sdram_ddr1 == TRUE) { /* DDR1 */ - if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) { + if (sdram_ddr1 == true) { /* DDR1 */ + if ((cas_2_0_available == true) && + (sdram_freq <= cycle_2_0_clk)) { mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK; *selected_cas = DDR_CAS_2; - } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) { + } else if ((cas_2_5_available == true) && + (sdram_freq <= cycle_2_5_clk)) { mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK; *selected_cas = DDR_CAS_2_5; - } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) { + } else if ((cas_3_0_available == true) && + (sdram_freq <= cycle_3_0_clk)) { mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK; *selected_cas = DDR_CAS_3; } else { @@ -1656,13 +1651,16 @@ static void program_mode(unsigned long *dimm_populated, debug("cas_3_0_available=%d\n", cas_3_0_available); debug("cas_4_0_available=%d\n", cas_4_0_available); debug("cas_5_0_available=%d\n", cas_5_0_available); - if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) { + if ((cas_3_0_available == true) && + (sdram_freq <= cycle_3_0_clk)) { mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK; *selected_cas = DDR_CAS_3; - } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) { + } else if ((cas_4_0_available == true) && + (sdram_freq <= cycle_4_0_clk)) { mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK; *selected_cas = DDR_CAS_4; - } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) { + } else if ((cas_5_0_available == true) && + (sdram_freq <= cycle_5_0_clk)) { mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK; *selected_cas = DDR_CAS_5; } else { @@ -1677,7 +1675,7 @@ static void program_mode(unsigned long *dimm_populated, } } - if (sdram_ddr1 == TRUE) + if (sdram_ddr1 == true) mmode |= SDRAM_MMODE_WR_DDR1; else { @@ -1851,16 +1849,16 @@ static void program_tr(unsigned long *dimm_populated, t_wpc_ns = 0; t_wtr_ns = 0; t_rpc_ns = 0; - sdram_ddr1 = TRUE; + sdram_ddr1 = true; /* loop through all the DIMM slots on the board */ for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) { /* If a dimm is installed in a particular slot ... */ if (dimm_populated[dimm_num] != SDRAM_NONE) { if (dimm_populated[dimm_num] == SDRAM_DDR2) - sdram_ddr1 = TRUE; + sdram_ddr1 = true; else - sdram_ddr1 = FALSE; + sdram_ddr1 = false; t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2); t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2); @@ -1925,7 +1923,7 @@ static void program_tr(unsigned long *dimm_populated, break; } - if (sdram_ddr1 == TRUE) { /* DDR1 */ + if (sdram_ddr1 == true) { /* DDR1 */ if (sdram_freq < 200000000) { sdtr2 |= SDRAM_SDTR2_WTR_1_CLK; sdtr2 |= SDRAM_SDTR2_WPC_2_CLK; @@ -2548,8 +2546,8 @@ calibration_loop: current_pass_length = 0; current_fail_length = 0; current_start = 0; - fail_found = FALSE; - pass_found = FALSE; + fail_found = false; + pass_found = false; /* * get the delay line calibration register value @@ -2570,8 +2568,8 @@ calibration_loop: * See if the rffd value passed. *-----------------------------------------------------------------*/ if (short_mem_test()) { - if (fail_found == TRUE) { - pass_found = TRUE; + if (fail_found == true) { + pass_found = true; if (current_pass_length == 0) current_start = rffd; @@ -2589,11 +2587,10 @@ calibration_loop: current_fail_length++; if (current_fail_length >= (dly_val >> 2)) { - if (fail_found == FALSE) { - fail_found = TRUE; - } else if (pass_found == TRUE) { + if (fail_found == false) + fail_found = true; + else if (pass_found == true) break; - } } } } /* for rffd */ @@ -2618,9 +2615,9 @@ calibration_loop: current_pass_length = 0; current_fail_length = 0; current_start = 0; - window_found = FALSE; - fail_found = FALSE; - pass_found = FALSE; + window_found = false; + fail_found = false; + pass_found = false; for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) { mfsdram(SDRAM_RQDC, rqdc_reg); @@ -2635,8 +2632,8 @@ calibration_loop: * See if the rffd value passed. *-----------------------------------------------------------------*/ if (short_mem_test()) { - if (fail_found == TRUE) { - pass_found = TRUE; + if (fail_found == true) { + pass_found = true; if (current_pass_length == 0) current_start = rqfd; @@ -2653,10 +2650,10 @@ calibration_loop: current_pass_length = 0; current_fail_length++; - if (fail_found == FALSE) { - fail_found = TRUE; - } else if (pass_found == TRUE) { - window_found = TRUE; + if (fail_found == false) { + fail_found = true; + } else if (pass_found == true) { + window_found = true; break; } } @@ -2667,7 +2664,7 @@ calibration_loop: /*------------------------------------------------------------------ * Make sure we found the valid read passing window. Halt if not *-----------------------------------------------------------------*/ - if (window_found == FALSE) { + if (window_found == false) { if (rqfd_start < SDRAM_RQDC_RQFD_MAX) { putc('\b'); putc(slash[loopi++ % 8]); @@ -2769,13 +2766,13 @@ static void test(void) mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_NON); - window_found = FALSE; - begin_found[0] = FALSE; - end_found[0] = FALSE; - search_end[0] = FALSE; - begin_found[1] = FALSE; - end_found[1] = FALSE; - search_end[1] = FALSE; + window_found = false; + begin_found[0] = false; + end_found[0] = false; + search_end[0] = false; + begin_found[1] = false; + end_found[1] = false; + search_end[1] = false; for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]); @@ -2812,32 +2809,32 @@ static void test(void) * See if the rffd value passed. *-----------------------------------------------------------------*/ if (i < NUMMEMTESTS) { - if ((end_found[dimm_num] == FALSE) && - (search_end[dimm_num] == TRUE)) { - end_found[dimm_num] = TRUE; + if ((end_found[dimm_num] == false) && + (search_end[dimm_num] == true)) { + end_found[dimm_num] = true; } - if ((end_found[0] == TRUE) && - (end_found[1] == TRUE)) + if ((end_found[0] == true) && + (end_found[1] == true)) break; } else { - if (begin_found[dimm_num] == FALSE) { - begin_found[dimm_num] = TRUE; - search_end[dimm_num] = TRUE; + if (begin_found[dimm_num] == false) { + begin_found[dimm_num] = true; + search_end[dimm_num] = true; } } } else { - begin_found[dimm_num] = TRUE; - end_found[dimm_num] = TRUE; + begin_found[dimm_num] = true; + end_found[dimm_num] = true; } } - if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE)) - window_found = TRUE; + if ((begin_found[0] == true) && (begin_found[1] == true)) + window_found = true; /*------------------------------------------------------------------ * Make sure we found the valid read passing window. Halt if not *-----------------------------------------------------------------*/ - if (window_found == FALSE) { + if (window_found == false) { printf("ERROR: Cannot determine a common read delay for the " "DIMM(s) installed.\n"); spd_ddr_init_hang (); diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c index ce769a7..3ceab32 100644 --- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c @@ -53,13 +53,6 @@ /*-----------------------------------------------------------------------------+ * Defines *-----------------------------------------------------------------------------*/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - #define MAXDIMMS 2 #define MAXRANKS 2 @@ -279,7 +272,7 @@ static void get_spd_info(unsigned long dimm_ranks[], unsigned long num_dimm_banks) { unsigned long dimm_num; - unsigned long dimm_found = FALSE; + unsigned long dimm_found = false; unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1; unsigned char num_of_bytes; unsigned char total_size; @@ -334,7 +327,7 @@ static void get_spd_info(unsigned long dimm_ranks[], "\n\n"); spd_ddr_init_hang(); } - dimm_found = TRUE; + dimm_found = true; debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM" "\n", dimm_num, ranks_on_dimm); if (ranks_on_dimm > max_ranks_per_dimm) { @@ -355,7 +348,7 @@ static void get_spd_info(unsigned long dimm_ranks[], debug("DIMM slot %lu: Not populated\n", dimm_num); } } - if (dimm_found == FALSE) { + if (dimm_found == false) { printf("ERROR: No memory installed.\n"); printf("Install at least one DDR2 DIMM.\n\n"); spd_ddr_init_hang(); @@ -882,7 +875,7 @@ static void program_ddr0_22(unsigned long dimm_ranks[], /* Check for ECC */ if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) & 0x02)) { - ecc_available = FALSE; + ecc_available = false; } } } diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 7aef43b..52f2623 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -243,7 +243,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(__init_end) - GOT_ENTRY(__bss_end__) + GOT_ENTRY(__bss_end) GOT_ENTRY(__bss_start) END_GOT #endif /* CONFIG_NAND_SPL */ @@ -1509,7 +1509,7 @@ clear_bss: * Now clear BSS segment */ lwz r3,GOT(__bss_start) - lwz r4,GOT(__bss_end__) + lwz r4,GOT(__bss_end) cmplw 0, r3, r4 beq 7f diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds index 2cadcc9..06010d6 100644 --- a/arch/powerpc/cpu/ppc4xx/u-boot.lds +++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds @@ -142,6 +142,6 @@ SECTIONS } :bss . = ALIGN(4); - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h index f763a54..d96e536 100644 --- a/arch/powerpc/include/asm/immap_512x.h +++ b/arch/powerpc/include/asm/immap_512x.h @@ -227,7 +227,9 @@ typedef struct clk512x { #define CLOCK_SCCR2_IIM_EN 0x00080000 /* SCFR1 System Clock Frequency Register 1 */ +#ifndef SCFR1_IPS_DIV #define SCFR1_IPS_DIV 0x3 +#endif #define SCFR1_IPS_DIV_MASK 0x03800000 #define SCFR1_IPS_DIV_SHIFT 23 @@ -238,6 +240,12 @@ typedef struct clk512x { #define SCFR1_LPC_DIV_MASK 0x00003800 #define SCFR1_LPC_DIV_SHIFT 11 +#define SCFR1_NFC_DIV_MASK 0x00000700 +#define SCFR1_NFC_DIV_SHIFT 8 + +#define SCFR1_DIU_DIV_MASK 0x000000FF +#define SCFR1_DIU_DIV_SHIFT 0 + /* SCFR2 System Clock Frequency Register 2 */ #define SCFR2_SYS_DIV 0xFC000000 #define SCFR2_SYS_DIV_SHIFT 26 @@ -343,6 +351,7 @@ typedef struct ddr512x { /* MDDRC SYS CFG and Timing CFG0 Registers */ #define MDDRC_SYS_CFG_EN 0xF0000000 +#define MDDRC_SYS_CFG_CKE_MASK 0x40000000 #define MDDRC_SYS_CFG_CMD_MASK 0x10000000 #define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF @@ -871,6 +880,19 @@ typedef struct iopin_t { void iopin_initialize(iopin_t *,int); /* + * support to adjust individual parts of the IO pin setup + */ + +#define IO_PIN_OVER_EACH (1 << 0) /* for compatibility */ +#define IO_PIN_OVER_FMUX (1 << 1) +#define IO_PIN_OVER_HOLD (1 << 2) +#define IO_PIN_OVER_PULL (1 << 3) +#define IO_PIN_OVER_STRIG (1 << 4) +#define IO_PIN_OVER_DRVSTR (1 << 5) + +void iopin_initialize_bits(iopin_t *, int); + +/* * IIM */ typedef struct iim512x { diff --git a/arch/powerpc/include/asm/sections.h b/arch/powerpc/include/asm/sections.h new file mode 100644 index 0000000..0a94102 --- /dev/null +++ b/arch/powerpc/include/asm/sections.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_POWERPC_SECTIONS_H +#define __ASM_POWERPC_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif diff --git a/arch/powerpc/include/asm/spl.h b/arch/powerpc/include/asm/spl.h index f43bc23..7d5f9a0 100644 --- a/arch/powerpc/include/asm/spl.h +++ b/arch/powerpc/include/asm/spl.h @@ -26,6 +26,6 @@ #define BOOT_DEVICE_NOR 1 /* Linker symbols */ -extern char __bss_start[], __bss_end__[]; +extern char __bss_start[], __bss_end[]; #endif diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index 7229a98..cf972d2 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -34,6 +34,11 @@ * include/asm-ppc/u-boot.h */ +#ifdef CONFIG_SYS_GENERIC_BOARD +/* Use the generic board which requires a unified bd_info */ +#include <asm-generic/u-boot.h> +#else + #ifndef __ASSEMBLY__ typedef struct bd_info { @@ -144,6 +149,8 @@ typedef struct bd_info { #endif /* __ASSEMBLY__ */ +#endif /* !CONFIG_SYS_GENERIC_BOARD */ + /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_PPC diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 86cf02a..59c723b 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -59,8 +59,10 @@ SOBJS-y += reloc.o COBJS-$(CONFIG_BAT_RW) += bat_rw.o ifndef CONFIG_SPL_BUILD +ifndef CONFIG_SYS_GENERIC_BOARD COBJS-y += board.o endif +endif COBJS-y += bootm.o COBJS-y += cache.o COBJS-y += extable.o diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 12270a4..422b4a3 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -123,7 +123,7 @@ DECLARE_GLOBAL_DATA_PTR; #endif extern ulong __init_end; -extern ulong __bss_end__; +extern ulong __bss_end; ulong monitor_flash_len; #if defined(CONFIG_CMD_BEDBUG) @@ -237,25 +237,18 @@ static int init_func_spi(void) /***********************************************************************/ #if defined(CONFIG_WATCHDOG) -static int init_func_watchdog_init(void) +int init_func_watchdog_init(void) { puts(" Watchdog enabled\n"); WATCHDOG_RESET(); return 0; } -#define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init, - -static int init_func_watchdog_reset(void) +int init_func_watchdog_reset(void) { WATCHDOG_RESET(); return 0; } - -#define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset, -#else -#define INIT_FUNC_WATCHDOG_INIT /* undef */ -#define INIT_FUNC_WATCHDOG_RESET /* undef */ #endif /* CONFIG_WATCHDOG */ /* @@ -326,7 +319,8 @@ static init_fnc_t *init_sequence[] = { #ifdef CONFIG_POST post_init_f, #endif - INIT_FUNC_WATCHDOG_RESET init_func_ram, + INIT_FUNC_WATCHDOG_RESET + init_func_ram, #if defined(CONFIG_SYS_DRAM_TEST) testdram, #endif /* CONFIG_SYS_DRAM_TEST */ @@ -419,7 +413,7 @@ void board_init_f(ulong bootflag) * - monitor code * - board info struct */ - len = (ulong)&__bss_end__ - CONFIG_SYS_MONITOR_BASE; + len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; /* * Subtract specified amount of memory to hide so that it won't diff --git a/arch/powerpc/lib/ticks.S b/arch/powerpc/lib/ticks.S index 1781039..63114bb 100644 --- a/arch/powerpc/lib/ticks.S +++ b/arch/powerpc/lib/ticks.S @@ -50,19 +50,24 @@ wait_ticks: stwu r1, -16(r1) mflr r0 /* save link register */ stw r0, 20(r1) /* Use r0 or GDB will be unhappy */ - mr r7, r3 /* save tick count */ + stw r14, 12(r1) /* save used registers */ + stw r15, 8(r1) + mr r14, r3 /* save tick count */ bl get_ticks /* Get start time */ /* Calculate end time */ - addc r7, r4, r7 /* Compute end time lower */ - addze r6, r3 /* and end time upper */ + addc r14, r4, r14 /* Compute end time lower */ + addze r15, r3 /* and end time upper */ WATCHDOG_RESET /* Trigger watchdog, if needed */ 1: bl get_ticks /* Get current time */ - subfc r4, r4, r7 /* Subtract current time from end time */ - subfe. r3, r3, r6 + subfc r4, r4, r14 /* Subtract current time from end time */ + subfe. r3, r3, r15 bge 1b /* Loop until time expired */ - mtlr r0 /* restore link register */ + lwz r15, 8(r1) /* restore saved registers */ + lwz r14, 12(r1) + lwz r0, 20(r1) addi r1,r1,16 + mtlr r0 blr diff --git a/arch/sandbox/include/asm/sections.h b/arch/sandbox/include/asm/sections.h index eafce7d..4c37860 100644 --- a/arch/sandbox/include/asm/sections.h +++ b/arch/sandbox/include/asm/sections.h @@ -9,6 +9,8 @@ #ifndef __SANDBOX_SECTIONS_H #define __SANDBOX_SECTIONS_H +#include <asm-generic/sections.h> + struct sb_cmdline_option; extern struct sb_cmdline_option *__u_boot_sandbox_option_start[], diff --git a/arch/sh/cpu/sh2/u-boot.lds b/arch/sh/cpu/sh2/u-boot.lds index 9bf1d85..3cd5699 100644 --- a/arch/sh/cpu/sh2/u-boot.lds +++ b/arch/sh/cpu/sh2/u-boot.lds @@ -88,5 +88,5 @@ SECTIONS } PROVIDE (bss_end = .); - PROVIDE (__bss_end__ = .); + PROVIDE (__bss_end = .); } diff --git a/arch/sh/cpu/sh3/u-boot.lds b/arch/sh/cpu/sh3/u-boot.lds index 29352ad..654c52c 100644 --- a/arch/sh/cpu/sh3/u-boot.lds +++ b/arch/sh/cpu/sh3/u-boot.lds @@ -95,5 +95,5 @@ SECTIONS } PROVIDE (bss_end = .); - PROVIDE (__bss_end__ = .); + PROVIDE (__bss_end = .); } diff --git a/arch/sh/cpu/sh4/u-boot.lds b/arch/sh/cpu/sh4/u-boot.lds index cf3da0d..11d7ffa 100644 --- a/arch/sh/cpu/sh4/u-boot.lds +++ b/arch/sh/cpu/sh4/u-boot.lds @@ -92,5 +92,5 @@ SECTIONS } PROVIDE (bss_end = .); - PROVIDE (__bss_end__ = .); + PROVIDE (__bss_end = .); } diff --git a/arch/sh/include/asm/sections.h b/arch/sh/include/asm/sections.h new file mode 100644 index 0000000..8824560 --- /dev/null +++ b/arch/sh/include/asm/sections.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_SH_SECTIONS_H +#define __ASM_SH_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 34d7881..6e43acf 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -65,6 +65,7 @@ static int sh_flash_init(void) #if defined(CONFIG_WATCHDOG) extern int watchdog_init(void); extern int watchdog_disable(void); +# undef INIT_FUNC_WATCHDOG_INIT # define INIT_FUNC_WATCHDOG_INIT watchdog_init, # define WATCHDOG_DISABLE watchdog_disable #else diff --git a/arch/sparc/cpu/leon2/Makefile b/arch/sparc/cpu/leon2/Makefile index a9a18eb..d4dc397 100644 --- a/arch/sparc/cpu/leon2/Makefile +++ b/arch/sparc/cpu/leon2/Makefile @@ -43,13 +43,6 @@ $(LIB): $(OBJS) # defines $(obj).depend target include $(SRCTREE)/rules.mk -$(START): $(START:.o=.S) - $(CC) -D__ASSEMBLY__ $(DBGFLAGS) $(OPTFLAGS) -D__KERNEL__ \ - -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) -I$(TOPDIR)/include \ - -fno-builtin -ffreestanding -nostdinc -isystem $(gccincdir) -pipe \ - $(PLATFORM_CPPFLAGS) -Wall -Wstrict-prototypes \ - -I$(TOPDIR)/board -c -o $(START) $(START:.o=.S) - sinclude $(obj).depend ######################################################################### diff --git a/arch/sparc/cpu/leon2/serial.c b/arch/sparc/cpu/leon2/serial.c index 40d5b01..b41ee01 100644 --- a/arch/sparc/cpu/leon2/serial.c +++ b/arch/sparc/cpu/leon2/serial.c @@ -31,16 +31,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* Force cache miss each time a serial controller reg is read */ -#define CACHE_BYPASS 1 - -#ifdef CACHE_BYPASS -#define READ_BYTE(var) SPARC_NOCACHE_READ_BYTE((unsigned int)&(var)) -#define READ_HWORD(var) SPARC_NOCACHE_READ_HWORD((unsigned int)&(var)) -#define READ_WORD(var) SPARC_NOCACHE_READ((unsigned int)&(var)) -#define READ_DWORD(var) SPARC_NOCACHE_READ_DWORD((unsigned int)&(var)) -#endif - static int leon2_serial_init(void) { LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS; diff --git a/arch/sparc/cpu/leon3/Makefile b/arch/sparc/cpu/leon3/Makefile index 16d3377..1d051e1 100644 --- a/arch/sparc/cpu/leon3/Makefile +++ b/arch/sparc/cpu/leon3/Makefile @@ -43,13 +43,6 @@ $(LIB): $(OBJS) # defines $(obj).depend target include $(SRCTREE)/rules.mk -$(START): $(START:.o=.S) - $(CC) -D__ASSEMBLY__ $(DBGFLAGS) $(OPTFLAGS) -D__KERNEL__ \ - -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) -I$(TOPDIR)/include \ - -fno-builtin -ffreestanding -nostdinc -isystem $(gccincdir) -pipe \ - $(PLATFORM_CPPFLAGS) -Wall -Wstrict-prototypes \ - -I$(TOPDIR)/board -c -o $(START) $(START:.o=.S) - sinclude $(obj).depend ######################################################################### diff --git a/arch/sparc/cpu/leon3/serial.c b/arch/sparc/cpu/leon3/serial.c index 838d451..af9ce55 100644 --- a/arch/sparc/cpu/leon3/serial.c +++ b/arch/sparc/cpu/leon3/serial.c @@ -32,16 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* Force cache miss each time a serial controller reg is read */ -#define CACHE_BYPASS 1 - -#ifdef CACHE_BYPASS -#define READ_BYTE(var) SPARC_NOCACHE_READ_BYTE((unsigned int)&(var)) -#define READ_HWORD(var) SPARC_NOCACHE_READ_HWORD((unsigned int)&(var)) -#define READ_WORD(var) SPARC_NOCACHE_READ((unsigned int)&(var)) -#define READ_DWORD(var) SPARC_NOCACHE_READ_DWORD((unsigned int)&(var)) -#endif - ambapp_dev_apbuart *leon3_apbuart = NULL; static int leon3_serial_init(void) diff --git a/arch/sparc/include/asm/sections.h b/arch/sparc/include/asm/sections.h new file mode 100644 index 0000000..90f7fa7 --- /dev/null +++ b/arch/sparc/include/asm/sections.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_SPARC_SECTIONS_H +#define __ASM_SPARC_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 23cacff..168dc24 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -36,6 +36,9 @@ PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0 +# Support generic board on x86 +__HAVE_ARCH_GENERIC_BOARD := y + PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index a8136a0..786009c 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -28,6 +28,7 @@ #include <asm/u-boot-x86.h> #include <asm/global_data.h> #include <asm/processor.h> +#include <asm/sections.h> #include <asm/arch/sysinfo.h> #include <asm/arch/tables.h> diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index ef5aa95..2d6911a 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -53,6 +53,7 @@ SECTIONS . = ALIGN(4); __data_end = .; + __init_end = .; . = ALIGN(4); .dynsym : { *(.dynsym*) } @@ -64,9 +65,6 @@ SECTIONS . = ALIGN(4); _end = .; - . = ALIGN(4); - - __end = .; .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; *(.bss) diff --git a/arch/x86/include/asm/config.h b/arch/x86/include/asm/config.h index 049c44e..3961b82 100644 --- a/arch/x86/include/asm/config.h +++ b/arch/x86/include/asm/config.h @@ -21,4 +21,5 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_SYS_GENERIC_BOARD #endif diff --git a/arch/x86/include/asm/sections.h b/arch/x86/include/asm/sections.h new file mode 100644 index 0000000..602df86 --- /dev/null +++ b/arch/x86/include/asm/sections.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_X86_SECTIONS_H +#define __ASM_X86_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 948615d..ae0c388 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -24,15 +24,6 @@ #ifndef _U_BOOT_I386_H_ #define _U_BOOT_I386_H_ 1 -/* Exports from the Linker Script */ -extern ulong __text_start; -extern ulong __data_end; -extern ulong __rel_dyn_start; -extern ulong __rel_dyn_end; -extern ulong __bss_start; -extern ulong __bss_end; -extern ulong _end; - /* cpu/.../cpu.c */ int x86_cpu_init_r(void); int cpu_init_r(void); diff --git a/arch/x86/include/asm/u-boot.h b/arch/x86/include/asm/u-boot.h index 2f45c7b..df759fa 100644 --- a/arch/x86/include/asm/u-boot.h +++ b/arch/x86/include/asm/u-boot.h @@ -39,6 +39,13 @@ #include <config.h> #include <compiler.h> +#ifdef CONFIG_SYS_GENERIC_BOARD +/* Use the generic board which requires a unified bd_info */ +#include <asm-generic/u-boot.h> +#else + +#ifndef __ASSEMBLY__ + typedef struct bd_info { unsigned long bi_memstart; /* start of DRAM memory */ phys_size_t bi_memsize; /* size of DRAM memory in bytes */ @@ -60,6 +67,10 @@ typedef struct bd_info { }bi_dram[CONFIG_NR_DRAM_BANKS]; } bd_t; +#endif /* __ASSEMBLY__ */ + +#endif /* !CONFIG_SYS_GENERIC_BOARD */ + /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_I386 diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 9b24dc5f..ee89354 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -25,7 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(ARCH).o +ifeq ($(CONFIG_SYS_GENERIC_BOARD),) COBJS-y += board.o +endif + COBJS-y += bootm.o COBJS-y += cmd_boot.o COBJS-y += gcc.o diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c index 2441a66..f372898 100644 --- a/arch/x86/lib/board.c +++ b/arch/x86/lib/board.c @@ -38,6 +38,7 @@ #include <asm/u-boot-x86.h> #include <asm/relocate.h> #include <asm/processor.h> +#include <asm/sections.h> #include <asm/init_helpers.h> #include <asm/init_wrappers.h> @@ -163,13 +164,13 @@ init_fnc_t *init_sequence_r[] = { #ifndef CONFIG_SYS_NO_FLASH flash_init_r, #endif -#ifdef CONFIG_SPI - init_func_spi; -#endif - env_relocate_r, #ifdef CONFIG_PCI pci_init_r, #endif +#ifdef CONFIG_SPI + init_func_spi, +#endif + env_relocate_r, stdio_init, jumptable_init_r, console_init_r, @@ -219,7 +220,7 @@ static void do_init_loop(init_fnc_t **init_fnc_ptr) void board_init_f(ulong boot_flags) { - gd->fdt_blob = gd->arch.new_fdt = NULL; + gd->fdt_blob = gd->new_fdt = NULL; gd->flags = boot_flags; do_init_loop(init_sequence_f); diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 414fdcc..af9dbc1 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -32,6 +32,7 @@ #include <spi.h> #include <status_led.h> #include <asm/processor.h> +#include <asm/sections.h> #include <asm/u-boot-x86.h> #include <linux/compiler.h> @@ -111,7 +112,7 @@ int calculate_relocation_address(void) */ if (gd->fdt_blob) { dest_addr -= fdt_size; - gd->arch.new_fdt = (void *)dest_addr; + gd->new_fdt = (void *)dest_addr; dest_addr &= ~15; } #endif diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index 3e370f2..f178db9 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -36,6 +36,7 @@ #include <malloc.h> #include <asm/u-boot-x86.h> #include <asm/relocate.h> +#include <asm/sections.h> #include <elf.h> int copy_uboot_to_ram(void) @@ -49,15 +50,15 @@ int copy_uboot_to_ram(void) int copy_fdt_to_ram(void) { - if (gd->arch.new_fdt) { + if (gd->new_fdt) { ulong fdt_size; fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); - memcpy(gd->arch.new_fdt, gd->fdt_blob, fdt_size); + memcpy(gd->new_fdt, gd->fdt_blob, fdt_size); debug("Relocated fdt from %p to %p, size %lx\n", - gd->fdt_blob, gd->arch.new_fdt, fdt_size); - gd->fdt_blob = gd->arch.new_fdt; + gd->fdt_blob, gd->new_fdt, fdt_size); + gd->fdt_blob = gd->new_fdt; } return 0; diff --git a/board/BuS/eb_cpu5282/u-boot.lds b/board/BuS/eb_cpu5282/u-boot.lds index 43bd9b7..c72043d 100644 --- a/board/BuS/eb_cpu5282/u-boot.lds +++ b/board/BuS/eb_cpu5282/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds index 3ff3871..2b76e92 100644 --- a/board/LEOX/elpt860/u-boot.lds +++ b/board/LEOX/elpt860/u-boot.lds @@ -112,6 +112,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/LEOX/elpt860/u-boot.lds.debug b/board/LEOX/elpt860/u-boot.lds.debug index 92901b1..592d9e3 100644 --- a/board/LEOX/elpt860/u-boot.lds.debug +++ b/board/LEOX/elpt860/u-boot.lds.debug @@ -134,6 +134,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/Marvell/common/memory.c b/board/Marvell/common/memory.c index 7fd6355..1400604 100644 --- a/board/Marvell/common/memory.c +++ b/board/Marvell/common/memory.c @@ -383,7 +383,7 @@ unsigned int memoryGetDeviceWidth (DEVICE device) * OUTPUT: * None. * RETURN: -* False for invalid size, true otherwise. +* false for invalid size, true otherwise. * * CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!! * @@ -509,7 +509,7 @@ bool memoryMapBank (MEMORY_BANK bank, unsigned int bankBase, * None. * * RETURN: -* False for invalid size, true otherwise. +* false for invalid size, true otherwise. * * CAUTION: PCI_functions must be implemented later To_do !!!!!!!!!!!!!!!!! * @@ -624,7 +624,7 @@ bool memoryMapDeviceSpace (DEVICE device, unsigned int deviceBase, * None. * * RETURN: -* False for invalid size, true otherwise. +* false for invalid size, true otherwise. * *******************************************************************************/ bool memorySetPciWindow (PCI_MEM_WINDOW pciWindow, unsigned int pciWindowBase, @@ -885,7 +885,7 @@ void gtMemorySetInternalSramBaseAddr (unsigned int sramBaseAddress) * None. * * RETURN: -* False for invalid size, true otherwise. +* false for invalid size, true otherwise. * *******************************************************************************/ bool memorySetProtectRegion (MEMORY_PROTECT_WINDOW window, @@ -1380,7 +1380,7 @@ void MemoryEnableWindow (MEMORY_WINDOW window) * OUTPUT: * None. * RETURN: -* True for a closed window, false otherwise . +* true for a closed window, false otherwise . *******************************************************************************/ MEMORY_WINDOW_STATUS MemoryGetMemWindowStatus (MEMORY_WINDOW window) { diff --git a/board/Marvell/db64360/mpsc.c b/board/Marvell/db64360/mpsc.c index 7ad6ae8..9227e5c 100644 --- a/board/Marvell/db64360/mpsc.c +++ b/board/Marvell/db64360/mpsc.c @@ -966,7 +966,7 @@ static int galmpsc_set_snoop (int mpsc, int value) * None. * * RETURN: -* True for success, false otherwise. +* true for success, false otherwise. * *******************************************************************************/ diff --git a/board/Marvell/db64360/mv_eth.h b/board/Marvell/db64360/mv_eth.h index bd8e05d..d7de9d9 100644 --- a/board/Marvell/db64360/mv_eth.h +++ b/board/Marvell/db64360/mv_eth.h @@ -46,13 +46,6 @@ ************************************************************************** ************************************************************************** *************************************************************************/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ #ifndef MAX_SKB_FRAGS #define MAX_SKB_FRAGS 0 diff --git a/board/Marvell/db64460/mpsc.c b/board/Marvell/db64460/mpsc.c index 303a636..45e13b8 100644 --- a/board/Marvell/db64460/mpsc.c +++ b/board/Marvell/db64460/mpsc.c @@ -966,7 +966,7 @@ static int galmpsc_set_snoop (int mpsc, int value) * None. * * RETURN: -* True for success, false otherwise. +* true for success, false otherwise. * *******************************************************************************/ diff --git a/board/Marvell/db64460/mv_eth.h b/board/Marvell/db64460/mv_eth.h index af4e818..1107e95 100644 --- a/board/Marvell/db64460/mv_eth.h +++ b/board/Marvell/db64460/mv_eth.h @@ -47,13 +47,6 @@ ************************************************************************** ************************************************************************** *************************************************************************/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ #ifndef MAX_SKB_FRAGS #define MAX_SKB_FRAGS 0 diff --git a/board/Marvell/include/core.h b/board/Marvell/include/core.h index c413439..3119d0a 100644 --- a/board/Marvell/include/core.h +++ b/board/Marvell/include/core.h @@ -91,11 +91,6 @@ extern unsigned int INTERNAL_REG_BASE_ADDR; #define _1G 0x40000000 #define _2G 0x80000000 -#ifndef BOOL_WAS_DEFINED -#define BOOL_WAS_DEFINED -typedef enum _bool{false,true} bool; -#endif - /* Little to Big endian conversion macros */ #ifdef LE /* Little Endian */ diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds index c2ec827..3334a44 100644 --- a/board/RPXClassic/u-boot.lds +++ b/board/RPXClassic/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug index e88bd97..40f17e9 100644 --- a/board/RPXClassic/u-boot.lds.debug +++ b/board/RPXClassic/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds index c2ec827..3334a44 100644 --- a/board/RPXlite/u-boot.lds +++ b/board/RPXlite/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug index e88bd97..40f17e9 100644 --- a/board/RPXlite/u-boot.lds.debug +++ b/board/RPXlite/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds index c2ec827..3334a44 100644 --- a/board/RPXlite_dw/u-boot.lds +++ b/board/RPXlite_dw/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug index 88c410c..7b89b4f 100644 --- a/board/RPXlite_dw/u-boot.lds.debug +++ b/board/RPXlite_dw/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds index f9d2ec2..84bb763 100644 --- a/board/RRvision/u-boot.lds +++ b/board/RRvision/u-boot.lds @@ -98,6 +98,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/a3m071/README b/board/a3m071/README index 7698614..a0fe832 100644 --- a/board/a3m071/README +++ b/board/a3m071/README @@ -62,7 +62,7 @@ the following command: All this can be integrated into an environment command: => setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip2 addtty; \ - fdt addr 1800000;fdt boardsetup;erase fc060000 fc07ffff; \ + fdt addr 1800000;fdt boardsetup;fdt chosen;erase fc060000 fc07ffff; \ cp.b 1800000 fc060000 10000' => saveenv diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c index 89ced82..0f9f883 100644 --- a/board/a3m071/a3m071.c +++ b/board/a3m071/a3m071.c @@ -24,10 +24,15 @@ #include <mpc5xxx.h> #include <pci.h> #include <miiphy.h> +#include <linux/compiler.h> #include <asm/processor.h> #include <asm/io.h> +#ifdef CONFIG_A4M2K +#include "is46r16320d.h" +#else #include "mt46v16m16-75.h" +#endif DECLARE_GLOBAL_DATA_PTR; @@ -63,6 +68,12 @@ static void sdram_start(int hi_addr) /* normal operation */ out_be32((void *)MPC5XXX_SDRAM_CTRL, control); + + /* + * Wait a short while for the DLL to lock before accessing + * the SDRAM + */ + udelay(100); } #endif @@ -157,12 +168,6 @@ static void get_revisions(int *failsavelevel, int *digiboardversion, struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; u8 val; - /* - * Figure out failsavelevel - * see ticket dsvk#59 - */ - *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */ - /* read digitalboard-version from TMR[2..4] */ val = 0; val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0; @@ -170,6 +175,17 @@ static void get_revisions(int *failsavelevel, int *digiboardversion, val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0; *digiboardversion = val; + /* + * A4M2K only supports digiboardversion. No failsavelevel and + * fpgaversion here. + */ +#if !defined(CONFIG_A4M2K) + /* + * Figure out failsavelevel + * see ticket dsvk#59 + */ + *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */ + if (*digiboardversion == 0) { *failsavelevel = 1; /* digiboard-version ok */ @@ -183,6 +199,7 @@ static void get_revisions(int *failsavelevel, int *digiboardversion, if (*fpgaversion == 1) *failsavelevel = 2; /* fpga-version ok */ } +#endif } /* @@ -196,6 +213,11 @@ void spl_board_init(void) struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; struct mpc5xxx_mmap_ctl *mm = (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; + +#if defined(CONFIG_A4M2K) + /* enable CS3 and CS5 (FPGA) */ + setbits_be32(&mm->ipbi_ws_ctrl, (1 << 19) | (1 << 21)); +#else int digiboardversion; int failsavelevel; int fpgaversion; @@ -219,6 +241,7 @@ void spl_board_init(void) /* And write new value back to register */ out_be32(&mm->ipbi_ws_ctrl, val); +#endif /* * No need to change the pin multiplexing (MPC5XXX_GPS_PORT_CONFIG) @@ -232,8 +255,57 @@ void spl_board_init(void) * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT) * set bit 0(msb) to 1 */ - setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, 1 << (31 - 0)); + setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_WDOG_GPIO_PIN); + +#if defined(CONFIG_A4M2K) + /* Setup USB[x] as MPCDiag[0..3] GPIO outputs */ + + /* set USB0,6,7,8 (MPCDiag[0..3]) direction to output */ + gpio->simple_ddr |= 1 << (31 - 15); + gpio->simple_ddr |= 1 << (31 - 14); + gpio->simple_ddr |= 1 << (31 - 13); + gpio->simple_ddr |= 1 << (31 - 12); + + /* enable USB0,6,7,8 (MPCDiag[0..3]) as GPIO */ + gpio->simple_gpioe |= 1 << (31 - 15); + gpio->simple_gpioe |= 1 << (31 - 14); + gpio->simple_gpioe |= 1 << (31 - 13); + gpio->simple_gpioe |= 1 << (31 - 12); + + /* Setup PSC2[0..2] as STSLED[0..2] GPIO outputs */ + + /* set PSC2[0..2] (STSLED[0..2]) direction to output */ + gpio->simple_ddr |= 1 << (31 - 27); + gpio->simple_ddr |= 1 << (31 - 26); + gpio->simple_ddr |= 1 << (31 - 25); + + /* enable PSC2[0..2] (STSLED[0..2]) as GPIO */ + gpio->simple_gpioe |= 1 << (31 - 27); + gpio->simple_gpioe |= 1 << (31 - 26); + gpio->simple_gpioe |= 1 << (31 - 25); + + /* Setup PSC6[2] as MRST2 self reset GPIO output */ + + /* set PSC6[2]/IRDA_TX (MRST2) direction to output */ + gpio->simple_ddr |= 1 << (31 - 3); + + /* set PSC6[2]/IRDA_TX (MRST2) output as open drain */ + gpio->simple_ode |= 1 << (31 - 3); + /* set PSC6[2]/IRDA_TX (MRST2) output as default high */ + gpio->simple_dvo |= 1 << (31 - 3); + + /* enable PSC6[2]/IRDA_TX (MRST2) as GPIO */ + gpio->simple_gpioe |= 1 << (31 - 3); + + /* Setup PSC6[3] as HARNSSCD harness code GPIO input */ + + /* set PSC6[3]/IR_USB_CLK (HARNSSCD) direction to input */ + gpio->simple_ddr |= 0 << (31 - 2); + + /* enable PSC6[3]/IR_USB_CLK (HARNSSCD) as GPIO */ + gpio->simple_gpioe |= 1 << (31 - 2); +#else /* setup GPIOs for status-leds if needed - see ticket #57 */ if (failsavelevel > 0) { /* digiboard-version is OK */ @@ -267,7 +339,7 @@ void spl_board_init(void) * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above */ } - +#endif } int checkboard(void) @@ -278,11 +350,16 @@ int checkboard(void) get_revisions(&failsavelevel, &digiboardversion, &fpgaversion); +#ifdef CONFIG_A4M2K + puts("Board: A4M2K\n"); + printf(" digiboard IO version %u\n", digiboardversion); +#else puts("Board: A3M071\n"); printf("Rev: failsave level %u\n", failsavelevel); printf(" digiboard IO version %u\n", digiboardversion); if (failsavelevel > 0) /* only if fpga-version red */ printf(" fpga IO version %u\n", fpgaversion); +#endif return 0; } @@ -333,3 +410,57 @@ int spl_start_uboot(void) return 1; } #endif + +#if defined(CONFIG_HW_WATCHDOG) +static int watchdog_toggle; + +void hw_watchdog_reset(void) +{ + int val; + + /* + * Check if watchdog is enabled via user command + */ + if ((gd->flags & GD_FLG_RELOC) && watchdog_toggle) { + /* Set direction to output */ + setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_WDOG_GPIO_PIN); + + /* + * Toggle watchdog output + */ + val = (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) & + CONFIG_WDOG_GPIO_PIN); + if (val) { + clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, + CONFIG_WDOG_GPIO_PIN); + } else { + setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, + CONFIG_WDOG_GPIO_PIN); + } + } +} + +int do_wdog_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc != 2) + goto usage; + + if (strncmp(argv[1], "on", 2) == 0) + watchdog_toggle = 1; + else if (strncmp(argv[1], "off", 3) == 0) + watchdog_toggle = 0; + else + goto usage; + + return 0; +usage: + printf("Usage: wdogtoggle %s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + wdogtoggle, CONFIG_SYS_MAXARGS, 2, do_wdog_toggle, + "toggle GPIO pin to service watchdog", + "[on/off] - Switch watchdog toggling via GPIO pin on/off" +); +#endif diff --git a/arch/arm/cpu/arm1176/s3c64xx/init.c b/board/a3m071/is46r16320d.h index f113d8e..8183d81 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/init.c +++ b/board/a3m071/is46r16320d.h @@ -1,6 +1,6 @@ /* - * (C) Copyright 2012 Ashok Kumar Reddy Kourla - * ashokkourla2000@gmail.com + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. * * See file CREDITS for list of people who contributed to this * project. @@ -16,11 +16,20 @@ * GNU General Public License for more details. */ -#include<common.h> +#define SDRAM_DDR /* is DDR */ -int arch_cpu_init(void) -{ - icache_enable(); +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +/* see is46r16320d datasheet and MPC5200UM chap. 8.6.1. */ - return 0; -} +/* SDRAM Config Standard timing */ +#define SDRAM_MODE 0x008d0000 +#define SDRAM_EMODE 0x40010000 +#define SDRAM_CONTROL 0x70430f00 +#define SDRAM_CONFIG1 0x33622930 +#define SDRAM_CONFIG2 0x46670000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index 7cf5b46..ef4a25b 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -61,6 +61,9 @@ SECTIONS } . = ALIGN (4); + + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) @@ -74,17 +77,23 @@ SECTIONS _end = .; +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + .bss_start __rel_dyn_start (OVERLAY) : { KEEP(*(.__bss_start)); + __bss_base = .; } - .bss __bss_start (OVERLAY) : { + .bss __bss_base (OVERLAY) : { *(.bss*) . = ALIGN(4); - ___bssend___ = .; + __bss_limit = .; } - .bss_end ___bssend___ (OVERLAY) : { - KEEP(*(.__bss_end__)); + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); } /DISCARD/ : { *(.dynstr*) } diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index e9b5547..00ad8b7 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -61,6 +61,9 @@ SECTIONS } . = ALIGN (4); + + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) @@ -74,17 +77,23 @@ SECTIONS _end = .; +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + .bss_start __rel_dyn_start (OVERLAY) : { KEEP(*(.__bss_start)); + __bss_base = .; } - .bss __bss_start (OVERLAY) : { + .bss __bss_base (OVERLAY) : { *(.bss*) . = ALIGN(4); - ___bssend___ = .; + __bss_limit = .; } - .bss_end ___bssend___ (OVERLAY) : { - KEEP(*(.__bss_end__)); + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); } /DISCARD/ : { *(.dynstr*) } diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index b79ea3c..44b990e 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -61,6 +61,9 @@ SECTIONS } . = ALIGN (4); + + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) @@ -74,17 +77,23 @@ SECTIONS _end = .; +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + .bss_start __rel_dyn_start (OVERLAY) : { KEEP(*(.__bss_start)); + __bss_base = .; } - .bss __bss_start (OVERLAY) : { + .bss __bss_base (OVERLAY) : { *(.bss*) . = ALIGN(4); - ___bssend___ = .; + __bss_limit = .; } - .bss_end ___bssend___ (OVERLAY) : { - KEEP(*(.__bss_end__)); + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); } /DISCARD/ : { *(.dynstr*) } diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds index 5e0ed00..def2f1f 100644 --- a/board/adder/u-boot.lds +++ b/board/adder/u-boot.lds @@ -89,7 +89,7 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } ENTRY(_start) diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c index 32b28f9..644c445 100644 --- a/board/ait/cam_enc_4xx/cam_enc_4xx.c +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -561,7 +561,8 @@ static char *menu_handle(struct menu_display *display) char *s; char temp[6][200]; - m = menu_create(display->title, display->timeout, 1, ait_menu_print); + m = menu_create(display->title, display->timeout, 1, ait_menu_print, + NULL, NULL); for (i = 0; display->menulist[i]; i++) { sprintf(key, "%d", i + 1); diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds index 52c986e..be1027d 100644 --- a/board/ait/cam_enc_4xx/u-boot-spl.lds +++ b/board/ait/cam_enc_4xx/u-boot-spl.lds @@ -38,7 +38,7 @@ SECTIONS .text : { __start = .; - arch/arm/cpu/arm926ejs/start.o (.text) + arch/arm/cpu/arm926ejs/start.o (.text*) *(.text*) } >.sram @@ -65,7 +65,7 @@ SECTIONS __bss_start = .; *(.bss*) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } >.sram __image_copy_end = .; diff --git a/board/altera/nios2-generic/u-boot.lds b/board/altera/nios2-generic/u-boot.lds index 900fe65..f309598 100644 --- a/board/altera/nios2-generic/u-boot.lds +++ b/board/altera/nios2-generic/u-boot.lds @@ -102,7 +102,7 @@ SECTIONS *(.scommon) } . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; PROVIDE (end = .); /* DEBUG -- symbol table, string table, etc. etc. diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds index 3861b67..e9f026f 100644 --- a/board/amcc/acadia/u-boot-nand.lds +++ b/board/amcc/acadia/u-boot-nand.lds @@ -98,6 +98,6 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 79788a8..6f5d0a6 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -477,16 +477,16 @@ int is_powerpc440ep_pass1(void) pvr = get_pvr(); if (pvr == PVR_POWERPC_440EP_PASS1) - return TRUE; + return true; else if (pvr == PVR_POWERPC_440EP_PASS2) - return FALSE; + return false; else { printf("brdutil error 3\n"); for (;;) ; } - return(FALSE); + return false; } /*----------------------------------------------------------------------------+ @@ -495,9 +495,9 @@ int is_powerpc440ep_pass1(void) int is_nand_selected(void) { #ifdef CONFIG_BAMBOO_NAND - return TRUE; + return true; #else - return FALSE; + return false; #endif } @@ -507,7 +507,7 @@ int is_nand_selected(void) unsigned char config_on_ebc_cs4_is_small_flash(void) { /* Not implemented yet => returns constant value */ - return TRUE; + return true; } /*----------------------------------------------------------------------------+ @@ -561,7 +561,7 @@ void ext_bus_cntlr_init(void) /*-------------------------------------------------------------------------+ | PPC440EP Pass1 +-------------------------------------------------------------------------*/ - if (is_powerpc440ep_pass1() == TRUE) { + if (is_powerpc440ep_pass1() == true) { switch(bootstrap_settings) { case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */ @@ -738,7 +738,7 @@ void ext_bus_cntlr_init(void) /*------------------------------------------------------------------------- */ ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH; ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0; - if ((is_nand_selected()) == TRUE) { + if ((is_nand_selected()) == true) { /* NAND Flash */ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; @@ -765,7 +765,7 @@ void ext_bus_cntlr_init(void) /*------------------------------------------------------------------------- */ ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM; ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0; - if ((is_nand_selected()) == TRUE) { + if ((is_nand_selected()) == true) { /* NAND Flash */ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; @@ -812,7 +812,7 @@ void ext_bus_cntlr_init(void) ebc0_cs0_bnap_value = 0; ebc0_cs0_bncr_value = 0; - if ((is_nand_selected()) == TRUE) { + if ((is_nand_selected()) == true) { /* NAND Flash */ ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH; ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1; @@ -830,7 +830,7 @@ void ext_bus_cntlr_init(void) ebc0_cs3_bncr_value = 0; } - if ((config_on_ebc_cs4_is_small_flash()) == TRUE) { + if ((config_on_ebc_cs4_is_small_flash()) == true) { /* Small Flash */ ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH; ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4; diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h index f2b78a9..6c49733 100644 --- a/board/amcc/bamboo/bamboo.h +++ b/board/amcc/bamboo/bamboo.h @@ -250,9 +250,6 @@ #define PVR_POWERPC_440EP_PASS1 0x42221850 #define PVR_POWERPC_440EP_PASS2 0x422218D3 -#define TRUE 1 -#define FALSE 0 - #define GPIO0 0 #define GPIO1 1 diff --git a/board/amcc/bamboo/u-boot-nand.lds b/board/amcc/bamboo/u-boot-nand.lds index 6308d49..209f484 100644 --- a/board/amcc/bamboo/u-boot-nand.lds +++ b/board/amcc/bamboo/u-boot-nand.lds @@ -99,6 +99,6 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds index 5fc9062..3d61613 100644 --- a/board/amcc/canyonlands/u-boot-nand.lds +++ b/board/amcc/canyonlands/u-boot-nand.lds @@ -99,6 +99,6 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/amcc/kilauea/u-boot-nand.lds b/board/amcc/kilauea/u-boot-nand.lds index 3861b67..e9f026f 100644 --- a/board/amcc/kilauea/u-boot-nand.lds +++ b/board/amcc/kilauea/u-boot-nand.lds @@ -98,6 +98,6 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds index b4600de..2ea3944 100644 --- a/board/amcc/sequoia/u-boot-nand.lds +++ b/board/amcc/sequoia/u-boot-nand.lds @@ -99,6 +99,6 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/amcc/sequoia/u-boot-ram.lds b/board/amcc/sequoia/u-boot-ram.lds index 521d12a..1b537f6 100644 --- a/board/amcc/sequoia/u-boot-ram.lds +++ b/board/amcc/sequoia/u-boot-ram.lds @@ -90,6 +90,6 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 1fab794..f606d92 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -47,9 +47,6 @@ void fpga_init (void); #define DEBUGF(fmt,args...) #endif -#define FALSE 0 -#define TRUE 1 - int board_early_init_f (void) { /*----------------------------------------------------------------------------+ diff --git a/board/astro/mcf5373l/u-boot.lds b/board/astro/mcf5373l/u-boot.lds index 5ee8fcc..264e43f 100644 --- a/board/astro/mcf5373l/u-boot.lds +++ b/board/astro/mcf5373l/u-boot.lds @@ -97,6 +97,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/bf533-ezkit/flash-defines.h b/board/bf533-ezkit/flash-defines.h index eb0af94..f073c0c 100644 --- a/board/bf533-ezkit/flash-defines.h +++ b/board/bf533-ezkit/flash-defines.h @@ -32,8 +32,6 @@ #define V_ULONG(a) (*(volatile unsigned long *)( a )) #define V_BYTE(a) (*(volatile unsigned char *)( a )) -#define TRUE 0x1 -#define FALSE 0x0 #define BUFFER_SIZE 0x80000 #define NO_COMMAND 0 #define GET_CODES 1 diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c index ab808d8..e4fcd1e 100644 --- a/board/bf533-ezkit/flash.c +++ b/board/bf533-ezkit/flash.c @@ -309,7 +309,7 @@ int read_flash(long nOffset, int *pnValue) nValue = *(volatile unsigned short *)addr; SSYNC(); *pnValue = nValue; - return TRUE; + return true; } int poll_toggle_bit(long lOffset) @@ -398,7 +398,7 @@ int erase_block_flash(int nBlock, unsigned long address) long ulSectorOff = 0x0; if ((nBlock < 0) || (nBlock > AFP_NumSectors)) - return FALSE; + return false; ulSectorOff = (address - CONFIG_SYS_FLASH_BASE); diff --git a/board/bf533-stamp/video.h b/board/bf533-stamp/video.h index 80837e2..949c3d8 100644 --- a/board/bf533-stamp/video.h +++ b/board/bf533-stamp/video.h @@ -9,9 +9,6 @@ #define YELLOW (0xD292D210) /* yellow pixel pattern */ #define WHITE (0xFE80FE80) /* white pixel pattern */ -#define true 1 -#define false 0 - typedef struct { unsigned int sav; unsigned int eav; diff --git a/board/chromebook-x86/dts/link.dts b/board/chromebook-x86/dts/link.dts index ae8217d..d0738cb 100644 --- a/board/chromebook-x86/dts/link.dts +++ b/board/chromebook-x86/dts/link.dts @@ -21,4 +21,15 @@ chosen { }; memory { device_type = "memory"; reg = <0 0>; }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich9"; + spi-flash@0 { + reg = <0>; + compatible = "winbond,w25q64", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + }; + }; }; diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c index 5522bf0..0faf197 100644 --- a/board/cm4008/flash.c +++ b/board/cm4008/flash.c @@ -29,6 +29,7 @@ #include <common.h> #include <linux/byteorder/swab.h> +#include <asm/sections.h> flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c index 5522bf0..0faf197 100644 --- a/board/cm41xx/flash.c +++ b/board/cm41xx/flash.c @@ -29,6 +29,7 @@ #include <common.h> #include <linux/byteorder/swab.h> +#include <asm/sections.h> flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index e0e8235..84c36ba 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -34,7 +34,9 @@ #include <i2c.h> #include <usb.h> #include <mmc.h> +#include <nand.h> #include <twl4030.h> +#include <bmp_layout.h> #include <linux/compiler.h> #include <asm/io.h> @@ -76,6 +78,67 @@ static u32 gpmc_nand_config[GPMC_MAX_REG] = { 0, }; +#ifdef CONFIG_LCD +#ifdef CONFIG_CMD_NAND +static int splash_load_from_nand(u32 bmp_load_addr) +{ + struct bmp_header *bmp_hdr; + int res, splash_screen_nand_offset = 0x100000; + size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); + + if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) + goto splash_address_too_high; + + res = nand_read_skip_bad(&nand_info[nand_curr_device], + splash_screen_nand_offset, &bmp_header_size, + NULL, nand_info[nand_curr_device].size, + (u_char *)bmp_load_addr); + if (res < 0) + return res; + + bmp_hdr = (struct bmp_header *)bmp_load_addr; + bmp_size = le32_to_cpu(bmp_hdr->file_size); + + if (bmp_load_addr + bmp_size >= gd->start_addr_sp) + goto splash_address_too_high; + + return nand_read_skip_bad(&nand_info[nand_curr_device], + splash_screen_nand_offset, &bmp_size, + NULL, nand_info[nand_curr_device].size, + (u_char *)bmp_load_addr); + +splash_address_too_high: + printf("Error: splashimage address too high. Data overwrites U-Boot " + "and/or placed beyond DRAM boundaries.\n"); + + return -1; +} +#else +static inline int splash_load_from_nand(void) +{ + return -1; +} +#endif /* CONFIG_CMD_NAND */ + +int board_splash_screen_prepare(void) +{ + char *env_splashimage_value; + u32 bmp_load_addr; + + env_splashimage_value = getenv("splashimage"); + if (env_splashimage_value == NULL) + return -1; + + bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); + if (bmp_load_addr == 0) { + printf("Error: bad splashimage address specified\n"); + return -1; + } + + return splash_load_from_nand(bmp_load_addr); +} +#endif /* CONFIG_LCD */ + /* * Routine: board_init * Description: hardware init. diff --git a/board/cm_t35/display.c b/board/cm_t35/display.c index 2f78bad..a004ea1 100644 --- a/board/cm_t35/display.c +++ b/board/cm_t35/display.c @@ -381,14 +381,6 @@ static enum display_type env_parse_displaytype(char *displaytype) return NONE; } -int lcd_line_length; -int lcd_color_fg; -int lcd_color_bg; -void *lcd_base; -short console_col; -short console_row; -void *lcd_console_address; - void lcd_ctrl_init(void *lcdbase) { struct prcm *prcm = (struct prcm *)PRCM_BASE; diff --git a/board/cobra5272/u-boot.lds b/board/cobra5272/u-boot.lds index 7421eec..809a705 100644 --- a/board/cobra5272/u-boot.lds +++ b/board/cobra5272/u-boot.lds @@ -96,6 +96,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds index 357f59d..1f006d7 100644 --- a/board/cogent/u-boot.lds +++ b/board/cogent/u-boot.lds @@ -97,6 +97,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug index e88bd97..40f17e9 100644 --- a/board/cogent/u-boot.lds.debug +++ b/board/cogent/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug index 99cbed4..1b45e5e 100644 --- a/board/cray/L1/u-boot.lds.debug +++ b/board/cray/L1/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds index 987b52d..663100e 100644 --- a/board/dave/PPChameleonEVB/u-boot.lds +++ b/board/dave/PPChameleonEVB/u-boot.lds @@ -126,6 +126,6 @@ SECTIONS } :bss . = ALIGN(4); - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c index 31b079b..2290257 100644 --- a/board/davedenx/aria/aria.c +++ b/board/davedenx/aria/aria.c @@ -35,70 +35,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* Clocks in use */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PATA_EN | \ - CLOCK_SCCR1_PCI_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN | \ - CLOCK_SCCR2_DIU_EN | \ - CLOCK_SCCR2_I2C_EN) - -int board_early_init_f(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 spridr; - - /* - * Initialize Local Window for the On Board FPGA access - */ - out_be32(&im->sysconf.lpcs2aw, - CSAW_START(CONFIG_SYS_ARIA_FPGA_BASE) | - CSAW_STOP(CONFIG_SYS_ARIA_FPGA_BASE, CONFIG_SYS_ARIA_FPGA_SIZE) - ); - out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); - sync_law(&im->sysconf.lpcs2aw); - - /* - * Initialize Local Window for the On Board SRAM access - */ - out_be32(&im->sysconf.lpcs6aw, - CSAW_START(CONFIG_SYS_ARIA_SRAM_BASE) | - CSAW_STOP(CONFIG_SYS_ARIA_SRAM_BASE, CONFIG_SYS_ARIA_SRAM_SIZE) - ); - out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG); - sync_law(&im->sysconf.lpcs6aw); - - /* - * Configure Flash Speed - */ - out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); - - spridr = in_be32(&im->sysconf.spridr); - - if (SVR_MJREV(spridr) >= 2) - out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); - - /* - * Enable clocks - */ - out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN); - out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN); -#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) - setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); -#endif - - return 0; -} - phys_size_t initdram (int board_type) { return fixed_sdram(NULL, NULL, 0); diff --git a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds index dd5f266..2ae5a2c 100644 --- a/board/davinci/da8xxevm/u-boot-spl-da850evm.lds +++ b/board/davinci/da8xxevm/u-boot-spl-da850evm.lds @@ -38,7 +38,7 @@ SECTIONS .text : { __start = .; - arch/arm/cpu/arm926ejs/start.o (.text) + arch/arm/cpu/arm926ejs/start.o (.text*) *(.text*) } >.sram @@ -66,7 +66,7 @@ SECTIONS __bss_start = .; *(.bss*) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } >.sram __image_copy_end = .; diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds index b3a41af..596a9e0 100644 --- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds +++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds @@ -34,15 +34,15 @@ SECTIONS . = ALIGN(4); .text : { - arch/arm/cpu/arm926ejs/start.o (.text) - arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text) - drivers/mtd/nand/libnand.o (.text) + arch/arm/cpu/arm926ejs/start.o (.text*) + arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text*) + drivers/mtd/nand/libnand.o (.text*) *(.text*) } . = ALIGN(4); - .rodata : { *(.rodata) } + .rodata : { *(.rodata*) } . = ALIGN(4); .data : { @@ -58,6 +58,7 @@ SECTIONS } . = ALIGN(4); + __image_copy_end = .; __rel_dyn_start = .; __rel_dyn_end = .; __dynsym_start = .; @@ -74,7 +75,7 @@ SECTIONS __bss_start = .; *(.bss*) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } _end = .; diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds index eb83b6f..6d4b187 100644 --- a/board/dvlhost/u-boot.lds +++ b/board/dvlhost/u-boot.lds @@ -61,6 +61,9 @@ SECTIONS } . = ALIGN (4); + + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) @@ -74,17 +77,23 @@ SECTIONS _end = .; +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + .bss_start __rel_dyn_start (OVERLAY) : { KEEP(*(.__bss_start)); + __bss_base = .; } - .bss __bss_start (OVERLAY) : { + .bss __bss_base (OVERLAY) : { *(.bss*) . = ALIGN(4); - ___bssend___ = .; + __bss_limit = .; } - .bss_end ___bssend___ (OVERLAY) : { - KEEP(*(.__bss_end__)); + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); } /DISCARD/ : { *(.dynstr*) } diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds index bd74d74..a1481c8 100644 --- a/board/eltec/mhpc/u-boot.lds +++ b/board/eltec/mhpc/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug index 614bbb2..a33b0a6 100644 --- a/board/eltec/mhpc/u-boot.lds.debug +++ b/board/eltec/mhpc/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds index ea04eca..e3f7d80 100644 --- a/board/emk/top860/u-boot.lds +++ b/board/emk/top860/u-boot.lds @@ -94,6 +94,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/emk/top860/u-boot.lds.debug b/board/emk/top860/u-boot.lds.debug index 39807d4..704e8c9 100644 --- a/board/emk/top860/u-boot.lds.debug +++ b/board/emk/top860/u-boot.lds.debug @@ -126,6 +126,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds index e5fa63e..c00b3c3 100644 --- a/board/ep88x/u-boot.lds +++ b/board/ep88x/u-boot.lds @@ -89,7 +89,7 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } ENTRY(_start) diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c index 3dfbf3b..1a5f656 100644 --- a/board/esd/common/lcd.c +++ b/board/esd/common/lcd.c @@ -260,7 +260,7 @@ int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * Big epson detected */ - reg_byte_swap = FALSE; + reg_byte_swap = false; palette_index = 0x1e2; palette_value = 0x1e4; lcd_depth = 16; @@ -269,7 +269,7 @@ int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * Big epson detected (with register swap bug) */ - reg_byte_swap = TRUE; + reg_byte_swap = true; palette_index = 0x1e3; palette_value = 0x1e5; lcd_depth = 16; @@ -278,7 +278,7 @@ int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * Small epson detected (704) */ - reg_byte_swap = FALSE; + reg_byte_swap = false; palette_index = 0x15; palette_value = 0x17; lcd_depth = 8; @@ -287,7 +287,7 @@ int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * Small epson detected (705) */ - reg_byte_swap = FALSE; + reg_byte_swap = false; palette_index = 0x15; palette_value = 0x17; lcd_depth = 8; @@ -300,7 +300,7 @@ int lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count, /* * S1D13505 detected */ - reg_byte_swap = TRUE; + reg_byte_swap = true; palette_index = 0x25; palette_value = 0x27; lcd_depth = 16; diff --git a/board/esd/common/lcd.h b/board/esd/common/lcd.h index 01f6019..5c48b5a 100644 --- a/board/esd/common/lcd.h +++ b/board/esd/common/lcd.h @@ -35,11 +35,6 @@ #define LOAD_LONG(data) SWAP_LONG(data) #define LOAD_SHORT(data) SWAP_SHORT(data) -#ifndef FALSE -#define FALSE 0 -#define TRUE (!FALSE) -#endif - #define S1D_WRITE_PALETTE(p,i,r,g,b) \ { \ out_8(&((uchar*)(p))[palette_index], (uchar)(i)); \ diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c index c89426d..4adcec0 100644 --- a/board/esd/cpci750/mpsc.c +++ b/board/esd/cpci750/mpsc.c @@ -967,7 +967,7 @@ static int galmpsc_set_snoop (int mpsc, int value) * None. * * RETURN: -* True for success, false otherwise. +* true for success, false otherwise. * *******************************************************************************/ diff --git a/board/esd/cpci750/mv_eth.h b/board/esd/cpci750/mv_eth.h index 3d0cb10..94745bc 100644 --- a/board/esd/cpci750/mv_eth.h +++ b/board/esd/cpci750/mv_eth.h @@ -47,13 +47,6 @@ ************************************************************************** ************************************************************************** *************************************************************************/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ #ifndef MAX_SKB_FRAGS #define MAX_SKB_FRAGS 0 diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c index 0014808..ccea715 100644 --- a/board/esd/dasa_sim/cmd_dasa_sim.c +++ b/board/esd/dasa_sim/cmd_dasa_sim.c @@ -30,10 +30,6 @@ #define OK 0 #define ERROR (-1) -#define TRUE 1 -#define FALSE 0 - - extern u_long pci9054_iobase; @@ -97,7 +93,7 @@ static int PciEepromWriteLongVPD (int offs, unsigned int value) } } - return TRUE; + return true; } diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds index cca527f..4297b8b 100644 --- a/board/esd/dasa_sim/u-boot.lds +++ b/board/esd/dasa_sim/u-boot.lds @@ -100,6 +100,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c index 748ad7c..e38678f 100644 --- a/board/esd/mecp5123/mecp5123.c +++ b/board/esd/mecp5123/mecp5123.c @@ -33,20 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* Clocks in use */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PCI_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_I2C_EN) - int eeprom_write_enable(unsigned dev_addr, int state) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; @@ -65,18 +51,9 @@ int eeprom_write_enable(unsigned dev_addr, int state) int board_early_init_f(void) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - u32 spridr; int i; /* - * Initialize Local Window for NOR FLASH access - */ - out_be32(&im->sysconf.lpcs0aw, - CSAW_START(CONFIG_SYS_FLASH_BASE) | - CSAW_STOP(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE)); - sync_law(&im->sysconf.lpcs0aw); - - /* * Initialize Local Window for boot access */ out_be32(&im->sysconf.lpbaw, @@ -84,37 +61,6 @@ int board_early_init_f(void) sync_law(&im->sysconf.lpbaw); /* - * Initialize Local Window for VPC3 access - */ - out_be32(&im->sysconf.lpcs1aw, - CSAW_START(CONFIG_SYS_VPC3_BASE) | - CSAW_STOP(CONFIG_SYS_VPC3_BASE, CONFIG_SYS_VPC3_SIZE)); - sync_law(&im->sysconf.lpcs1aw); - - /* - * Configure Flash Speed - */ - out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); - - /* - * Configure VPC3 Speed - */ - out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG); - - spridr = in_be32(&im->sysconf.spridr); - if (SVR_MJREV(spridr) >= 2) - out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); - - /* - * Enable clocks - */ - out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN); - out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN); -#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) - setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); -#endif - - /* * Configure MSCAN clocks */ for (i=0; i<4; ++i) { diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c index f92bbff..d38cc96 100644 --- a/board/esd/pmc440/fpga.c +++ b/board/esd/pmc440/fpga.c @@ -113,7 +113,7 @@ void fpga_serialslave_init(void) { debug("%s:%d: Initialize serial slave interface\n", __FUNCTION__, __LINE__); - fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */ + fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */ } @@ -188,7 +188,7 @@ int fpga_done_fn(int cookie) int fpga_pre_config_fn(int cookie) { debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); - fpga_reset(TRUE); + fpga_reset(true); /* release init# */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT); @@ -213,9 +213,9 @@ int fpga_post_config_fn(int cookie) /* enable PLD0..7 pins */ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N); - fpga_reset(TRUE); + fpga_reset(true); udelay (100); - fpga_reset(FALSE); + fpga_reset(false); udelay (100); FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK); @@ -296,7 +296,7 @@ void ngcc_fpga_serialslave_init(void) __FUNCTION__, __LINE__); /* make sure program pin is inactive */ - ngcc_fpga_pgm_fn (FALSE, FALSE, 0); + ngcc_fpga_pgm_fn(false, false, 0); } /* @@ -382,10 +382,10 @@ int ngcc_fpga_pre_config_fn(int cookie) pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); - ngcc_fpga_reset(TRUE); + ngcc_fpga_reset(true); FPGA_CLRBITS(&fpga->ctrla, 0xfffffe00); - ngcc_fpga_reset(TRUE); + ngcc_fpga_reset(true); return 0; } @@ -401,7 +401,7 @@ int ngcc_fpga_post_config_fn(int cookie) debug("%s:%d: NGCC FPGA post configuration\n", __FUNCTION__, __LINE__); udelay (100); - ngcc_fpga_reset(FALSE); + ngcc_fpga_reset(false); FPGA_SETBITS(&fpga->ctrla, 0x29f8c000); diff --git a/board/esd/pmc440/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds index 4469b80..6a5cef6 100644 --- a/board/esd/pmc440/u-boot-nand.lds +++ b/board/esd/pmc440/u-boot-nand.lds @@ -129,6 +129,6 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/esd/tasreg/u-boot.lds b/board/esd/tasreg/u-boot.lds index 7642bba..a4d9da7 100644 --- a/board/esd/tasreg/u-boot.lds +++ b/board/esd/tasreg/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds index 357a794..642f1c9 100644 --- a/board/esteem192e/u-boot.lds +++ b/board/esteem192e/u-boot.lds @@ -101,6 +101,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/evb64260/eth_addrtbl.c b/board/evb64260/eth_addrtbl.c index e8ef0e3..8c2c17f 100644 --- a/board/evb64260/eth_addrtbl.c +++ b/board/evb64260/eth_addrtbl.c @@ -6,9 +6,6 @@ #include "eth.h" #include "eth_addrtbl.h" -#define TRUE 1 -#define FALSE 0 - #define PRINTF printf #ifdef CONFIG_GT_USE_MAC_HASH_TABLE @@ -160,8 +157,8 @@ u32 hashTableFunction (u32 macH, u32 macL, u32 HashSize, u32 hash_mode) * rd - the RD field in the address table. * Outputs * address table entry is added. - * TRUE if success. - * FALSE if table full + * true if success. + * false if table full */ int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip) { @@ -206,7 +203,7 @@ int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip) if (i == HOP_NUMBER) { PRINTF ("addGT64260addressTableEntry: table section is full\n"); - return (FALSE); + return false; } /* @@ -215,7 +212,7 @@ int addAddressTableEntry (u32 port, u32 macH, u32 macL, u32 rd, u32 skip) entry->hi = newHi; entry->lo = newLo; DCACHE_FLUSH_N_SYNC ((u32) entry, MAC_ENTRY_SIZE); - return (TRUE); + return true; } #endif /* CONFIG_GT_USE_MAC_HASH_TABLE */ diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds index e2cfcfe..44c61eb 100644 --- a/board/evb64260/u-boot.lds +++ b/board/evb64260/u-boot.lds @@ -97,6 +97,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds index 450103d..0e2206c 100644 --- a/board/fads/u-boot.lds +++ b/board/fads/u-boot.lds @@ -95,7 +95,7 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } ENTRY(_start) diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds index bd74d74..a1481c8 100644 --- a/board/flagadm/u-boot.lds +++ b/board/flagadm/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug index 614bbb2..a33b0a6 100644 --- a/board/flagadm/u-boot.lds.debug +++ b/board/flagadm/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m5208evbe/u-boot.lds b/board/freescale/m5208evbe/u-boot.lds index f3c9ed8..6f80e41 100644 --- a/board/freescale/m5208evbe/u-boot.lds +++ b/board/freescale/m5208evbe/u-boot.lds @@ -97,6 +97,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds index ae0a48d..9db171e 100644 --- a/board/freescale/m52277evb/u-boot.lds +++ b/board/freescale/m52277evb/u-boot.lds @@ -96,6 +96,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m5235evb/u-boot.lds b/board/freescale/m5235evb/u-boot.lds index 603858b..f11d483 100644 --- a/board/freescale/m5235evb/u-boot.lds +++ b/board/freescale/m5235evb/u-boot.lds @@ -96,6 +96,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m5249evb/u-boot.lds b/board/freescale/m5249evb/u-boot.lds index 7421eec..809a705 100644 --- a/board/freescale/m5249evb/u-boot.lds +++ b/board/freescale/m5249evb/u-boot.lds @@ -96,6 +96,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m5253demo/u-boot.lds b/board/freescale/m5253demo/u-boot.lds index 6838247..9de8885 100644 --- a/board/freescale/m5253demo/u-boot.lds +++ b/board/freescale/m5253demo/u-boot.lds @@ -97,6 +97,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m5253evbe/u-boot.lds b/board/freescale/m5253evbe/u-boot.lds index 7421eec..809a705 100644 --- a/board/freescale/m5253evbe/u-boot.lds +++ b/board/freescale/m5253evbe/u-boot.lds @@ -96,6 +96,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m5271evb/u-boot.lds b/board/freescale/m5271evb/u-boot.lds index e222e80..82b67d5 100644 --- a/board/freescale/m5271evb/u-boot.lds +++ b/board/freescale/m5271evb/u-boot.lds @@ -96,6 +96,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m5272c3/u-boot.lds b/board/freescale/m5272c3/u-boot.lds index 7421eec..809a705 100644 --- a/board/freescale/m5272c3/u-boot.lds +++ b/board/freescale/m5272c3/u-boot.lds @@ -96,6 +96,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m5275evb/u-boot.lds b/board/freescale/m5275evb/u-boot.lds index c18758a..fda4cf4 100644 --- a/board/freescale/m5275evb/u-boot.lds +++ b/board/freescale/m5275evb/u-boot.lds @@ -96,6 +96,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m5282evb/u-boot.lds b/board/freescale/m5282evb/u-boot.lds index 20f6c47..cdfd0e4 100644 --- a/board/freescale/m5282evb/u-boot.lds +++ b/board/freescale/m5282evb/u-boot.lds @@ -96,6 +96,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds index 15dfa7d..c40c565 100644 --- a/board/freescale/m53017evb/u-boot.lds +++ b/board/freescale/m53017evb/u-boot.lds @@ -99,6 +99,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m5329evb/u-boot.lds b/board/freescale/m5329evb/u-boot.lds index 5013ff4..f803e4a 100644 --- a/board/freescale/m5329evb/u-boot.lds +++ b/board/freescale/m5329evb/u-boot.lds @@ -97,6 +97,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m5373evb/u-boot.lds b/board/freescale/m5373evb/u-boot.lds index 5ee8fcc..264e43f 100644 --- a/board/freescale/m5373evb/u-boot.lds +++ b/board/freescale/m5373evb/u-boot.lds @@ -97,6 +97,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m54418twr/u-boot.lds b/board/freescale/m54418twr/u-boot.lds index 2df386b..3247dbf 100644 --- a/board/freescale/m54418twr/u-boot.lds +++ b/board/freescale/m54418twr/u-boot.lds @@ -94,6 +94,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m54451evb/u-boot.lds b/board/freescale/m54451evb/u-boot.lds index 4440d61..fd1289e 100644 --- a/board/freescale/m54451evb/u-boot.lds +++ b/board/freescale/m54451evb/u-boot.lds @@ -94,6 +94,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m54455evb/u-boot.lds b/board/freescale/m54455evb/u-boot.lds index 2df386b..3247dbf 100644 --- a/board/freescale/m54455evb/u-boot.lds +++ b/board/freescale/m54455evb/u-boot.lds @@ -94,6 +94,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m547xevb/u-boot.lds b/board/freescale/m547xevb/u-boot.lds index 269bf8a..bbe36f0 100644 --- a/board/freescale/m547xevb/u-boot.lds +++ b/board/freescale/m547xevb/u-boot.lds @@ -94,6 +94,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/m548xevb/u-boot.lds b/board/freescale/m548xevb/u-boot.lds index 68bdad4..9315927 100644 --- a/board/freescale/m548xevb/u-boot.lds +++ b/board/freescale/m548xevb/u-boot.lds @@ -94,6 +94,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 97eeab3..33a8aa5 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -38,25 +38,6 @@ DECLARE_GLOBAL_DATA_PTR; -/* Clocks in use */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PATA_EN | \ - CLOCK_SCCR1_PCI_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \ - CLOCK_SCCR2_I2C_EN | \ - CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN | \ - CLOCK_SCCR2_USB1_EN | \ - CLOCK_SCCR2_USB2_EN) - void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip); /* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */ @@ -83,20 +64,6 @@ void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip) int board_early_init_f(void) { - volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; - u32 spridr; - - /* - * Initialize Local Window for the CPLD registers access (CS2 selects - * the CPLD chip) - */ - out_be32(&im->sysconf.lpcs2aw, - CSAW_START(CONFIG_SYS_CPLD_BASE) | - CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE) - ); - out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); - sync_law(&im->sysconf.lpcs2aw); - /* * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control * @@ -114,25 +81,6 @@ int board_early_init_f(void) out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32); } #endif - /* - * Configure Flash Speed - */ - out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); - - spridr = in_be32(&im->sysconf.spridr); - - if (SVR_MJREV (spridr) >= 2) - out_be32 (&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); - - /* - * Enable clocks - */ - out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN); - out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN); -#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) - setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); -#endif - return 0; } diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index 2d08fea..4969960 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -37,23 +37,23 @@ SECTIONS /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - arch/arm/cpu/arm1136/start.o (.text) - board/freescale/mx31ads/libmx31ads.o (.text) - arch/arm/lib/libarm.o (.text) - net/libnet.o (.text) - drivers/mtd/libmtd.o (.text) + arch/arm/cpu/arm1136/start.o (.text*) + board/freescale/mx31ads/libmx31ads.o (.text*) + arch/arm/lib/libarm.o (.text*) + net/libnet.o (.text*) + drivers/mtd/libmtd.o (.text*) . = DEFINED(env_offset) ? env_offset : .; - common/env_embedded.o(.text) + common/env_embedded.o(.text*) - *(.text) + *(.text*) } . = ALIGN(4); - .rodata : { *(.rodata) } + .rodata : { *(.rodata*) } . = ALIGN(4); .data : { - *(.data) + *(.data*) } . = ALIGN(4); @@ -80,17 +80,23 @@ SECTIONS _end = .; +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + .bss_start __rel_dyn_start (OVERLAY) : { KEEP(*(.__bss_start)); + __bss_base = .; } - .bss __bss_start (OVERLAY) : { + .bss __bss_base (OVERLAY) : { *(.bss*) . = ALIGN(4); - ___bssend___ = .; + __bss_limit = .; } - .bss_end ___bssend___ (OVERLAY) : { - KEEP(*(.__bss_end__)); + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); } /DISCARD/ : { *(.bss*) } diff --git a/board/freescale/mx31pdk/Makefile b/board/freescale/mx31pdk/Makefile index 5b7cafd..b910722 100644 --- a/board/freescale/mx31pdk/Makefile +++ b/board/freescale/mx31pdk/Makefile @@ -27,6 +27,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +ifdef CONFIG_SPL_BUILD +SOBJS := lowlevel_init.o +endif COBJS := mx31pdk.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/freescale/mx31pdk/config.mk b/board/freescale/mx31pdk/config.mk deleted file mode 100644 index de2c642..0000000 --- a/board/freescale/mx31pdk/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -ifdef CONFIG_NAND_SPL -CONFIG_SYS_TEXT_BASE = 0x87ec0000 -else -CONFIG_SYS_TEXT_BASE = 0x87f00000 -endif diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 895396c..49158bd 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -36,6 +36,14 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong bootflag) +{ + relocate_code(CONFIG_SPL_TEXT_BASE); + asm volatile("ldr pc, =nand_boot"); +} +#endif + int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index 2fc8570..8d433a3 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -58,6 +58,71 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; } +#ifdef CONFIG_NAND_MXC +static void setup_iomux_nand(void) +{ + u32 i, reg; + #define M4IF_GENP_WEIM_MM_MASK 0x00000001 + #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 + + reg = __raw_readl(M4IF_BASE_ADDR + 0xc); + reg &= ~M4IF_GENP_WEIM_MM_MASK; + __raw_writel(reg, M4IF_BASE_ADDR + 0xc); + for (i = 0x4; i < 0x94; i += 0x18) { + reg = __raw_readl(WEIM_BASE_ADDR + i); + reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK; + __raw_writel(reg, WEIM_BASE_ADDR + i); + } + + mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU); + mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU); + mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA0, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA1, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA2, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA3, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA4, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA5, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA6, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX53_PIN_EIM_DA7, PAD_CTL_PKE_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH); +} +#else +static void setup_iomux_nand(void) +{ +} +#endif + static void setup_iomux_uart(void) { /* UART1 RXD */ @@ -277,6 +342,7 @@ static void weim_cs1_settings(void) int board_early_init_f(void) { + setup_iomux_nand(); setup_iomux_uart(); return 0; } diff --git a/board/gaisler/gr_cpci_ax2000/u-boot.lds b/board/gaisler/gr_cpci_ax2000/u-boot.lds index dac87db..60039cc 100644 --- a/board/gaisler/gr_cpci_ax2000/u-boot.lds +++ b/board/gaisler/gr_cpci_ax2000/u-boot.lds @@ -134,7 +134,7 @@ SECTIONS . = ALIGN(16); /* to speed clearing of bss up */ } __bss_end = . ; - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); /* Relocated into main memory */ diff --git a/board/gaisler/gr_ep2s60/u-boot.lds b/board/gaisler/gr_ep2s60/u-boot.lds index 78e0e2d..ec73f73 100644 --- a/board/gaisler/gr_ep2s60/u-boot.lds +++ b/board/gaisler/gr_ep2s60/u-boot.lds @@ -134,7 +134,7 @@ SECTIONS . = ALIGN(16); /* to speed clearing of bss up */ } __bss_end = . ; - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); /* Relocated into main memory */ diff --git a/board/gaisler/gr_xc3s_1500/u-boot.lds b/board/gaisler/gr_xc3s_1500/u-boot.lds index 87ea473..18dfb81 100644 --- a/board/gaisler/gr_xc3s_1500/u-boot.lds +++ b/board/gaisler/gr_xc3s_1500/u-boot.lds @@ -135,7 +135,7 @@ SECTIONS . = ALIGN(16); /* to speed clearing of bss up */ } __bss_end = . ; - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); /* Relocated into main memory */ diff --git a/board/gaisler/grsim/u-boot.lds b/board/gaisler/grsim/u-boot.lds index e854a16..8de272e 100644 --- a/board/gaisler/grsim/u-boot.lds +++ b/board/gaisler/grsim/u-boot.lds @@ -134,7 +134,7 @@ SECTIONS . = ALIGN(16); /* to speed clearing of bss up */ } __bss_end = . ; - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); /* Relocated into main memory */ diff --git a/board/gaisler/grsim_leon2/u-boot.lds b/board/gaisler/grsim_leon2/u-boot.lds index f247e56..e57f734 100644 --- a/board/gaisler/grsim_leon2/u-boot.lds +++ b/board/gaisler/grsim_leon2/u-boot.lds @@ -133,7 +133,7 @@ SECTIONS . = ALIGN(16); /* to speed clearing of bss up */ } __bss_end = . ; - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); /* Relocated into main memory */ diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c index d42c500..4c36009 100644 --- a/board/gen860t/fpga.c +++ b/board/gen860t/fpga.c @@ -182,7 +182,7 @@ void fpga_selectmap_init (void) { PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__, __LINE__); - fpga_pgm_fn (FALSE, FALSE, 0); /* make sure program pin is inactive */ + fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */ } @@ -314,7 +314,7 @@ int fpga_abort_fn (int cookie) int fpga_pre_config_fn (int cookie) { PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); - fpga_reset (TRUE); + fpga_reset(true); return 0; } @@ -328,9 +328,9 @@ int fpga_post_config_fn (int cookie) int rc; PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__); - fpga_reset (TRUE); + fpga_reset(true); udelay (1000); - fpga_reset (FALSE); + fpga_reset(false); udelay (1000); /* diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds index b061441..30138dd 100644 --- a/board/gen860t/u-boot-flashenv.lds +++ b/board/gen860t/u-boot-flashenv.lds @@ -97,7 +97,7 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); .ppcenv: diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds index 9e9449d..08fb4aa 100644 --- a/board/gen860t/u-boot.lds +++ b/board/gen860t/u-boot.lds @@ -98,6 +98,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds index 958dd84..b351a68 100644 --- a/board/genietv/u-boot.lds +++ b/board/genietv/u-boot.lds @@ -112,6 +112,6 @@ SECTIONS common/env_embedded.o (.ppcenv) } . = ALIGN(4); - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug index a3aeb60..cc86941 100644 --- a/board/genietv/u-boot.lds.debug +++ b/board/genietv/u-boot.lds.debug @@ -138,6 +138,6 @@ SECTIONS { common/env_embedded.o (.ppcenv) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds index b2bb50d..8e58963 100644 --- a/board/hermes/u-boot.lds +++ b/board/hermes/u-boot.lds @@ -99,6 +99,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug index 4383c49..982b0f3 100644 --- a/board/hermes/u-boot.lds.debug +++ b/board/hermes/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds index 3133c55..5d1c2ad 100644 --- a/board/hymod/u-boot.lds +++ b/board/hymod/u-boot.lds @@ -143,6 +143,6 @@ SECTIONS common/env_embedded.o (.ppcenv) } . = ALIGN(4); - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug index e88bd97..40f17e9 100644 --- a/board/hymod/u-boot.lds.debug +++ b/board/hymod/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds index 40f4a38..6e4939b 100644 --- a/board/icu862/u-boot.lds +++ b/board/icu862/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug index 9995288..d5220cc 100644 --- a/board/icu862/u-boot.lds.debug +++ b/board/icu862/u-boot.lds.debug @@ -133,6 +133,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/idmr/u-boot.lds b/board/idmr/u-boot.lds index 6d13831..5b8d3b3 100644 --- a/board/idmr/u-boot.lds +++ b/board/idmr/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS . = ALIGN(4); _ebss = .; } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/ifm/ac14xx/Makefile b/board/ifm/ac14xx/Makefile new file mode 100644 index 0000000..9a76f32 --- /dev/null +++ b/board/ifm/ac14xx/Makefile @@ -0,0 +1,34 @@ +# +# (C) Copyright 2009 Wolfgang Denk <wd@denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y := $(BOARD).o + +COBJS := $(COBJS-y) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ifm/ac14xx/ac14xx.c b/board/ifm/ac14xx/ac14xx.c new file mode 100644 index 0000000..7442591 --- /dev/null +++ b/board/ifm/ac14xx/ac14xx.c @@ -0,0 +1,617 @@ +/* + * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> + * (C) Copyright 2009 Dave Srl www.dave.eu + * (C) Copyright 2010 ifm ecomatic GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/bitops.h> +#include <command.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <asm/mpc512x.h> +#include <fdt_support.h> +#ifdef CONFIG_MISC_INIT_R +#include <i2c.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static void gpio_configure(void) +{ + immap_t *im; + gpio512x_t *gpioregs; + + im = (immap_t *) CONFIG_SYS_IMMR; + gpioregs = &im->gpio; + out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */ + out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */ + + /* + * out_be32(&gpioregs->gpdir, 0xC2293020); + * workaround for a hardware affect: configure direction in pieces, + * setting all outputs at once drops the reset line too low and + * makes us lose the MII connection (breaks ethernet for us) + */ + out_be32(&gpioregs->gpdir, 0x02003060); /* direction */ + setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */ + udelay(10); + setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */ + udelay(10); + setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */ + udelay(10); + setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */ + + /* to turn from red to yellow when U-Boot runs */ + setbits_be32(&gpioregs->gpdat, 0x00002020); + out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */ + out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */ + out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */ + out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */ +} + +/* the physical location of the pins */ +#define GPIOKEY_ROW_BITMASK 0x40000000 +#define GPIOKEY_ROW_UPPER 0 +#define GPIOKEY_ROW_LOWER 1 + +#define GPIOKEY_COL0_BITMASK 0x20000000 +#define GPIOKEY_COL1_BITMASK 0x10000000 +#define GPIOKEY_COL2_BITMASK 0x08000000 + +/* the logical presentation of pressed keys */ +#define GPIOKEY_BIT_FNLEFT (1 << 5) +#define GPIOKEY_BIT_FNRIGHT (1 << 4) +#define GPIOKEY_BIT_DIRUP (1 << 3) +#define GPIOKEY_BIT_DIRLEFT (1 << 2) +#define GPIOKEY_BIT_DIRRIGHT (1 << 1) +#define GPIOKEY_BIT_DIRDOWN (1 << 0) + +/* the hotkey combination which starts recovery */ +#define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \ + GPIOKEY_BIT_DIRDOWN) + +static void gpio_selectrow(gpio512x_t *gpioregs, u32 row) +{ + + if (row) + setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK); + else + clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK); + udelay(10); +} + +static u32 gpio_querykbd(void) +{ + immap_t *im; + gpio512x_t *gpioregs; + u32 keybits; + u32 input; + + im = (immap_t *)CONFIG_SYS_IMMR; + gpioregs = &im->gpio; + keybits = 0; + + /* query upper row */ + gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER); + input = in_be32(&gpioregs->gpdat); + if ((input & GPIOKEY_COL0_BITMASK) == 0) + keybits |= GPIOKEY_BIT_FNLEFT; + if ((input & GPIOKEY_COL1_BITMASK) == 0) + keybits |= GPIOKEY_BIT_DIRUP; + if ((input & GPIOKEY_COL2_BITMASK) == 0) + keybits |= GPIOKEY_BIT_FNRIGHT; + + /* query lower row */ + gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER); + input = in_be32(&gpioregs->gpdat); + if ((input & GPIOKEY_COL0_BITMASK) == 0) + keybits |= GPIOKEY_BIT_DIRLEFT; + if ((input & GPIOKEY_COL1_BITMASK) == 0) + keybits |= GPIOKEY_BIT_DIRRIGHT; + if ((input & GPIOKEY_COL2_BITMASK) == 0) + keybits |= GPIOKEY_BIT_DIRDOWN; + + /* return bit pattern for keys */ + return keybits; +} + +/* excerpt from the recovery's hw_info.h */ + +static int eeprom_diag = 1; + +struct __attribute__ ((__packed__)) eeprom_layout { + char magic[3]; /** 'ifm' */ + u8 len[2]; /** content length without magic/len fields */ + u8 version[3]; /** structure version */ + u8 type; /** type of PCB */ + u8 reserved[0x37]; /** padding up to offset 0x40 */ + u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */ +}; + +#define HW_COMP_MAINCPU 2 + +static struct eeprom_layout eeprom_content; +static int eeprom_was_read; /* has_been_read */ +static int eeprom_is_valid; +static int eeprom_version; + +#define get_eeprom_field_int(name) ({ \ + int value; \ + int idx; \ + value = 0; \ + for (idx = 0; idx < sizeof(name); idx++) { \ + value <<= 8; \ + value |= name[idx]; \ + } \ + value; \ +}) + +static int read_eeprom(void) +{ + int eeprom_datalen; + int ret; + + if (eeprom_was_read) + return 0; + + eeprom_is_valid = 0; + ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + (uchar *)&eeprom_content, sizeof(eeprom_content)); + if (eeprom_diag) { + printf("DIAG: %s() read rc[%d], size[%d]\n", + __func__, ret, sizeof(eeprom_content)); + } + + if (ret != 0) + return -1; + + eeprom_was_read = 1; + + /* + * check validity of EEPROM content + * (check version, length, optionally checksum) + */ + eeprom_is_valid = 1; + eeprom_datalen = get_eeprom_field_int(eeprom_content.len); + eeprom_version = get_eeprom_field_int(eeprom_content.version); + + if (eeprom_diag) { + printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n", + __func__, eeprom_content.magic[0], + eeprom_content.magic[1], eeprom_content.magic[2], + eeprom_datalen, eeprom_version, eeprom_content.type); + } + if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0) + eeprom_is_valid = 0; + if (eeprom_datalen < sizeof(struct eeprom_layout) - 5) + eeprom_is_valid = 0; + if ((eeprom_version != 1) && (eeprom_version != 2)) + eeprom_is_valid = 0; + if (eeprom_content.type != HW_COMP_MAINCPU) + eeprom_is_valid = 0; + + if (eeprom_diag) + printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid); + + return ret; +} + +int mac_read_from_eeprom(void) +{ + const u8 *mac; + + if (read_eeprom()) { + printf("I2C EEPROM read failed.\n"); + return -1; + } + + if (!eeprom_is_valid) { + printf("I2C EEPROM content not valid\n"); + return -1; + } + + mac = NULL; + switch (eeprom_version) { + case 1: + case 2: + mac = (const u8 *)&eeprom_content.macaddress; + break; + } + + if (mac && is_valid_ether_addr(mac)) { + eth_setenv_enetaddr("ethaddr", mac); + printf("DIAG: %s() MAC value [%s]\n", + __func__, getenv("ethaddr")); + } + + return 0; +} + +/* + * BEWARE! + * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2 + * which the ADS, Aria or PDM360NG boards are using + * (the steps outlined here refer to the Micron datasheet) + */ +u32 sdram_init_seq[] = { + /* item 6, at least one NOP after CKE went high */ + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + /* item 7, precharge all; item 8, tRP (20ns) */ + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_NOP, + /* item 9, extended mode register; item 10, tMRD 10ns) */ + CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM, + CONFIG_SYS_DDRCMD_NOP, + /* + * item 11, (base) mode register _with_ reset DLL; + * item 12, tMRD (10ns) + */ + CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL | + CONFIG_SYS_MICRON_BMODE_PARAM, + CONFIG_SYS_DDRCMD_NOP, + /* item 13, precharge all; item 14, tRP (20ns) */ + CONFIG_SYS_DDRCMD_PCHG_ALL, + CONFIG_SYS_DDRCMD_NOP, + /* + * item 15, auto refresh (i.e. refresh with CKE held high); + * item 16, tRFC (70ns) + */ + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + /* + * item 17, auto refresh (i.e. refresh with CKE held high); + * item 18, tRFC (70ns) + */ + CONFIG_SYS_DDRCMD_RFSH, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + CONFIG_SYS_DDRCMD_NOP, + /* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */ + CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM, + CONFIG_SYS_DDRCMD_NOP, + /* + * item 21, "actually done", but make sure 200 DRAM clock cycles + * have passed after DLL reset before READ requests are issued + * (200 cycles at 160MHz -> 1.25 usec) + */ + /* EMPTY, optional, we don't do it */ +}; + +phys_size_t initdram(int board_type) +{ + return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq)); +} + +int misc_init_r(void) +{ + u32 keys; + char *s; + int want_recovery; + + /* we use bus I2C-0 for the on-board eeprom */ + i2c_set_bus_num(0); + + /* setup GPIO directions and initial values */ + gpio_configure(); + + /* + * check the GPIO keyboard, + * enforced start of the recovery when + * - the appropriate keys were pressed + * - a previous installation was aborted or has failed + * - "some" external software told us to + */ + want_recovery = 0; + keys = gpio_querykbd(); + printf("GPIO keyboard status [0x%08X]\n", keys); + /* XXX insist in the _exact_ combination? */ + if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) { + printf("GPIO keyboard requested RECOVERY\n"); + /* XXX TODO + * refine the logic to detect the first keypress, and + * wait to recheck IF it was the recovery combination? + */ + want_recovery = 1; + } + s = getenv("install_in_progress"); + if ((s != NULL) && (*s != '\0')) { + printf("previous installation aborted, running RECOVERY\n"); + want_recovery = 1; + } + s = getenv("install_failed"); + if ((s != NULL) && (*s != '\0')) { + printf("previous installation FAILED, running RECOVERY\n"); + want_recovery = 1; + } + s = getenv("want_recovery"); + if ((s != NULL) && (*s != '\0')) { + printf("running RECOVERY according to the request\n"); + want_recovery = 1; + } + + if (want_recovery) + setenv("bootcmd", "run recovery"); + + /* + * boot the recovery system without waiting; boot the + * production system without waiting by default, only + * insert a pause (to provide a chance to get a prompt) + * when GPIO keys were pressed during power on + */ + if (want_recovery) + setenv("bootdelay", "0"); + else if (!keys) + setenv("bootdelay", "0"); + else + setenv("bootdelay", "2"); + + /* get the ethernet MAC from I2C EEPROM */ + mac_read_from_eeprom(); + + return 0; +} + +/* setup specific IO pad configuration */ +static iopin_t ioregs_init[] = { + { /* LPC CS3 */ + offsetof(struct ioctrl512x, io_control_nfc_ce0), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + { /* LPC CS1 */ + offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* LPC CS2 */ + offsetof(struct ioctrl512x, io_control_lpc_cs2), 1, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* LPC CS4, CS5 */ + offsetof(struct ioctrl512x, io_control_pata_ce1), 2, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + { /* SDHC CLK, CMD, D0, D1, D2, D3 */ + offsetof(struct ioctrl512x, io_control_pata_ior), 6, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + { /* GPIO keyboard */ + offsetof(struct ioctrl512x, io_control_pci_ad30), 4, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO DN1 PF, LCD power, DN2 PF */ + offsetof(struct ioctrl512x, io_control_pci_ad26), 3, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO reset AS-i */ + offsetof(struct ioctrl512x, io_control_pci_ad21), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO reset safety */ + offsetof(struct ioctrl512x, io_control_pci_ad19), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO reset netX */ + offsetof(struct ioctrl512x, io_control_pci_ad16), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO ma2 en */ + offsetof(struct ioctrl512x, io_control_pci_ad15), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO SD CD, SD WP */ + offsetof(struct ioctrl512x, io_control_pci_ad08), 2, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* FEC RX DV */ + offsetof(struct ioctrl512x, io_control_pci_ad06), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(2), + }, + { /* GPIO AS-i prog, AS-i done, LCD backlight */ + offsetof(struct ioctrl512x, io_control_pci_ad05), 3, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO AS-i wdg */ + offsetof(struct ioctrl512x, io_control_pci_req2), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO safety wdg */ + offsetof(struct ioctrl512x, io_control_pci_req1), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO netX wdg */ + offsetof(struct ioctrl512x, io_control_pci_req0), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO IRQ powerfail */ + offsetof(struct ioctrl512x, io_control_pci_inta), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO AS-i PWRD */ + offsetof(struct ioctrl512x, io_control_pci_frame), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO LED0, LED1 */ + offsetof(struct ioctrl512x, io_control_pci_idsel), 2, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */ + offsetof(struct ioctrl512x, io_control_pci_irdy), 3, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* DIU clk */ + offsetof(struct ioctrl512x, io_control_spdif_txclk), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(2), + }, + { /* FEC TX ER, CRS */ + offsetof(struct ioctrl512x, io_control_spdif_tx), 2, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + { /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */ + offsetof(struct ioctrl512x, io_control_irq0), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + { /* + * FEC col, tx en, tx clk, txd 0-3, mdc, rx er, + * rdx 3-0, mdio, rx clk + */ + offsetof(struct ioctrl512x, io_control_psc0_0), 15, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + /* optional: make sure PSC3 remains the serial console */ + { /* LPC CS6 */ + offsetof(struct ioctrl512x, io_control_psc3_4), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + /* make sure PSC4 remains available for SPI, + *BUT* PSC4_1 is a GPIO kind of SS! */ + { /* enforce drive strength on the SPI pin */ + offsetof(struct ioctrl512x, io_control_psc4_0), 5, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { + offsetof(struct ioctrl512x, io_control_psc4_1), 1, + IO_PIN_OVER_FMUX, + IO_PIN_FMUX(3), + }, + /* optional: make sure PSC5 remains available for SPI */ + { /* enforce drive strength on the SPI pin */ + offsetof(struct ioctrl512x, io_control_psc5_0), 5, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(1), + }, + { /* LPC TSIZ1 */ + offsetof(struct ioctrl512x, io_control_psc6_0), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(1) | IO_PIN_DS(2), + }, + { /* DIU hsync */ + offsetof(struct ioctrl512x, io_control_psc6_1), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(1), + }, + { /* DIU vsync */ + offsetof(struct ioctrl512x, io_control_psc6_4), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(1), + }, + { /* PSC7, part of DIU RGB */ + offsetof(struct ioctrl512x, io_control_psc7_0), 2, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(1), + }, + { /* PSC7, safety UART */ + offsetof(struct ioctrl512x, io_control_psc7_2), 2, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(0) | IO_PIN_DS(1), + }, + { /* DIU (part of) RGB[] */ + offsetof(struct ioctrl512x, io_control_psc8_3), 16, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(1), + }, + { /* DIU data enable */ + offsetof(struct ioctrl512x, io_control_psc11_4), 1, + IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR, + IO_PIN_FMUX(2) | IO_PIN_DS(1), + }, + /* reduce LPB drive strength for improved EMI */ + { /* LPC OE, LPC RW */ + offsetof(struct ioctrl512x, io_control_lpc_oe), 2, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* LPC AX03 through LPC AD00 */ + offsetof(struct ioctrl512x, io_control_lpc_ax03), 36, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* LPC CS5 */ + offsetof(struct ioctrl512x, io_control_pata_ce2), 1, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* SDHC CLK */ + offsetof(struct ioctrl512x, io_control_nfc_wp), 1, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, + { /* SDHC DATA */ + offsetof(struct ioctrl512x, io_control_nfc_ale), 4, + IO_PIN_OVER_DRVSTR, + IO_PIN_DS(2), + }, +}; + +int checkboard(void) +{ + puts("Board: ifm AC14xx\n"); + + /* initialize function mux & slew rate IO inter alia on IO Pins */ + iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init)); + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds index c2ec827..3334a44 100644 --- a/board/ip860/u-boot.lds +++ b/board/ip860/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug index 0b34177..ecc9f26 100644 --- a/board/ip860/u-boot.lds.debug +++ b/board/ip860/u-boot.lds.debug @@ -133,6 +133,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 2bac916..0d4679d 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -24,7 +24,7 @@ #include <twl4030.h> #include <netdev.h> #include <asm/gpio.h> -#include <asm/arch/omap_gpmc.h> +#include <asm/omap_gpmc.h> #include <asm/io.h> #include <asm/arch/mem.h> #include <asm/arch/mmc_host_def.h> diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds index dcd53ec..1b43dbe 100644 --- a/board/ivm/u-boot.lds +++ b/board/ivm/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug index bae9fb2..62c66d7 100644 --- a/board/ivm/u-boot.lds.debug +++ b/board/ivm/u-boot.lds.debug @@ -133,6 +133,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/karo/tx25/Makefile b/board/karo/tx25/Makefile index 9617fa5..c26bf36 100644 --- a/board/karo/tx25/Makefile +++ b/board/karo/tx25/Makefile @@ -25,8 +25,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := tx25.o +ifdef CONFIG_SPL_BUILD SOBJS := lowlevel_init.o +endif +COBJS := tx25.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/karo/tx25/config.mk b/board/karo/tx25/config.mk deleted file mode 100644 index 18b2883..0000000 --- a/board/karo/tx25/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -ifdef CONFIG_NAND_SPL -CONFIG_SYS_TEXT_BASE = 0x810c0000 -else -CONFIG_SYS_TEXT_BASE = 0x81200000 -endif diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index 362f00a..85719a0 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -33,6 +33,14 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong bootflag) +{ + relocate_code(CONFIG_SPL_TEXT_BASE); + asm volatile("ldr pc, =nand_boot"); +} +#endif + #ifdef CONFIG_FEC_MXC #define GPIO_FEC_RESET_B IMX_GPIO_NR(4, 7) #define GPIO_FEC_ENABLE_B IMX_GPIO_NR(4, 9) diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c index defc885..f98844d 100644 --- a/board/keymile/km82xx/km82xx.c +++ b/board/keymile/km82xx/km82xx.c @@ -31,10 +31,7 @@ #include <libfdt.h> #endif -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) #include <i2c.h> -#endif - #include "../common/common.h" /* @@ -370,7 +367,7 @@ static void set_pin(int state, unsigned long mask); * will toggle once what forces the mgocge3un part to restart * immediately. */ -void handle_mgcoge3un_reset(void) +static void handle_mgcoge3un_reset(void) { char *bobcatreset = getenv("bobcatreset"); if (bobcatreset) { diff --git a/board/korat/u-boot-F7FC.lds b/board/korat/u-boot-F7FC.lds index b6fa79f..52c929c 100644 --- a/board/korat/u-boot-F7FC.lds +++ b/board/korat/u-boot-F7FC.lds @@ -135,6 +135,6 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds index c2ec827..3334a44 100644 --- a/board/kup/kup4k/u-boot.lds +++ b/board/kup/kup4k/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug index 88c410c..7b89b4f 100644 --- a/board/kup/kup4k/u-boot.lds.debug +++ b/board/kup/kup4k/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds index c2ec827..3334a44 100644 --- a/board/kup/kup4x/u-boot.lds +++ b/board/kup/kup4x/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug index 88c410c..7b89b4f 100644 --- a/board/kup/kup4x/u-boot.lds.debug +++ b/board/kup/kup4x/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds index 30523dc..ce11a91 100644 --- a/board/lwmon/u-boot.lds +++ b/board/lwmon/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug index 1d1b76a..cb5ed9c 100644 --- a/board/lwmon/u-boot.lds.debug +++ b/board/lwmon/u-boot.lds.debug @@ -133,6 +133,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/manroland/uc100/u-boot.lds b/board/manroland/uc100/u-boot.lds index 8c75dea..d1bb127 100644 --- a/board/manroland/uc100/u-boot.lds +++ b/board/manroland/uc100/u-boot.lds @@ -96,6 +96,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/matrix_vision/mvblx/mvblx.c b/board/matrix_vision/mvblx/mvblx.c index 49af384..3ea15a1 100644 --- a/board/matrix_vision/mvblx/mvblx.c +++ b/board/matrix_vision/mvblx/mvblx.c @@ -162,7 +162,7 @@ int board_eth_init(bd_t *bis) int overwrite_console(void) { - /* return TRUE if console should be overwritten */ + /* return true if console should be overwritten */ return 0; } diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds index 5707770..3225c0b 100644 --- a/board/matrix_vision/mvsmr/u-boot.lds +++ b/board/matrix_vision/mvsmr/u-boot.lds @@ -100,6 +100,6 @@ SECTIONS *(.sbss*) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds index c2ec827..3334a44 100644 --- a/board/mbx8xx/u-boot.lds +++ b/board/mbx8xx/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug index 063f2cc..1135117 100644 --- a/board/mbx8xx/u-boot.lds.debug +++ b/board/mbx8xx/u-boot.lds.debug @@ -133,6 +133,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/mcc200/lcd.c b/board/mcc200/lcd.c index 893f4b7..24f0abd 100644 --- a/board/mcc200/lcd.c +++ b/board/mcc200/lcd.c @@ -68,19 +68,6 @@ vidinfo_t panel_info = { LCD_WIDTH, LCD_HEIGHT, LCD_BPP }; -int lcd_line_length; - -int lcd_color_fg; -int lcd_color_bg; - -/* - * Frame buffer memory information - */ -void *lcd_base; /* Start of framebuffer memory */ -void *lcd_console_address; /* Start of console buffer */ - -short console_col = 0; -short console_row = 0; /* * The device we use to communicate with PSoC @@ -88,13 +75,6 @@ short console_row = 0; int serial_inited = 0; /* - * Exported functions - */ -void lcd_initcolregs (void); -void lcd_ctrl_init (void *lcdbase); -void lcd_enable (void); - -/* * Imported functions to support the PSoC protocol */ extern int serial_init_dev (unsigned long dev_base); @@ -156,12 +136,12 @@ void lcd_enable (void) #if !defined(SWAPPED_LCD) for (i=0; i<fb_size; i++) { - serial_putc_raw_dev (PSOC_PSC, ((char *)lcd_base)[i]); + serial_putc_raw_dev(PSOC_PSC, ((char *)gd->fb_base)[i]); } #else { int x, y, pwidth; - char *p = (char *)lcd_base; + char *p = (char *)gd->fb_base; pwidth = ((panel_info.vl_col+7) >> 3); for (y=0; y<panel_info.vl_row; y++) { diff --git a/board/mousse/flash.c b/board/mousse/flash.c index cc40535..5f60c8d 100644 --- a/board/mousse/flash.c +++ b/board/mousse/flash.c @@ -450,7 +450,7 @@ STATUS flashWrite (flash_dev_t * dev, int pos, char *buf, int len) } /* - * flashWritable returns TRUE if a range contains all F's. + * flashWritable returns true if a range contains all F's. */ STATUS flashWritable (flash_dev_t * dev, int pos, int len) diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds index 080829b..17ff94e 100644 --- a/board/mousse/u-boot.lds +++ b/board/mousse/u-boot.lds @@ -88,6 +88,6 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/mousse/u-boot.lds.ram b/board/mousse/u-boot.lds.ram index 5255651..2055429 100644 --- a/board/mousse/u-boot.lds.ram +++ b/board/mousse/u-boot.lds.ram @@ -96,6 +96,6 @@ SECTIONS common/env_embedded.o (.ppcenv) } > ram - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/mousse/u-boot.lds.rom b/board/mousse/u-boot.lds.rom index 29a34fb..3c7c544 100644 --- a/board/mousse/u-boot.lds.rom +++ b/board/mousse/u-boot.lds.rom @@ -123,6 +123,6 @@ SECTIONS *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/mpl/common/isa.c b/board/mpl/common/isa.c index fc56153..66724ed 100644 --- a/board/mpl/common/isa.c +++ b/board/mpl/common/isa.c @@ -41,13 +41,6 @@ #define PRINTF(fmt,args...) #endif -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - #if defined(CONFIG_PIP405) extern int drv_isa_kbd_init (void); @@ -116,9 +109,9 @@ unsigned char open_cfg_super_IO(int address) out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */ out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */ if(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */ - return TRUE; + return true; else - return FALSE; + return false; } void close_cfg_super_IO(int address) @@ -179,7 +172,7 @@ void isa_sio_loadtable(void) void isa_sio_setup(void) { - if(open_cfg_super_IO(SIO_CFG_PORT)==TRUE) + if (open_cfg_super_IO(SIO_CFG_PORT) == true) { isa_sio_loadtable(); close_cfg_super_IO(0x3F0); diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index 56a84e9..89ea276 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -77,8 +77,6 @@ DECLARE_GLOBAL_DATA_PTR; #undef SDRAM_DEBUG #define ENABLE_ECC /* for ecc boards */ -#define FALSE 0 -#define TRUE 1 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */ #ifndef __ldiv_t_defined @@ -771,7 +769,8 @@ int last_stage_init (void) int overwrite_console (void) { - return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */ + /* return true if console should be overwritten */ + return ((in8(PLD_EXT_CONF_REG) & 0x1) == 0); } diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index 75f57ad..b203037 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -36,9 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; #undef SDRAM_DEBUG -#define FALSE 0 -#define TRUE 1 - /* stdlib.h causes some compatibility problems; should fixe these! -- wd */ #ifndef __ldiv_t_defined typedef struct { @@ -700,7 +697,8 @@ int misc_init_r (void) int overwrite_console (void) { - return (in8 (CONFIG_PORT_ADDR) & 0x1); /* return TRUE if console should be overwritten */ + /* return true if console should be overwritten */ + return in8(CONFIG_PORT_ADDR) & 0x1; } @@ -945,7 +943,7 @@ void print_pip405_info (void) void user_led0 (unsigned char on) { - if (on == TRUE) + if (on == true) out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1)); else out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe)); @@ -953,7 +951,7 @@ void user_led0 (unsigned char on) void user_led1 (unsigned char on) { - if (on == TRUE) + if (on == true) out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2)); else out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd)); diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug index 99cbed4..1b45e5e 100644 --- a/board/mpl/pip405/u-boot.lds.debug +++ b/board/mpl/pip405/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds index e186ee6..adbb5f9 100644 --- a/board/mvblue/u-boot.lds +++ b/board/mvblue/u-boot.lds @@ -97,6 +97,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds index ddb5a72..03891e9 100644 --- a/board/netphone/u-boot.lds +++ b/board/netphone/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug index e1fe052..5f74337 100644 --- a/board/netphone/u-boot.lds.debug +++ b/board/netphone/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds index ddb5a72..03891e9 100644 --- a/board/netta/u-boot.lds +++ b/board/netta/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug index e1fe052..5f74337 100644 --- a/board/netta/u-boot.lds.debug +++ b/board/netta/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds index ddb5a72..03891e9 100644 --- a/board/netta2/u-boot.lds +++ b/board/netta2/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug index e1fe052..5f74337 100644 --- a/board/netta2/u-boot.lds.debug +++ b/board/netta2/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds index ddb5a72..03891e9 100644 --- a/board/netvia/u-boot.lds +++ b/board/netvia/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug index 3243fc0..2fb5897 100644 --- a/board/netvia/u-boot.lds.debug +++ b/board/netvia/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 7d9f361..8d7a227 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -132,10 +132,7 @@ int board_init(void) clock_init(); clock_verify(); -#ifdef CONFIG_SPI_UART_SWITCH - gpio_config_uart(); -#endif -#if defined(CONFIG_TEGRA_SPI) || defined(CONFIG_TEGRA_SLINK) +#ifdef CONFIG_FDT_SPI pin_mux_spi(); spi_init(); #endif diff --git a/board/nvidia/common/common.mk b/board/nvidia/common/common.mk index bd6202c..d9bcb85 100644 --- a/board/nvidia/common/common.mk +++ b/board/nvidia/common/common.mk @@ -1,4 +1,3 @@ # common options for all tegra boards COBJS-y += ../../nvidia/common/board.o -COBJS-$(CONFIG_SPI_UART_SWITCH) += ../../nvidia/common/uart-spi-switch.o COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += ../../nvidia/common/emc.o diff --git a/board/nvidia/common/uart-spi-switch.c b/board/nvidia/common/uart-spi-switch.c deleted file mode 100644 index e9d445d..0000000 --- a/board/nvidia/common/uart-spi-switch.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/gpio.h> -#include <asm/arch/pinmux.h> -#include <asm/arch/uart-spi-switch.h> -#include <asm/arch/tegra.h> -#include <asm/arch-tegra/tegra_spi.h> -#include <asm/arch-tegra/board.h> - -/* position of the UART/SPI select switch */ -enum spi_uart_switch { - SWITCH_UNKNOWN, - SWITCH_SPI, - SWITCH_UART, - SWITCH_BOTH -}; - -/* Information about the spi/uart switch */ -struct spi_uart { - int gpio; /* GPIO to control switch */ - u32 port; /* Port number of UART affected */ -}; - -static struct spi_uart local; -static enum spi_uart_switch switch_pos; /* Current switch position */ - - -static void get_config(struct spi_uart *config) -{ -#if defined CONFIG_SPI_CORRUPTS_UART - config->gpio = CONFIG_UART_DISABLE_GPIO; - config->port = CONFIG_SPI_CORRUPTS_UART_NR; -#else - config->gpio = -1; -#endif -} - -/* - * Init the UART / SPI switch. This can be called before relocation so we must - * not access BSS. - */ -void gpio_early_init_uart(void) -{ - struct spi_uart config; - - get_config(&config); - if (config.gpio != -1) { - /* Cannot provide a label prior to relocation */ - gpio_request(config.gpio, NULL); - gpio_direction_output(config.gpio, 0); - } -} - -/* - * Configure the UART / SPI switch. - */ -void gpio_config_uart(void) -{ - get_config(&local); - if (local.gpio != -1) { - gpio_direction_output(local.gpio, 0); - switch_pos = SWITCH_UART; - } else { - /* - * If we're here we don't have a SPI switch; go ahead and - * enable the SPI now. We didn't in spi_init() so we wouldn't - * kill the UART. - */ - pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); - switch_pos = SWITCH_BOTH; - } -} - -static void spi_uart_switch(struct spi_uart *config, - enum spi_uart_switch new_pos) -{ - if (switch_pos == SWITCH_BOTH || new_pos == switch_pos) - return; - - /* pre-delay, allow SPI/UART to settle, FIFO to empty, etc. */ - udelay(CONFIG_SPI_CORRUPTS_UART_DLY); - - /* We need to dynamically change the pinmux, shared w/UART RXD/CTS */ - pinmux_set_func(PINGRP_GMC, new_pos == SWITCH_SPI ? - PMUX_FUNC_SFLASH : PMUX_FUNC_UARTD); - - /* - * On Seaboard, MOSI/MISO are shared w/UART. - * Use GPIO I3 (UART_DISABLE) to tristate UART during SPI activity. - * Enable UART later (cs_deactivate) so we can use it for U-Boot comms. - */ - gpio_direction_output(config->gpio, new_pos == SWITCH_SPI); - switch_pos = new_pos; -} - -void pinmux_select_uart(void) -{ - spi_uart_switch(&local, SWITCH_UART); -} - -void pinmux_select_spi(void) -{ - spi_uart_switch(&local, SWITCH_SPI); -} diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index 2020a5f..2c23a29 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -16,7 +16,12 @@ #include <common.h> #include <asm/arch/pinmux.h> +#include <asm/arch/gp_padctrl.h> #include "pinmux-config-dalmore.h" +#include <i2c.h> + +#define BAT_I2C_ADDRESS 0x48 /* TPS65090 charger */ +#define PMU_I2C_ADDRESS 0x58 /* TPS65913 PMU */ /* * Routine: pinmux_init @@ -32,4 +37,65 @@ void pinmux_init(void) pinmux_config_table(unused_pins_lowpower, ARRAY_SIZE(unused_pins_lowpower)); + + /* Initialize any non-default pad configs (APB_MISC_GP regs) */ + padgrp_config_table(dalmore_padctrl, ARRAY_SIZE(dalmore_padctrl)); +} + +#if defined(CONFIG_TEGRA_MMC) +/* + * Do I2C/PMU writes to bring up SD card bus power + * + */ +void board_sdmmc_voltage_init(void) +{ + uchar reg, data_buffer[1]; + int ret; + + ret = i2c_set_bus_num(0);/* PMU is on bus 0 */ + if (ret) + printf("%s: i2c_set_bus_num returned %d\n", __func__, ret); + + /* TPS65913: LDO9_VOLTAGE = 3.3V */ + data_buffer[0] = 0x31; + reg = 0x61; + + ret = i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1); + if (ret) + printf("%s: PMU i2c_write %02X<-%02X returned %d\n", + __func__, reg, data_buffer[0], ret); + + /* TPS65913: LDO9_CTRL = Active */ + data_buffer[0] = 0x01; + reg = 0x60; + + ret = i2c_write(PMU_I2C_ADDRESS, reg, 1, data_buffer, 1); + if (ret) + printf("%s: PMU i2c_write %02X<-%02X returned %d\n", + __func__, reg, data_buffer[0], ret); + + /* TPS65090: FET6_CTRL = enable output auto discharge, enable FET6 */ + data_buffer[0] = 0x03; + reg = 0x14; + + ret = i2c_write(BAT_I2C_ADDRESS, reg, 1, data_buffer, 1); + if (ret) + printf("%s: BAT i2c_write %02X<-%02X returned %d\n", + __func__, reg, data_buffer[0], ret); +} + +/* + * Routine: pin_mux_mmc + * Description: setup the MMC muxes, power rails, etc. + */ +void pin_mux_mmc(void) +{ + /* + * NOTE: We don't do mmc-specific pin muxes here. + * They were done globally in pinmux_init(). + */ + + /* Bring up the SDIO3 power rail */ + board_sdmmc_voltage_init(); } +#endif /* MMC */ diff --git a/board/nvidia/dalmore/pinmux-config-dalmore.h b/board/nvidia/dalmore/pinmux-config-dalmore.h index 3ef6f4e..8c05a15 100644 --- a/board/nvidia/dalmore/pinmux-config-dalmore.h +++ b/board/nvidia/dalmore/pinmux-config-dalmore.h @@ -361,4 +361,10 @@ static struct pingroup_config tegra114_pinmux_set_nontristate[] = { DEFAULT_PINMUX(SDMMC3_CD_N, SDMMC3, UP, NORMAL, INPUT), }; + +static struct padctrl_config dalmore_padctrl[] = { + /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ + DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, \ + SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE), +}; #endif /* PINMUX_CONFIG_COMMON_H */ diff --git a/board/nvidia/dts/tegra114-dalmore.dts b/board/nvidia/dts/tegra114-dalmore.dts index 30cf1fb..86e9459 100644 --- a/board/nvidia/dts/tegra114-dalmore.dts +++ b/board/nvidia/dts/tegra114-dalmore.dts @@ -12,6 +12,8 @@ i2c2 = "/i2c@7000c400"; i2c3 = "/i2c@7000c500"; i2c4 = "/i2c@7000c700"; + sdhci0 = "/sdhci@78000600"; + sdhci1 = "/sdhci@78000400"; }; memory { @@ -43,4 +45,20 @@ status = "okay"; clock-frequency = <400000>; }; + + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + + sdhci@78000400 { + cd-gpios = <&gpio 170 1>; /* gpio PV2 */ + bus-width = <4>; + status = "okay"; + }; + + sdhci@78000600 { + bus-width = <8>; + status = "okay"; + }; }; diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index e581fdd..498e513 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -31,7 +31,7 @@ #include <asm/gpio.h> /* TODO: Remove this code when the SPI switch is working */ -#if !defined(CONFIG_SPI_UART_SWITCH) && (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA) +#if (CONFIG_MACH_TYPE != MACH_TYPE_VENTANA) void gpio_early_init_uart(void) { /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds index bd74d74..a1481c8 100644 --- a/board/nx823/u-boot.lds +++ b/board/nx823/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug index 614bbb2..a33b0a6 100644 --- a/board/nx823/u-boot.lds.debug +++ b/board/nx823/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/overo/overo.c b/board/overo/overo.c index 8690450..c10c44c 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -37,7 +37,7 @@ #include <asm/arch/mux.h> #include <asm/arch/mem.h> #include <asm/arch/sys_proto.h> -#include <asm/arch/omap_gpmc.h> +#include <asm/omap_gpmc.h> #include <asm/gpio.h> #include <asm/mach-types.h> #include "overo.h" diff --git a/board/pcippc2/cpc710.h b/board/pcippc2/cpc710.h deleted file mode 100644 index 8167270..0000000 --- a/board/pcippc2/cpc710.h +++ /dev/null @@ -1,96 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _CPC710_H_ -#define _CPC710_H_ - -/* Revision */ -#define CPC710_TYPE_100 0x80 -#define CPC710_TYPE_100P 0x90 - -/* System control area */ -#define HW_PHYS_SCA 0xff000000 - -#define HW_SCA_CPC0 0x000000 -#define HW_SCA_SDRAM0 0x000000 -#define HW_SCA_DMA0 0x1C0000 - -#define HW_PHYS_CPC0 (HW_PHYS_SCA + HW_SCA_CPC0) -#define HW_PHYS_SDRAM0 (HW_PHYS_SCA + HW_SCA_SDRAM0) - -#define HW_CPC0_PCICNFR 0x000c -#define HW_CPC0_RSTR 0x0010 -#define HW_CPC0_SPOR 0x00e8 -#define HW_CPC0_UCTL 0x1000 -#define HW_CPC0_SIOC0 0x1020 -#define HW_CPC0_ABCNTL 0x1030 -#define HW_CPC0_SESR 0x1060 -#define HW_CPC0_SEAR 0x1070 -#define HW_CPC0_PGCHP 0x1100 -#define HW_CPC0_RGBAN0 0x1110 -#define HW_CPC0_RGBAN1 0x1120 - -#define HW_CPC0_GPDIR 0x1130 -#define HW_CPC0_GPIN 0x1140 -#define HW_CPC0_GPOUT 0x1150 - -#define HW_CPC0_ATAS 0x1160 - -#define HW_CPC0_PCIBAR 0x200018 -#define HW_CPC0_PCIENB 0x201000 - -#define HW_SDRAM0_MCCR 0x1200 -#define HW_SDRAM0_MESR 0x1220 -#define HW_SDRAM0_MEAR 0x1230 - -#define HW_SDRAM0_MCER0 0x1300 -#define HW_SDRAM0_MCER1 0x1310 -#define HW_SDRAM0_MCER2 0x1320 -#define HW_SDRAM0_MCER3 0x1330 -#define HW_SDRAM0_MCER4 0x1340 -#define HW_SDRAM0_MCER5 0x1350 -#define HW_SDRAM0_MCER6 0x1360 -#define HW_SDRAM0_MCER7 0x1370 - -#define HW_BRIDGE_PCIDG 0xf6120 -#define HW_BRIDGE_INTACK 0xf7700 -#define HW_BRIDGE_PIBAR 0xf7800 -#define HW_BRIDGE_PMBAR 0xf7810 -#define HW_BRIDGE_CRR 0xf7ef0 -#define HW_BRIDGE_PR 0xf7f20 -#define HW_BRIDGE_ACR 0xf7f30 -#define HW_BRIDGE_MSIZE 0xf7f40 -#define HW_BRIDGE_IOSIZE 0xf7f60 -#define HW_BRIDGE_SMBAR 0xf7f80 -#define HW_BRIDGE_SIBAR 0xf7fc0 -#define HW_BRIDGE_CFGADDR 0xf8000 -#define HW_BRIDGE_CFGDATA 0xf8010 -#define HW_BRIDGE_PSSIZE 0xf8100 -#define HW_BRIDGE_BARPS 0xf8120 -#define HW_BRIDGE_PSBAR 0xf8140 - -/* Configuration space registers */ -#define CPC710_BUS_NUMBER 0x40 -#define CPC710_SUB_BUS_NUMBER 0x41 - -#endif diff --git a/board/pcippc2/cpc710_init_ram.c b/board/pcippc2/cpc710_init_ram.c deleted file mode 100644 index 8945351..0000000 --- a/board/pcippc2/cpc710_init_ram.c +++ /dev/null @@ -1,232 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <common.h> -#include <asm/io.h> - -#include "pcippc2.h" -#include "i2c.h" - -typedef struct cpc710_mem_org_s { - u8 rows; - u8 cols; - u8 banks2; - u8 org; -} cpc710_mem_org_t; - -static int cpc710_compute_mcer (u32 * mcer, - unsigned long *size, unsigned int sdram); -static int cpc710_eeprom_checksum (unsigned int sdram); -static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset); - -static u32 cpc710_mcer_mem[] = { - 0x000003f3, /* 18 lines, 4 Mb */ - 0x000003e3, /* 19 lines, 8 Mb */ - 0x000003c3, /* 20 lines, 16 Mb */ - 0x00000383, /* 21 lines, 32 Mb */ - 0x00000303, /* 22 lines, 64 Mb */ - 0x00000203, /* 23 lines, 128 Mb */ - 0x00000003, /* 24 lines, 256 Mb */ - 0x00000002, /* 25 lines, 512 Mb */ - 0x00000001 /* 26 lines, 1024 Mb */ -}; -static cpc710_mem_org_t cpc710_mem_org[] = { - {0x0c, 0x09, 0x02, 0x00}, /* 0000: 12/ 9/2 */ - {0x0d, 0x09, 0x02, 0x00}, /* 0000: 13/ 9/2 */ - {0x0d, 0x0a, 0x02, 0x00}, /* 0000: 13/10/2 */ - {0x0d, 0x0b, 0x02, 0x00}, /* 0000: 13/11/2 */ - {0x0d, 0x0c, 0x02, 0x00}, /* 0000: 13/12/2 */ - {0x0e, 0x0c, 0x02, 0x00}, /* 0000: 14/12/2 */ - {0x0b, 0x08, 0x02, 0x01}, /* 0001: 11/ 8/2 */ - {0x0b, 0x09, 0x01, 0x02}, /* 0010: 11/ 9/1 */ - {0x0b, 0x0a, 0x01, 0x03}, /* 0011: 11/10/1 */ - {0x0c, 0x08, 0x02, 0x04}, /* 0100: 12/ 8/2 */ - {0x0c, 0x0a, 0x02, 0x05}, /* 0101: 12/10/2 */ - {0x0d, 0x08, 0x01, 0x06}, /* 0110: 13/ 8/1 */ - {0x0d, 0x08, 0x02, 0x07}, /* 0111: 13/ 8/2 */ - {0x0d, 0x09, 0x01, 0x08}, /* 1000: 13/ 9/1 */ - {0x0d, 0x0a, 0x01, 0x09}, /* 1001: 13/10/1 */ - {0x0b, 0x08, 0x01, 0x0a}, /* 1010: 11/ 8/1 */ - {0x0c, 0x08, 0x01, 0x0b}, /* 1011: 12/ 8/1 */ - {0x0c, 0x09, 0x01, 0x0c}, /* 1100: 12/ 9/1 */ - {0x0e, 0x09, 0x02, 0x0d}, /* 1101: 14/ 9/2 */ - {0x0e, 0x0a, 0x02, 0x0e}, /* 1110: 14/10/2 */ - {0x0e, 0x0b, 0x02, 0x0f} /* 1111: 14/11/2 */ -}; - -unsigned long cpc710_ram_init (void) -{ - unsigned long memsize = 0; - unsigned long bank_size; - u32 mcer; - -#ifndef CONFIG_SYS_RAMBOOT - /* Clear memory banks - */ - out32 (REG (SDRAM0, MCER0), 0); - out32 (REG (SDRAM0, MCER1), 0); - out32 (REG (SDRAM0, MCER2), 0); - out32 (REG (SDRAM0, MCER3), 0); - out32 (REG (SDRAM0, MCER4), 0); - out32 (REG (SDRAM0, MCER5), 0); - out32 (REG (SDRAM0, MCER6), 0); - out32 (REG (SDRAM0, MCER7), 0); - iobarrier_rw (); - - /* Disable memory - */ - out32 (REG (SDRAM0, MCCR), 0x13b06000); - iobarrier_rw (); -#endif - - /* Only the first memory bank is initialised now - */ - if (!cpc710_compute_mcer (&mcer, &bank_size, 0)) { - puts ("Unsupported SDRAM type !\n"); - hang (); - } - memsize += bank_size; -#ifndef CONFIG_SYS_RAMBOOT - /* Enable bank, zero start - */ - out32 (REG (SDRAM0, MCER0), mcer | 0x80000000); - iobarrier_rw (); -#endif - -#ifndef CONFIG_SYS_RAMBOOT - /* Enable memory - */ - out32 (REG (SDRAM0, MCCR), in32 (REG (SDRAM0, MCCR)) | 0x80000000); - - /* Wait until initialisation finished - */ - while (!(in32 (REG (SDRAM0, MCCR)) & 0x20000000)) { - iobarrier_rw (); - } - - /* Clear Memory Error Status and Address registers - */ - out32 (REG (SDRAM0, MESR), 0); - out32 (REG (SDRAM0, MEAR), 0); - iobarrier_rw (); - - /* ECC is not configured now - */ -#endif - - /* Memory size counter - */ - out32 (REG (CPC0, RGBAN1), memsize); - - return memsize; -} - -static int cpc710_compute_mcer (u32 * mcer, unsigned long *size, unsigned int sdram) -{ - u8 rows; - u8 cols; - u8 banks2; - unsigned int lines; - u32 mc = 0; - unsigned int i; - cpc710_mem_org_t *org = 0; - - if (!i2c_reset ()) { - puts ("Can't reset I2C!\n"); - hang (); - } - - if (!cpc710_eeprom_checksum (sdram)) { - puts ("Invalid EEPROM checksum !\n"); - hang (); - } - - rows = cpc710_eeprom_read (sdram, 3); - cols = cpc710_eeprom_read (sdram, 4); - /* Can be 2 or 4 banks; divide by 2 - */ - banks2 = cpc710_eeprom_read (sdram, 17) / 2; - - lines = rows + cols + banks2; - - if (lines < 18 || lines > 26) { - /* Unsupported configuration - */ - return 0; - } - - mc |= cpc710_mcer_mem[lines - 18] << 6; - - for (i = 0; i < sizeof (cpc710_mem_org) / sizeof (cpc710_mem_org_t); - i++) { - cpc710_mem_org_t *corg = cpc710_mem_org + i; - - if (corg->rows == rows && corg->cols == cols - && corg->banks2 == banks2) { - org = corg; - - break; - } - } - - if (!org) { - /* Unsupported configuration - */ - return 0; - } - - mc |= (u32) org->org << 2; - - /* Supported configuration - */ - *mcer = mc; - *size = 1l << (lines + 4); - - return 1; -} - -static int cpc710_eeprom_checksum (unsigned int sdram) -{ - u8 sum = 0; - unsigned int i; - - for (i = 0; i < 63; i++) { - sum += cpc710_eeprom_read (sdram, i); - } - - return sum == cpc710_eeprom_read (sdram, 63); -} - -static u8 cpc710_eeprom_read (unsigned int sdram, unsigned int offset) -{ - u8 dev = (sdram << 1) | 0xa0; - u8 data; - - if (!i2c_read_byte (&data, dev, offset)) { - puts ("I2C error !\n"); - hang (); - } - - return data; -} diff --git a/board/pcippc2/cpc710_pci.c b/board/pcippc2/cpc710_pci.c deleted file mode 100644 index ccd18e1..0000000 --- a/board/pcippc2/cpc710_pci.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <common.h> -#include <asm/io.h> -#include <pci.h> - -#include "hardware.h" -#include "pcippc2.h" - -struct pci_controller local_hose, cpci_hose; - -static u32 cpc710_mapped_ram; - - /* Enable PCI retry timeouts - */ -void cpc710_pci_enable_timeout (void) -{ - out32(BRIDGE(LOCAL, CFGADDR), 0x50000080); - iobarrier_rw(); - out32(BRIDGE(LOCAL, CFGDATA), 0x32000000); - iobarrier_rw(); - - out32(BRIDGE(CPCI, CFGADDR), 0x50000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), 0x32000000); - iobarrier_rw(); -} - -void cpc710_pci_init (void) -{ - u32 sdram_size = pcippc2_sdram_size(); - - cpc710_mapped_ram = sdram_size < PCI_MEMORY_MAXSIZE ? - sdram_size : PCI_MEMORY_MAXSIZE; - - /* Select the local PCI - */ - out32(REG(CPC0, PCICNFR), 0x80000002); - iobarrier_rw(); - - out32(REG(CPC0, PCIBAR), BRIDGE_LOCAL_PHYS); - iobarrier_rw(); - - /* Enable PCI bridge address decoding - */ - out32(REG(CPC0, PCIENB), 0x80000000); - iobarrier_rw(); - - /* Select the CPCI bridge - */ - out32(REG(CPC0, PCICNFR), 0x80000003); - iobarrier_rw(); - - out32(REG(CPC0, PCIBAR), BRIDGE_CPCI_PHYS); - iobarrier_rw(); - - /* Enable PCI bridge address decoding - */ - out32(REG(CPC0, PCIENB), 0x80000000); - iobarrier_rw(); - - /* Disable configuration accesses - */ - out32(REG(CPC0, PCICNFR), 0x80000000); - iobarrier_rw(); - - /* Initialise the local PCI - */ - out32(BRIDGE(LOCAL, CRR), 0x7c000000); - iobarrier_rw(); - out32(BRIDGE(LOCAL, PCIDG), 0x40000000); - iobarrier_rw(); - out32(BRIDGE(LOCAL, PIBAR), BRIDGE_LOCAL_IO_BUS); - out32(BRIDGE(LOCAL, SIBAR), BRIDGE_LOCAL_IO_PHYS); - out32(BRIDGE(LOCAL, IOSIZE), -BRIDGE_LOCAL_IO_SIZE); - iobarrier_rw(); - out32(BRIDGE(LOCAL, PMBAR), BRIDGE_LOCAL_MEM_BUS); - out32(BRIDGE(LOCAL, SMBAR), BRIDGE_LOCAL_MEM_PHYS); - out32(BRIDGE(LOCAL, MSIZE), -BRIDGE_LOCAL_MEM_SIZE); - iobarrier_rw(); - out32(BRIDGE(LOCAL, PR), 0x00ffe000); - iobarrier_rw(); - out32(BRIDGE(LOCAL, ACR), 0xfe000000); - iobarrier_rw(); - out32(BRIDGE(LOCAL, PSBAR), PCI_MEMORY_BUS >> 24); - out32(BRIDGE(LOCAL, BARPS), PCI_MEMORY_PHYS >> 24); - out32(BRIDGE(LOCAL, PSSIZE), 256 - (cpc710_mapped_ram >> 24)); - iobarrier_rw(); - - /* Initialise the CPCI bridge - */ - out32(BRIDGE(CPCI, CRR), 0x7c000000); - iobarrier_rw(); - out32(BRIDGE(CPCI, PCIDG), 0xC0000000); - iobarrier_rw(); - out32(BRIDGE(CPCI, PIBAR), BRIDGE_CPCI_IO_BUS); - out32(BRIDGE(CPCI, SIBAR), BRIDGE_CPCI_IO_PHYS); - out32(BRIDGE(CPCI, IOSIZE), -BRIDGE_CPCI_IO_SIZE); - iobarrier_rw(); - out32(BRIDGE(CPCI, PMBAR), BRIDGE_CPCI_MEM_BUS); - out32(BRIDGE(CPCI, SMBAR), BRIDGE_CPCI_MEM_PHYS); - out32(BRIDGE(CPCI, MSIZE), -BRIDGE_CPCI_MEM_SIZE); - iobarrier_rw(); - out32(BRIDGE(CPCI, PR), 0x80ffe000); - iobarrier_rw(); - out32(BRIDGE(CPCI, ACR), 0xdf000000); - iobarrier_rw(); - out32(BRIDGE(CPCI, PSBAR), PCI_MEMORY_BUS >> 24); - out32(BRIDGE(CPCI, BARPS), PCI_MEMORY_PHYS >> 24); - out32(BRIDGE(CPCI, PSSIZE), 256 - (cpc710_mapped_ram >> 24)); - iobarrier_rw(); - - /* Local PCI - */ - - out32(BRIDGE(LOCAL, CFGADDR), 0x04000080); - iobarrier_rw(); - out32(BRIDGE(LOCAL, CFGDATA), 0x56010000); - iobarrier_rw(); - - out32(BRIDGE(LOCAL, CFGADDR), 0x0c000080); - iobarrier_rw(); - out32(BRIDGE(LOCAL, CFGDATA), PCI_LATENCY_TIMER_VAL << 16); - iobarrier_rw(); - - /* Set bus and subbus numbers - */ - out32(BRIDGE(LOCAL, CFGADDR), 0x40000080); - iobarrier_rw(); - out32(BRIDGE(LOCAL, CFGDATA), 0x00000000); - iobarrier_rw(); - - out32(BRIDGE(LOCAL, CFGADDR), 0x50000080); - iobarrier_rw(); - /* PCI retry timeouts will be enabled later - */ - out32(BRIDGE(LOCAL, CFGDATA), 0x00000000); - iobarrier_rw(); - - /* CPCI - */ - - /* Set bus and subbus numbers - */ - out32(BRIDGE(CPCI, CFGADDR), 0x40000080); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), 0x01010000); - iobarrier_rw(); - - out32(BRIDGE(CPCI, CFGADDR), 0x04000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), 0x56010000); - iobarrier_rw(); - - out32(BRIDGE(CPCI, CFGADDR), 0x0c000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), PCI_LATENCY_TIMER_VAL << 16); - iobarrier_rw(); - - /* Write to the PSBAR */ - out32(BRIDGE(CPCI, CFGADDR), 0x10000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), cpu_to_le32(PCI_MEMORY_BUS)); - iobarrier_rw(); - - /* Set bus and subbus numbers - */ - out32(BRIDGE(CPCI, CFGADDR), 0x40000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), 0x01ff0000); - iobarrier_rw(); - - out32(BRIDGE(CPCI, CFGADDR), 0x50000180); - iobarrier_rw(); - out32(BRIDGE(CPCI, CFGDATA), 0x32000000); - /* PCI retry timeouts will be enabled later - */ - out32(BRIDGE(CPCI, CFGDATA), 0x00000000); - iobarrier_rw(); - - /* Remove reset on the PCI buses - */ - out32(BRIDGE(LOCAL, CRR), 0xfc000000); - iobarrier_rw(); - out32(BRIDGE(CPCI, CRR), 0xfc000000); - iobarrier_rw(); - - local_hose.first_busno = 0; - local_hose.last_busno = 0xff; - - /* System memory space */ - pci_set_region(local_hose.regions + 0, - PCI_MEMORY_BUS, - PCI_MEMORY_PHYS, - PCI_MEMORY_MAXSIZE, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(local_hose.regions + 1, - BRIDGE_LOCAL_MEM_BUS, - BRIDGE_LOCAL_MEM_PHYS, - BRIDGE_LOCAL_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(local_hose.regions + 2, - BRIDGE_LOCAL_IO_BUS, - BRIDGE_LOCAL_IO_PHYS, - BRIDGE_LOCAL_IO_SIZE, - PCI_REGION_IO); - - local_hose.region_count = 3; - - pci_setup_indirect(&local_hose, - BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGADDR, - BRIDGE_LOCAL_PHYS + HW_BRIDGE_CFGDATA); - - pci_register_hose(&local_hose); - - /* Initialize PCI32 bus registers */ - pci_hose_write_config_byte(&local_hose, - PCI_BDF(local_hose.first_busno,0,0), - CPC710_BUS_NUMBER, - local_hose.first_busno); - pci_hose_write_config_byte(&local_hose, - PCI_BDF(local_hose.first_busno,0,0), - CPC710_SUB_BUS_NUMBER, - local_hose.last_busno); - - local_hose.last_busno = pci_hose_scan(&local_hose); - - /* Write out correct max subordinate bus number for local hose */ - pci_hose_write_config_byte(&local_hose, - PCI_BDF(local_hose.first_busno,0,0), - CPC710_SUB_BUS_NUMBER, - local_hose.last_busno); - - cpci_hose.first_busno = local_hose.last_busno + 1; - cpci_hose.last_busno = 0xff; - - /* System memory space */ - pci_set_region(cpci_hose.regions + 0, - PCI_MEMORY_BUS, - PCI_MEMORY_PHYS, - PCI_MEMORY_MAXSIZE, - PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(cpci_hose.regions + 1, - BRIDGE_CPCI_MEM_BUS, - BRIDGE_CPCI_MEM_PHYS, - BRIDGE_CPCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI I/O space */ - pci_set_region(cpci_hose.regions + 2, - BRIDGE_CPCI_IO_BUS, - BRIDGE_CPCI_IO_PHYS, - BRIDGE_CPCI_IO_SIZE, - PCI_REGION_IO); - - cpci_hose.region_count = 3; - - pci_setup_indirect(&cpci_hose, - BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGADDR, - BRIDGE_CPCI_PHYS + HW_BRIDGE_CFGDATA); - - pci_register_hose(&cpci_hose); - - /* Initialize PCI64 bus registers */ - pci_hose_write_config_byte(&cpci_hose, - PCI_BDF(cpci_hose.first_busno,0,0), - CPC710_BUS_NUMBER, - cpci_hose.first_busno); - pci_hose_write_config_byte(&cpci_hose, - PCI_BDF(cpci_hose.first_busno,0,0), - CPC710_SUB_BUS_NUMBER, - cpci_hose.last_busno); - - cpci_hose.last_busno = pci_hose_scan(&cpci_hose); - - /* Write out correct max subordinate bus number for cpci hose */ - pci_hose_write_config_byte(&cpci_hose, - PCI_BDF(cpci_hose.first_busno,0,0), - CPC710_SUB_BUS_NUMBER, - cpci_hose.last_busno); -} diff --git a/board/pcippc2/cpc710_pci.h b/board/pcippc2/cpc710_pci.h deleted file mode 100644 index 24d0db6..0000000 --- a/board/pcippc2/cpc710_pci.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _CPC710_PCI_H_ -#define _CPC710_PCI_H_ - -#define PCI_MEMORY_PHYS 0x00000000 -#define PCI_MEMORY_BUS 0x80000000 -#define PCI_MEMORY_MAXSIZE 0x20000000 - -#define BRIDGE_CPCI_PHYS 0xff500000 -#define BRIDGE_CPCI_MEM_SIZE 0x08000000 -#define BRIDGE_CPCI_MEM_PHYS 0xf0000000 -#define BRIDGE_CPCI_MEM_BUS 0x00000000 -#define BRIDGE_CPCI_IO_SIZE 0x02000000 -#define BRIDGE_CPCI_IO_PHYS 0xfc000000 -#define BRIDGE_CPCI_IO_BUS 0x00000000 - -#define BRIDGE_LOCAL_PHYS 0xff400000 -#define BRIDGE_LOCAL_MEM_SIZE 0x04000000 -#define BRIDGE_LOCAL_MEM_PHYS 0xf8000000 -#define BRIDGE_LOCAL_MEM_BUS 0x40000000 -#define BRIDGE_LOCAL_IO_SIZE 0x01000000 -#define BRIDGE_LOCAL_IO_PHYS 0xfe000000 -#define BRIDGE_LOCAL_IO_BUS 0x04000000 - -#define BRIDGE(r, x) (BRIDGE_##r##_PHYS + HW_BRIDGE_##x) - -#define PCI_LATENCY_TIMER_VAL 0xff - -#endif diff --git a/board/pcippc2/flash.c b/board/pcippc2/flash.c deleted file mode 100644 index ec604e0..0000000 --- a/board/pcippc2/flash.c +++ /dev/null @@ -1,573 +0,0 @@ -/* - * (C) Copyright 2001 - * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. - * - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <common.h> -#include <flash.h> -#include <asm/io.h> - -/*---------------------------------------------------------------------*/ -#undef DEBUG_FLASH - -#ifdef DEBUG_FLASH -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif -/*---------------------------------------------------------------------*/ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -static ulong flash_get_size (ulong addr, flash_info_t *info); -static int flash_get_offsets (ulong base, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_reset (ulong addr); - -unsigned long flash_init (void) -{ - unsigned int i; - unsigned long flash_size = 0; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - flash_info[i].sector_count = 0; - flash_info[i].size = 0; - } - - DEBUGF("\n## Get flash size @ 0x%08x\n", CONFIG_SYS_FLASH_BASE); - - flash_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info); - - DEBUGF("## Flash bank size: %08lx\n", flash_size); - - if (flash_size) { -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \ - CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_MAX_SIZE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - } else { - puts ("Warning: the BOOT Flash is not initialised !"); - } - - return flash_size; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (ulong addr, flash_info_t *info) -{ - short i; - uchar value; - - /* Write auto select command: read Manufacturer ID */ - out8(addr + 0x0555, 0xAA); - iobarrier_rw(); - out8(addr + 0x02AA, 0x55); - iobarrier_rw(); - out8(addr + 0x0555, 0x90); - iobarrier_rw(); - - value = in8(addr); - iobarrier_rw(); - - DEBUGF("Manuf. ID @ 0x%08lx: 0x%08x\n", (ulong)addr, value); - - switch (value | (value << 16)) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - - case STM_MANUFACT: - info->flash_id = FLASH_MAN_STM; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - flash_reset (addr); - return 0; - } - - value = in8(addr + 1); /* device ID */ - iobarrier_rw(); - - DEBUGF("Device ID @ 0x%08lx: 0x%08x\n", addr+1, value); - - switch ((ulong)value) { - case AMD_ID_F040B: - DEBUGF("Am29F040B\n"); - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512 kB */ - - case AMD_ID_LV040B: - DEBUGF("Am29LV040B\n"); - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512 kB */ - - case AMD_ID_LV400T: - DEBUGF("Am29LV400T\n"); - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV400B: - DEBUGF("Am29LV400B\n"); - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case AMD_ID_LV800T: - DEBUGF("Am29LV800T\n"); - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV800B: - DEBUGF("Am29LV400B\n"); - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case AMD_ID_LV160T: - DEBUGF("Am29LV160T\n"); - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV160B: - DEBUGF("Am29LV160B\n"); - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case AMD_ID_LV320T: - DEBUGF("Am29LV320T\n"); - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - -#if 0 - /* Has the same ID as AMD_ID_LV320T, to be fixed */ - case AMD_ID_LV320B: - DEBUGF("Am29LV320B\n"); - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - - case AMD_ID_LV033C: - DEBUGF("Am29LV033C\n"); - info->flash_id += FLASH_AM033C; - info->sector_count = 64; - info->size = 0x01000000; - break; /* => 16Mb */ - - case STM_ID_F040B: - DEBUGF("M29F040B\n"); - info->flash_id += FLASH_AM040; - info->sector_count = 8; - info->size = 0x00080000; - break; /* => 512 kB */ - - default: - info->flash_id = FLASH_UNKNOWN; - flash_reset (addr); - return (0); /* => no or unknown flash */ - - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - if (! flash_get_offsets (addr, info)) { - flash_reset (addr); - return 0; - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - value = in8(info->start[i] + 2); - iobarrier_rw(); - info->protect[i] = (value & 1) != 0; - } - - /* - * Reset bank to read mode - */ - flash_reset (addr); - - return (info->size); -} - -static int flash_get_offsets (ulong base, flash_info_t *info) -{ - unsigned int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: - /* set sector offsets for uniform sector type */ - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + i * info->size / - info->sector_count; - } - break; - default: - return 0; - } - - return 1; -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - volatile ulong addr = info->start[0]; - int flag, prot, sect, l_sect; - ulong start, now, last; - - if (s_first < 0 || s_first > s_last) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - out8(addr + 0x555, 0x80); - iobarrier_rw(); - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = info->start[sect]; - out8(addr, 0x30); - iobarrier_rw(); - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = info->start[l_sect]; - - DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT); - - while ((in8(addr) & 0x80) != 0x80) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - flash_reset (info->start[0]); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - iobarrier_rw(); - } - -DONE: - /* reset to read mode */ - flash_reset (info->start[0]); - - printf (" done\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/* - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - volatile ulong addr = info->start[0]; - ulong start; - int i; - - /* Check if Flash is (sufficiently) erased */ - if ((in32(dest) & data) != data) { - return (2); - } - - /* write each byte out */ - for (i = 0; i < 4; i++) { - char *data_ch = (char *)&data; - int flag = disable_interrupts(); - - out8(addr + 0x555, 0xAA); - iobarrier_rw(); - out8(addr + 0x2AA, 0x55); - iobarrier_rw(); - out8(addr + 0x555, 0xA0); - iobarrier_rw(); - out8(dest+i, data_ch[i]); - iobarrier_rw(); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - flash_reset (addr); - return (1); - } - iobarrier_rw(); - } - } - - flash_reset (addr); - return (0); -} - -/* - * Reset bank to read mode - */ -static void flash_reset (ulong addr) -{ - out8(addr, 0xF0); /* reset bank */ - iobarrier_rw(); -} - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_STM: printf ("SGS THOMSON "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n"); - break; - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - if (info->size % 0x100000 == 0) { - printf (" Size: %ld MB in %d Sectors\n", - info->size / 0x100000, info->sector_count); - } else if (info->size % 0x400 == 0) { - printf (" Size: %ld KB in %d Sectors\n", - info->size / 0x400, info->sector_count); - } else { - printf (" Size: %ld B in %d Sectors\n", - info->size, info->sector_count); - } - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); -} diff --git a/board/pcippc2/fpga_serial.c b/board/pcippc2/fpga_serial.c deleted file mode 100644 index de61ca0..0000000 --- a/board/pcippc2/fpga_serial.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <common.h> -#include <asm/io.h> - -#include "fpga_serial.h" -#include "hardware.h" -#include "pcippc2.h" - -DECLARE_GLOBAL_DATA_PTR; - - /* 8 data, 1 stop, no parity - */ -#define LCRVAL 0x03 - /* RTS/DTR - */ -#define MCRVAL 0x03 - /* Clear & enable FIFOs - */ -#define FCRVAL 0x07 - -static void fpga_serial_wait (void); -static void fpga_serial_print (char c); - -void fpga_serial_init (int baudrate) -{ - int clock_divisor = 115200 / baudrate; - - out8 (FPGA (INT, SERIAL_CONFIG), 0x24); - iobarrier_rw (); - - fpga_serial_wait (); - - out8 (UART (IER), 0); - out8 (UART (LCR), LCRVAL | 0x80); - iobarrier_rw (); - out8 (UART (DLL), clock_divisor & 0xff); - out8 (UART (DLM), clock_divisor >> 8); - iobarrier_rw (); - out8 (UART (LCR), LCRVAL); - iobarrier_rw (); - out8 (UART (MCR), MCRVAL); - out8 (UART (FCR), FCRVAL); - iobarrier_rw (); -} - -void fpga_serial_putc (char c) -{ - if (c) { - fpga_serial_print (c); - } -} - -int fpga_serial_getc (void) -{ - while ((in8 (UART (LSR)) & 0x01) == 0); - - return in8 (UART (RBR)); -} - -int fpga_serial_tstc (void) -{ - return (in8 (UART (LSR)) & 0x01) != 0; -} - -void fpga_serial_setbrg (void) -{ - int clock_divisor = 115200 / gd->baudrate; - - fpga_serial_wait (); - - out8 (UART (LCR), LCRVAL | 0x80); - iobarrier_rw (); - out8 (UART (DLL), clock_divisor & 0xff); - out8 (UART (DLM), clock_divisor >> 8); - iobarrier_rw (); - out8 (UART (LCR), LCRVAL); - iobarrier_rw (); -} - -static void fpga_serial_wait (void) -{ - while ((in8 (UART (LSR)) & 0x40) == 0); -} - -static void fpga_serial_print (char c) -{ - if (c == '\n') { - while ((in8 (UART (LSR)) & 0x20) == 0); - - out8 (UART (THR), '\r'); - iobarrier_rw (); - } - - while ((in8 (UART (LSR)) & 0x20) == 0); - - out8 (UART (THR), c); - iobarrier_rw (); - - if (c == '\n') { - fpga_serial_wait (); - } -} diff --git a/board/pcippc2/hardware.h b/board/pcippc2/hardware.h deleted file mode 100644 index 489929d..0000000 --- a/board/pcippc2/hardware.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _HARDWARE_H_ -#define _HARDWARE_H_ - -#include "cpc710.h" -#include "cpc710_pci.h" -#include "pcippc2_fpga.h" -#include "ns16550.h" - -#define REG(r, x) (HW_PHYS_##r + HW_##r##_##x) - - /* Address map: - * - * 0x00000000-0x20000000 SDRAM - * 0x40000000-0x00008000 Init RAM in the CPU DCache - * 0xf0000000-0xf8000000 CPCI MEM - * 0xf8000000-0xfc000000 Local PCI MEM - * 0xfc000000-0xfe000000 CPCI I/O - * 0xfe000000-0xff000000 Local PCI I/O - * 0xff000000-0xff201000 System configuration space - * 0xff400000-0xff500000 Local PCI bridge space - * 0xff500000-0xff600000 CPCI bridge space - * 0xfff00000-0xfff80000 Boot Flash - */ - -#endif diff --git a/board/pcippc2/i2c.c b/board/pcippc2/i2c.c deleted file mode 100644 index ab52562..0000000 --- a/board/pcippc2/i2c.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <common.h> -#include <asm/io.h> - -#include "hardware.h" -#include "i2c.h" - -static void i2c_start (void); -static void i2c_stop (void); -static int i2c_write (u8 data); -static void i2c_read (u8 * data); - -static inline void i2c_port_start (void); -static inline void i2c_clock (unsigned int val); -static inline void i2c_data (unsigned int val); -static inline unsigned int - i2c_in (void); -static inline void i2c_write_bit (unsigned int val); -static inline unsigned int - i2c_read_bit (void); - -static inline void i2c_udelay (unsigned int time); - -int i2c_read_byte ( - u8 * data, - u8 dev, - u8 offset) -{ - int err = 0; - - i2c_start(); - - err = ! i2c_write(dev); - - if (! err) - { - err = ! i2c_write(offset); - } - - if (! err) - { - i2c_start(); - } - - if (! err) - { - err = ! i2c_write(dev | 0x01); - } - - if (! err) - { - i2c_read(data); - } - - i2c_stop(); - - return ! err; -} - -static inline void i2c_udelay ( - unsigned int time) -{ - int v; - - asm volatile("mtdec %0" : : "r" (time * ((CONFIG_SYS_BUS_CLK / 4) / 1000000))); - - do - { - asm volatile("isync; mfdec %0" : "=r" (v)); - } while (v >= 0); -} - - /* Low-level hardware access - */ - -#define BIT_GPDATA 0x80000000 -#define BIT_GPCLK 0x40000000 - -static inline void i2c_port_start (void) -{ - out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~(BIT_GPCLK | BIT_GPDATA)); - out32(REG(CPC0, GPOUT), in32(REG(CPC0, GPOUT)) & ~(BIT_GPCLK | BIT_GPDATA)); - iobarrier_rw(); - - i2c_udelay(1); -} - -static inline void i2c_clock ( - unsigned int val) -{ - if (val) - { - out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~BIT_GPCLK); - } - else - { - out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) | BIT_GPCLK); - } - - iobarrier_rw(); - - i2c_udelay(1); -} - -static inline void i2c_data ( - unsigned int val) -{ - if (val) - { - out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) & ~BIT_GPDATA); - } - else - { - out32(REG(CPC0, GPDIR), in32(REG(CPC0, GPDIR)) | BIT_GPDATA); - } - - iobarrier_rw(); - - i2c_udelay(1); -} - -static inline unsigned int i2c_in (void) -{ - unsigned int val = ((in32(REG(CPC0, GPIN)) & BIT_GPDATA) != 0)?1:0; - - iobarrier_rw(); - - return val; -} - - - /* Protocol implementation - */ - -static inline void i2c_write_bit ( - unsigned int val) -{ - i2c_data(val); - i2c_udelay(10); - i2c_clock(1); - i2c_udelay(10); - i2c_clock(0); - i2c_udelay(10); -} - -static inline unsigned int i2c_read_bit (void) -{ - unsigned int val; - - i2c_data(1); - i2c_udelay(10); - - i2c_clock(1); - i2c_udelay(10); - - val = i2c_in(); - - i2c_clock(0); - i2c_udelay(10); - - return val; -} - -unsigned int i2c_reset (void) -{ - unsigned int val; - int i; - - i2c_port_start(); - - i=0; - do { - i2c_udelay(10); - i2c_clock(0); - i2c_udelay(10); - i2c_clock(1); - i2c_udelay(10); - val = i2c_in(); - i++; - } while ((i<9)&&(val==0)); - return (val); -} - - -static void i2c_start (void) -{ - i2c_data(1); - i2c_clock(1); - i2c_udelay(10); - i2c_data(0); - i2c_udelay(10); - i2c_clock(0); - i2c_udelay(10); -} - -static void i2c_stop (void) -{ - i2c_data(0); - i2c_udelay(10); - i2c_clock(1); - i2c_udelay(10); - i2c_data(1); - i2c_udelay(10); -} - -static int i2c_write ( - u8 data) -{ - unsigned int i; - - for (i = 0; i < 8; i++) - { - i2c_write_bit(data >> 7); - data <<= 1; - } - - return i2c_read_bit() == 0; -} - -static void i2c_read ( - u8 * data) -{ - unsigned int i; - u8 val = 0; - - for (i = 0; i < 8; i++) - { - val <<= 1; - val |= i2c_read_bit(); - } - - *data = val; - i2c_write_bit(1); /* NoAck */ -} diff --git a/board/pcippc2/ns16550.h b/board/pcippc2/ns16550.h deleted file mode 100644 index 7023f13..0000000 --- a/board/pcippc2/ns16550.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _NS16550_H_ -#define _NS16550_H_ - -#define NS16550_RBR 0x00 -#define NS16550_IER 0x01 -#define NS16550_FCR 0x02 -#define NS16550_LCR 0x03 -#define NS16550_MCR 0x04 -#define NS16550_LSR 0x05 -#define NS16550_MSR 0x06 -#define NS16550_SCR 0x07 - -#define NS16550_THR NS16550_RBR -#define NS16550_IIR NS16550_FCR -#define NS16550_DLL NS16550_RBR -#define NS16550_DLM NS16550_IER - -#endif diff --git a/board/pcippc2/pcippc2.c b/board/pcippc2/pcippc2.c deleted file mode 100644 index 5e6fc58..0000000 --- a/board/pcippc2/pcippc2.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <common.h> -#include <command.h> -#include <asm/io.h> -#include <linux/mtd/doc2000.h> -#include <watchdog.h> -#include <pci.h> -#include <netdev.h> -#include <serial.h> - -#include "hardware.h" -#include "pcippc2.h" -#include "sconsole.h" -#include "fpga_serial.h" - -DECLARE_GLOBAL_DATA_PTR; - -#if defined(CONFIG_WATCHDOG) - -static int pcippc2_wdt_init_done = 0; - -void pcippc2_wdt_init (void); - -#endif - - /* Check board identity - */ -int checkboard (void) -{ -#ifdef CONFIG_PCIPPC2 - puts ("Board: Gespac PCIPPC-2\n"); -#else - puts ("Board: Gespac PCIPPC-6\n"); -#endif - return 0; -} - - /* RAM size is stored in CPC0_RGBAN1 - */ -u32 pcippc2_sdram_size (void) -{ - return in32 (REG (CPC0, RGBAN1)); -} - -phys_size_t initdram (int board_type) -{ - return cpc710_ram_init (); -} - -int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - out32 (REG (CPC0, SPOR), 0); - iobarrier_rw (); - while (1); - /* notreached */ - return (-1); -} - -int board_early_init_f (void) -{ - out32 (REG (CPC0, RSTR), 0xC0000000); - iobarrier_rw (); - - out32 (REG (CPC0, RSTR), 0xF0000000); - iobarrier_rw (); - - out32 (REG (CPC0, UCTL), 0x00F80000); - - out32 (REG (CPC0, SIOC0), 0x30000000); - - out32 (REG (CPC0, ABCNTL), 0x00000000); - - out32 (REG (CPC0, SESR), 0x00000000); - out32 (REG (CPC0, SEAR), 0x00000000); - - /* Detect IBM Avignon CPC710 Revision */ - if ((in32 (REG (CPC0, UCTL)) & 0x000000F0) == CPC710_TYPE_100P) - out32 (REG (CPC0, PGCHP), 0xA0000040); - else - out32 (REG (CPC0, PGCHP), 0x80800040); - - - out32 (REG (CPC0, ATAS), 0x709C2508); - - iobarrier_rw (); - - return 0; -} - -void after_reloc (ulong dest_addr) -{ - /* Jump to the main U-Boot board init code - */ - board_init_r ((gd_t *)gd, dest_addr); -} - -int misc_init_r (void) -{ - pcippc2_fpga_init (); - - pcippc2_cpci3264_init (); - -#if defined(CONFIG_WATCHDOG) - pcippc2_wdt_init (); -#endif - - fpga_serial_init (sconsole_get_baudrate ()); - - sconsole_putc = fpga_serial_putc; - sconsole_puts = default_serial_puts; - sconsole_getc = fpga_serial_getc; - sconsole_tstc = fpga_serial_tstc; - sconsole_setbrg = fpga_serial_setbrg; - - sconsole_flush (); - return (0); -} - -void pci_init_board (void) -{ - cpc710_pci_init (); - - /* FPGA requires no retry timeouts to be enabled - */ - cpc710_pci_enable_timeout (); -} - -#ifdef CONFIG_CMD_DOC -void doc_init (void) -{ - doc_probe (pcippc2_fpga1_phys + HW_FPGA1_DOC); -} -#endif - -void pcippc2_cpci3264_init (void) -{ - pci_dev_t bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0); - - if (bdf == -1) - { - puts("Unable to find FPGA !\n"); - hang(); - } - - if((in32(pcippc2_fpga0_phys + HW_FPGA0_BOARD) & 0x01000000) == 0x01000000) - /* 32-bits Compact PCI bus - LSB bit */ - { - iobarrier_rw(); - out32(BRIDGE(CPCI, PCIDG), 0x40000000); /* 32-bits bridge, Pipeline */ - iobarrier_rw(); - } -} - -#if defined(CONFIG_WATCHDOG) - -void pcippc2_wdt_init (void) -{ - out16r (FPGA (WDT, PROG), 0xffff); - out8 (FPGA (WDT, CTRL), 0x1); - - pcippc2_wdt_init_done = 1; -} - -void pcippc2_wdt_done (void) -{ - out8 (FPGA (WDT, CTRL), 0x0); - - pcippc2_wdt_init_done = 0; -} - -void pcippc2_wdt_reset (void) -{ - if (pcippc2_wdt_init_done == 1) - out8 (FPGA (WDT, REFRESH), 0x56); -} - -void watchdog_reset (void) -{ - int re_enable = disable_interrupts (); - - pcippc2_wdt_reset (); - if (re_enable) - enable_interrupts (); -} - -#if defined(CONFIG_CMD_BSP) -int do_wd (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - switch (argc) { - case 1: - printf ("Watchdog timer status is %s\n", - pcippc2_wdt_init_done == 1 ? "on" : "off"); - - return 0; - case 2: - if (!strcmp(argv[1],"on")) { - pcippc2_wdt_init(); - printf("Watchdog timer now is on\n"); - - return 0; - - } else if (!strcmp(argv[1],"off")) { - pcippc2_wdt_done(); - printf("Watchdog timer now is off\n"); - - return 0; - - } else - break; - default: - break; - } - return cmd_usage(cmdtp); -} - -U_BOOT_CMD( - wd, 2, 1, do_wd, - "check and set watchdog", - "on - switch watchDog on\n" - "wd off - switch watchdog off\n" - "wd - print current status" -); - -#endif -#endif /* CONFIG_WATCHDOG */ - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} diff --git a/board/pcippc2/pcippc2.h b/board/pcippc2/pcippc2.h deleted file mode 100644 index a1366ef..0000000 --- a/board/pcippc2/pcippc2.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _PCIPPC2_H_ -#define _PCIPPC2_H_ - -#include <config.h> -#include <common.h> - -#include "hardware.h" - -#define FPGA(r, p) (pcippc2_fpga0_phys + HW_FPGA0_##r##_##p) -#define UART(r) (pcippc2_fpga0_phys + HW_FPGA0_UART1 + NS16550_##r * 4) -#define RTC(r) (pcippc2_fpga1_phys + HW_FPGA1_RTC + r) - -extern u32 pcippc2_fpga0_phys; -extern u32 pcippc2_fpga1_phys; - -extern u32 pcippc2_sdram_size (void); - -extern void pcippc2_fpga_init (void); - -extern void pcippc2_cpci3264_init (void); - -extern void cpc710_pci_init (void); -extern void cpc710_pci_enable_timeout (void); - -extern unsigned long - cpc710_ram_init (void); - -#endif diff --git a/board/pcippc2/pcippc2_fpga.c b/board/pcippc2/pcippc2_fpga.c deleted file mode 100644 index 7f6739d..0000000 --- a/board/pcippc2/pcippc2_fpga.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <common.h> -#include <asm/io.h> - -#include "pci.h" - -#include "hardware.h" -#include "pcippc2.h" - -u32 pcippc2_fpga0_phys; -u32 pcippc2_fpga1_phys; - -void pcippc2_fpga_init (void) -{ - pci_dev_t bdf = pci_find_device(FPGA_VENDOR_ID, FPGA_DEVICE_ID, 0); - unsigned int addr; - u16 cmd; - - if (bdf == -1) - { - puts("Unable to find FPGA !\n"); - hang(); - } - - pci_read_config_word(bdf, PCI_COMMAND, &cmd); - if ((cmd & (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)) != (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)) - { - puts("FPGA is not configured !\n"); - hang(); - } - - pci_read_config_dword(bdf, PCI_BASE_ADDRESS_0, &addr); - if (addr & 0x1) - { - /* IO space - */ - pcippc2_fpga0_phys = pci_io_to_phys(bdf, addr & 0xfffffffc); - } - else - { - /* Memory space - */ - pcippc2_fpga0_phys = pci_mem_to_phys(bdf, addr & 0xfffffff0); - } - - pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr); - if (addr & 0x1) - { - /* IO space - */ - pcippc2_fpga1_phys = pci_io_to_phys(bdf, addr & 0xfffffffc); - } - else - { - /* Memory space - */ - pcippc2_fpga1_phys = pci_mem_to_phys(bdf, addr & 0xfffffff0); - } - - /* Interrupts are not used - */ - out32(FPGA(INT, INTR_MASK), 0xffffffff); - iobarrier_rw(); -} diff --git a/board/pcippc2/pcippc2_fpga.h b/board/pcippc2/pcippc2_fpga.h deleted file mode 100644 index 850c331..0000000 --- a/board/pcippc2/pcippc2_fpga.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _PCIPPC2_FPGA_H_ -#define _PCIPPC2_FPGA_H_ - -#define FPGA_VENDOR_ID 0x1310 -#define FPGA_DEVICE_ID 0x000d - -#define HW_FPGA0_INT 0x0000 -#define HW_FPGA0_BOARD 0x0060 -#define HW_FPGA0_UART1 0x0080 -#define HW_FPGA0_UART2 0x0100 -#define HW_FPGA0_RTC 0x2000 -#define HW_FPGA0_DOC 0x4000 -#define HW_FPGA1_RTC 0x0000 -#define HW_FPGA1_DOC 0x4000 - -#define HW_FPGA0_INT_INTR_MASK 0x30 -#define HW_FPGA0_INT_INTR_STATUS 0x34 -#define HW_FPGA0_INT_INTR_EOI 0x40 -#define HW_FPGA0_INT_SERIAL_CONFIG 0x5c - -#define HW_FPGA0_WDT_CTRL 0x44 -#define HW_FPGA0_WDT_PROG 0x48 -#define HW_FPGA0_WDT_VAL 0x4c -#define HW_FPGA0_WDT_REFRESH 0x50 - -#endif diff --git a/board/pcippc2/sconsole.c b/board/pcippc2/sconsole.c deleted file mode 100644 index aa3c908..0000000 --- a/board/pcippc2/sconsole.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <common.h> -#include <serial.h> -#include <linux/compiler.h> - -#include "sconsole.h" - -DECLARE_GLOBAL_DATA_PTR; - -void (*sconsole_putc) (char) = 0; -void (*sconsole_puts) (const char *) = 0; -int (*sconsole_getc) (void) = 0; -int (*sconsole_tstc) (void) = 0; -void (*sconsole_setbrg) (void) = 0; - -static int sconsole_serial_init(void) -{ - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - - sb->pos = 0; - sb->size = 0; - sb->baud = gd->baudrate; - sb->max_size = CONFIG_SYS_SCONSOLE_SIZE - sizeof (sconsole_buffer_t); - - return (0); -} - -static void sconsole_serial_putc(char c) -{ - if (sconsole_putc) { - (*sconsole_putc) (c); - } else { - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - - if (c) { - sb->data[sb->pos++] = c; - if (sb->pos == sb->max_size) { - sb->pos = 0; - } - if (sb->size < sb->max_size) { - sb->size++; - } - } - } -} - -static void sconsole_serial_puts(const char *s) -{ - if (sconsole_puts) { - (*sconsole_puts) (s); - } else { - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - - while (*s) { - sb->data[sb->pos++] = *s++; - if (sb->pos == sb->max_size) { - sb->pos = 0; - } - if (sb->size < sb->max_size) { - sb->size++; - } - } - } -} - -static int sconsole_serial_getc(void) -{ - if (sconsole_getc) { - return (*sconsole_getc) (); - } else { - return 0; - } -} - -static int sconsole_serial_tstc(void) -{ - if (sconsole_tstc) { - return (*sconsole_tstc) (); - } else { - return 0; - } -} - -static void sconsole_serial_setbrg(void) -{ - if (sconsole_setbrg) { - (*sconsole_setbrg) (); - } else { - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - - sb->baud = gd->baudrate; - } -} - -static struct serial_device sconsole_serial_drv = { - .name = "sconsole_serial", - .start = sconsole_serial_init, - .stop = NULL, - .setbrg = sconsole_serial_setbrg, - .putc = sconsole_serial_putc, - .puts = sconsole_serial_puts, - .getc = sconsole_serial_getc, - .tstc = sconsole_serial_tstc, -}; - -void sconsole_serial_initialize(void) -{ - serial_register(&sconsole_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &sconsole_serial_drv; -} - -int sconsole_get_baudrate (void) -{ - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - - return sb->baud; -} - -void sconsole_flush (void) -{ - if (sconsole_putc) { - sconsole_buffer_t *sb = SCONSOLE_BUFFER; - unsigned int end = sb->pos < sb->size - ? sb->pos + sb->max_size - sb->size - : sb->pos - sb->size; - - while (sb->size) { - (*sconsole_putc) (sb->data[end++]); - if (end == sb->max_size) { - end = 0; - } - sb->size--; - } - } -} diff --git a/board/pcippc2/sconsole.h b/board/pcippc2/sconsole.h deleted file mode 100644 index ff0ccab..0000000 --- a/board/pcippc2/sconsole.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SCONSOLE_H_ -#define _SCONSOLE_H_ - -#include <config.h> - -typedef struct sconsole_buffer_s { - unsigned long size; - unsigned long max_size; - unsigned long pos; - unsigned long baud; - char data[1]; -} sconsole_buffer_t; - -#define SCONSOLE_BUFFER ((sconsole_buffer_t *) CONFIG_SYS_SCONSOLE_ADDR) - -extern void (* sconsole_putc) (char); -extern void (* sconsole_puts) (const char *); -extern int (* sconsole_getc) (void); -extern int (* sconsole_tstc) (void); -extern void (* sconsole_setbrg) (void); - -extern void sconsole_flush (void); -extern int sconsole_get_baudrate (void); - -#endif diff --git a/board/pdm360ng/pdm360ng.c b/board/pdm360ng/pdm360ng.c index a2a1323..3048acd 100644 --- a/board/pdm360ng/pdm360ng.c +++ b/board/pdm360ng/pdm360ng.c @@ -44,63 +44,6 @@ DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[]; ulong flash_get_size (phys_addr_t base, int banknum); -/* Clocks in use */ -#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ - CLOCK_SCCR1_LPC_EN | \ - CLOCK_SCCR1_NFC_EN | \ - CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ - CLOCK_SCCR1_PSCFIFO_EN | \ - CLOCK_SCCR1_DDR_EN | \ - CLOCK_SCCR1_FEC_EN | \ - CLOCK_SCCR1_TPR_EN) - -#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN | \ - CLOCK_SCCR2_DIU_EN | \ - CLOCK_SCCR2_I2C_EN) - -int board_early_init_f(void) -{ - volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - - /* - * Initialize Local Window for FLASH-Bank1 access (CS1) - */ - out_be32(&im->sysconf.lpcs1aw, - CSAW_START(CONFIG_SYS_FLASH1_BASE) | - CSAW_STOP(CONFIG_SYS_FLASH1_BASE, CONFIG_SYS_FLASH_SIZE) - ); - out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG); - - /* - * Local Window for MRAM access (CS2) - */ - out_be32(&im->sysconf.lpcs2aw, - CSAW_START(CONFIG_SYS_MRAM_BASE) | - CSAW_STOP(CONFIG_SYS_MRAM_BASE, CONFIG_SYS_MRAM_SIZE) - ); - out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG); - - sync_law(&im->sysconf.lpcs2aw); - - /* - * Configure Flash Speed - */ - out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG); - out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING); - - /* - * Enable clocks - */ - out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN); - out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN); -#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE) - setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN); -#endif - - return 0; -} - sdram_conf_t mddrc_config[] = { { (512 << 20), /* 512 MB RAM configuration */ @@ -557,7 +500,6 @@ void ft_board_setup(void *blob, bd_t *bd) int rc, i = 0; ft_cpu_setup(blob, bd); - fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); #ifdef CONFIG_FDT_FIXUP_PARTITIONS fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); #endif diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 55bc018..43d7b6e 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -61,7 +61,7 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; static void rtc32k_enable(void) { - struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE; + struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; /* * Unlock the RTC's registers. For more details please see the @@ -104,7 +104,8 @@ static struct emif_regs ddr3_emif_reg_data = { .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2, .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3, .zq_config = MT41J256M8HX15E_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY, + .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, }; #endif @@ -159,7 +160,7 @@ void s_init(void) enable_board_pin_mux(); config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data, - &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data); + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); #endif } @@ -199,8 +200,8 @@ static struct cpsw_slave_data cpsw_slaves[] = { }; static struct cpsw_platform_data cpsw_data = { - .mdio_base = AM335X_CPSW_MDIO_BASE, - .cpsw_base = AM335X_CPSW_BASE, + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, .mdio_div = 0xff, .channels = 8, .cpdma_reg_ofs = 0x800, diff --git a/board/prodrive/p3mx/mpsc.c b/board/prodrive/p3mx/mpsc.c index cc05b45..c6a3af5 100644 --- a/board/prodrive/p3mx/mpsc.c +++ b/board/prodrive/p3mx/mpsc.c @@ -962,7 +962,7 @@ static int galmpsc_set_snoop (int mpsc, int value) * None. * * RETURN: -* True for success, false otherwise. +* true for success, false otherwise. * *******************************************************************************/ diff --git a/board/prodrive/p3mx/mv_eth.h b/board/prodrive/p3mx/mv_eth.h index 8cc00dc..58a8cb9 100644 --- a/board/prodrive/p3mx/mv_eth.h +++ b/board/prodrive/p3mx/mv_eth.h @@ -47,13 +47,6 @@ ************************************************************************** ************************************************************************** *************************************************************************/ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */ #ifndef MAX_SKB_FRAGS #define MAX_SKB_FRAGS 0 diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds index c2ec827..3334a44 100644 --- a/board/quantum/u-boot.lds +++ b/board/quantum/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/quantum/u-boot.lds.debug b/board/quantum/u-boot.lds.debug index abc4640..c4cc39d 100644 --- a/board/quantum/u-boot.lds.debug +++ b/board/quantum/u-boot.lds.debug @@ -125,6 +125,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds index 9262aa5..ef3a17f 100644 --- a/board/r360mpi/u-boot.lds +++ b/board/r360mpi/u-boot.lds @@ -95,7 +95,7 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); . = ALIGN(128 * 1024); .ppcenv : diff --git a/board/raspberrypi/rpi_b/rpi_b.c b/board/raspberrypi/rpi_b/rpi_b.c index 688b0aa..6b3e095 100644 --- a/board/raspberrypi/rpi_b/rpi_b.c +++ b/board/raspberrypi/rpi_b/rpi_b.c @@ -15,13 +15,39 @@ */ #include <common.h> +#include <asm/arch/mbox.h> +#include <asm/arch/sdhci.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; +struct msg_get_arm_mem { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_get_arm_mem get_arm_mem; + u32 end_tag; +}; + +struct msg_get_clock_rate { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_get_clock_rate get_clock_rate; + u32 end_tag; +}; + int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + ALLOC_ALIGN_BUFFER(struct msg_get_arm_mem, msg, 1, 16); + int ret; + + BCM2835_MBOX_INIT_HDR(msg); + BCM2835_MBOX_INIT_TAG(&msg->get_arm_mem, GET_ARM_MEMORY); + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg->hdr); + if (ret) { + printf("bcm2835: Could not query ARM memory size\n"); + return -1; + } + + gd->ram_size = msg->get_arm_mem.body.resp.mem_size; return 0; } @@ -32,3 +58,22 @@ int board_init(void) return 0; } + +int board_mmc_init(void) +{ + ALLOC_ALIGN_BUFFER(struct msg_get_clock_rate, msg_clk, 1, 16); + int ret; + + BCM2835_MBOX_INIT_HDR(msg_clk); + BCM2835_MBOX_INIT_TAG(&msg_clk->get_clock_rate, GET_CLOCK_RATE); + msg_clk->get_clock_rate.body.req.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC; + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_clk->hdr); + if (ret) { + printf("bcm2835: Could not query eMMC clock rate\n"); + return -1; + } + + return bcm2835_sdhci_init(BCM2835_SDHCI_BASE, + msg_clk->get_clock_rate.body.resp.rate_hz); +} diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds index c6560c6..b354409 100644 --- a/board/rbc823/u-boot.lds +++ b/board/rbc823/u-boot.lds @@ -103,6 +103,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/renesas/sh7752evb/u-boot.lds b/board/renesas/sh7752evb/u-boot.lds index 5bbb63f..276f525 100644 --- a/board/renesas/sh7752evb/u-boot.lds +++ b/board/renesas/sh7752evb/u-boot.lds @@ -93,5 +93,5 @@ SECTIONS } PROVIDE (bss_end = .); - PROVIDE (__bss_end__ = .); + PROVIDE (__bss_end = .); } diff --git a/board/renesas/sh7757lcr/u-boot.lds b/board/renesas/sh7757lcr/u-boot.lds index 0717d04..5882427 100644 --- a/board/renesas/sh7757lcr/u-boot.lds +++ b/board/renesas/sh7757lcr/u-boot.lds @@ -94,5 +94,5 @@ SECTIONS } PROVIDE (bss_end = .); - PROVIDE (__bss_end__ = .); + PROVIDE (__bss_end = .); } diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds index 4662546..240b936 100644 --- a/board/rsdproto/u-boot.lds +++ b/board/rsdproto/u-boot.lds @@ -125,6 +125,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/sacsng/clkinit.c b/board/sacsng/clkinit.c index 4a7f362..3894a5c 100644 --- a/board/sacsng/clkinit.c +++ b/board/sacsng/clkinit.c @@ -94,11 +94,11 @@ uint Daq_BRG_Get_Div16(uint brg) if (*brg_ptr & CPM_BRG_DIV16) { /* DIV16 active */ - return (TRUE); + return true; } else { /* DIV16 inactive */ - return (FALSE); + return false; } } diff --git a/board/sacsng/clkinit.h b/board/sacsng/clkinit.h index 011638f..68d69db 100644 --- a/board/sacsng/clkinit.h +++ b/board/sacsng/clkinit.h @@ -22,11 +22,6 @@ * MA 02111-1307 USA */ -#ifndef FALSE -#define FALSE 0 -#define TRUE (!FALSE) -#endif - #define SLRCLK_EN_MASK 0x00040000 /* PA13 - SLRCLK_EN* */ #define MIN_SAMPLE_RATE 4000 /* Minimum sample rate */ diff --git a/board/samsung/dts/exynos5250-smdk5250.dts b/board/samsung/dts/exynos5250-smdk5250.dts index cbfab6f..8da973b 100644 --- a/board/samsung/dts/exynos5250-smdk5250.dts +++ b/board/samsung/dts/exynos5250-smdk5250.dts @@ -66,4 +66,57 @@ compatible = "maxim,max77686_pmic"; }; }; + + tmu@10060000 { + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; + }; + + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <2560>; + samsung,vl-row = <1600>; + samsung,vl-width = <2560>; + samsung,vl-height = <1600>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <32>; + samsung,vl-hbpd = <80>; + samsung,vl-hfpd = <48>; + samsung,vl-vspw = <6>; + samsung,vl-vbpd = <37>; + samsung,vl-vfpd = <3>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; + + dp@145b0000 { + samsung,lt-status = <0>; + + samsung,master-mode = <0>; + samsung,bist-mode = <0>; + samsung,bist-pattern = <0>; + samsung,h-sync-polarity = <0>; + samsung,v-sync-polarity = <0>; + samsung,interlaced = <0>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + }; }; diff --git a/board/samsung/dts/exynos5250-snow.dts b/board/samsung/dts/exynos5250-snow.dts new file mode 100644 index 0000000..8b303bf --- /dev/null +++ b/board/samsung/dts/exynos5250-snow.dts @@ -0,0 +1,58 @@ +/* + * SAMSUNG Snow board device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +/dts-v1/; +/include/ ARCH_CPU_DTS + +/ { + model = "Google Snow"; + compatible = "google,snow", "samsung,exynos5250"; + + aliases { + i2c0 = "/i2c@12c60000"; + i2c1 = "/i2c@12c70000"; + i2c2 = "/i2c@12c80000"; + i2c3 = "/i2c@12c90000"; + i2c4 = "/i2c@12ca0000"; + i2c5 = "/i2c@12cb0000"; + i2c6 = "/i2c@12cc0000"; + i2c7 = "/i2c@12cd0000"; + spi0 = "/spi@12d20000"; + spi1 = "/spi@12d30000"; + spi2 = "/spi@12d40000"; + spi3 = "/spi@131a0000"; + spi4 = "/spi@131b0000"; + }; + + sound@12d60000 { + samsung,i2s-epll-clock-frequency = <192000000>; + samsung,i2s-sampling-rate = <48000>; + samsung,i2s-bits-per-sample = <16>; + samsung,i2s-channels = <2>; + samsung,i2s-lr-clk-framesize = <256>; + samsung,i2s-bit-clk-framesize = <32>; + samsung,codec-type = "max98095"; + }; + + i2c@12cd0000 { + soundcodec@22 { + reg = <0x22>; + compatible = "maxim,max98095-codec"; + }; + }; + + i2c@12c60000 { + pmic@9 { + reg = <0x9>; + compatible = "maxim,max77686_pmic"; + }; + }; +}; diff --git a/board/samsung/smdk5250/clock_init.c b/board/samsung/smdk5250/clock_init.c index c009ae5..5b9e82f 100644 --- a/board/samsung/smdk5250/clock_init.c +++ b/board/samsung/smdk5250/clock_init.c @@ -434,10 +434,10 @@ void system_clock_init() val = readl(&clk->mux_stat_core1); } while ((val | MUX_MPLL_SEL_MASK) != val); - clrbits_le32(&clk->src_core1, MUX_CPLL_SEL_MASK); - clrbits_le32(&clk->src_core1, MUX_EPLL_SEL_MASK); - clrbits_le32(&clk->src_core1, MUX_VPLL_SEL_MASK); - clrbits_le32(&clk->src_core1, MUX_GPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK); + clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK); tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK | MUX_GPLL_SEL_MASK; do { @@ -494,35 +494,35 @@ void system_clock_init() val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, arm_clk_ratio->apll_sdiv); writel(val, &clk->apll_con0); - while (readl(&clk->apll_con0) & APLL_CON0_LOCKED) + while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0) ; /* Set MPLL */ writel(MPLL_CON1_VAL, &clk->mpll_con1); val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); writel(val, &clk->mpll_con0); - while (readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) + while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0) ; /* Set BPLL */ writel(BPLL_CON1_VAL, &clk->bpll_con1); val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); writel(val, &clk->bpll_con0); - while (readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) + while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0) ; /* Set CPLL */ writel(CPLL_CON1_VAL, &clk->cpll_con1); val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); writel(val, &clk->cpll_con0); - while (readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) + while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0) ; /* Set GPLL */ writel(GPLL_CON1_VAL, &clk->gpll_con1); val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); writel(val, &clk->gpll_con0); - while (readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) + while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0) ; /* Set EPLL */ @@ -530,7 +530,7 @@ void system_clock_init() writel(EPLL_CON1_VAL, &clk->epll_con1); val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); writel(val, &clk->epll_con0); - while (readl(&clk->epll_con0) & EPLL_CON0_LOCKED) + while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0) ; /* Set VPLL */ @@ -538,7 +538,7 @@ void system_clock_init() writel(VPLL_CON1_VAL, &clk->vpll_con1); val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); writel(val, &clk->vpll_con0); - while (readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) + while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0) ; writel(CLK_SRC_CORE0_VAL, &clk->src_core0); diff --git a/board/samsung/smdk5250/setup.h b/board/samsung/smdk5250/setup.h index a159601..34d8bc31 100644 --- a/board/samsung/smdk5250/setup.h +++ b/board/samsung/smdk5250/setup.h @@ -343,7 +343,7 @@ #define TOP2_VAL 0x0110000 /* CLK_SRC_PERIC0 */ -#define PWM_SEL 0 +#define PWM_SEL 6 #define UART3_SEL 6 #define UART2_SEL 6 #define UART1_SEL 6 diff --git a/board/samsung/smdk5250/smdk5250-uboot-spl.lds b/board/samsung/smdk5250/smdk5250-uboot-spl.lds index 4ef6a51..7df0a1d 100644 --- a/board/samsung/smdk5250/smdk5250-uboot-spl.lds +++ b/board/samsung/smdk5250/smdk5250-uboot-spl.lds @@ -37,7 +37,7 @@ SECTIONS .text : { __start = .; - arch/arm/cpu/armv7/start.o (.text) + arch/arm/cpu/armv7/start.o (.text*) *(.text*) } >.sram . = ALIGN(4); @@ -66,6 +66,6 @@ SECTIONS __bss_start = .; *(.bss*) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } >.sram } diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 7a5f132..8b09e1d 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -23,6 +23,7 @@ #include <common.h> #include <fdtdec.h> #include <asm/io.h> +#include <errno.h> #include <i2c.h> #include <lcd.h> #include <netdev.h> @@ -35,9 +36,40 @@ #include <asm/arch/sromc.h> #include <asm/arch/dp_info.h> #include <power/pmic.h> +#include <power/max77686_pmic.h> +#include <tmu.h> DECLARE_GLOBAL_DATA_PTR; +#if defined CONFIG_EXYNOS_TMU +/* + * Boot Time Thermal Analysis for SoC temperature threshold breach + */ +static void boot_temp_check(void) +{ + int temp; + + switch (tmu_monitor(&temp)) { + /* Status TRIPPED ans WARNING means corresponding threshold breach */ + case TMU_STATUS_TRIPPED: + puts("EXYNOS_TMU: TRIPPING! Device power going down ...\n"); + set_ps_hold_ctrl(); + hang(); + break; + case TMU_STATUS_WARNING: + puts("EXYNOS_TMU: WARNING! Temperature very high\n"); + break; + /* + * TMU_STATUS_INIT means something is wrong with temperature sensing + * and TMU status was changed back from NORMAL to INIT. + */ + case TMU_STATUS_INIT: + default: + debug("EXYNOS_TMU: Unknown TMU state\n"); + } +} +#endif + #ifdef CONFIG_USB_EHCI_EXYNOS int board_usb_vbus_init(void) { @@ -54,15 +86,39 @@ int board_usb_vbus_init(void) } #endif +#ifdef CONFIG_SOUND_MAX98095 +static void board_enable_audio_codec(void) +{ + struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) + samsung_get_base_gpio_part1(); + + /* Enable MAX98095 Codec */ + s5p_gpio_direction_output(&gpio1->x1, 7, 1); + s5p_gpio_set_pull(&gpio1->x1, 7, GPIO_PULL_NONE); +} +#endif + int board_init(void) { gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); + +#if defined CONFIG_EXYNOS_TMU + if (tmu_init(gd->fdt_blob) != TMU_STATUS_NORMAL) { + debug("%s: Failed to init TMU\n", __func__); + return -1; + } + boot_temp_check(); +#endif + #ifdef CONFIG_EXYNOS_SPI spi_init(); #endif #ifdef CONFIG_USB_EHCI_EXYNOS board_usb_vbus_init(); #endif +#ifdef CONFIG_SOUND_MAX98095 + board_enable_audio_codec(); +#endif return 0; } @@ -80,12 +136,119 @@ int dram_init(void) } #if defined(CONFIG_POWER) +static int pmic_reg_update(struct pmic *p, int reg, uint regval) +{ + u32 val; + int ret = 0; + + ret = pmic_reg_read(p, reg, &val); + if (ret) { + debug("%s: PMIC %d register read failed\n", __func__, reg); + return -1; + } + val |= regval; + ret = pmic_reg_write(p, reg, val); + if (ret) { + debug("%s: PMIC %d register write failed\n", __func__, reg); + return -1; + } + return 0; +} + int power_init_board(void) { + struct pmic *p; + + set_ps_hold_ctrl(); + + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (pmic_init(I2C_PMIC)) return -1; - else - return 0; + + p = pmic_get("MAX77686_PMIC"); + if (!p) + return -ENODEV; + + if (pmic_probe(p)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_32KHZ, MAX77686_32KHCP_EN)) + return -1; + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BBAT, + MAX77686_BBCHOSTEN | MAX77686_BBCVS_3_5V)) + return -1; + + /* VDD_MIF */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK1OUT, + MAX77686_BUCK1OUT_1V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK1OUT); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK1CRTL, + MAX77686_BUCK1CTRL_EN)) + return -1; + + /* VDD_ARM */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK2DVS1, + MAX77686_BUCK2DVS1_1_3V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK2DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK2CTRL1, + MAX77686_BUCK2CTRL_ON)) + return -1; + + /* VDD_INT */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK3DVS1, + MAX77686_BUCK3DVS1_1_0125V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK3DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK3CTRL, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_G3D */ + if (pmic_reg_write(p, MAX77686_REG_PMIC_BUCK4DVS1, + MAX77686_BUCK4DVS1_1_2V)) { + debug("%s: PMIC %d register write failed\n", __func__, + MAX77686_REG_PMIC_BUCK4DVS1); + return -1; + } + + if (pmic_reg_update(p, MAX77686_REG_PMIC_BUCK4CTRL1, + MAX77686_BUCK3CTRL_ON)) + return -1; + + /* VDD_LDO2 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO2CTRL1, + MAX77686_LD02CTRL1_1_5V | EN_LDO)) + return -1; + + /* VDD_LDO3 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO3CTRL1, + MAX77686_LD03CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO5 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO5CTRL1, + MAX77686_LD05CTRL1_1_8V | EN_LDO)) + return -1; + + /* VDD_LDO10 */ + if (pmic_reg_update(p, MAX77686_REG_PMIC_LDO10CTRL1, + MAX77686_LD10CTRL1_1_8V | EN_LDO)) + return -1; + + return 0; } #endif @@ -149,9 +312,10 @@ int board_eth_init(bd_t *bis) u32 smc_bw_conf, smc_bc_conf; struct fdt_sromc config; fdt_addr_t base_addr; - int node; #ifdef CONFIG_OF_CONTROL + int node; + node = decode_sromc(gd->fdt_blob, &config); if (node < 0) { debug("%s: Could not find sromc configuration\n", __func__); @@ -212,8 +376,17 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) { - printf("\nBoard: SMDK5250\n"); +#ifdef CONFIG_OF_CONTROL + const char *board_name; + board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + if (board_name == NULL) + printf("\nUnknown Board\n"); + else + printf("\nBoard: %s\n", board_name); +#else + printf("\nBoard: SMDK5250\n"); +#endif return 0; } #endif @@ -282,7 +455,7 @@ int board_early_init_f(void) #endif #ifdef CONFIG_LCD -void cfg_lcd_gpio(void) +void exynos_cfg_lcd_gpio(void) { struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); @@ -299,6 +472,12 @@ void cfg_lcd_gpio(void) s5p_gpio_cfg_pin(&gpio1->x0, 7, GPIO_FUNC(0x3)); } +void exynos_set_dp_phy(unsigned int onoff) +{ + set_dp_phy_ctrl(onoff); +} + +#ifndef CONFIG_OF_CONTROL vidinfo_t panel_info = { .vl_freq = 60, .vl_col = 2560, @@ -322,10 +501,6 @@ vidinfo_t panel_info = { .vl_cmd_allow_len = 0xf, .win_id = 3, - .cfg_gpio = cfg_lcd_gpio, - .backlight_on = NULL, - .lcd_power_on = NULL, - .reset_lcd = NULL, .dual_lcd_enabled = 0, .init_delay = 0, @@ -365,14 +540,16 @@ static struct edp_device_info edp_info = { }; static struct exynos_dp_platform_data dp_platform_data = { - .phy_enable = set_dp_phy_ctrl, .edp_dev_info = &edp_info, }; +#endif void init_panel_info(vidinfo_t *vid) { +#ifndef CONFIG_OF_CONTROL vid->rgb_mode = MODE_RGB_P, exynos_set_dp_platform_data(&dp_platform_data); +#endif } #endif diff --git a/board/samsung/smdk6400/.gitignore b/board/samsung/smdk6400/.gitignore deleted file mode 100644 index 25ab492..0000000 --- a/board/samsung/smdk6400/.gitignore +++ /dev/null @@ -1,5 +0,0 @@ -# -# Generated files -# - -/config.tmp diff --git a/board/samsung/smdk6400/Makefile b/board/samsung/smdk6400/Makefile deleted file mode 100644 index 0d3e63b..0000000 --- a/board/samsung/smdk6400/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2000, 2001, 2002 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y := smdk6400.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(SOBJS) $(OBJS) - $(call cmd_link_o_target, $(SOBJS) $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/samsung/smdk6400/config.mk b/board/samsung/smdk6400/config.mk deleted file mode 100644 index 6f04c2f..0000000 --- a/board/samsung/smdk6400/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> -# -# (C) Copyright 2008 -# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> -# -# SAMSUNG SMDK6400 board with mDirac3 (ARM1176) cpu -# -# see http://www.samsung.com/ for more information on SAMSUNG - -# On SMDK6400 we use the 64 MB SDRAM bank at -# -# 0x50000000 to 0x58000000 -# -# Linux-Kernel is expected to be at 0x50008000, entry 0x50008000 -# -# we load ourselves to 0x57e00000 without MMU -# with MMU, load address is changed to 0xc7e00000 -# -# download area is 0x5000c000 - -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -ifndef CONFIG_NAND_SPL -CONFIG_SYS_TEXT_BASE = $(RAM_TEXT) -else -CONFIG_SYS_TEXT_BASE = 0 -endif diff --git a/board/samsung/smdk6400/lowlevel_init.S b/board/samsung/smdk6400/lowlevel_init.S deleted file mode 100644 index f7ce176..0000000 --- a/board/samsung/smdk6400/lowlevel_init.S +++ /dev/null @@ -1,323 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <config.h> -#include <version.h> - -#include <asm/arch/s3c6400.h> - -#ifdef CONFIG_SERIAL1 -#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET) -#elif defined(CONFIG_SERIAL2) -#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET) -#else -#define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET) -#endif - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - - .globl lowlevel_init -lowlevel_init: - mov r12, lr - - /* LED on only #8 */ - ldr r0, =ELFIN_GPIO_BASE - ldr r1, =0x55540000 - str r1, [r0, #GPNCON_OFFSET] - - ldr r1, =0x55555555 - str r1, [r0, #GPNPUD_OFFSET] - - ldr r1, =0xf000 - str r1, [r0, #GPNDAT_OFFSET] - - /* Disable Watchdog */ - ldr r0, =0x7e000000 @0x7e004000 - orr r0, r0, #0x4000 - mov r1, #0 - str r1, [r0] - - /* External interrupt pending clear */ - ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/ - ldr r1, [r0] - str r1, [r0] - - ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000 - ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000 - - /* Disable all interrupts (VIC0 and VIC1) */ - mvn r3, #0x0 - str r3, [r0, #oINTMSK] - str r3, [r1, #oINTMSK] - - /* Set all interrupts as IRQ */ - mov r3, #0x0 - str r3, [r0, #oINTMOD] - str r3, [r1, #oINTMOD] - - /* Pending Interrupt Clear */ - mov r3, #0x0 - str r3, [r0, #oVECTADDR] - str r3, [r1, #oVECTADDR] - - /* init system clock */ - bl system_clock_init - -#ifndef CONFIG_NAND_SPL - /* for UART */ - bl uart_asm_init -#endif - -#ifdef CONFIG_BOOT_NAND - /* simple init for NAND */ - bl nand_asm_init -#endif - - /* Memory subsystem address 0x7e00f120 */ - ldr r0, =ELFIN_MEM_SYS_CFG - - /* Xm0CSn2 = NFCON CS0, Xm0CSn3 = NFCON CS1 */ - mov r1, #S3C64XX_MEM_SYS_CFG_NAND - str r1, [r0] - - bl mem_ctrl_asm_init - -/* Wakeup support. Don't know if it's going to be used, untested. */ - ldr r0, =(ELFIN_CLOCK_POWER_BASE + RST_STAT_OFFSET) - ldr r1, [r0] - bic r1, r1, #0xfffffff7 - cmp r1, #0x8 - beq wakeup_reset - -1: - mov lr, r12 - mov pc, lr - -wakeup_reset: - - /* Clear wakeup status register */ - ldr r0, =(ELFIN_CLOCK_POWER_BASE + WAKEUP_STAT_OFFSET) - ldr r1, [r0] - str r1, [r0] - - /* LED test */ - ldr r0, =ELFIN_GPIO_BASE - ldr r1, =0x3000 - str r1, [r0, #GPNDAT_OFFSET] - - /* Load return address and jump to kernel */ - ldr r0, =(ELFIN_CLOCK_POWER_BASE + INF_REG0_OFFSET) - /* r1 = physical address of s3c6400_cpu_resume function */ - ldr r1, [r0] - /* Jump to kernel (sleep-s3c6400.S) */ - mov pc, r1 - nop - nop -/* - * system_clock_init: Initialize core clock and bus clock. - * void system_clock_init(void) - */ -system_clock_init: - ldr r0, =ELFIN_CLOCK_POWER_BASE /* 0x7e00f000 */ - -#ifdef CONFIG_SYNC_MODE - ldr r1, [r0, #OTHERS_OFFSET] - mov r2, #0x40 - orr r1, r1, r2 - str r1, [r0, #OTHERS_OFFSET] - - nop - nop - nop - nop - nop - - ldr r2, =0x80 - orr r1, r1, r2 - str r1, [r0, #OTHERS_OFFSET] - -check_syncack: - ldr r1, [r0, #OTHERS_OFFSET] - ldr r2, =0xf00 - and r1, r1, r2 - cmp r1, #0xf00 - bne check_syncack -#else /* ASYNC Mode */ - nop - nop - nop - nop - nop - - /* - * This was unconditional in original Samsung sources, but it doesn't - * seem to make much sense on S3C6400. - */ -#ifndef CONFIG_S3C6400 - ldr r1, [r0, #OTHERS_OFFSET] - bic r1, r1, #0xC0 - orr r1, r1, #0x40 - str r1, [r0, #OTHERS_OFFSET] - -wait_for_async: - ldr r1, [r0, #OTHERS_OFFSET] - and r1, r1, #0xf00 - cmp r1, #0x0 - bne wait_for_async -#endif - - ldr r1, [r0, #OTHERS_OFFSET] - bic r1, r1, #0x40 - str r1, [r0, #OTHERS_OFFSET] -#endif - - mov r1, #0xff00 - orr r1, r1, #0xff - str r1, [r0, #APLL_LOCK_OFFSET] - str r1, [r0, #MPLL_LOCK_OFFSET] - - /* Set Clock Divider */ - ldr r1, [r0, #CLK_DIV0_OFFSET] - bic r1, r1, #0x30000 - bic r1, r1, #0xff00 - bic r1, r1, #0xff - ldr r2, =CLK_DIV_VAL - orr r1, r1, r2 - str r1, [r0, #CLK_DIV0_OFFSET] - - ldr r1, =APLL_VAL - str r1, [r0, #APLL_CON_OFFSET] - ldr r1, =MPLL_VAL - str r1, [r0, #MPLL_CON_OFFSET] - - /* FOUT of EPLL is 96MHz */ - ldr r1, =0x200203 - str r1, [r0, #EPLL_CON0_OFFSET] - ldr r1, =0x0 - str r1, [r0, #EPLL_CON1_OFFSET] - - /* APLL, MPLL, EPLL select to Fout */ - ldr r1, [r0, #CLK_SRC_OFFSET] - orr r1, r1, #0x7 - str r1, [r0, #CLK_SRC_OFFSET] - - /* wait at least 200us to stablize all clock */ - mov r1, #0x10000 -1: subs r1, r1, #1 - bne 1b - - /* Synchronization for VIC port */ -#if defined(CONFIG_SYNC_MODE) - ldr r1, [r0, #OTHERS_OFFSET] - orr r1, r1, #0x20 - str r1, [r0, #OTHERS_OFFSET] -#elif !defined(CONFIG_S3C6400) - /* According to 661558um_S3C6400X_rev10.pdf 0x20 is reserved */ - ldr r1, [r0, #OTHERS_OFFSET] - bic r1, r1, #0x20 - str r1, [r0, #OTHERS_OFFSET] -#endif - mov pc, lr - - -#ifndef CONFIG_NAND_SPL -/* - * uart_asm_init: Initialize UART's pins - */ -uart_asm_init: - /* set GPIO to enable UART */ - ldr r0, =ELFIN_GPIO_BASE - ldr r1, =0x220022 - str r1, [r0, #GPACON_OFFSET] - mov pc, lr -#endif - -#ifdef CONFIG_BOOT_NAND -/* - * NAND Interface init for SMDK6400 - */ -nand_asm_init: - ldr r0, =ELFIN_NAND_BASE - ldr r1, [r0, #NFCONF_OFFSET] - orr r1, r1, #0x70 - orr r1, r1, #0x7700 - str r1, [r0, #NFCONF_OFFSET] - - ldr r1, [r0, #NFCONT_OFFSET] - orr r1, r1, #0x07 - str r1, [r0, #NFCONT_OFFSET] - - mov pc, lr -#endif - -#ifdef CONFIG_ENABLE_MMU -/* - * MMU Table for SMDK6400 - */ - - /* form a first-level section entry */ -.macro FL_SECTION_ENTRY base,ap,d,c,b - .word (\base << 20) | (\ap << 10) | \ - (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1) -.endm - -.section .mmudata, "a" - .align 14 - /* the following alignment creates the mmu table at address 0x4000. */ - .globl mmu_table -mmu_table: - .set __base, 0 - /* 1:1 mapping for debugging */ - .rept 0xA00 - FL_SECTION_ENTRY __base, 3, 0, 0, 0 - .set __base, __base + 1 - .endr - - /* access is not allowed. */ - .rept 0xC00 - 0xA00 - .word 0x00000000 - .endr - - /* 128MB for SDRAM 0xC0000000 -> 0x50000000 */ - .set __base, 0x500 - .rept 0xC80 - 0xC00 - FL_SECTION_ENTRY __base, 3, 0, 1, 1 - .set __base, __base + 1 - .endr - - /* access is not allowed. */ - .rept 0x1000 - 0xc80 - .word 0x00000000 - .endr -#endif diff --git a/board/samsung/smdk6400/smdk6400.c b/board/samsung/smdk6400/smdk6400.c deleted file mode 100644 index c40d1f9..0000000 --- a/board/samsung/smdk6400/smdk6400.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#include <asm/arch/s3c6400.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -#define CS8900_Tacs 0x0 /* 0clk address set-up */ -#define CS8900_Tcos 0x4 /* 4clk chip selection set-up */ -#define CS8900_Tacc 0xE /* 14clk access cycle */ -#define CS8900_Tcoh 0x1 /* 1clk chip selection hold */ -#define CS8900_Tah 0x4 /* 4clk address holding time */ -#define CS8900_Tacp 0x6 /* 6clk page mode access cycle */ -#define CS8900_PMC 0x0 /* normal(1data)page mode configuration */ - -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" "subs %0, %1, #1\n" - "bne 1b" - : "=r" (loops) : "0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -static void cs8900_pre_init(void) -{ - SROM_BW_REG &= ~(0xf << 4); - SROM_BW_REG |= (1 << 7) | (1 << 6) | (1 << 4); - SROM_BC1_REG = ((CS8900_Tacs << 28) + (CS8900_Tcos << 24) + - (CS8900_Tacc << 16) + (CS8900_Tcoh << 12) + - (CS8900_Tah << 8) + (CS8900_Tacp << 4) + CS8900_PMC); -} - -int board_init(void) -{ - cs8900_pre_init(); - - /* NOR-flash in SROM0 */ - - /* Enable WAIT */ - SROM_BW_REG |= 4 | 8 | 1; - - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -} - -int dram_init(void) -{ - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - - return 0; -} - -#ifdef CONFIG_DISPLAY_BOARDINFO -int checkboard(void) -{ - printf("Board: SMDK6400\n"); - return 0; -} -#endif - -#ifdef CONFIG_ENABLE_MMU -ulong virt_to_phy_smdk6400(ulong addr) -{ - if ((0xc0000000 <= addr) && (addr < 0xc8000000)) - return addr - 0xc0000000 + 0x50000000; - else - printf("do not support this address : %08lx\n", addr); - - return addr; -} -#endif - -ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info) -{ - if (banknum == 0) { /* non-CFI boot flash */ - info->portwidth = FLASH_CFI_16BIT; - info->chipwidth = FLASH_CFI_BY16; - info->interface = FLASH_CFI_X16; - return 1; - } else - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/samsung/smdk6400/u-boot-nand.lds b/board/samsung/smdk6400/u-boot-nand.lds deleted file mode 100644 index ae32b16..0000000 --- a/board/samsung/smdk6400/u-boot-nand.lds +++ /dev/null @@ -1,86 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/arm1176/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - - . = align(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = align(4); - .mmudata : { *(.mmudata) } - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 88d193d..e20fb3d 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -42,6 +42,7 @@ #include <power/max8997_muic.h> #include <power/battery.h> #include <power/max17042_fg.h> +#include <usb_mass_storage.h> #include "setup.h" @@ -634,7 +635,7 @@ int board_early_init_f(void) return 0; } -static void lcd_reset(void) +void exynos_reset_lcd(void) { struct exynos4_gpio_part2 *gpio2 = (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); @@ -754,10 +755,6 @@ vidinfo_t panel_info = { .vl_cmd_allow_len = 0xf, .win_id = 3, - .cfg_gpio = NULL, - .backlight_on = NULL, - .lcd_power_on = NULL, /* lcd_power_on in mipi dsi driver */ - .reset_lcd = lcd_reset, .dual_lcd_enabled = 0, .init_delay = 0, @@ -791,3 +788,65 @@ void init_panel_info(vidinfo_t *vid) setenv("lcdinfo", "lcd=s6e8ax0"); } + +#ifdef CONFIG_USB_GADGET_MASS_STORAGE +static int ums_read_sector(struct ums_device *ums_dev, + ulong start, lbaint_t blkcnt, void *buf) +{ + if (ums_dev->mmc->block_dev.block_read(ums_dev->dev_num, + start + ums_dev->offset, blkcnt, buf) != blkcnt) + return -1; + + return 0; +} + +static int ums_write_sector(struct ums_device *ums_dev, + ulong start, lbaint_t blkcnt, const void *buf) +{ + if (ums_dev->mmc->block_dev.block_write(ums_dev->dev_num, + start + ums_dev->offset, blkcnt, buf) != blkcnt) + return -1; + + return 0; +} + +static void ums_get_capacity(struct ums_device *ums_dev, + long long int *capacity) +{ + long long int tmp_capacity; + + tmp_capacity = (long long int) ((ums_dev->offset + ums_dev->part_size) + * SECTOR_SIZE); + *capacity = ums_dev->mmc->capacity - tmp_capacity; +} + +static struct ums_board_info ums_board = { + .read_sector = ums_read_sector, + .write_sector = ums_write_sector, + .get_capacity = ums_get_capacity, + .name = "TRATS UMS disk", + .ums_dev = { + .mmc = NULL, + .dev_num = 0, + .offset = 0, + .part_size = 0. + }, +}; + +struct ums_board_info *board_ums_init(unsigned int dev_num, unsigned int offset, + unsigned int part_size) +{ + struct mmc *mmc; + + mmc = find_mmc_device(dev_num); + if (!mmc) + return NULL; + + ums_board.ums_dev.mmc = mmc; + ums_board.ums_dev.dev_num = dev_num; + ums_board.ums_dev.offset = offset; + ums_board.ums_dev.part_size = part_size; + + return &ums_board; +} +#endif diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index e742707..9b2770f 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -384,7 +384,7 @@ static void init_pmic_lcd(void) puts("LCD pmic initialisation error!\n"); } -static void lcd_cfg_gpio(void) +void exynos_cfg_lcd_gpio(void) { unsigned int i, f3_end = 4; @@ -423,7 +423,7 @@ static void lcd_cfg_gpio(void) spi_init(); } -static void reset_lcd(void) +void exynos_reset_lcd(void) { s5p_gpio_set_value(&gpio2->y4, 5, 1); udelay(10000); @@ -433,7 +433,7 @@ static void reset_lcd(void) udelay(100); } -static void lcd_power_on(void) +void exynos_lcd_power_on(void) { struct pmic *p = pmic_get("MAX8998_PMIC"); @@ -471,10 +471,6 @@ vidinfo_t panel_info = { .vl_cmd_allow_len = 0xf, .win_id = 0, - .cfg_gpio = lcd_cfg_gpio, - .backlight_on = NULL, - .lcd_power_on = lcd_power_on, - .reset_lcd = reset_lcd, .dual_lcd_enabled = 0, .init_delay = 0, @@ -484,6 +480,16 @@ vidinfo_t panel_info = { .mipi_enabled = 0, }; +void exynos_cfg_ldo(void) +{ + ld9040_cfg_ldo(); +} + +void exynos_enable_ldo(unsigned int onoff) +{ + ld9040_enable_ldo(onoff); +} + void init_panel_info(vidinfo_t *vid) { vid->logo_on = 1; @@ -498,9 +504,6 @@ void init_panel_info(vidinfo_t *vid) vid->pclk_name = 1; /* MPLL */ vid->sclk_div = 1; - vid->cfg_ldo = ld9040_cfg_ldo; - vid->enable_ldo = ld9040_enable_ldo; - setenv("lcdinfo", "lcd=ld9040"); } diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug index 6b99f13..b3b365e 100644 --- a/board/sandburst/karef/u-boot.lds.debug +++ b/board/sandburst/karef/u-boot.lds.debug @@ -141,6 +141,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug index 0b4192e..412af14 100644 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ b/board/sandburst/metrobox/u-boot.lds.debug @@ -141,6 +141,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/sandpoint/u-boot.lds b/board/sandpoint/u-boot.lds index ca13619..95e13c4 100644 --- a/board/sandpoint/u-boot.lds +++ b/board/sandpoint/u-boot.lds @@ -95,6 +95,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds index fa4de9d..66c5fba 100644 --- a/board/sixnet/u-boot.lds +++ b/board/sixnet/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds index 5929335..285e897 100644 --- a/board/snmc/qs850/u-boot.lds +++ b/board/snmc/qs850/u-boot.lds @@ -96,6 +96,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds index c2ec827..3334a44 100644 --- a/board/snmc/qs860t/u-boot.lds +++ b/board/snmc/qs860t/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds index c2ec827..3334a44 100644 --- a/board/spc1920/u-boot.lds +++ b/board/spc1920/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds index b2ad343..58f2565 100644 --- a/board/spd8xx/u-boot.lds +++ b/board/spd8xx/u-boot.lds @@ -102,6 +102,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug index 063f2cc..1135117 100644 --- a/board/spd8xx/u-boot.lds.debug +++ b/board/spd8xx/u-boot.lds.debug @@ -133,6 +133,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c index 85eb31b..74baa3f 100644 --- a/board/spear/x600/fpga.c +++ b/board/spear/x600/fpga.c @@ -113,7 +113,7 @@ static int fpga_done_fn(int cookie) static int fpga_pre_config_fn(int cookie) { debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__); - fpga_reset(TRUE); + fpga_reset(true); return 0; } @@ -128,9 +128,9 @@ static int fpga_post_config_fn(int cookie) debug("%s:%d: FPGA post configuration\n", __func__, __LINE__); - fpga_reset(TRUE); + fpga_reset(true); udelay(100); - fpga_reset(FALSE); + fpga_reset(false); udelay(100); return rc; @@ -200,7 +200,7 @@ static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { static void fpga_serialslave_init(void) { debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__); - fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */ + fpga_pgm_fn(false, false, 0); /* make sure program pin is inactive */ } static int expi_setup(int freq) diff --git a/board/stx/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds index ddb5a72..03891e9 100644 --- a/board/stx/stxxtc/u-boot.lds +++ b/board/stx/stxxtc/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/stx/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug index e1fe052..5f74337 100644 --- a/board/stx/stxxtc/u-boot.lds.debug +++ b/board/stx/stxxtc/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds index ebfa890..99b8bfa 100644 --- a/board/svm_sc8xx/u-boot.lds +++ b/board/svm_sc8xx/u-boot.lds @@ -110,6 +110,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/svm_sc8xx/u-boot.lds.debug b/board/svm_sc8xx/u-boot.lds.debug index abc4640..c4cc39d 100644 --- a/board/svm_sc8xx/u-boot.lds.debug +++ b/board/svm_sc8xx/u-boot.lds.debug @@ -125,6 +125,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index d576786..8347cf9 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -179,9 +179,9 @@ int fpga_post_config_fn(int cookie) { debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__); - fpga_reset(TRUE); + fpga_reset(true); udelay(100); - fpga_reset(FALSE); + fpga_reset(false); return 0; } diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index f4b972b..b371376 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -134,7 +134,7 @@ static int read_eeprom(void) static void rtc32k_enable(void) { - struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE; + struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; /* * Unlock the RTC's registers. For more details please see the @@ -208,6 +208,14 @@ static const struct ddr_data ddr3_data = { .datadldiff0 = PHY_DLL_LOCK_DIFF, }; +static const struct ddr_data ddr3_beagleblack_data = { + .datardsratio0 = MT41K256M16HA125E_RD_DQS, + .datawdsratio0 = MT41K256M16HA125E_WR_DQS, + .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, + .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + static const struct ddr_data ddr3_evm_data = { .datardsratio0 = MT41J512M8RH125_RD_DQS, .datawdsratio0 = MT41J512M8RH125_WR_DQS, @@ -230,6 +238,20 @@ static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, }; +static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { + .cmd0csratio = MT41K256M16HA125E_RATIO, + .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, + .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd1csratio = MT41K256M16HA125E_RATIO, + .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, + .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, + + .cmd2csratio = MT41K256M16HA125E_RATIO, + .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, + .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, +}; + static const struct cmd_control ddr3_evm_cmd_ctrl_data = { .cmd0csratio = MT41J512M8RH125_RATIO, .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, @@ -251,7 +273,18 @@ static struct emif_regs ddr3_emif_reg_data = { .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, .zq_config = MT41J128MJT125_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY, + .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, +}; + +static struct emif_regs ddr3_beagleblack_emif_reg_data = { + .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, + .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, + .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, + .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, + .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, + .zq_config = MT41K256M16HA125E_ZQ_CFG, + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, }; static struct emif_regs ddr3_evm_emif_reg_data = { @@ -261,7 +294,8 @@ static struct emif_regs ddr3_evm_emif_reg_data = { .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, .zq_config = MT41J512M8RH125_ZQ_CFG, - .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY, + .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | + PHY_EN_DYN_PWRDN, }; #endif @@ -341,15 +375,20 @@ void s_init(void) gpio_direction_output(GPIO_DDR_VTT_EN, 1); } - if (board_is_evm_sk() || board_is_bone_lt()) + if (board_is_evm_sk()) config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, - &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data); + &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); + else if (board_is_bone_lt()) + config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE, + &ddr3_beagleblack_data, + &ddr3_beagleblack_cmd_ctrl_data, + &ddr3_beagleblack_emif_reg_data, 0); else if (board_is_evm_15_or_later()) config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, - &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data); + &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); else config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, - &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data); + &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); #endif } @@ -412,8 +451,8 @@ static struct cpsw_slave_data cpsw_slaves[] = { }; static struct cpsw_platform_data cpsw_data = { - .mdio_base = AM335X_CPSW_MDIO_BASE, - .cpsw_base = AM335X_CPSW_BASE, + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, .mdio_div = 0xff, .channels = 8, .cpdma_reg_ofs = 0x800, diff --git a/board/ti/omap2420h4/config.mk b/board/ti/omap2420h4/config.mk index ca5ebdf..e5dff69 100644 --- a/board/ti/omap2420h4/config.mk +++ b/board/ti/omap2420h4/config.mk @@ -14,7 +14,7 @@ # (mem base + reserved) # For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80e80000 +#CONFIG_SYS_TEXT_BASE = 0x80e80000 # Used with full SRAM boot. # This is either with a GP system or a signed boot image. @@ -24,5 +24,5 @@ CONFIG_SYS_TEXT_BASE = 0x80e80000 # Handy to get symbols to debug ROM version. #CONFIG_SYS_TEXT_BASE = 0x0 -#CONFIG_SYS_TEXT_BASE = 0x08000000 +CONFIG_SYS_TEXT_BASE = 0x08000000 #CONFIG_SYS_TEXT_BASE = 0x04000000 diff --git a/board/ti/omap2420h4/mem.c b/board/ti/omap2420h4/mem.c index c8b4186..ba3f12a 100644 --- a/board/ti/omap2420h4/mem.c +++ b/board/ti/omap2420h4/mem.c @@ -200,19 +200,6 @@ void do_sdrc_init(u32 offset, u32 early) __asm__ __volatile__("": : :"memory"); /* limit compiler scope */ - /* u-boot is compiled to run in DDR or SRAM at 8xxxxxxx or 4xxxxxxx. - * If we are running in flash prior to relocation and we use data - * here which is not pc relative we need to get the address correct. - * We need to find the current flash mapping to dress up the initial - * pointer load. As long as this is const data we should be ok. - */ - if((early) && running_in_flash()){ - sdata = (sdrc_data_t *)(((u32)sdata & 0x0003FFFF) | get_gpmc0_base()); - /* NOR internal boot offset is 0x4000 from xloader signature */ - if(running_from_internal_boot()) - sdata = (sdrc_data_t *)((u32)sdata + 0x4000); - } - if (!early && (((mtype = get_mem_type()) == DDR_COMBO)||(mtype == DDR_STACKED))) { if(mtype == DDR_COMBO){ pmask = BIT2;/* combo part has a shared CKE signal, can't use feature */ diff --git a/board/ti/omap2420h4/omap2420h4.c b/board/ti/omap2420h4/omap2420h4.c index 188e4ac..532e989 100644 --- a/board/ti/omap2420h4/omap2420h4.c +++ b/board/ti/omap2420h4/omap2420h4.c @@ -190,10 +190,10 @@ void ether_init (void) * Routine: dram_init * Description: sets uboots idea of sdram size **********************************************/ -int dram_init (void) +int dram_init(void) { unsigned int size0=0,size1=0; - u32 mtype, btype, rev; + u32 mtype, btype; u8 chg_on = 0x5; /* enable charge of back up battery */ u8 vmode_on = 0x8C; #define NOT_EARLY 0 @@ -202,7 +202,6 @@ int dram_init (void) btype = get_board_type(); mtype = get_mem_type(); - rev = get_cpu_rev(); display_board_info(btype); if (btype == BOARD_H4_MENELAUS){ @@ -217,15 +216,28 @@ int dram_init (void) size0 = get_sdr_cs_size(SDRC_CS0_OSET); size1 = get_sdr_cs_size(SDRC_CS1_OSET); - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, size0 + size1); + + return 0; +} + +void dram_init_banksize(void) +{ + unsigned int size0, size1; + u32 rev; + + rev = get_cpu_rev(); + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */ gd->bd->bi_dram[1].start = PHYS_SDRAM_2; else /* ES2 and above can remap at 32MB granularity */ gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; gd->bd->bi_dram[1].size = size1; - return 0; + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; } /********************************************************** diff --git a/board/ti/omap5912osk/config.mk b/board/ti/omap5912osk/config.mk index 0ed7d8a..5b8d952 100644 --- a/board/ti/omap5912osk/config.mk +++ b/board/ti/omap5912osk/config.mk @@ -14,17 +14,17 @@ # TI OSK board with OMAP5912 (ARM925EJS) cpu # see http://www.ti.com/ for more information on Texas Instruments # -# OSK has 1 bank of 256 MB SDRAM +# OSK has 1 bank of 32 MB SDRAM # Physical Address: -# 1000'0000 to 2000'0000 +# 1000'0000 to 1200'0000 # # # Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 # (mem base + reserved) # -# we load ourself to 1108'0000 +# When running from RAM use address 1108'0000, otherwise when +# booting from NOR flash link to address 0000'0000. # -# - -CONFIG_SYS_TEXT_BASE = 0x11080000 +CONFIG_SYS_TEXT_BASE = 0x00000000 +#CONFIG_SYS_TEXT_BASE = 0x11080000 diff --git a/board/ti/omap5912osk/lowlevel_init.S b/board/ti/omap5912osk/lowlevel_init.S index e60161e..ca7361e 100644 --- a/board/ti/omap5912osk/lowlevel_init.S +++ b/board/ti/omap5912osk/lowlevel_init.S @@ -306,6 +306,23 @@ common_tc: ldr r1, VAL_MPU_CNTL_TIMER str r1, [r0] + /* + * Setup a temporary stack + */ + ldr sp, SRAM_STACK + bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ + + /* + * Save the old lr(passed in ip) and the current lr to stack + */ + push {ip, lr} + + /* + * go setup pll, mux, memory + */ + bl s_init + pop {ip, pc} + /* back to arch calling code */ mov pc, lr @@ -470,6 +487,9 @@ VAL_ARM_IDLECT2: VAL_ARM_IDLECT3: .word 0x00000015 +SRAM_STACK: + .word CONFIG_SYS_INIT_SP_ADDR + /* command values */ .equ CMD_SDRAM_NOP, 0x00000000 .equ CMD_SDRAM_PRECHARGE, 0x00000001 diff --git a/board/ti/omap5912osk/omap5912osk.c b/board/ti/omap5912osk/omap5912osk.c index fac683a..9514071 100644 --- a/board/ti/omap5912osk/omap5912osk.c +++ b/board/ti/omap5912osk/omap5912osk.c @@ -66,6 +66,14 @@ int board_init (void) /* adress of boot parameters */ gd->bd->bi_boot_params = 0x10000100; + flash__init(); + ether__init(); + + return 0; +} + +void s_init(void) +{ /* Configure MUX settings */ set_muxconf_regs (); peripheral_power_enable (); @@ -75,10 +83,6 @@ int board_init (void) * ... rkw ... */ icache_enable (); - - flash__init (); - ether__init (); - return 0; } /****************************** @@ -128,14 +132,19 @@ void ether__init (void) Routine: Description: ******************************/ -int dram_init (void) +int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +} + /****************************************************** Routine: set_muxconf_regs Description: Setting up the configuration Mux registers diff --git a/board/ti/omap5_evm/Makefile b/board/ti/omap5_uevm/Makefile index fa81d64..fa81d64 100644 --- a/board/ti/omap5_evm/Makefile +++ b/board/ti/omap5_uevm/Makefile diff --git a/board/ti/omap5_evm/evm.c b/board/ti/omap5_uevm/evm.c index 55337c0..55337c0 100644 --- a/board/ti/omap5_evm/evm.c +++ b/board/ti/omap5_uevm/evm.c diff --git a/board/ti/omap5_evm/mux_data.h b/board/ti/omap5_uevm/mux_data.h index a82795d..a82795d 100644 --- a/board/ti/omap5_evm/mux_data.h +++ b/board/ti/omap5_uevm/mux_data.h diff --git a/board/pcippc2/Makefile b/board/ti/ti814x/Makefile index 6f0a928..09d2422 100644 --- a/board/pcippc2/Makefile +++ b/board/ti/ti814x/Makefile @@ -1,35 +1,28 @@ # -# (C) Copyright 2002-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Makefile # -# See file CREDITS for list of people who contributed to this -# project. +# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# This program is distributed "as is" WITHOUT ANY WARRANTY of any +# kind, whether express or implied; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS = $(BOARD).o cpc710_pci.o flash.o sconsole.o \ - fpga_serial.o pcippc2_fpga.o cpc710_init_ram.o i2c.o - -SOBJS = +ifdef CONFIG_SPL_BUILD +COBJS := mux.o +endif +COBJS += evm.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) @@ -37,6 +30,12 @@ SOBJS := $(addprefix $(obj),$(SOBJS)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + ######################################################################### # defines $(obj).depend target diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c new file mode 100644 index 0000000..446e36b --- /dev/null +++ b/board/ti/ti814x/evm.c @@ -0,0 +1,198 @@ +/* + * evm.c + * + * Board functions for TI814x EVM + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <errno.h> +#include <spl.h> +#include <asm/arch/cpu.h> +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/ddr_defs.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> +#include <asm/emif.h> +#include <asm/gpio.h> +#include "evm.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; +static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; +#endif + +/* UART Defines */ +#ifdef CONFIG_SPL_BUILD +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + +static void rtc32k_enable(void) +{ + struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; + + /* + * Unlock the RTC's registers. For more details please see the + * RTC_SS section of the TRM. In order to unlock we need to + * write these specific values (keys) in this order. + */ + writel(0x83e70b13, &rtc->kick0r); + writel(0x95a4f1e0, &rtc->kick1r); + + /* Enable the RTC 32K OSC by setting bits 3 and 6. */ + writel((1 << 3) | (1 << 6), &rtc->osc); +} + +static void uart_enable(void) +{ + u32 regVal; + + /* UART softreset */ + regVal = readl(&uart_base->uartsyscfg); + regVal |= UART_RESET; + writel(regVal, &uart_base->uartsyscfg); + while ((readl(&uart_base->uartsyssts) & + UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK) + ; + + /* Disable smart idle */ + regVal = readl(&uart_base->uartsyscfg); + regVal |= UART_SMART_IDLE_EN; + writel(regVal, &uart_base->uartsyscfg); +} + +static void wdt_disable(void) +{ + writel(0xAAAA, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x5555, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; +} + +static const struct cmd_control evm_ddr2_cctrl_data = { + .cmd0csratio = 0x80, + .cmd0dldiff = 0x04, + .cmd0iclkout = 0x00, + + .cmd1csratio = 0x80, + .cmd1dldiff = 0x04, + .cmd1iclkout = 0x00, + + .cmd2csratio = 0x80, + .cmd2dldiff = 0x04, + .cmd2iclkout = 0x00, +}; + +static const struct emif_regs evm_ddr2_emif0_regs = { + .sdram_config = 0x40801ab2, + .ref_ctrl = 0x10000c30, + .sdram_tim1 = 0x0aaaf552, + .sdram_tim2 = 0x043631d2, + .sdram_tim3 = 0x00000327, + .emif_ddr_phy_ctlr_1 = 0x00000007 +}; + +static const struct emif_regs evm_ddr2_emif1_regs = { + .sdram_config = 0x40801ab2, + .ref_ctrl = 0x10000c30, + .sdram_tim1 = 0x0aaaf552, + .sdram_tim2 = 0x043631d2, + .sdram_tim3 = 0x00000327, + .emif_ddr_phy_ctlr_1 = 0x00000007 +}; + +const struct dmm_lisa_map_regs evm_lisa_map_regs = { + .dmm_lisa_map_0 = 0x00000000, + .dmm_lisa_map_1 = 0x00000000, + .dmm_lisa_map_2 = 0x806c0300, + .dmm_lisa_map_3 = 0x806c0300, +}; + +static const struct ddr_data evm_ddr2_data = { + .datardsratio0 = ((0x35<<10) | (0x35<<0)), + .datawdsratio0 = ((0x20<<10) | (0x20<<0)), + .datawiratio0 = ((0<<10) | (0<<0)), + .datagiratio0 = ((0<<10) | (0<<0)), + .datafwsratio0 = ((0x90<<10) | (0x90<<0)), + .datawrsratio0 = ((0x50<<10) | (0x50<<0)), + .datauserank0delay = 1, + .datadldiff0 = 0x4, +}; +#endif + +/* + * early system init of muxing and clocks. + */ +void s_init(void) +{ +#ifdef CONFIG_SPL_BUILD + /* WDT1 is already running when the bootloader gets control + * Disable it to avoid "random" resets + */ + wdt_disable(); + + /* Setup the PLLs and the clocks for the peripherals */ + pll_init(); + + /* Enable RTC32K clock */ + rtc32k_enable(); + + /* Set UART pins */ + enable_uart0_pin_mux(); + + /* Set MMC pins */ + enable_mmc1_pin_mux(); + + /* Enable UART */ + uart_enable(); + + gd = &gdata; + + preloader_console_init(); + + config_dmm(&evm_lisa_map_regs); + + config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, + &evm_ddr2_emif0_regs, 0); + config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, + &evm_ddr2_emif1_regs, 1); +#endif +} + +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100; + return 0; +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(1, 0, 0, -1, -1); + + return 0; +} +#endif diff --git a/board/ti/ti814x/evm.h b/board/ti/ti814x/evm.h new file mode 100644 index 0000000..40f8710 --- /dev/null +++ b/board/ti/ti814x/evm.h @@ -0,0 +1,7 @@ +#ifndef _EVM_H +#define _EVM_H + +void enable_uart0_pin_mux(void); +void enable_mmc1_pin_mux(void); + +#endif /* _EVM_H */ diff --git a/board/ti/ti814x/mux.c b/board/ti/ti814x/mux.c new file mode 100644 index 0000000..137acb4 --- /dev/null +++ b/board/ti/ti814x/mux.c @@ -0,0 +1,51 @@ +/* + * mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/hardware.h> +#include <asm/arch/mux.h> +#include <asm/io.h> +#include <i2c.h> +#include "evm.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(pincntl70), PULLUP_EN | MODE(0x01)}, /* UART0_RXD */ + {OFFSET(pincntl71), PULLUP_EN | MODE(0x01)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux mmc1_pin_mux[] = { + {OFFSET(pincntl1), PULLUP_EN | MODE(0x01)}, /* SD1_CLK */ + {OFFSET(pincntl2), PULLUP_EN | MODE(0x01)}, /* SD1_CMD */ + {OFFSET(pincntl3), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[0] */ + {OFFSET(pincntl4), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[1] */ + {OFFSET(pincntl5), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[2] */ + {OFFSET(pincntl6), PULLUP_EN | MODE(0x01)}, /* SD1_DAT[3] */ + {OFFSET(pincntl74), PULLUP_EN | MODE(0x40)}, /* SD1_POW */ + {OFFSET(pincntl75), MODE(0x40)}, /* SD1_SDWP */ + {OFFSET(pincntl80), PULLUP_EN | MODE(0x02)}, /* SD1_SDCD */ + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_mmc1_pin_mux(void) +{ + configure_module_pin_mux(mmc1_pin_mux); +} diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index bab452c..fbf321d 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -106,6 +106,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds index 9504fcd..f25a01b 100644 --- a/board/v37/u-boot.lds +++ b/board/v37/u-boot.lds @@ -93,6 +93,6 @@ SECTIONS *(COMMON) . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds index 1958c2f..61d1154 100644 --- a/board/vpac270/u-boot-spl.lds +++ b/board/vpac270/u-boot-spl.lds @@ -54,11 +54,13 @@ SECTIONS . = ALIGN(4); .data : { - *(.data) + *(.data*) } . = ALIGN(4); + __image_copy_end = .; + .rel.dyn : { __rel_dyn_start = .; *(.rel*) @@ -76,9 +78,9 @@ SECTIONS .bss __rel_dyn_start (OVERLAY) : { __bss_start = .; - *(.bss) + *(.bss*) . = ALIGN(4); - __bss_end__ = .; + __bss_end = .; } /DISCARD/ : { *(.bss*) } diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug index 18b7752..5792bac 100644 --- a/board/w7o/u-boot.lds.debug +++ b/board/w7o/u-boot.lds.debug @@ -132,6 +132,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c index 5b044a9..7c36af0 100644 --- a/board/woodburn/woodburn.c +++ b/board/woodburn/woodburn.c @@ -148,7 +148,7 @@ void board_init_f(ulong dummy) woodburn_init(); /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end__ - __bss_start); + memset(__bss_start, 0, __bss_end - __bss_start); /* Set global data pointer. */ gd = &gdata; diff --git a/board/xes/xpedite1000/u-boot.lds.debug b/board/xes/xpedite1000/u-boot.lds.debug index c02581d..cb26f0d 100644 --- a/board/xes/xpedite1000/u-boot.lds.debug +++ b/board/xes/xpedite1000/u-boot.lds.debug @@ -137,6 +137,6 @@ SECTIONS *(.bss) *(COMMON) } - __bss_end__ = . ; + __bss_end = . ; PROVIDE (end = .); } @@ -45,7 +45,7 @@ imx31_phycore arm arm1136 - - imx31_phycore_eet arm arm1136 imx31_phycore - mx31 imx31_phycore:IMX31_PHYCORE_EET qong arm arm1136 - davedenx mx31 mx31ads arm arm1136 - freescale mx31 -mx31pdk arm arm1136 - freescale mx31 mx31pdk:NAND_U_BOOT +mx31pdk arm arm1136 - freescale mx31 tt01 arm arm1136 - hale mx31 imx31_litekit arm arm1136 - logicpd mx31 flea3 arm arm1136 - CarMediaLab mx35 @@ -163,6 +163,7 @@ lsxhl arm arm926ejs lsxl buffalo km_kirkwood arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD km_kirkwood_pci arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_KIRKWOOD_PCI kmnusa arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_NUSA +kmsuv31 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_SUV31 mgcoge3un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_MGCOGE3UN kmcoge5un arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_COGE5UN portl2 arm arm926ejs km_arm keymile kirkwood km_kirkwood:KM_PORTL2 @@ -242,6 +243,7 @@ am335x_evm_uart3 arm armv7 am335x ti am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5 am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6 am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT +ti814x_evm arm armv7 ti814x ti am33xx pcm051 arm armv7 pcm051 phytec am33xx pcm051 highbank arm armv7 highbank - highbank mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg @@ -294,12 +296,13 @@ twister arm armv7 twister technex nokia_rx51 arm armv7 rx51 nokia omap3 omap4_panda arm armv7 panda ti omap4 omap4_sdp4430 arm armv7 sdp4430 ti omap4 -omap5_evm arm armv7 omap5_evm ti omap5 +omap5_uevm arm armv7 omap5_uevm ti omap5 dra7xx_evm arm armv7 dra7xx ti omap5 s5p_goni arm armv7 goni samsung s5pc1xx smdkc100 arm armv7 smdkc100 samsung s5pc1xx origen arm armv7 origen samsung exynos s5pc210_universal arm armv7 universal_c210 samsung exynos +snow arm armv7 smdk5250 samsung exynos smdk5250 arm armv7 smdk5250 samsung exynos smdkv310 arm armv7 smdkv310 samsung exynos trats arm armv7 trats samsung exynos @@ -480,8 +483,6 @@ openrisc-generic openrisc or1200 openrisc-generic openris EVB64260 powerpc 74xx_7xx evb64260 - - EVB64260 EVB64260_750CX powerpc 74xx_7xx evb64260 - - EVB64260 P3G4 powerpc 74xx_7xx evb64260 -PCIPPC2 powerpc 74xx_7xx pcippc2 -PCIPPC6 powerpc 74xx_7xx pcippc2 ppmc7xx powerpc 74xx_7xx ZUMA powerpc 74xx_7xx evb64260 ELPPC powerpc 74xx_7xx elppc eltec @@ -496,10 +497,12 @@ aria powerpc mpc512x - daveden mecp5123 powerpc mpc512x - esd mpc5121ads powerpc mpc512x mpc5121ads freescale mpc5121ads_rev2 powerpc mpc512x mpc5121ads freescale - mpc5121ads:MPC5121ADS_REV2 +ac14xx powerpc mpc512x ac14xx ifm cmi_mpc5xx powerpc mpc5xx cmi PATI powerpc mpc5xx pati mpl a3m071 powerpc mpc5xxx a3m071 a4m072 powerpc mpc5xxx a4m072 +a4m2k powerpc mpc5xxx a3m071 - - a3m071:A4M2K BC3450 powerpc mpc5xxx bc3450 canmb powerpc mpc5xxx cm5200 powerpc mpc5xxx diff --git a/common/Makefile b/common/Makefile index 719fc23..0e0fff1 100644 --- a/common/Makefile +++ b/common/Makefile @@ -36,6 +36,10 @@ COBJS-y += s_record.o COBJS-y += xyzModem.o COBJS-y += cmd_disk.o +# boards +COBJS-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o +COBJS-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o + # core command COBJS-y += cmd_boot.o COBJS-$(CONFIG_CMD_BOOTM) += cmd_bootm.o @@ -62,6 +66,7 @@ COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o COBJS-$(CONFIG_ENV_IS_IN_REMOTE) += env_remote.o +COBJS-$(CONFIG_ENV_IS_IN_UBI) += env_ubi.o COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o # command @@ -71,6 +76,7 @@ COBJS-$(CONFIG_CMD_SOURCE) += cmd_source.o COBJS-$(CONFIG_CMD_BDI) += cmd_bdinfo.o COBJS-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o COBJS-$(CONFIG_CMD_BMP) += cmd_bmp.o +COBJS-$(CONFIG_CMD_BOOTMENU) += cmd_bootmenu.o COBJS-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o COBJS-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o COBJS-$(CONFIG_CMD_CACHE) += cmd_cache.o @@ -175,6 +181,7 @@ COBJS-y += cmd_usb.o COBJS-y += usb.o usb_hub.o COBJS-$(CONFIG_USB_STORAGE) += usb_storage.o endif +COBJS-$(CONFIG_CMD_USB_MASS_STORAGE) += cmd_usb_mass_storage.o COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o COBJS-$(CONFIG_CMD_SPL) += cmd_spl.o diff --git a/common/bedbug.c b/common/bedbug.c index 60109cf..42ecf61 100644 --- a/common/bedbug.c +++ b/common/bedbug.c @@ -72,7 +72,7 @@ int downstring __P ((char *)); * F_INSTR - output raw instruction. * F_LINENO - show line # info if available. * - * Returns TRUE if the area was successfully disassembled or FALSE if + * Returns true if the area was successfully disassembled or false if * a problem was encountered with accessing the memory. */ @@ -137,8 +137,8 @@ int disppc (unsigned char *memaddr, unsigned char *virtual, int num_instr, for (i = 0; i < num_instr; ++i, memaddr += 4, ctx.virtual += 4) { #ifdef USE_SOURCE_CODE if (ctx.flags & F_LINENO) { - if ((line_info_from_addr ((Elf32_Word) ctx.virtual, filename, - funcname, &line_no) == TRUE) && + if ((line_info_from_addr ((Elf32_Word) ctx.virtual, + filename, funcname, &line_no) == true) && ((line_no != last_line_no) || (strcmp (last_funcname, funcname) != 0))) { print_source_line (filename, funcname, line_no, pfunc); @@ -154,15 +154,15 @@ int disppc (unsigned char *memaddr, unsigned char *virtual, int num_instr, #ifdef USE_SOURCE_CODE if (ctx.flags & F_SYMBOL) { if ((symname = - symbol_name_from_addr ((Elf32_Word) ctx.virtual, - TRUE, 0)) != 0) { + symbol_name_from_addr((Elf32_Word) ctx.virtual, + true, 0)) != 0) { cursym = symname; symoffset = 0; } else { if ((cursym == 0) && ((symname = - symbol_name_from_addr ((Elf32_Word) ctx.virtual, - FALSE, &symoffset)) != 0)) { + symbol_name_from_addr((Elf32_Word) ctx.virtual, + false, &symoffset)) != 0)) { cursym = symname; } else { symoffset += 4; @@ -205,7 +205,8 @@ int disppc (unsigned char *memaddr, unsigned char *virtual, int num_instr, } if (((ctx.flags & F_SIMPLE) == 0) || - (ctx.op->hfunc == 0) || ((*ctx.op->hfunc) (&ctx) == FALSE)) { + (ctx.op->hfunc == 0) || + ((*ctx.op->hfunc) (&ctx) == false)) { sprintf (&ctx.data[ctx.datalen], "%-7s ", ctx.op->name); ctx.datalen += 8; print_operands (&ctx); @@ -214,7 +215,7 @@ int disppc (unsigned char *memaddr, unsigned char *virtual, int num_instr, (*pfunc) (ctx.data); } - return TRUE; + return true; } /* disppc */ @@ -364,10 +365,10 @@ int print_operands (struct ppc_ctx *ctx) * value The address of an unsigned long to be filled in * with the value of the operand if it is found. This * will only be filled in if the function returns - * TRUE. This may be passed as 0 if the value is + * true. This may be passed as 0 if the value is * not required. * - * Returns TRUE if the operand was found or FALSE if it was not. + * Returns true if the operand was found or false if it was not. */ int get_operand_value (struct opcode *op, unsigned long instr, @@ -379,7 +380,7 @@ int get_operand_value (struct opcode *op, unsigned long instr, /*------------------------------------------------------------*/ if (field > n_operands) { - return FALSE; /* bad operand ?! */ + return false; /* bad operand ?! */ } /* Walk through the operands and list each in order */ @@ -393,10 +394,10 @@ int get_operand_value (struct opcode *op, unsigned long instr, if (value) { *value = (instr >> opr->shift) & ((1 << opr->bits) - 1); } - return TRUE; + return true; } - return FALSE; + return false; } /* operand_value */ @@ -649,7 +650,7 @@ int tbr_value (char *name) * Arguments: * ctx A pointer to the disassembler context record. * - * Returns TRUE if the simpler form was printed or FALSE if it was not. + * Returns true if the simpler form was printed or false if it was not. */ int handle_bc (struct ppc_ctx *ctx) @@ -669,33 +670,33 @@ int handle_bc (struct ppc_ctx *ctx) /*------------------------------------------------------------*/ - if (get_operand_value (ctx->op, ctx->instr, O_BO, &bo) == FALSE) - return FALSE; + if (get_operand_value(ctx->op, ctx->instr, O_BO, &bo) == false) + return false; - if (get_operand_value (ctx->op, ctx->instr, O_BI, &bi) == FALSE) - return FALSE; + if (get_operand_value(ctx->op, ctx->instr, O_BI, &bi) == false) + return false; if ((bo == 12) && (bi == 0)) { ctx->op = &blt; sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name); ctx->datalen += 8; print_operands (ctx); - return TRUE; + return true; } else if ((bo == 4) && (bi == 10)) { ctx->op = =⃥ sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name); ctx->datalen += 8; print_operands (ctx); - return TRUE; + return true; } else if ((bo == 16) && (bi == 0)) { ctx->op = &bdnz; sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name); ctx->datalen += 8; print_operands (ctx); - return TRUE; + return true; } - return FALSE; + return false; } /* handle_blt */ @@ -719,7 +720,7 @@ int handle_bc (struct ppc_ctx *ctx) * pfunc The address of a function to call to print the output. * * - * Returns TRUE if it was able to output the line info, or false if it was + * Returns true if it was able to output the line info, or false if it was * not. */ @@ -734,7 +735,7 @@ int print_source_line (char *filename, char *funcname, sprintf (out_buf, "%s %s(): line %d", filename, funcname, line_no); (*pfunc) (out_buf); - return TRUE; + return true; } /* print_source_line */ @@ -1039,14 +1040,14 @@ int downstring (char *s) * Arguments: * nextaddr The address (to be filled in) of the next * instruction to execute. This will only be a valid - * address if TRUE is returned. + * address if true is returned. * * step_over A flag indicating how to compute addresses for * branch statements: - * TRUE = Step over the branch (next) - * FALSE = step into the branch (step) + * true = Step over the branch (next) + * false = step into the branch (step) * - * Returns TRUE if it was able to compute the address. Returns FALSE if + * Returns true if it was able to compute the address. Returns false if * it has a problem reading the current instruction or one of the registers. */ @@ -1075,7 +1076,7 @@ int find_next_address (unsigned char *nextaddr, int step_over, if (nextaddr == 0 || regs == 0) { printf ("find_next_address: bad args"); - return FALSE; + return false; } pc = regs->nip & 0xfffffffc; @@ -1083,7 +1084,7 @@ int find_next_address (unsigned char *nextaddr, int step_over, if ((op = find_opcode (instr)) == (struct opcode *) 0) { printf ("find_next_address: can't parse opcode 0x%lx", instr); - return FALSE; + return false; } ctr = regs->ctr; @@ -1100,7 +1101,7 @@ int find_next_address (unsigned char *nextaddr, int step_over, !get_operand_value (op, instr, O_BI, &bi) || !get_operand_value (op, instr, O_AA, &aa) || !get_operand_value (op, instr, O_LK, &lk)) - return FALSE; + return false; if ((addr & (1 << 13)) != 0) addr = addr - (1 << 14); @@ -1116,7 +1117,7 @@ int find_next_address (unsigned char *nextaddr, int step_over, if (!get_operand_value (op, instr, O_LI, &addr) || !get_operand_value (op, instr, O_AA, &aa) || !get_operand_value (op, instr, O_LK, &lk)) - return FALSE; + return false; if ((addr & (1 << 23)) != 0) addr = addr - (1 << 24); @@ -1130,7 +1131,7 @@ int find_next_address (unsigned char *nextaddr, int step_over, if (!get_operand_value (op, instr, O_BO, &bo) || !get_operand_value (op, instr, O_BI, &bi) || !get_operand_value (op, instr, O_LK, &lk)) - return FALSE; + return false; addr = ctr; aa = 1; @@ -1143,7 +1144,7 @@ int find_next_address (unsigned char *nextaddr, int step_over, if (!get_operand_value (op, instr, O_BO, &bo) || !get_operand_value (op, instr, O_BI, &bi) || !get_operand_value (op, instr, O_LK, &lk)) - return FALSE; + return false; addr = lr; aa = 1; @@ -1227,12 +1228,12 @@ int find_next_address (unsigned char *nextaddr, int step_over, step = next = pc + 4; } - if (step_over == TRUE) + if (step_over == true) *(unsigned long *) nextaddr = next; else *(unsigned long *) nextaddr = step; - return TRUE; + return true; } /* find_next_address */ diff --git a/common/board_f.c b/common/board_f.c new file mode 100644 index 0000000..7698891 --- /dev/null +++ b/common/board_f.c @@ -0,0 +1,1012 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2002-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/compiler.h> +#include <version.h> +#include <environment.h> +#include <fdtdec.h> +#if defined(CONFIG_CMD_IDE) +#include <ide.h> +#endif +#include <i2c.h> +#include <initcall.h> +#include <logbuff.h> + +/* TODO: Can we move these into arch/ headers? */ +#ifdef CONFIG_8xx +#include <mpc8xx.h> +#endif +#ifdef CONFIG_5xx +#include <mpc5xx.h> +#endif +#ifdef CONFIG_MPC5xxx +#include <mpc5xxx.h> +#endif + +#include <post.h> +#include <spi.h> +#include <watchdog.h> +#include <asm/io.h> +#ifdef CONFIG_MP +#include <asm/mp.h> +#endif +#include <asm/sections.h> +#ifdef CONFIG_X86 +#include <asm/init_helpers.h> +#include <asm/relocate.h> +#endif +#include <linux/compiler.h> + +/* + * Pointer to initial global data area + * + * Here we initialize it if needed. + */ +#ifdef XTRN_DECLARE_GLOBAL_DATA_PTR +#undef XTRN_DECLARE_GLOBAL_DATA_PTR +#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ +DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_GD_ADDR); +#else +DECLARE_GLOBAL_DATA_PTR; +#endif + +/* + * sjg: IMO this code should be + * refactored to a single function, something like: + * + * void led_set_state(enum led_colour_t colour, int on); + */ +/************************************************************************ + * Coloured LED functionality + ************************************************************************ + * May be supplied by boards if desired + */ +inline void __coloured_LED_init(void) {} +void coloured_LED_init(void) + __attribute__((weak, alias("__coloured_LED_init"))); +inline void __red_led_on(void) {} +void red_led_on(void) __attribute__((weak, alias("__red_led_on"))); +inline void __red_led_off(void) {} +void red_led_off(void) __attribute__((weak, alias("__red_led_off"))); +inline void __green_led_on(void) {} +void green_led_on(void) __attribute__((weak, alias("__green_led_on"))); +inline void __green_led_off(void) {} +void green_led_off(void) __attribute__((weak, alias("__green_led_off"))); +inline void __yellow_led_on(void) {} +void yellow_led_on(void) __attribute__((weak, alias("__yellow_led_on"))); +inline void __yellow_led_off(void) {} +void yellow_led_off(void) __attribute__((weak, alias("__yellow_led_off"))); +inline void __blue_led_on(void) {} +void blue_led_on(void) __attribute__((weak, alias("__blue_led_on"))); +inline void __blue_led_off(void) {} +void blue_led_off(void) __attribute__((weak, alias("__blue_led_off"))); + +/* + * Why is gd allocated a register? Prior to reloc it might be better to + * just pass it around to each function in this file? + * + * After reloc one could argue that it is hardly used and doesn't need + * to be in a register. Or if it is it should perhaps hold pointers to all + * global data for all modules, so that post-reloc we can avoid the massive + * literal pool we get on ARM. Or perhaps just encourage each module to use + * a structure... + */ + +/* + * Could the CONFIG_SPL_BUILD infection become a flag in gd? + */ + +#if defined(CONFIG_WATCHDOG) +static int init_func_watchdog_init(void) +{ + puts(" Watchdog enabled\n"); + WATCHDOG_RESET(); + + return 0; +} + +int init_func_watchdog_reset(void) +{ + WATCHDOG_RESET(); + + return 0; +} +#endif /* CONFIG_WATCHDOG */ + +void __board_add_ram_info(int use_default) +{ + /* please define platform specific board_add_ram_info() */ +} + +void board_add_ram_info(int) + __attribute__ ((weak, alias("__board_add_ram_info"))); + +static int init_baud_rate(void) +{ + gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); + return 0; +} + +static int display_text_info(void) +{ + ulong bss_start, bss_end; + +#ifdef CONFIG_SYS_SYM_OFFSETS + bss_start = _bss_start_ofs + _TEXT_BASE; + bss_end = _bss_end_ofs + _TEXT_BASE; +#else + bss_start = (ulong)&__bss_start; + bss_end = (ulong)&__bss_end; +#endif + debug("U-Boot code: %08X -> %08lX BSS: -> %08lX\n", + CONFIG_SYS_TEXT_BASE, bss_start, bss_end); + +#ifdef CONFIG_MODEM_SUPPORT + debug("Modem Support enabled\n"); +#endif +#ifdef CONFIG_USE_IRQ + debug("IRQ Stack: %08lx\n", IRQ_STACK_START); + debug("FIQ Stack: %08lx\n", FIQ_STACK_START); +#endif + + return 0; +} + +static int announce_dram_init(void) +{ + puts("DRAM: "); + return 0; +} + +#ifdef CONFIG_PPC +static int init_func_ram(void) +{ +#ifdef CONFIG_BOARD_TYPES + int board_type = gd->board_type; +#else + int board_type = 0; /* use dummy arg */ +#endif + + gd->ram_size = initdram(board_type); + + if (gd->ram_size > 0) + return 0; + + puts("*** failed ***\n"); + return 1; +} +#endif + +static int show_dram_config(void) +{ + ulong size; + +#ifdef CONFIG_NR_DRAM_BANKS + int i; + + debug("\nRAM Configuration:\n"); + for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + size += gd->bd->bi_dram[i].size; + debug("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start); +#ifdef DEBUG + print_size(gd->bd->bi_dram[i].size, "\n"); +#endif + } + debug("\nDRAM: "); +#else + size = gd->ram_size; +#endif + + print_size(size, ""); + board_add_ram_info(0); + putc('\n'); + + return 0; +} + +ulong get_effective_memsize(void) +{ +#ifndef CONFIG_VERY_BIG_RAM + return gd->ram_size; +#else + /* limit stack to what we can reasonable map */ + return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? + CONFIG_MAX_MEM_MAPPED : gd->ram_size); +#endif +} + +void __dram_init_banksize(void) +{ +#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE) + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = get_effective_memsize(); +#endif +} + +void dram_init_banksize(void) + __attribute__((weak, alias("__dram_init_banksize"))); + +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) +static int init_func_i2c(void) +{ + puts("I2C: "); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + puts("ready\n"); + return 0; +} +#endif + +#if defined(CONFIG_HARD_SPI) +static int init_func_spi(void) +{ + puts("SPI: "); + spi_init(); + puts("ready\n"); + return 0; +} +#endif + +__maybe_unused +static int zero_global_data(void) +{ + memset((void *)gd, '\0', sizeof(gd_t)); + + return 0; +} + +static int setup_mon_len(void) +{ +#ifdef CONFIG_SYS_SYM_OFFSETS + gd->mon_len = _bss_end_ofs; +#else + /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */ + gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; +#endif + return 0; +} + +__weak int arch_cpu_init(void) +{ + return 0; +} + +static int setup_fdt(void) +{ +#ifdef CONFIG_OF_EMBED + /* Get a pointer to the FDT */ + gd->fdt_blob = _binary_dt_dtb_start; +#elif defined CONFIG_OF_SEPARATE + /* FDT is at end of image */ +# ifdef CONFIG_SYS_SYM_OFFSETS + gd->fdt_blob = (void *)(_end_ofs + CONFIG_SYS_TEXT_BASE); +# else + gd->fdt_blob = (ulong *)&_end; +# endif +#endif + /* Allow the early environment to override the fdt address */ + gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16, + (uintptr_t)gd->fdt_blob); + return 0; +} + +/* Get the top of usable RAM */ +__weak ulong board_get_usable_ram_top(ulong total_size) +{ + return gd->ram_top; +} + +static int setup_dest_addr(void) +{ + debug("Monitor len: %08lX\n", gd->mon_len); + /* + * Ram is setup, size stored in gd !! + */ + debug("Ram size: %08lX\n", (ulong)gd->ram_size); +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + /* + * Subtract specified amount of memory to hide so that it won't + * get "touched" at all by U-Boot. By fixing up gd->ram_size + * the Linux kernel should now get passed the now "corrected" + * memory size and won't touch it either. This should work + * for arch/ppc and arch/powerpc. Only Linux board ports in + * arch/powerpc with bootwrapper support, that recalculate the + * memory size from the SDRAM controller setup will have to + * get fixed. + */ + gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; +#endif +#ifdef CONFIG_SYS_SDRAM_BASE + gd->ram_top = CONFIG_SYS_SDRAM_BASE; +#endif + gd->ram_top += get_effective_memsize(); + gd->ram_top = board_get_usable_ram_top(gd->mon_len); + gd->dest_addr = gd->ram_top; + debug("Ram top: %08lX\n", (ulong)gd->ram_top); +#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) + /* + * We need to make sure the location we intend to put secondary core + * boot code is reserved and not used by any part of u-boot + */ + if (gd->dest_addr > determine_mp_bootpg(NULL)) { + gd->dest_addr = determine_mp_bootpg(NULL); + debug("Reserving MP boot page to %08lx\n", gd->dest_addr); + } +#endif + gd->dest_addr_sp = gd->dest_addr; + return 0; +} + +#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) +static int reserve_logbuffer(void) +{ + /* reserve kernel log buffer */ + gd->dest_addr -= LOGBUFF_RESERVE; + debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, + gd->dest_addr); + return 0; +} +#endif + +#ifdef CONFIG_PRAM +/* reserve protected RAM */ +static int reserve_pram(void) +{ + ulong reg; + + reg = getenv_ulong("pram", 10, CONFIG_PRAM); + gd->dest_addr -= (reg << 10); /* size is in kB */ + debug("Reserving %ldk for protected RAM at %08lx\n", reg, + gd->dest_addr); + return 0; +} +#endif /* CONFIG_PRAM */ + +/* Round memory pointer down to next 4 kB limit */ +static int reserve_round_4k(void) +{ + gd->dest_addr &= ~(4096 - 1); + return 0; +} + +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ + defined(CONFIG_ARM) +static int reserve_mmu(void) +{ + /* reserve TLB table */ + gd->arch.tlb_size = 4096 * 4; + gd->dest_addr -= gd->arch.tlb_size; + + /* round down to next 64 kB limit */ + gd->dest_addr &= ~(0x10000 - 1); + + gd->arch.tlb_addr = gd->dest_addr; + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + return 0; +} +#endif + +#ifdef CONFIG_LCD +static int reserve_lcd(void) +{ +#ifdef CONFIG_FB_ADDR + gd->fb_base = CONFIG_FB_ADDR; +#else + /* reserve memory for LCD display (always full pages) */ + gd->dest_addr = lcd_setmem(gd->dest_addr); + gd->fb_base = gd->dest_addr; +#endif /* CONFIG_FB_ADDR */ + return 0; +} +#endif /* CONFIG_LCD */ + +#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) \ + && !defined(CONFIG_ARM) && !defined(CONFIG_X86) +static int reserve_video(void) +{ + /* reserve memory for video display (always full pages) */ + gd->dest_addr = video_setmem(gd->dest_addr); + gd->fb_base = gd->dest_addr; + + return 0; +} +#endif + +static int reserve_uboot(void) +{ + /* + * reserve memory for U-Boot code, data & bss + * round down to next 4 kB limit + */ + gd->dest_addr -= gd->mon_len; + gd->dest_addr &= ~(4096 - 1); +#ifdef CONFIG_E500 + /* round down to next 64 kB limit so that IVPR stays aligned */ + gd->dest_addr &= ~(65536 - 1); +#endif + + debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, + gd->dest_addr); + return 0; +} + +#ifndef CONFIG_SPL_BUILD +/* reserve memory for malloc() area */ +static int reserve_malloc(void) +{ + gd->dest_addr_sp = gd->dest_addr - TOTAL_MALLOC_LEN; + debug("Reserving %dk for malloc() at: %08lx\n", + TOTAL_MALLOC_LEN >> 10, gd->dest_addr_sp); + return 0; +} + +/* (permanently) allocate a Board Info struct */ +static int reserve_board(void) +{ + gd->dest_addr_sp -= sizeof(bd_t); + gd->bd = (bd_t *)gd->dest_addr_sp; + memset(gd->bd, '\0', sizeof(bd_t)); + debug("Reserving %zu Bytes for Board Info at: %08lx\n", + sizeof(bd_t), gd->dest_addr_sp); + return 0; +} +#endif + +static int setup_machine(void) +{ +#ifdef CONFIG_MACH_TYPE + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ +#endif + return 0; +} + +static int reserve_global_data(void) +{ + gd->dest_addr_sp -= sizeof(gd_t); + gd->new_gd = (gd_t *)gd->dest_addr_sp; + debug("Reserving %zu Bytes for Global Data at: %08lx\n", + sizeof(gd_t), gd->dest_addr_sp); + return 0; +} + +static int reserve_fdt(void) +{ + /* + * If the device tree is sitting immediate above our image then we + * must relocate it. If it is embedded in the data section, then it + * will be relocated with other data. + */ + if (gd->fdt_blob) { + gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); + + gd->dest_addr_sp -= gd->fdt_size; + gd->new_fdt = (void *)gd->dest_addr_sp; + debug("Reserving %lu Bytes for FDT at: %p\n", + gd->fdt_size, gd->new_fdt); + } + + return 0; +} + +static int reserve_stacks(void) +{ +#ifdef CONFIG_SPL_BUILD +# ifdef CONFIG_ARM + gd->dest_addr_sp -= 128; /* leave 32 words for abort-stack */ + gd->irq_sp = gd->dest_addr_sp; +# endif +#else +# ifdef CONFIG_PPC + ulong *s; +# endif + + /* setup stack pointer for exceptions */ + gd->dest_addr_sp -= 16; + gd->dest_addr_sp &= ~0xf; + gd->irq_sp = gd->dest_addr_sp; + + /* + * Handle architecture-specific things here + * TODO(sjg@chromium.org): Perhaps create arch_reserve_stack() + * to handle this and put in arch/xxx/lib/stack.c + */ +# ifdef CONFIG_ARM +# ifdef CONFIG_USE_IRQ + gd->dest_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ); + debug("Reserving %zu Bytes for IRQ stack at: %08lx\n", + CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->dest_addr_sp); + + /* 8-byte alignment for ARM ABI compliance */ + gd->dest_addr_sp &= ~0x07; +# endif + /* leave 3 words for abort-stack, plus 1 for alignment */ + gd->dest_addr_sp -= 16; +# elif defined(CONFIG_PPC) + /* Clear initial stack frame */ + s = (ulong *) gd->dest_addr_sp; + *s = 0; /* Terminate back chain */ + *++s = 0; /* NULL return address */ +# endif /* Architecture specific code */ + + return 0; +#endif +} + +static int display_new_sp(void) +{ + debug("New Stack Pointer is: %08lx\n", gd->dest_addr_sp); + + return 0; +} + +#ifdef CONFIG_PPC +static int setup_board_part1(void) +{ + bd_t *bd = gd->bd; + + /* + * Save local variables to board info struct + */ + + bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ + bd->bi_memsize = gd->ram_size; /* size in bytes */ + +#ifdef CONFIG_SYS_SRAM_BASE + bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ + bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ +#endif + +#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ + defined(CONFIG_E500) || defined(CONFIG_MPC86xx) + bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ +#endif +#if defined(CONFIG_MPC5xxx) + bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ +#endif +#if defined(CONFIG_MPC83xx) + bd->bi_immrbar = CONFIG_SYS_IMMR; +#endif +#if defined(CONFIG_MPC8220) + bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ + bd->bi_inpfreq = gd->arch.inp_clk; + bd->bi_pcifreq = gd->pci_clk; + bd->bi_vcofreq = gd->arch.vco_clk; + bd->bi_pevfreq = gd->arch.pev_clk; + bd->bi_flbfreq = gd->arch.flb_clk; + + /* store bootparam to sram (backward compatible), here? */ + { + u32 *sram = (u32 *) CONFIG_SYS_SRAM_BASE; + + *sram++ = gd->ram_size; + *sram++ = gd->bus_clk; + *sram++ = gd->arch.inp_clk; + *sram++ = gd->cpu_clk; + *sram++ = gd->arch.vco_clk; + *sram++ = gd->arch.flb_clk; + *sram++ = 0xb8c3ba11; /* boot signature */ + } +#endif + + return 0; +} + +static int setup_board_part2(void) +{ + bd_t *bd = gd->bd; + + bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ + bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ +#if defined(CONFIG_CPM2) + bd->bi_cpmfreq = gd->arch.cpm_clk; + bd->bi_brgfreq = gd->arch.brg_clk; + bd->bi_sccfreq = gd->arch.scc_clk; + bd->bi_vco = gd->arch.vco_out; +#endif /* CONFIG_CPM2 */ +#if defined(CONFIG_MPC512X) + bd->bi_ipsfreq = gd->arch.ips_clk; +#endif /* CONFIG_MPC512X */ +#if defined(CONFIG_MPC5xxx) + bd->bi_ipbfreq = gd->arch.ipb_clk; + bd->bi_pcifreq = gd->pci_clk; +#endif /* CONFIG_MPC5xxx */ + + return 0; +} +#endif + +#ifdef CONFIG_SYS_EXTBDINFO +static int setup_board_extra(void) +{ + bd_t *bd = gd->bd; + + strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); + strncpy((char *) bd->bi_r_version, U_BOOT_VERSION, + sizeof(bd->bi_r_version)); + + bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ + bd->bi_plb_busfreq = gd->bus_clk; +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + bd->bi_pci_busfreq = get_PCI_freq(); + bd->bi_opbfreq = get_OPB_freq(); +#elif defined(CONFIG_XILINX_405) + bd->bi_pci_busfreq = get_PCI_freq(); +#endif + + return 0; +} +#endif + +#ifdef CONFIG_POST +static int init_post(void) +{ + post_bootmode_init(); + post_run(NULL, POST_ROM | post_bootmode_get(0)); + + return 0; +} +#endif + +static int setup_baud_rate(void) +{ + /* Ick, can we get rid of this line? */ + gd->bd->bi_baudrate = gd->baudrate; + + return 0; +} + +static int setup_dram_config(void) +{ + /* Ram is board specific, so move it to board code ... */ + dram_init_banksize(); + + return 0; +} + +static int reloc_fdt(void) +{ + if (gd->new_fdt) { + memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size); + gd->fdt_blob = gd->new_fdt; + } + + return 0; +} + +static int setup_reloc(void) +{ + gd->relocaddr = gd->dest_addr; + gd->start_addr_sp = gd->dest_addr_sp; + gd->reloc_off = gd->dest_addr - CONFIG_SYS_TEXT_BASE; + memcpy(gd->new_gd, (char *)gd, sizeof(gd_t)); + + debug("Relocation Offset is: %08lx\n", gd->reloc_off); + debug("Relocating to %08lx, new gd at %p, sp at %08lx\n", + gd->dest_addr, gd->new_gd, gd->dest_addr_sp); + + return 0; +} + +/* ARM calls relocate_code from its crt0.S */ +#if !defined(CONFIG_ARM) + +static int jump_to_copy(void) +{ + /* + * x86 is special, but in a nice way. It uses a trampoline which + * enables the dcache if possible. + * + * For now, other archs use relocate_code(), which is implemented + * similarly for all archs. When we do generic relocation, hopefully + * we can make all archs enable the dcache prior to relocation. + */ +#ifdef CONFIG_X86 + /* + * SDRAM and console are now initialised. The final stack can now + * be setup in SDRAM. Code execution will continue in Flash, but + * with the stack in SDRAM and Global Data in temporary memory + * (CPU cache) + */ + board_init_f_r_trampoline(gd->start_addr_sp); +#else + relocate_code(gd->dest_addr_sp, gd->new_gd, gd->dest_addr); +#endif + + return 0; +} +#endif + +/* Record the board_init_f() bootstage (after arch_cpu_init()) */ +static int mark_bootstage(void) +{ + bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f"); + + return 0; +} + +static init_fnc_t init_sequence_f[] = { +#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \ + !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \ + !defined(CONFIG_MPC86xx) + zero_global_data, +#endif + setup_fdt, + setup_mon_len, +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) + /* TODO: can this go into arch_cpu_init()? */ + probecpu, +#endif + arch_cpu_init, /* basic arch cpu dependent setup */ +#ifdef CONFIG_X86 + cpu_init_f, /* TODO(sjg@chromium.org): remove */ +# ifdef CONFIG_OF_CONTROL + find_fdt, /* TODO(sjg@chromium.org): remove */ +# endif +#endif + mark_bootstage, +#ifdef CONFIG_OF_CONTROL + fdtdec_check_fdt, +#endif +#if defined(CONFIG_BOARD_EARLY_INIT_F) + board_early_init_f, +#endif + /* TODO: can any of this go into arch_cpu_init()? */ +#if defined(CONFIG_PPC) && !defined(CONFIG_8xx_CPUCLK_DEFAULT) + get_clocks, /* get CPU and bus clocks (etc.) */ +#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ + && !defined(CONFIG_TQM885D) + adjust_sdram_tbs_8xx, +#endif + /* TODO: can we rename this to timer_init()? */ + init_timebase, +#endif +#ifdef CONFIG_ARM + timer_init, /* initialize timer */ +#endif +#ifdef CONFIG_BOARD_POSTCLK_INIT + board_postclk_init, +#endif +#ifdef CONFIG_FSL_ESDHC + get_clocks, +#endif +#ifdef CONFIG_SYS_ALLOC_DPRAM +#if !defined(CONFIG_CPM2) + dpram_init, +#endif +#endif +#if defined(CONFIG_BOARD_POSTCLK_INIT) + board_postclk_init, +#endif + env_init, /* initialize environment */ +#if defined(CONFIG_8xx_CPUCLK_DEFAULT) + /* get CPU and bus clocks according to the environment variable */ + get_clocks_866, + /* adjust sdram refresh rate according to the new clock */ + sdram_adjust_866, + init_timebase, +#endif + init_baud_rate, /* initialze baudrate settings */ + serial_init, /* serial communications setup */ + console_init_f, /* stage 1 init of console */ +#if defined(CONFIG_X86) && defined(CONFIG_OF_CONTROL) + prepare_fdt, /* TODO(sjg@chromium.org): remove */ +#endif + display_options, /* say that we are here */ + display_text_info, /* show debugging info if required */ +#if defined(CONFIG_8260) + prt_8260_rsr, + prt_8260_clks, +#endif /* CONFIG_8260 */ +#if defined(CONFIG_MPC83xx) + prt_83xx_rsr, +#endif +#ifdef CONFIG_PPC + checkcpu, +#endif +#if defined(CONFIG_DISPLAY_CPUINFO) + print_cpuinfo, /* display cpu info (and speed) */ +#endif +#if defined(CONFIG_MPC5xxx) + prt_mpc5xxx_clks, +#endif /* CONFIG_MPC5xxx */ +#if defined(CONFIG_MPC8220) + prt_mpc8220_clks, +#endif +#if defined(CONFIG_DISPLAY_BOARDINFO) + checkboard, /* display board info */ +#endif + INIT_FUNC_WATCHDOG_INIT +#if defined(CONFIG_MISC_INIT_F) + misc_init_f, +#endif + INIT_FUNC_WATCHDOG_RESET +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) + init_func_i2c, +#endif +#if defined(CONFIG_HARD_SPI) + init_func_spi, +#endif +#ifdef CONFIG_X86 + dram_init_f, /* configure available RAM banks */ + /* x86 would prefer that this happens after relocation */ + dram_init, +#endif + announce_dram_init, + /* TODO: unify all these dram functions? */ +#ifdef CONFIG_ARM + dram_init, /* configure available RAM banks */ +#endif +#ifdef CONFIG_PPC + init_func_ram, +#endif +#ifdef CONFIG_POST + post_init_f, +#endif + INIT_FUNC_WATCHDOG_RESET +#if defined(CONFIG_SYS_DRAM_TEST) + testdram, +#endif /* CONFIG_SYS_DRAM_TEST */ + INIT_FUNC_WATCHDOG_RESET + +#ifdef CONFIG_POST + init_post, +#endif + INIT_FUNC_WATCHDOG_RESET + /* + * Now that we have DRAM mapped and working, we can + * relocate the code and continue running from DRAM. + * + * Reserve memory at end of RAM for (top down in that order): + * - area that won't get touched by U-Boot and Linux (optional) + * - kernel log buffer + * - protected RAM + * - LCD framebuffer + * - monitor code + * - board info struct + */ + setup_dest_addr, +#if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) + reserve_logbuffer, +#endif +#ifdef CONFIG_PRAM + reserve_pram, +#endif + reserve_round_4k, +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \ + defined(CONFIG_ARM) + reserve_mmu, +#endif +#ifdef CONFIG_LCD + reserve_lcd, +#endif + /* TODO: Why the dependency on CONFIG_8xx? */ +#if defined(CONFIG_VIDEO) && (!defined(CONFIG_PPC) || defined(CONFIG_8xx)) \ + && !defined(CONFIG_ARM) && !defined(CONFIG_X86) + reserve_video, +#endif + reserve_uboot, +#ifndef CONFIG_SPL_BUILD + reserve_malloc, + reserve_board, +#endif + setup_machine, + reserve_global_data, + reserve_fdt, + reserve_stacks, + setup_dram_config, + show_dram_config, +#ifdef CONFIG_PPC + setup_board_part1, + INIT_FUNC_WATCHDOG_RESET + setup_board_part2, +#endif + setup_baud_rate, + display_new_sp, +#ifdef CONFIG_SYS_EXTBDINFO + setup_board_extra, +#endif + INIT_FUNC_WATCHDOG_RESET + reloc_fdt, + setup_reloc, +#ifndef CONFIG_ARM + jump_to_copy, +#endif + NULL, +}; + +void board_init_f(ulong boot_flags) +{ +#ifndef CONFIG_X86 + gd_t data; + + gd = &data; +#endif + + gd->flags = boot_flags; + + if (initcall_run_list(init_sequence_f)) + hang(); + +#ifndef CONFIG_ARM + /* NOTREACHED - jump_to_copy() does not return */ + hang(); +#endif +} + +#ifdef CONFIG_X86 +/* + * For now this code is only used on x86. + * + * init_sequence_f_r is the list of init functions which are run when + * U-Boot is executing from Flash with a semi-limited 'C' environment. + * The following limitations must be considered when implementing an + * '_f_r' function: + * - 'static' variables are read-only + * - Global Data (gd->xxx) is read/write + * + * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if + * supported). It _should_, if possible, copy global data to RAM and + * initialise the CPU caches (to speed up the relocation process) + * + * NOTE: At present only x86 uses this route, but it is intended that + * all archs will move to this when generic relocation is implemented. + */ +static init_fnc_t init_sequence_f_r[] = { + init_cache_f_r, + copy_uboot_to_ram, + clear_bss, + do_elf_reloc_fixups, + + NULL, +}; + +void board_init_f_r(void) +{ + if (initcall_run_list(init_sequence_f_r)) + hang(); + + /* + * U-Boot has been copied into SDRAM, the BSS has been cleared etc. + * Transfer execution from Flash to RAM by calculating the address + * of the in-RAM copy of board_init_r() and calling it + */ + (board_init_r + gd->reloc_off)(gd, gd->relocaddr); + + /* NOTREACHED - board_init_r() does not return */ + hang(); +} +#endif /* CONFIG_X86 */ + +void hang(void) +{ + puts("### ERROR ### Please RESET the board ###\n"); + for (;;); +} diff --git a/common/board_r.c b/common/board_r.c new file mode 100644 index 0000000..9605f80 --- /dev/null +++ b/common/board_r.c @@ -0,0 +1,917 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2002-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +/* TODO: can we just include all these headers whether needed or not? */ +#if defined(CONFIG_CMD_BEDBUG) +#include <bedbug/type.h> +#endif +#ifdef CONFIG_HAS_DATAFLASH +#include <dataflash.h> +#endif +#include <environment.h> +#include <fdtdec.h> +#if defined(CONFIG_CMD_IDE) +#include <ide.h> +#endif +#include <initcall.h> +#ifdef CONFIG_PS2KBD +#include <keyboard.h> +#endif +#if defined(CONFIG_CMD_KGDB) +#include <kgdb.h> +#endif +#include <logbuff.h> +#include <malloc.h> +#ifdef CONFIG_BITBANGMII +#include <miiphy.h> +#endif +#include <mmc.h> +#include <nand.h> +#include <onenand_uboot.h> +#include <scsi.h> +#include <serial.h> +#include <spi.h> +#include <stdio_dev.h> +#include <watchdog.h> +#ifdef CONFIG_ADDR_MAP +#include <asm/mmu.h> +#endif +#include <asm/sections.h> +#ifdef CONFIG_X86 +#include <asm/init_helpers.h> +#endif +#include <linux/compiler.h> + +DECLARE_GLOBAL_DATA_PTR; + +ulong monitor_flash_len; + +int __board_flash_wp_on(void) +{ + /* + * Most flashes can't be detected when write protection is enabled, + * so provide a way to let U-Boot gracefully ignore write protected + * devices. + */ + return 0; +} + +int board_flash_wp_on(void) + __attribute__ ((weak, alias("__board_flash_wp_on"))); + +void __cpu_secondary_init_r(void) +{ +} + +void cpu_secondary_init_r(void) + __attribute__ ((weak, alias("__cpu_secondary_init_r"))); + +static int initr_secondary_cpu(void) +{ + /* + * after non-volatile devices & environment is setup and cpu code have + * another round to deal with any initialization that might require + * full access to the environment or loading of some image (firmware) + * from a non-volatile device + */ + /* TODO: maybe define this for all archs? */ + cpu_secondary_init_r(); + + return 0; +} + +static int initr_reloc(void) +{ + gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ + bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r"); + + return 0; +} + +#ifdef CONFIG_ARM +/* + * Some of these functions are needed purely because the functions they + * call return void. If we change them to return 0, these stubs can go away. + */ +static int initr_caches(void) +{ + /* Enable caches */ + enable_caches(); + return 0; +} +#endif + +__weak int fixup_cpu(void) +{ + return 0; +} + +static int initr_reloc_global_data(void) +{ +#ifdef CONFIG_SYS_SYM_OFFSETS + monitor_flash_len = _end_ofs; +#else + monitor_flash_len = (ulong)&__init_end - gd->dest_addr; +#endif +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) + /* + * The gd->cpu pointer is set to an address in flash before relocation. + * We need to update it to point to the same CPU entry in RAM. + * TODO: why not just add gd->reloc_ofs? + */ + gd->arch.cpu += gd->dest_addr - CONFIG_SYS_MONITOR_BASE; + + /* + * If we didn't know the cpu mask & # cores, we can save them of + * now rather than 'computing' them constantly + */ + fixup_cpu(); +#endif +#ifdef CONFIG_SYS_EXTRA_ENV_RELOC + /* + * Some systems need to relocate the env_addr pointer early because the + * location it points to will get invalidated before env_relocate is + * called. One example is on systems that might use a L2 or L3 cache + * in SRAM mode and initialize that cache from SRAM mode back to being + * a cache in cpu_init_r. + */ + gd->env_addr += gd->dest_addr - CONFIG_SYS_MONITOR_BASE; +#endif + return 0; +} + +static int initr_serial(void) +{ + serial_initialize(); + return 0; +} + +#ifdef CONFIG_PPC +static int initr_trap(void) +{ + /* + * Setup trap handlers + */ + trap_init(gd->dest_addr); + + return 0; +} +#endif + +#ifdef CONFIG_ADDR_MAP +static int initr_addr_map(void) +{ + init_addr_map(); + + return 0; +} +#endif + +#ifdef CONFIG_LOGBUFFER +unsigned long logbuffer_base(void) +{ + return gd->ram_top - LOGBUFF_LEN; +} + +static int initr_logbuffer(void) +{ + logbuff_init_ptrs(); + return 0; +} +#endif + +#ifdef CONFIG_POST +static int initr_post_backlog(void) +{ + post_output_backlog(); + return 0; +} +#endif + +#ifdef CONFIG_SYS_DELAYED_ICACHE +static int initr_icache_enable(void) +{ + return 0; +} +#endif + +#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) +static int initr_unlock_ram_in_cache(void) +{ + unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */ + return 0; +} +#endif + +#ifdef CONFIG_PCI +static int initr_pci(void) +{ + pci_init(); + + return 0; +} +#endif + +#ifdef CONFIG_WINBOND_83C553 +static int initr_w83c553f(void) +{ + /* + * Initialise the ISA bridge + */ + initialise_w83c553f(); + return 0; +} +#endif + +static int initr_barrier(void) +{ +#ifdef CONFIG_PPC + /* TODO: Can we not use dmb() macros for this? */ + asm("sync ; isync"); +#endif + return 0; +} + +static int initr_malloc(void) +{ + ulong malloc_start; + + /* The malloc area is immediately below the monitor copy in DRAM */ + malloc_start = gd->dest_addr - TOTAL_MALLOC_LEN; + mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN); + return 0; +} + +__weak int power_init_board(void) +{ + return 0; +} + +static int initr_announce(void) +{ + debug("Now running in RAM - U-Boot at: %08lx\n", gd->dest_addr); + return 0; +} + +#if !defined(CONFIG_SYS_NO_FLASH) +static int initr_flash(void) +{ + ulong flash_size = 0; + bd_t *bd = gd->bd; + int ok; + + puts("Flash: "); + + if (board_flash_wp_on()) { + printf("Uninitialized - Write Protect On\n"); + /* Since WP is on, we can't find real size. Set to 0 */ + ok = 1; + } else { + flash_size = flash_init(); + ok = flash_size > 0; + } + if (!ok) { + puts("*** failed ***\n"); +#ifdef CONFIG_PPC + /* Why does PPC do this? */ + hang(); +#endif + return -1; + } + print_size(flash_size, ""); +#ifdef CONFIG_SYS_FLASH_CHECKSUM + /* + * Compute and print flash CRC if flashchecksum is set to 'y' + * + * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX + */ + if (getenv_yesno("flashchecksum") == 1) { + printf(" CRC: %08X", crc32(0, + (const unsigned char *) CONFIG_SYS_FLASH_BASE, + flash_size)); + } +#endif /* CONFIG_SYS_FLASH_CHECKSUM */ + putc('\n'); + + /* update start of FLASH memory */ +#ifdef CONFIG_SYS_FLASH_BASE + bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; +#endif + /* size of FLASH memory (final value) */ + bd->bi_flashsize = flash_size; + +#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) + /* Make a update of the Memctrl. */ + update_flash_size(flash_size); +#endif + + +#if defined(CONFIG_OXC) || defined(CONFIG_RMU) + /* flash mapped at end of memory map */ + bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size; +#elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE + bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */ +#endif + return 0; +} +#endif + +#ifdef CONFIG_PPC +static int initr_spi(void) +{ + /* PPC does this here */ +#ifdef CONFIG_SPI +#if !defined(CONFIG_ENV_IS_IN_EEPROM) + spi_init_f(); +#endif + spi_init_r(); +#endif + return 0; +} +#endif + +#ifdef CONFIG_CMD_NAND +/* go init the NAND */ +int initr_nand(void) +{ + puts("NAND: "); + nand_init(); + return 0; +} +#endif + +#if defined(CONFIG_CMD_ONENAND) +/* go init the NAND */ +int initr_onenand(void) +{ + puts("NAND: "); + onenand_init(); + return 0; +} +#endif + +#ifdef CONFIG_GENERIC_MMC +int initr_mmc(void) +{ + puts("MMC: "); + mmc_initialize(gd->bd); + return 0; +} +#endif + +#ifdef CONFIG_HAS_DATAFLASH +int initr_dataflash(void) +{ + AT91F_DataflashInit(); + dataflash_print_info(); + return 0; +} +#endif + +/* + * Tell if it's OK to load the environment early in boot. + * + * If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see + * if this is OK (defaulting to saying it's OK). + * + * NOTE: Loading the environment early can be a bad idea if security is + * important, since no verification is done on the environment. + * + * @return 0 if environment should not be loaded, !=0 if it is ok to load + */ +static int should_load_env(void) +{ +#ifdef CONFIG_OF_CONTROL + return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 1); +#elif defined CONFIG_DELAY_ENVIRONMENT + return 0; +#else + return 1; +#endif +} + +static int initr_env(void) +{ + /* initialize environment */ + if (should_load_env()) + env_relocate(); + else + set_default_env(NULL); + + /* Initialize from environment */ + load_addr = getenv_ulong("loadaddr", 16, load_addr); +#if defined(CONFIG_SYS_EXTBDINFO) +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) +#if defined(CONFIG_I2CFAST) + /* + * set bi_iic_fast for linux taking environment variable + * "i2cfast" into account + */ + { + char *s = getenv("i2cfast"); + + if (s && ((*s == 'y') || (*s == 'Y'))) { + gd->bd->bi_iic_fast[0] = 1; + gd->bd->bi_iic_fast[1] = 1; + } + } +#endif /* CONFIG_I2CFAST */ +#endif /* CONFIG_405GP, CONFIG_405EP */ +#endif /* CONFIG_SYS_EXTBDINFO */ + return 0; +} + +#ifdef CONFIG_HERMES +static int initr_hermes(void) +{ + if ((gd->board_type >> 16) == 2) + gd->bd->bi_ethspeed = gd->board_type & 0xFFFF; + else + gd->bd->bi_ethspeed = 0xFFFF; + return 0; +} + +static int initr_hermes_start(void) +{ + if (gd->bd->bi_ethspeed != 0xFFFF) + hermes_start_lxt980((int) gd->bd->bi_ethspeed); + return 0; +} +#endif + +#ifdef CONFIG_SC3 +/* TODO: with new initcalls, move this into the driver */ +extern void sc3_read_eeprom(void); + +static int initr_sc3_read_eeprom(void) +{ + sc3_read_eeprom(); + return 0; +} +#endif + +static int initr_jumptable(void) +{ + jumptable_init(); + return 0; +} + +#if defined(CONFIG_API) +static int initr_api(void) +{ + /* Initialize API */ + api_init(); + return 0; +} +#endif + +#ifdef CONFIG_DISPLAY_BOARDINFO_LATE +static int show_model_r(void) +{ + /* Put this here so it appears on the LCD, now it is ready */ +# ifdef CONFIG_OF_CONTROL + const char *model; + + model = (char *)fdt_getprop(gd->fdt_blob, 0, "model", NULL); + printf("Model: %s\n", model ? model : "<unknown>"); +# else + checkboard(); +# endif +} +#endif + +/* enable exceptions */ +#ifdef CONFIG_ARM +static int initr_enable_interrupts(void) +{ + enable_interrupts(); + return 0; +} +#endif + +#ifdef CONFIG_CMD_NET +static int initr_ethaddr(void) +{ + bd_t *bd = gd->bd; + + /* kept around for legacy kernels only ... ignore the next section */ + eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr); +#ifdef CONFIG_HAS_ETH1 + eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr); +#endif +#ifdef CONFIG_HAS_ETH2 + eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr); +#endif +#ifdef CONFIG_HAS_ETH3 + eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr); +#endif +#ifdef CONFIG_HAS_ETH4 + eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr); +#endif +#ifdef CONFIG_HAS_ETH5 + eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr); +#endif + return 0; +} +#endif /* CONFIG_CMD_NET */ + +#ifdef CONFIG_CMD_KGDB +static int initr_kgdb(void) +{ + puts("KGDB: "); + kgdb_init(); + return 0; +} +#endif + +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) +static int initr_status_led(void) +{ + status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); + + return 0; +} +#endif + +#if defined(CONFIG_CMD_SCSI) +static int initr_scsi(void) +{ + /* Not supported properly on ARM yet */ +#ifndef CONFIG_ARM + puts("SCSI: "); + scsi_init(); +#endif + + return 0; +} +#endif /* CONFIG_CMD_NET */ + +#if defined(CONFIG_CMD_DOC) +static int initr_doc(void) +{ + puts("DOC: "); + doc_init(); +} +#endif + +#ifdef CONFIG_BITBANGMII +static int initr_bbmii(void) +{ + bb_miiphy_init(); + return 0; +} +#endif + +#ifdef CONFIG_CMD_NET +static int initr_net(void) +{ + puts("Net: "); + eth_initialize(gd->bd); +#if defined(CONFIG_RESET_PHY_R) + debug("Reset Ethernet PHY\n"); + reset_phy(); +#endif + return 0; +} +#endif + +#ifdef CONFIG_POST +static int initr_post(void) +{ + post_run(NULL, POST_RAM | post_bootmode_get(0)); + return 0; +} +#endif + +#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE) +static int initr_pcmcia(void) +{ + puts("PCMCIA:"); + pcmcia_init(); + return 0; +} +#endif + +#if defined(CONFIG_CMD_IDE) +static int initr_ide(void) +{ +#ifdef CONFIG_IDE_8xx_PCCARD + puts("PCMCIA:"); +#else + puts("IDE: "); +#endif +#if defined(CONFIG_START_IDE) + if (board_start_ide()) + ide_init(); +#else + ide_init(); +#endif + return 0; +} +#endif + +#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) +/* + * Export available size of memory for Linux, taking into account the + * protected RAM at top of memory + */ +int initr_mem(void) +{ + ulong pram = 0; + char memsz[32]; + +# ifdef CONFIG_PRAM + pram = getenv_ulong("pram", 10, CONFIG_PRAM); +# endif +# if defined(CONFIG_LOGBUFFER) && !defined(CONFIG_ALT_LB_ADDR) + /* Also take the logbuffer into account (pram is in kB) */ + pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024; +# endif + sprintf(memsz, "%ldk", (gd->ram_size / 1024) - pram); + setenv("mem", memsz); + + return 0; +} +#endif + +#ifdef CONFIG_CMD_BEDBUG +static int initr_bedbug(void) +{ + bedbug_init(); + + return 0; +} +#endif + +#ifdef CONFIG_PS2KBD +static int initr_kbd(void) +{ + puts("PS/2: "); + kbd_init(); + return 0; +} +#endif + +#ifdef CONFIG_MODEM_SUPPORT +static int initr_modem(void) +{ + /* TODO: with new initcalls, move this into the driver */ + extern int do_mdm_init; + + do_mdm_init = gd->do_mdm_init; + return 0; +} +#endif + +static int run_main_loop(void) +{ + /* main_loop() can return to retry autoboot, if so just run it again */ + for (;;) + main_loop(); + return 0; +} + +/* + * Over time we hope to remove these functions with code fragments and + * stub funtcions, and instead call the relevant function directly. + * + * We also hope to remove most of the driver-related init and do it if/when + * the driver is later used. + * + * TODO: perhaps reset the watchdog in the initcall function after each call? + */ +init_fnc_t init_sequence_r[] = { + initr_reloc, + /* TODO: could x86/PPC have this also perhaps? */ +#ifdef CONFIG_ARM + initr_caches, + board_init, /* Setup chipselects */ +#endif + /* + * TODO: printing of the clock inforamtion of the board is now + * implemented as part of bdinfo command. Currently only support for + * davinci SOC's is added. Remove this check once all the board + * implement this. + */ +#ifdef CONFIG_CLOCKS + set_cpu_clk_info, /* Setup clock information */ +#endif +#ifdef CONFIG_X86 + init_bd_struct_r, +#endif + initr_reloc_global_data, + initr_serial, + initr_announce, + INIT_FUNC_WATCHDOG_RESET +#ifdef CONFIG_PPC + initr_trap, +#endif +#ifdef CONFIG_ADDR_MAP + initr_addr_map, +#endif +#if defined(CONFIG_BOARD_EARLY_INIT_R) + board_early_init_r, +#endif + INIT_FUNC_WATCHDOG_RESET +#ifdef CONFIG_LOGBUFFER + initr_logbuffer, +#endif +#ifdef CONFIG_POST + initr_post_backlog, +#endif + INIT_FUNC_WATCHDOG_RESET +#ifdef CONFIG_SYS_DELAYED_ICACHE + initr_icache_enable, +#endif +#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) + initr_unlock_ram_in_cache, +#endif +#if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT) + /* + * Do early PCI configuration _before_ the flash gets initialised, + * because PCU ressources are crucial for flash access on some boards. + */ + initr_pci, +#endif +#ifdef CONFIG_WINBOND_83C553 + initr_w83c553f, +#endif + initr_barrier, + initr_malloc, +#ifdef CONFIG_ARCH_EARLY_INIT_R + arch_early_init_r, +#endif + power_init_board, +#ifndef CONFIG_SYS_NO_FLASH + initr_flash, +#endif + INIT_FUNC_WATCHDOG_RESET +#if defined(CONFIG_PPC) || defined(CONFIG_X86) + /* initialize higher level parts of CPU like time base and timers */ + cpu_init_r, +#endif +#ifdef CONFIG_PPC + initr_spi, +#endif +#if defined(CONFIG_X86) && defined(CONFIG_SPI) + init_func_spi, +#endif +#ifdef CONFIG_CMD_NAND + initr_nand, +#endif +#ifdef CONFIG_CMD_ONENAND + initr_onenand, +#endif +#ifdef CONFIG_GENERIC_MMC + initr_mmc, +#endif +#ifdef CONFIG_HAS_DATAFLASH + initr_dataflash, +#endif + initr_env, + INIT_FUNC_WATCHDOG_RESET + initr_secondary_cpu, +#ifdef CONFIG_SC3 + initr_sc3_read_eeprom, +#endif +#ifdef CONFIG_HERMES + initr_hermes, +#endif +#if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET) + mac_read_from_eeprom, +#endif + INIT_FUNC_WATCHDOG_RESET +#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT) + /* + * Do pci configuration + */ + initr_pci, +#endif + stdio_init, + initr_jumptable, +#ifdef CONFIG_API + initr_api, +#endif + console_init_r, /* fully init console as a device */ +#ifdef CONFIG_DISPLAY_BOARDINFO_LATE + show_model_r, +#endif +#ifdef CONFIG_ARCH_MISC_INIT + arch_misc_init, /* miscellaneous arch-dependent init */ +#endif +#ifdef CONFIG_MISC_INIT_R + misc_init_r, /* miscellaneous platform-dependent init */ +#endif +#ifdef CONFIG_HERMES + initr_hermes_start, +#endif + INIT_FUNC_WATCHDOG_RESET +#ifdef CONFIG_CMD_KGDB + initr_kgdb, +#endif +#ifdef CONFIG_X86 + board_early_init_r, +#endif + interrupt_init, +#if defined(CONFIG_ARM) || defined(CONFIG_x86) + initr_enable_interrupts, +#endif +#ifdef CONFIG_X86 + timer_init, /* initialize timer */ +#endif +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + initr_status_led, +#endif + /* PPC has a udelay(20) here dating from 2002. Why? */ +#ifdef CONFIG_CMD_NET + initr_ethaddr, +#endif +#ifdef CONFIG_BOARD_LATE_INIT + board_late_init, +#endif +#ifdef CONFIG_CMD_SCSI + INIT_FUNC_WATCHDOG_RESET + initr_scsi, +#endif +#ifdef CONFIG_CMD_DOC + INIT_FUNC_WATCHDOG_RESET + initr_doc, +#endif +#ifdef CONFIG_BITBANGMII + initr_bbmii, +#endif +#ifdef CONFIG_CMD_NET + INIT_FUNC_WATCHDOG_RESET + initr_net, +#endif +#ifdef CONFIG_POST + initr_post, +#endif +#if defined(CONFIG_CMD_PCMCIA) && !defined(CONFIG_CMD_IDE) + initr_pcmcia, +#endif +#if defined(CONFIG_CMD_IDE) + initr_ide, +#endif +#ifdef CONFIG_LAST_STAGE_INIT + INIT_FUNC_WATCHDOG_RESET + /* + * Some parts can be only initialized if all others (like + * Interrupts) are up and running (i.e. the PC-style ISA + * keyboard). + */ + last_stage_init, +#endif +#ifdef CONFIG_CMD_BEDBUG + INIT_FUNC_WATCHDOG_RESET + initr_bedbug, +#endif +#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) + initr_mem, +#endif +#ifdef CONFIG_PS2KBD + initr_kbd, +#endif +#ifdef CONFIG_MODEM_SUPPORT + initr_modem, +#endif + run_main_loop, +}; + +void board_init_r(gd_t *new_gd, ulong dest_addr) +{ +#ifndef CONFIG_X86 + gd = new_gd; +#endif + if (initcall_run_list(init_sequence_r)) + hang(); + + /* NOTREACHED - run_main_loop() does not return */ + hang(); +} diff --git a/common/cmd_bedbug.c b/common/cmd_bedbug.c index 9791423..77b6e3e 100644 --- a/common/cmd_bedbug.c +++ b/common/cmd_bedbug.c @@ -292,7 +292,7 @@ int do_bedbug_step (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) return 1; } - if (!find_next_address ((unsigned char *) &addr, FALSE, bug_ctx.regs)) + if (!find_next_address((unsigned char *) &addr, false, bug_ctx.regs)) return 1; if (bug_ctx.set) @@ -323,7 +323,7 @@ int do_bedbug_next (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) return 1; } - if (!find_next_address ((unsigned char *) &addr, TRUE, bug_ctx.regs)) + if (!find_next_address((unsigned char *) &addr, true, bug_ctx.regs)) return 1; if (bug_ctx.set) diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 2e93352..7438469 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -88,7 +88,7 @@ static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); #include <linux/err.h> #include <nand.h> -#ifdef CONFIG_SILENT_CONSOLE +#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY) static void fixup_silent_linux(void); #endif @@ -128,6 +128,9 @@ static boot_os_fn do_bootm_rtems; #if defined(CONFIG_BOOTM_OSE) static boot_os_fn do_bootm_ose; #endif +#if defined(CONFIG_BOOTM_PLAN9) +static boot_os_fn do_bootm_plan9; +#endif #if defined(CONFIG_CMD_ELF) static boot_os_fn do_bootm_vxworks; static boot_os_fn do_bootm_qnxelf; @@ -154,6 +157,9 @@ static boot_os_fn *boot_os[] = { #if defined(CONFIG_BOOTM_OSE) [IH_OS_OSE] = do_bootm_ose, #endif +#if defined(CONFIG_BOOTM_PLAN9) + [IH_OS_PLAN9] = do_bootm_plan9, +#endif #if defined(CONFIG_CMD_ELF) [IH_OS_VXWORKS] = do_bootm_vxworks, [IH_OS_QNX] = do_bootm_qnxelf, @@ -694,7 +700,7 @@ int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) bootstage_mark(BOOTSTAGE_ID_CHECK_BOOT_OS); -#ifdef CONFIG_SILENT_CONSOLE +#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY) if (images.os.os == IH_OS_LINUX) fixup_silent_linux(); #endif @@ -1413,7 +1419,7 @@ U_BOOT_CMD( /*******************************************************************/ /* helper routines */ /*******************************************************************/ -#ifdef CONFIG_SILENT_CONSOLE +#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY) static void fixup_silent_linux(void) { char buf[256], *start, *end; @@ -1628,6 +1634,39 @@ static int do_bootm_ose(int flag, int argc, char * const argv[], } #endif /* CONFIG_BOOTM_OSE */ +#if defined(CONFIG_BOOTM_PLAN9) +static int do_bootm_plan9(int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + void (*entry_point)(void); + + if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) + return 1; + +#if defined(CONFIG_FIT) + if (!images->legacy_hdr_valid) { + fit_unsupported_reset("Plan 9"); + return 1; + } +#endif + + entry_point = (void (*)(void))images->ep; + + printf("## Transferring control to Plan 9 (at address %08lx) ...\n", + (ulong)entry_point); + + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + + /* + * Plan 9 Parameters: + * None + */ + (*entry_point)(); + + return 1; +} +#endif /* CONFIG_BOOTM_PLAN9 */ + #if defined(CONFIG_CMD_ELF) static int do_bootm_vxworks(int flag, int argc, char * const argv[], bootm_headers_t *images) @@ -1806,7 +1845,7 @@ static int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) usb_stop(); #endif -#ifdef CONFIG_SILENT_CONSOLE +#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY) fixup_silent_linux(); #endif arch_preboot_os(); diff --git a/common/cmd_bootmenu.c b/common/cmd_bootmenu.c new file mode 100644 index 0000000..a3cbffa --- /dev/null +++ b/common/cmd_bootmenu.c @@ -0,0 +1,517 @@ +/* + * (C) Copyright 2011-2013 Pali Rohár <pali.rohar@gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <ansi.h> +#include <menu.h> +#include <hush.h> +#include <watchdog.h> +#include <malloc.h> +#include <linux/string.h> + +/* maximum bootmenu entries */ +#define MAX_COUNT 99 + +/* maximal size of bootmenu env + * 9 = strlen("bootmenu_") + * 2 = strlen(MAX_COUNT) + * 1 = NULL term + */ +#define MAX_ENV_SIZE (9 + 2 + 1) + +struct bootmenu_entry { + unsigned short int num; /* unique number 0 .. MAX_COUNT */ + char key[3]; /* key identifier of number */ + char *title; /* title of entry */ + char *command; /* hush command of entry */ + struct bootmenu_data *menu; /* this bootmenu */ + struct bootmenu_entry *next; /* next menu entry (num+1) */ +}; + +struct bootmenu_data { + int delay; /* delay for autoboot */ + int active; /* active menu entry */ + int count; /* total count of menu entries */ + struct bootmenu_entry *first; /* first menu entry */ +}; + +enum bootmenu_key { + KEY_NONE = 0, + KEY_UP, + KEY_DOWN, + KEY_SELECT, +}; + +static char *bootmenu_getoption(unsigned short int n) +{ + char name[MAX_ENV_SIZE] = "bootmenu_"; + + if (n > MAX_COUNT) + return NULL; + + sprintf(name + 9, "%d", n); + return getenv(name); +} + +static void bootmenu_print_entry(void *data) +{ + struct bootmenu_entry *entry = data; + int reverse = (entry->menu->active == entry->num); + + /* + * Move cursor to line where the entry will be drown (entry->num) + * First 3 lines contain bootmenu header + 1 empty line + */ + printf(ANSI_CURSOR_POSITION, entry->num + 4, 1); + + puts(" "); + + if (reverse) + puts(ANSI_COLOR_REVERSE); + + puts(entry->title); + + if (reverse) + puts(ANSI_COLOR_RESET); +} + +static void bootmenu_autoboot_loop(struct bootmenu_data *menu, + enum bootmenu_key *key, int *esc) +{ + int i, c; + + if (menu->delay > 0) { + printf(ANSI_CURSOR_POSITION, menu->count + 5, 1); + printf(" Hit any key to stop autoboot: %2d ", menu->delay); + } + + while (menu->delay > 0) { + for (i = 0; i < 100; ++i) { + if (!tstc()) { + WATCHDOG_RESET(); + mdelay(10); + continue; + } + + menu->delay = -1; + c = getc(); + + switch (c) { + case '\e': + *esc = 1; + *key = KEY_NONE; + break; + case '\r': + *key = KEY_SELECT; + break; + default: + *key = KEY_NONE; + break; + } + + break; + } + + if (menu->delay < 0) + break; + + --menu->delay; + printf("\b\b\b%2d ", menu->delay); + } + + printf(ANSI_CURSOR_POSITION, menu->count + 5, 1); + puts(ANSI_CLEAR_LINE); + + if (menu->delay == 0) + *key = KEY_SELECT; +} + +static void bootmenu_loop(struct bootmenu_data *menu, + enum bootmenu_key *key, int *esc) +{ + int c; + + while (!tstc()) { + WATCHDOG_RESET(); + mdelay(10); + } + + c = getc(); + + switch (*esc) { + case 0: + /* First char of ANSI escape sequence '\e' */ + if (c == '\e') { + *esc = 1; + *key = KEY_NONE; + } + break; + case 1: + /* Second char of ANSI '[' */ + if (c == '[') { + *esc = 2; + *key = KEY_NONE; + } else { + *esc = 0; + } + break; + case 2: + case 3: + /* Third char of ANSI (number '1') - optional */ + if (*esc == 2 && c == '1') { + *esc = 3; + *key = KEY_NONE; + break; + } + + *esc = 0; + + /* ANSI 'A' - key up was pressed */ + if (c == 'A') + *key = KEY_UP; + /* ANSI 'B' - key down was pressed */ + else if (c == 'B') + *key = KEY_DOWN; + /* other key was pressed */ + else + *key = KEY_NONE; + + break; + } + + /* enter key was pressed */ + if (c == '\r') + *key = KEY_SELECT; +} + +static char *bootmenu_choice_entry(void *data) +{ + struct bootmenu_data *menu = data; + struct bootmenu_entry *iter; + enum bootmenu_key key = KEY_NONE; + int esc = 0; + int i; + + while (1) { + if (menu->delay >= 0) { + /* Autoboot was not stopped */ + bootmenu_autoboot_loop(menu, &key, &esc); + } else { + /* Some key was pressed, so autoboot was stopped */ + bootmenu_loop(menu, &key, &esc); + } + + switch (key) { + case KEY_UP: + if (menu->active > 0) + --menu->active; + /* no menu key selected, regenerate menu */ + return NULL; + case KEY_DOWN: + if (menu->active < menu->count - 1) + ++menu->active; + /* no menu key selected, regenerate menu */ + return NULL; + case KEY_SELECT: + iter = menu->first; + for (i = 0; i < menu->active; ++i) + iter = iter->next; + return iter->key; + default: + break; + } + } + + /* never happens */ + debug("bootmenu: this should not happen"); + return NULL; +} + +static void bootmenu_destroy(struct bootmenu_data *menu) +{ + struct bootmenu_entry *iter = menu->first; + struct bootmenu_entry *next; + + while (iter) { + next = iter->next; + free(iter->title); + free(iter->command); + free(iter); + iter = next; + } + free(menu); +} + +static struct bootmenu_data *bootmenu_create(int delay) +{ + unsigned short int i = 0; + const char *option; + struct bootmenu_data *menu; + struct bootmenu_entry *iter = NULL; + + int len; + char *sep; + struct bootmenu_entry *entry; + + menu = malloc(sizeof(struct bootmenu_data)); + if (!menu) + return NULL; + + menu->delay = delay; + menu->active = 0; + menu->first = NULL; + + while ((option = bootmenu_getoption(i))) { + sep = strchr(option, '='); + if (!sep) { + printf("Invalid bootmenu entry: %s\n", option); + break; + } + + entry = malloc(sizeof(struct bootmenu_entry)); + if (!entry) + goto cleanup; + + len = sep-option; + entry->title = malloc(len + 1); + if (!entry->title) { + free(entry); + goto cleanup; + } + memcpy(entry->title, option, len); + entry->title[len] = 0; + + len = strlen(sep + 1); + entry->command = malloc(len + 1); + if (!entry->command) { + free(entry->title); + free(entry); + goto cleanup; + } + memcpy(entry->command, sep + 1, len); + entry->command[len] = 0; + + sprintf(entry->key, "%d", i); + + entry->num = i; + entry->menu = menu; + entry->next = NULL; + + if (!iter) + menu->first = entry; + else + iter->next = entry; + + iter = entry; + ++i; + + if (i == MAX_COUNT - 1) + break; + } + + /* Add U-Boot console entry at the end */ + if (i <= MAX_COUNT - 1) { + entry = malloc(sizeof(struct bootmenu_entry)); + if (!entry) + goto cleanup; + + entry->title = strdup("U-Boot console"); + if (!entry->title) { + free(entry); + goto cleanup; + } + + entry->command = strdup(""); + if (!entry->command) { + free(entry->title); + free(entry); + goto cleanup; + } + + sprintf(entry->key, "%d", i); + + entry->num = i; + entry->menu = menu; + entry->next = NULL; + + if (!iter) + menu->first = entry; + else + iter->next = entry; + + iter = entry; + ++i; + } + + menu->count = i; + return menu; + +cleanup: + bootmenu_destroy(menu); + return NULL; +} + +static void bootmenu_show(int delay) +{ + int init = 0; + void *choice = NULL; + char *title = NULL; + char *command = NULL; + struct menu *menu; + struct bootmenu_data *bootmenu; + struct bootmenu_entry *iter; + char *option, *sep; + + /* If delay is 0 do not create menu, just run first entry */ + if (delay == 0) { + option = bootmenu_getoption(0); + if (!option) { + puts("bootmenu option 0 was not found\n"); + return; + } + sep = strchr(option, '='); + if (!sep) { + puts("bootmenu option 0 is invalid\n"); + return; + } + run_command(sep+1, 0); + return; + } + + bootmenu = bootmenu_create(delay); + if (!bootmenu) + return; + + menu = menu_create(NULL, bootmenu->delay, 1, bootmenu_print_entry, + bootmenu_choice_entry, bootmenu); + if (!menu) { + bootmenu_destroy(bootmenu); + return; + } + + for (iter = bootmenu->first; iter; iter = iter->next) { + if (!menu_item_add(menu, iter->key, iter)) + goto cleanup; + } + + /* Default menu entry is always first */ + menu_default_set(menu, "0"); + + puts(ANSI_CURSOR_HIDE); + puts(ANSI_CLEAR_CONSOLE); + printf(ANSI_CURSOR_POSITION, 1, 1); + + init = 1; + + if (menu_get_choice(menu, &choice)) { + iter = choice; + title = strdup(iter->title); + command = strdup(iter->command); + } + +cleanup: + menu_destroy(menu); + bootmenu_destroy(bootmenu); + + if (init) { + puts(ANSI_CURSOR_SHOW); + puts(ANSI_CLEAR_CONSOLE); + printf(ANSI_CURSOR_POSITION, 1, 1); + } + + if (title && command) { + debug("Starting entry '%s'\n", title); + free(title); + run_command(command, 0); + free(command); + } + +#ifdef CONFIG_POSTBOOTMENU + run_command(CONFIG_POSTBOOTMENU, 0); +#endif +} + +void menu_display_statusline(struct menu *m) +{ + struct bootmenu_entry *entry; + struct bootmenu_data *menu; + + if (menu_default_choice(m, (void *)&entry) < 0) + return; + + menu = entry->menu; + + printf(ANSI_CURSOR_POSITION, 1, 1); + puts(ANSI_CLEAR_LINE); + printf(ANSI_CURSOR_POSITION, 2, 1); + puts(" *** U-Boot Boot Menu ***"); + puts(ANSI_CLEAR_LINE_TO_END); + printf(ANSI_CURSOR_POSITION, 3, 1); + puts(ANSI_CLEAR_LINE); + + /* First 3 lines are bootmenu header + 2 empty lines between entries */ + printf(ANSI_CURSOR_POSITION, menu->count + 5, 1); + puts(ANSI_CLEAR_LINE); + printf(ANSI_CURSOR_POSITION, menu->count + 6, 1); + puts(" Press UP/DOWN to move, ENTER to select"); + puts(ANSI_CLEAR_LINE_TO_END); + printf(ANSI_CURSOR_POSITION, menu->count + 7, 1); + puts(ANSI_CLEAR_LINE); +} + +#ifdef CONFIG_MENU_SHOW +int menu_show(int bootdelay) +{ + bootmenu_show(bootdelay); + return -1; /* -1 - abort boot and run monitor code */ +} +#endif + +int do_bootmenu(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + char *delay_str = NULL; + int delay = 10; + +#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) + delay = CONFIG_BOOTDELAY; +#endif + + if (argc >= 2) + delay_str = argv[1]; + + if (!delay_str) + delay_str = getenv("bootmenu_delay"); + + if (delay_str) + delay = (int)simple_strtol(delay_str, NULL, 10); + + bootmenu_show(delay); + return 0; +} + +U_BOOT_CMD( + bootmenu, 2, 1, do_bootmenu, + "ANSI terminal bootmenu", + "[delay]\n" + " - show ANSI terminal bootmenu with autoboot delay" +); diff --git a/common/cmd_df.c b/common/cmd_df.c deleted file mode 100644 index f7e5df3..0000000 --- a/common/cmd_df.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Command for accessing DataFlash. - * - * Copyright (C) 2008 Atmel Corporation - */ -#include <common.h> -#include <df.h> - -static int do_df(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - const char *cmd; - - /* need at least two arguments */ - if (argc < 2) - goto usage; - - cmd = argv[1]; - - if (strcmp(cmd, "init") == 0) { - df_init(0, 0, 1000000); - return 0; - } - - if (strcmp(cmd, "info") == 0) { - df_show_info(); - return 0; - } - -usage: - return CMD_RET_USAGE; -} - -U_BOOT_CMD( - sf, 2, 1, do_serial_flash, - "Serial flash sub-system", - "probe [bus:]cs - init flash device on given SPI bus and CS") diff --git a/common/cmd_dfu.c b/common/cmd_dfu.c index 01d6b3a..83ef324 100644 --- a/common/cmd_dfu.c +++ b/common/cmd_dfu.c @@ -50,12 +50,15 @@ static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (ret) return CMD_RET_FAILURE; - if (strcmp(argv[3], "list") == 0) { + if (argc > 3 && strcmp(argv[3], "list") == 0) { dfu_show_entities(); goto done; } +#ifdef CONFIG_TRATS board_usb_init(); +#endif + g_dnl_register(s); while (1) { if (ctrlc()) diff --git a/common/cmd_dtt.c b/common/cmd_dtt.c index cd94423..edbd4a8 100644 --- a/common/cmd_dtt.c +++ b/common/cmd_dtt.c @@ -27,7 +27,9 @@ #include <dtt.h> #include <i2c.h> +#include <tmu.h> +#if defined CONFIG_DTT_SENSORS static unsigned long sensor_initialized; static void _initialize_dtt(void) @@ -59,9 +61,11 @@ void dtt_init(void) /* switch back to original I2C bus */ I2C_SET_BUS(old_bus); } +#endif -int do_dtt (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +int dtt_i2c(void) { +#if defined CONFIG_DTT_SENSORS int i; unsigned char sensors[] = CONFIG_DTT_SENSORS; int old_bus; @@ -83,8 +87,34 @@ int do_dtt (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) /* switch back to original I2C bus */ I2C_SET_BUS(old_bus); +#endif return 0; +} + +int dtt_tmu(void) +{ +#if defined CONFIG_TMU_CMD_DTT + int cur_temp; + + /* Sense and return latest thermal info */ + if (tmu_monitor(&cur_temp) == TMU_STATUS_INIT) { + puts("TMU is in unknown state, temperature is invalid\n"); + return -1; + } + printf("Current temperature: %u degrees Celsius\n", cur_temp); +#endif + return 0; +} + +int do_dtt(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int err = 0; + + err |= dtt_i2c(); + err |= dtt_tmu(); + + return err; } /* do_dtt() */ /***************************************************/ diff --git a/common/cmd_ext4.c b/common/cmd_ext4.c index dcf76a5..706fd54 100644 --- a/common/cmd_ext4.c +++ b/common/cmd_ext4.c @@ -88,10 +88,10 @@ int do_ext4_write(cmd_tbl_t *cmdtp, int flag, int argc, dev = dev_desc->dev; /* get the filename */ - filename = argv[3]; + filename = argv[4]; /* get the address in hexadecimal format (string to int) */ - ram_address = simple_strtoul(argv[4], NULL, 16); + ram_address = simple_strtoul(argv[3], NULL, 16); /* get the filesize in base 10 format */ file_size = simple_strtoul(argv[5], NULL, 10); @@ -122,7 +122,7 @@ fail: U_BOOT_CMD(ext4write, 6, 1, do_ext4_write, "create a file in the root directory", - "<interface> <dev[:part]> [Absolute filename path] [Address] [sizebytes]\n" + "<interface> <dev[:part]> <addr> <absolute filename path> [sizebytes]\n" " - create a file in / directory"); #endif diff --git a/common/cmd_fat.c b/common/cmd_fat.c index 86be044..0487438 100644 --- a/common/cmd_fat.c +++ b/common/cmd_fat.c @@ -49,6 +49,9 @@ U_BOOT_CMD( " If 'pos' is omitted, 0 is used. 'pos' requires 'bytes'.\n" " 'bytes' gives the size to load. If 'bytes' is 0 or omitted,\n" " the load stops on end of file.\n" + " If either 'pos' or 'bytes' are not aligned to\n" + " ARCH_DMA_MINALIGN then a misaligned buffer warning will\n" + " be printed and performance will suffer for the load.\n" " All numeric parameters are assumed to be hex." ); diff --git a/common/cmd_fdc.c b/common/cmd_fdc.c index 66e0ef0..dfa3690 100644 --- a/common/cmd_fdc.c +++ b/common/cmd_fdc.c @@ -39,13 +39,6 @@ #define PRINTF(fmt,args...) #endif -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - /*#if defined(CONFIG_CMD_DATE) */ /*#include <rtc.h> */ /*#endif */ @@ -214,9 +207,9 @@ int wait_for_fdc_int(void) timeout--; udelay(10); if(timeout==0) /* timeout occured */ - return FALSE; + return false; } - return TRUE; + return true; } /* reads a byte from the FIFO of the FDC and checks direction and RQM bit @@ -244,7 +237,7 @@ int fdc_need_more_output(void) c=(unsigned char)read_fdc_byte(); printf("Error: more output: %x\n",c); } - return TRUE; + return true; } @@ -260,10 +253,10 @@ int write_fdc_byte(unsigned char val) udelay(10); fdc_need_more_output(); if(timeout==0) /* timeout occured */ - return FALSE; + return false; } write_fdc_reg(FDC_FIFO,val); - return TRUE; + return true; } /* sets up all FDC commands and issues it to the FDC. If @@ -344,9 +337,9 @@ int fdc_issue_cmd(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG) } for(i=0;i<pCMD->cmdlen;i++) { /* PRINTF("write cmd%d = 0x%02X\n",i,pCMD->cmd[i]); */ - if(write_fdc_byte(pCMD->cmd[i])==FALSE) { + if (write_fdc_byte(pCMD->cmd[i]) == false) { PRINTF("Error: timeout while issue cmd%d\n",i); - return FALSE; + return false; } } timeout=FDC_TIME_OUT; @@ -355,12 +348,12 @@ int fdc_issue_cmd(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG) timeout--; if(timeout==0) { PRINTF(" timeout while reading result%d MSR=0x%02X\n",i,read_fdc_reg(FDC_MSR)); - return FALSE; + return false; } } pCMD->result[i]=(unsigned char)read_fdc_byte(); } - return TRUE; + return true; } /* selects the drive assigned in the cmd structur and @@ -391,9 +384,10 @@ void stop_fdc_drive(FDC_COMMAND_STRUCT *pCMD) int fdc_recalibrate(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG) { pCMD->cmd[COMMAND]=FDC_CMD_RECALIBRATE; - if(fdc_issue_cmd(pCMD,pFG)==FALSE) - return FALSE; - while(wait_for_fdc_int()!=TRUE); + if (fdc_issue_cmd(pCMD, pFG) == false) + return false; + while (wait_for_fdc_int() != true); + pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT; return(fdc_issue_cmd(pCMD,pFG)); } @@ -403,9 +397,10 @@ int fdc_recalibrate(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG) int fdc_seek(FDC_COMMAND_STRUCT *pCMD,FD_GEO_STRUCT *pFG) { pCMD->cmd[COMMAND]=FDC_CMD_SEEK; - if(fdc_issue_cmd(pCMD,pFG)==FALSE) - return FALSE; - while(wait_for_fdc_int()!=TRUE); + if (fdc_issue_cmd(pCMD, pFG) == false) + return false; + while (wait_for_fdc_int() != true); + pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT; return(fdc_issue_cmd(pCMD,pFG)); } @@ -421,7 +416,7 @@ int fdc_terminate(FDC_COMMAND_STRUCT *pCMD) for(i=0;i<7;i++) { pCMD->result[i]=(unsigned char)read_fdc_byte(); } - return TRUE; + return true; } /* reads data from FDC, seek commands are issued automatic */ @@ -440,18 +435,18 @@ int fdc_read_data(unsigned char *buffer, unsigned long blocks,FDC_COMMAND_STRUCT retriesrw=0; retriescal=0; offset=0; - if(fdc_seek(pCMD,pFG)==FALSE) { + if (fdc_seek(pCMD, pFG) == false) { stop_fdc_drive(pCMD); if (flags) enable_interrupts(); - return FALSE; + return false; } if((pCMD->result[STATUS_0]&0x20)!=0x20) { printf("Seek error Status: %02X\n",pCMD->result[STATUS_0]); stop_fdc_drive(pCMD); if (flags) enable_interrupts(); - return FALSE; + return false; } /* now determine the next seek point */ /* lastblk=pCMD->blnr + blocks; */ @@ -466,11 +461,11 @@ int fdc_read_data(unsigned char *buffer, unsigned long blocks,FDC_COMMAND_STRUCT retryrw: len=sect_size * readblk; pCMD->cmd[COMMAND]=FDC_CMD_READ; - if(fdc_issue_cmd(pCMD,pFG)==FALSE) { + if (fdc_issue_cmd(pCMD, pFG) == false) { stop_fdc_drive(pCMD); if (flags) enable_interrupts(); - return FALSE; + return false; } for (i=0;i<len;i++) { timeout=FDC_TIME_OUT; @@ -492,15 +487,15 @@ retryrw: stop_fdc_drive(pCMD); if (flags) enable_interrupts(); - return FALSE; + return false; } else { PRINTF(" trying to recalibrate Try %d\n",retriescal); - if(fdc_recalibrate(pCMD,pFG)==FALSE) { + if (fdc_recalibrate(pCMD, pFG) == false) { stop_fdc_drive(pCMD); if (flags) enable_interrupts(); - return FALSE; + return false; } retriesrw=0; goto retrycal; @@ -512,7 +507,7 @@ retryrw: } /* else >FDC_RW_RETRIES */ }/* if output */ timeout--; - }while(TRUE); + } while (true); } /* for len */ /* the last sector of a track or all data has been read, * we need to get the results */ @@ -530,22 +525,22 @@ retryrw: readblk=blocks; retrycal: /* a seek is necessary */ - if(fdc_seek(pCMD,pFG)==FALSE) { + if (fdc_seek(pCMD, pFG) == false) { stop_fdc_drive(pCMD); if (flags) enable_interrupts(); - return FALSE; + return false; } if((pCMD->result[STATUS_0]&0x20)!=0x20) { PRINTF("Seek error Status: %02X\n",pCMD->result[STATUS_0]); stop_fdc_drive(pCMD); - return FALSE; + return false; } - }while(TRUE); /* start over */ + } while (true); /* start over */ stop_fdc_drive(pCMD); /* switch off drive */ if (flags) enable_interrupts(); - return TRUE; + return true; } /* Scan all drives and check if drive is present and disk is inserted */ @@ -559,20 +554,20 @@ int fdc_check_drive(FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG) pCMD->drive=drives; select_fdc_drive(pCMD); pCMD->blnr=0; /* set to the 1st block */ - if(fdc_recalibrate(pCMD,pFG)==FALSE) + if (fdc_recalibrate(pCMD, pFG) == false) continue; if((pCMD->result[STATUS_0]&0x10)==0x10) continue; /* ok drive connected check for disk */ state|=(1<<drives); pCMD->blnr=pFG->size; /* set to the last block */ - if(fdc_seek(pCMD,pFG)==FALSE) + if (fdc_seek(pCMD, pFG) == false) continue; pCMD->blnr=0; /* set to the 1st block */ - if(fdc_recalibrate(pCMD,pFG)==FALSE) + if (fdc_recalibrate(pCMD, pFG) == false) continue; pCMD->cmd[COMMAND]=FDC_CMD_READ_ID; - if(fdc_issue_cmd(pCMD,pFG)==FALSE) + if (fdc_issue_cmd(pCMD, pFG) == false) continue; state|=(0x10<<drives); } @@ -584,7 +579,7 @@ int fdc_check_drive(FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG) ((state&(0x10<<i))==(0x10<<i)) ? pFG->name : ""); } pCMD->flags=state; - return TRUE; + return true; } @@ -611,9 +606,9 @@ int fdc_setup(int drive, FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG) write_fdc_reg(FDC_CCR,pFG->rate); /* then initialize the DSR */ write_fdc_reg(FDC_DSR,pFG->rate); - if(wait_for_fdc_int()==FALSE) { + if (wait_for_fdc_int() == false) { PRINTF("Time Out after writing CCR\n"); - return FALSE; + return false; } /* now issue sense Interrupt and status command * assuming only one drive present (drive 0) */ @@ -621,7 +616,7 @@ int fdc_setup(int drive, FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG) for(i=0;i<4;i++) { /* issue sense interrupt for all 4 possible drives */ pCMD->cmd[COMMAND]=FDC_CMD_SENSE_INT; - if(fdc_issue_cmd(pCMD,pFG)==FALSE) { + if (fdc_issue_cmd(pCMD, pFG) == false) { PRINTF("Sense Interrupt for drive %d failed\n",i); } } @@ -629,24 +624,24 @@ int fdc_setup(int drive, FDC_COMMAND_STRUCT *pCMD, FD_GEO_STRUCT *pFG) pCMD->drive=drive; select_fdc_drive(pCMD); pCMD->cmd[COMMAND]=FDC_CMD_CONFIGURE; - if(fdc_issue_cmd(pCMD,pFG)==FALSE) { + if (fdc_issue_cmd(pCMD, pFG) == false) { PRINTF(" configure timeout\n"); stop_fdc_drive(pCMD); - return FALSE; + return false; } /* issue specify command */ pCMD->cmd[COMMAND]=FDC_CMD_SPECIFY; - if(fdc_issue_cmd(pCMD,pFG)==FALSE) { + if (fdc_issue_cmd(pCMD, pFG) == false) { PRINTF(" specify timeout\n"); stop_fdc_drive(pCMD); - return FALSE; + return false; } /* then, we clear the reset in the DOR */ /* fdc_check_drive(pCMD,pFG); */ /* write_fdc_reg(FDC_DOR,0x04); */ - return TRUE; + return true; } #if defined(CONFIG_CMD_FDOS) @@ -664,30 +659,30 @@ int fdc_fdos_init (int drive) FDC_COMMAND_STRUCT *pCMD = &cmd; /* setup FDC and scan for drives */ - if(fdc_setup(drive,pCMD,pFG)==FALSE) { + if (fdc_setup(drive, pCMD, pFG) == false) { printf("\n** Error in setup FDC **\n"); - return FALSE; + return false; } - if(fdc_check_drive(pCMD,pFG)==FALSE) { + if (fdc_check_drive(pCMD, pFG) == false) { printf("\n** Error in check_drives **\n"); - return FALSE; + return false; } if((pCMD->flags&(1<<drive))==0) { /* drive not available */ printf("\n** Drive %d not available **\n",drive); - return FALSE; + return false; } if((pCMD->flags&(0x10<<drive))==0) { /* no disk inserted */ printf("\n** No disk inserted in drive %d **\n",drive); - return FALSE; + return false; } /* ok, we have a valid source */ pCMD->drive=drive; /* read first block */ pCMD->blnr=0; - return TRUE; + return true; } /************************************************************************** * int fdc_fdos_seek @@ -747,11 +742,11 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return CMD_RET_USAGE; } /* setup FDC and scan for drives */ - if(fdc_setup(boot_drive,pCMD,pFG)==FALSE) { + if (fdc_setup(boot_drive, pCMD, pFG) == false) { printf("\n** Error in setup FDC **\n"); return 1; } - if(fdc_check_drive(pCMD,pFG)==FALSE) { + if (fdc_check_drive(pCMD, pFG) == false) { printf("\n** Error in check_drives **\n"); return 1; } @@ -769,7 +764,7 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) pCMD->drive=boot_drive; /* read first block */ pCMD->blnr=0; - if(fdc_read_data((unsigned char *)addr,1,pCMD,pFG)==FALSE) { + if (fdc_read_data((unsigned char *)addr, 1, pCMD, pFG) == false) { printf("\nRead error:"); for(i=0;i<7;i++) printf("result%d: 0x%02X\n",i,pCMD->result[i]); @@ -801,7 +796,7 @@ int do_fdcboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) nrofblk++; printf("Loading %ld Bytes (%d blocks) at 0x%08lx..\n",imsize,nrofblk,addr); pCMD->blnr=0; - if(fdc_read_data((unsigned char *)addr,nrofblk,pCMD,pFG)==FALSE) { + if (fdc_read_data((unsigned char *)addr, nrofblk, pCMD, pFG) == false) { /* read image block */ printf("\nRead error:"); for(i=0;i<7;i++) diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 042c994..64dd76a 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -631,6 +631,7 @@ int do_mem_loopw (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif /* CONFIG_LOOPW */ +#ifdef CONFIG_CMD_MEMTEST static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr, vu_long *dummy) { @@ -1002,7 +1003,7 @@ static int do_mem_mtest(cmd_tbl_t *cmdtp, int flag, int argc, return ret; /* not reached */ } - +#endif /* CONFIG_CMD_MEMTEST */ /* Modify memory. * @@ -1240,11 +1241,13 @@ U_BOOT_CMD( ); #endif /* CONFIG_LOOPW */ +#ifdef CONFIG_CMD_MEMTEST U_BOOT_CMD( mtest, 5, 1, do_mem_mtest, "simple RAM read/write test", "[start [end [pattern [iterations]]]]" ); +#endif /* CONFIG_CMD_MEMTEST */ #ifdef CONFIG_MX_CYCLIC U_BOOT_CMD( diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 8c53a10..9f3d6c5 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -164,8 +164,12 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } if (strcmp(argv[1], "rescan") == 0) { - struct mmc *mmc = find_mmc_device(curr_device); + struct mmc *mmc; + if (argc != 2) + return CMD_RET_USAGE; + + mmc = find_mmc_device(curr_device); if (!mmc) { printf("no mmc device at slot %x\n", curr_device); return 1; @@ -179,8 +183,12 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } else if (strncmp(argv[1], "part", 4) == 0) { block_dev_desc_t *mmc_dev; - struct mmc *mmc = find_mmc_device(curr_device); + struct mmc *mmc; + + if (argc != 2) + return CMD_RET_USAGE; + mmc = find_mmc_device(curr_device); if (!mmc) { printf("no mmc device at slot %x\n", curr_device); return 1; @@ -196,6 +204,8 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) puts("get mmc type error!\n"); return 1; } else if (strcmp(argv[1], "list") == 0) { + if (argc != 2) + return CMD_RET_USAGE; print_mmc_devices('\n'); return 0; } else if (strcmp(argv[1], "dev") == 0) { diff --git a/common/cmd_mtdparts.c b/common/cmd_mtdparts.c index 0cfca0c..1c35f9d 100644 --- a/common/cmd_mtdparts.c +++ b/common/cmd_mtdparts.c @@ -106,6 +106,8 @@ #include <onenand_uboot.h> #endif +DECLARE_GLOBAL_DATA_PTR; + /* special size referring to all the remaining space in a partition */ #define SIZE_REMAINING 0xFFFFFFFF @@ -1420,7 +1422,7 @@ static int delete_partition(const char *id) return 1; if (generate_mtdparts_save(last_parts, MTDPARTS_MAXLEN) != 0) { - printf("generated mtdparts too long, reseting to null\n"); + printf("generated mtdparts too long, resetting to null\n"); return 1; } return 0; @@ -1518,7 +1520,7 @@ static int spread_partitions(void) index_partitions(); if (generate_mtdparts_save(last_parts, MTDPARTS_MAXLEN) != 0) { - printf("generated mtdparts too long, reseting to null\n"); + printf("generated mtdparts too long, resetting to null\n"); return 1; } return 0; @@ -1537,6 +1539,7 @@ static int parse_mtdparts(const char *const mtdparts) const char *p = mtdparts; struct mtd_device *dev; int err = 1; + char tmp_parts[MTDPARTS_MAXLEN]; debug("\n---parse_mtdparts---\nmtdparts = %s\n\n", p); @@ -1547,7 +1550,12 @@ static int parse_mtdparts(const char *const mtdparts) } /* re-read 'mtdparts' variable, mtd_devices_init may be updating env */ - p = getenv("mtdparts"); + if (gd->flags & GD_FLG_ENV_READY) { + p = getenv("mtdparts"); + } else { + p = tmp_parts; + getenv_f("mtdparts", tmp_parts, MTDPARTS_MAXLEN); + } if (strncmp(p, "mtdparts=", 9) != 0) { printf("mtdparts variable doesn't start with 'mtdparts='\n"); @@ -1705,6 +1713,7 @@ int mtdparts_init(void) const char *current_partition; int ids_changed; char tmp_ep[PARTITION_MAXLEN]; + char tmp_parts[MTDPARTS_MAXLEN]; debug("\n---mtdparts_init---\n"); if (!initialized) { @@ -1718,7 +1727,17 @@ int mtdparts_init(void) /* get variables */ ids = getenv("mtdids"); - parts = getenv("mtdparts"); + /* + * The mtdparts variable tends to be long. If we need to access it + * before the env is relocated, then we need to use our own stack + * buffer. gd->env_buf will be too small. + */ + if (gd->flags & GD_FLG_ENV_READY) { + parts = getenv("mtdparts"); + } else { + parts = tmp_parts; + getenv_f("mtdparts", tmp_parts, MTDPARTS_MAXLEN); + } current_partition = getenv("partition"); /* save it for later parsing, cannot rely on current partition pointer @@ -2016,7 +2035,7 @@ static int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc, } if (generate_mtdparts_save(last_parts, MTDPARTS_MAXLEN) != 0) { - printf("generated mtdparts too long, reseting to null\n"); + printf("generated mtdparts too long, resetting to null\n"); return 1; } diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 32348f3..e9d3d3c 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -137,7 +137,8 @@ static inline int str2long(const char *p, ulong *num) return *p != '\0' && *endptr == '\0'; } -static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size) +static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size, + loff_t *maxsize) { #ifdef CONFIG_CMD_MTDPARTS struct mtd_device *dev; @@ -160,6 +161,7 @@ static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size) *off = part->offset; *size = part->size; + *maxsize = part->size; *idx = dev->id->num; ret = set_dev(*idx); @@ -173,10 +175,11 @@ static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size) #endif } -static int arg_off(const char *arg, int *idx, loff_t *off, loff_t *maxsize) +static int arg_off(const char *arg, int *idx, loff_t *off, loff_t *size, + loff_t *maxsize) { if (!str2off(arg, off)) - return get_part(arg, idx, off, maxsize); + return get_part(arg, idx, off, size, maxsize); if (*off >= nand_info[*idx].size) { puts("Offset exceeds device limit\n"); @@ -184,36 +187,35 @@ static int arg_off(const char *arg, int *idx, loff_t *off, loff_t *maxsize) } *maxsize = nand_info[*idx].size - *off; + *size = *maxsize; return 0; } static int arg_off_size(int argc, char *const argv[], int *idx, - loff_t *off, loff_t *size) + loff_t *off, loff_t *size, loff_t *maxsize) { int ret; - loff_t maxsize = 0; if (argc == 0) { *off = 0; *size = nand_info[*idx].size; + *maxsize = *size; goto print; } - ret = arg_off(argv[0], idx, off, &maxsize); + ret = arg_off(argv[0], idx, off, size, maxsize); if (ret) return ret; - if (argc == 1) { - *size = maxsize; + if (argc == 1) goto print; - } if (!str2off(argv[1], size)) { printf("'%s' is not a number\n", argv[1]); return -1; } - if (*size > maxsize) { + if (*size > *maxsize) { puts("Size exceeds partition or device limit\n"); return -1; } @@ -307,7 +309,8 @@ int do_nand_env_oob(cmd_tbl_t *cmdtp, int argc, char *const argv[]) if (argc < 3) goto usage; - if (arg_off(argv[2], &idx, &addr, &maxsize)) { + /* We don't care about size, or maxsize. */ + if (arg_off(argv[2], &idx, &addr, &maxsize, &maxsize)) { puts("Offset or partition name expected\n"); return 1; } @@ -426,7 +429,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i, ret = 0; ulong addr; - loff_t off, size; + loff_t off, size, maxsize; char *cmd, *s; nand_info_t *nand; #ifdef CONFIG_SYS_NAND_QUIET @@ -551,7 +554,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("\nNAND %s: ", cmd); /* skip first two or three arguments, look for offset and size */ - if (arg_off_size(argc - o, argv + o, &dev, &off, &size) != 0) + if (arg_off_size(argc - o, argv + o, &dev, &off, &size, + &maxsize) != 0) return 1; nand = &nand_info[dev]; @@ -619,7 +623,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (s && !strcmp(s, ".raw")) { raw = 1; - if (arg_off(argv[3], &dev, &off, &size)) + if (arg_off(argv[3], &dev, &off, &size, &maxsize)) return 1; if (argc > 4 && !str2long(argv[4], &pagecount)) { @@ -635,7 +639,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) rwsize = pagecount * (nand->writesize + nand->oobsize); } else { if (arg_off_size(argc - 3, argv + 3, &dev, - &off, &size) != 0) + &off, &size, &maxsize) != 0) return 1; rwsize = size; @@ -645,9 +649,11 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) !strcmp(s, ".e") || !strcmp(s, ".i")) { if (read) ret = nand_read_skip_bad(nand, off, &rwsize, + NULL, maxsize, (u_char *)addr); else ret = nand_write_skip_bad(nand, off, &rwsize, + NULL, maxsize, (u_char *)addr, 0); #ifdef CONFIG_CMD_NAND_TRIMFFS } else if (!strcmp(s, ".trimffs")) { @@ -655,8 +661,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("Unknown nand command suffix '%s'\n", s); return 1; } - ret = nand_write_skip_bad(nand, off, &rwsize, - (u_char *)addr, + ret = nand_write_skip_bad(nand, off, &rwsize, NULL, + maxsize, (u_char *)addr, WITH_DROP_FFS); #endif #ifdef CONFIG_CMD_NAND_YAFFS @@ -665,9 +671,9 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("Unknown nand command suffix '%s'.\n", s); return 1; } - ret = nand_write_skip_bad(nand, off, &rwsize, - (u_char *)addr, - WITH_INLINE_OOB); + ret = nand_write_skip_bad(nand, off, &rwsize, NULL, + maxsize, (u_char *)addr, + WITH_YAFFS_OOB); #endif } else if (!strcmp(s, ".oob")) { /* out-of-band data */ @@ -775,7 +781,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (s && !strcmp(s, ".allexcept")) allexcept = 1; - if (arg_off_size(argc - 2, argv + 2, &dev, &off, &size) < 0) + if (arg_off_size(argc - 2, argv + 2, &dev, &off, &size, + &maxsize) < 0) return 1; if (!nand_unlock(&nand_info[dev], off, size, allexcept)) { @@ -873,7 +880,8 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, printf("\nLoading from %s, offset 0x%lx\n", nand->name, offset); cnt = nand->writesize; - r = nand_read_skip_bad(nand, offset, &cnt, (u_char *) addr); + r = nand_read_skip_bad(nand, offset, &cnt, NULL, nand->size, + (u_char *)addr); if (r) { puts("** Read error\n"); bootstage_error(BOOTSTAGE_ID_NAND_HDR_READ); @@ -905,7 +913,8 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, } bootstage_mark(BOOTSTAGE_ID_NAND_TYPE); - r = nand_read_skip_bad(nand, offset, &cnt, (u_char *) addr); + r = nand_read_skip_bad(nand, offset, &cnt, NULL, nand->size, + (u_char *)addr); if (r) { puts("** Read error\n"); bootstage_error(BOOTSTAGE_ID_NAND_READ); diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 3a05e60..afa128e 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -62,9 +62,10 @@ DECLARE_GLOBAL_DATA_PTR; !defined(CONFIG_ENV_IS_IN_ONENAND) && \ !defined(CONFIG_ENV_IS_IN_SPI_FLASH) && \ !defined(CONFIG_ENV_IS_IN_REMOTE) && \ + !defined(CONFIG_ENV_IS_IN_UBI) && \ !defined(CONFIG_ENV_IS_NOWHERE) # error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\ -SPI_FLASH|NVRAM|MMC|FAT|REMOTE} or CONFIG_ENV_IS_NOWHERE +SPI_FLASH|NVRAM|MMC|FAT|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE #endif /* @@ -273,6 +274,10 @@ int setenv(const char *varname, const char *varvalue) { const char * const argv[4] = { "setenv", varname, varvalue, NULL }; + /* before import into hashtable */ + if (!(gd->flags & GD_FLG_ENV_READY)) + return 1; + if (varvalue == NULL || varvalue[0] == '\0') return _do_env_set(0, 2, (char * const *)argv); else @@ -325,41 +330,50 @@ static int do_env_set(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int do_env_ask(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char message[CONFIG_SYS_CBSIZE]; - int size = CONFIG_SYS_CBSIZE - 1; - int i, len, pos; + int i, len, pos, size; char *local_args[4]; + char *endptr; local_args[0] = argv[0]; local_args[1] = argv[1]; local_args[2] = NULL; local_args[3] = NULL; - /* Check the syntax */ - switch (argc) { - case 1: + /* + * Check the syntax: + * + * env_ask envname [message1 ...] [size] + */ + if (argc == 1) return CMD_RET_USAGE; - case 2: /* env_ask envname */ - sprintf(message, "Please enter '%s':", argv[1]); - break; - - case 3: /* env_ask envname size */ - sprintf(message, "Please enter '%s':", argv[1]); - size = simple_strtoul(argv[2], NULL, 10); - break; + /* + * We test the last argument if it can be converted + * into a decimal number. If yes, we assume it's + * the size. Otherwise we echo it as part of the + * message. + */ + i = simple_strtoul(argv[argc - 1], &endptr, 10); + if (*endptr != '\0') { /* no size */ + size = CONFIG_SYS_CBSIZE - 1; + } else { /* size given */ + size = i; + --argc; + } - default: /* env_ask envname message1 ... messagen size */ - for (i = 2, pos = 0; i < argc - 1; i++) { + if (argc <= 2) { + sprintf(message, "Please enter '%s': ", argv[1]); + } else { + /* env_ask envname message1 ... messagen [size] */ + for (i = 2, pos = 0; i < argc; i++) { if (pos) message[pos++] = ' '; strcpy(message + pos, argv[i]); pos += strlen(argv[i]); } - + message[pos++] = ' '; message[pos] = '\0'; - size = simple_strtoul(argv[argc - 1], NULL, 10); - break; } if (size >= CONFIG_SYS_CBSIZE) @@ -1168,14 +1182,7 @@ U_BOOT_CMD( askenv, CONFIG_SYS_MAXARGS, 1, do_env_ask, "get environment variables from stdin", "name [message] [size]\n" - " - get environment variable 'name' from stdin (max 'size' chars)\n" - "askenv name\n" - " - get environment variable 'name' from stdin\n" - "askenv name size\n" - " - get environment variable 'name' from stdin (max 'size' chars)\n" - "askenv name [message] size\n" - " - display 'message' string and get environment variable 'name'" - "from stdin (max 'size' chars)" + " - get environment variable 'name' from stdin (max 'size' chars)" ); #endif diff --git a/common/cmd_part.c b/common/cmd_part.c index d997597..b79f074 100644 --- a/common/cmd_part.c +++ b/common/cmd_part.c @@ -96,7 +96,7 @@ int do_part(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( part, 5, 1, do_part, "disk partition related commands", - "part uuid <interface> <dev>:<part>\n" + "uuid <interface> <dev>:<part>\n" " - print partition UUID\n" "part uuid <interface> <dev>:<part> <varname>\n" " - set environment variable to partition UUID\n" diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c index ee75db9..2dbd49c 100644 --- a/common/cmd_pxe.c +++ b/common/cmd_pxe.c @@ -1280,7 +1280,8 @@ static struct menu *pxe_menu_to_menu(struct pxe_menu *cfg) /* * Create a menu and add items for all the labels. */ - m = menu_create(cfg->title, cfg->timeout, cfg->prompt, label_print); + m = menu_create(cfg->title, cfg->timeout, cfg->prompt, label_print, + NULL, NULL); if (!m) return NULL; diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c index 266bfa6..13b3d99 100644 --- a/common/cmd_scsi.c +++ b/common/cmd_scsi.c @@ -110,7 +110,7 @@ void scsi_scan(int mode) scsi_dev_desc[i].vendor[0]=0; scsi_dev_desc[i].product[0]=0; scsi_dev_desc[i].revision[0]=0; - scsi_dev_desc[i].removable=FALSE; + scsi_dev_desc[i].removable = false; scsi_dev_desc[i].if_type=IF_TYPE_SCSI; scsi_dev_desc[i].dev=i; scsi_dev_desc[i].part_type=PART_TYPE_UNKNOWN; @@ -125,7 +125,7 @@ void scsi_scan(int mode) pccb->pdata=(unsigned char *)&tempbuff; pccb->datalen=512; scsi_setup_inquiry(pccb); - if(scsi_exec(pccb)!=TRUE) { + if (scsi_exec(pccb) != true) { if(pccb->contr_stat==SCSI_SEL_TIME_OUT) { debug ("Selection timeout ID %d\n",pccb->target); continue; /* selection timeout => assuming no device present */ @@ -139,7 +139,7 @@ void scsi_scan(int mode) continue; /* skip unknown devices */ } if((modi&0x80)==0x80) /* drive is removable */ - scsi_dev_desc[scsi_max_devs].removable=TRUE; + scsi_dev_desc[scsi_max_devs].removable=true; /* get info for this device */ scsi_ident_cpy((unsigned char *)&scsi_dev_desc[scsi_max_devs].vendor[0], &tempbuff[8], 8); @@ -152,8 +152,8 @@ void scsi_scan(int mode) pccb->datalen=0; scsi_setup_test_unit_ready(pccb); - if(scsi_exec(pccb)!=TRUE) { - if(scsi_dev_desc[scsi_max_devs].removable==TRUE) { + if (scsi_exec(pccb) != true) { + if (scsi_dev_desc[scsi_max_devs].removable == true) { scsi_dev_desc[scsi_max_devs].type=perq; goto removable; } @@ -404,7 +404,7 @@ static ulong scsi_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer) debug("scsi_read_ext: startblk " LBAF ", blccnt %x buffer %lx\n", start, smallblks, buf_addr); - if(scsi_exec(pccb)!=TRUE) { + if (scsi_exec(pccb) != true) { scsi_print_error(pccb); blkcnt-=blks; break; @@ -458,7 +458,7 @@ static ulong scsi_write(int device, ulong blknr, } debug("%s: startblk " LBAF ", blccnt %x buffer %lx\n", __func__, start, smallblks, buf_addr); - if (scsi_exec(pccb) != TRUE) { + if (scsi_exec(pccb) != true) { scsi_print_error(pccb); blkcnt -= blks; break; @@ -521,7 +521,7 @@ int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz) pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */ pccb->datalen = 8; - if (scsi_exec(pccb) != TRUE) + if (scsi_exec(pccb) != true) return 1; *capacity = ((lbaint_t)pccb->pdata[0] << 24) | @@ -547,7 +547,7 @@ int scsi_read_capacity(ccb *pccb, lbaint_t *capacity, unsigned long *blksz) pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */ pccb->datalen = 16; - if (scsi_exec(pccb) != TRUE) + if (scsi_exec(pccb) != true) return 1; *capacity = ((uint64_t)pccb->pdata[0] << 56) | diff --git a/common/cmd_sf.c b/common/cmd_sf.c index b175358..0a17782 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -5,8 +5,8 @@ * Licensed under the GPL-2 or later. */ -#include <div64.h> #include <common.h> +#include <div64.h> #include <malloc.h> #include <spi_flash.h> @@ -369,8 +369,8 @@ static void spi_test_next_stage(struct test_info *test) * @param vbuf Verification buffer * @return 0 if ok, -1 on error */ -static int spi_flash_test(struct spi_flash *flash, char *buf, ulong len, - ulong offset, char *vbuf) +static int spi_flash_test(struct spi_flash *flash, uint8_t *buf, ulong len, + ulong offset, uint8_t *vbuf) { struct test_info test; int i; @@ -431,9 +431,9 @@ static int do_spi_flash_test(int argc, char * const argv[]) { unsigned long offset; unsigned long len; - char *buf = (char *)CONFIG_SYS_TEXT_BASE; + uint8_t *buf = (uint8_t *)CONFIG_SYS_TEXT_BASE; char *endp; - char *vbuf; + uint8_t *vbuf; int ret; offset = simple_strtoul(argv[1], &endp, 16); diff --git a/common/cmd_test.c b/common/cmd_test.c index d4ec186..acc0ecf 100644 --- a/common/cmd_test.c +++ b/common/cmd_test.c @@ -21,6 +21,15 @@ * MA 02111-1307 USA */ +/* + * Define _STDBOOL_H here to avoid macro expansion of true and false. + * If the future code requires macro true or false, remove this define + * and undef true and false before U_BOOT_CMD. This define and comment + * shall be removed if change to U_BOOT_CMD is made to take string + * instead of stringifying it. + */ +#define _STDBOOL_H + #include <common.h> #include <command.h> diff --git a/common/cmd_ubi.c b/common/cmd_ubi.c index 35b1d31..5ba4feb 100644 --- a/common/cmd_ubi.c +++ b/common/cmd_ubi.c @@ -23,6 +23,9 @@ #include <asm/errno.h> #include <jffs2/load_kernel.h> +#undef ubi_msg +#define ubi_msg(fmt, ...) printf("UBI: " fmt "\n", ##__VA_ARGS__) + #define DEV_TYPE_NONE 0 #define DEV_TYPE_NAND 1 #define DEV_TYPE_ONENAND 2 @@ -263,7 +266,7 @@ out_err: return err; } -static int ubi_volume_write(char *volume, void *buf, size_t size) +int ubi_volume_write(char *volume, void *buf, size_t size) { int err = 1; int rsvd_bytes = 0; @@ -308,12 +311,10 @@ static int ubi_volume_write(char *volume, void *buf, size_t size) ubi_gluebi_updated(vol); } - printf("%d bytes written to volume %s\n", size, volume); - return 0; } -static int ubi_volume_read(char *volume, char *buf, size_t size) +int ubi_volume_read(char *volume, char *buf, size_t size) { int err, lnum, off, len, tbuf_size; void *tbuf; @@ -325,8 +326,6 @@ static int ubi_volume_read(char *volume, char *buf, size_t size) if (vol == NULL) return ENODEV; - printf("Read %d bytes from volume %s to %p\n", size, volume, buf); - if (vol->updating) { printf("updating"); return EBUSY; @@ -431,26 +430,82 @@ static int ubi_dev_scan(struct mtd_info *info, char *ubidev, return 0; } -static int do_ubi(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +int ubi_part(char *part_name, const char *vid_header_offset) { - size_t size = 0; - ulong addr = 0; int err = 0; - - if (argc < 2) - return CMD_RET_USAGE; + char mtd_dev[16]; + struct mtd_device *dev; + struct part_info *part; + u8 pnum; if (mtdparts_init() != 0) { printf("Error initializing mtdparts!\n"); return 1; } +#ifdef CONFIG_CMD_UBIFS + /* + * Automatically unmount UBIFS partition when user + * changes the UBI device. Otherwise the following + * UBIFS commands will crash. + */ + if (ubifs_is_mounted()) + cmd_ubifs_umount(); +#endif + + /* todo: get dev number for NAND... */ + ubi_dev.nr = 0; + + /* + * Call ubi_exit() before re-initializing the UBI subsystem + */ + if (ubi_initialized) { + ubi_exit(); + del_mtd_partitions(ubi_dev.mtd_info); + } + + /* + * Search the mtd device number where this partition + * is located + */ + if (find_dev_and_part(part_name, &dev, &pnum, &part)) { + printf("Partition %s not found!\n", part_name); + return 1; + } + sprintf(mtd_dev, "%s%d", MTD_DEV_TYPE(dev->id->type), dev->id->num); + ubi_dev.mtd_info = get_mtd_device_nm(mtd_dev); + if (IS_ERR(ubi_dev.mtd_info)) { + printf("Partition %s not found on device %s!\n", part_name, + mtd_dev); + return 1; + } + + ubi_dev.selected = 1; + + strcpy(ubi_dev.part_name, part_name); + err = ubi_dev_scan(ubi_dev.mtd_info, ubi_dev.part_name, + vid_header_offset); + if (err) { + printf("UBI init error %d\n", err); + ubi_dev.selected = 0; + return err; + } + + ubi = ubi_devices[0]; + + return 0; +} + +static int do_ubi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + size_t size = 0; + ulong addr = 0; + + if (argc < 2) + return CMD_RET_USAGE; + if (strcmp(argv[1], "part") == 0) { - char mtd_dev[16]; - struct mtd_device *dev; - struct part_info *part; const char *vid_header_offset = NULL; - u8 pnum; /* Print current partition */ if (argc == 2) { @@ -467,58 +522,10 @@ static int do_ubi(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) if (argc < 3) return CMD_RET_USAGE; -#ifdef CONFIG_CMD_UBIFS - /* - * Automatically unmount UBIFS partition when user - * changes the UBI device. Otherwise the following - * UBIFS commands will crash. - */ - if (ubifs_is_mounted()) - cmd_ubifs_umount(); -#endif - - /* todo: get dev number for NAND... */ - ubi_dev.nr = 0; - - /* - * Call ubi_exit() before re-initializing the UBI subsystem - */ - if (ubi_initialized) { - ubi_exit(); - del_mtd_partitions(ubi_dev.mtd_info); - } - - /* - * Search the mtd device number where this partition - * is located - */ - if (find_dev_and_part(argv[2], &dev, &pnum, &part)) { - printf("Partition %s not found!\n", argv[2]); - return 1; - } - sprintf(mtd_dev, "%s%d", MTD_DEV_TYPE(dev->id->type), dev->id->num); - ubi_dev.mtd_info = get_mtd_device_nm(mtd_dev); - if (IS_ERR(ubi_dev.mtd_info)) { - printf("Partition %s not found on device %s!\n", argv[2], mtd_dev); - return 1; - } - - ubi_dev.selected = 1; - if (argc > 3) vid_header_offset = argv[3]; - strcpy(ubi_dev.part_name, argv[2]); - err = ubi_dev_scan(ubi_dev.mtd_info, ubi_dev.part_name, - vid_header_offset); - if (err) { - printf("UBI init error %d\n", err); - ubi_dev.selected = 0; - return err; - } - - ubi = ubi_devices[0]; - return 0; + return ubi_part(argv[2], vid_header_offset); } if ((strcmp(argv[1], "part") != 0) && (!ubi_dev.selected)) { @@ -571,6 +578,8 @@ static int do_ubi(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) } if (strncmp(argv[1], "write", 5) == 0) { + int ret; + if (argc < 5) { printf("Please see usage\n"); return 1; @@ -579,7 +588,13 @@ static int do_ubi(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) addr = simple_strtoul(argv[2], NULL, 16); size = simple_strtoul(argv[4], NULL, 16); - return ubi_volume_write(argv[3], (void *)addr, size); + ret = ubi_volume_write(argv[3], (void *)addr, size); + if (!ret) { + printf("%d bytes written to volume %s\n", size, + argv[3]); + } + + return ret; } if (strncmp(argv[1], "read", 4) == 0) { @@ -597,8 +612,12 @@ static int do_ubi(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) argc--; } - if (argc == 3) + if (argc == 3) { + printf("Read %d bytes from volume %s to %lx\n", size, + argv[3], addr); + return ubi_volume_read(argv[3], (char *)addr, size); + } } printf("Please see usage\n"); diff --git a/common/cmd_usb_mass_storage.c b/common/cmd_usb_mass_storage.c new file mode 100644 index 0000000..87a5f2f --- /dev/null +++ b/common/cmd_usb_mass_storage.c @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * Lukasz Majewski <l.majewski@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <errno.h> +#include <common.h> +#include <command.h> +#include <g_dnl.h> +#include <usb_mass_storage.h> + +int do_usb_mass_storage(cmd_tbl_t *cmdtp, int flag, + int argc, char * const argv[]) +{ + char *ep; + unsigned int dev_num = 0, offset = 0, part_size = 0; + int rc; + + struct ums_board_info *ums_info; + static char *s = "ums"; + + if (argc < 2) { + printf("usage: ums <dev> - e.g. ums 0\n"); + return 0; + } + + dev_num = (int)simple_strtoul(argv[1], &ep, 16); + + if (dev_num) { + puts("\nSet eMMC device to 0! - e.g. ums 0\n"); + goto fail; + } + + board_usb_init(); + ums_info = board_ums_init(dev_num, offset, part_size); + + if (!ums_info) { + printf("MMC: %d -> NOT available\n", dev_num); + goto fail; + } + rc = fsg_init(ums_info); + if (rc) { + printf("cmd ums: fsg_init failed\n"); + goto fail; + } + + g_dnl_register(s); + + while (1) { + /* Handle control-c and timeouts */ + if (ctrlc()) { + printf("The remote end did not respond in time.\n"); + goto exit; + } + usb_gadget_handle_interrupts(); + /* Check if USB cable has been detached */ + if (fsg_main_thread(NULL) == EIO) + goto exit; + } +exit: + g_dnl_unregister(); + return 0; + +fail: + return -1; +} + +U_BOOT_CMD(ums, CONFIG_SYS_MAXARGS, 1, do_usb_mass_storage, + "Use the UMS [User Mass Storage]", + "ums - User Mass Storage Gadget" +); diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 2a9d169..3c70d5d 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -201,7 +201,7 @@ MORECORE_FAILURE (default: -1) The value returned upon failure of MORECORE. MORECORE_CLEARS (default 1) - True (1) if the routine mapped to MORECORE zeroes out memory (which + true (1) if the routine mapped to MORECORE zeroes out memory (which holds for sbrk). DEFAULT_TRIM_THRESHOLD DEFAULT_TOP_PAD diff --git a/common/dlmalloc.src b/common/dlmalloc.src index 32a38bc..d86acff 100644 --- a/common/dlmalloc.src +++ b/common/dlmalloc.src @@ -198,7 +198,7 @@ MORECORE_FAILURE (default: -1) The value returned upon failure of MORECORE. MORECORE_CLEARS (default 1) - True (1) if the routine mapped to MORECORE zeroes out memory (which + true (1) if the routine mapped to MORECORE zeroes out memory (which holds for sbrk). DEFAULT_TRIM_THRESHOLD DEFAULT_TOP_PAD diff --git a/common/env_callback.c b/common/env_callback.c index 78ca367..78aafb4 100644 --- a/common/env_callback.c +++ b/common/env_callback.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; /* * Look up a callback function pointer by name */ -struct env_clbk_tbl *find_env_callback(const char *name) +static struct env_clbk_tbl *find_env_callback(const char *name) { struct env_clbk_tbl *clbkp; int i; diff --git a/common/env_nand.c b/common/env_nand.c index 5b69889..b745822 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -281,7 +281,8 @@ int readenv(size_t offset, u_char *buf) } else { char_ptr = &buf[amount_loaded]; if (nand_read_skip_bad(&nand_info[0], offset, - &len, char_ptr)) + &len, NULL, + nand_info[0].size, char_ptr)) return 1; offset += blocksize; diff --git a/common/env_ubi.c b/common/env_ubi.c new file mode 100644 index 0000000..1ed8b02 --- /dev/null +++ b/common/env_ubi.c @@ -0,0 +1,220 @@ +/* + * (c) Copyright 2012 by National Instruments, + * Joe Hershberger <joe.hershberger@ni.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <command.h> +#include <environment.h> +#include <errno.h> +#include <malloc.h> +#include <search.h> +#include <ubi_uboot.h> +#undef crc32 + +char *env_name_spec = "UBI"; + +env_t *env_ptr; + +DECLARE_GLOBAL_DATA_PTR; + +int env_init(void) +{ + /* use default */ + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 1; + + return 0; +} + +#ifdef CONFIG_CMD_SAVEENV +#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT +static unsigned char env_flags; + +int saveenv(void) +{ + ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1); + ssize_t len; + char *res; + + res = (char *)&env_new->data; + len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + return 1; + } + + if (ubi_part(CONFIG_ENV_UBI_PART, NULL)) { + printf("\n** Cannot find mtd partition \"%s\"\n", + CONFIG_ENV_UBI_PART); + return 1; + } + + env_new->crc = crc32(0, env_new->data, ENV_SIZE); + env_new->flags = ++env_flags; /* increase the serial */ + + if (gd->env_valid == 1) { + puts("Writing to redundant UBI... "); + if (ubi_volume_write(CONFIG_ENV_UBI_VOLUME_REDUND, + (void *)env_new, CONFIG_ENV_SIZE)) { + printf("\n** Unable to write env to %s:%s **\n", + CONFIG_ENV_UBI_PART, + CONFIG_ENV_UBI_VOLUME_REDUND); + return 1; + } + } else { + puts("Writing to UBI... "); + if (ubi_volume_write(CONFIG_ENV_UBI_VOLUME, + (void *)env_new, CONFIG_ENV_SIZE)) { + printf("\n** Unable to write env to %s:%s **\n", + CONFIG_ENV_UBI_PART, + CONFIG_ENV_UBI_VOLUME); + return 1; + } + } + + puts("done\n"); + + gd->env_valid = gd->env_valid == 2 ? 1 : 2; + + return 0; +} +#else /* ! CONFIG_SYS_REDUNDAND_ENVIRONMENT */ +int saveenv(void) +{ + ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1); + ssize_t len; + char *res; + + res = (char *)&env_new->data; + len = hexport_r(&env_htab, '\0', 0, &res, ENV_SIZE, 0, NULL); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + return 1; + } + + if (ubi_part(CONFIG_ENV_UBI_PART, NULL)) { + printf("\n** Cannot find mtd partition \"%s\"\n", + CONFIG_ENV_UBI_PART); + return 1; + } + + env_new->crc = crc32(0, env_new->data, ENV_SIZE); + + if (ubi_volume_write(CONFIG_ENV_UBI_VOLUME, (void *)env_new, + CONFIG_ENV_SIZE)) { + printf("\n** Unable to write env to %s:%s **\n", + CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME); + return 1; + } + + puts("done\n"); + return 0; +} +#endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */ +#endif /* CONFIG_CMD_SAVEENV */ + +#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT +void env_relocate_spec(void) +{ + ALLOC_CACHE_ALIGN_BUFFER(char, env1_buf, CONFIG_ENV_SIZE); + ALLOC_CACHE_ALIGN_BUFFER(char, env2_buf, CONFIG_ENV_SIZE); + int crc1_ok = 0, crc2_ok = 0; + env_t *ep, *tmp_env1, *tmp_env2; + + tmp_env1 = (env_t *)env1_buf; + tmp_env2 = (env_t *)env2_buf; + + if (ubi_part(CONFIG_ENV_UBI_PART, NULL)) { + printf("\n** Cannot find mtd partition \"%s\"\n", + CONFIG_ENV_UBI_PART); + set_default_env(NULL); + return; + } + + if (ubi_volume_read(CONFIG_ENV_UBI_VOLUME, (void *)tmp_env1, + CONFIG_ENV_SIZE)) { + printf("\n** Unable to read env from %s:%s **\n", + CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME); + } + + if (ubi_volume_read(CONFIG_ENV_UBI_VOLUME_REDUND, (void *)tmp_env2, + CONFIG_ENV_SIZE)) { + printf("\n** Unable to read redundant env from %s:%s **\n", + CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME_REDUND); + } + + crc1_ok = crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc; + crc2_ok = crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc; + + if (!crc1_ok && !crc2_ok) { + set_default_env("!bad CRC"); + return; + } else if (crc1_ok && !crc2_ok) { + gd->env_valid = 1; + } else if (!crc1_ok && crc2_ok) { + gd->env_valid = 2; + } else { + /* both ok - check serial */ + if (tmp_env1->flags == 255 && tmp_env2->flags == 0) + gd->env_valid = 2; + else if (tmp_env2->flags == 255 && tmp_env1->flags == 0) + gd->env_valid = 1; + else if (tmp_env1->flags > tmp_env2->flags) + gd->env_valid = 1; + else if (tmp_env2->flags > tmp_env1->flags) + gd->env_valid = 2; + else /* flags are equal - almost impossible */ + gd->env_valid = 1; + } + + if (gd->env_valid == 1) + ep = tmp_env1; + else + ep = tmp_env2; + + env_flags = ep->flags; + env_import((char *)ep, 0); +} +#else /* ! CONFIG_SYS_REDUNDAND_ENVIRONMENT */ +void env_relocate_spec(void) +{ + ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE); + + if (ubi_part(CONFIG_ENV_UBI_PART, NULL)) { + printf("\n** Cannot find mtd partition \"%s\"\n", + CONFIG_ENV_UBI_PART); + set_default_env(NULL); + return; + } + + if (ubi_volume_read(CONFIG_ENV_UBI_VOLUME, (void *)&buf, + CONFIG_ENV_SIZE)) { + printf("\n** Unable to read env from %s:%s **\n", + CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME); + set_default_env(NULL); + return; + } + + env_import(buf, 1); +} +#endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */ diff --git a/common/hash.c b/common/hash.c index f5badcb..c9ac33e 100644 --- a/common/hash.c +++ b/common/hash.c @@ -25,6 +25,7 @@ #include <common.h> #include <command.h> +#include <hw_sha.h> #include <hash.h> #include <sha1.h> #include <sha256.h> @@ -37,6 +38,23 @@ */ static struct hash_algo hash_algo[] = { /* + * CONFIG_SHA_HW_ACCEL is defined if hardware acceleration is + * available. + */ +#ifdef CONFIG_SHA_HW_ACCEL + { + "sha1", + SHA1_SUM_LEN, + hw_sha1, + CHUNKSZ_SHA1, + }, { + "sha256", + SHA256_SUM_LEN, + hw_sha256, + CHUNKSZ_SHA256, + }, +#endif + /* * This is CONFIG_CMD_SHA1SUM instead of CONFIG_SHA1 since otherwise * it bloats the code for boards which use SHA1 but not the 'hash' * or 'sha1sum' commands. diff --git a/common/image.c b/common/image.c index 6afbb40..60c2127 100644 --- a/common/image.c +++ b/common/image.c @@ -108,6 +108,7 @@ static const table_entry_t uimage_os[] = { #endif { IH_OS_NETBSD, "netbsd", "NetBSD", }, { IH_OS_OSE, "ose", "Enea OSE", }, + { IH_OS_PLAN9, "plan9", "Plan 9", }, { IH_OS_RTEMS, "rtems", "RTEMS", }, { IH_OS_U_BOOT, "u-boot", "U-Boot", }, #if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC) diff --git a/common/lcd.c b/common/lcd.c index 590bbb9..edae835 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -83,9 +83,35 @@ #define CONFIG_CONSOLE_SCROLL_LINES 1 #endif -DECLARE_GLOBAL_DATA_PTR; +/************************************************************************/ +/* ** CONSOLE DEFINITIONS & FUNCTIONS */ +/************************************************************************/ +#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) +# define CONSOLE_ROWS ((panel_info.vl_row-BMP_LOGO_HEIGHT) \ + / VIDEO_FONT_HEIGHT) +#else +# define CONSOLE_ROWS (panel_info.vl_row / VIDEO_FONT_HEIGHT) +#endif + +#define CONSOLE_COLS (panel_info.vl_col / VIDEO_FONT_WIDTH) +#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length) +#define CONSOLE_ROW_FIRST lcd_console_address +#define CONSOLE_ROW_SECOND (lcd_console_address + CONSOLE_ROW_SIZE) +#define CONSOLE_ROW_LAST (lcd_console_address + CONSOLE_SIZE \ + - CONSOLE_ROW_SIZE) +#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) +#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) + +#if LCD_BPP == LCD_MONOCHROME +# define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \ + (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) +#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) +# define COLOR_MASK(c) (c) +#else +# error Unsupported LCD BPP. +#endif -ulong lcd_setmem (ulong addr); +DECLARE_GLOBAL_DATA_PTR; static void lcd_drawchars(ushort x, ushort y, uchar *str, int count); static inline void lcd_puts_xy(ushort x, ushort y, uchar *s); @@ -93,22 +119,25 @@ static inline void lcd_putc_xy(ushort x, ushort y, uchar c); static int lcd_init(void *lcdbase); -static void *lcd_logo (void); +static void *lcd_logo(void); static int lcd_getbgcolor(void); static void lcd_setfgcolor(int color); static void lcd_setbgcolor(int color); +static int lcd_color_fg; +static int lcd_color_bg; +int lcd_line_length; + char lcd_is_enabled = 0; -static char lcd_flush_dcache; /* 1 to flush dcache after each lcd update */ +static short console_col; +static short console_row; +static void *lcd_console_address; +static void *lcd_base; /* Start of framebuffer memory */ -#ifdef NOT_USED_SO_FAR -static void lcd_getcolreg(ushort regno, - ushort *red, ushort *green, ushort *blue); -static int lcd_getfgcolor(void); -#endif /* NOT_USED_SO_FAR */ +static char lcd_flush_dcache; /* 1 to flush dcache after each lcd update */ /************************************************************************/ @@ -148,7 +177,7 @@ static void console_scrollup(void) /* Clear the last rows */ memset(lcd_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE * rows, COLOR_MASK(lcd_color_bg), - CONSOLE_ROW_SIZE * rows); + CONSOLE_ROW_SIZE * rows); lcd_sync(); console_row -= rows; @@ -160,9 +189,8 @@ static inline void console_back(void) { if (--console_col < 0) { console_col = CONSOLE_COLS-1 ; - if (--console_row < 0) { + if (--console_row < 0) console_row = 0; - } } lcd_putc_xy(console_col * VIDEO_FONT_WIDTH, @@ -173,16 +201,13 @@ static inline void console_back(void) static inline void console_newline(void) { - ++console_row; console_col = 0; /* Check if we need to scroll the terminal */ - if (console_row >= CONSOLE_ROWS) { - /* Scroll everything up */ + if (++console_row >= CONSOLE_ROWS) console_scrollup(); - } else { + else lcd_sync(); - } } /*----------------------------------------------------------------------*/ @@ -234,9 +259,9 @@ void lcd_puts(const char *s) return; } - while (*s) { + while (*s) lcd_putc(*s++); - } + lcd_sync(); } @@ -283,7 +308,7 @@ static void lcd_drawchars(ushort x, ushort y, uchar *str, int count) #endif #if LCD_BPP == LCD_MONOCHROME - uchar rest = *d & -(1 << (8-off)); + uchar rest = *d & -(1 << (8 - off)); uchar sym; #endif for (i = 0; i < count; ++i) { @@ -313,7 +338,7 @@ static void lcd_drawchars(ushort x, ushort y, uchar *str, int count) #endif } #if LCD_BPP == LCD_MONOCHROME - *d = rest | (*d & ((1 << (8-off)) - 1)); + *d = rest | (*d & ((1 << (8 - off)) - 1)); #endif } } @@ -340,7 +365,7 @@ static inline void lcd_putc_xy(ushort x, ushort y, uchar c) #define N_BLK_VERT 2 #define N_BLK_HOR 3 -static int test_colors[N_BLK_HOR*N_BLK_VERT] = { +static int test_colors[N_BLK_HOR * N_BLK_VERT] = { CONSOLE_COLOR_RED, CONSOLE_COLOR_GREEN, CONSOLE_COLOR_YELLOW, CONSOLE_COLOR_BLUE, CONSOLE_COLOR_MAGENTA, CONSOLE_COLOR_CYAN, }; @@ -361,7 +386,7 @@ static void test_pattern(void) for (v = 0; v < v_max; ++v) { uchar iy = v / v_step; for (h = 0; h < h_max; ++h) { - uchar ix = N_BLK_HOR * iy + (h/h_step); + uchar ix = N_BLK_HOR * iy + h / h_step; *pix++ = test_colors[ix]; } } @@ -379,14 +404,12 @@ int lcd_get_size(int *line_length) return *line_length * panel_info.vl_row; } -int drv_lcd_init (void) +int drv_lcd_init(void) { struct stdio_dev lcddev; int rc; - lcd_base = (void *)(gd->fb_base); - - lcd_get_size(&lcd_line_length); + lcd_base = (void *) gd->fb_base; lcd_init(lcd_base); /* LCD initialization */ @@ -399,7 +422,7 @@ int drv_lcd_init (void) lcddev.putc = lcd_putc; /* 'putc' function */ lcddev.puts = lcd_puts; /* 'puts' function */ - rc = stdio_register (&lcddev); + rc = stdio_register(&lcddev); return (rc == 0) ? 1 : rc; } @@ -438,11 +461,11 @@ void lcd_clear(void) /* set framebuffer to background color */ memset((char *)lcd_base, COLOR_MASK(lcd_getbgcolor()), - lcd_line_length*panel_info.vl_row); + lcd_line_length * panel_info.vl_row); #endif /* Paint the logo and retrieve LCD base address */ debug("[LCD] Drawing the logo...\n"); - lcd_console_address = lcd_logo (); + lcd_console_address = lcd_logo(); console_col = 0; console_row = 0; @@ -470,9 +493,23 @@ static int lcd_init(void *lcdbase) debug("[LCD] Initializing LCD frambuffer at %p\n", lcdbase); lcd_ctrl_init(lcdbase); + + /* + * lcd_ctrl_init() of some drivers (i.e. bcm2835 on rpi_b) ignores + * the 'lcdbase' argument and uses custom lcd base address + * by setting up gd->fb_base. Check for this condition and fixup + * 'lcd_base' address. + */ + if ((unsigned long)lcdbase != gd->fb_base) + lcd_base = (void *)gd->fb_base; + + debug("[LCD] Using LCD frambuffer at %p\n", lcd_base); + + lcd_get_size(&lcd_line_length); + lcd_line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8; lcd_is_enabled = 1; lcd_clear(); - lcd_enable (); + lcd_enable(); /* Initialize the console */ console_col = 0; @@ -513,7 +550,8 @@ ulong lcd_setmem(ulong addr) /* Allocate pages for the frame buffer. */ addr -= size; - debug("Reserving %ldk for LCD Framebuffer at: %08lx\n", size>>10, addr); + debug("Reserving %ldk for LCD Framebuffer at: %08lx\n", + size >> 10, addr); return addr; } @@ -534,12 +572,10 @@ static void lcd_setbgcolor(int color) /*----------------------------------------------------------------------*/ -#ifdef NOT_USED_SO_FAR -static int lcd_getfgcolor(void) +int lcd_getfgcolor(void) { return lcd_color_fg; } -#endif /* NOT_USED_SO_FAR */ /*----------------------------------------------------------------------*/ @@ -548,8 +584,6 @@ static int lcd_getbgcolor(void) return lcd_color_bg; } -/*----------------------------------------------------------------------*/ - /************************************************************************/ /* ** Chipset depending Bitmap / Logo stuff... */ /************************************************************************/ @@ -566,13 +600,11 @@ static inline ushort *configuration_get_cmap(void) return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0)); #elif !defined(CONFIG_ATMEL_HLCD) && !defined(CONFIG_EXYNOS_FB) return panel_info.cmap; -#else -#if defined(CONFIG_LCD_LOGO) +#elif defined(CONFIG_LCD_LOGO) return bmp_logo_palette; #else return NULL; #endif -#endif } #ifdef CONFIG_LCD_LOGO @@ -591,15 +623,16 @@ void bitmap_plot(int x, int y) immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; cpm8xx_t *cp = &(immr->im_cpm); #endif + unsigned bpix = NBITS(panel_info.vl_bpix); debug("Logo: width %d height %d colors %d cmap %d\n", BMP_LOGO_WIDTH, BMP_LOGO_HEIGHT, BMP_LOGO_COLORS, ARRAY_SIZE(bmp_logo_palette)); bmap = &bmp_logo_bitmap[0]; - fb = (uchar *)(lcd_base + y * lcd_line_length + x); + fb = (uchar *)(lcd_base + y * lcd_line_length + x * bpix / 8); - if (NBITS(panel_info.vl_bpix) < 12) { + if (bpix < 12) { /* Leave room for default color map * default case: generic system with no cmap (most likely 16bpp) * cmap was set to the source palette, so no change is done. @@ -645,12 +678,12 @@ void bitmap_plot(int x, int y) for (i = 0; i < BMP_LOGO_HEIGHT; ++i) { memcpy(fb, bmap, BMP_LOGO_WIDTH); bmap += BMP_LOGO_WIDTH; - fb += panel_info.vl_col; + fb += panel_info.vl_col; } } else { /* true color mode */ u16 col16; - fb16 = (ushort *)(lcd_base + y * lcd_line_length + x); + fb16 = (ushort *)fb; for (i = 0; i < BMP_LOGO_HEIGHT; ++i) { for (j = 0; j < BMP_LOGO_WIDTH; j++) { col16 = bmp_logo_palette[(bmap[j]-16)]; @@ -736,12 +769,11 @@ static void draw_encoded_bitmap(ushort **fbp, ushort c, int cnt) *fb++ = c; cnt--; } - (*fbp) = fb; + *fbp = fb; } /* - * Do not call this function directly, must be called from - * lcd_display_bitmap. + * Do not call this function directly, must be called from lcd_display_bitmap. */ static void lcd_display_rle8_bitmap(bmp_image_t *bmp, ushort *cmap, uchar *fb, int x_off, int y_off) @@ -868,8 +900,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) unsigned long pwidth = panel_info.vl_col; unsigned colors, bpix, bmp_bpix; - if (!bmp || !((bmp->header.signature[0] == 'B') && - (bmp->header.signature[1] == 'M'))) { + if (!bmp || !(bmp->header.signature[0] == 'B' && + bmp->header.signature[1] == 'M')) { printf("Error: no valid bmp image at %lx\n", bmp_image); return 1; @@ -882,7 +914,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) bpix = NBITS(panel_info.vl_bpix); - if ((bpix != 1) && (bpix != 8) && (bpix != 16) && (bpix != 32)) { + if (bpix != 1 && bpix != 8 && bpix != 16 && bpix != 32) { printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n", bpix, bmp_bpix); @@ -950,7 +982,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) } #endif - padded_width = (width&0x3) ? ((width&~0x3)+4) : (width); + padded_width = (width & 0x3 ? (width & ~0x3) + 4 : width); #ifdef CONFIG_SPLASH_SCREEN_ALIGN splash_align_axis(&x, pwidth, width); @@ -962,7 +994,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) if ((y + height) > panel_info.vl_row) height = panel_info.vl_row - y; - bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset); + bmap = (uchar *) bmp + le32_to_cpu(bmp->header.data_offset); fb = (uchar *) (lcd_base + (y + height - 1) * lcd_line_length + x * bpix / 8); @@ -997,7 +1029,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) } } bmap += (padded_width - width); - fb -= (byte_width + lcd_line_length); + fb -= byte_width + lcd_line_length; } break; @@ -1009,7 +1041,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) fb_put_word(&fb, &bmap); bmap += (padded_width - width) * 2; - fb -= (width * 2 + lcd_line_length); + fb -= width * 2 + lcd_line_length; } break; #endif /* CONFIG_BMP_16BPP */ @@ -1023,7 +1055,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) *(fb++) = *(bmap++); *(fb++) = *(bmap++); } - fb -= (lcd_line_length + width * (bpix / 8)); + fb -= lcd_line_length + width * (bpix / 8); } break; #endif /* CONFIG_BMP_32BPP */ @@ -1098,7 +1130,7 @@ static void *lcd_logo(void) return (void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length); #else return (void *)lcd_base; -#endif /* CONFIG_LCD_LOGO && !CONFIG_LCD_INFO_BELOW_LOGO */ +#endif /* CONFIG_LCD_LOGO && !defined(CONFIG_LCD_INFO_BELOW_LOGO) */ } #ifdef CONFIG_SPLASHIMAGE_GUARD @@ -1150,6 +1182,3 @@ int lcd_get_screen_columns(void) { return CONSOLE_COLS; } - -/************************************************************************/ -/************************************************************************/ diff --git a/common/main.c b/common/main.c index e2d2e09..a15f020 100644 --- a/common/main.c +++ b/common/main.c @@ -95,7 +95,7 @@ extern void mdm_init(void); /* defined in board.c */ * Watch for 'delay' seconds for autoboot stop or autoboot delay string. * returns: 0 - no key string, allow autoboot 1 - got key string, abort */ -#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) +#if defined(CONFIG_BOOTDELAY) # if defined(CONFIG_AUTOBOOT_KEYED) #ifndef CONFIG_MENU static inline @@ -279,7 +279,7 @@ int abortboot(int bootdelay) return abort; } # endif /* CONFIG_AUTOBOOT_KEYED */ -#endif /* CONFIG_BOOTDELAY >= 0 */ +#endif /* CONFIG_BOOTDELAY */ /* * Runs the given boot command securely. Specifically: @@ -295,8 +295,7 @@ int abortboot(int bootdelay) * printing the error message to console. */ -#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) && \ - defined(CONFIG_OF_CONTROL) +#if defined(CONFIG_BOOTDELAY) && defined(CONFIG_OF_CONTROL) static void secure_boot_cmd(char *cmd) { cmd_tbl_t *cmdtp; @@ -358,11 +357,10 @@ void main_loop (void) int rc = 1; int flag; #endif -#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) && \ - defined(CONFIG_OF_CONTROL) +#if defined(CONFIG_BOOTDELAY) && defined(CONFIG_OF_CONTROL) char *env; #endif -#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) +#if defined(CONFIG_BOOTDELAY) char *s; int bootdelay; #endif @@ -378,6 +376,10 @@ void main_loop (void) bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop"); +#if defined CONFIG_OF_CONTROL + set_working_fdt_addr((void *)gd->fdt_blob); +#endif /* CONFIG_OF_CONTROL */ + #ifdef CONFIG_BOOTCOUNT_LIMIT bootcount = bootcount_load(); bootcount++; @@ -431,7 +433,7 @@ void main_loop (void) update_tftp (0UL); #endif /* CONFIG_UPDATE_TFTP */ -#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0) +#if defined(CONFIG_BOOTDELAY) s = getenv ("bootdelay"); bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY; @@ -500,10 +502,6 @@ void main_loop (void) #endif /* CONFIG_MENUKEY */ #endif /* CONFIG_BOOTDELAY */ -#if defined CONFIG_OF_CONTROL - set_working_fdt_addr((void *)gd->fdt_blob); -#endif /* CONFIG_OF_CONTROL */ - /* * Main Loop for Monitor Command Processing */ diff --git a/common/menu.c b/common/menu.c index 6b2a2db..64b461a 100644 --- a/common/menu.c +++ b/common/menu.c @@ -47,6 +47,8 @@ struct menu { char *title; int prompt; void (*item_data_print)(void *); + char *(*item_choice)(void *); + void *item_choice_data; struct list_head items; }; @@ -174,7 +176,7 @@ static inline struct menu_item *menu_item_by_key(struct menu *m, * Set *choice to point to the default item's data, if any default item was * set, and returns 1. If no default item was set, returns -ENOENT. */ -static inline int menu_default_choice(struct menu *m, void **choice) +int menu_default_choice(struct menu *m, void **choice) { if (m->default_item) { *choice = m->default_item->data; @@ -204,18 +206,26 @@ static inline int menu_interactive_choice(struct menu *m, void **choice) menu_display(m); - readret = readline_into_buffer("Enter choice: ", cbuf, - m->timeout / 10); + if (!m->item_choice) { + readret = readline_into_buffer("Enter choice: ", cbuf, + m->timeout / 10); - if (readret >= 0) { - choice_item = menu_item_by_key(m, cbuf); - - if (!choice_item) { - printf("%s not found\n", cbuf); - m->timeout = 0; + if (readret >= 0) { + choice_item = menu_item_by_key(m, cbuf); + if (!choice_item) + printf("%s not found\n", cbuf); + } else { + return menu_default_choice(m, choice); } - } else - return menu_default_choice(m, choice); + } else { + char *key = m->item_choice(m->item_choice_data); + + if (key) + choice_item = menu_item_by_key(m, key); + } + + if (!choice_item) + m->timeout = 0; } *choice = choice_item->data; @@ -348,11 +358,19 @@ int menu_item_add(struct menu *m, char *item_key, void *item_data) * what must be entered to select an item, the item_data_print function should * make it obvious what the key for each entry is. * + * item_choice - If not NULL, will be called when asking the user to choose an + * item. Returns a key string corresponding to the choosen item or NULL if + * no item has been selected. + * + * item_choice_data - Will be passed as the argument to the item_choice function + * * Returns a pointer to the menu if successful, or NULL if there is * insufficient memory available to create the menu. */ struct menu *menu_create(char *title, int timeout, int prompt, - void (*item_data_print)(void *)) + void (*item_data_print)(void *), + char *(*item_choice)(void *), + void *item_choice_data) { struct menu *m; @@ -365,6 +383,8 @@ struct menu *menu_create(char *title, int timeout, int prompt, m->prompt = prompt; m->timeout = timeout; m->item_data_print = item_data_print; + m->item_choice = item_choice; + m->item_choice_data = item_choice_data; if (title) { m->title = strdup(title); @@ -23,6 +23,13 @@ ######################################################################### +# Set shell to bash if possible, otherwise fall back to sh +SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \ + else if [ -x /bin/bash ]; then echo /bin/bash; \ + else echo sh; fi; fi) + +export SHELL + ifeq ($(CURDIR),$(SRCTREE)) dir := else @@ -219,6 +226,14 @@ ifeq ($(CONFIG_SPL_BUILD),y) CPPFLAGS += -DCONFIG_SPL_BUILD endif +# Does this architecture support generic board init? +ifeq ($(__HAVE_ARCH_GENERIC_BOARD),) +ifneq ($(CONFIG_SYS_GENERIC_BOARD),) +$(error Your architecture does not support generic board. Please undefined \ +CONFIG_SYS_GENERIC_BOARD in your board config file) +endif +endif + ifneq ($(RESET_VECTOR_ADDRESS),) CPPFLAGS += -DRESET_VECTOR_ADDRESS=$(RESET_VECTOR_ADDRESS) endif diff --git a/disk/part_efi.c b/disk/part_efi.c index b3fd0e9..e9987f0 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -30,6 +30,7 @@ * * This limits the maximum size of addressable storage to < 2 Terra Bytes */ +#include <asm/unaligned.h> #include <common.h> #include <command.h> #include <ide.h> @@ -505,7 +506,7 @@ err: static int pmbr_part_valid(struct partition *part) { if (part->sys_ind == EFI_PMBR_OSTYPE_EFI_GPT && - le32_to_cpu(part->start_sect) == 1UL) { + get_unaligned_le32(&part->start_sect) == 1UL) { return 1; } diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation index 5a9a2fb..645b374 100644 --- a/doc/README.arm-relocation +++ b/doc/README.arm-relocation @@ -40,15 +40,15 @@ Boards which are not fixed to support relocation will be REMOVED! ----------------------------------------------------------------------------- -For boards which boot from nand_spl, it is possible to save one copy +For boards which boot from spl, it is possible to save one copy if CONFIG_SYS_TEXT_BASE == relocation address! This prevents that uboot code is copied again in relocate_code(). -example for the tx25 board: +example for the tx25 board booting from NAND Flash: a) cpu starts b) it copies the first page in nand to internal ram - (nand_spl_code) + (spl code) c) end executes this code d) this initialize CPU, RAM, ... and copy itself to RAM (this bin must fit in one page, so board_init_f() @@ -79,20 +79,20 @@ TODO ----------------------------------------------------------------------------- -Relocation with NAND_SPL (example for the tx25): +Relocation with SPL (example for the tx25 booting from NAND Flash): - cpu copies the first page from NAND to 0xbb000000 (IMX_NFC_BASE) and start with code execution on this address. -- The First page contains u-boot code from u-boot:nand_spl/nand_boot_fsl_nfc.c - which inits the dram, cpu registers, reloacte itself to CONFIG_SYS_TEXT_BASE and loads +- The First page contains u-boot code from drivers/mtd/nand/mxc_nand_spl.c + which inits the dram, cpu registers, reloacte itself to CONFIG_SPL_TEXT_BASE and loads the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution @CONFIG_SYS_NAND_U_BOOT_START - This u-boot does no RAM init, nor CPU register setup. Just look where it has to copy and relocate itself to this address. If relocate address = CONFIG_SYS_TEXT_BASE (not the same, as the - CONFIG_SYS_TEXT_BASE from the nand_spl code), then there is no need + CONFIG_SPL_TEXT_BASE from the spl code), then there is no need to copy, just go on with bss clear and jump to board_init_r. ----------------------------------------------------------------------------- diff --git a/doc/README.bootmenu b/doc/README.bootmenu new file mode 100644 index 0000000..9e85b40 --- /dev/null +++ b/doc/README.bootmenu @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2011-2012 Pali Rohár <pali.rohar@gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +ANSI terminal bootmenu command + +The "bootmenu" command uses U-Boot menu interfaces and provides +a simple mechanism for creating menus with different boot items. +The cursor keys "Up" and "Down" are used for navigation through +the items. Current active menu item is highlighted and can be +selected using the "Enter" key. The selection of the highlighted +menu entry invokes an U-Boot command (or a list of commands) +associated with this menu entry. + +The "bootmenu" command interprets ANSI escape sequencies, so +an ANSI terminal is required for proper menu rendering and item +selection. + +The assembling of the menu is done via a set of environment variables +"bootmenu_<num>" and "bootmenu_delay", i.e.: + + bootmenu_delay=<delay> + bootmenu_<num>="<title>=<commands>" + + <delay> is the autoboot delay in seconds, after which the first + menu entry will be selected automatically + + <num> is the boot menu entry number, starting from zero + + <title> is the text of the menu entry shown on the console + or on the boot screen + + <commands> are commands which will be executed when a menu + entry is selected + + (title and commands are separated by first appearance of '=' + character in the environment variable) + +First (optional) argument of the "bootmenu" command is a delay specifier +and it overrides the delay value defined by "bootmenu_delay" environment +variable. If the environment variable "bootmenu_delay" is not set or if +the argument of the "bootmenu" command is not specified, the default delay +will be CONFIG_BOOTDELAY. If delay is 0, no menu entries will be shown on +the console (or on the screen) and the command of the first menu entry will +be called immediately. If delay is less then 0, bootmenu will be shown and +autoboot will be disabled. + +Bootmenu always adds menu entry "U-Boot console" at the end of all menu +entries specified by environment variables. When selecting this entry +the bootmenu terminates and the usual U-Boot command prompt is presented +to the user. + +Example environment: + + setenv bootmenu_0 Boot 1. kernel=bootm 0x82000000 # Set first menu entry + setenv bootmenu_1 Boot 2. kernel=bootm 0x83000000 # Set second menu entry + setenv bootmenu_2 Reset board=reset # Set third menu entry + setenv bootmenu_3 U-Boot boot order=boot # Set fourth menu entry + bootmenu 20 # Run bootmenu with autoboot delay 20s + + +The above example will be rendered as below +(without decorating rectangle): + +┌──────────────────────────────────────────┐ +│ │ +│ *** U-Boot Boot Menu *** │ +│ │ +│ Boot 1. kernel │ +│ Boot 2. kernel │ +│ Reset board │ +│ U-Boot boot order │ +│ U-Boot console │ +│ │ +│ Hit any key to stop autoboot: 20 │ +│ Press UP/DOWN to move, ENTER to select │ +│ │ +└──────────────────────────────────────────┘ + +Selected menu entry will be highlighted - it will have inverted +background and text colors. + +To enable the "bootmenu" command add following definitions to the +board config file: + + #define CONFIG_CMD_BOOTMENU + #define CONFIG_MENU + +To run the bootmenu at startup add these additional definitions: + + #define CONFIG_AUTOBOOT_KEYED + #define CONFIG_BOOTDELAY 30 + #define CONFIG_MENU_SHOW + +When you intend to use the bootmenu on color frame buffer console, +make sure to additionally define CONFIG_CFB_CONSOLE_ANSI in the +board config file. diff --git a/doc/README.fdt-control b/doc/README.fdt-control index 85bda03..8352835 100644 --- a/doc/README.fdt-control +++ b/doc/README.fdt-control @@ -156,6 +156,14 @@ To use this, put something like this in your board header file: #define CONFIG_EXTRA_ENV_SETTINGS "fdtcontroladdr=10000\0" +Build: + +After board configuration is done, fdt supported u-boot can be build in two ways: +1) build the default dts which is defined from CONFIG_DEFAULT_DEVICE_TREE + $ make +2) build the user specified dts file + $ make DEVICE_TREE=<dts-file-name> + Limitations ----------- diff --git a/doc/README.memory-test b/doc/README.memory-test new file mode 100644 index 0000000..eb60e8d --- /dev/null +++ b/doc/README.memory-test @@ -0,0 +1,98 @@ +The most frequent cause of problems when porting U-Boot to new +hardware, or when using a sloppy port on some board, is memory errors. +In most cases these are not caused by failing hardware, but by +incorrect initialization of the memory controller. So it appears to +be a good idea to always test if the memory is working correctly, +before looking for any other potential causes of any problems. + +U-Boot implements 3 different approaches to perform memory tests: + +1. The get_ram_size() function (see "common/memsize.c"). + + This function is supposed to be used in each and every U-Boot port + determine the presence and actual size of each of the potential + memory banks on this piece of hardware. The code is supposed to be + very fast, so running it for each reboot does not hurt. It is a + little known and generally underrated fact that this code will also + catch 99% of hardware related (i. e. reliably reproducible) memory + errors. It is strongly recommended to always use this function, in + each and every port of U-Boot. + +2. The "mtest" command. + + This is probably the best known memory test utility in U-Boot. + Unfortunately, it is also the most problematic, and the most + useless one. + + There are a number of serious problems with this command: + + - It is terribly slow. Running "mtest" on the whole system RAM + takes a _long_ time before there is any significance in the fact + that no errors have been found so far. + + - It is difficult to configure, and to use. And any errors here + will reliably crash or hang your system. "mtest" is dumb and has + no knowledge about memory ranges that may be in use for other + purposes, like exception code, U-Boot code and data, stack, + malloc arena, video buffer, log buffer, etc. If you let it, it + will happily "test" all such areas, which of course will cause + some problems. + + - It is not easy to configure and use, and a large number of + systems are seriously misconfigured. The original idea was to + test basically the whole system RAM, with only exempting the + areas used by U-Boot itself - on most systems these are the areas + used for the exception vectors (usually at the very lower end of + system memory) and for U-Boot (code, data, etc. - see above; + these are usually at the very upper end of system memory). But + experience has shown that a very large number of ports use + pretty much bogus settings of CONFIG_SYS_MEMTEST_START and + CONFIG_SYS_MEMTEST_END; this results in useless tests (because + the ranges is too small and/or badly located) or in critical + failures (system crashes). + + Because of these issues, the "mtest" command is considered depre- + cated. It should not be enabled in most normal ports of U-Boot, + especially not in production. If you really need a memory test, + then see 1. and 3. above resp. below. + +3. The most thorough memory test facility is available as part of the + POST (Power-On Self Test) sub-system, see "post/drivers/memory.c". + + If you really need to perform memory tests (for example, because + it is mandatory part of your requirement specification), then + enable this test which is generic and should work on all archi- + tectures. + +WARNING: + +It should pointed out that _all_ these memory tests have one +fundamental, unfixable design flaw: they are based on the assumption +that memory errors can be found by writing to and reading from memory. +Unfortunately, this is only true for the relatively harmless, usually +static errors like shorts between data or address lines, unconnected +pins, etc. All the really nasty errors which will first turn your +hair gray, only to make you tear it out later, are dynamical errors, +which usually happen not with simple read or write cycles on the bus, +but when performing back-to-back data transfers in burst mode. Such +accesses usually happen only for certain DMA operations, or for heavy +cache use (instruction fetching, cache flushing). So far I am not +aware of any freely available code that implements a generic, and +efficient, memory test like that. The best known test case to stress +a system like that is to boot Linux with root file system mounted over +NFS, and then build some larger software package natively (say, +compile a Linux kernel on the system) - this will cause enough context +switches, network traffic (and thus DMA transfers from the network +controller), varying RAM use, etc. to trigger any weak spots in this +area. + +Note: An attempt was made once to implement such a test to catch +memory problems on a specific board. The code is pretty much board +specific (for example, it includes setting specific GPIO signals to +provide triggers for an attached logic analyzer), but you can get an +idea how it works: see "examples/standalone/test_burst*". + +Note 2: Ironically enough, the "test_burst" did not catch any RAM +errors, not a single one ever. The problems this code was supposed +to catch did not happen when accessing the RAM, but when reading from +NOR flash. diff --git a/doc/README.menu b/doc/README.menu index 6ce6bba..a8999ca 100644 --- a/doc/README.menu +++ b/doc/README.menu @@ -51,7 +51,9 @@ struct menu; * menu_create() - Creates a menu handle with default settings */ struct menu *menu_create(char *title, int timeout, int prompt, - void (*item_data_print)(void *)); + void (*item_data_print)(void *), + char *(*item_choice)(void *), + void *item_choice_data); /* * menu_item_add() - Adds or replaces a menu item @@ -64,6 +66,11 @@ int menu_item_add(struct menu *m, char *item_key, void *item_data); int menu_default_set(struct menu *m, char *item_key); /* + * menu_default_choice() - Set *choice to point to the default item's data + */ +int menu_default_choice(struct menu *m, void **choice); + +/* * menu_get_choice() - Returns the user's selected menu entry, or the * default if the menu is set to not prompt or the timeout expires. */ diff --git a/doc/README.omap3 b/doc/README.omap3 index 0a37de0..1fbe79d 100644 --- a/doc/README.omap3 +++ b/doc/README.omap3 @@ -145,6 +145,34 @@ int omap3_dma_wait_for_transfer(uint32_t chan) int omap3_dma_get_revision(uint32_t *minor, uint32_t *major) Read silicon Revision of the DMA module +NAND +==== + +There are some OMAP3 devices out there with NAND attached. Due to the fact that +OMAP3 ROM code can only handle 1-bit hamming ECC for accessing first page +(place where SPL lives) we require this setup for u-boot at least when reading +the second progam within SPL. A lot of newer NAND chips however require more +than 1-bit ECC for the pages, some can live with 1-bit for the first page. To +handle this we can switch to another ECC algorithm after reading the payload +within SPL. + +BCH8 +---- + +To enable hardware assisted BCH8 (8-bit BCH [Bose, Chaudhuri, Hocquenghem]) on +OMAP3 devices we can use the BCH library in lib/bch.c. To do so add CONFIG_BCH +to enable the library and CONFIG_NAND_OMAP_BCH8 to to enable hardware assisted +syndrom generation to your board config. +The NAND OOB layout is the same as in linux kernel, if the linux kernel BCH8 +implementation for OMAP3 works for you so the u-boot version should also. +When you require the SPL to read with BCH8 there are two more configs to +change: + + * CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in + GPMC_NAND_HW_BCH8_ECC_LAYOUT defined in + arch/arm/include/asm/arch-omap3/omap_gpmc.h) + * CONFIG_SYS_NAND_ECCSIZE must be 512 + * CONFIG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup Acknowledgements ================ diff --git a/doc/README.scrapyard b/doc/README.scrapyard index e9ca96c..2cdb8a9 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,6 +11,7 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +smdk6400 arm arm1176 - - Zhong Hongbo <bocui107@gmail.com> ns9750dev arm arm926ejs - - Markus Pietrek <mpietrek@fsforth.de> AMX860 powerpc mpc860 1b0757e 2012-10-28 Wolfgang Denk <wd@denx.de> c2mon powerpc mpc855 1b0757e 2012-10-28 Wolfgang Denk <wd@denx.de> @@ -90,3 +91,5 @@ MVS1 powerpc MPC823 306620b 2008-08-26 Andre Schwar adsvix ARM PXA27x 7610db1 2008-07-30 Adrian Filipi <adrian.filipi@eurotech.com> R5200 ColdFire - 48ead7a 2008-03-31 Zachary P. Landau <zachary.landau@labxtechnologies.com> CPCI440 powerpc 440GP b568fd2 2007-12-27 Matthias Fuchs <matthias.fuchs@esd-electronics.com> +PCIPPC2 powerpc MPC740/MPC750 7c9e89b 2013-02-07 Wolfgang Denk <wd@denx.de> +PCIPPC6 powerpc MPC740/MPC750 - - Wolfgang Denk <wd@denx.de> diff --git a/doc/README.silent b/doc/README.silent index 70202ce..6d90a0e 100644 --- a/doc/README.silent +++ b/doc/README.silent @@ -23,4 +23,6 @@ The following actions are taken if "silent" is set at boot time: - When booting a linux kernel, the "bootargs" are fixed up so that the argument "console=" will be in the command line, no matter how - it was set in "bootargs" before. + it was set in "bootargs" before. If you don't want the linux command + line to be affected, define CONFIG_SILENT_U_BOOT_ONLY in your board + config file as well, and this part of the feature will be disabled. diff --git a/doc/device-tree-bindings/exynos/tmu.txt b/doc/device-tree-bindings/exynos/tmu.txt new file mode 100644 index 0000000..89d3bf0 --- /dev/null +++ b/doc/device-tree-bindings/exynos/tmu.txt @@ -0,0 +1,44 @@ +Exynos Thermal management Unit + +Required properties: + + - compatible : Should be "samsung,exynos-tmu" for TMU + - samsung,min-temp : Minimum temperature value (25 degree celsius) + - Current temperature of SoC should be more than this value. + - samsung,max-temp : Maximum temperature value (125 degree celsius) + - Current temperature of SoC should be less than this value. + - samsung,start-warning : Temperature at which TMU starts giving warning (degree celsius) + - samsung,start-tripping : Temperature at which TMU shuts down the system (degree celsius) + - samsung,hw-tripping : Temperature at which hardware tripping should happen + in case TMU fails to power off (degree celsius) + - samsung,efuse-min-value : SOC efuse min value (Constant 40) + - efuse-value should be more than this value. + - samsung,efuse-value : SOC actual efuse value (Literal value) + - This is the data trimming info. + - This value is used to calculate measuring error. + - samsung,efuse-max-value : SoC max efuse value (Constant 100) + - efuse-value should be less than this value. + - samsung,slope : Default value 274761730 (Constant 0x1060_8802). + - This is the default value for TMU_CONTROL register. + - It sets the gain of amplifier to the positive-tc generator block. + - It selects thermal tripping mode and enables thermal tripping. + - samsung,dc-value : Measured data calibration value (Constant 25) + - Used for tempearture calculation. + - This is 25 because temperature measured is always above 25 degrees. + + +Example: + +tmu@10060000 { + compatible = "samsung,exynos-tmu" + samsung,min-temp = <25>; + samsung,max-temp = <125>; + samsung,start-warning = <95>; + samsung,start-tripping = <105>; + samsung,hw-tripping = <110>; + samsung,efuse-min-value = <40>; + samsung,efuse-value = <55>; + samsung,efuse-max-value = <100>; + samsung,slope = <274761730>; + samsung,dc-value = <25>; +}; diff --git a/doc/device-tree-bindings/video/exynos-dp.txt b/doc/device-tree-bindings/video/exynos-dp.txt new file mode 100644 index 0000000..464a853 --- /dev/null +++ b/doc/device-tree-bindings/video/exynos-dp.txt @@ -0,0 +1,69 @@ +Exynos Display port controller +============================== + +Required properties: +SOC specific: + compatible: should be "samsung,exynos5-dp" + reg: Base address of DP IP + +Optional properties: + samsung,h-res: X resolution of the panel + samsung,h-sync-width: hsync value + samsung,h-back-porch: left margin + samsung,h-front-porch right margin + samsung,v-res: Y resolution of the panel + samsung,v-sync-width: vsync value + samsung,v-back-porch: upper margin + samsung,v-front-porch: lower margin + samsung,v-sync-rate: refresh rate + + samsung,lt-status: Link training status + 0(DP_LT_NONE), 1(DP_LT_START), 2(DP_LT_CR), 3(DP_LT_ET), + 4(DP_LT_FINISHED), 5(DP_LT_FAIL) + + samsung,master-mode: 1 if you want to run DP as master, else 0 + samsung,bist-mode: 1 to enable video bist mode, else 0 + samsung,bist-pattern: bist mode pattern type + 0(NO_PATTERN), 1(COLOR_RAMP), 2(BALCK_WHITE_V_LINES), + 3(COLOR_SQUARE), 4(INVALID_PATTERN), 5(COLORBAR_32), + 6(COLORBAR_64),7(WHITE_GRAY_BALCKBAR_32), + 8(WHITE_GRAY_BALCKBAR_64),9(MOBILE_WHITEBAR_32), + 10(MOBILE_WHITEBAR_64) + samsung,h-sync-polarity: Horizontal Sync polarity + CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + samsung,v-sync-polarity: Vertical Sync polarity + CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + samsung,interlaced: Progressive if 0, else Interlaced + samsung,color-space: input video data format + COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2 + samsung,dynamic-range: dynamic range for input video data + VESA = 0, CEA = 1 + samsung,ycbcr-coeff: YCbCr co-efficients for input video + COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1 + samsung,color-depth: number of bits per colour component + COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3 + +Example: +SOC specific part: + dp@145b0000 { + compatible = "samsung,exynos5-dp"; + reg = <0x145b0000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + +Board(panel) specific part: + dp@145b0000 { + samsung,lt-status = <0>; + + samsung,master-mode = <0>; + samsung,bist-mode = <0>; + samsung,bist-pattern = <0>; + samsung,h-sync-polarity = <0>; + samsung,v-sync-polarity = <0>; + samsung,interlaced = <0>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + }; diff --git a/doc/device-tree-bindings/video/exynos-fb.txt b/doc/device-tree-bindings/video/exynos-fb.txt new file mode 100644 index 0000000..bb7441c --- /dev/null +++ b/doc/device-tree-bindings/video/exynos-fb.txt @@ -0,0 +1,92 @@ +Exynos Display Controller +========================= +Required properties: +SOC specific: + compatible: should be "samsung,exynos-fimd" + reg: Base address of FIMD IP. + +Board(panel specific): + samsung,vl-col: X resolution of the panel + samsung,vl-row: Y resolution of the panel + samsung,vl-freq: Refresh rate + samsung,vl-bpix: Bits per pixel + samsung,vl-hspw: Hsync value + samsung,vl-hfpd: Right margin + samsung,vl-hbpd: Left margin + samsung,vl-vspw: Vsync value + samsung,vl-vfpd: Lower margin + samsung,vl-vbpd: Upper margin + +Optional properties: +Board(panel specific): + samsung,vl-width: width of display area in mm + samsung,vl-height: Height of display area in mm + + samsung,vl-clkp: Clock polarity + CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + samsung,vl-oep: Output Enable polarity + CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + samsung,vl-hsp: Horizontal Sync polarity + CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + samsung,vl-vsp: Vertical Sync polarity + CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + samsung,vl-dp: Data polarity + CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + + samsung,vl-cmd-allow-len: Wait end of frame + samsung,winid: Window number on which data is to be displayed + samsung,init-delay: Delay before LCD initialization starts + samsung,power-on-delay: Delay after LCD is powered on + samsung,reset-delay: Delay after LCD is reset + samsung,interface-mode: 1(FIMD_RGB_INTERFACE), 2(FIMD_CPU_INTERFACE) + samsung,mipi-enabled: 1 if you want to use MIPI, else 0 + samsung,dp-enabled: 1is you want to use DP, else 0 + samsung,cs-setup: cs_setup value in FIMD_CPU_INTERFACE mode. + samsung,wr-setup: wr_setup value in FIMD_CPU_INTERFACE mode. + samsung,wr-act: wr_act value in FIMD_CPU_INTERFACE mode. + samsung,wr-hold: wr_hold value in FIMD_CPU_INTERFACE mode. + samsung,logo-on: 1 if you want to use custom logo. + 0 if you want LCD console. + samsung,logo-width: pixel width of logo image. Valid if logo_on = 1 + samsung,logo-height: pixel height of logo image. Valid if logo_on = 1 + samsung,logo-addr: Address of logo image. Valid if logo_on = 1 + samsung,rgb-mode: 0(MODE_RGB_P), 1(MODE_BGR_P), + 2(MODE_RGB_S), 3(MODE_BGR_S) + samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL) + samsung,sclk-div: parent_clock/source_clock ratio + samsung,dual-lcd-enabled: 1 if you support two LCD, else 0 + +Example: +SOC specific part: + fimd@14400000 { + compatible = "samsung,exynos-fimd"; + reg = <0x14400000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + }; + +Board specific part: + fimd@14400000 { + samsung,vl-freq = <60>; + samsung,vl-col = <2560>; + samsung,vl-row = <1600>; + samsung,vl-width = <2560>; + samsung,vl-height = <1600>; + + samsung,vl-clkp; + samsung,vl-dp; + samsung,vl-bpix = <4>; + + samsung,vl-hspw = <32>; + samsung,vl-hbpd = <80>; + samsung,vl-hfpd = <48>; + samsung,vl-vspw = <6>; + samsung,vl-vbpd = <37>; + samsung,vl-vfpd = <3>; + samsung,vl-cmd-allow-len = <0xf>; + + samsung,winid = <3>; + samsung,interface-mode = <1>; + samsung,dp-enabled = <1>; + samsung,dual-lcd-enabled = <0>; + }; diff --git a/doc/driver-model/UDM-pci.txt b/doc/driver-model/UDM-pci.txt index b65e9ea..c2cf2d5 100644 --- a/doc/driver-model/UDM-pci.txt +++ b/doc/driver-model/UDM-pci.txt @@ -240,10 +240,6 @@ III) Analysis of in-tree drivers ---------------- Standard driver, uses indirect functions. - 8) pcippc2/cpc710_pci.c - ----------------------- - Standard driver, uses indirect functions, has two busses. - 9) Marvell/db64360/pci.c ------------------------ Standard driver, uses dword for read/write ops, has two busses. diff --git a/doc/driver-model/UDM-serial.txt b/doc/driver-model/UDM-serial.txt index ef71fea..1011c32 100644 --- a/doc/driver-model/UDM-serial.txt +++ b/doc/driver-model/UDM-serial.txt @@ -96,88 +96,84 @@ III) Analysis of in-tree drivers ------------------ No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 10) s3c64xx.c + 10) sandbox.c ------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 11) sandbox.c - ------------- - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - - 12) serial.c + 11) serial.c ------------ This is a complementary part of NS16550 UART driver, see above. - 13) serial_clps7111.c + 12) serial_clps7111.c --------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 14) serial_imx.c + 13) serial_imx.c ---------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. This driver might be removed in favor of serial_mxc.c . - 15) serial_ixp.c + 14) serial_ixp.c ---------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 16) serial_ks8695.c + 15) serial_ks8695.c ------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 17) serial_max3100.c + 16) serial_max3100.c -------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 18) serial_mxc.c + 17) serial_mxc.c ---------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 19) serial_netarm.c + 18) serial_netarm.c ------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 20) serial_pl01x.c + 19) serial_pl01x.c ------------------ No support for CONFIG_SERIAL_MULTI. Simple conversion possible, though this driver in fact contains two drivers in total. - 21) serial_pxa.c + 20) serial_pxa.c ---------------- This driver is a bit complicated, but due to clean support for CONFIG_SERIAL_MULTI, there are no expected obstructions throughout the conversion process. - 22) serial_s3c24x0.c + 21) serial_s3c24x0.c -------------------- This driver, being quite ad-hoc might need some work to bring back to shape. - 23) serial_s3c44b0.c + 22) serial_s3c44b0.c -------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 24) serial_s5p.c + 23) serial_s5p.c ---------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 25) serial_sa1100.c + 24) serial_sa1100.c ------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 26) serial_sh.c + 25) serial_sh.c --------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 27) serial_xuartlite.c + 26) serial_xuartlite.c ---------------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - 28) usbtty.c + 27) usbtty.c ------------ This driver seems very complicated and entangled with USB framework. The conversion might be complicated here. - 29) arch/powerpc/cpu/mpc512x/serial.c + 28) arch/powerpc/cpu/mpc512x/serial.c ------------------------------------- This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to proper place. diff --git a/doc/driver-model/UDM-watchdog.txt b/doc/driver-model/UDM-watchdog.txt index 271bd26..7db3286 100644 --- a/doc/driver-model/UDM-watchdog.txt +++ b/doc/driver-model/UDM-watchdog.txt @@ -292,11 +292,6 @@ III) Analysis of in-tree drivers Only function proxy call. Code cleanup needed. - 45) board/pcippc2/pcippc2.c - --------------------------- - The driver is standard HW watchdog. Simple conversion is possible. - - 46) board/pcs440ep/pcs440ep.c ----------------------------- The driver is standard HW watchdog. Simple conversion is possible. diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt index e04ba2d..ce72861 100644 --- a/doc/feature-removal-schedule.txt +++ b/doc/feature-removal-schedule.txt @@ -7,30 +7,47 @@ file. --------------------------- -What: Users of the legacy miiphy_* code -When: undetermined +What: Remove CONFIG_CMD_MEMTEST from default list +When: Release v2013.07 -Why: We now have a PHY library, which allows everyone to share PHY - drivers. All new drivers should use this infrastructure, and - all old drivers should get converted to use it. +Why: The "mtest" command is of little practical use (if any), and + experience has shown that a large number of board configu- + rations define useless or even dangerous start and end + addresses. If not even the board maintainers are able to + figure out which memory range can be reliably tested, how can + we expect such from the end users? As this problem comes up + repeatedly, we rather do not enable this command by default, + so only people who know what they are doing will be confronted + with it. -Who: Andy Fleming <afleming@freescale.com> and driver maintainers +Who: Wolfgang Denk <wd@denx.de> --------------------------- -What: boards with xxx_config targets in top level Makefile -When: Release v2012.03 +What: Remove CONFIG_SYS_ENABLE_PADS_ALL and CONFIG_SYS_CLOCKS_ENABLE_ALL +When: Release v2013.07 + +Why: When set these options enable "all" of the pads and clocks found + on OMAP4/5 platforms, so that the Linux Kernel does not have to. + It has been agreed that this goes against the U-Boot design + philosophy and since f3f98bb0 we have not enabled more than is + used in U-Boot. The kernel has been updating drivers to enable + rather than assume pads/clocks have been enabled already. Our + expectation is that by v2013.07 a suitable kernel shall exist that + does not need these options set for a reasonable I/O set to function. + +Who: Tom Rini <trini@ti.com> and Sricharan R <r.sricharan@ti.com> -Why: We have a boards.cfg file which the vast majority of boards have - converted over to. Boards that still manually run mkconfig in the - top level Makefile are either dead, or the maintainer doesn't care, - or they are doing something weird/wrong that should be fixed in a - different way, or they need to extend boards.cfg syntax (unlikely). +--------------------------- + +What: Users of the legacy miiphy_* code +When: undetermined - In any case, if no one cares about these boards to figure out how - to make boards.cfg work, then we'll just punt them. +Why: We now have a PHY library, which allows everyone to share PHY + drivers. All new drivers should use this infrastructure, and + all old drivers should get converted to use it. -Who: Mike Frysinger <vapier@gentoo.org> +Who: Andy Fleming <afleming@freescale.com> and driver maintainers --------------------------- diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index dbb5e8c..3b2ed6e 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -52,10 +52,6 @@ /* Length of the BIOS image */ #define MAX_BIOSLEN (128 * 1024L) -/* Define some useful types and macros */ -#define true 1 -#define false 0 - /* Place to save PCI BAR's that we change and later restore */ static u32 saveROMBaseAddress; static u32 saveBaseAddress10; @@ -242,7 +238,7 @@ pcidev - PCI device info for the video card on the bus to boot VGAInfo - BIOS emulator VGA info structure RETURNS: -True if successfully initialised, false if not. +true if successfully initialised, false if not. REMARKS: Loads and POST's the display controllers BIOS, directly from the BIOS @@ -295,7 +291,7 @@ static int PCI_postController(pci_dev_t pcidev, BE_VGAInfo * VGAInfo) PARAMETERS: pcidev - PCI device info for the video card on the bus to boot pVGAInfo - Place to return VGA info structure is requested -cleanUp - True to clean up on exit, false to leave emulator active +cleanUp - true to clean up on exit, false to leave emulator active REMARKS: Boots the PCI/AGP video card on the bus using the Video ROM BIOS image diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c index 84724b7..ad88a53 100644 --- a/drivers/bios_emulator/besys.c +++ b/drivers/bios_emulator/besys.c @@ -47,6 +47,8 @@ * ****************************************************************************/ +#define __io +#include <asm/io.h> #include <common.h> #include "biosemui.h" diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c index 7cf4879..bcc192f 100644 --- a/drivers/bios_emulator/bios.c +++ b/drivers/bios_emulator/bios.c @@ -41,6 +41,8 @@ * ****************************************************************************/ +#define __io +#include <asm/io.h> #include <common.h> #include "biosemui.h" diff --git a/drivers/bios_emulator/include/biosemu.h b/drivers/bios_emulator/include/biosemu.h index 13cb317..e92e96e 100644 --- a/drivers/bios_emulator/include/biosemu.h +++ b/drivers/bios_emulator/include/biosemu.h @@ -127,9 +127,9 @@ biosmem_limit - Limit of the BIOS image busmem_base - Base of the VGA bus memory timer - Timer used to emulate PC timer ports timer0 - Latched value for timer 0 -timer0Latched - True if timer 0 value was just latched +timer0Latched - true if timer 0 value was just latched timer2 - Current value for timer 2 -emulateVGA - True to emulate VGA I/O and memory accesses +emulateVGA - true to emulate VGA I/O and memory accesses ****************************************************************************/ typedef struct { diff --git a/drivers/bios_emulator/x86emu/debug.c b/drivers/bios_emulator/x86emu/debug.c index 6417d09..2fa8050 100644 --- a/drivers/bios_emulator/x86emu/debug.c +++ b/drivers/bios_emulator/x86emu/debug.c @@ -309,7 +309,7 @@ void x86emu_single_step(void) case 'P': noDecode = (noDecode) ? 0 : 1; printk("Toggled decoding to %s\n", - (noDecode) ? "FALSE" : "TRUE"); + (noDecode) ? "false" : "true"); break; case 't': case 0: diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c index 8c785ae..cab7f8c 100644 --- a/drivers/block/ahci.c +++ b/drivers/block/ahci.c @@ -865,14 +865,14 @@ int scsi_exec(ccb *pccb) break; default: printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); - return FALSE; + return false; } if (ret) { debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); - return FALSE; + return false; } - return TRUE; + return true; } diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index a88d0f7..42c177f 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -56,8 +56,8 @@ struct mvsata_port_registers { * Sanity checks: * - to compile at all, we need CONFIG_SYS_ATA_BASE_ADDR. * - for ide_preinit to make sense, we need at least one of - * CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE0_OFFSET; - * - for inde_preinit to be called, we need CONFIG_IDE_PREINIT. + * CONFIG_SYS_ATA_IDE0_OFFSET or CONFIG_SYS_ATA_IDE1_OFFSET; + * - for ide_preinit to be called, we need CONFIG_IDE_PREINIT. * Fail with an explanation message if these conditions are not met. * This is particularly important for CONFIG_IDE_PREINIT, because * its lack would not cause a build error. diff --git a/drivers/block/sata_dwc.c b/drivers/block/sata_dwc.c index 28d87f5..49288a7 100644 --- a/drivers/block/sata_dwc.c +++ b/drivers/block/sata_dwc.c @@ -360,7 +360,7 @@ int init_sata(int dev) if (status == 0x7f) { printf("Hard Disk not found.\n"); dev_state = SATA_NODEVICE; - rc = FALSE; + rc = false; return rc; } @@ -381,7 +381,7 @@ int init_sata(int dev) printf("** TimeOUT **\n"); dev_state = SATA_NODEVICE; - rc = FALSE; + rc = false; return rc; } if ((i >= 100) && ((i % 100) == 0)) @@ -458,7 +458,7 @@ static int sata_dwc_softreset(struct ata_port *ap) } else { printf("No device found\n"); dev_state = SATA_NODEVICE; - return FALSE; + return false; } tmp = ATA_DEVICE_OBS; @@ -737,7 +737,7 @@ static int ata_dev_read_id(struct ata_device *dev, unsigned int *p_class, status = ata_busy_wait(ap, ATA_BUSY, 30000); if (status & ATA_BUSY) { printf("BSY = 0 check. timeout.\n"); - rc = FALSE; + rc = false; return rc; } @@ -987,7 +987,7 @@ unsigned ata_exec_internal(struct ata_device *dev, status = ata_busy_wait(ap, ATA_BUSY, 300000); if (status & ATA_BUSY) { printf("BSY = 0 check. timeout.\n"); - rc = FALSE; + rc = false; return rc; } @@ -997,7 +997,7 @@ unsigned ata_exec_internal(struct ata_device *dev, tag = ATA_TAG_INTERNAL; if (test_and_set_bit(tag, &ap->qc_allocated)) { - rc = FALSE; + rc = false; return rc; } @@ -1656,14 +1656,14 @@ static int check_sata_dev_state(void) ret = ata_dev_read_sectors(pdata, datalen, 0, 1); - if (ret == TRUE) + if (ret == true) break; i++; if (i > (ATA_RESET_TIME * 100)) { printf("** TimeOUT **\n"); dev_state = SATA_NODEVICE; - return FALSE; + return false; } if ((i >= 100) && ((i % 100) == 0)) @@ -1672,7 +1672,7 @@ static int check_sata_dev_state(void) dev_state = SATA_READY; - return TRUE; + return true; } static unsigned int ata_dev_set_feature(struct ata_device *dev, @@ -1772,7 +1772,7 @@ ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer) blks = 0; } - if (ata_dev_read_sectors(pdata, datalen, block, n_block) != TRUE) { + if (ata_dev_read_sectors(pdata, datalen, block, n_block) != true) { printf("sata_dwc : Hard disk read error.\n"); blkcnt -= blks; break; @@ -1795,7 +1795,7 @@ static int ata_dev_read_sectors(unsigned char *pdata, unsigned long datalen, int may_fallback = 1; if (dev_state == SATA_ERROR) - return FALSE; + return false; ata_dev_select(ap, dev->devno, 1, 1); @@ -1893,11 +1893,11 @@ retry: goto err_out; } - return TRUE; + return true; err_out: printf("failed to READ SECTORS (%s, err_mask=0x%x)\n", reason, err_mask); - return FALSE; + return false; } #if defined(CONFIG_SATA_DWC) && !defined(CONFIG_LBA48) @@ -1946,7 +1946,7 @@ ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer) blks = 0; } - if (ata_dev_write_sectors(pdata, datalen, block, n_block) != TRUE) { + if (ata_dev_write_sectors(pdata, datalen, block, n_block) != true) { printf("sata_dwc : Hard disk read error.\n"); blkcnt -= blks; break; @@ -1969,7 +1969,7 @@ static int ata_dev_write_sectors(unsigned char* pdata, unsigned long datalen, int may_fallback = 1; if (dev_state == SATA_ERROR) - return FALSE; + return false; ata_dev_select(ap, dev->devno, 1, 1); @@ -2068,9 +2068,9 @@ retry: goto err_out; } - return TRUE; + return true; err_out: printf("failed to WRITE SECTORS (%s, err_mask=0x%x)\n", reason, err_mask); - return FALSE; + return false; } diff --git a/drivers/block/sata_dwc.h b/drivers/block/sata_dwc.h index 204d644..e4e4ab1 100644 --- a/drivers/block/sata_dwc.h +++ b/drivers/block/sata_dwc.h @@ -467,11 +467,4 @@ struct ata_port { unsigned char *pdata; }; -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - #endif diff --git a/drivers/block/sym53c8xx.c b/drivers/block/sym53c8xx.c index 564aa98..656683a 100644 --- a/drivers/block/sym53c8xx.c +++ b/drivers/block/sym53c8xx.c @@ -764,9 +764,9 @@ int scsi_exec(ccb *pccb) retry: scsi_issue(pccb); if(pccb->contr_stat!=SIR_COMPLETE) - return FALSE; + return false; if(pccb->status==S_GOOD) - return TRUE; + return true; if(pccb->status==S_CHECK_COND) { /* check condition */ for(i=0;i<16;i++) tmpcmd[i]=pccb->cmd[i]; @@ -797,12 +797,12 @@ retry: case SENSE_NO_SENSE: case SENSE_RECOVERED_ERROR: /* seems to be ok */ - return TRUE; + return true; break; case SENSE_NOT_READY: if((pccb->sense_buf[12]!=0x04)||(pccb->sense_buf[13]!=0x01)) { /* if device is not in process of becoming ready */ - return FALSE; + return false; break; } /* else fall through */ case SENSE_UNIT_ATTENTION: @@ -814,13 +814,13 @@ retry: goto retry; } PRINTF("Target %d not ready, %d retried\n",pccb->target,retrycnt); - return FALSE; + return false; default: - return FALSE; + return false; } } PRINTF("Status = %X\n",pccb->status); - return FALSE; + return false; } diff --git a/arch/arm/cpu/arm1176/s3c64xx/Makefile b/drivers/crypto/Makefile index 266a073..2c54793 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/Makefile +++ b/drivers/crypto/Makefile @@ -1,9 +1,6 @@ # -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> +# Copyright (c) 2013 Samsung Electronics Co., Ltd. +# http://www.samsung.com # # See file CREDITS for list of people who contributed to this # project. @@ -15,7 +12,7 @@ # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License @@ -26,20 +23,20 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(SOC).o - -SOBJS = reset.o +LIB := $(obj)libcrypto.o -COBJS-$(CONFIG_S3C6400) += cpu_init.o speed.o -COBJS-y += timer.o init.o +COBJS-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) -all: $(obj).depend $(START) $(LIB) +all: $(LIB) -$(LIB): $(OBJS) +$(LIB): $(obj).depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) + ######################################################################### # defines $(obj).depend target @@ -47,4 +44,4 @@ include $(SRCTREE)/rules.mk sinclude $(obj).depend -######################################################################### +######################################################################## diff --git a/drivers/crypto/ace_sha.c b/drivers/crypto/ace_sha.c new file mode 100644 index 0000000..53ebb33 --- /dev/null +++ b/drivers/crypto/ace_sha.c @@ -0,0 +1,126 @@ +/* + * Advanced Crypto Engine - SHA Firmware + * Copyright (c) 2012 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#include <common.h> +#include <sha256.h> +#include <sha1.h> +#include <asm/errno.h> +#include "ace_sha.h" + +/* SHA1 value for the message of zero length */ +static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = { + 0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D, + 0x32, 0x55, 0xBF, 0xFF, 0x95, 0x60, 0x18, 0x90, + 0xAF, 0xD8, 0x07, 0x09}; + +/* SHA256 value for the message of zero length */ +static const unsigned char sha256_digest_emptymsg[SHA256_SUM_LEN] = { + 0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14, + 0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24, + 0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C, + 0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55}; + +int ace_sha_hash_digest(const unsigned char *pbuf, unsigned int buf_len, + unsigned char *pout, unsigned int hash_type) +{ + unsigned int i, reg, len; + unsigned int *pdigest; + struct exynos_ace_sfr *ace_sha_reg = + (struct exynos_ace_sfr *)samsung_get_base_ace_sfr(); + + if (buf_len == 0) { + /* ACE H/W cannot compute hash value for empty string */ + if (hash_type == ACE_SHA_TYPE_SHA1) + memcpy(pout, sha1_digest_emptymsg, SHA1_SUM_LEN); + else + memcpy(pout, sha256_digest_emptymsg, SHA256_SUM_LEN); + return 0; + } + + /* Flush HRDMA */ + writel(ACE_FC_HRDMACFLUSH_ON, &ace_sha_reg->fc_hrdmac); + writel(ACE_FC_HRDMACFLUSH_OFF, &ace_sha_reg->fc_hrdmac); + + /* Set byte swap of data in */ + writel(ACE_HASH_SWAPDI_ON | ACE_HASH_SWAPDO_ON | ACE_HASH_SWAPIV_ON, + &ace_sha_reg->hash_byteswap); + + /* Select Hash input mux as external source */ + reg = readl(&ace_sha_reg->fc_fifoctrl); + reg = (reg & ~ACE_FC_SELHASH_MASK) | ACE_FC_SELHASH_EXOUT; + writel(reg, &ace_sha_reg->fc_fifoctrl); + + /* Set Hash as SHA1 or SHA256 and start Hash engine */ + reg = (hash_type == ACE_SHA_TYPE_SHA1) ? + ACE_HASH_ENGSEL_SHA1HASH : ACE_HASH_ENGSEL_SHA256HASH; + reg |= ACE_HASH_STARTBIT_ON; + writel(reg, &ace_sha_reg->hash_control); + + /* Enable FIFO mode */ + writel(ACE_HASH_FIFO_ON, &ace_sha_reg->hash_fifo_mode); + + /* Set message length */ + writel(buf_len, &ace_sha_reg->hash_msgsize_low); + writel(0, &ace_sha_reg->hash_msgsize_high); + + /* Set HRDMA */ + writel((unsigned int)pbuf, &ace_sha_reg->fc_hrdmas); + writel(buf_len, &ace_sha_reg->fc_hrdmal); + + while ((readl(&ace_sha_reg->hash_status) & ACE_HASH_MSGDONE_MASK) == + ACE_HASH_MSGDONE_OFF) { + /* + * PRNG error bit goes HIGH if a PRNG request occurs without + * a complete seed setup. We are using this bit to check h/w + * fault because proper setup is not expected in that case. + */ + if ((readl(&ace_sha_reg->hash_status) + & ACE_HASH_PRNGERROR_MASK) == ACE_HASH_PRNGERROR_ON) + return -EBUSY; + } + + /* Clear MSG_DONE bit */ + writel(ACE_HASH_MSGDONE_ON, &ace_sha_reg->hash_status); + + /* Read hash result */ + pdigest = (unsigned int *)pout; + len = (hash_type == ACE_SHA_TYPE_SHA1) ? SHA1_SUM_LEN : SHA256_SUM_LEN; + + for (i = 0; i < len / 4; i++) + pdigest[i] = readl(&ace_sha_reg->hash_result[i]); + + /* Clear HRDMA pending bit */ + writel(ACE_FC_HRDMA, &ace_sha_reg->fc_intpend); + + return 0; +} + +void hw_sha256(const unsigned char *pbuf, unsigned int buf_len, + unsigned char *pout, unsigned int chunk_size) +{ + if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA256)) + debug("ACE was not setup properly or it is faulty\n"); +} + +void hw_sha1(const unsigned char *pbuf, unsigned int buf_len, + unsigned char *pout, unsigned int chunk_size) +{ + if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1)) + debug("ACE was not setup properly or it is faulty\n"); +} diff --git a/drivers/crypto/ace_sha.h b/drivers/crypto/ace_sha.h new file mode 100644 index 0000000..0292a08 --- /dev/null +++ b/drivers/crypto/ace_sha.h @@ -0,0 +1,325 @@ +/* + * Header file for Advanced Crypto Engine - SFR definitions + * + * Copyright (c) 2012 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __ACE_SHA_H +#define __ACE_SHA_H + +struct exynos_ace_sfr { + unsigned int fc_intstat; /* base + 0 */ + unsigned int fc_intenset; + unsigned int fc_intenclr; + unsigned int fc_intpend; + unsigned int fc_fifostat; + unsigned int fc_fifoctrl; + unsigned int fc_global; + unsigned int res1; + unsigned int fc_brdmas; + unsigned int fc_brdmal; + unsigned int fc_brdmac; + unsigned int res2; + unsigned int fc_btdmas; + unsigned int fc_btdmal; + unsigned int fc_btdmac; + unsigned int res3; + unsigned int fc_hrdmas; + unsigned int fc_hrdmal; + unsigned int fc_hrdmac; + unsigned int res4; + unsigned int fc_pkdmas; + unsigned int fc_pkdmal; + unsigned int fc_pkdmac; + unsigned int fc_pkdmao; + unsigned char res5[0x1a0]; + + unsigned int aes_control; /* base + 0x200 */ + unsigned int aes_status; + unsigned char res6[0x8]; + unsigned int aes_in[4]; + unsigned int aes_out[4]; + unsigned int aes_iv[4]; + unsigned int aes_cnt[4]; + unsigned char res7[0x30]; + unsigned int aes_key[8]; + unsigned char res8[0x60]; + + unsigned int tdes_control; /* base + 0x300 */ + unsigned int tdes_status; + unsigned char res9[0x8]; + unsigned int tdes_key[6]; + unsigned int tdes_iv[2]; + unsigned int tdes_in[2]; + unsigned int tdes_out[2]; + unsigned char res10[0xc0]; + + unsigned int hash_control; /* base + 0x400 */ + unsigned int hash_control2; + unsigned int hash_fifo_mode; + unsigned int hash_byteswap; + unsigned int hash_status; + unsigned char res11[0xc]; + unsigned int hash_msgsize_low; + unsigned int hash_msgsize_high; + unsigned int hash_prelen_low; + unsigned int hash_prelen_high; + unsigned int hash_in[16]; + unsigned int hash_key_in[16]; + unsigned int hash_iv[8]; + unsigned char res12[0x30]; + unsigned int hash_result[8]; + unsigned char res13[0x20]; + unsigned int hash_seed[8]; + unsigned int hash_prng[8]; + unsigned char res14[0x180]; + + unsigned int pka_sfr[5]; /* base + 0x700 */ +}; + +/* ACE_FC_INT */ +#define ACE_FC_PKDMA (1 << 0) +#define ACE_FC_HRDMA (1 << 1) +#define ACE_FC_BTDMA (1 << 2) +#define ACE_FC_BRDMA (1 << 3) +#define ACE_FC_PRNG_ERROR (1 << 4) +#define ACE_FC_MSG_DONE (1 << 5) +#define ACE_FC_PRNG_DONE (1 << 6) +#define ACE_FC_PARTIAL_DONE (1 << 7) + +/* ACE_FC_FIFOSTAT */ +#define ACE_FC_PKFIFO_EMPTY (1 << 0) +#define ACE_FC_PKFIFO_FULL (1 << 1) +#define ACE_FC_HRFIFO_EMPTY (1 << 2) +#define ACE_FC_HRFIFO_FULL (1 << 3) +#define ACE_FC_BTFIFO_EMPTY (1 << 4) +#define ACE_FC_BTFIFO_FULL (1 << 5) +#define ACE_FC_BRFIFO_EMPTY (1 << 6) +#define ACE_FC_BRFIFO_FULL (1 << 7) + +/* ACE_FC_FIFOCTRL */ +#define ACE_FC_SELHASH_MASK (3 << 0) +#define ACE_FC_SELHASH_EXOUT (0 << 0) /* independent source */ +#define ACE_FC_SELHASH_BCIN (1 << 0) /* blk cipher input */ +#define ACE_FC_SELHASH_BCOUT (2 << 0) /* blk cipher output */ +#define ACE_FC_SELBC_MASK (1 << 2) +#define ACE_FC_SELBC_AES (0 << 2) +#define ACE_FC_SELBC_DES (1 << 2) + +/* ACE_FC_GLOBAL */ +#define ACE_FC_SSS_RESET (1 << 0) +#define ACE_FC_DMA_RESET (1 << 1) +#define ACE_FC_AES_RESET (1 << 2) +#define ACE_FC_DES_RESET (1 << 3) +#define ACE_FC_HASH_RESET (1 << 4) +#define ACE_FC_AXI_ENDIAN_MASK (3 << 6) +#define ACE_FC_AXI_ENDIAN_LE (0 << 6) +#define ACE_FC_AXI_ENDIAN_BIBE (1 << 6) +#define ACE_FC_AXI_ENDIAN_WIBE (2 << 6) + +/* Feed control - BRDMA control */ +#define ACE_FC_BRDMACFLUSH_OFF (0 << 0) +#define ACE_FC_BRDMACFLUSH_ON (1 << 0) +#define ACE_FC_BRDMACSWAP_ON (1 << 1) +#define ACE_FC_BRDMACARPROT_MASK (0x7 << 2) +#define ACE_FC_BRDMACARPROT_OFS 2 +#define ACE_FC_BRDMACARCACHE_MASK (0xf << 5) +#define ACE_FC_BRDMACARCACHE_OFS 5 + +/* Feed control - BTDMA control */ +#define ACE_FC_BTDMACFLUSH_OFF (0 << 0) +#define ACE_FC_BTDMACFLUSH_ON (1 << 0) +#define ACE_FC_BTDMACSWAP_ON (1 << 1) +#define ACE_FC_BTDMACAWPROT_MASK (0x7 << 2) +#define ACE_FC_BTDMACAWPROT_OFS 2 +#define ACE_FC_BTDMACAWCACHE_MASK (0xf << 5) +#define ACE_FC_BTDMACAWCACHE_OFS 5 + +/* Feed control - HRDMA control */ +#define ACE_FC_HRDMACFLUSH_OFF (0 << 0) +#define ACE_FC_HRDMACFLUSH_ON (1 << 0) +#define ACE_FC_HRDMACSWAP_ON (1 << 1) +#define ACE_FC_HRDMACARPROT_MASK (0x7 << 2) +#define ACE_FC_HRDMACARPROT_OFS 2 +#define ACE_FC_HRDMACARCACHE_MASK (0xf << 5) +#define ACE_FC_HRDMACARCACHE_OFS 5 + +/* Feed control - PKDMA control */ +#define ACE_FC_PKDMACBYTESWAP_ON (1 << 3) +#define ACE_FC_PKDMACDESEND_ON (1 << 2) +#define ACE_FC_PKDMACTRANSMIT_ON (1 << 1) +#define ACE_FC_PKDMACFLUSH_ON (1 << 0) + +/* Feed control - PKDMA offset */ +#define ACE_FC_SRAMOFFSET_MASK 0xfff + +/* AES control */ +#define ACE_AES_MODE_MASK (1 << 0) +#define ACE_AES_MODE_ENC (0 << 0) +#define ACE_AES_MODE_DEC (1 << 0) +#define ACE_AES_OPERMODE_MASK (3 << 1) +#define ACE_AES_OPERMODE_ECB (0 << 1) +#define ACE_AES_OPERMODE_CBC (1 << 1) +#define ACE_AES_OPERMODE_CTR (2 << 1) +#define ACE_AES_FIFO_MASK (1 << 3) +#define ACE_AES_FIFO_OFF (0 << 3) /* CPU mode */ +#define ACE_AES_FIFO_ON (1 << 3) /* FIFO mode */ +#define ACE_AES_KEYSIZE_MASK (3 << 4) +#define ACE_AES_KEYSIZE_128 (0 << 4) +#define ACE_AES_KEYSIZE_192 (1 << 4) +#define ACE_AES_KEYSIZE_256 (2 << 4) +#define ACE_AES_KEYCNGMODE_MASK (1 << 6) +#define ACE_AES_KEYCNGMODE_OFF (0 << 6) +#define ACE_AES_KEYCNGMODE_ON (1 << 6) +#define ACE_AES_SWAP_MASK (0x1f << 7) +#define ACE_AES_SWAPKEY_OFF (0 << 7) +#define ACE_AES_SWAPKEY_ON (1 << 7) +#define ACE_AES_SWAPCNT_OFF (0 << 8) +#define ACE_AES_SWAPCNT_ON (1 << 8) +#define ACE_AES_SWAPIV_OFF (0 << 9) +#define ACE_AES_SWAPIV_ON (1 << 9) +#define ACE_AES_SWAPDO_OFF (0 << 10) +#define ACE_AES_SWAPDO_ON (1 << 10) +#define ACE_AES_SWAPDI_OFF (0 << 11) +#define ACE_AES_SWAPDI_ON (1 << 11) +#define ACE_AES_COUNTERSIZE_MASK (3 << 12) +#define ACE_AES_COUNTERSIZE_128 (0 << 12) +#define ACE_AES_COUNTERSIZE_64 (1 << 12) +#define ACE_AES_COUNTERSIZE_32 (2 << 12) +#define ACE_AES_COUNTERSIZE_16 (3 << 12) + +/* AES status */ +#define ACE_AES_OUTRDY_MASK (1 << 0) +#define ACE_AES_OUTRDY_OFF (0 << 0) +#define ACE_AES_OUTRDY_ON (1 << 0) +#define ACE_AES_INRDY_MASK (1 << 1) +#define ACE_AES_INRDY_OFF (0 << 1) +#define ACE_AES_INRDY_ON (1 << 1) +#define ACE_AES_BUSY_MASK (1 << 2) +#define ACE_AES_BUSY_OFF (0 << 2) +#define ACE_AES_BUSY_ON (1 << 2) + +/* TDES control */ +#define ACE_TDES_MODE_MASK (1 << 0) +#define ACE_TDES_MODE_ENC (0 << 0) +#define ACE_TDES_MODE_DEC (1 << 0) +#define ACE_TDES_OPERMODE_MASK (1 << 1) +#define ACE_TDES_OPERMODE_ECB (0 << 1) +#define ACE_TDES_OPERMODE_CBC (1 << 1) +#define ACE_TDES_SEL_MASK (3 << 3) +#define ACE_TDES_SEL_DES (0 << 3) +#define ACE_TDES_SEL_TDESEDE (1 << 3) /* TDES EDE mode */ +#define ACE_TDES_SEL_TDESEEE (3 << 3) /* TDES EEE mode */ +#define ACE_TDES_FIFO_MASK (1 << 5) +#define ACE_TDES_FIFO_OFF (0 << 5) /* CPU mode */ +#define ACE_TDES_FIFO_ON (1 << 5) /* FIFO mode */ +#define ACE_TDES_SWAP_MASK (0xf << 6) +#define ACE_TDES_SWAPKEY_OFF (0 << 6) +#define ACE_TDES_SWAPKEY_ON (1 << 6) +#define ACE_TDES_SWAPIV_OFF (0 << 7) +#define ACE_TDES_SWAPIV_ON (1 << 7) +#define ACE_TDES_SWAPDO_OFF (0 << 8) +#define ACE_TDES_SWAPDO_ON (1 << 8) +#define ACE_TDES_SWAPDI_OFF (0 << 9) +#define ACE_TDES_SWAPDI_ON (1 << 9) + +/* TDES status */ +#define ACE_TDES_OUTRDY_MASK (1 << 0) +#define ACE_TDES_OUTRDY_OFF (0 << 0) +#define ACE_TDES_OUTRDY_ON (1 << 0) +#define ACE_TDES_INRDY_MASK (1 << 1) +#define ACE_TDES_INRDY_OFF (0 << 1) +#define ACE_TDES_INRDY_ON (1 << 1) +#define ACE_TDES_BUSY_MASK (1 << 2) +#define ACE_TDES_BUSY_OFF (0 << 2) +#define ACE_TDES_BUSY_ON (1 << 2) + +/* Hash control */ +#define ACE_HASH_ENGSEL_MASK (0xf << 0) +#define ACE_HASH_ENGSEL_SHA1HASH (0x0 << 0) +#define ACE_HASH_ENGSEL_SHA1HMAC (0x1 << 0) +#define ACE_HASH_ENGSEL_SHA1HMACIN (0x1 << 0) +#define ACE_HASH_ENGSEL_SHA1HMACOUT (0x9 << 0) +#define ACE_HASH_ENGSEL_MD5HASH (0x2 << 0) +#define ACE_HASH_ENGSEL_MD5HMAC (0x3 << 0) +#define ACE_HASH_ENGSEL_MD5HMACIN (0x3 << 0) +#define ACE_HASH_ENGSEL_MD5HMACOUT (0xb << 0) +#define ACE_HASH_ENGSEL_SHA256HASH (0x4 << 0) +#define ACE_HASH_ENGSEL_SHA256HMAC (0x5 << 0) +#define ACE_HASH_ENGSEL_PRNG (0x8 << 0) +#define ACE_HASH_STARTBIT_ON (1 << 4) +#define ACE_HASH_USERIV_EN (1 << 5) +#define ACE_HASH_PAUSE_ON (1 << 0) + +/* Hash control - FIFO mode */ +#define ACE_HASH_FIFO_MASK (1 << 0) +#define ACE_HASH_FIFO_OFF (0 << 0) +#define ACE_HASH_FIFO_ON (1 << 0) + +/* Hash control - byte swap */ +#define ACE_HASH_SWAP_MASK (0xf << 0) +#define ACE_HASH_SWAPKEY_OFF (0 << 0) +#define ACE_HASH_SWAPKEY_ON (1 << 0) +#define ACE_HASH_SWAPIV_OFF (0 << 1) +#define ACE_HASH_SWAPIV_ON (1 << 1) +#define ACE_HASH_SWAPDO_OFF (0 << 2) +#define ACE_HASH_SWAPDO_ON (1 << 2) +#define ACE_HASH_SWAPDI_OFF (0 << 3) +#define ACE_HASH_SWAPDI_ON (1 << 3) + +/* Hash status */ +#define ACE_HASH_BUFRDY_MASK (1 << 0) +#define ACE_HASH_BUFRDY_OFF (0 << 0) +#define ACE_HASH_BUFRDY_ON (1 << 0) +#define ACE_HASH_SEEDSETTING_MASK (1 << 1) +#define ACE_HASH_SEEDSETTING_OFF (0 << 1) +#define ACE_HASH_SEEDSETTING_ON (1 << 1) +#define ACE_HASH_PRNGBUSY_MASK (1 << 2) +#define ACE_HASH_PRNGBUSY_OFF (0 << 2) +#define ACE_HASH_PRNGBUSY_ON (1 << 2) +#define ACE_HASH_PARTIALDONE_MASK (1 << 4) +#define ACE_HASH_PARTIALDONE_OFF (0 << 4) +#define ACE_HASH_PARTIALDONE_ON (1 << 4) +#define ACE_HASH_PRNGDONE_MASK (1 << 5) +#define ACE_HASH_PRNGDONE_OFF (0 << 5) +#define ACE_HASH_PRNGDONE_ON (1 << 5) +#define ACE_HASH_MSGDONE_MASK (1 << 6) +#define ACE_HASH_MSGDONE_OFF (0 << 6) +#define ACE_HASH_MSGDONE_ON (1 << 6) +#define ACE_HASH_PRNGERROR_MASK (1 << 7) +#define ACE_HASH_PRNGERROR_OFF (0 << 7) +#define ACE_HASH_PRNGERROR_ON (1 << 7) + +#define ACE_SHA_TYPE_SHA1 1 +#define ACE_SHA_TYPE_SHA256 2 + +/** + * Computes hash value of input pbuf using ACE + * + * @param in_addr A pointer to the input buffer + * @param bufleni Byte length of input buffer + * @param out_addr A pointer to the output buffer. When complete + * 32 bytes are copied to pout[0]...pout[31]. Thus, a user + * should allocate at least 32 bytes at pOut in advance. + * @param hash_type SHA1 or SHA256 + * + * @return 0 on Success, -1 on Failure (Timeout) + */ +int ace_sha_hash_digest(const uchar * in_addr, uint buflen, + uchar * out_addr, uint hash_type); +#endif diff --git a/drivers/dfu/Makefile b/drivers/dfu/Makefile index 7b717bc..153095d 100644 --- a/drivers/dfu/Makefile +++ b/drivers/dfu/Makefile @@ -27,6 +27,7 @@ LIB = $(obj)libdfu.o COBJS-$(CONFIG_DFU_FUNCTION) += dfu.o COBJS-$(CONFIG_DFU_MMC) += dfu_mmc.o +COBJS-$(CONFIG_DFU_NAND) += dfu_nand.o SRCS := $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index e8477fb..6af6890 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -44,90 +44,232 @@ static int dfu_find_alt_num(const char *s) static unsigned char __aligned(CONFIG_SYS_CACHELINE_SIZE) dfu_buf[DFU_DATA_BUF_SIZE]; +static int dfu_write_buffer_drain(struct dfu_entity *dfu) +{ + long w_size; + int ret; + + /* flush size? */ + w_size = dfu->i_buf - dfu->i_buf_start; + if (w_size == 0) + return 0; + + /* update CRC32 */ + dfu->crc = crc32(dfu->crc, dfu->i_buf_start, w_size); + + ret = dfu->write_medium(dfu, dfu->offset, dfu->i_buf_start, &w_size); + if (ret) + debug("%s: Write error!\n", __func__); + + /* point back */ + dfu->i_buf = dfu->i_buf_start; + + /* update offset */ + dfu->offset += w_size; + + puts("#"); + + return ret; +} + int dfu_write(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) { - static unsigned char *i_buf; - static int i_blk_seq_num; - long w_size = 0; int ret = 0; + int tret; + + debug("%s: name: %s buf: 0x%p size: 0x%x p_num: 0x%x offset: 0x%llx bufoffset: 0x%x\n", + __func__, dfu->name, buf, size, blk_seq_num, dfu->offset, + dfu->i_buf - dfu->i_buf_start); + + if (!dfu->inited) { + /* initial state */ + dfu->crc = 0; + dfu->offset = 0; + dfu->bad_skip = 0; + dfu->i_blk_seq_num = 0; + dfu->i_buf_start = dfu_buf; + dfu->i_buf_end = dfu_buf + sizeof(dfu_buf); + dfu->i_buf = dfu->i_buf_start; + + dfu->inited = 1; + } - debug("%s: name: %s buf: 0x%p size: 0x%x p_num: 0x%x i_buf: 0x%p\n", - __func__, dfu->name, buf, size, blk_seq_num, i_buf); + if (dfu->i_blk_seq_num != blk_seq_num) { + printf("%s: Wrong sequence number! [%d] [%d]\n", + __func__, dfu->i_blk_seq_num, blk_seq_num); + return -1; + } - if (blk_seq_num == 0) { - i_buf = dfu_buf; - i_blk_seq_num = 0; + /* DFU 1.1 standard says: + * The wBlockNum field is a block sequence number. It increments each + * time a block is transferred, wrapping to zero from 65,535. It is used + * to provide useful context to the DFU loader in the device." + * + * This means that it's a 16 bit counter that roll-overs at + * 0xffff -> 0x0000. By having a typical 4K transfer block + * we roll-over at exactly 256MB. Not very fun to debug. + * + * Handling rollover, and having an inited variable, + * makes things work. + */ + + /* handle rollover */ + dfu->i_blk_seq_num = (dfu->i_blk_seq_num + 1) & 0xffff; + + /* flush buffer if overflow */ + if ((dfu->i_buf + size) > dfu->i_buf_end) { + tret = dfu_write_buffer_drain(dfu); + if (ret == 0) + ret = tret; } - if (i_blk_seq_num++ != blk_seq_num) { - printf("%s: Wrong sequence number! [%d] [%d]\n", - __func__, i_blk_seq_num, blk_seq_num); + /* we should be in buffer now (if not then size too large) */ + if ((dfu->i_buf + size) > dfu->i_buf_end) { + printf("%s: Wrong size! [%d] [%d] - %d\n", + __func__, dfu->i_blk_seq_num, blk_seq_num, size); return -1; } - memcpy(i_buf, buf, size); - i_buf += size; + memcpy(dfu->i_buf, buf, size); + dfu->i_buf += size; + /* if end or if buffer full flush */ + if (size == 0 || (dfu->i_buf + size) > dfu->i_buf_end) { + tret = dfu_write_buffer_drain(dfu); + if (ret == 0) + ret = tret; + } + + /* end? */ if (size == 0) { - /* Integrity check (if needed) */ - debug("%s: %s %d [B] CRC32: 0x%x\n", __func__, dfu->name, - i_buf - dfu_buf, crc32(0, dfu_buf, i_buf - dfu_buf)); + /* Now try and flush to the medium if needed. */ + if (dfu->flush_medium) + ret = dfu->flush_medium(dfu); + printf("\nDFU complete CRC32: 0x%08x\n", dfu->crc); - w_size = i_buf - dfu_buf; - ret = dfu->write_medium(dfu, dfu_buf, &w_size); - if (ret) - debug("%s: Write error!\n", __func__); + /* clear everything */ + dfu->crc = 0; + dfu->offset = 0; + dfu->i_blk_seq_num = 0; + dfu->i_buf_start = dfu_buf; + dfu->i_buf_end = dfu_buf + sizeof(dfu_buf); + dfu->i_buf = dfu->i_buf_start; + + dfu->inited = 0; - i_blk_seq_num = 0; - i_buf = NULL; - return ret; } - return ret; + return ret = 0 ? size : ret; +} + +static int dfu_read_buffer_fill(struct dfu_entity *dfu, void *buf, int size) +{ + long chunk; + int ret, readn; + + readn = 0; + while (size > 0) { + /* get chunk that can be read */ + chunk = min(size, dfu->b_left); + /* consume */ + if (chunk > 0) { + memcpy(buf, dfu->i_buf, chunk); + dfu->crc = crc32(dfu->crc, buf, chunk); + dfu->i_buf += chunk; + dfu->b_left -= chunk; + size -= chunk; + buf += chunk; + readn += chunk; + } + + /* all done */ + if (size > 0) { + /* no more to read */ + if (dfu->r_left == 0) + break; + + dfu->i_buf = dfu->i_buf_start; + dfu->b_left = dfu->i_buf_end - dfu->i_buf_start; + + /* got to read, but buffer is empty */ + if (dfu->b_left > dfu->r_left) + dfu->b_left = dfu->r_left; + ret = dfu->read_medium(dfu, dfu->offset, dfu->i_buf, + &dfu->b_left); + if (ret != 0) { + debug("%s: Read error!\n", __func__); + return ret; + } + dfu->offset += dfu->b_left; + dfu->r_left -= dfu->b_left; + + puts("#"); + } + } + + return readn; } int dfu_read(struct dfu_entity *dfu, void *buf, int size, int blk_seq_num) { - static unsigned char *i_buf; - static int i_blk_seq_num; - static long r_size; - static u32 crc; int ret = 0; debug("%s: name: %s buf: 0x%p size: 0x%x p_num: 0x%x i_buf: 0x%p\n", - __func__, dfu->name, buf, size, blk_seq_num, i_buf); + __func__, dfu->name, buf, size, blk_seq_num, dfu->i_buf); + + if (!dfu->inited) { + ret = dfu->read_medium(dfu, 0, buf, &dfu->r_left); + if (ret != 0) { + debug("%s: failed to get r_left\n", __func__); + return ret; + } + + debug("%s: %s %ld [B]\n", __func__, dfu->name, dfu->r_left); + + dfu->i_blk_seq_num = 0; + dfu->crc = 0; + dfu->offset = 0; + dfu->i_buf_start = dfu_buf; + dfu->i_buf_end = dfu_buf + sizeof(dfu_buf); + dfu->i_buf = dfu->i_buf_start; + dfu->b_left = 0; - if (blk_seq_num == 0) { - i_buf = dfu_buf; - ret = dfu->read_medium(dfu, i_buf, &r_size); - debug("%s: %s %ld [B]\n", __func__, dfu->name, r_size); - i_blk_seq_num = 0; - /* Integrity check (if needed) */ - crc = crc32(0, dfu_buf, r_size); + dfu->bad_skip = 0; + + dfu->inited = 1; } - if (i_blk_seq_num++ != blk_seq_num) { + if (dfu->i_blk_seq_num != blk_seq_num) { printf("%s: Wrong sequence number! [%d] [%d]\n", - __func__, i_blk_seq_num, blk_seq_num); + __func__, dfu->i_blk_seq_num, blk_seq_num); return -1; } + /* handle rollover */ + dfu->i_blk_seq_num = (dfu->i_blk_seq_num + 1) & 0xffff; - if (r_size >= size) { - memcpy(buf, i_buf, size); - i_buf += size; - r_size -= size; - return size; - } else { - memcpy(buf, i_buf, r_size); - i_buf += r_size; - debug("%s: %s CRC32: 0x%x\n", __func__, dfu->name, crc); - puts("UPLOAD ... done\nCtrl+C to exit ...\n"); + ret = dfu_read_buffer_fill(dfu, buf, size); + if (ret < 0) { + printf("%s: Failed to fill buffer\n", __func__); + return -1; + } + + if (ret < size) { + debug("%s: %s CRC32: 0x%x\n", __func__, dfu->name, dfu->crc); + puts("\nUPLOAD ... done\nCtrl+C to exit ...\n"); - i_buf = NULL; - i_blk_seq_num = 0; - crc = 0; - return r_size; + dfu->i_blk_seq_num = 0; + dfu->crc = 0; + dfu->offset = 0; + dfu->i_buf_start = dfu_buf; + dfu->i_buf_end = dfu_buf + sizeof(dfu_buf); + dfu->i_buf = dfu->i_buf_start; + dfu->b_left = 0; + + dfu->bad_skip = 0; + + dfu->inited = 0; } + return ret; } @@ -147,6 +289,9 @@ static int dfu_fill_entity(struct dfu_entity *dfu, char *s, int alt, if (strcmp(interface, "mmc") == 0) { if (dfu_fill_entity_mmc(dfu, s)) return -1; + } else if (strcmp(interface, "nand") == 0) { + if (dfu_fill_entity_nand(dfu, s)) + return -1; } else { printf("%s: Device %s not (yet) supported!\n", __func__, interface); diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 5d504df..e2f3978 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -21,6 +21,8 @@ #include <common.h> #include <malloc.h> +#include <errno.h> +#include <div64.h> #include <dfu.h> enum dfu_mmc_op { @@ -28,32 +30,51 @@ enum dfu_mmc_op { DFU_OP_WRITE, }; +static unsigned char __aligned(CONFIG_SYS_CACHELINE_SIZE) + dfu_file_buf[CONFIG_SYS_DFU_MAX_FILE_SIZE]; +static long dfu_file_buf_len; + static int mmc_block_op(enum dfu_mmc_op op, struct dfu_entity *dfu, - void *buf, long *len) + u64 offset, void *buf, long *len) { char cmd_buf[DFU_CMD_BUF_SIZE]; + u32 blk_start, blk_count; + + /* + * We must ensure that we work in lba_blk_size chunks, so ALIGN + * this value. + */ + *len = ALIGN(*len, dfu->data.mmc.lba_blk_size); + + blk_start = dfu->data.mmc.lba_start + + (u32)lldiv(offset, dfu->data.mmc.lba_blk_size); + blk_count = *len / dfu->data.mmc.lba_blk_size; + if (blk_start + blk_count > + dfu->data.mmc.lba_start + dfu->data.mmc.lba_size) { + puts("Request would exceed designated area!\n"); + return -EINVAL; + } - sprintf(cmd_buf, "mmc %s 0x%x %x %x", + sprintf(cmd_buf, "mmc %s %p %x %x", op == DFU_OP_READ ? "read" : "write", - (unsigned int) buf, - dfu->data.mmc.lba_start, - dfu->data.mmc.lba_size); - - if (op == DFU_OP_READ) - *len = dfu->data.mmc.lba_blk_size * dfu->data.mmc.lba_size; + buf, blk_start, blk_count); debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf); return run_command(cmd_buf, 0); } -static inline int mmc_block_write(struct dfu_entity *dfu, void *buf, long *len) +static int mmc_file_buffer(struct dfu_entity *dfu, void *buf, long *len) { - return mmc_block_op(DFU_OP_WRITE, dfu, buf, len); -} + if (dfu_file_buf_len + *len > CONFIG_SYS_DFU_MAX_FILE_SIZE) { + dfu_file_buf_len = 0; + return -EINVAL; + } -static inline int mmc_block_read(struct dfu_entity *dfu, void *buf, long *len) -{ - return mmc_block_op(DFU_OP_READ, dfu, buf, len); + /* Add to the current buffer. */ + memcpy(dfu_file_buf + dfu_file_buf_len, buf, *len); + dfu_file_buf_len += *len; + + return 0; } static int mmc_file_op(enum dfu_mmc_op op, struct dfu_entity *dfu, @@ -65,20 +86,23 @@ static int mmc_file_op(enum dfu_mmc_op op, struct dfu_entity *dfu, switch (dfu->layout) { case DFU_FS_FAT: - sprintf(cmd_buf, "fat%s mmc %d:%d 0x%x %s %lx", + sprintf(cmd_buf, "fat%s mmc %d:%d 0x%x %s", op == DFU_OP_READ ? "load" : "write", dfu->data.mmc.dev, dfu->data.mmc.part, - (unsigned int) buf, dfu->name, *len); + (unsigned int) buf, dfu->name); + if (op == DFU_OP_WRITE) + sprintf(cmd_buf + strlen(cmd_buf), " %lx", *len); break; case DFU_FS_EXT4: - sprintf(cmd_buf, "ext4%s mmc %d:%d /%s 0x%x %ld", + sprintf(cmd_buf, "ext4%s mmc %d:%d 0x%x /%s", op == DFU_OP_READ ? "load" : "write", dfu->data.mmc.dev, dfu->data.mmc.part, - dfu->name, (unsigned int) buf, *len); + (unsigned int) buf, dfu->name); break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, dfu_get_layout(dfu->layout)); + return -1; } debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf); @@ -101,27 +125,18 @@ static int mmc_file_op(enum dfu_mmc_op op, struct dfu_entity *dfu, return ret; } -static inline int mmc_file_write(struct dfu_entity *dfu, void *buf, long *len) -{ - return mmc_file_op(DFU_OP_WRITE, dfu, buf, len); -} - -static inline int mmc_file_read(struct dfu_entity *dfu, void *buf, long *len) -{ - return mmc_file_op(DFU_OP_READ, dfu, buf, len); -} - -int dfu_write_medium_mmc(struct dfu_entity *dfu, void *buf, long *len) +int dfu_write_medium_mmc(struct dfu_entity *dfu, + u64 offset, void *buf, long *len) { int ret = -1; switch (dfu->layout) { case DFU_RAW_ADDR: - ret = mmc_block_write(dfu, buf, len); + ret = mmc_block_op(DFU_OP_WRITE, dfu, offset, buf, len); break; case DFU_FS_FAT: case DFU_FS_EXT4: - ret = mmc_file_write(dfu, buf, len); + ret = mmc_file_buffer(dfu, buf, len); break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, @@ -131,17 +146,34 @@ int dfu_write_medium_mmc(struct dfu_entity *dfu, void *buf, long *len) return ret; } -int dfu_read_medium_mmc(struct dfu_entity *dfu, void *buf, long *len) +int dfu_flush_medium_mmc(struct dfu_entity *dfu) +{ + int ret = 0; + + if (dfu->layout != DFU_RAW_ADDR) { + /* Do stuff here. */ + ret = mmc_file_op(DFU_OP_WRITE, dfu, &dfu_file_buf, + &dfu_file_buf_len); + + /* Now that we're done */ + dfu_file_buf_len = 0; + } + + return ret; +} + +int dfu_read_medium_mmc(struct dfu_entity *dfu, u64 offset, void *buf, + long *len) { int ret = -1; switch (dfu->layout) { case DFU_RAW_ADDR: - ret = mmc_block_read(dfu, buf, len); + ret = mmc_block_op(DFU_OP_READ, dfu, offset, buf, len); break; case DFU_FS_FAT: case DFU_FS_EXT4: - ret = mmc_file_read(dfu, buf, len); + ret = mmc_file_op(DFU_OP_READ, dfu, buf, len); break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, @@ -153,6 +185,10 @@ int dfu_read_medium_mmc(struct dfu_entity *dfu, void *buf, long *len) int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) { + int dev, part; + struct mmc *mmc; + block_dev_desc_t *blk_dev; + disk_partition_t partinfo; char *st; dfu->dev_type = DFU_DEV_MMC; @@ -166,8 +202,35 @@ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) dfu->layout = DFU_FS_FAT; } else if (!strcmp(st, "ext4")) { dfu->layout = DFU_FS_EXT4; + } else if (!strcmp(st, "part")) { + + dfu->layout = DFU_RAW_ADDR; + + dev = simple_strtoul(s, &s, 10); + s++; + part = simple_strtoul(s, &s, 10); + + mmc = find_mmc_device(dev); + if (mmc == NULL || mmc_init(mmc)) { + printf("%s: could not find mmc device #%d!\n", + __func__, dev); + return -ENODEV; + } + + blk_dev = &mmc->block_dev; + if (get_partition_info(blk_dev, part, &partinfo) != 0) { + printf("%s: could not find partition #%d on mmc device #%d!\n", + __func__, part, dev); + return -ENODEV; + } + + dfu->data.mmc.lba_start = partinfo.start; + dfu->data.mmc.lba_size = partinfo.size; + dfu->data.mmc.lba_blk_size = partinfo.blksz; + } else { printf("%s: Memory layout (%s) not supported!\n", __func__, st); + return -ENODEV; } if (dfu->layout == DFU_FS_EXT4 || dfu->layout == DFU_FS_FAT) { @@ -177,6 +240,10 @@ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) dfu->read_medium = dfu_read_medium_mmc; dfu->write_medium = dfu_write_medium_mmc; + dfu->flush_medium = dfu_flush_medium_mmc; + + /* initial state */ + dfu->inited = 0; return 0; } diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c new file mode 100644 index 0000000..7dc89b2 --- /dev/null +++ b/drivers/dfu/dfu_nand.c @@ -0,0 +1,187 @@ +/* + * dfu_nand.c -- DFU for NAND routines. + * + * Copyright (C) 2012-2013 Texas Instruments, Inc. + * + * Based on dfu_mmc.c which is: + * Copyright (C) 2012 Samsung Electronics + * author: Lukasz Majewski <l.majewski@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <errno.h> +#include <div64.h> +#include <dfu.h> +#include <linux/mtd/mtd.h> +#include <jffs2/load_kernel.h> +#include <nand.h> + +enum dfu_nand_op { + DFU_OP_READ = 1, + DFU_OP_WRITE, +}; + +static int nand_block_op(enum dfu_nand_op op, struct dfu_entity *dfu, + u64 offset, void *buf, long *len) +{ + loff_t start, lim; + size_t count, actual; + int ret; + nand_info_t *nand; + + /* if buf == NULL return total size of the area */ + if (buf == NULL) { + *len = dfu->data.nand.size; + return 0; + } + + start = dfu->data.nand.start + offset + dfu->bad_skip; + lim = dfu->data.nand.start + dfu->data.nand.size - start; + count = *len; + + if (nand_curr_device < 0 || + nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || + !nand_info[nand_curr_device].name) { + printf("%s: invalid nand device\n", __func__); + return -1; + } + + nand = &nand_info[nand_curr_device]; + + if (op == DFU_OP_READ) + ret = nand_read_skip_bad(nand, start, &count, &actual, + lim, buf); + else + ret = nand_write_skip_bad(nand, start, &count, &actual, + lim, buf, 0); + + if (ret != 0) { + printf("%s: nand_%s_skip_bad call failed at %llx!\n", + __func__, op == DFU_OP_READ ? "read" : "write", + start); + return ret; + } + + /* + * Find out where we stopped writing data. This can be deeper into + * the NAND than we expected due to having to skip bad blocks. So + * we must take this into account for the next write, if any. + */ + if (actual > count) + dfu->bad_skip += actual - count; + + return ret; +} + +static inline int nand_block_write(struct dfu_entity *dfu, + u64 offset, void *buf, long *len) +{ + return nand_block_op(DFU_OP_WRITE, dfu, offset, buf, len); +} + +static inline int nand_block_read(struct dfu_entity *dfu, + u64 offset, void *buf, long *len) +{ + return nand_block_op(DFU_OP_READ, dfu, offset, buf, len); +} + +static int dfu_write_medium_nand(struct dfu_entity *dfu, + u64 offset, void *buf, long *len) +{ + int ret = -1; + + switch (dfu->layout) { + case DFU_RAW_ADDR: + ret = nand_block_write(dfu, offset, buf, len); + break; + default: + printf("%s: Layout (%s) not (yet) supported!\n", __func__, + dfu_get_layout(dfu->layout)); + } + + return ret; +} + +static int dfu_read_medium_nand(struct dfu_entity *dfu, u64 offset, void *buf, + long *len) +{ + int ret = -1; + + switch (dfu->layout) { + case DFU_RAW_ADDR: + ret = nand_block_read(dfu, offset, buf, len); + break; + default: + printf("%s: Layout (%s) not (yet) supported!\n", __func__, + dfu_get_layout(dfu->layout)); + } + + return ret; +} + +int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s) +{ + char *st; + int ret, dev, part; + + dfu->dev_type = DFU_DEV_NAND; + st = strsep(&s, " "); + if (!strcmp(st, "raw")) { + dfu->layout = DFU_RAW_ADDR; + dfu->data.nand.start = simple_strtoul(s, &s, 16); + s++; + dfu->data.nand.size = simple_strtoul(s, &s, 16); + } else if (!strcmp(st, "part")) { + char mtd_id[32]; + struct mtd_device *mtd_dev; + u8 part_num; + struct part_info *pi; + + dfu->layout = DFU_RAW_ADDR; + + dev = simple_strtoul(s, &s, 10); + s++; + part = simple_strtoul(s, &s, 10); + + sprintf(mtd_id, "%s%d,%d", "nand", dev, part - 1); + printf("using id '%s'\n", mtd_id); + + mtdparts_init(); + + ret = find_dev_and_part(mtd_id, &mtd_dev, &part_num, &pi); + if (ret != 0) { + printf("Could not locate '%s'\n", mtd_id); + return -1; + } + + dfu->data.nand.start = pi->offset; + dfu->data.nand.size = pi->size; + + } else { + printf("%s: Memory layout (%s) not supported!\n", __func__, st); + return -1; + } + + dfu->read_medium = dfu_read_medium_nand; + dfu->write_medium = dfu_write_medium_nand; + + /* initial state */ + dfu->inited = 0; + + return 0; +} diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index 4703fc1..0ae78f9 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -140,7 +140,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) } /* Establish the initial state */ - (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */ + (*fn->config) (true, true, cookie); /* Assert nCONFIG */ udelay(2); /* T_cfg > 2us */ @@ -152,7 +152,7 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) return FPGA_FAIL; } - (*fn->config) (FALSE, TRUE, cookie); /* Deassert nCONFIG */ + (*fn->config) (false, true, cookie); /* Deassert nCONFIG */ udelay(2); /* T_cf2st1 < 4us */ /* Wait for nSTATUS to be released (i.e. deasserted) */ @@ -192,13 +192,13 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) i = 8; do { /* Deassert the clock */ - (*fn->clk) (FALSE, TRUE, cookie); + (*fn->clk) (false, true, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->data) ( (val & 0x01), TRUE, cookie); + (*fn->data) ((val & 0x01), true, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->clk) (true, true, cookie); CONFIG_FPGA_DELAY (); val >>= 1; i --; @@ -232,9 +232,9 @@ static int ACEX1K_ps_load(Altera_desc *desc, const void *buf, size_t bsize) for (i = 0; i < 12; i++) { CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ } ret_val = FPGA_SUCCESS; diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index f087d01..8388da5 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -215,7 +215,7 @@ int altera_info( Altera_desc *desc ) static int altera_validate (Altera_desc * desc, const char *fn) { - int ret_val = FALSE; + int ret_val = false; if (desc) { if ((desc->family > min_altera_type) && @@ -223,7 +223,7 @@ static int altera_validate (Altera_desc * desc, const char *fn) if ((desc->iface > min_altera_iface_type) && (desc->iface < max_altera_iface_type)) { if (desc->size) { - ret_val = TRUE; + ret_val = true; } else { printf ("%s: NULL part size\n", fn); } diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 0773e73..6b734c2 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -144,9 +144,9 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) } /* Establish the initial state */ - (*fn->config) (FALSE, TRUE, cookie); /* De-assert nCONFIG */ + (*fn->config) (false, true, cookie); /* De-assert nCONFIG */ udelay(100); - (*fn->config) (TRUE, TRUE, cookie); /* Assert nCONFIG */ + (*fn->config) (true, true, cookie); /* Assert nCONFIG */ udelay(2); /* T_cfg > 2us */ @@ -164,7 +164,7 @@ static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize) /* Get ready for the burn */ CONFIG_FPGA_DELAY (); - ret = (*fn->write) (buf, bsize, TRUE, cookie); + ret = (*fn->write) (buf, bsize, true, cookie); if (ret) { puts ("** Write failed.\n"); (*fn->abort) (cookie); diff --git a/drivers/fpga/lattice.c b/drivers/fpga/lattice.c index d8b642a..8c3465a 100644 --- a/drivers/fpga/lattice.c +++ b/drivers/fpga/lattice.c @@ -275,7 +275,7 @@ signed char ispVM(void) static int lattice_validate(Lattice_desc *desc, const char *fn) { - int ret_val = FALSE; + int ret_val = false; if (desc) { if ((desc->family > min_lattice_type) && @@ -283,7 +283,7 @@ static int lattice_validate(Lattice_desc *desc, const char *fn) if ((desc->iface > min_lattice_iface_type) && (desc->iface < max_lattice_iface_type)) { if (desc->size) { - ret_val = TRUE; + ret_val = true; } else { printf("%s: NULL part size\n", fn); } diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 4bc7070..0bc400d 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -162,11 +162,11 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) } /* Establish the initial state */ - (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */ + (*fn->pgm) (true, true, cookie); /* Assert the program, commit */ /* Get ready for the burn */ CONFIG_FPGA_DELAY (); - (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */ + (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */ ts = get_timer (0); /* get current time */ /* Now wait for INIT and BUSY to go high */ @@ -179,20 +179,20 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) } } while ((*fn->init) (cookie) && (*fn->busy) (cookie)); - (*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */ - (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->wr) (true, true, cookie); /* Assert write, commit */ + (*fn->cs) (true, true, cookie); /* Assert chip select, commit */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ /* Load the data */ while (bytecount < bsize) { /* XXX - do we check for an Ctrl-C press in here ??? */ /* XXX - Check the error bit? */ - (*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */ + (*fn->wdata) (data[bytecount++], true, cookie); /* write the data */ CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ #ifdef CONFIG_SYS_FPGA_CHECK_BUSY ts = get_timer (0); /* get current time */ @@ -201,9 +201,9 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) * make sure we aren't busy forever... */ CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for BUSY to clear.\n"); @@ -220,8 +220,8 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) } CONFIG_FPGA_DELAY (); - (*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */ - (*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */ + (*fn->cs) (false, true, cookie); /* Deassert the chip select */ + (*fn->wr) (false, true, cookie); /* Deassert the write pin */ #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc ('\n'); /* terminate the dotted line */ @@ -233,9 +233,9 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) while ((*fn->done) (cookie) == FPGA_FAIL) { CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); @@ -277,15 +277,15 @@ static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) printf ("Starting Dump of FPGA Device %d...\n", cookie); - (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->cs) (true, true, cookie); /* Assert chip select, commit */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ /* dump the data */ while (bytecount < bsize) { /* XXX - do we check for an Ctrl-C press in here ??? */ - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */ #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK if (bytecount % (bsize / 40) == 0) @@ -293,9 +293,9 @@ static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) #endif } - (*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */ - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->cs) (false, false, cookie); /* Deassert the chip select */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc ('\n'); /* terminate the dotted line */ @@ -351,7 +351,7 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) } /* Establish the initial state */ - (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */ + (*fn->pgm) (true, true, cookie); /* Assert the program, commit */ /* Wait for INIT state (init low) */ ts = get_timer (0); /* get current time */ @@ -365,7 +365,7 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* Get ready for the burn */ CONFIG_FPGA_DELAY (); - (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */ + (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */ ts = get_timer (0); /* get current time */ /* Now wait for INIT to go high */ @@ -390,13 +390,13 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) i = 8; do { /* Deassert the clock */ - (*fn->clk) (FALSE, TRUE, cookie); + (*fn->clk) (false, true, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->wr) ((val & 0x80), TRUE, cookie); + (*fn->wr) ((val & 0x80), true, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->clk) (true, true, cookie); CONFIG_FPGA_DELAY (); val <<= 1; i --; @@ -417,14 +417,14 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* now check for done signal */ ts = get_timer (0); /* get current time */ ret_val = FPGA_SUCCESS; - (*fn->wr) (TRUE, TRUE, cookie); + (*fn->wr) (true, true, cookie); while (! (*fn->done) (cookie)) { CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ putc ('*'); diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 1633a70..c63c605 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -166,11 +166,11 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) } /* Establish the initial state */ - (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */ + (*fn->pgm) (true, true, cookie); /* Assert the program, commit */ /* Get ready for the burn */ CONFIG_FPGA_DELAY (); - (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */ + (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */ ts = get_timer (0); /* get current time */ /* Now wait for INIT and BUSY to go high */ @@ -183,20 +183,20 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) } } while ((*fn->init) (cookie) && (*fn->busy) (cookie)); - (*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */ - (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->wr) (true, true, cookie); /* Assert write, commit */ + (*fn->cs) (true, true, cookie); /* Assert chip select, commit */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ /* Load the data */ while (bytecount < bsize) { /* XXX - do we check for an Ctrl-C press in here ??? */ /* XXX - Check the error bit? */ - (*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */ + (*fn->wdata) (data[bytecount++], true, cookie); /* write the data */ CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ #ifdef CONFIG_SYS_FPGA_CHECK_BUSY ts = get_timer (0); /* get current time */ @@ -205,9 +205,9 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) * make sure we aren't busy forever... */ CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for BUSY to clear.\n"); @@ -224,8 +224,8 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) } CONFIG_FPGA_DELAY (); - (*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */ - (*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */ + (*fn->cs) (false, true, cookie); /* Deassert the chip select */ + (*fn->wr) (false, true, cookie); /* Deassert the write pin */ #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc ('\n'); /* terminate the dotted line */ @@ -239,9 +239,9 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) * make sure we aren't busy forever... */ CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */ puts ("** Timeout waiting for DONE to clear.\n"); @@ -283,15 +283,15 @@ static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) printf ("Starting Dump of FPGA Device %d...\n", cookie); - (*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->cs) (true, true, cookie); /* Assert chip select, commit */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ /* dump the data */ while (bytecount < bsize) { /* XXX - do we check for an Ctrl-C press in here ??? */ - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ (*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */ #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK if (bytecount % (bsize / 40) == 0) @@ -299,9 +299,9 @@ static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) #endif } - (*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */ - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->cs) (false, false, cookie); /* Deassert the chip select */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc ('\n'); /* terminate the dotted line */ @@ -357,7 +357,7 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) } /* Establish the initial state */ - (*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */ + (*fn->pgm) (true, true, cookie); /* Assert the program, commit */ /* Wait for INIT state (init low) */ ts = get_timer (0); /* get current time */ @@ -373,7 +373,7 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* Get ready for the burn */ CONFIG_FPGA_DELAY (); - (*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */ + (*fn->pgm) (false, true, cookie); /* Deassert the program, commit */ ts = get_timer (0); /* get current time */ /* Now wait for INIT to go high */ @@ -389,7 +389,7 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* Load the data */ if(*fn->bwr) - (*fn->bwr) (data, bsize, TRUE, cookie); + (*fn->bwr) (data, bsize, true, cookie); else { while (bytecount < bsize) { @@ -405,13 +405,13 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) i = 8; do { /* Deassert the clock */ - (*fn->clk) (FALSE, TRUE, cookie); + (*fn->clk) (false, true, cookie); CONFIG_FPGA_DELAY (); /* Write data */ - (*fn->wr) ((val & 0x80), TRUE, cookie); + (*fn->wr) ((val & 0x80), true, cookie); CONFIG_FPGA_DELAY (); /* Assert the clock */ - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->clk) (true, true, cookie); CONFIG_FPGA_DELAY (); val <<= 1; i --; @@ -433,16 +433,16 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* now check for done signal */ ts = get_timer (0); /* get current time */ ret_val = FPGA_SUCCESS; - (*fn->wr) (TRUE, TRUE, cookie); + (*fn->wr) (true, true, cookie); while (! (*fn->done) (cookie)) { /* XXX - we should have a check in here somewhere to * make sure we aren't busy forever... */ CONFIG_FPGA_DELAY (); - (*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */ + (*fn->clk) (false, true, cookie); /* Deassert the clock pin */ CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */ + (*fn->clk) (true, true, cookie); /* Assert the clock pin */ putc ('*'); diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index b26d231..3974e47 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -221,7 +221,7 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) * There is no maximum value for the pulse width. Check to make * sure that INIT_B goes low after assertion of PROG_B */ - (*fn->pgm) (TRUE, TRUE, cookie); + (*fn->pgm) (true, true, cookie); udelay (10); ts = get_timer (0); do { @@ -234,9 +234,9 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) } } while (!(*fn->init) (cookie)); - (*fn->pgm) (FALSE, TRUE, cookie); + (*fn->pgm) (false, true, cookie); CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->clk) (true, true, cookie); /* * Start a timer and wait for INIT_B to go high @@ -253,8 +253,8 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) } } while ((*fn->init) (cookie) && (*fn->busy) (cookie)); - (*fn->wr) (TRUE, TRUE, cookie); - (*fn->cs) (TRUE, TRUE, cookie); + (*fn->wr) (true, true, cookie); + (*fn->cs) (true, true, cookie); udelay (10000); @@ -286,15 +286,15 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) } #endif - (*fn->wdata) (data[bytecount++], TRUE, cookie); + (*fn->wdata) (data[bytecount++], true, cookie); CONFIG_FPGA_DELAY (); /* * Cycle the clock pin */ - (*fn->clk) (FALSE, TRUE, cookie); + (*fn->clk) (false, true, cookie); CONFIG_FPGA_DELAY (); - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->clk) (true, true, cookie); #ifdef CONFIG_SYS_FPGA_CHECK_BUSY ts = get_timer (0); @@ -319,8 +319,8 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) * Finished writing the data; deassert FPGA CS_B and WRITE_B signals. */ CONFIG_FPGA_DELAY (); - (*fn->cs) (FALSE, TRUE, cookie); - (*fn->wr) (FALSE, TRUE, cookie); + (*fn->cs) (false, true, cookie); + (*fn->wr) (false, true, cookie); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc ('\n'); @@ -381,8 +381,8 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) printf ("Starting Dump of FPGA Device %d...\n", cookie); - (*fn->cs) (TRUE, TRUE, cookie); - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->cs) (true, true, cookie); + (*fn->clk) (true, true, cookie); while (bytecount < bsize) { #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC @@ -394,8 +394,8 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* * Cycle the clock and read the data */ - (*fn->clk) (FALSE, TRUE, cookie); - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->clk) (false, true, cookie); + (*fn->clk) (true, true, cookie); (*fn->rdata) (&(data[bytecount++]), cookie); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK if (bytecount % (bsize / 40) == 0) @@ -406,9 +406,9 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* * Deassert CS_B and cycle the clock to deselect the device. */ - (*fn->cs) (FALSE, FALSE, cookie); - (*fn->clk) (FALSE, TRUE, cookie); - (*fn->clk) (TRUE, TRUE, cookie); + (*fn->cs) (false, false, cookie); + (*fn->clk) (false, true, cookie); + (*fn->clk) (true, true, cookie); #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK putc ('\n'); diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 4072cb4..32787b2 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -242,7 +242,7 @@ int xilinx_info (Xilinx_desc * desc) static int xilinx_validate (Xilinx_desc * desc, char *fn) { - int ret_val = FALSE; + int ret_val = false; if (desc) { if ((desc->family > min_xilinx_type) && @@ -250,7 +250,7 @@ static int xilinx_validate (Xilinx_desc * desc, char *fn) if ((desc->iface > min_xilinx_iface_type) && (desc->iface < max_xilinx_iface_type)) { if (desc->size) { - ret_val = TRUE; + ret_val = true; } else printf ("%s: NULL part size\n", fn); } else diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index 769a2ba..46d2506 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -86,13 +86,6 @@ static int GetI2CSDA(void) #endif } -#if 0 -static void SetI2CSDA(int x) -{ - rGPEDAT = (rGPEDAT & ~0x8000) | (x & 1) << 15; -} -#endif - static void SetI2CSCL(int x) { struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); @@ -331,7 +324,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, &i2c->iicstat); i = 0; - while ((i < data_len) && (result = I2C_OK)) { + while ((i < data_len) && (result == I2C_OK)) { result = WaitForXfer(i2c); writel(data[i], &i2c->iicds); ReadWriteByte(i2c); @@ -343,17 +336,16 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, result = WaitForXfer(i2c); /* send STOP */ - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); + writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); ReadWriteByte(i2c); break; case I2C_READ: if (addr && addr_len) { - writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); writel(chip, &i2c->iicds); /* send START */ - writel(readl(&i2c->iicstat) | I2C_START_STOP, - &i2c->iicstat); + writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, + &i2c->iicstat); result = WaitForXfer(i2c); if (IsACK(i2c)) { i = 0; @@ -387,11 +379,10 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, } } else { - writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); writel(chip, &i2c->iicds); /* send START */ - writel(readl(&i2c->iicstat) | I2C_START_STOP, - &i2c->iicstat); + writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, + &i2c->iicstat); result = WaitForXfer(i2c); if (IsACK(i2c)) { diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 65791aa..1d6faa2 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -43,6 +43,7 @@ COBJS-$(CONFIG_MXS_MMC) += mxsmmc.o COBJS-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o COBJS-$(CONFIG_SDHCI) += sdhci.o +COBJS-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o diff --git a/drivers/mmc/bcm2835_sdhci.c b/drivers/mmc/bcm2835_sdhci.c new file mode 100644 index 0000000..54cfabf --- /dev/null +++ b/drivers/mmc/bcm2835_sdhci.c @@ -0,0 +1,190 @@ +/* + * This code was extracted from: + * git://github.com/gonzoua/u-boot-pi.git master + * and hence presumably (C) 2012 Oleksandr Tymoshenko + * + * Tweaks for U-Boot upstreaming + * (C) 2012 Stephen Warren + * + * Portions (e.g. read/write macros, concepts for back-to-back register write + * timing workarounds) obviously extracted from the Linux kernel at: + * https://github.com/raspberrypi/linux.git rpi-3.6.y + * + * The Linux kernel code has the following (c) and license, which is hence + * propagated to Oleksandr's tree and here: + * + * Support for SDHCI device on 2835 + * Based on sdhci-bcm2708.c (c) 2010 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* Supports: + * SDHCI platform device - Arasan SD controller in BCM2708 + * + * Inspired by sdhci-pci.c, by Pierre Ossman + */ + +#include <common.h> +#include <malloc.h> +#include <sdhci.h> +#include <asm/arch/timer.h> + +/* 400KHz is max freq for card ID etc. Use that as min */ +#define MIN_FREQ 400000 + +struct bcm2835_sdhci_host { + struct sdhci_host host; + uint twoticks_delay; + ulong last_write; +}; + +static inline struct bcm2835_sdhci_host *to_bcm(struct sdhci_host *host) +{ + return (struct bcm2835_sdhci_host *)host; +} + +static inline void bcm2835_sdhci_raw_writel(struct sdhci_host *host, u32 val, + int reg) +{ + struct bcm2835_sdhci_host *bcm_host = to_bcm(host); + + /* + * The Arasan has a bugette whereby it may lose the content of + * successive writes to registers that are within two SD-card clock + * cycles of each other (a clock domain crossing problem). + * It seems, however, that the data register does not have this problem. + * (Which is just as well - otherwise we'd have to nobble the DMA engine + * too) + */ + while (get_timer_us(bcm_host->last_write) < bcm_host->twoticks_delay) + ; + + writel(val, host->ioaddr + reg); + bcm_host->last_write = get_timer_us(0); +} + +static inline u32 bcm2835_sdhci_raw_readl(struct sdhci_host *host, int reg) +{ + return readl(host->ioaddr + reg); +} + +static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg) +{ + bcm2835_sdhci_raw_writel(host, val, reg); +} + +static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg) +{ + static u32 shadow; + u32 oldval = (reg == SDHCI_COMMAND) ? shadow : + bcm2835_sdhci_raw_readl(host, reg & ~3); + u32 word_num = (reg >> 1) & 1; + u32 word_shift = word_num * 16; + u32 mask = 0xffff << word_shift; + u32 newval = (oldval & ~mask) | (val << word_shift); + + if (reg == SDHCI_TRANSFER_MODE) + shadow = newval; + else + bcm2835_sdhci_raw_writel(host, newval, reg & ~3); +} + +static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) +{ + u32 oldval = bcm2835_sdhci_raw_readl(host, reg & ~3); + u32 byte_num = reg & 3; + u32 byte_shift = byte_num * 8; + u32 mask = 0xff << byte_shift; + u32 newval = (oldval & ~mask) | (val << byte_shift); + + bcm2835_sdhci_raw_writel(host, newval, reg & ~3); +} + +static u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg) +{ + u32 val = bcm2835_sdhci_raw_readl(host, reg); + + return val; +} + +static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg) +{ + u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3)); + u32 word_num = (reg >> 1) & 1; + u32 word_shift = word_num * 16; + u32 word = (val >> word_shift) & 0xffff; + + return word; +} + +static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg) +{ + u32 val = bcm2835_sdhci_raw_readl(host, (reg & ~3)); + u32 byte_num = reg & 3; + u32 byte_shift = byte_num * 8; + u32 byte = (val >> byte_shift) & 0xff; + + return byte; +} + +static const struct sdhci_ops bcm2835_ops = { + .write_l = bcm2835_sdhci_writel, + .write_w = bcm2835_sdhci_writew, + .write_b = bcm2835_sdhci_writeb, + .read_l = bcm2835_sdhci_readl, + .read_w = bcm2835_sdhci_readw, + .read_b = bcm2835_sdhci_readb, +}; + +int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq) +{ + struct bcm2835_sdhci_host *bcm_host; + struct sdhci_host *host; + + bcm_host = malloc(sizeof(*bcm_host)); + if (!bcm_host) { + printf("sdhci_host malloc fail!\n"); + return 1; + } + + /* + * See the comments in bcm2835_sdhci_raw_writel(). + * + * This should probably be dynamically calculated based on the actual + * frequency. However, this is the longest we'll have to wait, and + * doesn't seem to slow access down too much, so the added complexity + * doesn't seem worth it for now. + * + * 1/MIN_FREQ is (max) time per tick of eMMC clock. + * 2/MIN_FREQ is time for two ticks. + * Multiply by 1000000 to get uS per two ticks. + * +1 for hack rounding. + */ + bcm_host->twoticks_delay = ((2 * 1000000) / MIN_FREQ) + 1; + bcm_host->last_write = 0; + + host = &bcm_host->host; + host->name = "bcm2835_sdhci"; + host->ioaddr = (void *)regbase; + host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B | + SDHCI_QUIRK_WAIT_SEND_CMD; + host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; + host->ops = &bcm2835_ops; + + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + add_sdhci(host, emmc_freq, MIN_FREQ); + + return 0; +} diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 7b5fdd9..d732581 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -51,8 +51,12 @@ int mmc_getwp(struct mmc *mmc) wp = board_mmc_getwp(mmc); - if ((wp < 0) && mmc->getwp) - wp = mmc->getwp(mmc); + if (wp < 0) { + if (mmc->getwp) + wp = mmc->getwp(mmc); + else + wp = 0; + } return wp; } @@ -692,8 +696,12 @@ int mmc_getcd(struct mmc *mmc) cd = board_mmc_getcd(mmc); - if ((cd < 0) && mmc->getcd) - cd = mmc->getcd(mmc); + if (cd < 0) { + if (mmc->getcd) + cd = mmc->getcd(mmc); + else + cd = 1; + } return cd; } diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 67cfcc2..166744c 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -593,8 +593,6 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, mmc->send_cmd = mmc_send_cmd; mmc->set_ios = mmc_set_ios; mmc->init = mmc_init_setup; - mmc->getcd = omap_mmc_getcd; - mmc->getwp = omap_mmc_getwp; mmc->priv = priv_data; switch (dev_index) { @@ -616,7 +614,13 @@ int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, return 1; } priv_data->cd_gpio = omap_mmc_setup_gpio_in(cd_gpio, "mmc_cd"); + if (priv_data->cd_gpio != -1) + mmc->getcd = omap_mmc_getcd; + priv_data->wp_gpio = omap_mmc_setup_gpio_in(wp_gpio, "mmc_wp"); + if (priv_data->wp_gpio != -1) + mmc->getwp = omap_mmc_getwp; + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC) & ~host_caps_mask; diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index daca0ea..1eaea04 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -412,9 +412,11 @@ int sdhci_init(struct mmc *mmc) status = sdhci_readl(host, SDHCI_PRESENT_STATE); } - /* Eable all state */ - sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_ENABLE); - sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_SIGNAL_ENABLE); + /* Enable only interrupts served by the SD controller */ + sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK + , SDHCI_INT_ENABLE); + /* Mask all sdhci interrupt sources */ + sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE); return 0; } diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 60dbb78..cf10b0d 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -210,9 +210,11 @@ unsigned long flash_sector_size(flash_info_t *info, flash_sect_t sect) static inline void * flash_map (flash_info_t * info, flash_sect_t sect, uint offset) { - unsigned int byte_offset = offset * info->portwidth; + unsigned int byte_offset = offset * info->portwidth / info->chipwidth; + unsigned int addr = (info->start[sect] + byte_offset); + unsigned int mask = 0xffffffff << (info->portwidth - 1); - return (void *)(info->start[sect] + byte_offset); + return (void *)(uintptr_t)(addr & mask); } static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, @@ -398,6 +400,8 @@ void flash_write_cmd (flash_info_t * info, flash_sect_t sect, #endif flash_write64(cword.ll, addr); break; + default: + printf("fwc: Unknown port width %d\n", info->portwidth); } /* Ensure all the instructions are fully finished */ @@ -585,7 +589,6 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector, prompt, info->start[sector], flash_read_long (info, sector, 0)); flash_write_cmd (info, sector, 0, info->cmd_reset); - udelay(1); return ERR_TIMOUT; } udelay (1); /* also triggers watchdog */ @@ -753,12 +756,8 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) static flash_sect_t find_sector (flash_info_t * info, ulong addr) { static flash_sect_t saved_sector; /* previously found sector */ - static flash_info_t *saved_info; /* previously used flash bank */ flash_sect_t sector = saved_sector; - if ((info != saved_info) || (sector >= info->sector_count)) - sector = 0; - while ((info->start[sector] < addr) && (sector < info->sector_count - 1)) sector++; @@ -770,7 +769,6 @@ static flash_sect_t find_sector (flash_info_t * info, ulong addr) sector--; saved_sector = sector; - saved_info = info; return sector; } @@ -787,12 +785,15 @@ static int flash_write_cfiword (flash_info_t * info, ulong dest, /* Check if Flash is (sufficiently) erased */ switch (info->portwidth) { case FLASH_CFI_8BIT: + debug("%s: 8-bit 0x%02x\n", __func__, cword.c); flag = ((flash_read8(dstaddr) & cword.c) == cword.c); break; case FLASH_CFI_16BIT: + debug("%s: 16-bit 0x%04x\n", __func__, cword.w); flag = ((flash_read16(dstaddr) & cword.w) == cword.w); break; case FLASH_CFI_32BIT: + debug("%s: 32-bit 0x%08lx\n", __func__, cword.l); flag = ((flash_read32(dstaddr) & cword.l) == cword.l); break; case FLASH_CFI_64BIT: @@ -1053,6 +1054,8 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) flash_sect_t sect; int st; + debug("%s: erasing sectors %d to %d\n", __func__, s_first, s_last); + if (info->flash_id != FLASH_MAN_CFI) { puts ("Can't erase unknown flash type - aborted\n"); return 1; @@ -1162,6 +1165,9 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) rcode = 1; else if (flash_verbose) putc ('.'); + } else { + debug("\nSector %d is protected.\n", + info->protect[sect]); } } @@ -1857,7 +1863,7 @@ static void flash_read_cfi (flash_info_t *info, void *buf, unsigned int i; for (i = 0; i < len; i++) - p[i] = flash_read_uchar(info, start + i); + p[i] = flash_read_uchar(info, start + (i * 2)); } static void __flash_cmd_reset(flash_info_t *info) @@ -1878,21 +1884,40 @@ static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) { int cfi_offset; - /* Issue FLASH reset command */ - flash_cmd_reset(info); - for (cfi_offset=0; cfi_offset < sizeof(flash_offset_cfi) / sizeof(uint); cfi_offset++) { + /* Issue FLASH reset command */ + flash_cmd_reset(info); flash_write_cmd (info, 0, flash_offset_cfi[cfi_offset], FLASH_CMD_CFI); - if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') - && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') - && flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) { + if (flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP, 'Q') && + flash_isequal(info, 0, + FLASH_OFFSET_CFI_RESP + 2, 'R') && + flash_isequal(info, 0, + FLASH_OFFSET_CFI_RESP + 4, 'Y')) { flash_read_cfi(info, qry, FLASH_OFFSET_CFI_RESP, sizeof(struct cfi_qry)); +#ifdef CONFIG_SYS_FLASH_INTERFACE_WIDTH + info->interface = CONFIG_SYS_FLASH_INTERFACE_WIDTH; +#else info->interface = le16_to_cpu(qry->interface_desc); - + /* Some flash chips can support multiple bus widths. + * In this case, override the interface width and + * limit it to the port width. + */ + if ((info->interface == FLASH_CFI_X8X16) && + (info->portwidth == FLASH_CFI_8BIT)) { + debug("Overriding 16-bit interface" + " width to 8-bit port width.\n"); + info->interface = FLASH_CFI_X8; + } else if ((info->interface == FLASH_CFI_X16X32) && + (info->portwidth == FLASH_CFI_16BIT)) { + debug("Overriding 16-bit interface" + " width to 16-bit port width.\n"); + info->interface = FLASH_CFI_X16; + } +#endif info->cfi_offset = flash_offset_cfi[cfi_offset]; debug ("device interface is %d\n", info->interface); @@ -1903,8 +1928,8 @@ static int __flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) info->chipwidth << CFI_FLASH_SHIFT_WIDTH); /* calculate command offsets as in the Linux driver */ - info->addr_unlock1 = 0x555; - info->addr_unlock2 = 0x2aa; + info->addr_unlock1 = 0xaaa; + info->addr_unlock2 = 0x555; /* * modify the unlock address if we are @@ -1938,8 +1963,12 @@ static int flash_detect_cfi (flash_info_t * info, struct cfi_qry *qry) for (info->chipwidth = FLASH_CFI_BY8; info->chipwidth <= info->portwidth; info->chipwidth <<= 1) - if (__flash_detect_cfi(info, qry)) + if (__flash_detect_cfi(info, qry)) { + debug("Found CFI flash, portwidth %d," + " chipwidth %d\n", + info->portwidth, info->chipwidth); return 1; + } } debug ("not found\n"); return 0; @@ -1958,7 +1987,7 @@ static void flash_fixup_amd(flash_info_t *info, struct cfi_qry *qry) /* CFI < 1.1, try to guess from device id */ if ((info->device_id & 0x80) != 0) cfi_reverse_geometry(qry); - } else if (flash_read_uchar(info, info->ext_addr + 0xf) == 3) { + } else if (flash_read_uchar(info, info->ext_addr + 0x1e) == 3) { /* CFI >= 1.1, deduct from top/bottom flag */ /* note: ext_addr is valid since cfi_version > 0 */ cfi_reverse_geometry(qry); @@ -2024,6 +2053,26 @@ static void flash_fixup_sst(flash_info_t *info, struct cfi_qry *qry) } } +static void flash_fixup_num(flash_info_t *info, struct cfi_qry *qry) +{ + /* + * The M29EW devices seem to report the CFI information wrong + * when it's in 8 bit mode. + * There's an app note from Numonyx on this issue. + * So adjust the buffer size for M29EW while operating in 8-bit mode + */ + if (((qry->max_buf_write_size) > 0x8) && + (info->device_id == 0x7E) && + (info->device_id2 == 0x2201 || + info->device_id2 == 0x2301 || + info->device_id2 == 0x2801 || + info->device_id2 == 0x4801)) { + debug("Adjusted buffer size on Numonyx flash" + " M29EW family in 8 bit mode\n"); + qry->max_buf_write_size = 0x8; + } +} + /* * The following code cannot be run from FLASH! * @@ -2054,14 +2103,15 @@ ulong flash_get_size (phys_addr_t base, int banknum) if (flash_detect_cfi (info, &qry)) { info->vendor = le16_to_cpu(qry.p_id); - info->ext_addr = le16_to_cpu(qry.p_adr); + info->ext_addr = le16_to_cpu(qry.p_adr) * 2; + debug("extended address is 0x%x\n", info->ext_addr); num_erase_regions = qry.num_erase_regions; if (info->ext_addr) { info->cfi_version = (ushort) flash_read_uchar (info, - info->ext_addr + 3) << 8; + info->ext_addr + 6) << 8; info->cfi_version |= (ushort) flash_read_uchar (info, - info->ext_addr + 4); + info->ext_addr + 8); } #ifdef DEBUG @@ -2105,6 +2155,9 @@ ulong flash_get_size (phys_addr_t base, int banknum) case 0x00bf: /* SST */ flash_fixup_sst(info, &qry); break; + case 0x0089: /* Numonyx */ + flash_fixup_num(info, &qry); + break; } debug ("manufacturer is %d\n", info->vendor); @@ -2112,6 +2165,8 @@ ulong flash_get_size (phys_addr_t base, int banknum) debug ("device id is 0x%x\n", info->device_id); debug ("device id2 is 0x%x\n", info->device_id2); debug ("cfi version is 0x%04x\n", info->cfi_version); + debug("port width: %d, chipwidth: %d, interface: %d\n", + info->portwidth, info->chipwidth, info->interface); size_ratio = info->portwidth / info->chipwidth; /* if the chip is x8/x16 reduce the ratio by half */ diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index 96dcda2..cbfc679 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -347,16 +347,18 @@ static struct mtd_part *add_one_partition(struct mtd_info *master, if (mtd_mod_by_eb(cur_offset, master) != 0) { /* Round up to next erasesize */ slave->offset = (mtd_div_by_eb(cur_offset, master) + 1) * master->erasesize; - printk(KERN_NOTICE "Moving partition %d: " - "0x%012llx -> 0x%012llx\n", partno, - (unsigned long long)cur_offset, (unsigned long long)slave->offset); + debug("Moving partition %d: 0x%012llx -> 0x%012llx\n", + partno, (unsigned long long)cur_offset, + (unsigned long long)slave->offset); } } if (slave->mtd.size == MTDPART_SIZ_FULL) slave->mtd.size = master->size - slave->offset; - printk(KERN_NOTICE "0x%012llx-0x%012llx : \"%s\"\n", (unsigned long long)slave->offset, - (unsigned long long)(slave->offset + slave->mtd.size), slave->mtd.name); + debug("0x%012llx-0x%012llx : \"%s\"\n", + (unsigned long long)slave->offset, + (unsigned long long)(slave->offset + slave->mtd.size), + slave->mtd.name); /* let's do some sanity checks */ if (slave->offset >= master->size) { @@ -463,7 +465,7 @@ int add_mtd_partitions(struct mtd_info *master, if (mtd_partitions.next == NULL) INIT_LIST_HEAD(&mtd_partitions); - printk(KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n", nbparts, master->name); + debug("Creating %d MTD partitions on \"%s\":\n", nbparts, master->name); for (i = 0; i < nbparts; i++) { slave = add_one_partition(master, parts + i, i, cur_offset); diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index c77c0c4..35769c5 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -73,7 +73,6 @@ COBJS-$(CONFIG_NAND_MXS) += mxs_nand.o COBJS-$(CONFIG_NAND_NDFC) += ndfc.o COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.o -COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o COBJS-$(CONFIG_TEGRA_NAND) += tegra_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o @@ -82,6 +81,7 @@ COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o else # minimal SPL drivers COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o +COBJS-$(CONFIG_NAND_MXC) += mxc_nand_spl.o endif # drivers endif # nand diff --git a/drivers/mtd/nand/kirkwood_nand.c b/drivers/mtd/nand/kirkwood_nand.c index bdab5aa..0a99a10 100644 --- a/drivers/mtd/nand/kirkwood_nand.c +++ b/drivers/mtd/nand/kirkwood_nand.c @@ -74,7 +74,11 @@ void kw_nand_select_chip(struct mtd_info *mtd, int chip) int board_nand_init(struct nand_chip *nand) { nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING; +#if defined(CONFIG_NAND_ECC_BCH) + nand->ecc.mode = NAND_ECC_SOFT_BCH; +#else nand->ecc.mode = NAND_ECC_SOFT; +#endif nand->cmd_ctrl = kw_nand_hwcontrol; nand->chip_delay = 40; nand->select_chip = kw_nand_select_chip; diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index d0ded48..eeba521 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -22,20 +22,22 @@ #include <nand.h> #include <linux/err.h> #include <asm/io.h> -#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) +#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \ + defined(CONFIG_MX51) || defined(CONFIG_MX53) #include <asm/arch/imx-regs.h> #endif -#include <fsl_nfc.h> +#include "mxc_nand.h" #define DRIVER_NAME "mxc_nand" -typedef enum {false, true} bool; - struct mxc_nand_host { struct mtd_info mtd; struct nand_chip *nand; - struct fsl_nfc_regs __iomem *regs; + struct mxc_nand_regs __iomem *regs; +#ifdef MXC_NFC_V3_2 + struct mxc_nand_ip_regs __iomem *ip_regs; +#endif int spare_only; int status_request; int pagesize_2k; @@ -77,7 +79,7 @@ static struct nand_ecclayout nand_hw_eccoob2k = { .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} }, }; #endif -#elif defined(MXC_NFC_V2_1) +#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) #ifndef CONFIG_SYS_NAND_LARGEPAGE static struct nand_ecclayout nand_hw_eccoob = { .eccbytes = 9, @@ -98,45 +100,14 @@ static struct nand_ecclayout nand_hw_eccoob2k = { #endif #endif -#ifdef CONFIG_MX27 -static int is_16bit_nand(void) -{ - struct system_control_regs *sc_regs = - (struct system_control_regs *)IMX_SYSTEM_CTL_BASE; - - if (readl(&sc_regs->fmcr) & NF_16BIT_SEL) - return 1; - else - return 0; -} -#elif defined(CONFIG_MX31) static int is_16bit_nand(void) { - struct clock_control_regs *sc_regs = - (struct clock_control_regs *)CCM_BASE; - - if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B) - return 1; - else - return 0; -} -#elif defined(CONFIG_MX25) || defined(CONFIG_MX35) -static int is_16bit_nand(void) -{ - struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - - if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL) - return 1; - else - return 0; -} +#if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT) + return 1; #else -#warning "8/16 bit NAND autodetection not supported" -static int is_16bit_nand(void) -{ return 0; -} #endif +} static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size) { @@ -150,7 +121,7 @@ static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size /* * This function polls the NANDFC to wait for the basic operation to - * complete by checking the INT bit of config2 register. + * complete by checking the INT bit. */ static void wait_op_done(struct mxc_nand_host *host, int max_retries, uint16_t param) @@ -158,10 +129,17 @@ static void wait_op_done(struct mxc_nand_host *host, int max_retries, uint32_t tmp; while (max_retries-- > 0) { - if (readw(&host->regs->config2) & NFC_INT) { - tmp = readw(&host->regs->config2); - tmp &= ~NFC_INT; - writew(tmp, &host->regs->config2); +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) + tmp = readnfc(&host->regs->config2); + if (tmp & NFC_V1_V2_CONFIG2_INT) { + tmp &= ~NFC_V1_V2_CONFIG2_INT; + writenfc(tmp, &host->regs->config2); +#elif defined(MXC_NFC_V3_2) + tmp = readnfc(&host->ip_regs->ipc); + if (tmp & NFC_V3_IPC_INT) { + tmp &= ~NFC_V3_IPC_INT; + writenfc(tmp, &host->ip_regs->ipc); +#endif break; } udelay(1); @@ -180,8 +158,8 @@ static void send_cmd(struct mxc_nand_host *host, uint16_t cmd) { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd); - writew(cmd, &host->regs->flash_cmd); - writew(NFC_CMD, &host->regs->config2); + writenfc(cmd, &host->regs->flash_cmd); + writenfc(NFC_CMD, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, cmd); @@ -196,8 +174,8 @@ static void send_addr(struct mxc_nand_host *host, uint16_t addr) { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr); - writew(addr, &host->regs->flash_addr); - writew(NFC_ADDR, &host->regs->config2); + writenfc(addr, &host->regs->flash_addr); + writenfc(NFC_ADDR, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, addr); @@ -213,7 +191,7 @@ static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id, if (spare_only) MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only); - if (is_mxc_nfc_21()) { + if (is_mxc_nfc_21() || is_mxc_nfc_32()) { int i; /* * The controller copies the 64 bytes of spare data from @@ -229,19 +207,26 @@ static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id, } } - writew(buf_id, &host->regs->buf_addr); +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) + writenfc(buf_id, &host->regs->buf_addr); +#elif defined(MXC_NFC_V3_2) + uint32_t tmp = readnfc(&host->regs->config1); + tmp &= ~NFC_V3_CONFIG1_RBA_MASK; + tmp |= NFC_V3_CONFIG1_RBA(buf_id); + writenfc(tmp, &host->regs->config1); +#endif /* Configure spare or page+spare access */ if (!host->pagesize_2k) { - uint16_t config1 = readw(&host->regs->config1); + uint32_t config1 = readnfc(&host->regs->config1); if (spare_only) - config1 |= NFC_SP_EN; + config1 |= NFC_CONFIG1_SP_EN; else - config1 &= ~NFC_SP_EN; - writew(config1, &host->regs->config1); + config1 &= ~NFC_CONFIG1_SP_EN; + writenfc(config1, &host->regs->config1); } - writew(NFC_INPUT, &host->regs->config2); + writenfc(NFC_INPUT, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, spare_only); @@ -256,24 +241,31 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id, { MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only); - writew(buf_id, &host->regs->buf_addr); +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) + writenfc(buf_id, &host->regs->buf_addr); +#elif defined(MXC_NFC_V3_2) + uint32_t tmp = readnfc(&host->regs->config1); + tmp &= ~NFC_V3_CONFIG1_RBA_MASK; + tmp |= NFC_V3_CONFIG1_RBA(buf_id); + writenfc(tmp, &host->regs->config1); +#endif /* Configure spare or page+spare access */ if (!host->pagesize_2k) { - uint32_t config1 = readw(&host->regs->config1); + uint32_t config1 = readnfc(&host->regs->config1); if (spare_only) - config1 |= NFC_SP_EN; + config1 |= NFC_CONFIG1_SP_EN; else - config1 &= ~NFC_SP_EN; - writew(config1, &host->regs->config1); + config1 &= ~NFC_CONFIG1_SP_EN; + writenfc(config1, &host->regs->config1); } - writew(NFC_OUTPUT, &host->regs->config2); + writenfc(NFC_OUTPUT, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, spare_only); - if (is_mxc_nfc_21()) { + if (is_mxc_nfc_21() || is_mxc_nfc_32()) { int i; /* @@ -293,17 +285,23 @@ static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id, /* Request the NANDFC to perform a read of the NAND device ID. */ static void send_read_id(struct mxc_nand_host *host) { - uint16_t tmp; + uint32_t tmp; +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) /* NANDFC buffer 0 is used for device ID output */ - writew(0x0, &host->regs->buf_addr); + writenfc(0x0, &host->regs->buf_addr); +#elif defined(MXC_NFC_V3_2) + tmp = readnfc(&host->regs->config1); + tmp &= ~NFC_V3_CONFIG1_RBA_MASK; + writenfc(tmp, &host->regs->config1); +#endif /* Read ID into main buffer */ - tmp = readw(&host->regs->config1); - tmp &= ~NFC_SP_EN; - writew(tmp, &host->regs->config1); + tmp = readnfc(&host->regs->config1); + tmp &= ~NFC_CONFIG1_SP_EN; + writenfc(tmp, &host->regs->config1); - writew(NFC_ID, &host->regs->config2); + writenfc(NFC_ID, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, 0); @@ -315,32 +313,40 @@ static void send_read_id(struct mxc_nand_host *host) */ static uint16_t get_dev_status(struct mxc_nand_host *host) { +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) void __iomem *main_buf = host->regs->main_area[1]; uint32_t store; - uint16_t ret, tmp; +#endif + uint32_t ret, tmp; /* Issue status request to NAND device */ +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) /* store the main area1 first word, later do recovery */ store = readl(main_buf); /* NANDFC buffer 1 is used for device status */ - writew(1, &host->regs->buf_addr); + writenfc(1, &host->regs->buf_addr); +#endif /* Read status into main buffer */ - tmp = readw(&host->regs->config1); - tmp &= ~NFC_SP_EN; - writew(tmp, &host->regs->config1); + tmp = readnfc(&host->regs->config1); + tmp &= ~NFC_CONFIG1_SP_EN; + writenfc(tmp, &host->regs->config1); - writew(NFC_STATUS, &host->regs->config2); + writenfc(NFC_STATUS, &host->regs->operation); /* Wait for operation to complete */ wait_op_done(host, TROP_US_DELAY, 0); +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) /* * Status is placed in first word of main buffer * get status, then recovery area 1 data */ ret = readw(main_buf); writel(store, main_buf); +#elif defined(MXC_NFC_V3_2) + ret = readnfc(&host->regs->config1) >> 16; +#endif return ret; } @@ -359,13 +365,23 @@ static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on) { struct nand_chip *nand_chip = mtd->priv; struct mxc_nand_host *host = nand_chip->priv; - uint16_t tmp = readw(&host->regs->config1); +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) + uint16_t tmp = readnfc(&host->regs->config1); if (on) - tmp |= NFC_ECC_EN; + tmp |= NFC_V1_V2_CONFIG1_ECC_EN; else - tmp &= ~NFC_ECC_EN; - writew(tmp, &host->regs->config1); + tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN; + writenfc(tmp, &host->regs->config1); +#elif defined(MXC_NFC_V3_2) + uint32_t tmp = readnfc(&host->ip_regs->config2); + + if (on) + tmp |= NFC_V3_CONFIG2_ECC_EN; + else + tmp &= ~NFC_V3_CONFIG2_ECC_EN; + writenfc(tmp, &host->ip_regs->config2); +#endif } #ifdef CONFIG_MXC_NAND_HWECC @@ -377,7 +393,7 @@ static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode) */ } -#ifdef MXC_NFC_V2_1 +#if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip, int page, int sndcmd) @@ -391,7 +407,7 @@ static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd, MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: Reading OOB area of page %u to oob %p\n", - __FUNCTION__, host->page_addr, buf); + __func__, page, buf); chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page); for (i = 0; i < chip->ecc.steps; i++) { @@ -445,7 +461,7 @@ static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd, int n; _mxc_nand_enable_hwecc(mtd, 0); - chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr); + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) { host->col_addr = n * eccsize; @@ -489,7 +505,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd, uint8_t *oob = chip->oob_poi; MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n", - host->page_addr, buf, oob); + page, buf, oob); /* first read the data area and the available portion of OOB */ for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) { @@ -527,7 +543,7 @@ static int mxc_nand_read_page_syndrome(struct mtd_info *mtd, /* Then switch ECC off and read the OOB area to get the ECC code */ _mxc_nand_enable_hwecc(mtd, 0); - chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr); + chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page); eccsteps = chip->ecc.steps; oob = chip->oob_poi + chip->ecc.prepad; for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) { @@ -698,7 +714,7 @@ static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat, * additional correction. 2-Bit errors cannot be corrected by * HW ECC, so we need to return failure */ - uint16_t ecc_status = readw(&host->regs->ecc_status_result); + uint16_t ecc_status = readnfc(&host->regs->ecc_status_result); if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { MTDDEBUG(MTD_DEBUG_LEVEL0, @@ -1167,8 +1183,8 @@ static struct nand_bbt_descr bbt_mirror_descr = { int board_nand_init(struct nand_chip *this) { struct mtd_info *mtd; -#ifdef MXC_NFC_V2_1 - uint16_t tmp; +#if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) + uint32_t tmp; #endif #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT @@ -1195,14 +1211,18 @@ int board_nand_init(struct nand_chip *this) this->read_buf = mxc_nand_read_buf; this->verify_buf = mxc_nand_verify_buf; - host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; + host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE; +#ifdef MXC_NFC_V3_2 + host->ip_regs = + (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE; +#endif host->clk_act = 1; #ifdef CONFIG_MXC_NAND_HWECC this->ecc.calculate = mxc_nand_calculate_ecc; this->ecc.hwctl = mxc_nand_enable_hwecc; this->ecc.correct = mxc_nand_correct_data; - if (is_mxc_nfc_21()) { + if (is_mxc_nfc_21() || is_mxc_nfc_32()) { this->ecc.mode = NAND_ECC_HW_SYNDROME; this->ecc.read_page = mxc_nand_read_page_syndrome; this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome; @@ -1240,25 +1260,26 @@ int board_nand_init(struct nand_chip *this) this->ecc.layout = &nand_hw_eccoob; #endif +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) #ifdef MXC_NFC_V2_1 - tmp = readw(&host->regs->config1); - tmp |= NFC_ONE_CYCLE; - tmp |= NFC_4_8N_ECC; - writew(tmp, &host->regs->config1); + tmp = readnfc(&host->regs->config1); + tmp |= NFC_V2_CONFIG1_ONE_CYCLE; + tmp |= NFC_V2_CONFIG1_ECC_MODE_4; + writenfc(tmp, &host->regs->config1); if (host->pagesize_2k) - writew(64/2, &host->regs->spare_area_size); + writenfc(64/2, &host->regs->spare_area_size); else - writew(16/2, &host->regs->spare_area_size); + writenfc(16/2, &host->regs->spare_area_size); #endif /* * preset operation * Unlock the internal RAM Buffer */ - writew(0x2, &host->regs->config); + writenfc(0x2, &host->regs->config); /* Blocks to be unlocked */ - writew(0x0, &host->regs->unlockstart_blkaddr); + writenfc(0x0, &host->regs->unlockstart_blkaddr); /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the * unlockend_blkaddr, but the magic 0x4000 does not always work * when writing more than some 32 megabytes (on 2k page nands) @@ -1270,10 +1291,53 @@ int board_nand_init(struct nand_chip *this) * This might be NAND chip specific and the i.MX31 datasheet is * extremely vague about the semantics of this register. */ - writew(0xFFFF, &host->regs->unlockend_blkaddr); + writenfc(0xFFFF, &host->regs->unlockend_blkaddr); /* Unlock Block Command for given address range */ - writew(0x4, &host->regs->wrprot); + writenfc(0x4, &host->regs->wrprot); +#elif defined(MXC_NFC_V3_2) + writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1); + writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc); + + /* Unlock the internal RAM Buffer */ + writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK, + &host->ip_regs->wrprot); + + /* Blocks to be unlocked */ + for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++) + writenfc(0x0 | 0xFFFF << 16, + &host->ip_regs->wrprot_unlock_blkaddr[tmp]); + + writenfc(0, &host->ip_regs->ipc); + + tmp = readnfc(&host->ip_regs->config2); + tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK | + NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK); + tmp |= NFC_V3_CONFIG2_ONE_CYCLE; + + if (host->pagesize_2k) { + tmp |= NFC_V3_CONFIG2_SPAS(64/2); + tmp |= NFC_V3_CONFIG2_PS_2048; + } else { + tmp |= NFC_V3_CONFIG2_SPAS(16/2); + tmp |= NFC_V3_CONFIG2_PS_512; + } + + writenfc(tmp, &host->ip_regs->config2); + + tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) | + NFC_V3_CONFIG3_NO_SDMA | + NFC_V3_CONFIG3_RBB_MODE | + NFC_V3_CONFIG3_SBB(6) | /* Reset default */ + NFC_V3_CONFIG3_ADD_OP(0); + + if (!(this->options & NAND_BUSWIDTH_16)) + tmp |= NFC_V3_CONFIG3_FW8; + + writenfc(tmp, &host->ip_regs->config3); + + writenfc(0, &host->ip_regs->delay_line); +#endif return 0; } diff --git a/drivers/mtd/nand/mxc_nand.h b/drivers/mtd/nand/mxc_nand.h new file mode 100644 index 0000000..308ff8d --- /dev/null +++ b/drivers/mtd/nand/mxc_nand.h @@ -0,0 +1,225 @@ +/* + * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MXC_NAND_H +#define __MXC_NAND_H + +/* + * Register map and bit definitions for the Freescale NAND Flash Controller + * present in various i.MX devices. + * + * MX31 and MX27 have version 1, which has: + * 4 512-byte main buffers and + * 4 16-byte spare buffers + * to support up to 2K byte pagesize nand. + * Reading or writing a 2K page requires 4 FDI/FDO cycles. + * + * MX25 and MX35 have version 2.1, and MX51 and MX53 have version 3.2, which + * have: + * 8 512-byte main buffers and + * 8 64-byte spare buffers + * to support up to 4K byte pagesize nand. + * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. + * Also some of registers are moved and/or changed meaning as seen below. + */ +#if defined(CONFIG_MX27) || defined(CONFIG_MX31) +#define MXC_NFC_V1 +#define is_mxc_nfc_1() 1 +#define is_mxc_nfc_21() 0 +#define is_mxc_nfc_32() 0 +#elif defined(CONFIG_MX25) || defined(CONFIG_MX35) +#define MXC_NFC_V2_1 +#define is_mxc_nfc_1() 0 +#define is_mxc_nfc_21() 1 +#define is_mxc_nfc_32() 0 +#elif defined(CONFIG_MX51) || defined(CONFIG_MX53) +#define MXC_NFC_V3 +#define MXC_NFC_V3_2 +#define is_mxc_nfc_1() 0 +#define is_mxc_nfc_21() 0 +#define is_mxc_nfc_32() 1 +#else +#error "MXC NFC implementation not supported" +#endif +#define is_mxc_nfc_3() is_mxc_nfc_32() + +#if defined(MXC_NFC_V1) +#define NAND_MXC_NR_BUFS 4 +#define NAND_MXC_SPARE_BUF_SIZE 16 +#define NAND_MXC_REG_OFFSET 0xe00 +#define NAND_MXC_2K_MULTI_CYCLE +#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) +#define NAND_MXC_NR_BUFS 8 +#define NAND_MXC_SPARE_BUF_SIZE 64 +#define NAND_MXC_REG_OFFSET 0x1e00 +#endif + +struct mxc_nand_regs { + u8 main_area[NAND_MXC_NR_BUFS][0x200]; + u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE]; + /* + * reserved size is offset of nfc registers + * minus total main and spare sizes + */ + u8 reserved1[NAND_MXC_REG_OFFSET + - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)]; +#if defined(MXC_NFC_V1) + u16 buf_size; + u16 reserved2; + u16 buf_addr; + u16 flash_addr; + u16 flash_cmd; + u16 config; + u16 ecc_status_result; + u16 rsltmain_area; + u16 rsltspare_area; + u16 wrprot; + u16 unlockstart_blkaddr; + u16 unlockend_blkaddr; + u16 nf_wrprst; + u16 config1; + u16 config2; +#elif defined(MXC_NFC_V2_1) + u16 reserved2[2]; + u16 buf_addr; + u16 flash_addr; + u16 flash_cmd; + u16 config; + u32 ecc_status_result; + u16 spare_area_size; + u16 wrprot; + u16 reserved3[2]; + u16 nf_wrprst; + u16 config1; + u16 config2; + u16 reserved4; + u16 unlockstart_blkaddr; + u16 unlockend_blkaddr; + u16 unlockstart_blkaddr1; + u16 unlockend_blkaddr1; + u16 unlockstart_blkaddr2; + u16 unlockend_blkaddr2; + u16 unlockstart_blkaddr3; + u16 unlockend_blkaddr3; +#elif defined(MXC_NFC_V3_2) + u32 flash_cmd; + u32 flash_addr[12]; + u32 config1; + u32 ecc_status_result; + u32 status_sum; + u32 launch; +#endif +}; + +#ifdef MXC_NFC_V3_2 +struct mxc_nand_ip_regs { + u32 wrprot; + u32 wrprot_unlock_blkaddr[8]; + u32 config2; + u32 config3; + u32 ipc; + u32 err_addr; + u32 delay_line; +}; +#endif + +/* Set FCMD to 1, rest to 0 for Command operation */ +#define NFC_CMD 0x1 + +/* Set FADD to 1, rest to 0 for Address operation */ +#define NFC_ADDR 0x2 + +/* Set FDI to 1, rest to 0 for Input operation */ +#define NFC_INPUT 0x4 + +/* Set FDO to 001, rest to 0 for Data Output operation */ +#define NFC_OUTPUT 0x8 + +/* Set FDO to 010, rest to 0 for Read ID operation */ +#define NFC_ID 0x10 + +/* Set FDO to 100, rest to 0 for Read Status operation */ +#define NFC_STATUS 0x20 + +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) +#define NFC_CONFIG1_SP_EN (1 << 2) +#define NFC_CONFIG1_RST (1 << 6) +#define NFC_CONFIG1_CE (1 << 7) +#elif defined(MXC_NFC_V3_2) +#define NFC_CONFIG1_SP_EN (1 << 0) +#define NFC_CONFIG1_CE (1 << 1) +#define NFC_CONFIG1_RST (1 << 2) +#endif +#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) +#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) +#define NFC_V1_V2_CONFIG1_BIG (1 << 5) +#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) +#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8) +#define NFC_V2_CONFIG1_FP_INT (1 << 11) +#define NFC_V3_CONFIG1_RBA_MASK (0x7 << 4) +#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7) << 4) + +#define NFC_V1_V2_CONFIG2_INT (1 << 15) +#define NFC_V3_CONFIG2_PS_MASK (0x3 << 0) +#define NFC_V3_CONFIG2_PS_512 (0 << 0) +#define NFC_V3_CONFIG2_PS_2048 (1 << 0) +#define NFC_V3_CONFIG2_PS_4096 (2 << 0) +#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) +#define NFC_V3_CONFIG2_ECC_EN (1 << 3) +#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) +#define NFC_V3_CONFIG2_NUM_ADDR_PH0 (1 << 5) +#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) +#define NFC_V3_CONFIG2_PPB_MASK (0x3 << 7) +#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7) +#define NFC_V3_CONFIG2_EDC_MASK (0x7 << 9) +#define NFC_V3_CONFIG2_EDC(x) (((x) & 0x7) << 9) +#define NFC_V3_CONFIG2_NUM_ADDR_PH1(x) (((x) & 0x3) << 12) +#define NFC_V3_CONFIG2_INT_MSK (1 << 15) +#define NFC_V3_CONFIG2_SPAS_MASK (0xff << 16) +#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) +#define NFC_V3_CONFIG2_ST_CMD_MASK (0xff << 24) +#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) + +#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) +#define NFC_V3_CONFIG3_FW8 (1 << 3) +#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) +#define NFC_V3_CONFIG3_NUM_OF_DEVS(x) (((x) & 0x7) << 12) +#define NFC_V3_CONFIG3_RBB_MODE (1 << 15) +#define NFC_V3_CONFIG3_NO_SDMA (1 << 20) + +#define NFC_V3_WRPROT_UNLOCK (1 << 2) +#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) + +#define NFC_V3_IPC_CREQ (1 << 0) +#define NFC_V3_IPC_INT (1 << 31) + +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) +#define operation config2 +#define readnfc readw +#define writenfc writew +#elif defined(MXC_NFC_V3_2) +#define operation launch +#define readnfc readl +#define writenfc writel +#endif + +#endif /* __MXC_NAND_H */ diff --git a/nand_spl/nand_boot_fsl_nfc.c b/drivers/mtd/nand/mxc_nand_spl.c index a40c998..09f23c3 100644 --- a/nand_spl/nand_boot_fsl_nfc.c +++ b/drivers/mtd/nand/mxc_nand_spl.c @@ -28,66 +28,119 @@ #include <nand.h> #include <asm/arch/imx-regs.h> #include <asm/io.h> -#include <fsl_nfc.h> +#include "mxc_nand.h" -static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR; +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) +static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR; +#elif defined(MXC_NFC_V3_2) +static struct mxc_nand_regs *const nfc = (void *)NFC_BASE_ADDR_AXI; +static struct mxc_nand_ip_regs *const nfc_ip = (void *)NFC_BASE_ADDR; +#endif static void nfc_wait_ready(void) { uint32_t tmp; - while (!(readw(&nfc->config2) & NFC_INT)) +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) + while (!(readnfc(&nfc->config2) & NFC_V1_V2_CONFIG2_INT)) + ; + + /* Reset interrupt flag */ + tmp = readnfc(&nfc->config2); + tmp &= ~NFC_V1_V2_CONFIG2_INT; + writenfc(tmp, &nfc->config2); +#elif defined(MXC_NFC_V3_2) + while (!(readnfc(&nfc_ip->ipc) & NFC_V3_IPC_INT)) ; /* Reset interrupt flag */ - tmp = readw(&nfc->config2); - tmp &= ~NFC_INT; - writew(tmp, &nfc->config2); + tmp = readnfc(&nfc_ip->ipc); + tmp &= ~NFC_V3_IPC_INT; + writenfc(tmp, &nfc_ip->ipc); +#endif } static void nfc_nand_init(void) { -#if defined(MXC_NFC_V2_1) +#if defined(MXC_NFC_V3_2) + int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; + int tmp; + + tmp = (readnfc(&nfc_ip->config2) & ~(NFC_V3_CONFIG2_SPAS_MASK | + NFC_V3_CONFIG2_EDC_MASK | NFC_V3_CONFIG2_PS_MASK)) | + NFC_V3_CONFIG2_SPAS(CONFIG_SYS_NAND_OOBSIZE / 2) | + NFC_V3_CONFIG2_INT_MSK | NFC_V3_CONFIG2_ECC_EN | + NFC_V3_CONFIG2_ONE_CYCLE; + if (CONFIG_SYS_NAND_PAGE_SIZE == 4096) + tmp |= NFC_V3_CONFIG2_PS_4096; + else if (CONFIG_SYS_NAND_PAGE_SIZE == 2048) + tmp |= NFC_V3_CONFIG2_PS_2048; + else if (CONFIG_SYS_NAND_PAGE_SIZE == 512) + tmp |= NFC_V3_CONFIG2_PS_512; + /* + * if spare size is larger that 16 bytes per 512 byte hunk + * then use 8 symbol correction instead of 4 + */ + if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16) + tmp |= NFC_V3_CONFIG2_ECC_MODE_8; + else + tmp &= ~NFC_V3_CONFIG2_ECC_MODE_8; + writenfc(tmp, &nfc_ip->config2); + + tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) | + NFC_V3_CONFIG3_NO_SDMA | + NFC_V3_CONFIG3_RBB_MODE | + NFC_V3_CONFIG3_SBB(6) | /* Reset default */ + NFC_V3_CONFIG3_ADD_OP(0); +#ifndef CONFIG_SYS_NAND_BUSWIDTH_16 + tmp |= NFC_V3_CONFIG3_FW8; +#endif + writenfc(tmp, &nfc_ip->config3); + + writenfc(0, &nfc_ip->delay_line); +#elif defined(MXC_NFC_V2_1) int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; int config1; - writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size); + writenfc(CONFIG_SYS_NAND_OOBSIZE / 2, &nfc->spare_area_size); /* unlocking RAM Buff */ - writew(0x2, &nfc->config); + writenfc(0x2, &nfc->config); /* hardware ECC checking and correct */ - config1 = readw(&nfc->config1) | NFC_ECC_EN | NFC_INT_MSK | - NFC_ONE_CYCLE | NFC_FP_INT; + config1 = readnfc(&nfc->config1) | NFC_V1_V2_CONFIG1_ECC_EN | + NFC_V1_V2_CONFIG1_INT_MSK | NFC_V2_CONFIG1_ONE_CYCLE | + NFC_V2_CONFIG1_FP_INT; /* * if spare size is larger that 16 bytes per 512 byte hunk * then use 8 symbol correction instead of 4 */ - if (CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16) - config1 &= ~NFC_4_8N_ECC; + if (CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16) + config1 &= ~NFC_V2_CONFIG1_ECC_MODE_4; else - config1 |= NFC_4_8N_ECC; - writew(config1, &nfc->config1); + config1 |= NFC_V2_CONFIG1_ECC_MODE_4; + writenfc(config1, &nfc->config1); #elif defined(MXC_NFC_V1) /* unlocking RAM Buff */ - writew(0x2, &nfc->config); + writenfc(0x2, &nfc->config); /* hardware ECC checking and correct */ - writew(NFC_ECC_EN | NFC_INT_MSK, &nfc->config1); + writenfc(NFC_V1_V2_CONFIG1_ECC_EN | NFC_V1_V2_CONFIG1_INT_MSK, + &nfc->config1); #endif } static void nfc_nand_command(unsigned short command) { - writew(command, &nfc->flash_cmd); - writew(NFC_CMD, &nfc->config2); + writenfc(command, &nfc->flash_cmd); + writenfc(NFC_CMD, &nfc->operation); nfc_wait_ready(); } static void nfc_nand_address(unsigned short address) { - writew(address, &nfc->flash_addr); - writew(NFC_ADDR, &nfc->config2); + writenfc(address, &nfc->flash_addr); + writenfc(NFC_ADDR, &nfc->operation); nfc_wait_ready(); } @@ -121,8 +174,14 @@ static void nfc_nand_data_output(void) int i; #endif - writew(0, &nfc->buf_addr); - writew(NFC_OUTPUT, &nfc->config2); +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) + writenfc(0, &nfc->buf_addr); +#elif defined(MXC_NFC_V3_2) + int config1 = readnfc(&nfc->config1); + config1 &= ~NFC_V3_CONFIG1_RBA_MASK; + writenfc(config1, &nfc->config1); +#endif + writenfc(NFC_OUTPUT, &nfc->operation); nfc_wait_ready(); #ifdef NAND_MXC_2K_MULTI_CYCLE /* @@ -130,8 +189,8 @@ static void nfc_nand_data_output(void) * for pages larger than 512 bytes. */ for (i = 1; i < CONFIG_SYS_NAND_PAGE_SIZE / 512; i++) { - writew(i, &nfc->buf_addr); - writew(NFC_OUTPUT, &nfc->config2); + writenfc(i, &nfc->buf_addr); + writenfc(NFC_OUTPUT, &nfc->operation); nfc_wait_ready(); } #endif @@ -142,10 +201,10 @@ static int nfc_nand_check_ecc(void) #if defined(MXC_NFC_V1) u16 ecc_status = readw(&nfc->ecc_status_result); return (ecc_status & 0x3) == 2 || (ecc_status >> 2) == 2; -#elif defined(MXC_NFC_V2_1) +#elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2) u32 ecc_status = readl(&nfc->ecc_status_result); int ecc_per_page = CONFIG_SYS_NAND_PAGE_SIZE / 512; - int err_limit = CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page > 16 ? 8 : 4; + int err_limit = CONFIG_SYS_NAND_OOBSIZE / ecc_per_page > 16 ? 8 : 4; int subpages = CONFIG_SYS_NAND_PAGE_SIZE / 512; do { @@ -160,7 +219,14 @@ static int nfc_nand_check_ecc(void) static void nfc_nand_read_page(unsigned int page_address) { - writew(0, &nfc->buf_addr); /* read in first 0 buffer */ + /* read in first 0 buffer */ +#if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1) + writenfc(0, &nfc->buf_addr); +#elif defined(MXC_NFC_V3_2) + int config1 = readnfc(&nfc->config1); + config1 &= ~NFC_V3_CONFIG1_RBA_MASK; + writenfc(config1, &nfc->config1); +#endif nfc_nand_command(NAND_CMD_READ0); nfc_nand_page_address(page_address); @@ -266,14 +332,6 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf) return 0; } -#if defined(CONFIG_ARM) -void board_init_f (ulong bootflag) -{ - relocate_code (CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, - CONFIG_SYS_TEXT_BASE); -} -#endif - /* * The main entry for NAND booting. It's necessary that SDRAM is already * configured and available since this code loads the main U-Boot image diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index ff2d348..4727f9c 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -416,11 +416,13 @@ int nand_unlock(struct mtd_info *mtd, loff_t start, size_t length, * @param nand NAND device * @param offset offset in flash * @param length image length + * @param used length of flash needed for the requested length * @return 0 if the image fits and there are no bad blocks * 1 if the image fits, but there are bad blocks * -1 if the image does not fit */ -static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length) +static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length, + size_t *used) { size_t len_excl_bad = 0; int ret = 0; @@ -442,8 +444,13 @@ static int check_skip_len(nand_info_t *nand, loff_t offset, size_t length) ret = 1; offset += block_len; + *used += block_len; } + /* If the length is not a multiple of block_len, adjust. */ + if (len_excl_bad > length) + *used -= (len_excl_bad - length); + return ret; } @@ -476,23 +483,36 @@ static size_t drop_ffs(const nand_info_t *nand, const u_char *buf, * Write image to NAND flash. * Blocks that are marked bad are skipped and the is written to the next * block instead as long as the image is short enough to fit even after - * skipping the bad blocks. + * skipping the bad blocks. Due to bad blocks we may not be able to + * perform the requested write. In the case where the write would + * extend beyond the end of the NAND device, both length and actual (if + * not NULL) are set to 0. In the case where the write would extend + * beyond the limit we are passed, length is set to 0 and actual is set + * to the required length. * * @param nand NAND device * @param offset offset in flash * @param length buffer length + * @param actual set to size required to write length worth of + * buffer or 0 on error, if not NULL + * @param lim maximum size that actual may be in order to not + * exceed the buffer * @param buffer buffer to read from * @param flags flags modifying the behaviour of the write to NAND * @return 0 in case of success */ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, - u_char *buffer, int flags) + size_t *actual, loff_t lim, u_char *buffer, int flags) { int rval = 0, blocksize; size_t left_to_write = *length; + size_t used_for_write = 0; u_char *p_buffer = buffer; int need_skip; + if (actual) + *actual = 0; + #ifdef CONFIG_CMD_NAND_YAFFS if (flags & WITH_YAFFS_OOB) { if (flags & ~WITH_YAFFS_OOB) @@ -529,13 +549,23 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, return -EINVAL; } - need_skip = check_skip_len(nand, offset, *length); + need_skip = check_skip_len(nand, offset, *length, &used_for_write); + + if (actual) + *actual = used_for_write; + if (need_skip < 0) { printf("Attempt to write outside the flash area\n"); *length = 0; return -EINVAL; } + if (used_for_write > lim) { + puts("Size of write exceeds partition or device limit\n"); + *length = 0; + return -EFBIG; + } + if (!need_skip && !(flags & WITH_DROP_FFS)) { rval = nand_write(nand, offset, length, buffer); if (rval == 0) @@ -626,36 +656,58 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, * * Read image from NAND flash. * Blocks that are marked bad are skipped and the next block is read - * instead as long as the image is short enough to fit even after skipping the - * bad blocks. + * instead as long as the image is short enough to fit even after + * skipping the bad blocks. Due to bad blocks we may not be able to + * perform the requested read. In the case where the read would extend + * beyond the end of the NAND device, both length and actual (if not + * NULL) are set to 0. In the case where the read would extend beyond + * the limit we are passed, length is set to 0 and actual is set to the + * required length. * * @param nand NAND device * @param offset offset in flash * @param length buffer length, on return holds number of read bytes + * @param actual set to size required to read length worth of buffer or 0 + * on error, if not NULL + * @param lim maximum size that actual may be in order to not exceed the + * buffer * @param buffer buffer to write to * @return 0 in case of success */ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, - u_char *buffer) + size_t *actual, loff_t lim, u_char *buffer) { int rval; size_t left_to_read = *length; + size_t used_for_read = 0; u_char *p_buffer = buffer; int need_skip; if ((offset & (nand->writesize - 1)) != 0) { printf("Attempt to read non page-aligned data\n"); *length = 0; + if (actual) + *actual = 0; return -EINVAL; } - need_skip = check_skip_len(nand, offset, *length); + need_skip = check_skip_len(nand, offset, *length, &used_for_read); + + if (actual) + *actual = used_for_read; + if (need_skip < 0) { printf("Attempt to read outside the flash area\n"); *length = 0; return -EINVAL; } + if (used_for_read > lim) { + puts("Size of read exceeds partition or device limit\n"); + *length = 0; + return -EFBIG; + } + if (!need_skip) { rval = nand_read(nand, offset, length, buffer); if (!rval || rval == -EUCLEAN) diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 6ebbb5e..213d2c9 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -156,7 +156,7 @@ static uint8_t ndfc_read_byte(struct mtd_info *mtd) struct nand_chip *chip = mtd->priv; -#ifdef CONFIG_SYS_NDFC_16BIT +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT return (uint8_t) readw(chip->IO_ADDR_R); #else return readb(chip->IO_ADDR_R); @@ -218,7 +218,7 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.bytes = 3; nand->select_chip = ndfc_select_chip; -#ifdef CONFIG_SYS_NDFC_16BIT +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT nand->options |= NAND_BUSWIDTH_16; #endif diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index cee394e..bc1bcad 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -25,8 +25,10 @@ #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/mem.h> -#include <asm/arch/omap_gpmc.h> +#include <asm/arch/cpu.h> +#include <asm/omap_gpmc.h> #include <linux/mtd/nand_ecc.h> +#include <linux/bch.h> #include <linux/compiler.h> #include <nand.h> #ifdef CONFIG_AM33XX @@ -36,6 +38,8 @@ static uint8_t cs; static __maybe_unused struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT; +static __maybe_unused struct nand_ecclayout hw_bch8_nand_oob = + GPMC_NAND_HW_BCH8_ECC_LAYOUT; /* * omap_nand_hwcontrol - Set the address pointers corretly for the @@ -238,13 +242,13 @@ static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) } /* - * BCH8 support (needs ELM and thus AM33xx-only) + * Generic BCH interface */ -#ifdef CONFIG_AM33XX struct nand_bch_priv { uint8_t mode; uint8_t type; uint8_t nibbles; + struct bch_control *control; }; /* bch types */ @@ -252,21 +256,146 @@ struct nand_bch_priv { #define ECC_BCH8 1 #define ECC_BCH16 2 +/* GPMC ecc engine settings */ +#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ +#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ + /* BCH nibbles for diff bch levels */ #define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1) #define ECC_BCH4_NIBBLES 13 #define ECC_BCH8_NIBBLES 26 #define ECC_BCH16_NIBBLES 52 -static struct nand_ecclayout hw_bch8_nand_oob = GPMC_NAND_HW_BCH8_ECC_LAYOUT; - -static struct nand_bch_priv bch_priv = { +/* + * This can be a single instance cause all current users have only one NAND + * with nearly the same setup (BCH8, some with ELM and others with sw BCH + * library). + * When some users with other BCH strength will exists this have to change! + */ +static __maybe_unused struct nand_bch_priv bch_priv = { .mode = NAND_ECC_HW_BCH, .type = ECC_BCH8, - .nibbles = ECC_BCH8_NIBBLES + .nibbles = ECC_BCH8_NIBBLES, + .control = NULL }; /* + * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in + * GPMC controller + * @mtd: MTD device structure + * @mode: Read/Write mode + */ +__maybe_unused +static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) +{ + uint32_t val; + uint32_t dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; +#ifdef CONFIG_AM33XX + uint32_t unused_length = 0; +#endif + uint32_t wr_mode = BCH_WRAPMODE_6; + struct nand_bch_priv *bch = chip->priv; + + /* Clear the ecc result registers, select ecc reg as 1 */ + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); + +#ifdef CONFIG_AM33XX + wr_mode = BCH_WRAPMODE_1; + + switch (bch->nibbles) { + case ECC_BCH4_NIBBLES: + unused_length = 3; + break; + case ECC_BCH8_NIBBLES: + unused_length = 2; + break; + case ECC_BCH16_NIBBLES: + unused_length = 0; + break; + } + + /* + * This is ecc_size_config for ELM mode. + * Here we are using different settings for read and write access and + * also depending on BCH strength. + */ + switch (mode) { + case NAND_ECC_WRITE: + /* write access only setup eccsize1 config */ + val = ((unused_length + bch->nibbles) << 22); + break; + + case NAND_ECC_READ: + default: + /* + * by default eccsize0 selected for ecc1resultsize + * eccsize0 config. + */ + val = (bch->nibbles << 12); + /* eccsize1 config */ + val |= (unused_length << 22); + break; + } +#else + /* + * This ecc_size_config setting is for BCH sw library. + * + * Note: we only support BCH8 currently with BCH sw library! + * Should be really easy to adobt to BCH4, however some omap3 have + * flaws with BCH4. + * + * Here we are using wrapping mode 6 both for reading and writing, with: + * size0 = 0 (no additional protected byte in spare area) + * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) + */ + val = (32 << 22) | (0 << 12); +#endif + /* ecc size configuration */ + writel(val, &gpmc_cfg->ecc_size_config); + + /* + * Configure the ecc engine in gpmc + * We assume 512 Byte sector pages for access to NAND. + */ + val = (1 << 16); /* enable BCH mode */ + val |= (bch->type << 12); /* setup BCH type */ + val |= (wr_mode << 8); /* setup wrapping mode */ + val |= (dev_width << 7); /* setup device width (16 or 8 bit) */ + val |= (cs << 1); /* setup chip select to work on */ + debug("set ECC_CONFIG=0x%08x\n", val); + writel(val, &gpmc_cfg->ecc_config); +} + +/* + * omap_enable_ecc_bch - This function enables the bch h/w ecc functionality + * @mtd: MTD device structure + * @mode: Read/Write mode + */ +__maybe_unused +static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode) +{ + struct nand_chip *chip = mtd->priv; + + omap_hwecc_init_bch(chip, mode); + /* enable ecc */ + writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config); +} + +/* + * omap_ecc_disable - Disable H/W ECC calculation + * + * @mtd: MTD device structure + */ +static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd) +{ + writel((readl(&gpmc_cfg->ecc_config) & ~0x1), &gpmc_cfg->ecc_config); +} + +/* + * BCH8 support (needs ELM and thus AM33xx-only) + */ +#ifdef CONFIG_AM33XX +/* * omap_read_bch8_result - Read BCH result for BCH8 level * * @mtd: MTD device structure @@ -305,18 +434,6 @@ static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian, } /* - * omap_ecc_disable - Disable H/W ECC calculation - * - * @mtd: MTD device structure - * - */ -static void omap_ecc_disable(struct mtd_info *mtd) -{ - writel((readl(&gpmc_cfg->ecc_config) & ~0x1), - &gpmc_cfg->ecc_config); -} - -/* * omap_rotate_ecc_bch - Rotate the syndrome bytes * * @mtd: MTD device structure @@ -467,76 +584,6 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, return 0; } -/* - * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in - * GPMC controller - * @mtd: MTD device structure - * @mode: Read/Write mode - */ -static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) -{ - uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; - uint32_t unused_length = 0; - struct nand_bch_priv *bch = chip->priv; - - switch (bch->nibbles) { - case ECC_BCH4_NIBBLES: - unused_length = 3; - break; - case ECC_BCH8_NIBBLES: - unused_length = 2; - break; - case ECC_BCH16_NIBBLES: - unused_length = 0; - break; - } - - /* Clear the ecc result registers, select ecc reg as 1 */ - writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); - - switch (mode) { - case NAND_ECC_WRITE: - /* eccsize1 config */ - val = ((unused_length + bch->nibbles) << 22); - break; - - case NAND_ECC_READ: - default: - /* by default eccsize0 selected for ecc1resultsize */ - /* eccsize0 config */ - val = (bch->nibbles << 12); - /* eccsize1 config */ - val |= (unused_length << 22); - break; - } - /* ecc size configuration */ - writel(val, &gpmc_cfg->ecc_size_config); - /* by default 512bytes sector page is selected */ - /* set bch mode */ - val = (1 << 16); - /* bch4 / bch8 / bch16 */ - val |= (bch->type << 12); - /* set wrap mode to 1 */ - val |= (1 << 8); - val |= (dev_width << 7); - val |= (cs << 1); - writel(val, &gpmc_cfg->ecc_config); -} - -/* - * omap_enable_ecc_bch- This function enables the bch h/w ecc functionality - * @mtd: MTD device structure - * @mode: Read/Write mode - * - */ -static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode) -{ - struct nand_chip *chip = mtd->priv; - - omap_hwecc_init_bch(chip, mode); - /* enable ecc */ - writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config); -} /** * omap_read_page_bch - hardware ecc based page read function @@ -601,15 +648,137 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, } #endif /* CONFIG_AM33XX */ -#ifndef CONFIG_SPL_BUILD /* - * omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc. - * The default is to come up on s/w ecc + * OMAP3 BCH8 support (with BCH library) + */ +#ifdef CONFIG_NAND_OMAP_BCH8 +/* + * omap_calculate_ecc_bch - Read BCH ECC result * - * @hardware - 1 -switch to h/w ecc, 0 - s/w ecc + * @mtd: MTD device structure + * @dat: The pointer to data on which ecc is computed (unused here) + * @ecc: The ECC output buffer + */ +static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, + uint8_t *ecc) +{ + int ret = 0; + size_t i; + unsigned long nsectors, val1, val2, val3, val4; + + nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1; + + for (i = 0; i < nsectors; i++) { + /* Read hw-computed remainder */ + val1 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[0]); + val2 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[1]); + val3 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[2]); + val4 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[3]); + + /* + * Add constant polynomial to remainder, in order to get an ecc + * sequence of 0xFFs for a buffer filled with 0xFFs. + */ + *ecc++ = 0xef ^ (val4 & 0xFF); + *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF); + *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF); + *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF); + *ecc++ = 0xed ^ (val3 & 0xFF); + *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF); + *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF); + *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF); + *ecc++ = 0x97 ^ (val2 & 0xFF); + *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF); + *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF); + *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF); + *ecc++ = 0xb5 ^ (val1 & 0xFF); + } + + /* + * Stop reading anymore ECC vals and clear old results + * enable will be called if more reads are required + */ + omap_ecc_disable(mtd); + + return ret; +} + +/** + * omap_correct_data_bch - Decode received data and correct errors + * @mtd: MTD device structure + * @data: page data + * @read_ecc: ecc read from nand flash + * @calc_ecc: ecc read from HW ECC registers + */ +static int omap_correct_data_bch(struct mtd_info *mtd, u_char *data, + u_char *read_ecc, u_char *calc_ecc) +{ + int i, count; + /* cannot correct more than 8 errors */ + unsigned int errloc[8]; + struct nand_chip *chip = mtd->priv; + struct nand_bch_priv *chip_priv = chip->priv; + struct bch_control *bch = chip_priv->control; + + count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc); + if (count > 0) { + /* correct errors */ + for (i = 0; i < count; i++) { + /* correct data only, not ecc bytes */ + if (errloc[i] < 8*512) + data[errloc[i]/8] ^= 1 << (errloc[i] & 7); + printf("corrected bitflip %u\n", errloc[i]); +#ifdef DEBUG + puts("read_ecc: "); + /* + * BCH8 have 13 bytes of ECC; BCH4 needs adoption + * here! + */ + for (i = 0; i < 13; i++) + printf("%02x ", read_ecc[i]); + puts("\n"); + puts("calc_ecc: "); + for (i = 0; i < 13; i++) + printf("%02x ", calc_ecc[i]); + puts("\n"); +#endif + } + } else if (count < 0) { + puts("ecc unrecoverable error\n"); + } + return count; +} + +/** + * omap_free_bch - Release BCH ecc resources + * @mtd: MTD device structure + */ +static void __maybe_unused omap_free_bch(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct nand_bch_priv *chip_priv = chip->priv; + struct bch_control *bch = NULL; + + if (chip_priv) + bch = chip_priv->control; + + if (bch) { + free_bch(bch); + chip_priv->control = NULL; + } +} +#endif /* CONFIG_NAND_OMAP_BCH8 */ + +#ifndef CONFIG_SPL_BUILD +/* + * omap_nand_switch_ecc - switch the ECC operation between different engines + * (h/w and s/w) and different algorithms (hamming and BCHx) * + * @hardware - true if one of the HW engines should be used + * @eccstrength - the number of bits that could be corrected + * (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16) */ -void omap_nand_switch_ecc(int32_t hardware) +void omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) { struct nand_chip *nand; struct mtd_info *mtd; @@ -627,6 +796,7 @@ void omap_nand_switch_ecc(int32_t hardware) nand->options |= NAND_OWN_BUFFERS; /* Reset ecc interface */ + nand->ecc.mode = NAND_ECC_NONE; nand->ecc.read_page = NULL; nand->ecc.write_page = NULL; nand->ecc.read_oob = NULL; @@ -636,28 +806,35 @@ void omap_nand_switch_ecc(int32_t hardware) nand->ecc.calculate = NULL; /* Setup the ecc configurations again */ - if (hardware == 1) { - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_nand_oob; - nand->ecc.size = 512; - nand->ecc.bytes = 3; - nand->ecc.hwctl = omap_enable_hwecc; - nand->ecc.correct = omap_correct_data; - nand->ecc.calculate = omap_calculate_ecc; - omap_hwecc_init(nand); - printf("HW ECC selected\n"); + if (hardware) { + if (eccstrength == 1) { + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &hw_nand_oob; + nand->ecc.size = 512; + nand->ecc.bytes = 3; + nand->ecc.hwctl = omap_enable_hwecc; + nand->ecc.correct = omap_correct_data; + nand->ecc.calculate = omap_calculate_ecc; + omap_hwecc_init(nand); + printf("1-bit hamming HW ECC selected\n"); + } +#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) + else if (eccstrength == 8) { + nand->ecc.mode = NAND_ECC_HW; + nand->ecc.layout = &hw_bch8_nand_oob; + nand->ecc.size = 512; #ifdef CONFIG_AM33XX - } else if (hardware == 2) { - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.layout = &hw_bch8_nand_oob; - nand->ecc.size = 512; - nand->ecc.bytes = 14; - nand->ecc.read_page = omap_read_page_bch; - nand->ecc.hwctl = omap_enable_ecc_bch; - nand->ecc.correct = omap_correct_data_bch; - nand->ecc.calculate = omap_calculate_ecc_bch; - omap_hwecc_init_bch(nand, NAND_ECC_READ); - printf("HW BCH8 selected\n"); + nand->ecc.bytes = 14; + nand->ecc.read_page = omap_read_page_bch; +#else + nand->ecc.bytes = 13; +#endif + nand->ecc.hwctl = omap_enable_ecc_bch; + nand->ecc.correct = omap_correct_data_bch; + nand->ecc.calculate = omap_calculate_ecc_bch; + omap_hwecc_init_bch(nand, NAND_ECC_READ); + printf("8-bit BCH HW ECC selected\n"); + } #endif } else { nand->ecc.mode = NAND_ECC_SOFT; @@ -731,16 +908,28 @@ int board_nand_init(struct nand_chip *nand) nand->chip_delay = 100; +#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) #ifdef CONFIG_AM33XX + /* AM33xx uses the ELM */ /* required in case of BCH */ elm_init(); - +#else + /* + * Whereas other OMAP based SoC do not have the ELM, they use the BCH + * SW library. + */ + bch_priv.control = init_bch(13, 8, 0x201b /* hw polynominal */); + if (!bch_priv.control) { + puts("Could not init_bch()\n"); + return -ENODEV; + } +#endif /* BCH info that will be correct for SPL or overridden otherwise. */ nand->priv = &bch_priv; #endif /* Default ECC mode */ -#ifdef CONFIG_AM33XX +#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) nand->ecc.mode = NAND_ECC_HW; nand->ecc.layout = &hw_bch8_nand_oob; nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; @@ -748,7 +937,9 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.hwctl = omap_enable_ecc_bch; nand->ecc.correct = omap_correct_data_bch; nand->ecc.calculate = omap_calculate_ecc_bch; +#ifdef CONFIG_AM33XX nand->ecc.read_page = omap_read_page_bch; +#endif omap_hwecc_init_bch(nand, NAND_ECC_READ); #else #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC) diff --git a/drivers/mtd/nand/s3c64xx.c b/drivers/mtd/nand/s3c64xx.c deleted file mode 100644 index 87f0341..0000000 --- a/drivers/mtd/nand/s3c64xx.c +++ /dev/null @@ -1,295 +0,0 @@ -/* - * (C) Copyright 2006 DENX Software Engineering - * - * Implementation for U-Boot 1.1.6 by Samsung - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#include <nand.h> -#include <linux/mtd/nand.h> - -#include <asm/arch/s3c6400.h> - -#include <asm/io.h> -#include <asm/errno.h> - -#define MAX_CHIPS 2 -static int nand_cs[MAX_CHIPS] = {0, 1}; - -#ifdef CONFIG_NAND_SPL -#define printf(arg...) do {} while (0) -#endif - -/* Nand flash definition values by jsgood */ -#ifdef S3C_NAND_DEBUG -/* - * Function to print out oob buffer for debugging - * Written by jsgood - */ -static void print_oob(const char *header, struct mtd_info *mtd) -{ - int i; - struct nand_chip *chip = mtd->priv; - - printf("%s:\t", header); - - for (i = 0; i < 64; i++) - printf("%02x ", chip->oob_poi[i]); - - printf("\n"); -} -#endif /* S3C_NAND_DEBUG */ - -static void s3c_nand_select_chip(struct mtd_info *mtd, int chip) -{ - int ctrl = readl(NFCONT); - - switch (chip) { - case -1: - ctrl |= 6; - break; - case 0: - ctrl &= ~2; - break; - case 1: - ctrl &= ~4; - break; - default: - return; - } - - writel(ctrl, NFCONT); -} - -/* - * Hardware specific access to control-lines function - * Written by jsgood - */ -static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (ctrl & NAND_CTRL_CHANGE) { - if (ctrl & NAND_CLE) - this->IO_ADDR_W = (void __iomem *)NFCMMD; - else if (ctrl & NAND_ALE) - this->IO_ADDR_W = (void __iomem *)NFADDR; - else - this->IO_ADDR_W = (void __iomem *)NFDATA; - if (ctrl & NAND_NCE) - s3c_nand_select_chip(mtd, *(int *)this->priv); - else - s3c_nand_select_chip(mtd, -1); - } - - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - -/* - * Function for checking device ready pin - * Written by jsgood - */ -static int s3c_nand_device_ready(struct mtd_info *mtdinfo) -{ - return !!(readl(NFSTAT) & NFSTAT_RnB); -} - -#ifdef CONFIG_SYS_S3C_NAND_HWECC -/* - * This function is called before encoding ecc codes to ready ecc engine. - * Written by jsgood - */ -static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode) -{ - u_long nfcont, nfconf; - - /* - * The original driver used 4-bit ECC for "new" MLC chips, i.e., for - * those with non-zero ID[3][3:2], which anyway only holds for ST - * (Numonyx) chips - */ - nfconf = readl(NFCONF) & ~NFCONF_ECC_4BIT; - - writel(nfconf, NFCONF); - - /* Initialize & unlock */ - nfcont = readl(NFCONT); - nfcont |= NFCONT_INITECC; - nfcont &= ~NFCONT_MECCLOCK; - - if (mode == NAND_ECC_WRITE) - nfcont |= NFCONT_ECC_ENC; - else if (mode == NAND_ECC_READ) - nfcont &= ~NFCONT_ECC_ENC; - - writel(nfcont, NFCONT); -} - -/* - * This function is called immediately after encoding ecc codes. - * This function returns encoded ecc codes. - * Written by jsgood - */ -static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, - u_char *ecc_code) -{ - u_long nfcont, nfmecc0; - - /* Lock */ - nfcont = readl(NFCONT); - nfcont |= NFCONT_MECCLOCK; - writel(nfcont, NFCONT); - - nfmecc0 = readl(NFMECC0); - - ecc_code[0] = nfmecc0 & 0xff; - ecc_code[1] = (nfmecc0 >> 8) & 0xff; - ecc_code[2] = (nfmecc0 >> 16) & 0xff; - ecc_code[3] = (nfmecc0 >> 24) & 0xff; - - return 0; -} - -/* - * This function determines whether read data is good or not. - * If SLC, must write ecc codes to controller before reading status bit. - * If MLC, status bit is already set, so only reading is needed. - * If status bit is good, return 0. - * If correctable errors occured, do that. - * If uncorrectable errors occured, return -1. - * Written by jsgood - */ -static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat, - u_char *read_ecc, u_char *calc_ecc) -{ - int ret = -1; - u_long nfestat0, nfmeccdata0, nfmeccdata1, err_byte_addr; - u_char err_type, repaired; - - /* SLC: Write ecc to compare */ - nfmeccdata0 = (calc_ecc[1] << 16) | calc_ecc[0]; - nfmeccdata1 = (calc_ecc[3] << 16) | calc_ecc[2]; - writel(nfmeccdata0, NFMECCDATA0); - writel(nfmeccdata1, NFMECCDATA1); - - /* Read ecc status */ - nfestat0 = readl(NFESTAT0); - err_type = nfestat0 & 0x3; - - switch (err_type) { - case 0: /* No error */ - ret = 0; - break; - - case 1: - /* - * 1 bit error (Correctable) - * (nfestat0 >> 7) & 0x7ff :error byte number - * (nfestat0 >> 4) & 0x7 :error bit number - */ - err_byte_addr = (nfestat0 >> 7) & 0x7ff; - repaired = dat[err_byte_addr] ^ (1 << ((nfestat0 >> 4) & 0x7)); - - printf("S3C NAND: 1 bit error detected at byte %ld. " - "Correcting from 0x%02x to 0x%02x...OK\n", - err_byte_addr, dat[err_byte_addr], repaired); - - dat[err_byte_addr] = repaired; - - ret = 1; - break; - - case 2: /* Multiple error */ - case 3: /* ECC area error */ - printf("S3C NAND: ECC uncorrectable error detected. " - "Not correctable.\n"); - ret = -1; - break; - } - - return ret; -} -#endif /* CONFIG_SYS_S3C_NAND_HWECC */ - -/* - * Board-specific NAND initialization. The following members of the - * argument are board-specific (per include/linux/mtd/nand.h): - * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device - * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device - * - hwcontrol: hardwarespecific function for accesing control-lines - * - dev_ready: hardwarespecific function for accesing device ready/busy line - * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must - * only be provided if a hardware ECC is available - * - eccmode: mode of ecc, see defines - * - chip_delay: chip dependent delay for transfering data from array to - * read regs (tR) - * - options: various chip options. They can partly be set to inform - * nand_scan about special functionality. See the defines for further - * explanation - * Members with a "?" were not set in the merged testing-NAND branch, - * so they are not set here either. - */ -int board_nand_init(struct nand_chip *nand) -{ - static int chip_n; - - if (chip_n >= MAX_CHIPS) - return -ENODEV; - - NFCONT_REG = (NFCONT_REG & ~NFCONT_WP) | NFCONT_ENABLE | 0x6; - - nand->IO_ADDR_R = (void __iomem *)NFDATA; - nand->IO_ADDR_W = (void __iomem *)NFDATA; - nand->cmd_ctrl = s3c_nand_hwcontrol; - nand->dev_ready = s3c_nand_device_ready; - nand->select_chip = s3c_nand_select_chip; - nand->options = 0; -#ifdef CONFIG_NAND_SPL - nand->read_byte = nand_read_byte; - nand->write_buf = nand_write_buf; - nand->read_buf = nand_read_buf; -#endif - -#ifdef CONFIG_SYS_S3C_NAND_HWECC - nand->ecc.hwctl = s3c_nand_enable_hwecc; - nand->ecc.calculate = s3c_nand_calculate_ecc; - nand->ecc.correct = s3c_nand_correct_data; - - /* - * If you get more than 1 NAND-chip with different page-sizes on the - * board one day, it will get more complicated... - */ - nand->ecc.mode = NAND_ECC_HW; - nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; - nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; -#else - nand->ecc.mode = NAND_ECC_SOFT; -#endif /* ! CONFIG_SYS_S3C_NAND_HWECC */ - - nand->priv = nand_cs + chip_n++; - - return 0; -} diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 1a7b40e..858e322 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -632,10 +632,6 @@ static int onenand_check_bufferram(struct mtd_info *mtd, loff_t addr) int blockpage, found = 0; unsigned int i; -#ifdef CONFIG_S3C64XX - return 0; -#endif - if (ONENAND_IS_2PLANE(this)) blockpage = onenand_get_2x_blockpage(mtd, addr); else diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c index 0d94ea5..5eb2b3a 100644 --- a/drivers/mtd/onenand/samsung.c +++ b/drivers/mtd/onenand/samsung.c @@ -1,5 +1,5 @@ /* - * S3C64XX/S5PC100 OneNAND driver at U-Boot + * S5PC100 OneNAND driver at U-Boot * * Copyright (C) 2008-2009 Samsung Electronics * Kyungmin Park <kyungmin.park@samsung.com> @@ -62,12 +62,7 @@ do { \ #define ONENAND_MAIN_SPARE_ACCESS 0x16 #define ONENAND_PIPELINE_READ 0x4000 -#if defined(CONFIG_S3C64XX) -#define MAP_00 (0x0 << 24) -#define MAP_01 (0x1 << 24) -#define MAP_10 (0x2 << 24) -#define MAP_11 (0x3 << 24) -#elif defined(CONFIG_S5P) +#if defined(CONFIG_S5P) #define MAP_00 (0x0 << 26) #define MAP_01 (0x1 << 26) #define MAP_10 (0x2 << 26) @@ -116,12 +111,7 @@ static void s3c_write_cmd(int value, unsigned int cmd) * return the buffer address on the memory device * It will be combined with CMD_MAP_XX */ -#if defined(CONFIG_S3C64XX) -static unsigned int s3c_mem_addr(int fba, int fpa, int fsa) -{ - return (fba << 12) | (fpa << 6) | (fsa << 4); -} -#elif defined(CONFIG_S5P) +#if defined(CONFIG_S5P) static unsigned int s3c_mem_addr(int fba, int fpa, int fsa) { return (fba << 13) | (fpa << 7) | (fsa << 5); @@ -550,45 +540,6 @@ static void s3c_onenand_unlock_all(struct mtd_info *mtd) s3c_onenand_check_lock_status(mtd); } -#ifdef CONFIG_S3C64XX -static void s3c_set_width_regs(struct onenand_chip *this) -{ - int dev_id, density; - int fba, fpa, fsa; - int dbs_dfs; - - dev_id = DEVICE_ID0_REG; - - density = (dev_id >> ONENAND_DEVICE_DENSITY_SHIFT) & 0xf; - dbs_dfs = !!(dev_id & ONENAND_DEVICE_IS_DDP); - - fba = density + 7; - if (dbs_dfs) - fba--; /* Decrease the fba */ - fpa = 6; - if (density >= ONENAND_DEVICE_DENSITY_512Mb) - fsa = 2; - else - fsa = 1; - - DPRINTK("FBA %lu, FPA %lu, FSA %lu, DDP %lu", - FBA_WIDTH0_REG, FPA_WIDTH0_REG, FSA_WIDTH0_REG, - DDP_DEVICE_REG); - - DPRINTK("mem_cfg0 0x%lx, sync mode %lu, " - "dev_page_size %lu, BURST LEN %lu", - MEM_CFG0_REG, SYNC_MODE_REG, - DEV_PAGE_SIZE_REG, BURST_LEN0_REG); - - DEV_PAGE_SIZE_REG = 0x1; - - FBA_WIDTH0_REG = fba; - FPA_WIDTH0_REG = fpa; - FSA_WIDTH0_REG = fsa; - DBS_DFS_WIDTH0_REG = dbs_dfs; -} -#endif - int s5pc110_chip_probe(struct mtd_info *mtd) { return 0; @@ -620,10 +571,7 @@ void s3c_onenand_init(struct mtd_info *mtd) onenand->mtd = mtd; -#if defined(CONFIG_S3C64XX) - onenand->base = (void *)0x70100000; - onenand->ahb_addr = (void *)0x20000000; -#elif defined(CONFIG_S5P) +#if defined(CONFIG_S5P) onenand->base = (void *)0xE7100000; onenand->ahb_addr = (void *)0xB0000000; #endif diff --git a/drivers/mtd/spi/atmel.c b/drivers/mtd/spi/atmel.c index 006f6d5..6a92c4b 100644 --- a/drivers/mtd/spi/atmel.c +++ b/drivers/mtd/spi/atmel.c @@ -480,15 +480,13 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode) return NULL; } - asf = malloc(sizeof(struct atmel_spi_flash)); + asf = spi_flash_alloc(struct atmel_spi_flash, spi, params->name); if (!asf) { debug("SF: Failed to allocate memory\n"); return NULL; } asf->params = params; - asf->flash.spi = spi; - asf->flash.name = params->name; /* Assuming power-of-two page size initially. */ page_size = 1 << params->l2_page_size; @@ -513,7 +511,6 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode) asf->flash.erase = dataflash_erase_at45; page_size += 1 << (params->l2_page_size - 5); } else { - asf->flash.read = spi_flash_cmd_read_fast; asf->flash.write = dataflash_write_p2; asf->flash.erase = dataflash_erase_p2; } @@ -524,9 +521,6 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode) case DF_FAMILY_AT26F: case DF_FAMILY_AT26DF: - asf->flash.read = spi_flash_cmd_read_fast; - asf->flash.write = spi_flash_cmd_write_multi; - asf->flash.erase = spi_flash_cmd_erase; asf->flash.page_size = page_size; asf->flash.sector_size = 4096; /* clear SPRL# bit for locked flash */ diff --git a/drivers/mtd/spi/eon.c b/drivers/mtd/spi/eon.c index 691ed4e..b16e7ab 100644 --- a/drivers/mtd/spi/eon.c +++ b/drivers/mtd/spi/eon.c @@ -46,18 +46,12 @@ struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) return NULL; } - flash = malloc(sizeof(*flash)); + flash = spi_flash_alloc_base(spi, params->name); if (!flash) { debug("SF: Failed to allocate memory\n"); return NULL; } - flash->spi = spi; - flash->name = params->name; - - flash->write = spi_flash_cmd_write_multi; - flash->erase = spi_flash_cmd_erase; - flash->read = spi_flash_cmd_read_fast; flash->page_size = 256; flash->sector_size = 256 * 16 * 16; flash->size = 256 * 16 diff --git a/drivers/mtd/spi/macronix.c b/drivers/mtd/spi/macronix.c index c97a39d..036c30d 100644 --- a/drivers/mtd/spi/macronix.c +++ b/drivers/mtd/spi/macronix.c @@ -97,18 +97,12 @@ struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode) return NULL; } - flash = malloc(sizeof(*flash)); + flash = spi_flash_alloc_base(spi, params->name); if (!flash) { debug("SF: Failed to allocate memory\n"); return NULL; } - flash->spi = spi; - flash->name = params->name; - - flash->write = spi_flash_cmd_write_multi; - flash->erase = spi_flash_cmd_erase; - flash->read = spi_flash_cmd_read_fast; flash->page_size = 256; flash->sector_size = 256 * 16 * 16; flash->size = flash->sector_size * params->nr_blocks; diff --git a/drivers/mtd/spi/ramtron.c b/drivers/mtd/spi/ramtron.c index 0999781..5299a6d 100644 --- a/drivers/mtd/spi/ramtron.c +++ b/drivers/mtd/spi/ramtron.c @@ -284,15 +284,13 @@ struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode) return NULL; found: - sn = malloc(sizeof(*sn)); + sn = spi_flash_alloc(struct ramtron_spi_fram, spi, params->name); if (!sn) { debug("SF: Failed to allocate memory\n"); return NULL; } sn->params = params; - sn->flash.spi = spi; - sn->flash.name = params->name; sn->flash.write = ramtron_write; sn->flash.read = ramtron_read; diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c index 9288672..bc558c4 100644 --- a/drivers/mtd/spi/spansion.c +++ b/drivers/mtd/spi/spansion.c @@ -128,18 +128,12 @@ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) return NULL; } - flash = malloc(sizeof(*flash)); + flash = spi_flash_alloc_base(spi, params->name); if (!flash) { debug("SF: Failed to allocate memory\n"); return NULL; } - flash->spi = spi; - flash->name = params->name; - - flash->write = spi_flash_cmd_write_multi; - flash->erase = spi_flash_cmd_erase; - flash->read = spi_flash_cmd_read_fast; flash->page_size = 256; flash->sector_size = 256 * params->pages_per_sector; flash->size = flash->sector_size * params->nr_sectors; diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 00aece9..111185a 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -8,6 +8,7 @@ */ #include <common.h> +#include <fdtdec.h> #include <malloc.h> #include <spi.h> #include <spi_flash.h> @@ -15,6 +16,8 @@ #include "spi_flash_internal.h" +DECLARE_GLOBAL_DATA_PTR; + static void spi_flash_addr(u32 addr, u8 *cmd) { /* cmd[0] is actual command */ @@ -87,6 +90,9 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); + if (flash->spi->max_write_size) + chunk_len = min(chunk_len, flash->spi->max_write_size); + cmd[1] = page_addr >> 8; cmd[2] = page_addr; cmd[3] = byte_addr; @@ -111,8 +117,11 @@ int spi_flash_cmd_write_multi(struct spi_flash *flash, u32 offset, if (ret) break; - page_addr++; - byte_addr = 0; + byte_addr += chunk_len; + if (byte_addr == page_size) { + page_addr++; + byte_addr = 0; + } } debug("SF: program %s %zu bytes @ %#x\n", @@ -140,6 +149,10 @@ int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, { u8 cmd[5]; + /* Handle memory-mapped SPI */ + if (flash->memory_map) + memcpy(data, flash->memory_map + offset, len); + cmd[0] = CMD_READ_ARRAY_FAST; spi_flash_addr(offset, cmd); cmd[4] = 0x00; @@ -269,6 +282,34 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) return 0; } +#ifdef CONFIG_OF_CONTROL +int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash) +{ + fdt_addr_t addr; + fdt_size_t size; + int node; + + /* If there is no node, do nothing */ + node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH); + if (node < 0) + return 0; + + addr = fdtdec_get_addr_size(blob, node, "memory-map", &size); + if (addr == FDT_ADDR_T_NONE) { + debug("%s: Cannot decode address\n", __func__); + return 0; + } + + if (flash->size != size) { + debug("%s: Memory map must cover entire device\n", __func__); + return -1; + } + flash->memory_map = (void *)addr; + + return 0; +} +#endif /* CONFIG_OF_CONTROL */ + /* * The following table holds all device probe functions * @@ -385,9 +426,18 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, goto err_manufacturer_probe; } +#ifdef CONFIG_OF_CONTROL + if (spi_flash_decode_fdt(gd->fdt_blob, flash)) { + debug("SF: FDT decode error\n"); + goto err_manufacturer_probe; + } +#endif printf("SF: Detected %s with page size ", flash->name); print_size(flash->sector_size, ", total "); - print_size(flash->size, "\n"); + print_size(flash->size, ""); + if (flash->memory_map) + printf(", mapped at %p", flash->memory_map); + puts("\n"); spi_release_bus(spi); @@ -401,6 +451,31 @@ err_claim_bus: return NULL; } +void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi, + const char *name) +{ + struct spi_flash *flash; + void *ptr; + + ptr = malloc(size); + if (!ptr) { + debug("SF: Failed to allocate memory\n"); + return NULL; + } + memset(ptr, '\0', size); + flash = (struct spi_flash *)(ptr + offset); + + /* Set up some basic fields - caller will sort out sizes */ + flash->spi = spi; + flash->name = name; + + flash->read = spi_flash_cmd_read_fast; + flash->write = spi_flash_cmd_write_multi; + flash->erase = spi_flash_cmd_erase; + + return flash; +} + void spi_flash_free(struct spi_flash *flash) { spi_free_slave(flash->spi); diff --git a/drivers/mtd/spi/sst.c b/drivers/mtd/spi/sst.c index ced4f24..95f5490 100644 --- a/drivers/mtd/spi/sst.c +++ b/drivers/mtd/spi/sst.c @@ -203,22 +203,16 @@ spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode) return NULL; } - stm = malloc(sizeof(*stm)); + stm = spi_flash_alloc(struct sst_spi_flash, spi, params->name); if (!stm) { debug("SF: Failed to allocate memory\n"); return NULL; } stm->params = params; - stm->flash.spi = spi; - stm->flash.name = params->name; if (stm->params->flags & SST_FEAT_WP) stm->flash.write = sst_write_wp; - else - stm->flash.write = spi_flash_cmd_write_multi; - stm->flash.erase = spi_flash_cmd_erase; - stm->flash.read = spi_flash_cmd_read_fast; stm->flash.page_size = 256; stm->flash.sector_size = 4096; stm->flash.size = stm->flash.sector_size * params->nr_sectors; diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c index 8a19344..2a9972b 100644 --- a/drivers/mtd/spi/stmicro.c +++ b/drivers/mtd/spi/stmicro.c @@ -176,18 +176,12 @@ struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) return NULL; } - flash = malloc(sizeof(*flash)); + flash = spi_flash_alloc_base(spi, params->name); if (!flash) { debug("SF: Failed to allocate memory\n"); return NULL; } - flash->spi = spi; - flash->name = params->name; - - flash->write = spi_flash_cmd_write_multi; - flash->erase = spi_flash_cmd_erase; - flash->read = spi_flash_cmd_read_fast; flash->page_size = 256; flash->sector_size = 256 * params->pages_per_sector; flash->size = flash->sector_size * params->nr_sectors; diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c index 4418302..2716209 100644 --- a/drivers/mtd/spi/winbond.c +++ b/drivers/mtd/spi/winbond.c @@ -68,6 +68,11 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { .name = "W25Q80", }, { + .id = 0x6016, + .nr_blocks = 512, + .name = "W25Q32DW", + }, + { .id = 0x6017, .nr_blocks = 128, .name = "W25Q64DW", @@ -92,18 +97,12 @@ struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) return NULL; } - flash = malloc(sizeof(*flash)); + flash = spi_flash_alloc_base(spi, params->name); if (!flash) { debug("SF: Failed to allocate memory\n"); return NULL; } - flash->spi = spi; - flash->name = params->name; - - flash->write = spi_flash_cmd_write_multi; - flash->erase = spi_flash_cmd_erase; - flash->read = spi_flash_cmd_read_fast; flash->page_size = 256; flash->sector_size = 4096; flash->size = 4096 * 16 * params->nr_blocks; diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index d144ac2..a708162 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -478,19 +478,19 @@ static int attach_by_scanning(struct ubi_device *ubi) err = ubi_eba_init_scan(ubi, si); if (err) - goto out_wl; + goto out_vtbl; err = ubi_wl_init_scan(ubi, si); if (err) - goto out_vtbl; + goto out_eba; ubi_scan_destroy_si(si); return 0; +out_eba: + ubi_eba_close(ubi); out_vtbl: vfree(ubi->vtbl); -out_wl: - ubi_wl_close(ubi); out_si: ubi_scan_destroy_si(si); return err; diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h index 14c3a5f..044e849 100644 --- a/drivers/mtd/ubi/ubi.h +++ b/drivers/mtd/ubi/ubi.h @@ -59,7 +59,11 @@ #define UBI_NAME_STR "ubi" /* Normal UBI messages */ +#ifdef CONFIG_UBI_SILENCE_MSG +#define ubi_msg(fmt, ...) +#else #define ubi_msg(fmt, ...) printk(KERN_NOTICE "UBI: " fmt "\n", ##__VA_ARGS__) +#endif /* UBI warning messages */ #define ubi_warn(fmt, ...) printk(KERN_WARNING "UBI warning: %s: " fmt "\n", \ __func__, ##__VA_ARGS__) diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c index 88b867a..d1ba722 100644 --- a/drivers/mtd/ubi/wl.c +++ b/drivers/mtd/ubi/wl.c @@ -1538,6 +1538,7 @@ int ubi_wl_init_scan(struct ubi_device *ubi, struct ubi_scan_info *si) if (ubi->avail_pebs < WL_RESERVED_PEBS) { ubi_err("no enough physical eraseblocks (%d, need %d)", ubi->avail_pebs, WL_RESERVED_PEBS); + err = -ENOSPC; goto out_free; } ubi->avail_pebs -= WL_RESERVED_PEBS; diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c index ed7cf20..89ebf0b 100644 --- a/drivers/net/armada100_fec.c +++ b/drivers/net/armada100_fec.c @@ -100,7 +100,7 @@ static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg, } /* wait for the SMI register to become available */ - if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) { + if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) { printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__); return -1; } @@ -108,7 +108,7 @@ static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg, writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, ®s->smi); /* now wait for the data to be valid */ - if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, TRUE)) { + if (armdfec_phy_timeout(®s->smi, SMI_R_VALID, true)) { val = readl(®s->smi); printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n", __func__, val); @@ -143,7 +143,7 @@ static int smi_reg_write(const char *devname, } /* wait for the SMI register to become available */ - if (armdfec_phy_timeout(®s->smi, SMI_BUSY, FALSE)) { + if (armdfec_phy_timeout(®s->smi, SMI_BUSY, false)) { printf("ARMD100 FEC: (%s) PHY busy timeout\n", __func__); return -1; } diff --git a/drivers/net/armada100_fec.h b/drivers/net/armada100_fec.h index e2df4fc..dcac964 100644 --- a/drivers/net/armada100_fec.h +++ b/drivers/net/armada100_fec.h @@ -29,13 +29,6 @@ #ifndef __ARMADA100_FEC_H__ #define __ARMADA100_FEC_H__ -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - #define PORT_NUM 0x0 /* RX & TX descriptor command */ diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 93f8417..7a36850 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -24,6 +24,7 @@ #include <asm/errno.h> #include <asm/io.h> #include <phy.h> +#include <asm/arch/cpu.h> #define BITMASK(bits) (BIT(bits) - 1) #define PHY_REG_MASK 0x1f diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 8ba98b2..c1863f4 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -313,14 +313,14 @@ void e1000_standby_eeprom(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code ****************************************************************************/ -static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) +static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) { uint32_t eecd = 0; DEBUGFUNC(); if (hw->mac_type == e1000_ich8lan) - return FALSE; + return false; if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { eecd = E1000_READ_REG(hw, EECD); @@ -330,9 +330,9 @@ static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) /* If both bits are set, device is Flash type */ if (eecd == 0x03) - return FALSE; + return false; } - return TRUE; + return true; } /****************************************************************************** @@ -421,8 +421,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->opcode_bits = 3; eeprom->address_bits = 6; eeprom->delay_usec = 50; - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = false; + eeprom->use_eewr = false; break; case e1000_82540: case e1000_82545: @@ -439,8 +439,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->word_size = 64; eeprom->address_bits = 6; } - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = false; + eeprom->use_eewr = false; break; case e1000_82541: case e1000_82541_rev_2: @@ -469,8 +469,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->address_bits = 6; } } - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = false; + eeprom->use_eewr = false; break; case e1000_82571: case e1000_82572: @@ -484,8 +484,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->page_size = 8; eeprom->address_bits = 8; } - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = false; + eeprom->use_eewr = false; break; case e1000_82573: case e1000_82574: @@ -499,9 +499,9 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->page_size = 8; eeprom->address_bits = 8; } - eeprom->use_eerd = TRUE; - eeprom->use_eewr = TRUE; - if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { + eeprom->use_eerd = true; + eeprom->use_eewr = true; + if (e1000_is_onboard_nvm_eeprom(hw) == false) { eeprom->type = e1000_eeprom_flash; eeprom->word_size = 2048; @@ -522,8 +522,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) eeprom->page_size = 8; eeprom->address_bits = 8; } - eeprom->use_eerd = TRUE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = true; + eeprom->use_eewr = false; break; /* ich8lan does not support currently. if needed, please @@ -535,8 +535,8 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) int32_t i = 0; eeprom->type = e1000_eeprom_ich8; - eeprom->use_eerd = FALSE; - eeprom->use_eewr = FALSE; + eeprom->use_eerd = false; + eeprom->use_eewr = false; eeprom->word_size = E1000_SHADOW_RAM_WORDS; uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); @@ -544,7 +544,7 @@ static int32_t e1000_init_eeprom_params(struct e1000_hw *hw) * so as to save time for driver init */ if (hw->eeprom_shadow_ram != NULL) { for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { - hw->eeprom_shadow_ram[i].modified = FALSE; + hw->eeprom_shadow_ram[i].modified = false; hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; } } @@ -779,8 +779,8 @@ e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, * directly. In this case, we need to acquire the EEPROM so that * FW or other port software does not interrupt. */ - if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && - hw->eeprom.use_eerd == FALSE) { + if (e1000_is_onboard_nvm_eeprom(hw) == true && + hw->eeprom.use_eerd == false) { /* Prepare the EEPROM for bit-bang reading */ if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) @@ -788,7 +788,7 @@ e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, } /* Eerd register EEPROM access requires no eeprom aquire/release */ - if (eeprom->use_eerd == TRUE) + if (eeprom->use_eerd == true) return e1000_read_eeprom_eerd(hw, offset, words, data); /* ich8lan does not support currently. if needed, please @@ -935,7 +935,7 @@ e1000_set_phy_mode(struct e1000_hw *hw) if (ret_val) return ret_val; - hw->phy_reset_disable = FALSE; + hw->phy_reset_disable = false; } } @@ -1098,17 +1098,17 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) return E1000_SUCCESS; } -static boolean_t e1000_is_second_port(struct e1000_hw *hw) +static bool e1000_is_second_port(struct e1000_hw *hw) { switch (hw->mac_type) { case e1000_80003es2lan: case e1000_82546: case e1000_82571: if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) - return TRUE; + return true; /* Fallthrough */ default: - return FALSE; + return false; } } @@ -1373,7 +1373,7 @@ e1000_reset_hw(struct e1000_hw *hw) E1000_WRITE_FLUSH(hw); /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ - hw->tbi_compatibility_on = FALSE; + hw->tbi_compatibility_on = false; /* Delay to allow any outstanding PCI transactions to complete before * resetting the device @@ -2098,7 +2098,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw) hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) - hw->phy_reset_disable = FALSE; + hw->phy_reset_disable = false; return E1000_SUCCESS; } @@ -2118,7 +2118,7 @@ e1000_copper_link_preconfig(struct e1000_hw *hw) ****************************************************************************/ static int32_t -e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active) +e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active) { uint32_t phy_ctrl = 0; int32_t ret_val; @@ -2253,7 +2253,7 @@ e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active) ****************************************************************************/ static int32_t -e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active) +e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active) { uint32_t phy_ctrl = 0; int32_t ret_val; @@ -2378,7 +2378,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw) /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ if (hw->phy_type == e1000_phy_igp) { /* disable lplu d3 during driver init */ - ret_val = e1000_set_d3_lplu_state(hw, FALSE); + ret_val = e1000_set_d3_lplu_state(hw, false); if (ret_val) { DEBUGOUT("Error Disabling LPLU D3\n"); return ret_val; @@ -2386,7 +2386,7 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw) } /* disable lplu d0 during driver init */ - ret_val = e1000_set_d0_lplu_state(hw, FALSE); + ret_val = e1000_set_d0_lplu_state(hw, false); if (ret_val) { DEBUGOUT("Error Disabling LPLU D0\n"); return ret_val; @@ -2495,9 +2495,9 @@ e1000_copper_link_igp_setup(struct e1000_hw *hw) /***************************************************************************** * This function checks the mode of the firmware. * - * returns - TRUE when the mode is IAMT or FALSE. + * returns - true when the mode is IAMT or false. ****************************************************************************/ -boolean_t +bool e1000_check_mng_mode(struct e1000_hw *hw) { uint32_t fwsm; @@ -2508,12 +2508,12 @@ e1000_check_mng_mode(struct e1000_hw *hw) if (hw->mac_type == e1000_ich8lan) { if ((fwsm & E1000_FWSM_MODE_MASK) == (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) - return TRUE; + return true; } else if ((fwsm & E1000_FWSM_MODE_MASK) == (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) - return TRUE; + return true; - return FALSE; + return false; } static int32_t @@ -2675,7 +2675,7 @@ e1000_copper_link_ggp_setup(struct e1000_hw *hw) * firmware will have already initialized them. We only initialize * them if the HW is not in IAMT mode. */ - if (e1000_check_mng_mode(hw) == FALSE) { + if (e1000_check_mng_mode(hw) == false) { /* Enable Electrical Idle on the PHY */ phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; ret_val = e1000_write_phy_reg(hw, @@ -2879,7 +2879,7 @@ e1000_copper_link_autoneg(struct e1000_hw *hw) } } - hw->get_link_status = TRUE; + hw->get_link_status = true; return E1000_SUCCESS; } @@ -3598,7 +3598,7 @@ e1000_check_for_link(struct eth_device *nic) } if (phy_data & MII_SR_LINK_STATUS) { - hw->get_link_status = FALSE; + hw->get_link_status = false; } else { /* No link detected */ return -E1000_ERR_NOLINK; @@ -3661,7 +3661,7 @@ e1000_check_for_link(struct eth_device *nic) rctl = E1000_READ_REG(hw, RCTL); rctl &= ~E1000_RCTL_SBP; E1000_WRITE_REG(hw, RCTL, rctl); - hw->tbi_compatibility_on = FALSE; + hw->tbi_compatibility_on = false; } } else { /* If TBI compatibility is was previously off, turn it on. For @@ -3670,7 +3670,7 @@ e1000_check_for_link(struct eth_device *nic) * will look like CRC errors to to the hardware. */ if (!hw->tbi_compatibility_on) { - hw->tbi_compatibility_on = TRUE; + hw->tbi_compatibility_on = true; rctl = E1000_READ_REG(hw, RCTL); rctl |= E1000_RCTL_SBP; E1000_WRITE_REG(hw, RCTL, rctl); @@ -4569,7 +4569,7 @@ e1000_detect_gig_phy(struct e1000_hw *hw) { int32_t phy_init_status, ret_val; uint16_t phy_id_high, phy_id_low; - boolean_t match = FALSE; + bool match = false; DEBUGFUNC(); @@ -4609,11 +4609,11 @@ e1000_detect_gig_phy(struct e1000_hw *hw) switch (hw->mac_type) { case e1000_82543: if (hw->phy_id == M88E1000_E_PHY_ID) - match = TRUE; + match = true; break; case e1000_82544: if (hw->phy_id == M88E1000_I_PHY_ID) - match = TRUE; + match = true; break; case e1000_82540: case e1000_82545: @@ -4621,37 +4621,37 @@ e1000_detect_gig_phy(struct e1000_hw *hw) case e1000_82546: case e1000_82546_rev_3: if (hw->phy_id == M88E1011_I_PHY_ID) - match = TRUE; + match = true; break; case e1000_82541: case e1000_82541_rev_2: case e1000_82547: case e1000_82547_rev_2: if(hw->phy_id == IGP01E1000_I_PHY_ID) - match = TRUE; + match = true; break; case e1000_82573: if (hw->phy_id == M88E1111_I_PHY_ID) - match = TRUE; + match = true; break; case e1000_82574: if (hw->phy_id == BME1000_E_PHY_ID) - match = TRUE; + match = true; break; case e1000_80003es2lan: if (hw->phy_id == GG82563_E_PHY_ID) - match = TRUE; + match = true; break; case e1000_ich8lan: if (hw->phy_id == IGP03E1000_E_PHY_ID) - match = TRUE; + match = true; if (hw->phy_id == IFE_E_PHY_ID) - match = TRUE; + match = true; if (hw->phy_id == IFE_PLUS_E_PHY_ID) - match = TRUE; + match = true; if (hw->phy_id == IFE_C_E_PHY_ID) - match = TRUE; + match = true; break; default: DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); @@ -4682,7 +4682,7 @@ e1000_set_media_type(struct e1000_hw *hw) if (hw->mac_type != e1000_82543) { /* tbi_compatibility is only valid on 82543 */ - hw->tbi_compatibility_en = FALSE; + hw->tbi_compatibility_en = false; } switch (hw->device_id) { @@ -4714,7 +4714,7 @@ e1000_set_media_type(struct e1000_hw *hw) if (status & E1000_STATUS_TBIMODE) { hw->media_type = e1000_media_type_fiber; /* tbi_compatibility not valid on fiber */ - hw->tbi_compatibility_en = FALSE; + hw->tbi_compatibility_en = false; } else { hw->media_type = e1000_media_type_copper; } @@ -4788,8 +4788,8 @@ e1000_sw_init(struct eth_device *nic) hw->media_type = e1000_media_type_fiber; } - hw->tbi_compatibility_en = TRUE; - hw->wait_autoneg_complete = TRUE; + hw->tbi_compatibility_en = true; + hw->wait_autoneg_complete = true; if (hw->mac_type < e1000_82543) hw->report_tx_early = 0; else @@ -5194,7 +5194,7 @@ e1000_initialize(bd_t * bis) hw->original_fc = e1000_fc_default; hw->autoneg_failed = 0; hw->autoneg = 1; - hw->get_link_status = TRUE; + hw->get_link_status = true; hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); hw->mac_type = e1000_undefined; diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index 1bbae50..6b93c2b 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -89,11 +89,6 @@ int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw, int argc, char * const argv[]); #endif -typedef enum { - FALSE = 0, - TRUE = 1 -} boolean_t; - /* Enumerated types specific to the e1000 hardware */ /* Media Access Controlers */ typedef enum { @@ -340,7 +335,7 @@ struct e1000_phy_stats { Control and Address */ #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */ -#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False +#define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive false Carrier Counter */ #define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnet Counter */ @@ -1040,14 +1035,14 @@ struct e1000_hw_stats { }; struct e1000_eeprom_info { - e1000_eeprom_type type; - uint16_t word_size; - uint16_t opcode_bits; - uint16_t address_bits; - uint16_t delay_usec; - uint16_t page_size; - boolean_t use_eerd; - boolean_t use_eewr; +e1000_eeprom_type type; + uint16_t word_size; + uint16_t opcode_bits; + uint16_t address_bits; + uint16_t delay_usec; + uint16_t page_size; + bool use_eerd; + bool use_eewr; }; typedef enum { @@ -1150,20 +1145,20 @@ struct e1000_hw { #if 0 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; #endif - boolean_t disable_polarity_correction; - boolean_t speed_downgraded; - boolean_t get_link_status; - boolean_t tbi_compatibility_en; - boolean_t tbi_compatibility_on; - boolean_t fc_strict_ieee; - boolean_t fc_send_xon; - boolean_t report_tx_early; - boolean_t phy_reset_disable; - boolean_t initialize_hw_bits_disable; + bool disable_polarity_correction; + bool speed_downgraded; + bool get_link_status; + bool tbi_compatibility_en; + bool tbi_compatibility_on; + bool fc_strict_ieee; + bool fc_send_xon; + bool report_tx_early; + bool phy_reset_disable; + bool initialize_hw_bits_disable; #if 0 - boolean_t adaptive_ifs; - boolean_t ifs_params_forced; - boolean_t in_ifs_mode; + bool adaptive_ifs; + bool ifs_params_forced; + bool in_ifs_mode; #endif e1000_smart_speed smart_speed; e1000_dsp_config dsp_config_state; @@ -1860,11 +1855,11 @@ struct e1000_hw { * Typical use: * ... * if (TBI_ACCEPT) { - * accept_frame = TRUE; + * accept_frame = true; * e1000_tbi_adjust_stats(adapter, MacAddress); * frame_length--; * } else { - * accept_frame = FALSE; + * accept_frame = false; * } * ... */ @@ -2080,7 +2075,7 @@ struct e1000_hw { #define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */ #define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */ #define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */ -#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */ +#define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=false Carrier */ #define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */ #define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */ #define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */ diff --git a/drivers/net/e1000_spi.c b/drivers/net/e1000_spi.c index 5f774f4..93043a1 100644 --- a/drivers/net/e1000_spi.c +++ b/drivers/net/e1000_spi.c @@ -17,7 +17,7 @@ * never return an error. */ static int e1000_spi_xfer(struct e1000_hw *hw, unsigned int bitlen, - const void *dout_mem, void *din_mem, boolean_t intr) + const void *dout_mem, void *din_mem, bool intr) { const uint8_t *dout = dout_mem; uint8_t *din = din_mem; @@ -145,7 +145,7 @@ int spi_xfer(struct spi_slave *spi, unsigned int bitlen, if (flags & SPI_XFER_BEGIN) e1000_standby_eeprom(hw); - ret = e1000_spi_xfer(hw, bitlen, dout_mem, din_mem, TRUE); + ret = e1000_spi_xfer(hw, bitlen, dout_mem, din_mem, true); if (flags & SPI_XFER_END) e1000_standby_eeprom(hw); @@ -169,7 +169,7 @@ int spi_xfer(struct spi_slave *spi, unsigned int bitlen, #define SPI_EEPROM_STATUS_BUSY 0x01 #define SPI_EEPROM_STATUS_WREN 0x02 -static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, boolean_t intr) +static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, bool intr) { u8 op[] = { SPI_EEPROM_ENABLE_WR }; e1000_standby_eeprom(hw); @@ -181,7 +181,7 @@ static int e1000_spi_eeprom_enable_wr(struct e1000_hw *hw, boolean_t intr) * of the EEPROM commands at this time. */ #if 0 -static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, boolean_t intr) +static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, bool intr) { u8 op[] = { SPI_EEPROM_DISABLE_WR }; e1000_standby_eeprom(hw); @@ -189,7 +189,7 @@ static int e1000_spi_eeprom_disable_wr(struct e1000_hw *hw, boolean_t intr) } static int e1000_spi_eeprom_write_status(struct e1000_hw *hw, - u8 status, boolean_t intr) + u8 status, bool intr) { u8 op[] = { SPI_EEPROM_WRITE_STATUS, status }; e1000_standby_eeprom(hw); @@ -197,7 +197,7 @@ static int e1000_spi_eeprom_write_status(struct e1000_hw *hw, } #endif -static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, boolean_t intr) +static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, bool intr) { u8 op[] = { SPI_EEPROM_READ_STATUS, 0 }; e1000_standby_eeprom(hw); @@ -207,7 +207,7 @@ static int e1000_spi_eeprom_read_status(struct e1000_hw *hw, boolean_t intr) } static int e1000_spi_eeprom_write_page(struct e1000_hw *hw, - const void *data, u16 off, u16 len, boolean_t intr) + const void *data, u16 off, u16 len, bool intr) { u8 op[] = { SPI_EEPROM_WRITE_PAGE, @@ -225,7 +225,7 @@ static int e1000_spi_eeprom_write_page(struct e1000_hw *hw, } static int e1000_spi_eeprom_read_page(struct e1000_hw *hw, - void *data, u16 off, u16 len, boolean_t intr) + void *data, u16 off, u16 len, bool intr) { u8 op[] = { SPI_EEPROM_READ_PAGE, @@ -242,7 +242,7 @@ static int e1000_spi_eeprom_read_page(struct e1000_hw *hw, return 0; } -static int e1000_spi_eeprom_poll_ready(struct e1000_hw *hw, boolean_t intr) +static int e1000_spi_eeprom_poll_ready(struct e1000_hw *hw, bool intr) { int status; while ((status = e1000_spi_eeprom_read_status(hw, intr)) >= 0) { @@ -253,7 +253,7 @@ static int e1000_spi_eeprom_poll_ready(struct e1000_hw *hw, boolean_t intr) } static int e1000_spi_eeprom_dump(struct e1000_hw *hw, - void *data, u16 off, unsigned int len, boolean_t intr) + void *data, u16 off, unsigned int len, bool intr) { /* Interruptibly wait for the EEPROM to be ready */ if (e1000_spi_eeprom_poll_ready(hw, intr)) @@ -282,7 +282,7 @@ static int e1000_spi_eeprom_dump(struct e1000_hw *hw, } static int e1000_spi_eeprom_program(struct e1000_hw *hw, - const void *data, u16 off, u16 len, boolean_t intr) + const void *data, u16 off, u16 len, bool intr) { /* Program each page in sequence */ while (len) { @@ -362,7 +362,7 @@ static int do_e1000_spi_show(cmd_tbl_t *cmdtp, struct e1000_hw *hw, free(buffer); return 1; } - err = e1000_spi_eeprom_dump(hw, buffer, offset, length, TRUE); + err = e1000_spi_eeprom_dump(hw, buffer, offset, length, true); e1000_release_eeprom(hw); if (err) { E1000_ERR(hw->nic, "Interrupted!\n"); @@ -421,7 +421,7 @@ static int do_e1000_spi_dump(cmd_tbl_t *cmdtp, struct e1000_hw *hw, } /* Perform the programming operation */ - if (e1000_spi_eeprom_dump(hw, dest, offset, length, TRUE) < 0) { + if (e1000_spi_eeprom_dump(hw, dest, offset, length, true) < 0) { E1000_ERR(hw->nic, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; @@ -456,7 +456,7 @@ static int do_e1000_spi_program(cmd_tbl_t *cmdtp, struct e1000_hw *hw, } /* Perform the programming operation */ - if (e1000_spi_eeprom_program(hw, source, offset, length, TRUE) < 0) { + if (e1000_spi_eeprom_program(hw, source, offset, length, true) < 0) { E1000_ERR(hw->nic, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; @@ -472,7 +472,7 @@ static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw, { uint16_t i, length, checksum = 0, checksum_reg; uint16_t *buffer; - boolean_t upd; + bool upd; if (argc == 0) upd = 0; @@ -498,7 +498,7 @@ static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw, } /* Read the EEPROM */ - if (e1000_spi_eeprom_dump(hw, buffer, 0, length, TRUE) < 0) { + if (e1000_spi_eeprom_dump(hw, buffer, 0, length, true) < 0) { E1000_ERR(hw->nic, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; @@ -533,7 +533,7 @@ static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw, printf("%s: Reprogramming the EEPROM checksum...\n", hw->nic->name); buffer[i] = cpu_to_le16(checksum); if (e1000_spi_eeprom_program(hw, &buffer[i], i * sizeof(uint16_t), - sizeof(uint16_t), TRUE)) { + sizeof(uint16_t), true)) { E1000_ERR(hw->nic, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; diff --git a/drivers/net/ne2000_base.h b/drivers/net/ne2000_base.h index 5446de4..eee0956 100644 --- a/drivers/net/ne2000_base.h +++ b/drivers/net/ne2000_base.h @@ -79,10 +79,6 @@ are GPL, so this is, of course, GPL. #ifndef __NE2000_BASE_H__ #define __NE2000_BASE_H__ -#define bool int -#define false 0 -#define true 1 - /* * Debugging details * diff --git a/drivers/net/npe/IxEthAcc.c b/drivers/net/npe/IxEthAcc.c index 20d3d9e..7185558 100644 --- a/drivers/net/npe/IxEthAcc.c +++ b/drivers/net/npe/IxEthAcc.c @@ -82,7 +82,7 @@ extern PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex; * @ingroup IxEthAccPri * */ -BOOL ixEthAccServiceInit = FALSE; +BOOL ixEthAccServiceInit = false; /* global filtering bit mask */ PUBLIC UINT32 ixEthAccNewSrcMask; @@ -168,7 +168,7 @@ PUBLIC IxEthAccStatus ixEthAccInit() } /* initialiasation is complete */ - ixEthAccServiceInit = TRUE; + ixEthAccServiceInit = true; return IX_ETH_ACC_SUCCESS; @@ -200,11 +200,11 @@ PUBLIC void ixEthAccUnload(void) /* set all ports as uninitialized */ for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) { - ixEthAccPortData[portId].portInitialized = FALSE; + ixEthAccPortData[portId].portInitialized = false; } /* uninitialize the service */ - ixEthAccServiceInit = FALSE; + ixEthAccServiceInit = false; } } @@ -248,7 +248,7 @@ PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId) * Set the port init flag. */ - ixEthAccPortData[portId].portInitialized = TRUE; + ixEthAccPortData[portId].portInitialized = true; #ifdef CONFIG_IXP425_COMPONENT_ETHDB /* init learning/filtering database structures for this port */ diff --git a/drivers/net/npe/IxEthAccCommon.c b/drivers/net/npe/IxEthAccCommon.c index 211203d..b93a8c8 100644 --- a/drivers/net/npe/IxEthAccCommon.c +++ b/drivers/net/npe/IxEthAccCommon.c @@ -102,7 +102,7 @@ IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate = (IxQMgrCallbackId) 0, /**< Callback tag */ IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - TRUE, /**< Enable Q notification at startup */ + true, /**< Enable Q notification at startup */ IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */ @@ -122,7 +122,7 @@ IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate = (IxQMgrCallbackId) 0, /**< Callback tag */ IX_QMGR_Q_SIZE64, /**< Allocate Smaller Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - TRUE, /**< Enable Q notification at startup */ + true, /**< Enable Q notification at startup */ IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */ @@ -144,7 +144,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= (IxQMgrCallbackId) IX_ETH_PORT_1, IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - FALSE, /**< Disable Q notification at startup */ + false, /**< Disable Q notification at startup */ IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /***< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ @@ -157,7 +157,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= (IxQMgrCallbackId) IX_ETH_PORT_2, IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - FALSE, /**< Disable Q notification at startup */ + false, /**< Disable Q notification at startup */ IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE, /**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ @@ -170,7 +170,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= (IxQMgrCallbackId) IX_ETH_PORT_3, IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - FALSE, /**< Disable Q notification at startup */ + false, /**< Disable Q notification at startup */ IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE, /**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ @@ -183,7 +183,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= (IxQMgrCallbackId) IX_ETH_PORT_1, IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - FALSE, /**< Disable Q notification at startup */ + false, /**< Disable Q notification at startup */ IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE, /**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ @@ -196,7 +196,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= (IxQMgrCallbackId) IX_ETH_PORT_2, IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - FALSE, /**< Disable Q notification at startup */ + false, /**< Disable Q notification at startup */ IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE, /**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ @@ -209,7 +209,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= (IxQMgrCallbackId) IX_ETH_PORT_3, IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /** Queue Entry Sizes - all Q entries are single ord entries */ - FALSE, /** Disable Q notification at startup */ + false, /** Disable Q notification at startup */ IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE, /** Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /* No queues use almost empty */ IX_QMGR_Q_WM_LEVEL64, /** Q High water mark - needed used */ @@ -222,7 +222,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= (IxQMgrCallbackId) 0, IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - TRUE, /**< Enable Q notification at startup */ + true, /**< Enable Q notification at startup */ IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback */ IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ IX_QMGR_Q_WM_LEVEL2, /**< Q High water mark - needed by NPE */ @@ -449,7 +449,7 @@ ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes) /* * Set notification condition for Q */ - if ( qInfoDes->qNotificationEnableAtStartup == TRUE ) + if (qInfoDes->qNotificationEnableAtStartup == true) { if ( ixQMgrNotificationEnable(qInfoDes->qId, qInfoDes->qConditionSource) @@ -513,7 +513,7 @@ IxEthAccStatus ixEthAccQMgrQueuesConfig(void) IxEthDBProperty ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY; IxEthDBPropertyType ixEthDBPropertyType = IX_ETH_DB_INTEGER_PROPERTY; UINT32 ixEthDBParameter = 0; - BOOL completelySorted = FALSE; + BOOL completelySorted = false; /* Fill the corspondance between ports and queues * This defines the mapping from port to queue Ids. @@ -706,7 +706,7 @@ IxEthAccStatus ixEthAccQMgrQueuesConfig(void) do { sortIterations++; - completelySorted = TRUE; + completelySorted = true; for (rxQueue = 0; rxQueue < rxQueueCount - sortIterations; rxQueue++) @@ -732,7 +732,7 @@ IxEthAccStatus ixEthAccQMgrQueuesConfig(void) rxQueues[rxQueue+1].npeId = npeId; rxQueues[rxQueue+1].qId = qId; rxQueues[rxQueue+1].trafficClass = trafficClass; - completelySorted = FALSE; + completelySorted = false; } } } diff --git a/drivers/net/npe/IxEthAccDataPlane.c b/drivers/net/npe/IxEthAccDataPlane.c index b62f0d0..6df3307 100644 --- a/drivers/net/npe/IxEthAccDataPlane.c +++ b/drivers/net/npe/IxEthAccDataPlane.c @@ -948,7 +948,7 @@ IxEthAccStatus ixEthAccPortRxCallbackRegister(IxEthAccPortId portId, for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++) { if ((ixEthAccMacState[port].portDisableState == ACTIVE) - && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == TRUE)) + && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == true)) { /* one of the active ports has a different rx callback type. * Changing the callback type when the port is enabled @@ -977,7 +977,7 @@ IxEthAccStatus ixEthAccPortRxCallbackRegister(IxEthAccPortId portId, return (IX_ETH_ACC_INVALID_ARG); } - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = FALSE; + ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = false; return (IX_ETH_ACC_SUCCESS); } @@ -1025,7 +1025,7 @@ IxEthAccStatus ixEthAccPortMultiBufferRxCallbackRegister( for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++) { if ((ixEthAccMacState[port].portDisableState == ACTIVE) - && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == FALSE)) + && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == false)) { /* one of the active ports has a different rx callback type. * Changing the callback type when the port is enabled @@ -1055,7 +1055,7 @@ IxEthAccStatus ixEthAccPortMultiBufferRxCallbackRegister( return (IX_ETH_ACC_INVALID_ARG); } - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = TRUE; + ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = true; return (IX_ETH_ACC_SUCCESS); } @@ -1456,7 +1456,7 @@ ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr) IX_ETH_ACC_FATAL_LOG( "ixEthRxFrameProcess: Illegal port: %u\n", (UINT32)portId, 0, 0, 0, 0, 0); - return FALSE; + return false; } #endif @@ -1468,7 +1468,7 @@ ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr) if ((flags & (IX_ETHACC_NE_FILTERMASK | IX_ETHACC_NE_NEWSRCMASK)) == 0) { /* "best case" scenario : nothing special to do for this frame */ - return TRUE; + return true; } #ifdef CONFIG_IXP425_COMPONENT_ETHDB @@ -1540,10 +1540,10 @@ ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr) RX_STATS_INC(portId, rxFiltered); /* indicate that frame should not be subjected to further processing */ - return FALSE; + return false; } - return TRUE; + return true; } diff --git a/drivers/net/npe/IxEthAccMac.c b/drivers/net/npe/IxEthAccMac.c index 369ee91..5540b33 100644 --- a/drivers/net/npe/IxEthAccMac.c +++ b/drivers/net/npe/IxEthAccMac.c @@ -304,7 +304,7 @@ ixEthAccPortEnablePriv(IxEthAccPortId portId) /* set the global state */ ixEthAccMacState[portId].portDisableState = ACTIVE; - ixEthAccMacState[portId].enabled = TRUE; + ixEthAccMacState[portId].enabled = true; /* rewrite the setup (including mac filtering) depending * on current options @@ -515,7 +515,7 @@ ixEthAccPortDisableRxCallback (UINT32 cbTag, IxEthAccPortId portId = (IxEthAccPortId)cbTag; /* call the portDisable receive callback */ - (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, FALSE); + (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, false); } PRIVATE void @@ -527,7 +527,7 @@ ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag, while (*mBufPtr) { /* call the portDisable receive callback with one buffer at a time */ - (ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, TRUE); + (ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, true); } } @@ -820,7 +820,7 @@ ixEthAccPortDisablePriv(IxEthAccPortId portId) } /* disable MAC Tx and Rx services */ - ixEthAccMacState[portId].enabled = FALSE; + ixEthAccMacState[portId].enabled = false; ixEthAccMacStateUpdate(portId); /* restore the Rx and TxDone callbacks (within a critical section) */ @@ -869,14 +869,14 @@ ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled) IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0); /* Since Eth NPE is not available, port must be disabled */ - *enabled = FALSE ; + *enabled = false ; return IX_ETH_ACC_SUCCESS ; } if (!IX_ETH_IS_PORT_INITIALIZED(portId)) { /* Since Eth NPE is not available, port must be disabled */ - *enabled = FALSE ; + *enabled = false ; return (IX_ETH_ACC_PORT_UNINITIALIZED); } @@ -1259,7 +1259,7 @@ ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId) IX_ETH_ACC_MAC_RX_CNTRL1, regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN); - ixEthAccMacState[portId].promiscuous = FALSE; + ixEthAccMacState[portId].promiscuous = false; ixEthAccMulticastAddressSet(portId); @@ -1297,7 +1297,7 @@ ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId) IX_ETH_ACC_MAC_RX_CNTRL1, regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN); - ixEthAccMacState[portId].promiscuous = TRUE; + ixEthAccMacState[portId].promiscuous = true; ixEthAccMulticastAddressSet(portId); @@ -1361,7 +1361,7 @@ ixEthAccPortUnicastMacAddressSetPriv (IxEthAccPortId portId, IX_ETH_ACC_MAC_UNI_ADDR_1 + i*sizeof(UINT32), macAddr->macAddress[i]); } - ixEthAccMacState[portId].initDone = TRUE; + ixEthAccMacState[portId].initDone = true; return IX_ETH_ACC_SUCCESS; } @@ -1552,7 +1552,7 @@ ixEthAccPortMulticastAddressJoinAllPriv (IxEthAccPortId portId) IX_IEEE803_MAC_ADDRESS_SIZE); ixEthAccMacState[portId].mcastAddrIndex = 1; - ixEthAccMacState[portId].joinAll = TRUE; + ixEthAccMacState[portId].joinAll = true; ixEthAccMulticastAddressSet(portId); @@ -1599,7 +1599,7 @@ ixEthAccPortMulticastAddressLeavePriv (IxEthAccPortId portId, { if(ixEthAccMacEqual(macAddr, &mcastMacAddr)) { - ixEthAccMacState[portId].joinAll = FALSE; + ixEthAccMacState[portId].joinAll = false; } /*Decrement the index into the multicast address table for the current port*/ @@ -1643,7 +1643,7 @@ ixEthAccPortMulticastAddressLeaveAllPriv (IxEthAccPortId portId) } ixEthAccMacState[portId].mcastAddrIndex = 0; - ixEthAccMacState[portId].joinAll = FALSE; + ixEthAccMacState[portId].joinAll = false; ixEthAccMulticastAddressSet(portId); @@ -1770,7 +1770,7 @@ ixEthAccPortDuplexModeSetPriv (IxEthAccPortId portId, REG_WRITE(ixEthAccMacBase[portId], IX_ETH_ACC_MAC_RX_CNTRL1, rxregval | IX_ETH_ACC_RX_CNTRL1_PAUSE_EN); - ixEthAccMacState[portId].fullDuplex = TRUE; + ixEthAccMacState[portId].fullDuplex = true; } else if (mode == IX_ETH_ACC_HALF_DUPLEX) @@ -1786,7 +1786,7 @@ ixEthAccPortDuplexModeSetPriv (IxEthAccPortId portId, IX_ETH_ACC_MAC_RX_CNTRL1, rxregval & ~IX_ETH_ACC_RX_CNTRL1_PAUSE_EN); - ixEthAccMacState[portId].fullDuplex = FALSE; + ixEthAccMacState[portId].fullDuplex = false; } else { @@ -1876,7 +1876,7 @@ ixEthAccPortTxFrameAppendPaddingEnablePriv (IxEthAccPortId portId) regval | IX_ETH_ACC_TX_CNTRL1_PAD_EN); - ixEthAccMacState[portId].txPADAppend = TRUE; + ixEthAccMacState[portId].txPADAppend = true; return IX_ETH_ACC_SUCCESS; } @@ -1908,7 +1908,7 @@ ixEthAccPortTxFrameAppendPaddingDisablePriv (IxEthAccPortId portId) IX_ETH_ACC_MAC_TX_CNTRL1, regval & ~IX_ETH_ACC_TX_CNTRL1_PAD_EN); - ixEthAccMacState[portId].txPADAppend = FALSE; + ixEthAccMacState[portId].txPADAppend = false; return IX_ETH_ACC_SUCCESS; } @@ -1941,7 +1941,7 @@ ixEthAccPortTxFrameAppendFCSEnablePriv (IxEthAccPortId portId) IX_ETH_ACC_MAC_TX_CNTRL1, regval | IX_ETH_ACC_TX_CNTRL1_FCS_EN); - ixEthAccMacState[portId].txFCSAppend = TRUE; + ixEthAccMacState[portId].txFCSAppend = true; return IX_ETH_ACC_SUCCESS; } @@ -1973,7 +1973,7 @@ ixEthAccPortTxFrameAppendFCSDisablePriv (IxEthAccPortId portId) IX_ETH_ACC_MAC_TX_CNTRL1, regval & ~IX_ETH_ACC_TX_CNTRL1_FCS_EN); - ixEthAccMacState[portId].txFCSAppend = FALSE; + ixEthAccMacState[portId].txFCSAppend = false; return IX_ETH_ACC_SUCCESS; } @@ -2004,7 +2004,7 @@ ixEthAccPortRxFrameAppendFCSEnablePriv (IxEthAccPortId portId) IX_ETH_ACC_MAC_RX_CNTRL1, regval | IX_ETH_ACC_RX_CNTRL1_CRC_EN); - ixEthAccMacState[portId].rxFCSAppend = TRUE; + ixEthAccMacState[portId].rxFCSAppend = true; return IX_ETH_ACC_SUCCESS; } @@ -2035,7 +2035,7 @@ ixEthAccPortRxFrameAppendFCSDisablePriv (IxEthAccPortId portId) IX_ETH_ACC_MAC_RX_CNTRL1, regval & ~IX_ETH_ACC_RX_CNTRL1_CRC_EN); - ixEthAccMacState[portId].rxFCSAppend = FALSE; + ixEthAccMacState[portId].rxFCSAppend = false; return IX_ETH_ACC_SUCCESS; } @@ -2327,17 +2327,17 @@ ixEthAccMacInit(IxEthAccPortId portId) return IX_ETH_ACC_SUCCESS ; } - if(ixEthAccMacState[portId].macInitialised == FALSE) + if(ixEthAccMacState[portId].macInitialised == false) { - ixEthAccMacState[portId].fullDuplex = TRUE; - ixEthAccMacState[portId].rxFCSAppend = TRUE; - ixEthAccMacState[portId].txFCSAppend = TRUE; - ixEthAccMacState[portId].txPADAppend = TRUE; - ixEthAccMacState[portId].enabled = FALSE; - ixEthAccMacState[portId].promiscuous = TRUE; - ixEthAccMacState[portId].joinAll = FALSE; - ixEthAccMacState[portId].initDone = FALSE; - ixEthAccMacState[portId].macInitialised = TRUE; + ixEthAccMacState[portId].fullDuplex = true; + ixEthAccMacState[portId].rxFCSAppend = true; + ixEthAccMacState[portId].txFCSAppend = true; + ixEthAccMacState[portId].txPADAppend = true; + ixEthAccMacState[portId].enabled = false; + ixEthAccMacState[portId].promiscuous = true; + ixEthAccMacState[portId].joinAll = false; + ixEthAccMacState[portId].initDone = false; + ixEthAccMacState[portId].macInitialised = true; /* initialize MIB stats mutexes */ ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsLock); @@ -2417,7 +2417,7 @@ ixEthAccMacStateUpdate(IxEthAccPortId portId) { UINT32 regval; - if ( ixEthAccMacState[portId].enabled == FALSE ) + if ( ixEthAccMacState[portId].enabled == false ) { /* Just disable both the transmitter and reciver in the MAC. */ REG_READ(ixEthAccMacBase[portId], @@ -2480,7 +2480,7 @@ ixEthAccMacStateUpdate(IxEthAccPortId portId) ixEthAccPortPromiscuousModeClearPriv(portId); } - if ( ixEthAccMacState[portId].enabled == TRUE ) + if ( ixEthAccMacState[portId].enabled == true ) { /* Enable both the transmitter and reciver in the MAC. */ REG_READ(ixEthAccMacBase[portId], @@ -2509,10 +2509,10 @@ ixEthAccMacEqual(IxEthAccMacAddr *macAddr1, { if(macAddr1->macAddress[i] != macAddr2->macAddress[i]) { - return FALSE; + return false; } } - return TRUE; + return true; } PRIVATE void @@ -2554,7 +2554,7 @@ ixEthAccMulticastAddressSet(IxEthAccPortId portId) * are set in the result */ - if (ixEthAccMacState[portId].promiscuous == TRUE) + if (ixEthAccMacState[portId].promiscuous == true) { /* Promiscuous Mode is set, and filtering * allow all packets, and enable the mcast and @@ -2569,7 +2569,7 @@ ixEthAccMulticastAddressSet(IxEthAccPortId portId) } else { - if(ixEthAccMacState[portId].joinAll == TRUE) + if(ixEthAccMacState[portId].joinAll == true) { /* Join all is set. The mask and address are * the multicast settings. diff --git a/drivers/net/npe/IxEthDBAPI.c b/drivers/net/npe/IxEthDBAPI.c index b2bfb72..d46c47c 100644 --- a/drivers/net/npe/IxEthDBAPI.c +++ b/drivers/net/npe/IxEthDBAPI.c @@ -60,7 +60,7 @@ IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDB IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - return ixEthDBTriggerAddPortUpdate(macAddr, portID, TRUE); + return ixEthDBTriggerAddPortUpdate(macAddr, portID, true); } IX_ETH_DB_PUBLIC @@ -74,7 +74,7 @@ IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthD IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - return ixEthDBTriggerAddPortUpdate(macAddr, portID, FALSE); + return ixEthDBTriggerAddPortUpdate(macAddr, portID, false); } IX_ETH_DB_PUBLIC @@ -102,7 +102,7 @@ void ixEthDBDatabaseMaintenance() { HashIterator iterator; UINT32 portIndex; - BOOL agingRequired = FALSE; + BOOL agingRequired = false; /* ports who will have deleted records and therefore will need updating */ IxEthDBPortMap triggerPorts; @@ -120,7 +120,7 @@ void ixEthDBDatabaseMaintenance() { if (ixEthDBPortInfo[portIndex].agingEnabled && ixEthDBPortInfo[portIndex].enabled) { - agingRequired = TRUE; + agingRequired = true; } } @@ -152,9 +152,9 @@ void ixEthDBDatabaseMaintenance() } else { - ixEthDBPortInfo[portIndex].agingEnabled = FALSE; - ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = FALSE; - ixEthDBPortInfo[portIndex].updateMethod.userControlled = TRUE; + ixEthDBPortInfo[portIndex].agingEnabled = false; + ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false; + ixEthDBPortInfo[portIndex].updateMethod.userControlled = true; ixOsalLog(IX_OSAL_LOG_LVL_FATAL, IX_OSAL_LOG_DEV_STDOUT, @@ -173,7 +173,7 @@ void ixEthDBDatabaseMaintenance() { MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; UINT32 *age = NULL; - BOOL staticEntry = TRUE; + BOOL staticEntry = true; if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) { @@ -187,10 +187,10 @@ void ixEthDBDatabaseMaintenance() } else { - staticEntry = TRUE; + staticEntry = true; } - if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == FALSE)) + if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == false)) { /* manually increment the age if the port has no such capability */ if ((ixEthDBPortDefinitions[descriptor->portID].capabilities & IX_ETH_ENTRY_AGING) == 0) @@ -341,7 +341,7 @@ IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID) IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - ixEthDBPortInfo[portID].agingEnabled = FALSE; + ixEthDBPortInfo[portID].agingEnabled = false; return IX_ETH_DB_SUCCESS; } @@ -355,7 +355,7 @@ IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID) IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - ixEthDBPortInfo[portID].agingEnabled = TRUE; + ixEthDBPortInfo[portID].agingEnabled = true; return IX_ETH_DB_SUCCESS; } @@ -442,7 +442,7 @@ IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING); ixEthDBPortInfo[portID].updateMethod.updateEnabled = enableUpdate; - ixEthDBPortInfo[portID].updateMethod.userControlled = TRUE; + ixEthDBPortInfo[portID].updateMethod.userControlled = true; return IX_ETH_DB_SUCCESS; } diff --git a/drivers/net/npe/IxEthDBAPISupport.c b/drivers/net/npe/IxEthDBAPISupport.c index 36bc200..1facb89 100644 --- a/drivers/net/npe/IxEthDBAPISupport.c +++ b/drivers/net/npe/IxEthDBAPISupport.c @@ -128,18 +128,18 @@ void ixEthDBPortInit(IxEthDBPortId portID) SET_DEPENDENCY_MAP(portInfo->dependencyPortMap, portID); /* default values */ - portInfo->agingEnabled = FALSE; - portInfo->enabled = FALSE; - portInfo->macAddressUploaded = FALSE; + portInfo->agingEnabled = false; + portInfo->enabled = false; + portInfo->macAddressUploaded = false; portInfo->maxRxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE; portInfo->maxTxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE; /* default update control values */ portInfo->updateMethod.searchTree = NULL; - portInfo->updateMethod.searchTreePendingWrite = FALSE; - portInfo->updateMethod.treeInitialized = FALSE; - portInfo->updateMethod.updateEnabled = FALSE; - portInfo->updateMethod.userControlled = FALSE; + portInfo->updateMethod.searchTreePendingWrite = false; + portInfo->updateMethod.treeInitialized = false; + portInfo->updateMethod.updateEnabled = false; + portInfo->updateMethod.userControlled = false; /* default WiFi parameters */ memset(portInfo->bbsid, 0, sizeof (portInfo->bbsid)); @@ -153,9 +153,9 @@ void ixEthDBPortInit(IxEthDBPortId portID) } /* initialize state save */ - ixEthDBPortState[portID].saved = FALSE; + ixEthDBPortState[portID].saved = false; - portInfo->initialized = TRUE; + portInfo->initialized = true; } /** @@ -190,7 +190,7 @@ IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID) SET_DEPENDENCY_MAP(triggerPorts, portID); /* mark as enabled */ - portInfo->enabled = TRUE; + portInfo->enabled = true; /* Operation stops here when Ethernet Learning is not enabled */ if(IX_FEATURE_CTRL_SWCONFIG_DISABLED == @@ -214,7 +214,7 @@ IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID) if (!portInfo->updateMethod.userControlled && ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0)) { - portInfo->updateMethod.updateEnabled = TRUE; + portInfo->updateMethod.updateEnabled = true; } /* if this is first time initialization then we already have @@ -227,7 +227,7 @@ IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID) ixEthDBUpdatePortLearningTrees(triggerPorts); /* mark tree as being initialized */ - portInfo->updateMethod.treeInitialized = TRUE; + portInfo->updateMethod.treeInitialized = true; } } @@ -262,7 +262,7 @@ IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID) ixEthDBFilteringPortMaximumTxFrameSizeSet(portID, ixEthDBPortState[portID].maxTxFrameSize); /* discard previous save */ - ixEthDBPortState[portID].saved = FALSE; + ixEthDBPortState[portID].saved = false; } IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Enabling succeeded for port %d\n", portID); @@ -321,7 +321,7 @@ IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) memcpy(ixEthDBPortState[portID].transmitTaggingInfo, portInfo->transmitTaggingInfo, sizeof (IxEthDBVlanSet)); memcpy(ixEthDBPortState[portID].priorityTable, portInfo->priorityTable, sizeof (IxEthDBPriorityTable)); - ixEthDBPortState[portID].saved = TRUE; + ixEthDBPortState[portID].saved = true; /* now turn off all EthDB filtering features on the port */ @@ -330,7 +330,7 @@ IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) { ixEthDBPortVlanMembershipRangeAdd((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID); - ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, FALSE); + ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, false); ixEthDBAcceptableFrameTypeSet((IxEthDBPortId) portID, IX_ETH_DB_ACCEPT_ALL_FRAMES); ixEthDBIngressVlanTaggingEnabledSet((IxEthDBPortId) portID, IX_ETH_DB_PASS_THROUGH); @@ -342,7 +342,7 @@ IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) /* STP */ if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) { - ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, FALSE); + ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, false); } /* Firewall */ @@ -350,7 +350,7 @@ IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) { ixEthDBFirewallModeSet((IxEthDBPortId) portID, IX_ETH_DB_FIREWALL_BLACK_LIST); ixEthDBFirewallTableDownload((IxEthDBPortId) portID); - ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, FALSE); + ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, false); } /* Frame size filter */ @@ -413,18 +413,18 @@ IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) } /* mark as disabled */ - portInfo->enabled = FALSE; + portInfo->enabled = false; /* disable updates unless the user has specifically altered the default behavior */ if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) { if (!portInfo->updateMethod.userControlled) { - portInfo->updateMethod.updateEnabled = FALSE; + portInfo->updateMethod.updateEnabled = false; } /* make sure we re-initialize the NPE learning tree when the port is re-enabled */ - portInfo->updateMethod.treeInitialized = FALSE; + portInfo->updateMethod.treeInitialized = false; } ixEthDBUpdateUnlock(); @@ -668,7 +668,7 @@ IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAdd if (result == IX_SUCCESS) { - ixEthDBPortInfo[portID].macAddressUploaded = TRUE; + ixEthDBPortInfo[portID].macAddressUploaded = true; } return result; diff --git a/drivers/net/npe/IxEthDBCore.c b/drivers/net/npe/IxEthDBCore.c index 25b7cbb..8b3c1d9 100644 --- a/drivers/net/npe/IxEthDBCore.c +++ b/drivers/net/npe/IxEthDBCore.c @@ -51,7 +51,7 @@ IX_ETH_DB_PUBLIC BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyType[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1]; /* private initialization flag */ -IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = FALSE; +IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = false; /** * @brief initializes EthDB @@ -124,7 +124,7 @@ IxEthDBStatus ixEthDBInit(void) ixEthDBFeatureCapabilityScan(); } - ethDBInitializationComplete = TRUE; + ethDBInitializationComplete = true; return result; } @@ -179,7 +179,7 @@ IxEthDBStatus ixEthDBUnload(void) ixOsalMutexDestroy(&ixEthDBPortInfo[portIndex].npeAckLock); } - ixEthDBPortInfo[portIndex].initialized = FALSE; + ixEthDBPortInfo[portIndex].initialized = false; } /* shutdown event processor */ @@ -188,7 +188,7 @@ IxEthDBStatus ixEthDBUnload(void) /* deallocate NPE update zones */ ixEthDBNPEUpdateAreasUnload(); - ethDBInitializationComplete = FALSE; + ethDBInitializationComplete = false; return IX_ETH_DB_SUCCESS; } diff --git a/drivers/net/npe/IxEthDBEvents.c b/drivers/net/npe/IxEthDBEvents.c index 4d44e03..529063d 100644 --- a/drivers/net/npe/IxEthDBEvents.c +++ b/drivers/net/npe/IxEthDBEvents.c @@ -61,8 +61,8 @@ IX_ETH_DB_PRIVATE PortEventQueue eventQueue; IX_ETH_DB_PRIVATE IxOsalMutex eventQueueLock; IX_ETH_DB_PRIVATE IxOsalMutex portUpdateLock; -IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown = FALSE; -IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = FALSE; +IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown = false; +IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = false; /* imported data */ extern HashTable dbHashtable; @@ -143,7 +143,7 @@ IxEthDBStatus ixEthDBStartLearningFunction(void) return IX_ETH_DB_FAIL; } - ixEthDBLearningShutdown = FALSE; + ixEthDBLearningShutdown = false; /* create processor loop thread */ if (ixOsalThreadCreate(&eventProcessorThread, &threadAttr, ixEthDBEventProcessorLoop, NULL) != IX_SUCCESS) @@ -173,7 +173,7 @@ IxEthDBStatus ixEthDBStartLearningFunction(void) IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void) { - ixEthDBLearningShutdown = TRUE; + ixEthDBLearningShutdown = true; /* wake up event processing loop to actually process the shutdown event */ ixOsalSemaphorePost(&eventQueueSemaphore); @@ -253,13 +253,13 @@ void ixEthDBEventProcessorLoop(void *unused1) IxEthDBPortMap triggerPorts; IxEthDBPortId portIndex; - ixEthDBEventProcessorRunning = TRUE; + ixEthDBEventProcessorRunning = true; IX_ETH_DB_EVENTS_TRACE("DB: (Events) Event processor loop was started\n"); while (!ixEthDBLearningShutdown) { - BOOL keepProcessing = TRUE; + BOOL keepProcessing = true; UINT32 processedEvents = 0; IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Waiting for new learning event...\n"); @@ -302,7 +302,7 @@ void ixEthDBEventProcessorLoop(void *unused1) if (processedEvents > EVENT_PROCESSING_LIMIT /* maximum burst reached? */ || ixOsalSemaphoreTryWait(&eventQueueSemaphore) != IX_SUCCESS) /* or empty queue? */ { - keepProcessing = FALSE; + keepProcessing = false; } } @@ -313,10 +313,10 @@ void ixEthDBEventProcessorLoop(void *unused1) /* turn off automatic updates */ for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) { - ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = FALSE; + ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false; } - ixEthDBEventProcessorRunning = FALSE; + ixEthDBEventProcessorRunning = false; } /** @@ -381,7 +381,7 @@ void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts) * * @param macAddr MAC address of the new record * @param portID port ID of the new record - * @param staticEntry TRUE if record is static, FALSE if dynamic + * @param staticEntry true if record is static, false if dynamic * * @return IX_ETH_DB_SUCCESS if the event creation was * successfull or IX_ETH_DB_BUSY if the event queue is full @@ -430,7 +430,7 @@ IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPor { if (ixEthDBPeek(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS) != IX_ETH_DB_NO_SUCH_ADDR) { - return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, FALSE); + return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, false); } else { diff --git a/drivers/net/npe/IxEthDBFeatures.c b/drivers/net/npe/IxEthDBFeatures.c index 7a58d26..c5b680a 100644 --- a/drivers/net/npe/IxEthDBFeatures.c +++ b/drivers/net/npe/IxEthDBFeatures.c @@ -169,7 +169,7 @@ void ixEthDBFeatureCapabilityScan(void) /* enable port, VLAN and Firewall feature bits to initialize QoS/VLAN/Firewall configuration */ portInfo->featureStatus |= IX_ETH_DB_VLAN_QOS; portInfo->featureStatus |= IX_ETH_DB_FIREWALL; - portInfo->enabled = TRUE; + portInfo->enabled = true; #define CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ #ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ @@ -195,7 +195,7 @@ void ixEthDBFeatureCapabilityScan(void) ixEthDBPortVlanMembershipRangeRemove(portIndex, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID); /* clear TTI table - no VLAN tagged frames will be transmitted */ - ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, FALSE); + ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, false); /* set membership on 0, otherwise no Tx or Rx is working */ ixEthDBPortVlanMembershipAdd(portIndex, 0); @@ -221,12 +221,12 @@ void ixEthDBFeatureCapabilityScan(void) #endif /* by default we turn off invalid source MAC address filtering */ - ixEthDBFirewallInvalidAddressFilterEnable(portIndex, FALSE); + ixEthDBFirewallInvalidAddressFilterEnable(portIndex, false); /* disable port, VLAN, Firewall feature bits */ portInfo->featureStatus &= ~IX_ETH_DB_VLAN_QOS; portInfo->featureStatus &= ~IX_ETH_DB_FIREWALL; - portInfo->enabled = FALSE; + portInfo->enabled = false; /* enable filtering by default if present */ if ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0) @@ -271,7 +271,7 @@ IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature * * * @param portID ID of the port * @param feature feature to enable or disable - * @param enabled TRUE to enable the selected feature or FALSE to disable it + * @param enabled true to enable the selected feature or false to disable it * * Note that this function is documented in the main component * header file, IxEthDB.h. @@ -333,7 +333,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, } /* force port enabled */ - portInfo->enabled = TRUE; + portInfo->enabled = true; if (enable) { @@ -399,7 +399,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, /* enable TPID port extraction */ if (status == IX_ETH_DB_SUCCESS) { - status = ixEthDBVlanPortExtractionEnable(portID, TRUE); + status = ixEthDBVlanPortExtractionEnable(portID, true); } } else if (feature == IX_ETH_DB_FIREWALL) @@ -414,7 +414,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, if (status == IX_ETH_DB_SUCCESS) { - status = ixEthDBFirewallInvalidAddressFilterEnable(portID, FALSE); + status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false); } } } @@ -445,7 +445,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, if (status == IX_ETH_DB_SUCCESS) { - status = ixEthDBFirewallInvalidAddressFilterEnable(portID, FALSE); + status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false); } if (status == IX_ETH_DB_SUCCESS) @@ -515,7 +515,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, /* disable TPID port extraction */ if (status == IX_ETH_DB_SUCCESS) { - status = ixEthDBVlanPortExtractionEnable(portID, FALSE); + status = ixEthDBVlanPortExtractionEnable(portID, false); } } #endif @@ -538,9 +538,9 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, * * @param portID port ID * @param present location to store a boolean value indicating - * if the feature is present (TRUE) or not (FALSE) + * if the feature is present (true) or not (false) * @param enabled location to store a booleam value indicating - * if the feature is present (TRUE) or not (FALSE) + * if the feature is present (true) or not (false) * * Note that this function is documented in the main component * header file, IxEthDB.h. diff --git a/drivers/net/npe/IxEthDBFirewall.c b/drivers/net/npe/IxEthDBFirewall.c index eb46174..6fb5ab6 100644 --- a/drivers/net/npe/IxEthDBFirewall.c +++ b/drivers/net/npe/IxEthDBFirewall.c @@ -72,7 +72,7 @@ IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 UINT32 mode = 0; PortInfo *portInfo = &ixEthDBPortInfo[portID]; - mode = (portInfo->srcAddressFilterEnabled != FALSE) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST); + mode = (portInfo->srcAddressFilterEnabled != false) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST); FILL_SETFIREWALLMODE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), @@ -123,8 +123,8 @@ IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode m * @brief enables or disables the invalid source MAC address filter * * @param portID ID of the port - * @param enable TRUE to enable invalid source MAC address filtering - * or FALSE to disable it + * @param enable true to enable invalid source MAC address filtering + * or false to disable it * * The invalid source MAC address filter will discard, when enabled, * frames whose source MAC address is a multicast or the broadcast MAC diff --git a/drivers/net/npe/IxEthDBLearning.c b/drivers/net/npe/IxEthDBLearning.c index 2287dbe..8406741 100644 --- a/drivers/net/npe/IxEthDBLearning.c +++ b/drivers/net/npe/IxEthDBLearning.c @@ -105,8 +105,8 @@ UINT32 ixEthDBKeyXORHash(void *key) * collisions, i.e. descriptors with different mac addresses and the same * hash value, where this function is used to differentiate entries. * - * @retval TRUE if the entry matches the reference key (equal addresses) - * @retval FALSE if the entry does not match the reference key + * @retval true if the entry matches the reference key (equal addresses) + * @retval false if the entry does not match the reference key * * @internal */ diff --git a/drivers/net/npe/IxEthDBNPEAdaptor.c b/drivers/net/npe/IxEthDBNPEAdaptor.c index 112a46c..d47ffec 100644 --- a/drivers/net/npe/IxEthDBNPEAdaptor.c +++ b/drivers/net/npe/IxEthDBNPEAdaptor.c @@ -203,7 +203,7 @@ void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSi /* debug */ IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) checking node at offset %d...\n", eltEntryOffset / ELT_ENTRY_SIZE); - if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != TRUE) + if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != true) { IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is empty\n"); } diff --git a/drivers/net/npe/IxEthDBPortUpdate.c b/drivers/net/npe/IxEthDBPortUpdate.c index cdf114b..813e4ee 100644 --- a/drivers/net/npe/IxEthDBPortUpdate.c +++ b/drivers/net/npe/IxEthDBPortUpdate.c @@ -60,7 +60,7 @@ extern HashTable dbHashtable; * * @param typeArray array indexed on record types, each * element indicating whether the record type requires an - * automatic update (TRUE) or not (FALSE) + * automatic update (true) or not (false) * * Automatic updates are done for registered record types * upon adding, updating (that is, updating the record portID) @@ -70,7 +70,7 @@ extern HashTable dbHashtable; * * It is assumed that the typeArray parameter is allocated large * enough to hold all the user defined types. Also, the type - * array should be initialized to FALSE as this function only + * array should be initialized to false as this function only * caters for types which do require automatic updates. * * Note that this function should be called by the component @@ -84,8 +84,8 @@ extern HashTable dbHashtable; IX_ETH_DB_PUBLIC UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray) { - typeArray[IX_ETH_DB_FILTERING_RECORD] = TRUE; - typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = TRUE; + typeArray[IX_ETH_DB_FILTERING_RECORD] = true; + typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = true; return 2; } @@ -174,7 +174,7 @@ void ixEthDBCreateTrees(IxEthDBPortMap updatePorts) { UINT32 portIndex; BOOL result; - BOOL portsLeft = TRUE; + BOOL portsLeft = true; while (portsLeft) { @@ -305,11 +305,11 @@ void ixEthDBCreateTrees(IxEthDBPortMap updatePorts) } /* mark tree as valid */ - port->updateMethod.searchTreePendingWrite = TRUE; + port->updateMethod.searchTreePendingWrite = true; } else { - portsLeft = FALSE; + portsLeft = false; IX_ETH_DB_UPDATE_TRACE("DB: (Update) No trees to create this round\n"); } @@ -374,7 +374,7 @@ IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType ty /* forget last used search tree */ port->updateMethod.searchTree = NULL; - port->updateMethod.searchTreePendingWrite = FALSE; + port->updateMethod.searchTreePendingWrite = false; /* dependending on the update type we do different things */ if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD) @@ -393,9 +393,9 @@ IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType ty } else { - ixEthDBPortInfo[portID].agingEnabled = FALSE; - ixEthDBPortInfo[portID].updateMethod.updateEnabled = FALSE; - ixEthDBPortInfo[portID].updateMethod.userControlled = TRUE; + ixEthDBPortInfo[portID].agingEnabled = false; + ixEthDBPortInfo[portID].updateMethod.updateEnabled = false; + ixEthDBPortInfo[portID].updateMethod.userControlled = true; ERROR_LOG("EthDB: (PortUpdate) disabling aging and updates on port %d (assumed dead)\n", portID); diff --git a/drivers/net/npe/IxEthDBReports.c b/drivers/net/npe/IxEthDBReports.c index 9c7ae1c..912e608 100644 --- a/drivers/net/npe/IxEthDBReports.c +++ b/drivers/net/npe/IxEthDBReports.c @@ -62,7 +62,7 @@ IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map) { UINT32 portIndex; - BOOL mapSelf = TRUE, mapNone = TRUE, firstPort = TRUE; + BOOL mapSelf = true, mapNone = true, firstPort = true; /* dependency port maps */ printf("Dependency port map: "); @@ -72,22 +72,22 @@ IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap { if (IS_PORT_INCLUDED(portIndex, map)) { - mapNone = FALSE; + mapNone = false; if (portIndex != portID) { - mapSelf = FALSE; + mapSelf = false; } printf("%s%d", firstPort ? "{" : ", ", portIndex); - firstPort = FALSE; + firstPort = false; } } if (mapNone) { - mapSelf = FALSE; + mapSelf = false; } printf("%s (%s)\n", firstPort ? "" : "}", mapSelf ? "self" : mapNone ? "none" : "group"); diff --git a/drivers/net/npe/IxEthDBSearch.c b/drivers/net/npe/IxEthDBSearch.c index 4a10878..75fdebe 100644 --- a/drivers/net/npe/IxEthDBSearch.c +++ b/drivers/net/npe/IxEthDBSearch.c @@ -50,7 +50,7 @@ extern HashTable dbHashtable; * @param untypedReference record to match against * @param untypedEntry record to match * - * @return TRUE if the match is successful or FALSE otherwise + * @return true if the match is successful or false otherwise * * @internal */ @@ -61,7 +61,7 @@ BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry) MacDescriptor *reference = (MacDescriptor *) untypedReference; /* check accepted record types */ - if ((entry->type & reference->type) == 0) return FALSE; + if ((entry->type & reference->type) == 0) return false; return (ixEthDBAddressCompare((UINT8 *) entry->macAddress, (UINT8 *) reference->macAddress) == 0); } @@ -73,7 +73,7 @@ BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry) * @param untypedReference record to match against * @param untypedEntry record to match * - * @return TRUE if the match is successful or FALSE otherwise + * @return true if the match is successful or false otherwise * * @internal */ @@ -84,7 +84,7 @@ BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry) MacDescriptor *reference = (MacDescriptor *) untypedReference; /* check accepted record types */ - if ((entry->type & reference->type) == 0) return FALSE; + if ((entry->type & reference->type) == 0) return false; return (IX_ETH_DB_GET_VLAN_ID(entry->recordData.filteringVlanData.ieee802_1qTag) == IX_ETH_DB_GET_VLAN_ID(reference->recordData.filteringVlanData.ieee802_1qTag)) && @@ -98,7 +98,7 @@ BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry) * @param untypedReference record to match against * @param untypedEntry record to match * - * @return TRUE if the match is successful or FALSE otherwise + * @return true if the match is successful or false otherwise * * @internal */ @@ -109,7 +109,7 @@ BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry) MacDescriptor *reference = (MacDescriptor *) untypedReference; /* check accepted record types */ - if ((entry->type & reference->type) == 0) return FALSE; + if ((entry->type & reference->type) == 0) return false; return (entry->portID == reference->portID) && (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0); @@ -125,7 +125,7 @@ BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry) * array on invalid types. Calling it will display an * error message, indicating an error in the component logic. * - * @return FALSE + * @return false * * @internal */ @@ -137,7 +137,7 @@ BOOL ixEthDBNullMatch(void *reference, void *entry) ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, "DB: (Search) The NullMatch function was called, wrong key type?\n", 0, 0, 0, 0, 0, 0); - return FALSE; + return false; } /** diff --git a/drivers/net/npe/IxEthDBSpanningTree.c b/drivers/net/npe/IxEthDBSpanningTree.c index 6d9fd6e..029f7ac 100644 --- a/drivers/net/npe/IxEthDBSpanningTree.c +++ b/drivers/net/npe/IxEthDBSpanningTree.c @@ -49,7 +49,7 @@ * @brief sets the STP blocking state of a port * * @param portID ID of the port - * @param blocked TRUE to block the port or FALSE to unblock it + * @param blocked true to block the port or false to unblock it * * Note that this function is documented in the main component * header file, IxEthDB.h. diff --git a/drivers/net/npe/IxEthDBUtil.c b/drivers/net/npe/IxEthDBUtil.c index e708bf1..24acc24 100644 --- a/drivers/net/npe/IxEthDBUtil.c +++ b/drivers/net/npe/IxEthDBUtil.c @@ -94,13 +94,13 @@ BOOL ixEthDBCheckSingleBitValue(UINT32 value) while (value != 0) { - if (value == 1) return TRUE; - else if ((value & 1) == 1) return FALSE; + if (value == 1) return true; + else if ((value & 1) == 1) return false; value >>= 1; } - return FALSE; + return false; #endif } diff --git a/drivers/net/npe/IxEthDBVlan.c b/drivers/net/npe/IxEthDBVlan.c index e2efb9b..522a30b 100644 --- a/drivers/net/npe/IxEthDBVlan.c +++ b/drivers/net/npe/IxEthDBVlan.c @@ -642,7 +642,7 @@ IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet * * @param portID ID of the port * @param vlanID VLAN ID to enable or disable Egress tagging on - * @param enabled TRUE to enable and FALSE to disable tagging + * @param enabled true to enable and false to disable tagging * * Note that this function is documented in the main component * header file, IxEthDB.h. @@ -670,7 +670,7 @@ IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEt * @param portID ID of the port * @param vlanID VLAN ID to retrieve the tagging status for * @param enabled location to store the tagging status - * (TRUE - tagging enabled, FALSE - tagging disabled) + * (true - tagging enabled, false - tagging disabled) * * Note that this function is documented in the main component * header file, IxEthDB.h. @@ -702,7 +702,7 @@ IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEt * @param portID ID of the port * @param vlanIDMin start of VLAN range * @param vlanIDMax end of VLAN range - * @param enabled TRUE to enable or FALSE to disable VLAN tagging + * @param enabled true to enable or false to disable VLAN tagging * * Note that this function is documented in the main component * header file, IxEthDB.h. @@ -1151,7 +1151,7 @@ IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriori * from the VLAN TPID field * * @param portID ID of the port - * @param enable TRUE to enable or FALSE to disable + * @param enable true to enable or false to disable * * Note that this function is documented in the main component * header file, IxEthDB.h. diff --git a/drivers/net/npe/IxEthMii.c b/drivers/net/npe/IxEthMii.c index 4d92f17..f8b439d 100644 --- a/drivers/net/npe/IxEthMii.c +++ b/drivers/net/npe/IxEthMii.c @@ -65,7 +65,7 @@ PRIVATE UINT32 ixEthMiiPhyId[IXP425_ETH_ACC_MII_MAX_ADDR]; * Scan for PHYs on the MII bus. This function returns * an array of booleans, one for each PHY address. * If a PHY is found at a particular address, the - * corresponding entry in the array is set to TRUE. + * corresponding entry in the array is set to true. * */ @@ -89,7 +89,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount) i<IXP425_ETH_ACC_MII_MAX_ADDR; i++) { - phyPresent[i] = FALSE; + phyPresent[i] = false; } /* iterate through the PHY addresses */ @@ -119,7 +119,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount) ) { /* supported phy */ - phyPresent[i] = TRUE; + phyPresent[i] = true; } /* end of if(ixEthMiiPhyId) */ else { @@ -131,7 +131,7 @@ ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount) "ixEthMiiPhyScan : unexpected Mii PHY ID %8.8x\n", ixEthMiiPhyId[i], 2, 3, 4, 5, 6); ixEthMiiPhyId[i] = IX_ETH_MII_UNKNOWN_PHY_ID; - phyPresent[i] = TRUE; + phyPresent[i] = true; } } } @@ -347,10 +347,10 @@ ixEthMiiLinkStatus(UINT32 phyAddr, return IX_FAIL; } - *linkUp = FALSE; - *speed100 = FALSE; - *fullDuplex = FALSE; - *autoneg = FALSE; + *linkUp = false; + *speed100 = false; + *fullDuplex = false; + *autoneg = false; if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) && (ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID)) @@ -406,20 +406,20 @@ ixEthMiiLinkStatus(UINT32 phyAddr, if ((regval & IX_ETH_MII_SR_TX_FULL_DPX) != 0) { /* 100 Base X full dplx */ - *speed100 = TRUE; - *fullDuplex = TRUE; + *speed100 = true; + *fullDuplex = true; return IX_SUCCESS; } if ((regval & IX_ETH_MII_SR_TX_HALF_DPX) != 0) { /* 100 Base X half dplx */ - *speed100 = TRUE; + *speed100 = true; return IX_SUCCESS; } if ((regval & IX_ETH_MII_SR_10T_FULL_DPX) != 0) { /* 10 mb full dplx */ - *fullDuplex = TRUE; + *fullDuplex = true; return IX_SUCCESS; } if ((regval & IX_ETH_MII_SR_10T_HALF_DPX) != 0) diff --git a/drivers/net/npe/IxFeatureCtrl.c b/drivers/net/npe/IxFeatureCtrl.c index 2e196a1..b6728e4 100644 --- a/drivers/net/npe/IxFeatureCtrl.c +++ b/drivers/net/npe/IxFeatureCtrl.c @@ -72,7 +72,7 @@ IX_OSAL_WRITE_LONG(ixFeatureCtrlRegister, (value)); \ /* Boolean to mark the fact that the EXP_CONFIG address space was mapped */ -PRIVATE BOOL ixFeatureCtrlExpCfgRegionMapped = FALSE; +PRIVATE BOOL ixFeatureCtrlExpCfgRegionMapped = false; /* Pointer holding the virtual address of the Feature Control Register */ PRIVATE VUINT32 *ixFeatureCtrlRegister = NULL; @@ -81,7 +81,7 @@ PRIVATE VUINT32 *ixFeatureCtrlRegister = NULL; PRIVATE BOOL swConfiguration[IX_FEATURECTRL_SWCONFIG_MAX]; /* Flag to control swConfiguration[] is initialized once */ -PRIVATE BOOL swConfigurationFlag = FALSE ; +PRIVATE BOOL swConfigurationFlag = false ; /* Array containing component mask values */ #ifdef __ixp42X @@ -158,7 +158,7 @@ void ixFeatureCtrlExpMap(void) /* If the EXP Configuration space has already been mapped then * return */ - if (ixFeatureCtrlExpCfgRegionMapped == TRUE) + if (ixFeatureCtrlExpCfgRegionMapped == true) { return; } @@ -176,7 +176,7 @@ void ixFeatureCtrlExpMap(void) (VUINT32 *) (expCfgBaseAddress + IX_FEATURE_CTRL_REG_OFFSET); /* Mark the fact that the EXP_CONFIG space has already been mapped */ - ixFeatureCtrlExpCfgRegionMapped = TRUE; + ixFeatureCtrlExpCfgRegionMapped = true; } /** @@ -186,15 +186,15 @@ void ixFeatureCtrlExpMap(void) PRIVATE void ixFeatureCtrlSwConfigurationInit(void) { UINT32 i; - if (FALSE == swConfigurationFlag) + if (false == swConfigurationFlag) { for (i=0; i<IX_FEATURECTRL_SWCONFIG_MAX ; i++) { /* By default, all software configuration are enabled */ - swConfiguration[i]= TRUE ; + swConfiguration[i]= true ; } /*Make sure this function only initializes swConfiguration[] once*/ - swConfigurationFlag = TRUE ; + swConfigurationFlag = true ; } } @@ -326,7 +326,7 @@ ixFeatureCtrlProductIdRead () extern IxFeatureCtrlProductId AsmixFeatureCtrlProductIdRead(); #ifndef IN_KERNEL - mode = SetKMode(TRUE); + mode = SetKMode(true); #endif pdId = AsmixFeatureCtrlProductIdRead(); #ifndef IN_KERNEL @@ -372,7 +372,7 @@ ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType) ixFeatureCtrlSwConfigurationInit(); /* Check and return software configuration */ - return ((swConfiguration[(UINT32)swConfigType] == TRUE) ? IX_FEATURE_CTRL_SWCONFIG_ENABLED: IX_FEATURE_CTRL_SWCONFIG_DISABLED); + return ((swConfiguration[(UINT32)swConfigType] == true) ? IX_FEATURE_CTRL_SWCONFIG_ENABLED: IX_FEATURE_CTRL_SWCONFIG_DISABLED); } /** diff --git a/drivers/net/npe/IxNpeDl.c b/drivers/net/npe/IxNpeDl.c index 3738337..bfeac87 100644 --- a/drivers/net/npe/IxNpeDl.c +++ b/drivers/net/npe/IxNpeDl.c @@ -89,9 +89,9 @@ typedef struct */ static IxNpeDlNpeState ixNpeDlNpeState[IX_NPEDL_NPEID_MAX] = { - {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}, - {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}, - {FALSE, {IX_NPEDL_NPEID_MAX, 0, 0, 0}} + {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}, + {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}, + {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}} }; static IxNpeDlStats ixNpeDlStats; @@ -99,7 +99,7 @@ static IxNpeDlStats ixNpeDlStats; /* * Software guard to prevent NPE from being started multiple times. */ -static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={FALSE, FALSE, FALSE} ; +static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={false, false, false} ; /* @@ -195,7 +195,7 @@ ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr, if (IX_SUCCESS == status) { ixNpeDlNpeState[npeId].imageId = *imageIdPtr; - ixNpeDlNpeState[npeId].validImage = TRUE; + ixNpeDlNpeState[npeId].validImage = true; ixNpeDlStats.successfulDownloads++; status = ixNpeDlNpeExecutionStart (npeId); @@ -204,7 +204,7 @@ ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr, (status == IX_NPEDL_CRITICAL_MICROCODE_ERR)) { ixNpeDlNpeState[npeId].imageId = *imageIdPtr; - ixNpeDlNpeState[npeId].validImage = FALSE; + ixNpeDlNpeState[npeId].validImage = false; ixNpeDlStats.criticalFailDownloads++; } } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */ @@ -507,7 +507,7 @@ ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId) if (IX_SUCCESS == status) { /* Indicate NPE has been stopped */ - ixNpeDlNpeStarted[npeId] = FALSE ; + ixNpeDlNpeStarted[npeId] = false ; } return status; @@ -573,7 +573,7 @@ ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId) } /* end of if-else(IX_NPEDL_NPEID_NPEC) */ } /* end of if not IXP42x-A0 Silicon */ - if (TRUE == ixNpeDlNpeStarted[npeId]) + if (true == ixNpeDlNpeStarted[npeId]) { /* NPE has been started. */ return IX_SUCCESS ; @@ -588,7 +588,7 @@ ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId) if (IX_SUCCESS == status) { /* Indicate NPE has started */ - ixNpeDlNpeStarted[npeId] = TRUE ; + ixNpeDlNpeStarted[npeId] = true ; } IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, @@ -674,7 +674,7 @@ ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId) if (IX_SUCCESS == status) { /* Indicate NPE has been stopped */ - ixNpeDlNpeStarted[npeId] = FALSE ; + ixNpeDlNpeStarted[npeId] = false ; } return status; @@ -840,10 +840,10 @@ ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, * currently loaded images. If a critical error occured * during download, record that the NPE has an invalid image */ - status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, TRUE); + status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, true); if (IX_SUCCESS == status) { - ixNpeDlNpeState[npeId].validImage = TRUE; + ixNpeDlNpeState[npeId].validImage = true; ixNpeDlStats.successfulDownloads++; status = ixNpeDlNpeExecutionStart (npeId); @@ -851,7 +851,7 @@ ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) || (status == IX_NPEDL_CRITICAL_MICROCODE_ERR)) { - ixNpeDlNpeState[npeId].validImage = FALSE; + ixNpeDlNpeState[npeId].validImage = false; ixNpeDlStats.criticalFailDownloads++; } diff --git a/drivers/net/npe/IxNpeDlImageMgr.c b/drivers/net/npe/IxNpeDlImageMgr.c index 9bcdc9c..0484483 100644 --- a/drivers/net/npe/IxNpeDlImageMgr.c +++ b/drivers/net/npe/IxNpeDlImageMgr.c @@ -414,11 +414,11 @@ ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary) { IxNpeDlImageMgrImageLibraryHeader *header = (IxNpeDlImageMgrImageLibraryHeader *) microCodeImageLibrary; - BOOL result = TRUE; + BOOL result = true; if (!header || header->signature != IX_NPEDL_IMAGEMGR_SIGNATURE) { - result = FALSE; + result = false; ixNpeDlImageMgrStats.invalidSignature++; } @@ -469,11 +469,11 @@ ixNpeDlImageMgrImageIdCompare ( (imageIdA->major == imageIdB->major) && (imageIdA->minor == imageIdB->minor)) { - return TRUE; + return true; } else { - return FALSE; + return false; } } @@ -491,11 +491,11 @@ ixNpeDlImageMgrNpeFunctionIdCompare ( if ((imageIdA->npeId == imageIdB->npeId) && (imageIdA->functionalityId == imageIdB->functionalityId)) { - return TRUE; + return true; } else { - return FALSE; + return false; } } @@ -550,7 +550,7 @@ ixNpeDlImageMgrImageFind_legacy ( UINT32 imageCount = 0; IX_STATUS status = IX_FAIL; IxNpeDlImageMgrImageLibraryHeader *header; - BOOL imageFound = FALSE; + BOOL imageFound = false; IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, "Entering ixNpeDlImageMgrImageFind\n"); @@ -584,7 +584,7 @@ ixNpeDlImageMgrImageFind_legacy ( /* get the image size */ *imageSize = header->entry[imageCount].image.size; status = IX_SUCCESS; - imageFound = TRUE; + imageFound = true; } imageCount++; } diff --git a/drivers/net/npe/IxNpeDlNpeMgr.c b/drivers/net/npe/IxNpeDlNpeMgr.c index a9ea8bc..aaffeeb 100644 --- a/drivers/net/npe/IxNpeDlNpeMgr.c +++ b/drivers/net/npe/IxNpeDlNpeMgr.c @@ -229,7 +229,7 @@ static IxNpeDlEcsRegResetValue ixNpeDlEcsRegResetValues[] = static IxNpeDlNpeMgrStats ixNpeDlNpeMgrStats; /* Set when NPE register memory has been mapped */ -static BOOL ixNpeDlMemInitialised = FALSE; +static BOOL ixNpeDlMemInitialised = false; /* @@ -290,7 +290,7 @@ ixNpeDlNpeMgrInit (void) IX_OSAL_ASSERT(virtAddr); ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = virtAddr; - ixNpeDlMemInitialised = TRUE; + ixNpeDlMemInitialised = true; } } @@ -314,7 +314,7 @@ ixNpeDlNpeMgrUninit (void) ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = 0; ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = 0; - ixNpeDlMemInitialised = FALSE; + ixNpeDlMemInitialised = false; return IX_SUCCESS; } @@ -662,7 +662,7 @@ ixNpeDlNpeMgrNpeReset ( { /* for each physical register in the NPE reg file, write 0 : */ status = ixNpeDlNpeMgrPhysicalRegWrite (npeBaseAddress, regAddr, - 0, TRUE); + 0, true); if (status != IX_SUCCESS) { return status; /* abort reset */ @@ -684,7 +684,7 @@ ixNpeDlNpeMgrNpeReset ( { regVal = ixNpeDlCtxtRegResetValues[ctxtReg]; status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, - ctxtReg, regVal, TRUE); + ctxtReg, regVal, true); if (status != IX_SUCCESS) { return status; /* abort reset */ diff --git a/drivers/net/npe/IxNpeMh.c b/drivers/net/npe/IxNpeMh.c index 8703def..2870ff7 100644 --- a/drivers/net/npe/IxNpeMh.c +++ b/drivers/net/npe/IxNpeMh.c @@ -79,7 +79,7 @@ * static variables. */ -PRIVATE BOOL ixNpeMhInitialized = FALSE; +PRIVATE BOOL ixNpeMhInitialized = false; /* * Extern function prototypes. @@ -128,7 +128,7 @@ PUBLIC IX_STATUS ixNpeMhInitialize ( */ ixNpeMhConfigInitialize (npeInterrupts); - ixNpeMhInitialized = TRUE; + ixNpeMhInitialized = true; IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " "ixNpeMhInitialize\n"); @@ -153,7 +153,7 @@ PUBLIC IX_STATUS ixNpeMhUnload (void) /* Uninitialize the Configuration module */ ixNpeMhConfigUninit (); - ixNpeMhInitialized = FALSE; + ixNpeMhInitialized = false; IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " "ixNpeMhUnload\n"); diff --git a/drivers/net/npe/IxNpeMhConfig.c b/drivers/net/npe/IxNpeMhConfig.c index 50c8f21..092d480 100644 --- a/drivers/net/npe/IxNpeMhConfig.c +++ b/drivers/net/npe/IxNpeMhConfig.c @@ -105,7 +105,7 @@ IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] = 0, 0, NULL, - FALSE + false }, { 0, @@ -116,7 +116,7 @@ IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] = 0, 0, NULL, - FALSE + false }, { 0, @@ -127,7 +127,7 @@ IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] = 0, 0, NULL, - FALSE + false } }; diff --git a/drivers/net/npe/IxNpeMhSend.c b/drivers/net/npe/IxNpeMhSend.c index 318913a..27bc9b7 100644 --- a/drivers/net/npe/IxNpeMhSend.c +++ b/drivers/net/npe/IxNpeMhSend.c @@ -124,7 +124,7 @@ BOOL ixNpeMhSendInFifoIsFull( IxNpeMhNpeId npeId, UINT32 maxSendRetries) { - BOOL isFull = FALSE; + BOOL isFull = false; UINT32 numRetries = 0; /* check the NPE's inFIFO */ diff --git a/drivers/net/npe/IxOsalOsSemaphore.c b/drivers/net/npe/IxOsalOsSemaphore.c index 443aefd..672bec1 100644 --- a/drivers/net/npe/IxOsalOsSemaphore.c +++ b/drivers/net/npe/IxOsalOsSemaphore.c @@ -135,10 +135,10 @@ static void drv_mutex_destroy(IxOsalMutex *mutex) static int drv_mutex_trylock(IxOsalMutex *mutex) { - int result = TRUE; + int result = true; if (*mutex == 1) - result = FALSE; + result = false; return result; } diff --git a/drivers/net/npe/IxQMgrDispatcher.c b/drivers/net/npe/IxQMgrDispatcher.c index 9cb1439..25a3e85 100644 --- a/drivers/net/npe/IxQMgrDispatcher.c +++ b/drivers/net/npe/IxQMgrDispatcher.c @@ -160,7 +160,7 @@ static IxQMgrQId priorityTable[IX_QMGR_MAX_NUM_QUEUES]; /* * This flag indicates to the dispatcher that the priority table needs to be rebuilt. */ -static BOOL rebuildTable = FALSE; +static BOOL rebuildTable = false; /* Dispatcher statistics */ static IxQMgrDispatcherStats dispatcherStats; @@ -197,7 +197,7 @@ ixQMgrDispatcherInit (void) int i; IxFeatureCtrlProductId productId = 0; IxFeatureCtrlDeviceId deviceId = 0; - BOOL stickyIntSilicon = TRUE; + BOOL stickyIntSilicon = true; /* Set default priorities */ for (i=0; i< IX_QMGR_MAX_NUM_QUEUES; i++) @@ -226,7 +226,7 @@ ixQMgrDispatcherInit (void) dispatcherStats.queueStats[i].priorityChangeCnt = 0; dispatcherStats.queueStats[i].intNoCallbackCnt = 0; dispatcherStats.queueStats[i].intLostCallbackCnt = 0; - dispatcherStats.queueStats[i].notificationEnabled = FALSE; + dispatcherStats.queueStats[i].notificationEnabled = false; dispatcherStats.queueStats[i].srcSel = 0; } @@ -258,7 +258,7 @@ ixQMgrDispatcherInit (void) (IX_FEATURE_CTRL_SILICON_TYPE_A0 == (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId))) { - stickyIntSilicon = FALSE; + stickyIntSilicon = false; } /* @@ -293,7 +293,7 @@ ixQMgrDispatcherPrioritySet (IxQMgrQId qId, /* Change priority */ dispatchQInfo[qId].priority = priority; /* Set flag */ - rebuildTable = TRUE; + rebuildTable = true; ixOsalIrqUnlock(ixQMgrLockKey); @@ -364,7 +364,7 @@ ixQMgrNotificationEnable (IxQMgrQId qId, #endif #ifndef NDEBUG - dispatcherStats.queueStats[qId].notificationEnabled = TRUE; + dispatcherStats.queueStats[qId].notificationEnabled = true; dispatcherStats.queueStats[qId].srcSel = srcSel; #endif @@ -428,7 +428,7 @@ ixQMgrNotificationDisable (IxQMgrQId qId) * so need critical section */ #ifndef NDEBUG - dispatcherStats.queueStats[qId].notificationEnabled = FALSE; + dispatcherStats.queueStats[qId].notificationEnabled = false; #endif ixQMgrLockKey = ixOsalIrqLock(); @@ -593,7 +593,7 @@ ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group) qIndex += IX_QMGR_MIN_QUEUPP_QID; } - if (statusChangeFlag == FALSE) + if (statusChangeFlag == false) { /* check if the interrupt register contains * only 1 bit set (happy day scenario) @@ -800,7 +800,7 @@ ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group) * For example: * intRegVal = 0x0010 * currDispatchQInfo->intRegCheckMask = 0x0010 - * intRegVal == currDispatchQInfo->intRegCheckMask is TRUE. + * intRegVal == currDispatchQInfo->intRegCheckMask is true. */ currDispatchQInfo = &dispatchQInfo[qIndex]; if (intRegVal == currDispatchQInfo->intRegCheckMask) @@ -955,7 +955,7 @@ ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group) * For example: * intRegVal = 0x0010 * currDispatchQInfo->intRegCheckMask = 0x0010 - * intRegVal == currDispatchQInfo->intRegCheckMask is TRUE. + * intRegVal == currDispatchQInfo->intRegCheckMask is true. */ currDispatchQInfo = &dispatchQInfo[qIndex]; if (intRegVal == currDispatchQInfo->intRegCheckMask) @@ -1118,7 +1118,7 @@ ixQMgrDispatcherReBuildPriorityTable (void) int uppQuePriorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; /* Reset the rebuild flag */ - rebuildTable = FALSE; + rebuildTable = false; /* initialize the mak used to identify the queues in the first half * of the priority table @@ -1266,7 +1266,7 @@ ixQMgrPeriodicDone (void) * Update statistics */ dispatcherStats.queueStats[i].enableCount++; - dispatcherStats.queueStats[i].notificationEnabled = TRUE; + dispatcherStats.queueStats[i].notificationEnabled = true; #endif } } diff --git a/drivers/net/npe/IxQMgrInit.c b/drivers/net/npe/IxQMgrInit.c index b00c22d..61ca96c 100644 --- a/drivers/net/npe/IxQMgrInit.c +++ b/drivers/net/npe/IxQMgrInit.c @@ -66,7 +66,7 @@ * Set to true if initialized * N.B. global so integration/unit tests can reinitialize */ -BOOL qMgrIsInitialized = FALSE; +BOOL qMgrIsInitialized = false; /* * Function definitions. @@ -90,7 +90,7 @@ ixQMgrInit (void) ixQMgrQAccessInit (); /* Initialization complete */ - qMgrIsInitialized = TRUE; + qMgrIsInitialized = true; return IX_SUCCESS; } @@ -107,7 +107,7 @@ ixQMgrUnload (void) ixQMgrQCfgUninit (); /* Uninitialization complete */ - qMgrIsInitialized = FALSE; + qMgrIsInitialized = false; return IX_SUCCESS; } diff --git a/drivers/net/npe/IxQMgrQCfg.c b/drivers/net/npe/IxQMgrQCfg.c index ec7d837..26ec327 100644 --- a/drivers/net/npe/IxQMgrQCfg.c +++ b/drivers/net/npe/IxQMgrQCfg.c @@ -94,7 +94,7 @@ typedef struct char qName[IX_QMGR_MAX_QNAME_LEN+1]; /* Textual description of a queue*/ IxQMgrQSizeInWords qSizeInWords; /* The number of words in the queue */ IxQMgrQEntrySizeInWords qEntrySizeInWords; /* Number of words per queue entry*/ - BOOL isConfigured; /* This flag is TRUE if the queue has + BOOL isConfigured; /* This flag is true if the queue has * been configured */ } IxQMgrCfgQ; @@ -120,7 +120,7 @@ static UINT32 freeSramAddress=0; /* 4 words of zeroed memory for inline access */ static UINT32 zeroedPlaceHolder[4] = { 0, 0, 0, 0 }; -static BOOL cfgInitialized = FALSE; +static BOOL cfgInitialized = false; static IxOsalMutex ixQMgrQCfgMutex; @@ -177,10 +177,10 @@ ixQMgrQCfgInit (void) strcpy (cfgQueueInfo[loopIndex].qName, ""); cfgQueueInfo[loopIndex].qSizeInWords = 0; cfgQueueInfo[loopIndex].qEntrySizeInWords = 0; - cfgQueueInfo[loopIndex].isConfigured = FALSE; + cfgQueueInfo[loopIndex].isConfigured = false; /* Statistics */ - stats.qStats[loopIndex].isConfigured = FALSE; + stats.qStats[loopIndex].isConfigured = false; stats.qStats[loopIndex].qName = cfgQueueInfo[loopIndex].qName; } @@ -191,13 +191,13 @@ ixQMgrQCfgInit (void) ixOsalMutexInit(&ixQMgrQCfgMutex); - cfgInitialized = TRUE; + cfgInitialized = true; } void ixQMgrQCfgUninit (void) { - cfgInitialized = FALSE; + cfgInitialized = false; /* Uninitialise the AqmIf component */ ixQMgrAqmIfUninit (); @@ -281,13 +281,13 @@ ixQMgrQConfig (char *qName, IX_QMGR_QUE_BUFFER_SPACE_SIZE); /* The queue is now configured */ - cfgQueueInfo[qId].isConfigured = TRUE; + cfgQueueInfo[qId].isConfigured = true; ixOsalMutexUnlock(&ixQMgrQCfgMutex); #ifndef NDEBUG /* Update statistics */ - stats.qStats[qId].isConfigured = TRUE; + stats.qStats[qId].isConfigured = true; stats.qStats[qId].qName = cfgQueueInfo[qId].qName; #endif return IX_SUCCESS; @@ -417,7 +417,7 @@ ixQMgrQIsConfigured (IxQMgrQId qId) { if (!IX_QMGR_QID_IS_VALID(qId)) { - return FALSE; + return false; } return cfgQueueInfo[qId].isConfigured; @@ -487,7 +487,7 @@ watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level) case IX_QMGR_Q_WM_LEVEL64: break; default: - return FALSE; + return false; } /* Check watermark is not bigger than the qSizeInEntries */ @@ -495,10 +495,10 @@ watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level) if ((unsigned)level > qSizeInEntries) { - return FALSE; + return false; } - return TRUE; + return true; } PRIVATE BOOL @@ -512,10 +512,10 @@ qSizeInWordsIsOk (IxQMgrQSizeInWords qSize) case IX_QMGR_Q_SIZE32: case IX_QMGR_Q_SIZE64: case IX_QMGR_Q_SIZE128: - status = TRUE; + status = true; break; default: - status = FALSE; + status = false; break; } @@ -532,10 +532,10 @@ qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize) case IX_QMGR_Q_ENTRY_SIZE1: case IX_QMGR_Q_ENTRY_SIZE2: case IX_QMGR_Q_ENTRY_SIZE4: - status = TRUE; + status = true; break; default: - status = FALSE; + status = false; break; } diff --git a/drivers/net/npe/include/IxAtmdAccCtrl.h b/drivers/net/npe/include/IxAtmdAccCtrl.h index 50ef582..7b87345 100644 --- a/drivers/net/npe/include/IxAtmdAccCtrl.h +++ b/drivers/net/npe/include/IxAtmdAccCtrl.h @@ -1933,12 +1933,12 @@ PUBLIC IX_STATUS ixAtmdAccPortDisable (IxAtmLogicalPort port); * @brief disable a PHY logical port * * This function indicates if the port disable for a port has completed. This -* function will return TRUE if the port has never been enabled. +* function will return true if the port has never been enabled. * * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] * -* @return @li TRUE disable is complete -* @return @li FALSE disable failed, wrong parameter . +* @return @li true disable is complete +* @return @li false disable failed, wrong parameter . * * @note - This function needs internal locks and should not be called * from an interrupt context diff --git a/drivers/net/npe/include/IxEthAcc_p.h b/drivers/net/npe/include/IxEthAcc_p.h index 4e0de82..eda3e30 100644 --- a/drivers/net/npe/include/IxEthAcc_p.h +++ b/drivers/net/npe/include/IxEthAcc_p.h @@ -92,7 +92,7 @@ #define IX_ETH_ACC_PUBLIC -#define IX_ETH_ACC_IS_PORT_VALID(port) ((port) < IX_ETH_ACC_NUMBER_OF_PORTS ? TRUE : FALSE ) +#define IX_ETH_ACC_IS_PORT_VALID(port) ((port) < IX_ETH_ACC_NUMBER_OF_PORTS ? true : false ) @@ -286,7 +286,7 @@ extern IxEthAccPortDataInfo ixEthAccPortData[]; #define IX_ETH_IS_PORT_INITIALIZED(port) (ixEthAccPortData[port].portInitialized) extern BOOL ixEthAccServiceInit; -#define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == TRUE ) +#define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == true ) /* * Maximum number of frames to consume from the Rx Frame Q. diff --git a/drivers/net/npe/include/IxEthDB.h b/drivers/net/npe/include/IxEthDB.h index 1189c9a..dfdfe1a 100644 --- a/drivers/net/npe/include/IxEthDB.h +++ b/drivers/net/npe/include/IxEthDB.h @@ -229,7 +229,7 @@ typedef enum IX_ETH_DB_INTEGER_PROPERTY = 0x1, /**< 4 byte unsigned integer type */ IX_ETH_DB_STRING_PROPERTY = 0x2, /**< NULL-terminated string type of maximum 255 characters (including the terminator) */ IX_ETH_DB_MAC_ADDR_PROPERTY = 0x3, /**< 6 byte MAC address type */ - IX_ETH_DB_BOOL_PROPERTY = 0x4 /**< 4 byte boolean type; can contain only TRUE and FALSE values */ + IX_ETH_DB_BOOL_PROPERTY = 0x4 /**< 4 byte boolean type; can contain only true and false values */ } IxEthDBPropertyType; /* list of supported properties for the IX_ETH_DB_VLAN_QOS feature */ @@ -1427,8 +1427,8 @@ IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriori * * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be matched against outgoing frames - * @param enabled BOOL [in] - TRUE to enable Egress VLAN tagging on the port and given VLAN, and - * FALSE to disable Egress VLAN tagging + * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN, and + * false to disable Egress VLAN tagging * * @retval IX_ETH_DB_SUCCESS operation completed successfully * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier @@ -1450,8 +1450,8 @@ IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEt * @param portID [in] - ID of the port to extract the Egress VLAN ID tagging status from * @param vlanID VLAN [in] - ID whose tagging status is to be extracted * @param enabled [in] - user-specifed location where the status is copied to; following - * the successfull execution of this function the value will be TRUE if Egress VLAN - * tagging is enabled for the given port and VLAN ID, and FALSE otherwise + * the successfull execution of this function the value will be true if Egress VLAN + * tagging is enabled for the given port and VLAN ID, and false otherwise * * - Reentrant - no * - ISR Callable - no @@ -1486,8 +1486,8 @@ IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEt * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN range to be matched against outgoing frames * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN range to be matched against outgoing frames - * @param enabled BOOL [in] - TRUE to enable Egress VLAN tagging on the port and given VLAN range, - * and FALSE to disable Egress VLAN tagging + * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN range, + * and false to disable Egress VLAN tagging * * @retval IX_ETH_DB_SUCCESS operation completed successfully * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier @@ -1640,7 +1640,7 @@ IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBT * This feature is disabled by default. * * @param portID ID of the port to configure port ID extraction on - * @param enable TRUE to enable port ID extraction and FALSE to disable it + * @param enable true to enable port ID extraction and false to disable it * * @retval IX_ETH_DB_SUCCESS operation completed successfully * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier @@ -1759,7 +1759,7 @@ IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature * * * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the features on (use IX_ETH_DB_ALL_PORTS for all the ports) * @param feature @ref IxEthDBFeature [in] - feature or feature set to enable or disable - * @param enabled BOOL [in] - TRUE to enable the feature and FALSE to disable it + * @param enabled BOOL [in] - true to enable the feature and false to disable it * * @note Certain features, from a functional point of view, cannot be disabled as such at NPE level; * when such features are set to <i>disabled</i> using the EthDB API they will be configured in such @@ -1786,7 +1786,7 @@ IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, * * This function returns the availability and status for a feature set. * Note that if more than one feature is selected (e.g. IX_ETH_DB_LEARNING | IX_ETH_DB_FILTERING) - * the "present" and "enabled" return values will be set to TRUE only if all the features in the + * the "present" and "enabled" return values will be set to true only if all the features in the * feature set are present and enabled (not only some). * * @param portID @ref IxEthDBPortId [in] - ID of the port @@ -1873,7 +1873,7 @@ IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature fea * - IX_ETH_DB_INTEGER_PROPERTY - 4 bytes are copied from the source location * - IX_ETH_DB_STRING_PROPERTY - the source string will be copied up to the NULL '\0' string terminator, maximum of 255 characters * - IX_ETH_DB_MAC_ADDR_PROPERTY - 6 bytes are copied from the source location - * - IX_ETH_DB_BOOL_PROPERTY - 4 bytes are copied from the source location; the only allowed values are TRUE (1L) and false (0L) + * - IX_ETH_DB_BOOL_PROPERTY - 4 bytes are copied from the source location; the only allowed values are true (1L) and false (0L) * * @see ixEthDBFeaturePropertySet * @@ -2134,7 +2134,7 @@ IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid); * @brief Sets the STP blocked/unblocked state for a port * * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param blocked BOOL [in] - TRUE to set the port as STP blocked, FALSE to set it as unblocked + * @param blocked BOOL [in] - true to set the port as STP blocked, false to set it as unblocked * * @retval IX_ETH_DB_SUCCESS operation completed successfully * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier @@ -2153,7 +2153,7 @@ IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blo * @brief Retrieves the STP blocked/unblocked state for a port * * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param blocked BOOL * [in] - set to TRUE if the port is STP blocked, FALSE otherwise + * @param blocked BOOL * [in] - set to true if the port is STP blocked, false otherwise * * @retval IX_ETH_DB_SUCCESS operation completed successfully * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier @@ -2214,7 +2214,7 @@ IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode m * NPE image. * * @param portID ID of the port - * @param enable TRUE to enable invalid MAC address filtering and FALSE to disable it + * @param enable true to enable invalid MAC address filtering and false to disable it * * @retval IX_ETH_DB_SUCCESS operation completed successfully * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier diff --git a/drivers/net/npe/include/IxEthDB_p.h b/drivers/net/npe/include/IxEthDB_p.h index ccec7ea..d173d12 100644 --- a/drivers/net/npe/include/IxEthDB_p.h +++ b/drivers/net/npe/include/IxEthDB_p.h @@ -169,9 +169,9 @@ extern int overflowEvent; #define TREE_POOL_SIZE (4000) /**< number of MacTreeNode objects; each entry has 16 bytes */ /* retry policies */ -#define BUSY_RETRY_ENABLED (TRUE) /**< if set to TRUE the API will retry automatically calls returning BUSY */ -#define FOREVER_RETRY (TRUE) /**< if set to TRUE the API will retry forever BUSY calls */ -#define MAX_RETRIES (400) /**< upper retry limit - used only when FOREVER_RETRY is FALSE */ +#define BUSY_RETRY_ENABLED (true) /**< if set to true the API will retry automatically calls returning BUSY */ +#define FOREVER_RETRY (true) /**< if set to true the API will retry forever BUSY calls */ +#define MAX_RETRIES (400) /**< upper retry limit - used only when FOREVER_RETRY is false */ #define BUSY_RETRY_YIELD (5) /**< ticks to yield for every failed retry */ /* event management */ @@ -179,8 +179,8 @@ extern int overflowEvent; #define EVENT_PROCESSING_LIMIT (100) /**< batch processing control size (how many events are extracted from the queue at once) */ /* MAC descriptors */ -#define STATIC_ENTRY (TRUE) -#define DYNAMIC_ENTRY (FALSE) +#define STATIC_ENTRY (true) +#define DYNAMIC_ENTRY (false) /* age reset on next maintenance - incrementing by 1 will reset to 0 */ #define AGE_RESET (0xFFFFFFFF) @@ -270,7 +270,7 @@ extern int overflowEvent; /* gives an empty dependency map */ #define SET_EMPTY_DEPENDENCY_MAP(map) { int i = 0; for (; i < 32 ; i++) map[i] = 0; } -#define IS_EMPTY_DEPENDENCY_MAP(result, map) { int i = 0 ; result = TRUE; for (; i < 32 ; i++) if (map[i] != 0) { result = FALSE; break; }} +#define IS_EMPTY_DEPENDENCY_MAP(result, map) { int i = 0 ; result = true; for (; i < 32 ; i++) if (map[i] != 0) { result = false; break; }} /** * gives a map consisting only of 'portID' @@ -293,12 +293,12 @@ extern int overflowEvent; #define EXCLUDE_PORT_FROM_MAP(map, portID) { map[portID >> 3] &= ~(1 << (portID & 0x7); } /** - * returns TRUE if map1 is a subset of map2 and FALSE otherwise + * returns true if map1 is a subset of map2 and false otherwise */ -#define IS_MAP_SUBSET(result, map1, map2) { int i = 0; result = TRUE; for (; i < 32 ; i++) if ((map1[i] | map2[i]) != map2[i]) result = FALSE; } +#define IS_MAP_SUBSET(result, map1, map2) { int i = 0; result = true; for (; i < 32 ; i++) if ((map1[i] | map2[i]) != map2[i]) result = false; } /** - * returns TRUE is portID is part of map and FALSE otherwise + * returns true is portID is part of map and false otherwise */ #define IS_PORT_INCLUDED(portID, map) ((map[portID >> 3] & (1 << (portID & 0x7))) != 0) @@ -308,9 +308,9 @@ extern int overflowEvent; #define DIFF_MAPS(map, map1, map2) { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] ^ (map1[i] & map2[i]); } /** - * returns TRUE if the maps collide (have at least one port in common) and FALSE otherwise + * returns true if the maps collide (have at least one port in common) and false otherwise */ -#define MAPS_COLLIDE(result, map1, map2) { int i = 0; result = FALSE; for (; i < 32 ; i++) if ((map1[i] & map2[i]) != 0) result = TRUE; } +#define MAPS_COLLIDE(result, map1, map2) { int i = 0; result = false; for (; i < 32 ; i++) if ((map1[i] & map2[i]) != 0) result = true; } /* size (number of ports) of a dependency map */ #define GET_MAP_SIZE(map, size) { int i = 0, b = 0; size = 0; for (; i < 32 ; i++) { char y = map[i]; for (; b < 8 && (y >>= 1); b++) size += (y & 1); }} @@ -415,7 +415,7 @@ typedef union struct { UINT32 age; - BOOL staticEntry; /**< TRUE if this address is static (doesn't age) */ + BOOL staticEntry; /**< true if this address is static (doesn't age) */ } filteringData; struct @@ -492,26 +492,26 @@ typedef void (*IxEthDBNoteWriteFn)(void *address, MacTreeNode *node); typedef struct { - BOOL updateEnabled; /**< TRUE if updates are enabled for port */ - BOOL userControlled; /**< TRUE if the user has manually used ixEthDBPortUpdateEnableSet */ - BOOL treeInitialized; /**< TRUE if the NPE has received an initial tree */ + BOOL updateEnabled; /**< true if updates are enabled for port */ + BOOL userControlled; /**< true if the user has manually used ixEthDBPortUpdateEnableSet */ + BOOL treeInitialized; /**< true if the NPE has received an initial tree */ IxEthDBPortUpdateHandler updateHandler; /**< port update handler routine */ void *npeUpdateZone; /**< port update memory zone */ void *npeGwUpdateZone; /**< port update memory zone for gateways */ void *vlanUpdateZone; /**< port update memory zone for VLAN tables */ MacTreeNode *searchTree; /**< internal search tree, in MacTreeNode representation */ - BOOL searchTreePendingWrite; /**< TRUE if searchTree holds a tree pending write to the port */ + BOOL searchTreePendingWrite; /**< true if searchTree holds a tree pending write to the port */ } PortUpdateMethod; typedef struct { IxEthDBPortId portID; /**< port ID */ - BOOL enabled; /**< TRUE if the port is enabled */ - BOOL agingEnabled; /**< TRUE if aging on this port is enabled */ + BOOL enabled; /**< true if the port is enabled */ + BOOL agingEnabled; /**< true if aging on this port is enabled */ BOOL initialized; IxEthDBPortMap dependencyPortMap; /**< dependency port map for this port */ PortUpdateMethod updateMethod; /**< update method structure */ - BOOL macAddressUploaded; /**< TRUE if the MAC address was uploaded into the port */ + BOOL macAddressUploaded; /**< true if the MAC address was uploaded into the port */ UINT32 maxRxFrameSize; /**< maximum Rx frame size for this port */ UINT32 maxTxFrameSize; /**< maximum Rx frame size for this port */ diff --git a/drivers/net/npe/include/IxEthMii.h b/drivers/net/npe/include/IxEthMii.h index 397253a..93d3b79 100644 --- a/drivers/net/npe/include/IxEthMii.h +++ b/drivers/net/npe/include/IxEthMii.h @@ -83,7 +83,7 @@ * * @brief Scan the MDIO bus for PHYs * This function scans PHY addresses 0 through 31, and sets phyPresent[n] to - * TRUE if a phy is discovered at address n. + * true if a phy is discovered at address n. * * - Reentrant - no * - ISR Callable - no @@ -120,9 +120,9 @@ PUBLIC IX_STATUS ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount); * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. * * @param phyAddr UINT32 [in] - * @param speed100 BOOL [in] - set to TRUE for 100Mbit/s operation, FALSE for 10Mbit/s - * @param fullDuplex BOOL [in] - set to TRUE for Full Duplex, FALSE for Half Duplex - * @param autonegotiate BOOL [in] - set to TRUE to enable autonegotiation + * @param speed100 BOOL [in] - set to true for 100Mbit/s operation, false for 10Mbit/s + * @param fullDuplex BOOL [in] - set to true for Full Duplex, false for Half Duplex + * @param autonegotiate BOOL [in] - set to true to enable autonegotiation * * @return IX_STATUS * - IX_SUCCESS @@ -223,10 +223,10 @@ PUBLIC IX_STATUS ixEthMiiPhyReset(UINT32 phyAddr); * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. * * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * @param linkUp BOOL [out] - set to TRUE if the link is up - * @param speed100 BOOL [out] - set to TRUE indicates 100Mbit/s, FALSE indicates 10Mbit/s - * @param fullDuplex BOOL [out] - set to TRUE indicates Full Duplex, FALSE indicates Half Duplex - * @param autoneg BOOL [out] - set to TRUE indicates autonegotiation is enabled, FALSE indicates autonegotiation is disabled + * @param linkUp BOOL [out] - set to true if the link is up + * @param speed100 BOOL [out] - set to true indicates 100Mbit/s, false indicates 10Mbit/s + * @param fullDuplex BOOL [out] - set to true indicates Full Duplex, false indicates Half Duplex + * @param autoneg BOOL [out] - set to true indicates autonegotiation is enabled, false indicates autonegotiation is disabled * * @return IX_STATUS * - IX_SUCCESS diff --git a/drivers/net/npe/include/IxFeatureCtrl.h b/drivers/net/npe/include/IxFeatureCtrl.h index dabc38e..1662a00 100644 --- a/drivers/net/npe/include/IxFeatureCtrl.h +++ b/drivers/net/npe/include/IxFeatureCtrl.h @@ -706,14 +706,14 @@ ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType); * @brief This function enable/disable the specified software configuration. * * Usage Example:<br> - * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, TRUE) is used + * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, true) is used * to enable Ethernet Learning Feature <br> - * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, FALSE) is used + * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false) is used * to disable Ethernet Learning Feature <br> * * @param swConfigType IxFeatureCtrlSwConfig [in] - the type of a software configuration * defined in IxFeatureCtrlSwConfig enumeration. - * @param enabled BOOL [in] - To enable(TRUE) / disable (FALSE) the specified software + * @param enabled BOOL [in] - To enable(true) / disable (false) the specified software * configuration. * * @return none diff --git a/drivers/net/npe/include/IxHssAcc.h b/drivers/net/npe/include/IxHssAcc.h index 07bb119..52d5716 100644 --- a/drivers/net/npe/include/IxHssAcc.h +++ b/drivers/net/npe/include/IxHssAcc.h @@ -583,12 +583,12 @@ typedef struct */ typedef struct { - BOOL hdlc56kMode; /**< 56kbps(TRUE)/64kbps(FALSE) HDLC */ + BOOL hdlc56kMode; /**< 56kbps(true)/64kbps(false) HDLC */ IxHssAcc56kEndianness hdlc56kEndian; /**< 56kbps data endianness - - ignored if hdlc56kMode is FALSE*/ - BOOL hdlc56kUnusedBitPolarity0; /**< The polarity '0'(TRUE)/'1'(FALSE) of the unused + - ignored if hdlc56kMode is false*/ + BOOL hdlc56kUnusedBitPolarity0; /**< The polarity '0'(true)/'1'(false) of the unused bit while in 56kbps mode - - ignored if hdlc56kMode is FALSE*/ + - ignored if hdlc56kMode is false*/ } IxHssAccHdlcMode; /** @@ -1006,9 +1006,9 @@ ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId, * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 * * @return - * - TRUE The state of this HSS/HDLC port combination is disconnected, + * - true The state of this HSS/HDLC port combination is disconnected, * so if a disconnect was called, it is now completed. - * - FALSE The state of this HSS/HDLC port combination is connected, + * - false The state of this HSS/HDLC port combination is connected, * so if a disconnect was called, it is not yet completed. */ PUBLIC BOOL @@ -1259,7 +1259,7 @@ ixHssAccChanDisconnect (IxHssAccHssPort hssPortId); * identical ports (0-1). * @param *dataRecvd BOOL [out] - This BOOL indicates to the client whether * or not the access component has read any data for the client. If - * FALSE, the other output parameters will not have been written to. + * false, the other output parameters will not have been written to. * @param *rxOffset unsigned [out] - An offset to indicate to the client * where within the receive buffers the NPE has just written the received * data to. diff --git a/drivers/net/npe/include/IxNpeDl.h b/drivers/net/npe/include/IxNpeDl.h index 86f69f4..f514c2e 100644 --- a/drivers/net/npe/include/IxNpeDl.h +++ b/drivers/net/npe/include/IxNpeDl.h @@ -637,7 +637,7 @@ ixNpeDlMicrocodeImageLibraryOverride (UINT32 *clientImageLibrary); * @param imageIdPtr @ref IxNpeDlImageId* [in] - Pointer to Id of the microcode * image to download. * @param verify BOOL [in] - ON/OFF option to verify the download. If ON - * (verify == TRUE), the Downloader will read back + * (verify == true), the Downloader will read back * each word written to the NPE registers to * ensure the download operation was successful. * diff --git a/drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h b/drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h index a752f26..876a438 100644 --- a/drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h +++ b/drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h @@ -81,7 +81,7 @@ * @param UINT32 [in] npeBaseAddress - Base Address of NPE * @param UINT32 [in] insMemAddress - NPE instruction memory address to write * @param UINT32 [in] insMemData - data to write to instruction memory - * @param BOOL [in] verify - if TRUE, verify the memory location is + * @param BOOL [in] verify - if true, verify the memory location is * written successfully. * * This function is used to write a single word of data to a location in NPE @@ -93,7 +93,7 @@ * @post * * @return - * - IX_FAIL if verify is TRUE and the memory location was not written + * - IX_FAIL if verify is true and the memory location was not written * successfully * - IX_SUCCESS otherwise */ @@ -113,7 +113,7 @@ ixNpeDlNpeMgrInsMemWrite (UINT32 npeBaseAddress, UINT32 insMemAddress, * @param UINT32 [in] npeBaseAddress - Base Address of NPE * @param UINT32 [in] dataMemAddress - NPE data memory address to write * @param UINT32 [in] dataMemData - data to write to NPE data memory - * @param BOOL [in] verify - if TRUE, verify the memory location is + * @param BOOL [in] verify - if true, verify the memory location is * written successfully. * * This function is used to write a single word of data to a location in NPE @@ -125,7 +125,7 @@ ixNpeDlNpeMgrInsMemWrite (UINT32 npeBaseAddress, UINT32 insMemAddress, * @post * * @return - * - IX_FAIL if verify is TRUE and the memory location was not written + * - IX_FAIL if verify is true and the memory location was not written * successfully * - IX_SUCCESS otherwise */ @@ -304,7 +304,7 @@ ixNpeDlNpeMgrDebugInstructionPostExec (UINT32 npeBaseAddress); * @param UINT32 [in] npeBaseAddress - Base Address of NPE * @param UINT32 [in] regAddr - number of the physical register (0-31)* * @param UINT32 [in] regValue - value to write to the physical register - * @param BOOL [in] verify - if TRUE, verify the register is written + * @param BOOL [in] verify - if true, verify the register is written * successfully. * * This function writes a physical register in the NPE data register file. @@ -324,7 +324,7 @@ ixNpeDlNpeMgrDebugInstructionPostExec (UINT32 npeBaseAddress); * a sequence of calls to this function * * @return - * - IX_FAIL if verify is TRUE and the Context Register was not written + * - IX_FAIL if verify is true and the Context Register was not written * successfully * - IX_SUCCESS if Context Register was written successfully * - IX_NPEDL_CRITICAL_NPE_ERR if Context Register was not written @@ -349,7 +349,7 @@ ixNpeDlNpeMgrPhysicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr, * @param IxNpeDlCtxtRegNum [in] ctxtReg - which Context Store reg to write * @param UINT32 [in] ctxtRegVal - value to write to the Context Store * register - * @param BOOL [in] verify - if TRUE, verify the register is + * @param BOOL [in] verify - if true, verify the register is * written successfully. * * This function writes the contents of a Context Store register in the NPE @@ -366,7 +366,7 @@ ixNpeDlNpeMgrPhysicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr, * a sequence of calls to this function * * @return - * - IX_FAIL if verify is TRUE and the Context Register was not written + * - IX_FAIL if verify is true and the Context Register was not written * successfully * - IX_SUCCESS if Context Register was written successfully * - IX_NPEDL_CRITICAL_NPE_ERR if Context Register was not written diff --git a/drivers/net/npe/include/IxNpeDlNpeMgr_p.h b/drivers/net/npe/include/IxNpeDlNpeMgr_p.h index b7fb0f0..e25e532 100644 --- a/drivers/net/npe/include/IxNpeDlNpeMgr_p.h +++ b/drivers/net/npe/include/IxNpeDlNpeMgr_p.h @@ -126,7 +126,7 @@ IX_STATUS ixNpeDlNpeMgrUninit (void); * @param IxNpeDlNpeId [in] npeId - Id of target NPE * @param UINT32* [in] imageCodePtr - pointer to image code in image to be * downloaded - * @param BOOL [in] verify - if TRUE, verify each word written to + * @param BOOL [in] verify - if true, verify each word written to * NPE memory. * * This function loads a image containing blocks of microcode onto a diff --git a/drivers/net/npe/include/IxNpeMhConfig_p.h b/drivers/net/npe/include/IxNpeMhConfig_p.h index 375b346..8c8b9ab 100644 --- a/drivers/net/npe/include/IxNpeMhConfig_p.h +++ b/drivers/net/npe/include/IxNpeMhConfig_p.h @@ -110,7 +110,7 @@ typedef struct UINT32 inFifoRegister; /**< inFIFO register virutal address */ UINT32 outFifoRegister; /**< outFIFO register virtual address */ IxNpeMhConfigIsr isr; /**< isr routine for handling interrupt */ - BOOL oldInterruptState; /**< old interrupt state (TRUE => enabled) */ + BOOL oldInterruptState; /**< old interrupt state (true => enabled) */ } IxNpeMhConfigNpeInfo; @@ -250,7 +250,7 @@ void ixNpeMhConfigIsrRegister ( * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will * be enabled. * - * @return Returns the previous state of the interrupt (TRUE => enabled). + * @return Returns the previous state of the interrupt (true => enabled). */ BOOL ixNpeMhConfigNpeInterruptEnable ( @@ -265,7 +265,7 @@ BOOL ixNpeMhConfigNpeInterruptEnable ( * @param IxNpeMhNpeId npeId (in) - the ID of the NPE whose interrupt will * be disabled. * - * @return Returns the previous state of the interrupt (TRUE => enabled). + * @return Returns the previous state of the interrupt (true => enabled). */ BOOL ixNpeMhConfigNpeInterruptDisable ( @@ -293,7 +293,7 @@ IxNpeMhMessageId ixNpeMhConfigMessageIdGet ( * * @param IxNpeMhNpeId npeId (in) - the NPE ID to validate. * - * @return True if the NPE ID is valid, otherwise False. + * @return true if the NPE ID is valid, otherwise false. */ BOOL ixNpeMhConfigNpeIdIsValid ( @@ -340,7 +340,7 @@ void ixNpeMhConfigLockRelease ( * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO * will be checked. * - * @return True if the inFIFO is empty, otherwise False. + * @return true if the inFIFO is empty, otherwise false. */ IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsEmpty ( @@ -355,7 +355,7 @@ IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsEmpty ( * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the inFIFO * will be checked. * - * @return True if the inFIFO is full, otherwise False. + * @return true if the inFIFO is full, otherwise false. */ IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsFull ( @@ -370,7 +370,7 @@ IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigInFifoIsFull ( * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO * will be checked. * - * @return True if the outFIFO is empty, otherwise False. + * @return true if the outFIFO is empty, otherwise false. */ IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsEmpty ( @@ -385,7 +385,7 @@ IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsEmpty ( * @param IxNpeMhNpeId npeId (in) - The ID of the NPE for which the outFIFO * will be checked. * - * @return True if the outFIFO is full, otherwise False. + * @return true if the outFIFO is full, otherwise false. */ IXNPEMHCONFIG_INLINE BOOL ixNpeMhConfigOutFifoIsFull ( diff --git a/drivers/net/npe/include/IxOsal.h b/drivers/net/npe/include/IxOsal.h index 4ca2e45..28c44af 100644 --- a/drivers/net/npe/include/IxOsal.h +++ b/drivers/net/npe/include/IxOsal.h @@ -1204,8 +1204,8 @@ PUBLIC void ixOsalTicksToTimeval (UINT32 ticks, IxOsalTimeval * pTv); * @li Reentrant: yes * @li IRQ safe: yes * - * @return - TRUE if the structures are equal - * - FALSE otherwise + * @return - true if the structures are equal + * - false otherwise * Note: This function is OS-independant */ #define IX_OSAL_TIME_EQ(tvA, tvB) \ @@ -1225,8 +1225,8 @@ PUBLIC void ixOsalTicksToTimeval (UINT32 ticks, IxOsalTimeval * pTv); * @li Reentrant: yes * @li IRQ safe: yes * - * @return - TRUE if tvA < tvB - * - FALSE otherwise + * @return - true if tvA < tvB + * - false otherwise * Note: This function is OS-independent. Implemented by core. */ #define IX_OSAL_TIME_LT(tvA,tvB) \ @@ -1247,8 +1247,8 @@ PUBLIC void ixOsalTicksToTimeval (UINT32 ticks, IxOsalTimeval * pTv); * @li Reentrant: yes * @li IRQ safe: yes * - * @return - TRUE if tvA > tvB - * - FALSE otherwise + * @return - true if tvA > tvB + * - false otherwise * Note: This function is OS-independent. */ #define IX_OSAL_TIME_GT(tvA, tvB) \ diff --git a/drivers/net/npe/include/IxOsalTypes.h b/drivers/net/npe/include/IxOsalTypes.h index a190a70..06e71de 100644 --- a/drivers/net/npe/include/IxOsalTypes.h +++ b/drivers/net/npe/include/IxOsalTypes.h @@ -107,22 +107,6 @@ typedef volatile INT32 VINT32; */ #define IX_OSAL_BILLION (1000000000) -#ifndef TRUE -#define TRUE 1L -#endif - -#if TRUE != 1 -#error TRUE is not defined to 1 -#endif - -#ifndef FALSE -#define FALSE 0L -#endif - -#if FALSE != 0 -#error FALSE is not defined to 0 -#endif - #ifndef NULL #define NULL 0L #endif diff --git a/drivers/net/npe/include/IxPerfProfAcc.h b/drivers/net/npe/include/IxPerfProfAcc.h index 65c0ba9..7e4527a 100644 --- a/drivers/net/npe/include/IxPerfProfAcc.h +++ b/drivers/net/npe/include/IxPerfProfAcc.h @@ -1281,8 +1281,8 @@ ixPerfProfAccXcycleResultsGet ( * Check if Xcycle measuring task is running. * * @return - * - TRUE - Xcycle is running - * - FALSE - Xcycle is not running + * - true - Xcycle is running + * - false - Xcycle is not running * * @li Reentrant : no * @li ISR Callable : no diff --git a/drivers/net/npe/include/IxQMgrAqmIf_p.h b/drivers/net/npe/include/IxQMgrAqmIf_p.h index 4f0f64d..b63c4a9 100644 --- a/drivers/net/npe/include/IxQMgrAqmIf_p.h +++ b/drivers/net/npe/include/IxQMgrAqmIf_p.h @@ -606,10 +606,10 @@ ixQMgrAqmIfQStatusCheck (UINT32 *oldQStatusWords, (newQStatusWords[statusWordOffset] & mask)) && ((newQStatusWords[statusWordOffset] & mask) == checkValue)) { - return TRUE; + return true; } - return FALSE; + return false; } /* @@ -665,7 +665,7 @@ ixQMgrAqmIfQInterruptEnableRegRead (IxQMgrDispatchGroup group, /* * This inline function will read the status bit of a queue - * specified by qId. If reset is TRUE the bit is cleared. + * specified by qId. If reset is true the bit is cleared. */ IX_QMGR_AQMIF_INLINE BOOL ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, @@ -707,11 +707,11 @@ ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId, { ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset)); } - return TRUE; + return true; } /* Bit not set */ - return FALSE; + return false; } @@ -733,12 +733,12 @@ ixQMgrAqmIfUnderflowCheck (IxQMgrQId qId) IX_QMGR_QUEUOSTAT0_OFFSET, IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD, IX_QMGR_UNDERFLOW_BIT_OFFSET, - TRUE/*reset*/)); + true/*reset*/)); } else { /* Qs 32-63 have no underflow status */ - return FALSE; + return false; } } @@ -755,12 +755,12 @@ ixQMgrAqmIfOverflowCheck (IxQMgrQId qId) IX_QMGR_QUEUOSTAT0_OFFSET, IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD, IX_QMGR_OVERFLOW_BIT_OFFSET, - TRUE/*reset*/)); + true/*reset*/)); } else { /* Qs 32-63 have no overflow status */ - return FALSE; + return false; } } @@ -870,7 +870,7 @@ ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId, IX_QMGR_QUEUPPSTAT0_OFFSET, IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD, 0/*relativeBitOffset*/, - FALSE/*!reset*/)) + false/*!reset*/)) { *status |= IX_QMGR_Q_STATUS_NE_BIT_MASK; } @@ -884,7 +884,7 @@ ixQMgrAqmIfQueUppStatRead (IxQMgrQId qId, IX_QMGR_QUEUPPSTAT1_OFFSET, IX_QMGR_QUEUPPSTAT_NUM_QUE_PER_WORD, 0/*relativeBitOffset*/, - FALSE/*!reset*/)) + false/*!reset*/)) { *status |= IX_QMGR_Q_STATUS_F_BIT_MASK; } diff --git a/drivers/net/npe/include/IxSspAcc.h b/drivers/net/npe/include/IxSspAcc.h index 35e7abf..61d911b 100644 --- a/drivers/net/npe/include/IxSspAcc.h +++ b/drivers/net/npe/include/IxSspAcc.h @@ -898,7 +898,7 @@ ixSspAccTxFIFOIntDisable ( * * @brief Enables/disables the loopback mode * - * @param "BOOL [in] loopbackEnable" - True to enable and false to disable. + * @param "BOOL [in] loopbackEnable" - true to enable and false to disable. * * Global Data : * - None. diff --git a/drivers/net/npe/include/IxTimeSyncAcc.h b/drivers/net/npe/include/IxTimeSyncAcc.h index 25effed..52c4c1c 100644 --- a/drivers/net/npe/include/IxTimeSyncAcc.h +++ b/drivers/net/npe/include/IxTimeSyncAcc.h @@ -497,8 +497,8 @@ ixTimeSyncAccTargetTimeInterruptDisable(void); * the Target Time in the IEEE 1588 hardware assist block. If the condition is * true an event flag is set in the hardware. * - * @param ttmPollFlag [out] - TRUE if the target time reached/hit condition event set - * FALSE if the target time reached/hit condition event is + * @param ttmPollFlag [out] - true if the target time reached/hit condition event set + * false if the target time reached/hit condition event is not set * @param targetTime [out] - Capture current targetTime into client provided buffer * @@ -656,9 +656,9 @@ ixTimeSyncAccAuxTimeInterruptDisable(IxTimeSyncAccAuxMode auxMode); * (Master or Slave) * * @param auxMode [in] - Auxiliary Snapshot Register (Slave or Master) to be checked - * @param auxPollFlag [out] - TRUE if the time stamp captured in auxiliary + * @param auxPollFlag [out] - true if the time stamp captured in auxiliary snapshot register - * FALSE if the time stamp not captured in + * false if the time stamp not captured in auxiliary snapshot register * @param auxTime [out] - Copy the current Auxiliary Snapshot Register value into the * client provided buffer diff --git a/drivers/net/npe/npe.c b/drivers/net/npe/npe.c index 1fe3a95..6fc9f86 100644 --- a/drivers/net/npe/npe.c +++ b/drivers/net/npe/npe.c @@ -322,7 +322,7 @@ static int npe_csr_load(void) } /* don't need this for U-Boot */ - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, FALSE); + ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false); if (ixEthAccInit() != IX_ETH_ACC_SUCCESS) { printf("Error initialising Ethernet access driver!\n"); @@ -647,29 +647,29 @@ int npe_initialize(bd_t * bis) */ if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_1] = TRUE; + npe_exists[IX_ETH_PORT_1] = true; if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_2] = TRUE; + npe_exists[IX_ETH_PORT_2] = true; break; case IX_FEATURE_CTRL_SILICON_TYPE_A0: /* * If it is A0 Silicon, we enable both as both Eth Coprocessors * are available. */ - npe_exists[IX_ETH_PORT_1] = TRUE; - npe_exists[IX_ETH_PORT_2] = TRUE; + npe_exists[IX_ETH_PORT_1] = true; + npe_exists[IX_ETH_PORT_2] = true; break; } } else if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X) { if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_1] = TRUE; + npe_exists[IX_ETH_PORT_1] = true; if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_2] = TRUE; + npe_exists[IX_ETH_PORT_2] = true; } npe_used[IX_ETH_PORT_1] = 1; diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 8c71901..1dac16a 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libpower.o +COBJS-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o COBJS-$(CONFIG_FTPMU010_POWER) += ftpmu010.o COBJS-$(CONFIG_TPS6586X_POWER) += tps6586x.o COBJS-$(CONFIG_TWL4030_POWER) += twl4030.o diff --git a/drivers/power/exynos-tmu.c b/drivers/power/exynos-tmu.c new file mode 100644 index 0000000..d4b3e65 --- /dev/null +++ b/drivers/power/exynos-tmu.c @@ -0,0 +1,319 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Akshay Saraswat <akshay.s@samsung.com> + * + * EXYNOS - Thermal Management Unit + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <errno.h> +#include <fdtdec.h> +#include <tmu.h> +#include <asm/arch/tmu.h> +#include <asm/arch/power.h> + +#define TRIMINFO_RELOAD 1 +#define CORE_EN 1 +#define THERM_TRIP_EN (1 << 12) + +#define INTEN_RISE0 1 +#define INTEN_RISE1 (1 << 4) +#define INTEN_RISE2 (1 << 8) +#define INTEN_FALL0 (1 << 16) +#define INTEN_FALL1 (1 << 20) +#define INTEN_FALL2 (1 << 24) + +#define TRIM_INFO_MASK 0xff + +#define INTCLEAR_RISE0 1 +#define INTCLEAR_RISE1 (1 << 4) +#define INTCLEAR_RISE2 (1 << 8) +#define INTCLEAR_FALL0 (1 << 16) +#define INTCLEAR_FALL1 (1 << 20) +#define INTCLEAR_FALL2 (1 << 24) +#define INTCLEARALL (INTCLEAR_RISE0 | INTCLEAR_RISE1 | \ + INTCLEAR_RISE2 | INTCLEAR_FALL0 | \ + INTCLEAR_FALL1 | INTCLEAR_FALL2) + +/* Tmeperature threshold values for various thermal events */ +struct temperature_params { + /* minimum value in temperature code range */ + unsigned int min_val; + /* maximum value in temperature code range */ + unsigned int max_val; + /* temperature threshold to start warning */ + unsigned int start_warning; + /* temperature threshold CPU tripping */ + unsigned int start_tripping; + /* temperature threshold for HW tripping */ + unsigned int hardware_tripping; +}; + +/* Pre-defined values and thresholds for calibration of current temperature */ +struct tmu_data { + /* pre-defined temperature thresholds */ + struct temperature_params ts; + /* pre-defined efuse range minimum value */ + unsigned int efuse_min_value; + /* pre-defined efuse value for temperature calibration */ + unsigned int efuse_value; + /* pre-defined efuse range maximum value */ + unsigned int efuse_max_value; + /* current temperature sensing slope */ + unsigned int slope; +}; + +/* TMU device specific details and status */ +struct tmu_info { + /* base Address for the TMU */ + unsigned tmu_base; + /* pre-defined values for calibration and thresholds */ + struct tmu_data data; + /* value required for triminfo_25 calibration */ + unsigned int te1; + /* value required for triminfo_85 calibration */ + unsigned int te2; + /* Value for measured data calibration */ + int dc_value; + /* enum value indicating status of the TMU */ + int tmu_state; +}; + +/* Global struct tmu_info variable to store init values */ +static struct tmu_info gbl_info; + +/* + * Get current temperature code from register, + * then calculate and calibrate it's value + * in degree celsius. + * + * @return current temperature of the chip as sensed by TMU + */ +static int get_cur_temp(struct tmu_info *info) +{ + int cur_temp; + struct exynos5_tmu_reg *reg = (struct exynos5_tmu_reg *)info->tmu_base; + + /* + * Temperature code range between min 25 and max 125. + * May run more than once for first call as initial sensing + * has not yet happened. + */ + do { + cur_temp = readl(®->current_temp) & 0xff; + } while (cur_temp == 0 && info->tmu_state == TMU_STATUS_NORMAL); + + /* Calibrate current temperature */ + cur_temp = cur_temp - info->te1 + info->dc_value; + + return cur_temp; +} + +/* + * Monitors status of the TMU device and exynos temperature + * + * @param temp pointer to the current temperature value + * @return enum tmu_status_t value, code indicating event to execute + */ +enum tmu_status_t tmu_monitor(int *temp) +{ + int cur_temp; + struct tmu_data *data = &gbl_info.data; + + if (gbl_info.tmu_state == TMU_STATUS_INIT) + return TMU_STATUS_INIT; + + /* Read current temperature of the SOC */ + cur_temp = get_cur_temp(&gbl_info); + *temp = cur_temp; + + /* Temperature code lies between min 25 and max 125 */ + if (cur_temp >= data->ts.start_tripping && + cur_temp <= data->ts.max_val) { + return TMU_STATUS_TRIPPED; + } else if (cur_temp >= data->ts.start_warning) { + return TMU_STATUS_WARNING; + } else if (cur_temp < data->ts.start_warning && + cur_temp >= data->ts.min_val) { + return TMU_STATUS_NORMAL; + } else { + /* Temperature code does not lie between min 25 and max 125 */ + gbl_info.tmu_state = TMU_STATUS_INIT; + debug("EXYNOS_TMU: Thermal reading failed\n"); + return TMU_STATUS_INIT; + } +} + +/* + * Get TMU specific pre-defined values from FDT + * + * @param info pointer to the tmu_info struct + * @param blob FDT blob + * @return int value, 0 for success + */ +static int get_tmu_fdt_values(struct tmu_info *info, const void *blob) +{ +#ifdef CONFIG_OF_CONTROL + int node; + int error = 0; + + /* Get the node from FDT for TMU */ + node = fdtdec_next_compatible(blob, 0, + COMPAT_SAMSUNG_EXYNOS_TMU); + if (node < 0) { + debug("EXYNOS_TMU: No node for tmu in device tree\n"); + return -1; + } + + /* + * Get the pre-defined TMU specific values from FDT. + * All of these are expected to be correct otherwise + * miscalculation of register values in tmu_setup_parameters + * may result in misleading current temperature. + */ + info->tmu_base = fdtdec_get_addr(blob, node, "reg"); + if (info->tmu_base == FDT_ADDR_T_NONE) { + debug("%s: Missing tmu-base\n", __func__); + return -1; + } + info->data.ts.min_val = fdtdec_get_int(blob, + node, "samsung,min-temp", -1); + error |= info->data.ts.min_val; + info->data.ts.max_val = fdtdec_get_int(blob, + node, "samsung,max-temp", -1); + error |= info->data.ts.max_val; + info->data.ts.start_warning = fdtdec_get_int(blob, + node, "samsung,start-warning", -1); + error |= info->data.ts.start_warning; + info->data.ts.start_tripping = fdtdec_get_int(blob, + node, "samsung,start-tripping", -1); + error |= info->data.ts.start_tripping; + info->data.ts.hardware_tripping = fdtdec_get_int(blob, + node, "samsung,hw-tripping", -1); + error |= info->data.ts.hardware_tripping; + info->data.efuse_min_value = fdtdec_get_int(blob, + node, "samsung,efuse-min-value", -1); + error |= info->data.efuse_min_value; + info->data.efuse_value = fdtdec_get_int(blob, + node, "samsung,efuse-value", -1); + error |= info->data.efuse_value; + info->data.efuse_max_value = fdtdec_get_int(blob, + node, "samsung,efuse-max-value", -1); + error |= info->data.efuse_max_value; + info->data.slope = fdtdec_get_int(blob, + node, "samsung,slope", -1); + error |= info->data.slope; + info->dc_value = fdtdec_get_int(blob, + node, "samsung,dc-value", -1); + error |= info->dc_value; + + if (error == -1) { + debug("fail to get tmu node properties\n"); + return -1; + } +#endif + + return 0; +} + +/* + * Calibrate and calculate threshold values and + * enable interrupt levels + * + * @param info pointer to the tmu_info struct + */ +static void tmu_setup_parameters(struct tmu_info *info) +{ + unsigned int te_code, con; + unsigned int warning_code, trip_code, hwtrip_code; + unsigned int cooling_temp; + unsigned int rising_value; + struct tmu_data *data = &info->data; + struct exynos5_tmu_reg *reg = (struct exynos5_tmu_reg *)info->tmu_base; + + /* Must reload for reading efuse value from triminfo register */ + writel(TRIMINFO_RELOAD, ®->triminfo_control); + + /* Get the compensation parameter */ + te_code = readl(®->triminfo); + info->te1 = te_code & TRIM_INFO_MASK; + info->te2 = ((te_code >> 8) & TRIM_INFO_MASK); + + if ((data->efuse_min_value > info->te1) || + (info->te1 > data->efuse_max_value) + || (info->te2 != 0)) + info->te1 = data->efuse_value; + + /* Get RISING & FALLING Threshold value */ + warning_code = data->ts.start_warning + + info->te1 - info->dc_value; + trip_code = data->ts.start_tripping + + info->te1 - info->dc_value; + hwtrip_code = data->ts.hardware_tripping + + info->te1 - info->dc_value; + + cooling_temp = 0; + + rising_value = ((warning_code << 8) | + (trip_code << 16) | + (hwtrip_code << 24)); + + /* Set interrupt level */ + writel(rising_value, ®->threshold_temp_rise); + writel(cooling_temp, ®->threshold_temp_fall); + + /* + * Init TMU control tuning parameters + * [28:24] VREF - Voltage reference + * [15:13] THERM_TRIP_MODE - Tripping mode + * [12] THERM_TRIP_EN - Thermal tripping enable + * [11:8] BUF_SLOPE_SEL - Gain of amplifier + * [6] THERM_TRIP_BY_TQ_EN - Tripping by TQ pin + */ + writel(data->slope, ®->tmu_control); + + writel(INTCLEARALL, ®->intclear); + + /* TMU core enable */ + con = readl(®->tmu_control); + con |= THERM_TRIP_EN | CORE_EN; + + writel(con, ®->tmu_control); + + /* Enable HW thermal trip */ + set_hw_thermal_trip(); + + /* LEV1 LEV2 interrupt enable */ + writel(INTEN_RISE1 | INTEN_RISE2, ®->inten); +} + +/* + * Initialize TMU device + * + * @param blob FDT blob + * @return int value, 0 for success + */ +int tmu_init(const void *blob) +{ + gbl_info.tmu_state = TMU_STATUS_INIT; + if (get_tmu_fdt_values(&gbl_info, blob) < 0) + goto ret; + + tmu_setup_parameters(&gbl_info); + gbl_info.tmu_state = TMU_STATUS_NORMAL; +ret: + + return gbl_info.tmu_state; +} diff --git a/drivers/rtc/ds1374.c b/drivers/rtc/ds1374.c index d61a228..ec04ec8 100644 --- a/drivers/rtc/ds1374.c +++ b/drivers/rtc/ds1374.c @@ -84,15 +84,6 @@ #define RTC_SR_BIT_AF 0x01 /* Bit 0 = Alarm Flag */ #define RTC_SR_BIT_OSF 0x80 /* Bit 7 - Osc Stop Flag */ -typedef unsigned char boolean_t; - -#ifndef TRUE -#define TRUE ((boolean_t)(0==0)) -#endif -#ifndef FALSE -#define FALSE (!TRUE) -#endif - const char RtcTodAddr[] = { RTC_TOD_CNT_BYTE0_ADDR, RTC_TOD_CNT_BYTE1_ADDR, @@ -101,7 +92,7 @@ const char RtcTodAddr[] = { }; static uchar rtc_read (uchar reg); -static void rtc_write (uchar reg, uchar val, boolean_t set); +static void rtc_write(uchar reg, uchar val, bool set); static void rtc_write_raw (uchar reg, uchar val); /* @@ -185,7 +176,7 @@ int rtc_set (struct rtc_time *tmp){ } /* Start clock */ - rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, FALSE); + rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, false); return 0; } @@ -202,18 +193,18 @@ void rtc_reset (void){ struct rtc_time tmp; /* clear status flags */ - rtc_write (RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), FALSE); /* clearing OSF and AF */ + rtc_write(RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), false); /* clearing OSF and AF */ /* Initialise DS1374 oriented to MPC8349E-ADS */ rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_EN_OSC |RTC_CTL_BIT_WACE - |RTC_CTL_BIT_AIE), FALSE);/* start osc, disable WACE, clear AIE + |RTC_CTL_BIT_AIE), false);/* start osc, disable WACE, clear AIE - set to 0 */ rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_WD_ALM |RTC_CTL_BIT_WDSTR |RTC_CTL_BIT_RS1 |RTC_CTL_BIT_RS2 - |RTC_CTL_BIT_BBSQW), TRUE);/* disable WD/ALM, WDSTR set to INT-pin, + |RTC_CTL_BIT_BBSQW), true);/* disable WD/ALM, WDSTR set to INT-pin, set BBSQW and SQW to 32k - set to 1 */ tmp.tm_year = 1970; @@ -229,9 +220,9 @@ void rtc_reset (void){ tmp.tm_year, tmp.tm_mon, tmp.tm_mday, tmp.tm_hour, tmp.tm_min, tmp.tm_sec); - rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAC, TRUE); - rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR,0xDE, TRUE); - rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR,0xAD, TRUE); + rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAC, true); + rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR, 0xDE, true); + rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAD, true); } /* @@ -242,9 +233,9 @@ static uchar rtc_read (uchar reg) return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); } -static void rtc_write (uchar reg, uchar val, boolean_t set) +static void rtc_write(uchar reg, uchar val, bool set) { - if (set == TRUE) { + if (set == true) { val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg); i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); } else { diff --git a/drivers/rtc/mk48t59.c b/drivers/rtc/mk48t59.c index e285823..3af2623 100644 --- a/drivers/rtc/mk48t59.c +++ b/drivers/rtc/mk48t59.c @@ -49,20 +49,6 @@ static void rtc_write (short reg, uchar val) out8(RTC_PORT_DATA, val); } -#elif defined(CONFIG_PCIPPC2) - -#include "../board/pcippc2/pcippc2.h" - -static uchar rtc_read (short reg) -{ - return in8(RTC(reg)); -} - -static void rtc_write (short reg, uchar val) -{ - out8(RTC(reg),val); -} - #elif defined(CONFIG_EVAL5200) static uchar rtc_read (short reg) diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index de3f471..fbc4e97 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -35,7 +35,6 @@ COBJS-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o COBJS-$(CONFIG_MCFUART) += mcfuart.o COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o COBJS-$(CONFIG_SYS_NS16550) += ns16550.o -COBJS-$(CONFIG_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_S5P) += serial_s5p.o COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 87a0917..7f013ab 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -36,17 +36,31 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) { -#if (!defined(CONFIG_SYS_NS16550_BROKEN_TEMT)) +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX)) + /* + * On some OMAP3 devices when UART3 is configured for boot mode before + * SPL starts only THRE bit is set. We have to empty the transmitter + * before initialization starts. + */ + if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE)) + == UART_LSR_THRE) { + serial_out(UART_LCR_DLAB, &com_port->lcr); + serial_out(baud_divisor & 0xff, &com_port->dll); + serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); + serial_out(UART_LCRVAL, &com_port->lcr); + serial_out(0, &com_port->mdr1); + } +#endif + while (!(serial_in(&com_port->lsr) & UART_LSR_TEMT)) ; -#endif serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier); #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ - defined(CONFIG_AM33XX) + defined(CONFIG_AM33XX) || defined(CONFIG_TI814X) serial_out(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif - serial_out(UART_LCR_BKSE | UART_LCRVAL, (ulong)&com_port->lcr); + serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); serial_out(0, &com_port->dll); serial_out(0, &com_port->dlm); serial_out(UART_LCRVAL, &com_port->lcr); @@ -57,7 +71,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) serial_out((baud_divisor >> 8) & 0xff, &com_port->dlm); serial_out(UART_LCRVAL, &com_port->lcr); #if (defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)) || \ - defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) + defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \ + defined(CONFIG_TI814X) #if defined(CONFIG_APTIX) /* /13 mode so Aptix 6MHz can hit 115200 */ diff --git a/drivers/serial/s3c64xx.c b/drivers/serial/s3c64xx.c deleted file mode 100644 index b590992..0000000 --- a/drivers/serial/s3c64xx.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include <common.h> -#include <linux/compiler.h> -#include <serial.h> -#include <asm/arch/s3c6400.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SERIAL1 -#define UART_NR S3C64XX_UART0 - -#elif defined(CONFIG_SERIAL2) -#define UART_NR S3C64XX_UART1 - -#elif defined(CONFIG_SERIAL3) -#define UART_NR S3C64XX_UART2 - -#else -#error "Bad: you didn't configure serial ..." -#endif - -/* - * The coefficient, used to calculate the baudrate on S3C6400 UARTs is - * calculated as - * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT - * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1, - * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants: - */ -static const int udivslot[] = { - 0, - 0x0080, - 0x0808, - 0x0888, - 0x2222, - 0x4924, - 0x4a52, - 0x54aa, - 0x5555, - 0xd555, - 0xd5d5, - 0xddd5, - 0xdddd, - 0xdfdd, - 0xdfdf, - 0xffdf, -}; - -static void s3c64xx_serial_setbrg(void) -{ - s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR); - u32 pclk = get_PCLK(); - u32 baudrate = gd->baudrate; - int i; - - i = (pclk / baudrate) % 16; - - uart->UBRDIV = pclk / baudrate / 16 - 1; - uart->UDIVSLOT = udivslot[i]; - - for (i = 0; i < 100; i++) - barrier(); -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - */ -static int s3c64xx_serial_init(void) -{ - s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR); - - /* reset and enable FIFOs, set triggers to the maximum */ - uart->UFCON = 0xff; - uart->UMCON = 0; - /* 8N1 */ - uart->ULCON = 3; - /* No interrupts, no DMA, pure polling */ - uart->UCON = 5; - - serial_setbrg(); - - return 0; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int s3c64xx_serial_getc(void) -{ - s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR); - - /* wait for character to arrive */ - while (!(uart->UTRSTAT & 0x1)); - - return uart->URXH & 0xff; -} - -#ifdef CONFIG_MODEM_SUPPORT -static int be_quiet; -void disable_putc(void) -{ - be_quiet = 1; -} - -void enable_putc(void) -{ - be_quiet = 0; -} -#endif - - -/* - * Output a single byte to the serial port. - */ -static void s3c64xx_serial_putc(const char c) -{ - s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR); - -#ifdef CONFIG_MODEM_SUPPORT - if (be_quiet) - return; -#endif - - /* wait for room in the tx FIFO */ - while (!(uart->UTRSTAT & 0x2)); - - uart->UTXH = c; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -static int s3c64xx_serial_tstc(void) -{ - s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR); - - return uart->UTRSTAT & 0x1; -} - -static struct serial_device s3c64xx_serial_drv = { - .name = "s3c64xx_serial", - .start = s3c64xx_serial_init, - .stop = NULL, - .setbrg = s3c64xx_serial_setbrg, - .putc = s3c64xx_serial_putc, - .puts = default_serial_puts, - .getc = s3c64xx_serial_getc, - .tstc = s3c64xx_serial_tstc, -}; - -void s3c64xx_serial_initialize(void) -{ - serial_register(&s3c64xx_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &s3c64xx_serial_drv; -} diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 7922bf0..9f04643 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -165,7 +165,6 @@ serial_initfunc(atmel_serial_initialize); serial_initfunc(lpc32xx_serial_initialize); serial_initfunc(mcf_serial_initialize); serial_initfunc(oc_serial_initialize); -serial_initfunc(s3c64xx_serial_initialize); serial_initfunc(sandbox_serial_initialize); serial_initfunc(clps7111_serial_initialize); serial_initfunc(imx_serial_initialize); @@ -259,7 +258,6 @@ void serial_initialize(void) lpc32xx_serial_initialize(); mcf_serial_initialize(); oc_serial_initialize(); - s3c64xx_serial_initialize(); sandbox_serial_initialize(); clps7111_serial_initialize(); imx_serial_initialize(); diff --git a/drivers/serial/usbtty.c b/drivers/serial/usbtty.c index e47cb9a..8e08153 100644 --- a/drivers/serial/usbtty.c +++ b/drivers/serial/usbtty.c @@ -63,7 +63,7 @@ /* * Buffers to hold input and output data */ -#define USBTTY_BUFFER_SIZE 256 +#define USBTTY_BUFFER_SIZE 2048 static circbuf_t usbtty_input; static circbuf_t usbtty_output; @@ -971,8 +971,8 @@ static void usbtty_event_handler (struct usb_device_instance *device, /* * is_usbd_high_speed routine needs to be defined by * specific gadget driver - * It returns TRUE if device enumerates at High speed - * Retuns FALSE otherwise + * It returns true if device enumerates at High speed + * Retuns false otherwise */ for (i = 0; i < NUM_ENDPOINTS; i++) { if (((ep_descriptor_ptrs[i]->bmAttributes & diff --git a/drivers/sound/Makefile b/drivers/sound/Makefile index 8fdffb1..1987ca1 100644 --- a/drivers/sound/Makefile +++ b/drivers/sound/Makefile @@ -28,6 +28,7 @@ LIB := $(obj)libsound.o COBJS-$(CONFIG_SOUND) += sound.o COBJS-$(CONFIG_I2S) += samsung-i2s.o COBJS-$(CONFIG_SOUND_WM8994) += wm8994.o +COBJS-$(CONFIG_SOUND_MAX98095) += max98095.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/sound/max98095.c b/drivers/sound/max98095.c new file mode 100644 index 0000000..d69db58 --- /dev/null +++ b/drivers/sound/max98095.c @@ -0,0 +1,550 @@ +/* + * max98095.c -- MAX98095 ALSA SoC Audio driver + * + * Copyright 2011 Maxim Integrated Products + * + * Modified for uboot by R. Chandrasekar (rcsekar@samsung.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <asm/arch/clk.h> +#include <asm/arch/cpu.h> +#include <asm/arch/power.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <common.h> +#include <div64.h> +#include <fdtdec.h> +#include <i2c.h> +#include <sound.h> +#include "i2s.h" +#include "max98095.h" + +enum max98095_type { + MAX98095, +}; + +struct max98095_priv { + enum max98095_type devtype; + unsigned int sysclk; + unsigned int rate; + unsigned int fmt; +}; + +static struct sound_codec_info g_codec_info; +struct max98095_priv g_max98095_info; +unsigned int g_max98095_i2c_dev_addr; + +/* Index 0 is reserved. */ +int rate_table[] = {0, 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000, + 88200, 96000}; + +/* + * Writes value to a device register through i2c + * + * @param reg reg number to be write + * @param data data to be writen to the above registor + * + * @return int value 1 for change, 0 for no change or negative error code. + */ +static int max98095_i2c_write(unsigned int reg, unsigned char data) +{ + debug("%s: Write Addr : 0x%02X, Data : 0x%02X\n", + __func__, reg, data); + return i2c_write(g_max98095_i2c_dev_addr, reg, 1, &data, 1); +} + +/* + * Read a value from a device register through i2c + * + * @param reg reg number to be read + * @param data address of read data to be stored + * + * @return int value 0 for success, -1 in case of error. + */ +static unsigned int max98095_i2c_read(unsigned int reg, unsigned char *data) +{ + int ret; + + ret = i2c_read(g_max98095_i2c_dev_addr, reg, 1, data, 1); + if (ret != 0) { + debug("%s: Error while reading register %#04x\n", + __func__, reg); + return -1; + } + + return 0; +} + +/* + * update device register bits through i2c + * + * @param reg codec register + * @param mask register mask + * @param value new value + * + * @return int value 0 for success, non-zero error code. + */ +static int max98095_update_bits(unsigned int reg, unsigned char mask, + unsigned char value) +{ + int change, ret = 0; + unsigned char old, new; + + if (max98095_i2c_read(reg, &old) != 0) + return -1; + new = (old & ~mask) | (value & mask); + change = (old != new) ? 1 : 0; + if (change) + ret = max98095_i2c_write(reg, new); + if (ret < 0) + return ret; + + return change; +} + +/* + * codec mclk clock divider coefficients based on sampling rate + * + * @param rate sampling rate + * @param value address of indexvalue to be stored + * + * @return 0 for success or negative error code. + */ +static int rate_value(int rate, u8 *value) +{ + int i; + + for (i = 1; i < ARRAY_SIZE(rate_table); i++) { + if (rate_table[i] >= rate) { + *value = i; + return 0; + } + } + *value = 1; + + return -1; +} + +/* + * Sets hw params for max98095 + * + * @param max98095 max98095 information pointer + * @param rate Sampling rate + * @param bits_per_sample Bits per sample + * + * @return -1 for error and 0 Success. + */ +static int max98095_hw_params(struct max98095_priv *max98095, + unsigned int rate, unsigned int bits_per_sample) +{ + u8 regval; + int error; + + switch (bits_per_sample) { + case 16: + error = max98095_update_bits(M98095_034_DAI2_FORMAT, + M98095_DAI_WS, 0); + break; + case 24: + error = max98095_update_bits(M98095_034_DAI2_FORMAT, + M98095_DAI_WS, M98095_DAI_WS); + break; + default: + debug("%s: Illegal bits per sample %d.\n", + __func__, bits_per_sample); + return -1; + } + + if (rate_value(rate, ®val)) { + debug("%s: Failed to set sample rate to %d.\n", + __func__, rate); + return -1; + } + max98095->rate = rate; + + error |= max98095_update_bits(M98095_031_DAI2_CLKMODE, + M98095_CLKMODE_MASK, regval); + + /* Update sample rate mode */ + if (rate < 50000) + error |= max98095_update_bits(M98095_038_DAI2_FILTERS, + M98095_DAI_DHF, 0); + else + error |= max98095_update_bits(M98095_038_DAI2_FILTERS, + M98095_DAI_DHF, M98095_DAI_DHF); + + if (error < 0) { + debug("%s: Error setting hardware params.\n", __func__); + return -1; + } + + return 0; +} + +/* + * Configures Audio interface system clock for the given frequency + * + * @param max98095 max98095 information + * @param freq Sampling frequency in Hz + * + * @return -1 for error and 0 success. + */ +static int max98095_set_sysclk(struct max98095_priv *max98095, + unsigned int freq) +{ + int error = 0; + + /* Requested clock frequency is already setup */ + if (freq == max98095->sysclk) + return 0; + + /* Setup clocks for slave mode, and using the PLL + * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) + * 0x02 (when master clk is 20MHz to 40MHz).. + * 0x03 (when master clk is 40MHz to 60MHz).. + */ + if ((freq >= 10000000) && (freq < 20000000)) { + error = max98095_i2c_write(M98095_026_SYS_CLK, 0x10); + } else if ((freq >= 20000000) && (freq < 40000000)) { + error = max98095_i2c_write(M98095_026_SYS_CLK, 0x20); + } else if ((freq >= 40000000) && (freq < 60000000)) { + error = max98095_i2c_write(M98095_026_SYS_CLK, 0x30); + } else { + debug("%s: Invalid master clock frequency\n", __func__); + return -1; + } + + debug("%s: Clock at %uHz\n", __func__, freq); + + if (error < 0) + return -1; + + max98095->sysclk = freq; + return 0; +} + +/* + * Sets Max98095 I2S format + * + * @param max98095 max98095 information + * @param fmt i2S format - supports a subset of the options defined + * in i2s.h. + * + * @return -1 for error and 0 Success. + */ +static int max98095_set_fmt(struct max98095_priv *max98095, int fmt) +{ + u8 regval = 0; + int error = 0; + + if (fmt == max98095->fmt) + return 0; + + max98095->fmt = fmt; + + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { + case SND_SOC_DAIFMT_CBS_CFS: + /* Slave mode PLL */ + error |= max98095_i2c_write(M98095_032_DAI2_CLKCFG_HI, + 0x80); + error |= max98095_i2c_write(M98095_033_DAI2_CLKCFG_LO, + 0x00); + break; + case SND_SOC_DAIFMT_CBM_CFM: + /* Set to master mode */ + regval |= M98095_DAI_MAS; + break; + case SND_SOC_DAIFMT_CBS_CFM: + case SND_SOC_DAIFMT_CBM_CFS: + default: + debug("%s: Clock mode unsupported\n", __func__); + return -1; + } + + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { + case SND_SOC_DAIFMT_I2S: + regval |= M98095_DAI_DLY; + break; + case SND_SOC_DAIFMT_LEFT_J: + break; + default: + debug("%s: Unrecognized format.\n", __func__); + return -1; + } + + switch (fmt & SND_SOC_DAIFMT_INV_MASK) { + case SND_SOC_DAIFMT_NB_NF: + break; + case SND_SOC_DAIFMT_NB_IF: + regval |= M98095_DAI_WCI; + break; + case SND_SOC_DAIFMT_IB_NF: + regval |= M98095_DAI_BCI; + break; + case SND_SOC_DAIFMT_IB_IF: + regval |= M98095_DAI_BCI | M98095_DAI_WCI; + break; + default: + debug("%s: Unrecognized inversion settings.\n", __func__); + return -1; + } + + error |= max98095_update_bits(M98095_034_DAI2_FORMAT, + M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | + M98095_DAI_WCI, regval); + + error |= max98095_i2c_write(M98095_035_DAI2_CLOCK, + M98095_DAI_BSEL64); + + if (error < 0) { + debug("%s: Error setting i2s format.\n", __func__); + return -1; + } + + return 0; +} + +/* + * resets the audio codec + * + * @return -1 for error and 0 success. + */ +static int max98095_reset(void) +{ + int i, ret; + + /* + * Gracefully reset the DSP core and the codec hardware in a proper + * sequence. + */ + ret = max98095_i2c_write(M98095_00F_HOST_CFG, 0); + if (ret != 0) { + debug("%s: Failed to reset DSP: %d\n", __func__, ret); + return ret; + } + + ret = max98095_i2c_write(M98095_097_PWR_SYS, 0); + if (ret != 0) { + debug("%s: Failed to reset codec: %d\n", __func__, ret); + return ret; + } + + /* + * Reset to hardware default for registers, as there is not a soft + * reset hardware control register. + */ + for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) { + ret = max98095_i2c_write(i, 0); + if (ret < 0) { + debug("%s: Failed to reset: %d\n", __func__, ret); + return ret; + } + } + + return 0; +} + +/* + * Intialise max98095 codec device + * + * @param max98095 max98095 information + * + * @returns -1 for error and 0 Success. + */ +static int max98095_device_init(struct max98095_priv *max98095) +{ + unsigned char id; + int error = 0; + + /* reset the codec, the DSP core, and disable all interrupts */ + error = max98095_reset(); + if (error != 0) { + debug("Reset\n"); + return error; + } + + /* initialize private data */ + max98095->sysclk = -1U; + max98095->rate = -1U; + max98095->fmt = -1U; + + error = max98095_i2c_read(M98095_0FF_REV_ID, &id); + if (error < 0) { + debug("%s: Failure reading hardware revision: %d\n", + __func__, id); + goto err_access; + } + debug("%s: Hardware revision: %c\n", __func__, (id - 0x40) + 'A'); + + error |= max98095_i2c_write(M98095_097_PWR_SYS, M98095_PWRSV); + + /* + * initialize registers to hardware default configuring audio + * interface2 to DAC + */ + error |= max98095_i2c_write(M98095_048_MIX_DAC_LR, + M98095_DAI2M_TO_DACL|M98095_DAI2M_TO_DACR); + + error |= max98095_i2c_write(M98095_092_PWR_EN_OUT, + M98095_SPK_SPREADSPECTRUM); + error |= max98095_i2c_write(M98095_045_CFG_DSP, M98095_DSPNORMAL); + error |= max98095_i2c_write(M98095_04E_CFG_HP, M98095_HPNORMAL); + + error |= max98095_i2c_write(M98095_02C_DAI1_IOCFG, + M98095_S1NORMAL|M98095_SDATA); + + error |= max98095_i2c_write(M98095_036_DAI2_IOCFG, + M98095_S2NORMAL|M98095_SDATA); + + error |= max98095_i2c_write(M98095_040_DAI3_IOCFG, + M98095_S3NORMAL|M98095_SDATA); + + /* take the codec out of the shut down */ + error |= max98095_update_bits(M98095_097_PWR_SYS, M98095_SHDNRUN, + M98095_SHDNRUN); + /* route DACL and DACR output to HO and Spekers */ + error |= max98095_i2c_write(M98095_050_MIX_SPK_LEFT, 0x01); /* DACL */ + error |= max98095_i2c_write(M98095_051_MIX_SPK_RIGHT, 0x01);/* DACR */ + error |= max98095_i2c_write(M98095_04C_MIX_HP_LEFT, 0x01); /* DACL */ + error |= max98095_i2c_write(M98095_04D_MIX_HP_RIGHT, 0x01); /* DACR */ + + /* power Enable */ + error |= max98095_i2c_write(M98095_091_PWR_EN_OUT, 0xF3); + + /* set Volume */ + error |= max98095_i2c_write(M98095_064_LVL_HP_L, 15); + error |= max98095_i2c_write(M98095_065_LVL_HP_R, 15); + error |= max98095_i2c_write(M98095_067_LVL_SPK_L, 16); + error |= max98095_i2c_write(M98095_068_LVL_SPK_R, 16); + + /* Enable DAIs */ + error |= max98095_i2c_write(M98095_093_BIAS_CTRL, 0x30); + error |= max98095_i2c_write(M98095_096_PWR_DAC_CK, 0x07); + +err_access: + if (error < 0) + return -1; + + return 0; +} + +static int max98095_do_init(struct sound_codec_info *pcodec_info, + int sampling_rate, int mclk_freq, + int bits_per_sample) +{ + int ret = 0; + + /* Enable codec clock */ + set_xclkout(); + + /* shift the device address by 1 for 7 bit addressing */ + g_max98095_i2c_dev_addr = pcodec_info->i2c_dev_addr >> 1; + + if (pcodec_info->codec_type == CODEC_MAX_98095) + g_max98095_info.devtype = MAX98095; + else { + debug("%s: Codec id [%d] not defined\n", __func__, + pcodec_info->codec_type); + return -1; + } + + ret = max98095_device_init(&g_max98095_info); + if (ret < 0) { + debug("%s: max98095 codec chip init failed\n", __func__); + return ret; + } + + ret = max98095_set_sysclk(&g_max98095_info, mclk_freq); + if (ret < 0) { + debug("%s: max98095 codec set sys clock failed\n", __func__); + return ret; + } + + ret = max98095_hw_params(&g_max98095_info, sampling_rate, + bits_per_sample); + + if (ret == 0) { + ret = max98095_set_fmt(&g_max98095_info, + SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBS_CFS); + } + + return ret; +} + +static int get_max98095_codec_values(struct sound_codec_info *pcodec_info, + const void *blob) +{ + int error = 0; +#ifdef CONFIG_OF_CONTROL + enum fdt_compat_id compat; + int node; + int parent; + + /* Get the node from FDT for codec */ + node = fdtdec_next_compatible(blob, 0, COMPAT_MAXIM_98095_CODEC); + if (node <= 0) { + debug("EXYNOS_SOUND: No node for codec in device tree\n"); + debug("node = %d\n", node); + return -1; + } + + parent = fdt_parent_offset(blob, node); + if (parent < 0) { + debug("%s: Cannot find node parent\n", __func__); + return -1; + } + + compat = fdtdec_lookup(blob, parent); + switch (compat) { + case COMPAT_SAMSUNG_S3C2440_I2C: + pcodec_info->i2c_bus = i2c_get_bus_num_fdt(parent); + error |= pcodec_info->i2c_bus; + debug("i2c bus = %d\n", pcodec_info->i2c_bus); + pcodec_info->i2c_dev_addr = fdtdec_get_int(blob, node, + "reg", 0); + error |= pcodec_info->i2c_dev_addr; + debug("i2c dev addr = %x\n", pcodec_info->i2c_dev_addr); + break; + default: + debug("%s: Unknown compat id %d\n", __func__, compat); + return -1; + } +#else + pcodec_info->i2c_bus = AUDIO_I2C_BUS; + pcodec_info->i2c_dev_addr = AUDIO_I2C_REG; + debug("i2c dev addr = %d\n", pcodec_info->i2c_dev_addr); +#endif + pcodec_info->codec_type = CODEC_MAX_98095; + if (error == -1) { + debug("fail to get max98095 codec node properties\n"); + return -1; + } + + return 0; +} + +/* max98095 Device Initialisation */ +int max98095_init(const void *blob, int sampling_rate, int mclk_freq, + int bits_per_sample) +{ + int ret; + int old_bus = i2c_get_bus_num(); + struct sound_codec_info *pcodec_info = &g_codec_info; + + if (get_max98095_codec_values(pcodec_info, blob) < 0) { + debug("FDT Codec values failed\n"); + return -1; + } + + i2c_set_bus_num(pcodec_info->i2c_bus); + ret = max98095_do_init(pcodec_info, sampling_rate, mclk_freq, + bits_per_sample); + i2c_set_bus_num(old_bus); + + return ret; +} diff --git a/drivers/sound/max98095.h b/drivers/sound/max98095.h new file mode 100644 index 0000000..ae5eb14 --- /dev/null +++ b/drivers/sound/max98095.h @@ -0,0 +1,311 @@ +/* + * max98095.h -- MAX98095 ALSA SoC Audio driver + * + * Copyright 2011 Maxim Integrated Products + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _MAX98095_H +#define _MAX98095_H + +/* + * MAX98095 Registers Definition + */ + +#define M98095_000_HOST_DATA 0x00 +#define M98095_001_HOST_INT_STS 0x01 +#define M98095_002_HOST_RSP_STS 0x02 +#define M98095_003_HOST_CMD_STS 0x03 +#define M98095_004_CODEC_STS 0x04 +#define M98095_005_DAI1_ALC_STS 0x05 +#define M98095_006_DAI2_ALC_STS 0x06 +#define M98095_007_JACK_AUTO_STS 0x07 +#define M98095_008_JACK_MANUAL_STS 0x08 +#define M98095_009_JACK_VBAT_STS 0x09 +#define M98095_00A_ACC_ADC_STS 0x0A +#define M98095_00B_MIC_NG_AGC_STS 0x0B +#define M98095_00C_SPK_L_VOLT_STS 0x0C +#define M98095_00D_SPK_R_VOLT_STS 0x0D +#define M98095_00E_TEMP_SENSOR_STS 0x0E +#define M98095_00F_HOST_CFG 0x0F +#define M98095_010_HOST_INT_CFG 0x10 +#define M98095_011_HOST_INT_EN 0x11 +#define M98095_012_CODEC_INT_EN 0x12 +#define M98095_013_JACK_INT_EN 0x13 +#define M98095_014_JACK_INT_EN 0x14 +#define M98095_015_DEC 0x15 +#define M98095_016_RESERVED 0x16 +#define M98095_017_RESERVED 0x17 +#define M98095_018_KEYCODE3 0x18 +#define M98095_019_KEYCODE2 0x19 +#define M98095_01A_KEYCODE1 0x1A +#define M98095_01B_KEYCODE0 0x1B +#define M98095_01C_OEMCODE1 0x1C +#define M98095_01D_OEMCODE0 0x1D +#define M98095_01E_XCFG1 0x1E +#define M98095_01F_XCFG2 0x1F +#define M98095_020_XCFG3 0x20 +#define M98095_021_XCFG4 0x21 +#define M98095_022_XCFG5 0x22 +#define M98095_023_XCFG6 0x23 +#define M98095_024_XGPIO 0x24 +#define M98095_025_XCLKCFG 0x25 +#define M98095_026_SYS_CLK 0x26 +#define M98095_027_DAI1_CLKMODE 0x27 +#define M98095_028_DAI1_CLKCFG_HI 0x28 +#define M98095_029_DAI1_CLKCFG_LO 0x29 +#define M98095_02A_DAI1_FORMAT 0x2A +#define M98095_02B_DAI1_CLOCK 0x2B +#define M98095_02C_DAI1_IOCFG 0x2C +#define M98095_02D_DAI1_TDM 0x2D +#define M98095_02E_DAI1_FILTERS 0x2E +#define M98095_02F_DAI1_LVL1 0x2F +#define M98095_030_DAI1_LVL2 0x30 +#define M98095_031_DAI2_CLKMODE 0x31 +#define M98095_032_DAI2_CLKCFG_HI 0x32 +#define M98095_033_DAI2_CLKCFG_LO 0x33 +#define M98095_034_DAI2_FORMAT 0x34 +#define M98095_035_DAI2_CLOCK 0x35 +#define M98095_036_DAI2_IOCFG 0x36 +#define M98095_037_DAI2_TDM 0x37 +#define M98095_038_DAI2_FILTERS 0x38 +#define M98095_039_DAI2_LVL1 0x39 +#define M98095_03A_DAI2_LVL2 0x3A +#define M98095_03B_DAI3_CLKMODE 0x3B +#define M98095_03C_DAI3_CLKCFG_HI 0x3C +#define M98095_03D_DAI3_CLKCFG_LO 0x3D +#define M98095_03E_DAI3_FORMAT 0x3E +#define M98095_03F_DAI3_CLOCK 0x3F +#define M98095_040_DAI3_IOCFG 0x40 +#define M98095_041_DAI3_TDM 0x41 +#define M98095_042_DAI3_FILTERS 0x42 +#define M98095_043_DAI3_LVL1 0x43 +#define M98095_044_DAI3_LVL2 0x44 +#define M98095_045_CFG_DSP 0x45 +#define M98095_046_DAC_CTRL1 0x46 +#define M98095_047_DAC_CTRL2 0x47 +#define M98095_048_MIX_DAC_LR 0x48 +#define M98095_049_MIX_DAC_M 0x49 +#define M98095_04A_MIX_ADC_LEFT 0x4A +#define M98095_04B_MIX_ADC_RIGHT 0x4B +#define M98095_04C_MIX_HP_LEFT 0x4C +#define M98095_04D_MIX_HP_RIGHT 0x4D +#define M98095_04E_CFG_HP 0x4E +#define M98095_04F_MIX_RCV 0x4F +#define M98095_050_MIX_SPK_LEFT 0x50 +#define M98095_051_MIX_SPK_RIGHT 0x51 +#define M98095_052_MIX_SPK_CFG 0x52 +#define M98095_053_MIX_LINEOUT1 0x53 +#define M98095_054_MIX_LINEOUT2 0x54 +#define M98095_055_MIX_LINEOUT_CFG 0x55 +#define M98095_056_LVL_SIDETONE_DAI12 0x56 +#define M98095_057_LVL_SIDETONE_DAI3 0x57 +#define M98095_058_LVL_DAI1_PLAY 0x58 +#define M98095_059_LVL_DAI1_EQ 0x59 +#define M98095_05A_LVL_DAI2_PLAY 0x5A +#define M98095_05B_LVL_DAI2_EQ 0x5B +#define M98095_05C_LVL_DAI3_PLAY 0x5C +#define M98095_05D_LVL_ADC_L 0x5D +#define M98095_05E_LVL_ADC_R 0x5E +#define M98095_05F_LVL_MIC1 0x5F +#define M98095_060_LVL_MIC2 0x60 +#define M98095_061_LVL_LINEIN 0x61 +#define M98095_062_LVL_LINEOUT1 0x62 +#define M98095_063_LVL_LINEOUT2 0x63 +#define M98095_064_LVL_HP_L 0x64 +#define M98095_065_LVL_HP_R 0x65 +#define M98095_066_LVL_RCV 0x66 +#define M98095_067_LVL_SPK_L 0x67 +#define M98095_068_LVL_SPK_R 0x68 +#define M98095_069_MICAGC_CFG 0x69 +#define M98095_06A_MICAGC_THRESH 0x6A +#define M98095_06B_SPK_NOISEGATE 0x6B +#define M98095_06C_DAI1_ALC1_TIME 0x6C +#define M98095_06D_DAI1_ALC1_COMP 0x6D +#define M98095_06E_DAI1_ALC1_EXPN 0x6E +#define M98095_06F_DAI1_ALC1_GAIN 0x6F +#define M98095_070_DAI1_ALC2_TIME 0x70 +#define M98095_071_DAI1_ALC2_COMP 0x71 +#define M98095_072_DAI1_ALC2_EXPN 0x72 +#define M98095_073_DAI1_ALC2_GAIN 0x73 +#define M98095_074_DAI1_ALC3_TIME 0x74 +#define M98095_075_DAI1_ALC3_COMP 0x75 +#define M98095_076_DAI1_ALC3_EXPN 0x76 +#define M98095_077_DAI1_ALC3_GAIN 0x77 +#define M98095_078_DAI2_ALC1_TIME 0x78 +#define M98095_079_DAI2_ALC1_COMP 0x79 +#define M98095_07A_DAI2_ALC1_EXPN 0x7A +#define M98095_07B_DAI2_ALC1_GAIN 0x7B +#define M98095_07C_DAI2_ALC2_TIME 0x7C +#define M98095_07D_DAI2_ALC2_COMP 0x7D +#define M98095_07E_DAI2_ALC2_EXPN 0x7E +#define M98095_07F_DAI2_ALC2_GAIN 0x7F +#define M98095_080_DAI2_ALC3_TIME 0x80 +#define M98095_081_DAI2_ALC3_COMP 0x81 +#define M98095_082_DAI2_ALC3_EXPN 0x82 +#define M98095_083_DAI2_ALC3_GAIN 0x83 +#define M98095_084_HP_NOISE_GATE 0x84 +#define M98095_085_AUX_ADC 0x85 +#define M98095_086_CFG_LINE 0x86 +#define M98095_087_CFG_MIC 0x87 +#define M98095_088_CFG_LEVEL 0x88 +#define M98095_089_JACK_DET_AUTO 0x89 +#define M98095_08A_JACK_DET_MANUAL 0x8A +#define M98095_08B_JACK_KEYSCAN_DBC 0x8B +#define M98095_08C_JACK_KEYSCAN_DLY 0x8C +#define M98095_08D_JACK_KEY_THRESH 0x8D +#define M98095_08E_JACK_DC_SLEW 0x8E +#define M98095_08F_JACK_TEST_CFG 0x8F +#define M98095_090_PWR_EN_IN 0x90 +#define M98095_091_PWR_EN_OUT 0x91 +#define M98095_092_PWR_EN_OUT 0x92 +#define M98095_093_BIAS_CTRL 0x93 +#define M98095_094_PWR_DAC_21 0x94 +#define M98095_095_PWR_DAC_03 0x95 +#define M98095_096_PWR_DAC_CK 0x96 +#define M98095_097_PWR_SYS 0x97 + +#define M98095_0FF_REV_ID 0xFF + +#define M98095_REG_CNT (0xFF+1) +#define M98095_REG_MAX_CACHED 0X97 + +/* MAX98095 Registers Bit Fields */ + +/* M98095_00F_HOST_CFG */ +#define M98095_SEG (1<<0) +#define M98095_XTEN (1<<1) +#define M98095_MDLLEN (1<<2) + +/* M98095_027_DAI1_CLKMODE, M98095_031_DAI2_CLKMODE, M98095_03B_DAI3_CLKMODE */ +#define M98095_CLKMODE_MASK 0xFF + +/* M98095_02A_DAI1_FORMAT, M98095_034_DAI2_FORMAT, M98095_03E_DAI3_FORMAT */ +#define M98095_DAI_MAS (1<<7) +#define M98095_DAI_WCI (1<<6) +#define M98095_DAI_BCI (1<<5) +#define M98095_DAI_DLY (1<<4) +#define M98095_DAI_TDM (1<<2) +#define M98095_DAI_FSW (1<<1) +#define M98095_DAI_WS (1<<0) + +/* M98095_02B_DAI1_CLOCK, M98095_035_DAI2_CLOCK, M98095_03F_DAI3_CLOCK */ +#define M98095_DAI_BSEL64 (1<<0) +#define M98095_DAI_DOSR_DIV2 (0<<5) +#define M98095_DAI_DOSR_DIV4 (1<<5) + +/* M98095_02C_DAI1_IOCFG, M98095_036_DAI2_IOCFG, M98095_040_DAI3_IOCFG */ +#define M98095_S1NORMAL (1<<6) +#define M98095_S2NORMAL (2<<6) +#define M98095_S3NORMAL (3<<6) +#define M98095_SDATA (3<<0) + +/* M98095_02E_DAI1_FILTERS, M98095_038_DAI2_FILTERS, M98095_042_DAI3_FILTERS */ +#define M98095_DAI_DHF (1<<3) + +/* M98095_045_DSP_CFG */ +#define M98095_DSPNORMAL (5<<4) + +/* M98095_048_MIX_DAC_LR */ +#define M98095_DAI1L_TO_DACR (1<<7) +#define M98095_DAI1R_TO_DACR (1<<6) +#define M98095_DAI2M_TO_DACR (1<<5) +#define M98095_DAI1L_TO_DACL (1<<3) +#define M98095_DAI1R_TO_DACL (1<<2) +#define M98095_DAI2M_TO_DACL (1<<1) +#define M98095_DAI3M_TO_DACL (1<<0) + +/* M98095_049_MIX_DAC_M */ +#define M98095_DAI1L_TO_DACM (1<<3) +#define M98095_DAI1R_TO_DACM (1<<2) +#define M98095_DAI2M_TO_DACM (1<<1) +#define M98095_DAI3M_TO_DACM (1<<0) + +/* M98095_04E_MIX_HP_CFG */ +#define M98095_HPNORMAL (3<<4) + +/* M98095_05F_LVL_MIC1, M98095_060_LVL_MIC2 */ +#define M98095_MICPRE_MASK (3<<5) +#define M98095_MICPRE_SHIFT 5 + +/* M98095_064_LVL_HP_L, M98095_065_LVL_HP_R */ +#define M98095_HP_MUTE (1<<7) + +/* M98095_066_LVL_RCV */ +#define M98095_REC_MUTE (1<<7) + +/* M98095_067_LVL_SPK_L, M98095_068_LVL_SPK_R */ +#define M98095_SP_MUTE (1<<7) + +/* M98095_087_CFG_MIC */ +#define M98095_MICSEL_MASK (3<<0) +#define M98095_DIGMIC_L (1<<2) +#define M98095_DIGMIC_R (1<<3) +#define M98095_DIGMIC2L (1<<4) +#define M98095_DIGMIC2R (1<<5) + +/* M98095_088_CFG_LEVEL */ +#define M98095_VSEN (1<<6) +#define M98095_ZDEN (1<<5) +#define M98095_BQ2EN (1<<3) +#define M98095_BQ1EN (1<<2) +#define M98095_EQ2EN (1<<1) +#define M98095_EQ1EN (1<<0) + +/* M98095_090_PWR_EN_IN */ +#define M98095_INEN (1<<7) +#define M98095_MB2EN (1<<3) +#define M98095_MB1EN (1<<2) +#define M98095_MBEN (3<<2) +#define M98095_ADREN (1<<1) +#define M98095_ADLEN (1<<0) + +/* M98095_091_PWR_EN_OUT */ +#define M98095_HPLEN (1<<7) +#define M98095_HPREN (1<<6) +#define M98095_SPLEN (1<<5) +#define M98095_SPREN (1<<4) +#define M98095_RECEN (1<<3) +#define M98095_DALEN (1<<1) +#define M98095_DAREN (1<<0) + +/* M98095_092_PWR_EN_OUT */ +#define M98095_SPK_FIXEDSPECTRUM (0<<4) +#define M98095_SPK_SPREADSPECTRUM (1<<4) + +/* M98095_097_PWR_SYS */ +#define M98095_SHDNRUN (1<<7) +#define M98095_PERFMODE (1<<3) +#define M98095_HPPLYBACK (1<<2) +#define M98095_PWRSV8K (1<<1) +#define M98095_PWRSV (1<<0) + +#define M98095_COEFS_PER_BAND 5 + +/* Equalizer filter coefficients */ +#define M98095_110_DAI1_EQ_BASE 0x10 +#define M98095_142_DAI2_EQ_BASE 0x42 + +/* Biquad filter coefficients */ +#define M98095_174_DAI1_BQ_BASE 0x74 +#define M98095_17E_DAI2_BQ_BASE 0x7E + +/* function prototype */ + +/* + * intialise max98095 sound codec device for the given configuration + * + * @param blob FDT node for codec values + * @param sampling_rate Sampling rate (Hz) + * @param mclk_freq MCLK Frequency (Hz) + * @param bits_per_sample bits per Sample (must be 16 or 24) + * + * @returns -1 for error and 0 Success. + */ +int max98095_init(const void *blob, int sampling_rate, int mclk_freq, + int bits_per_sample); + +#endif diff --git a/drivers/sound/sound.c b/drivers/sound/sound.c index fa8432d..a4bf4ad 100644 --- a/drivers/sound/sound.c +++ b/drivers/sound/sound.c @@ -31,6 +31,7 @@ #include <sound.h> #include <asm/arch/sound.h> #include "wm8994.h" +#include "max98095.h" /* defines */ #define SOUND_400_HZ 400 @@ -149,11 +150,15 @@ static int codec_init(const void *blob, struct i2stx_info *pi2s_tx) pi2s_tx->samplingrate, (pi2s_tx->samplingrate * (pi2s_tx->rfs)), pi2s_tx->bitspersample, pi2s_tx->channels); + } else if (!strcmp(codectype, "max98095")) { + ret = max98095_init(blob, pi2s_tx->samplingrate, + (pi2s_tx->samplingrate * (pi2s_tx->rfs)), + pi2s_tx->bitspersample); } else { - debug("%s: Unknown code type %s\n", __func__, - codectype); + debug("%s: Unknown codec type %s\n", __func__, codectype); return -1; } + if (ret) { debug("%s: Codec init failed\n", __func__); return -1; diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index b8264df..d08609e 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -25,6 +25,9 @@ include $(TOPDIR)/config.mk LIB := $(obj)libspi.o +# There are many options which enable SPI, so make this library available +COBJS-y += spi.o + COBJS-$(CONFIG_ALTERA_SPI) += altera_spi.o COBJS-$(CONFIG_ANDES_SPI) += andes_spi.o COBJS-$(CONFIG_ARMADA100_SPI) += armada100_spi.o @@ -36,6 +39,7 @@ COBJS-$(CONFIG_CF_SPI) += cf_spi.o COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o +COBJS-$(CONFIG_ICH_SPI) += ich.o COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o @@ -46,8 +50,10 @@ COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o -COBJS-$(CONFIG_TEGRA_SPI) += tegra_spi.o -COBJS-$(CONFIG_TEGRA_SLINK) += tegra_slink.o +COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o +COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o +COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o +COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o COBJS := $(COBJS-y) diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index 138d6f4..b53607a 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -83,12 +83,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!spi_cs_is_valid(bus, cs)) return NULL; - altspi = malloc(sizeof(*altspi)); + altspi = spi_alloc_slave(struct altera_spi_slave, bus, cs); if (!altspi) return NULL; - altspi->slave.bus = bus; - altspi->slave.cs = cs; altspi->base = altera_spi_base_list[bus]; debug("%s: bus:%i cs:%i base:%lx\n", __func__, bus, cs, altspi->base); diff --git a/drivers/spi/andes_spi.c b/drivers/spi/andes_spi.c index fdde139..c56377b 100644 --- a/drivers/spi/andes_spi.c +++ b/drivers/spi/andes_spi.c @@ -53,12 +53,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!spi_cs_is_valid(bus, cs)) return NULL; - ds = malloc(sizeof(*ds)); + ds = spi_alloc_slave(struct andes_spi_slave, bus, cs); if (!ds) return NULL; - ds->slave.bus = bus; - ds->slave.cs = cs; ds->regs = (struct andes_spi_regs *)CONFIG_SYS_SPI_BASE; /* diff --git a/drivers/spi/armada100_spi.c b/drivers/spi/armada100_spi.c index 7384c9c..afdbe05 100644 --- a/drivers/spi/armada100_spi.c +++ b/drivers/spi/armada100_spi.c @@ -120,12 +120,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, { struct armd_spi_slave *pss; - pss = malloc(sizeof(*pss)); + pss = spi_alloc_slave(struct armd_spi_slave, bus, cs); if (!pss) return NULL; - pss->slave.bus = bus; - pss->slave.cs = cs; pss->spi_reg = (struct ssp_reg *)SSP_REG_BASE(CONFIG_SYS_SSP_PORT); pss->cr0 = SSCR0_MOTO | SSCR0_DATASIZE(DEFAULT_WORD_LEN) | SSCR0_SSE; diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c index ce7d460..f4b1bad 100644 --- a/drivers/spi/atmel_spi.c +++ b/drivers/spi/atmel_spi.c @@ -84,12 +84,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (mode & SPI_CPOL) csrx |= ATMEL_SPI_CSRx_CPOL; - as = malloc(sizeof(struct atmel_spi_slave)); + as = spi_alloc_slave(struct atmel_spi_slave, bus, cs); if (!as) return NULL; - as->slave.bus = bus; - as->slave.cs = cs; as->regs = regs; as->mr = ATMEL_SPI_MR_MSTR | ATMEL_SPI_MR_MODFDIS #if defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9M10G45) diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c index e080bec..ab2e8b9 100644 --- a/drivers/spi/bfin_spi.c +++ b/drivers/spi/bfin_spi.c @@ -182,12 +182,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, default: return NULL; } - bss = malloc(sizeof(*bss)); + bss = spi_alloc_slave(struct bfin_spi_slave, bus, cs); if (!bss) return NULL; - bss->slave.bus = bus; - bss->slave.cs = cs; bss->mmr_base = (void *)mmr_base; bss->ctl = SPE | MSTR | TDBR_CORE; if (mode & SPI_CPHA) bss->ctl |= CPHA; diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c index fde3447..c25c4a9 100644 --- a/drivers/spi/bfin_spi6xx.c +++ b/drivers/spi/bfin_spi6xx.c @@ -178,12 +178,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; } - bss = malloc(sizeof(*bss)); + bss = spi_alloc_slave(struct bfin_spi_slave, bus, cs); if (!bss) return NULL; - bss->slave.bus = bus; - bss->slave.cs = cs; bss->regs = (struct bfin_spi_regs *)reg_base; bss->control = SPI_CTL_EN | SPI_CTL_MSTR; if (mode & SPI_CPHA) diff --git a/drivers/spi/cf_qspi.c b/drivers/spi/cf_qspi.c index 72dd1a5..a37ac4e 100644 --- a/drivers/spi/cf_qspi.c +++ b/drivers/spi/cf_qspi.c @@ -120,13 +120,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!spi_cs_is_valid(bus, cs)) return NULL; - dev = malloc(sizeof(struct cf_qspi_slave)); + dev = spi_alloc_slave(struct cf_qspi_slave, bus, cs); if (!dev) return NULL; /* Initialize to known value */ - dev->slave.bus = bus; - dev->slave.cs = cs; dev->regs = (qspi_t *)MMAP_QSPI; dev->qmr = 0; dev->qwr = 0; diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index a883da9..afe7917 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -330,12 +330,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!spi_cs_is_valid(bus, cs)) return NULL; - cfslave = malloc(sizeof(struct cf_spi_slave)); + cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs); if (!cfslave) return NULL; - cfslave->slave.bus = bus; - cfslave->slave.cs = cs; cfslave->baudrate = max_hz; /* specific setup */ diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 13aca52..74792af 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -44,12 +44,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!spi_cs_is_valid(bus, cs)) return NULL; - ds = malloc(sizeof(*ds)); + ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs); if (!ds) return NULL; - ds->slave.bus = bus; - ds->slave.cs = cs; ds->regs = (struct davinci_spi_regs *)CONFIG_SYS_SPI_BASE; ds->freq = max_hz; diff --git a/drivers/spi/exynos_spi.c b/drivers/spi/exynos_spi.c index be60ada..607e1cd 100644 --- a/drivers/spi/exynos_spi.c +++ b/drivers/spi/exynos_spi.c @@ -89,15 +89,13 @@ struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs, return NULL; } - spi_slave = malloc(sizeof(*spi_slave)); + spi_slave = spi_alloc_slave(struct exynos_spi_slave, busnum, cs); if (!spi_slave) { debug("%s: Could not allocate spi_slave\n", __func__); return NULL; } bus = &spi_bus[busnum]; - spi_slave->slave.bus = busnum; - spi_slave->slave.cs = cs; spi_slave->regs = bus->regs; spi_slave->mode = mode; spi_slave->periph_id = bus->periph_id; @@ -360,6 +358,7 @@ static inline struct exynos_spi *get_spi_base(int dev_index) * @param bus SPI bus structure to fill with information * @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing */ +#ifdef CONFIG_OF_CONTROL static int spi_get_config(const void *blob, int node, struct spi_bus *bus) { bus->node = node; @@ -415,6 +414,7 @@ static int process_nodes(const void *blob, int node_list[], int count) return 0; } +#endif /* Sadly there is no error return from this function */ void spi_init(void) diff --git a/drivers/spi/fdt_spi.c b/drivers/spi/fdt_spi.c new file mode 100644 index 0000000..58f139a --- /dev/null +++ b/drivers/spi/fdt_spi.c @@ -0,0 +1,186 @@ +/* + * Common fdt based SPI driver front end + * + * Copyright (c) 2013 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch-tegra20/tegra20_sflash.h> +#include <asm/arch-tegra20/tegra20_slink.h> +#include <asm/arch-tegra114/tegra114_spi.h> +#include <spi.h> +#include <fdtdec.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct fdt_spi_driver { + int compat; + int max_ctrls; + int (*init)(int *node_list, int count); + int (*claim_bus)(struct spi_slave *slave); + int (*release_bus)(struct spi_slave *slave); + int (*cs_is_valid)(unsigned int bus, unsigned int cs); + struct spi_slave *(*setup_slave)(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode); + void (*free_slave)(struct spi_slave *slave); + void (*cs_activate)(struct spi_slave *slave); + void (*cs_deactivate)(struct spi_slave *slave); + int (*xfer)(struct spi_slave *slave, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags); +}; + +static struct fdt_spi_driver fdt_spi_drivers[] = { +#ifdef CONFIG_TEGRA20_SFLASH + { + .compat = COMPAT_NVIDIA_TEGRA20_SFLASH, + .max_ctrls = 1, + .init = tegra20_spi_init, + .claim_bus = tegra20_spi_claim_bus, + .cs_is_valid = tegra20_spi_cs_is_valid, + .setup_slave = tegra20_spi_setup_slave, + .free_slave = tegra20_spi_free_slave, + .cs_activate = tegra20_spi_cs_activate, + .cs_deactivate = tegra20_spi_cs_deactivate, + .xfer = tegra20_spi_xfer, + }, +#endif +#ifdef CONFIG_TEGRA20_SLINK + { + .compat = COMPAT_NVIDIA_TEGRA20_SLINK, + .max_ctrls = CONFIG_TEGRA_SLINK_CTRLS, + .init = tegra30_spi_init, + .claim_bus = tegra30_spi_claim_bus, + .cs_is_valid = tegra30_spi_cs_is_valid, + .setup_slave = tegra30_spi_setup_slave, + .free_slave = tegra30_spi_free_slave, + .cs_activate = tegra30_spi_cs_activate, + .cs_deactivate = tegra30_spi_cs_deactivate, + .xfer = tegra30_spi_xfer, + }, +#endif +#ifdef CONFIG_TEGRA114_SPI + { + .compat = COMPAT_NVIDIA_TEGRA114_SPI, + .max_ctrls = CONFIG_TEGRA114_SPI_CTRLS, + .init = tegra114_spi_init, + .claim_bus = tegra114_spi_claim_bus, + .cs_is_valid = tegra114_spi_cs_is_valid, + .setup_slave = tegra114_spi_setup_slave, + .free_slave = tegra114_spi_free_slave, + .cs_activate = tegra114_spi_cs_activate, + .cs_deactivate = tegra114_spi_cs_deactivate, + .xfer = tegra114_spi_xfer, + }, +#endif +}; + +static struct fdt_spi_driver *driver; + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + if (!driver) + return 0; + else if (!driver->cs_is_valid) + return 1; + else + return driver->cs_is_valid(bus, cs); +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + if (!driver || !driver->setup_slave) + return NULL; + + return driver->setup_slave(bus, cs, max_hz, mode); +} + +void spi_free_slave(struct spi_slave *slave) +{ + if (driver && driver->free_slave) + return driver->free_slave(slave); +} + +static int spi_init_driver(struct fdt_spi_driver *driver) +{ + int count; + int node_list[driver->max_ctrls]; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi", + driver->compat, + node_list, + driver->max_ctrls); + return driver->init(node_list, count); +} + +void spi_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(fdt_spi_drivers); i++) { + driver = &fdt_spi_drivers[i]; + if (!spi_init_driver(driver)) + break; + } + if (i == ARRAY_SIZE(fdt_spi_drivers)) + driver = NULL; +} + +int spi_claim_bus(struct spi_slave *slave) +{ + if (!driver) + return 1; + if (!driver->claim_bus) + return 0; + + return driver->claim_bus(slave); +} + +void spi_release_bus(struct spi_slave *slave) +{ + if (driver && driver->release_bus) + driver->release_bus(slave); +} + +void spi_cs_activate(struct spi_slave *slave) +{ + if (driver && driver->cs_activate) + driver->cs_activate(slave); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + if (driver && driver->cs_deactivate) + driver->cs_deactivate(slave); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags) +{ + if (!driver || !driver->xfer) + return -1; + + return driver->xfer(slave, bitlen, data_out, data_in, flags); +} diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index eb99e90..28609ee 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -79,12 +79,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!spi_cs_is_valid(bus, cs)) return NULL; - fsl = malloc(sizeof(struct fsl_spi_slave)); + fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); if (!fsl) return NULL; - fsl->slave.bus = bus; - fsl->slave.cs = cs; fsl->mode = mode; fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c new file mode 100644 index 0000000..468d356 --- /dev/null +++ b/drivers/spi/ich.c @@ -0,0 +1,754 @@ +/* + * Copyright (c) 2011-12 The Chromium OS Authors. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This file is derived from the flashrom project. + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <pci.h> +#include <pci_ids.h> +#include <asm/io.h> + +#include "ich.h" + +#define SPI_OPCODE_WREN 0x06 +#define SPI_OPCODE_FAST_READ 0x0b + +struct ich_ctlr { + pci_dev_t dev; /* PCI device number */ + int ich_version; /* Controller version, 7 or 9 */ + int ichspi_lock; + int locked; + uint8_t *opmenu; + int menubytes; + void *base; /* Base of register set */ + uint16_t *preop; + uint16_t *optype; + uint32_t *addr; + uint8_t *data; + unsigned databytes; + uint8_t *status; + uint16_t *control; + uint32_t *bbar; + uint32_t *pr; /* only for ich9 */ + uint8_t *speed; /* pointer to speed control */ + ulong max_speed; /* Maximum bus speed in MHz */ +}; + +struct ich_ctlr ctlr; + +static inline struct ich_spi_slave *to_ich_spi(struct spi_slave *slave) +{ + return container_of(slave, struct ich_spi_slave, slave); +} + +static unsigned int ich_reg(const void *addr) +{ + return (unsigned)(addr - ctlr.base) & 0xffff; +} + +static u8 ich_readb(const void *addr) +{ + u8 value = readb(addr); + + debug("read %2.2x from %4.4x\n", value, ich_reg(addr)); + + return value; +} + +static u16 ich_readw(const void *addr) +{ + u16 value = readw(addr); + + debug("read %4.4x from %4.4x\n", value, ich_reg(addr)); + + return value; +} + +static u32 ich_readl(const void *addr) +{ + u32 value = readl(addr); + + debug("read %8.8x from %4.4x\n", value, ich_reg(addr)); + + return value; +} + +static void ich_writeb(u8 value, void *addr) +{ + writeb(value, addr); + debug("wrote %2.2x to %4.4x\n", value, ich_reg(addr)); +} + +static void ich_writew(u16 value, void *addr) +{ + writew(value, addr); + debug("wrote %4.4x to %4.4x\n", value, ich_reg(addr)); +} + +static void ich_writel(u32 value, void *addr) +{ + writel(value, addr); + debug("wrote %8.8x to %4.4x\n", value, ich_reg(addr)); +} + +static void write_reg(const void *value, void *dest, uint32_t size) +{ + memcpy_toio(dest, value, size); +} + +static void read_reg(const void *src, void *value, uint32_t size) +{ + memcpy_fromio(value, src, size); +} + +static void ich_set_bbar(struct ich_ctlr *ctlr, uint32_t minaddr) +{ + const uint32_t bbar_mask = 0x00ffff00; + uint32_t ichspi_bbar; + + minaddr &= bbar_mask; + ichspi_bbar = ich_readl(ctlr->bbar) & ~bbar_mask; + ichspi_bbar |= minaddr; + ich_writel(ichspi_bbar, ctlr->bbar); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + puts("spi_cs_is_valid used but not implemented\n"); + return 0; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct ich_spi_slave *ich; + + ich = spi_alloc_slave(struct ich_spi_slave, bus, cs); + if (!ich) { + puts("ICH SPI: Out of memory\n"); + return NULL; + } + + /* + * Yes this controller can only write a small number of bytes at + * once! The limit is typically 64 bytes. + */ + ich->slave.max_write_size = ctlr.databytes; + ich->speed = max_hz; + + return &ich->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct ich_spi_slave *ich = to_ich_spi(slave); + + free(ich); +} + +/* + * Check if this device ID matches one of supported Intel PCH devices. + * + * Return the ICH version if there is a match, or zero otherwise. + */ +static int get_ich_version(uint16_t device_id) +{ + if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) + return 7; + + if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && + device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || + (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && + device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) + return 9; + + return 0; +} + +/* @return 1 if the SPI flash supports the 33MHz speed */ +static int ich9_can_do_33mhz(pci_dev_t dev) +{ + u32 fdod, speed; + + /* Observe SPI Descriptor Component Section 0 */ + pci_write_config_dword(dev, 0xb0, 0x1000); + + /* Extract the Write/Erase SPI Frequency from descriptor */ + pci_read_config_dword(dev, 0xb4, &fdod); + + /* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */ + speed = (fdod >> 21) & 7; + + return speed == 1; +} + +static int ich_find_spi_controller(pci_dev_t *devp, int *ich_versionp) +{ + int last_bus = pci_last_busno(); + int bus; + + if (last_bus == -1) { + debug("No PCI busses?\n"); + return -1; + } + + for (bus = 0; bus <= last_bus; bus++) { + uint16_t vendor_id, device_id; + uint32_t ids; + pci_dev_t dev; + + dev = PCI_BDF(bus, 31, 0); + pci_read_config_dword(dev, 0, &ids); + vendor_id = ids; + device_id = ids >> 16; + + if (vendor_id == PCI_VENDOR_ID_INTEL) { + *devp = dev; + *ich_versionp = get_ich_version(device_id); + return 0; + } + } + + debug("ICH SPI: No ICH found.\n"); + return -1; +} + +static int ich_init_controller(struct ich_ctlr *ctlr) +{ + uint8_t *rcrb; /* Root Complex Register Block */ + uint32_t rcba; /* Root Complex Base Address */ + + pci_read_config_dword(ctlr->dev, 0xf0, &rcba); + /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ + rcrb = (uint8_t *)(rcba & 0xffffc000); + if (ctlr->ich_version == 7) { + struct ich7_spi_regs *ich7_spi; + + ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020); + ctlr->ichspi_lock = ich_readw(&ich7_spi->spis) & SPIS_LOCK; + ctlr->opmenu = ich7_spi->opmenu; + ctlr->menubytes = sizeof(ich7_spi->opmenu); + ctlr->optype = &ich7_spi->optype; + ctlr->addr = &ich7_spi->spia; + ctlr->data = (uint8_t *)ich7_spi->spid; + ctlr->databytes = sizeof(ich7_spi->spid); + ctlr->status = (uint8_t *)&ich7_spi->spis; + ctlr->control = &ich7_spi->spic; + ctlr->bbar = &ich7_spi->bbar; + ctlr->preop = &ich7_spi->preop; + ctlr->base = ich7_spi; + } else if (ctlr->ich_version == 9) { + struct ich9_spi_regs *ich9_spi; + + ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800); + ctlr->ichspi_lock = ich_readw(&ich9_spi->hsfs) & HSFS_FLOCKDN; + ctlr->opmenu = ich9_spi->opmenu; + ctlr->menubytes = sizeof(ich9_spi->opmenu); + ctlr->optype = &ich9_spi->optype; + ctlr->addr = &ich9_spi->faddr; + ctlr->data = (uint8_t *)ich9_spi->fdata; + ctlr->databytes = sizeof(ich9_spi->fdata); + ctlr->status = &ich9_spi->ssfs; + ctlr->control = (uint16_t *)ich9_spi->ssfc; + ctlr->speed = ich9_spi->ssfc + 2; + ctlr->bbar = &ich9_spi->bbar; + ctlr->preop = &ich9_spi->preop; + ctlr->pr = &ich9_spi->pr[0]; + ctlr->base = ich9_spi; + } else { + debug("ICH SPI: Unrecognized ICH version %d.\n", + ctlr->ich_version); + return -1; + } + debug("ICH SPI: Version %d detected\n", ctlr->ich_version); + + /* Work out the maximum speed we can support */ + ctlr->max_speed = 20000000; + if (ctlr->ich_version == 9 && ich9_can_do_33mhz(ctlr->dev)) + ctlr->max_speed = 33000000; + + ich_set_bbar(ctlr, 0); + + return 0; +} + +void spi_init(void) +{ + uint8_t bios_cntl; + + if (ich_find_spi_controller(&ctlr.dev, &ctlr.ich_version)) { + printf("ICH SPI: Cannot find device\n"); + return; + } + + if (ich_init_controller(&ctlr)) { + printf("ICH SPI: Cannot setup controller\n"); + return; + } + + /* + * Disable the BIOS write protect so write commands are allowed. On + * v9, deassert SMM BIOS Write Protect Disable. + */ + pci_read_config_byte(ctlr.dev, 0xdc, &bios_cntl); + if (ctlr.ich_version == 9) + bios_cntl &= ~(1 << 5); + pci_write_config_byte(ctlr.dev, 0xdc, bios_cntl | 0x1); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ +} + +void spi_cs_activate(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* Handled by ICH automatically. */ +} + +static inline void spi_use_out(struct spi_trans *trans, unsigned bytes) +{ + trans->out += bytes; + trans->bytesout -= bytes; +} + +static inline void spi_use_in(struct spi_trans *trans, unsigned bytes) +{ + trans->in += bytes; + trans->bytesin -= bytes; +} + +static void spi_setup_type(struct spi_trans *trans, int data_bytes) +{ + trans->type = 0xFF; + + /* Try to guess spi type from read/write sizes. */ + if (trans->bytesin == 0) { + if (trans->bytesout + data_bytes > 4) + /* + * If bytesin = 0 and bytesout > 4, we presume this is + * a write data operation, which is accompanied by an + * address. + */ + trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; + else + trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; + return; + } + + if (trans->bytesout == 1) { /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; + return; + } + + if (trans->bytesout == 4) /* and bytesin is > 0 */ + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + + /* Fast read command is called with 5 bytes instead of 4 */ + if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { + trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; + --trans->bytesout; + } +} + +static int spi_setup_opcode(struct spi_trans *trans) +{ + uint16_t optypes; + uint8_t opmenu[ctlr.menubytes]; + + trans->opcode = trans->out[0]; + spi_use_out(trans, 1); + if (!ctlr.ichspi_lock) { + /* The lock is off, so just use index 0. */ + ich_writeb(trans->opcode, ctlr.opmenu); + optypes = ich_readw(ctlr.optype); + optypes = (optypes & 0xfffc) | (trans->type & 0x3); + ich_writew(optypes, ctlr.optype); + return 0; + } else { + /* The lock is on. See if what we need is on the menu. */ + uint8_t optype; + uint16_t opcode_index; + + /* Write Enable is handled as atomic prefix */ + if (trans->opcode == SPI_OPCODE_WREN) + return 0; + + read_reg(ctlr.opmenu, opmenu, sizeof(opmenu)); + for (opcode_index = 0; opcode_index < ctlr.menubytes; + opcode_index++) { + if (opmenu[opcode_index] == trans->opcode) + break; + } + + if (opcode_index == ctlr.menubytes) { + printf("ICH SPI: Opcode %x not found\n", + trans->opcode); + return -1; + } + + optypes = ich_readw(ctlr.optype); + optype = (optypes >> (opcode_index * 2)) & 0x3; + if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && + optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && + trans->bytesout >= 3) { + /* We guessed wrong earlier. Fix it up. */ + trans->type = optype; + } + if (optype != trans->type) { + printf("ICH SPI: Transaction doesn't fit type %d\n", + optype); + return -1; + } + return opcode_index; + } +} + +static int spi_setup_offset(struct spi_trans *trans) +{ + /* Separate the SPI address and data. */ + switch (trans->type) { + case SPI_OPCODE_TYPE_READ_NO_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: + return 0; + case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: + case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: + trans->offset = ((uint32_t)trans->out[0] << 16) | + ((uint32_t)trans->out[1] << 8) | + ((uint32_t)trans->out[2] << 0); + spi_use_out(trans, 3); + return 1; + default: + printf("Unrecognized SPI transaction type %#x\n", trans->type); + return -1; + } +} + +/* + * Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set + * below is true) or 0. In case the wait was for the bit(s) to set - write + * those bits back, which would cause resetting them. + * + * Return the last read status value on success or -1 on failure. + */ +static int ich_status_poll(u16 bitmask, int wait_til_set) +{ + int timeout = 600000; /* This will result in 6s */ + u16 status = 0; + + while (timeout--) { + status = ich_readw(ctlr.status); + if (wait_til_set ^ ((status & bitmask) == 0)) { + if (wait_til_set) + ich_writew((status & bitmask), ctlr.status); + return status; + } + udelay(10); + } + + printf("ICH SPI: SCIP timeout, read %x, expected %x\n", + status, bitmask); + return -1; +} + +/* +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) +*/ +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct ich_spi_slave *ich = to_ich_spi(slave); + uint16_t control; + int16_t opcode_index; + int with_address; + int status; + int bytes = bitlen / 8; + struct spi_trans *trans = &ich->trans; + unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END); + int using_cmd = 0; + /* Align read transactions to 64-byte boundaries */ + char buff[ctlr.databytes]; + + /* Ee don't support writing partial bytes. */ + if (bitlen % 8) { + debug("ICH SPI: Accessing partial bytes not supported\n"); + return -1; + } + + /* An empty end transaction can be ignored */ + if (type == SPI_XFER_END && !dout && !din) + return 0; + + if (type & SPI_XFER_BEGIN) + memset(trans, '\0', sizeof(*trans)); + + /* Dp we need to come back later to finish it? */ + if (dout && type == SPI_XFER_BEGIN) { + if (bytes > ICH_MAX_CMD_LEN) { + debug("ICH SPI: Command length limit exceeded\n"); + return -1; + } + memcpy(trans->cmd, dout, bytes); + trans->cmd_len = bytes; + debug("ICH SPI: Saved %d bytes\n", bytes); + return 0; + } + + /* + * We process a 'middle' spi_xfer() call, which has no + * SPI_XFER_BEGIN/END, as an independent transaction as if it had + * an end. We therefore repeat the command. This is because ICH + * seems to have no support for this, or because interest (in digging + * out the details and creating a special case in the code) is low. + */ + if (trans->cmd_len) { + trans->out = trans->cmd; + trans->bytesout = trans->cmd_len; + using_cmd = 1; + debug("ICH SPI: Using %d bytes\n", trans->cmd_len); + } else { + trans->out = dout; + trans->bytesout = dout ? bytes : 0; + } + + trans->in = din; + trans->bytesin = din ? bytes : 0; + + /* There has to always at least be an opcode. */ + if (!trans->bytesout) { + debug("ICH SPI: No opcode for transfer\n"); + return -1; + } + + if (ich_status_poll(SPIS_SCIP, 0) == -1) + return -1; + + ich_writew(SPIS_CDS | SPIS_FCERR, ctlr.status); + + spi_setup_type(trans, using_cmd ? bytes : 0); + opcode_index = spi_setup_opcode(trans); + if (opcode_index < 0) + return -1; + with_address = spi_setup_offset(trans); + if (with_address < 0) + return -1; + + if (trans->opcode == SPI_OPCODE_WREN) { + /* + * Treat Write Enable as Atomic Pre-Op if possible + * in order to prevent the Management Engine from + * issuing a transaction between WREN and DATA. + */ + if (!ctlr.ichspi_lock) + ich_writew(trans->opcode, ctlr.preop); + return 0; + } + + if (ctlr.speed && ctlr.max_speed >= 33000000) { + int byte; + + byte = ich_readb(ctlr.speed); + if (ich->speed >= 33000000) + byte |= SSFC_SCF_33MHZ; + else + byte &= ~SSFC_SCF_33MHZ; + ich_writeb(byte, ctlr.speed); + } + + /* See if we have used up the command data */ + if (using_cmd && dout && bytes) { + trans->out = dout; + trans->bytesout = bytes; + debug("ICH SPI: Moving to data, %d bytes\n", bytes); + } + + /* Preset control fields */ + control = ich_readw(ctlr.control); + control &= ~SSFC_RESERVED; + control = SPIC_SCGO | ((opcode_index & 0x07) << 4); + + /* Issue atomic preop cycle if needed */ + if (ich_readw(ctlr.preop)) + control |= SPIC_ACS; + + if (!trans->bytesout && !trans->bytesin) { + /* SPI addresses are 24 bit only */ + if (with_address) + ich_writel(trans->offset & 0x00FFFFFF, ctlr.addr); + + /* + * This is a 'no data' command (like Write Enable), its + * bitesout size was 1, decremented to zero while executing + * spi_setup_opcode() above. Tell the chip to send the + * command. + */ + ich_writew(control, ctlr.control); + + /* wait for the result */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + debug("ICH SPI: Command transaction error\n"); + return -1; + } + + return 0; + } + + /* + * Check if this is a write command atempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (trans->bytesout > ctlr.databytes) { + debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n"); + return -1; + } + + /* + * Read or write up to databytes bytes at a time until everything has + * been sent. + */ + while (trans->bytesout || trans->bytesin) { + uint32_t data_length; + uint32_t aligned_offset; + uint32_t diff; + + aligned_offset = trans->offset & ~(ctlr.databytes - 1); + diff = trans->offset - aligned_offset; + + /* SPI addresses are 24 bit only */ + ich_writel(aligned_offset & 0x00FFFFFF, ctlr.addr); + + if (trans->bytesout) + data_length = min(trans->bytesout, ctlr.databytes); + else + data_length = min(trans->bytesin, ctlr.databytes); + + /* Program data into FDATA0 to N */ + if (trans->bytesout) { + write_reg(trans->out, ctlr.data, data_length); + spi_use_out(trans, data_length); + if (with_address) + trans->offset += data_length; + } + + /* Add proper control fields' values */ + control &= ~((ctlr.databytes - 1) << 8); + control |= SPIC_DS; + control |= (data_length - 1) << 8; + + /* write it */ + ich_writew(control, ctlr.control); + + /* Wait for Cycle Done Status or Flash Cycle Error. */ + status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); + if (status == -1) + return -1; + + if (status & SPIS_FCERR) { + debug("ICH SPI: Data transaction error\n"); + return -1; + } + + if (trans->bytesin) { + if (diff) { + data_length -= diff; + read_reg(ctlr.data, buff, ctlr.databytes); + memcpy(trans->in, buff + diff, data_length); + } else { + read_reg(ctlr.data, trans->in, data_length); + } + spi_use_in(trans, data_length); + if (with_address) + trans->offset += data_length; + } + } + + /* Clear atomic preop now that xfer is done */ + ich_writew(0, ctlr.preop); + + return 0; +} + + +/* + * This uses the SPI controller from the Intel Cougar Point and Panther Point + * PCH to write-protect portions of the SPI flash until reboot. The changes + * don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's + * done elsewhere. + */ +int spi_write_protect_region(uint32_t lower_limit, uint32_t length, int hint) +{ + uint32_t tmplong; + uint32_t upper_limit; + + if (!ctlr.pr) { + printf("%s: operation not supported on this chipset\n", + __func__); + return -1; + } + + if (length == 0 || + lower_limit > (0xFFFFFFFFUL - length) + 1 || + hint < 0 || hint > 4) { + printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__, + lower_limit, length, hint); + return -1; + } + + upper_limit = lower_limit + length - 1; + + /* + * Determine bits to write, as follows: + * 31 Write-protection enable (includes erase operation) + * 30:29 reserved + * 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff) + * 15 Read-protection enable + * 14:13 reserved + * 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000) + */ + tmplong = 0x80000000 | + ((upper_limit & 0x01fff000) << 4) | + ((lower_limit & 0x01fff000) >> 12); + + printf("%s: writing 0x%08x to %p\n", __func__, tmplong, + &ctlr.pr[hint]); + ctlr.pr[hint] = tmplong; + + return 0; +} diff --git a/drivers/spi/ich.h b/drivers/spi/ich.h new file mode 100644 index 0000000..bd7bc12 --- /dev/null +++ b/drivers/spi/ich.h @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This file is derived from the flashrom project. + */ + +struct ich7_spi_regs { + uint16_t spis; + uint16_t spic; + uint32_t spia; + uint64_t spid[8]; + uint64_t _pad; + uint32_t bbar; + uint16_t preop; + uint16_t optype; + uint8_t opmenu[8]; +} __packed; + +struct ich9_spi_regs { + uint32_t bfpr; /* 0x00 */ + uint16_t hsfs; + uint16_t hsfc; + uint32_t faddr; + uint32_t _reserved0; + uint32_t fdata[16]; /* 0x10 */ + uint32_t frap; /* 0x50 */ + uint32_t freg[5]; + uint32_t _reserved1[3]; + uint32_t pr[5]; /* 0x74 */ + uint32_t _reserved2[2]; + uint8_t ssfs; /* 0x90 */ + uint8_t ssfc[3]; + uint16_t preop; /* 0x94 */ + uint16_t optype; + uint8_t opmenu[8]; /* 0x98 */ + uint32_t bbar; + uint8_t _reserved3[12]; + uint32_t fdoc; + uint32_t fdod; + uint8_t _reserved4[8]; + uint32_t afc; + uint32_t lvscc; + uint32_t uvscc; + uint8_t _reserved5[4]; + uint32_t fpb; + uint8_t _reserved6[28]; + uint32_t srdl; + uint32_t srdc; + uint32_t srd; +} __packed; + +enum { + SPIS_SCIP = 0x0001, + SPIS_GRANT = 0x0002, + SPIS_CDS = 0x0004, + SPIS_FCERR = 0x0008, + SSFS_AEL = 0x0010, + SPIS_LOCK = 0x8000, + SPIS_RESERVED_MASK = 0x7ff0, + SSFS_RESERVED_MASK = 0x7fe2 +}; + +enum { + SPIC_SCGO = 0x000002, + SPIC_ACS = 0x000004, + SPIC_SPOP = 0x000008, + SPIC_DBC = 0x003f00, + SPIC_DS = 0x004000, + SPIC_SME = 0x008000, + SSFC_SCF_MASK = 0x070000, + SSFC_RESERVED = 0xf80000, + + /* Mask for speed byte, biuts 23:16 of SSFC */ + SSFC_SCF_33MHZ = 0x01, +}; + +enum { + HSFS_FDONE = 0x0001, + HSFS_FCERR = 0x0002, + HSFS_AEL = 0x0004, + HSFS_BERASE_MASK = 0x0018, + HSFS_BERASE_SHIFT = 3, + HSFS_SCIP = 0x0020, + HSFS_FDOPSS = 0x2000, + HSFS_FDV = 0x4000, + HSFS_FLOCKDN = 0x8000 +}; + +enum { + HSFC_FGO = 0x0001, + HSFC_FCYCLE_MASK = 0x0006, + HSFC_FCYCLE_SHIFT = 1, + HSFC_FDBC_MASK = 0x3f00, + HSFC_FDBC_SHIFT = 8, + HSFC_FSMIE = 0x8000 +}; + +enum { + SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, + SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, + SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, + SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 +}; + +enum { + ICH_MAX_CMD_LEN = 5, +}; + +struct spi_trans { + uint8_t cmd[ICH_MAX_CMD_LEN]; + int cmd_len; + const uint8_t *out; + uint32_t bytesout; + uint8_t *in; + uint32_t bytesin; + uint8_t type; + uint8_t opcode; + uint32_t offset; +}; + +struct ich_spi_slave { + struct spi_slave slave; + struct spi_trans trans; /* current transaction in progress */ + int speed; /* SPI speed in Hz */ +}; diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c index de81064..caa91e3 100644 --- a/drivers/spi/kirkwood_spi.c +++ b/drivers/spi/kirkwood_spi.c @@ -49,13 +49,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!spi_cs_is_valid(bus, cs)) return NULL; - slave = malloc(sizeof(struct spi_slave)); + slave = spi_alloc_slave_base(bus, cs); if (!slave) return NULL; - slave->bus = bus; - slave->cs = cs; - writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl); /* calculate spi clock prescaller using max_hz */ diff --git a/drivers/spi/mpc52xx_spi.c b/drivers/spi/mpc52xx_spi.c index 3e96b3f..4b50bca 100644 --- a/drivers/spi/mpc52xx_spi.c +++ b/drivers/spi/mpc52xx_spi.c @@ -48,13 +48,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, { struct spi_slave *slave; - slave = malloc(sizeof(struct spi_slave)); + slave = spi_alloc_slave_base(bus, cs); if (!slave) return NULL; - slave->bus = bus; - slave->cs = cs; - return slave; } diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index 4e46041..6b0e3b4 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -45,13 +45,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!spi_cs_is_valid(bus, cs)) return NULL; - slave = malloc(sizeof(struct spi_slave)); + slave = spi_alloc_slave_base(bus, cs); if (!slave) return NULL; - slave->bus = bus; - slave->cs = cs; - /* * TODO: Some of the code in spi_init() should probably move * here, or into spi_claim_bus() below. diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 20419e6..5bed858 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -409,7 +409,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (bus >= ARRAY_SIZE(spi_bases)) return NULL; - mxcs = calloc(sizeof(struct mxc_spi_slave), 1); + mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs); if (!mxcs) { puts("mxc_spi: SPI Slave not allocated !\n"); return NULL; @@ -425,8 +425,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, cs = ret; - mxcs->slave.bus = bus; - mxcs->slave.cs = cs; mxcs->base = spi_bases[bus]; ret = spi_cfg_mxc(mxcs, cs, max_hz, mode); diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c index ffa3c1d..aa999f9 100644 --- a/drivers/spi/mxs_spi.c +++ b/drivers/spi/mxs_spi.c @@ -77,15 +77,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; } - mxs_slave = calloc(sizeof(struct mxs_spi_slave), 1); + mxs_slave = spi_alloc_slave(struct mxs_spi_slave, bus, cs); if (!mxs_slave) return NULL; if (mxs_dma_init_channel(MXS_DMA_CHANNEL_AHB_APBH_SSP0 + bus)) goto err_init; - mxs_slave->slave.bus = bus; - mxs_slave->slave.cs = cs; mxs_slave->max_khz = max_hz / 1000; mxs_slave->mode = mode; mxs_slave->regs = mxs_ssp_regs_by_bus(bus); diff --git a/drivers/spi/oc_tiny_spi.c b/drivers/spi/oc_tiny_spi.c index fc01fb8..6f7b1ed 100644 --- a/drivers/spi/oc_tiny_spi.c +++ b/drivers/spi/oc_tiny_spi.c @@ -90,13 +90,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!spi_cs_is_valid(bus, cs) || gpio_request(cs, "tiny_spi")) return NULL; - tiny_spi = malloc(sizeof(*tiny_spi)); + tiny_spi = spi_alloc_slave(struct tiny_spi_slave, bus, cs); if (!tiny_spi) return NULL; - memset(tiny_spi, 0, sizeof(*tiny_spi)); - tiny_spi->slave.bus = bus; - tiny_spi->slave.cs = cs; tiny_spi->host = &tiny_spi_host_list[bus]; tiny_spi->mode = mode & (SPI_CPOL | SPI_CPHA); tiny_spi->flg = mode & SPI_CS_HIGH ? 1 : 0; diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 344d5b8..80a4e47 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -80,12 +80,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct omap3_spi_slave *ds; - - ds = malloc(sizeof(struct omap3_spi_slave)); - if (!ds) { - printf("SPI error: malloc of SPI structure failed\n"); - return NULL; - } + struct mcspi *regs; /* * OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules) @@ -98,21 +93,21 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, switch (bus) { case 0: - ds->regs = (struct mcspi *)OMAP3_MCSPI1_BASE; + regs = (struct mcspi *)OMAP3_MCSPI1_BASE; break; #ifdef OMAP3_MCSPI2_BASE case 1: - ds->regs = (struct mcspi *)OMAP3_MCSPI2_BASE; + regs = (struct mcspi *)OMAP3_MCSPI2_BASE; break; #endif #ifdef OMAP3_MCSPI3_BASE case 2: - ds->regs = (struct mcspi *)OMAP3_MCSPI3_BASE; + regs = (struct mcspi *)OMAP3_MCSPI3_BASE; break; #endif #ifdef OMAP3_MCSPI4_BASE case 3: - ds->regs = (struct mcspi *)OMAP3_MCSPI4_BASE; + regs = (struct mcspi *)OMAP3_MCSPI4_BASE; break; #endif default: @@ -120,7 +115,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, Supported busses 0 - 3\n", bus); return NULL; } - ds->slave.bus = bus; if (((bus == 0) && (cs > 3)) || ((bus == 1) && (cs > 1)) || @@ -130,19 +124,26 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, on bus %i\n", cs, bus); return NULL; } - ds->slave.cs = cs; if (max_hz > OMAP3_MCSPI_MAX_FREQ) { printf("SPI error: unsupported frequency %i Hz. \ Max frequency is 48 Mhz\n", max_hz); return NULL; } - ds->freq = max_hz; if (mode > SPI_MODE_3) { printf("SPI error: unsupported SPI mode %i\n", mode); return NULL; } + + ds = spi_alloc_slave(struct omap3_spi_slave, bus, cs); + if (!ds) { + printf("SPI error: malloc of SPI structure failed\n"); + return NULL; + } + + ds->regs = regs; + ds->freq = max_hz; ds->mode = mode; return &ds->slave; diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c index e944b23..744afe3 100644 --- a/drivers/spi/sh_spi.c +++ b/drivers/spi/sh_spi.c @@ -103,12 +103,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!spi_cs_is_valid(bus, cs)) return NULL; - ss = malloc(sizeof(struct spi_slave)); + ss = spi_alloc_slave(struct sh_spi, bus, cs); if (!ss) return NULL; - ss->slave.bus = bus; - ss->slave.cs = cs; ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE; /* SPI sycle stop */ diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c index 13df8cb..a1b84b6 100644 --- a/drivers/spi/soft_spi.c +++ b/drivers/spi/soft_spi.c @@ -73,12 +73,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!spi_cs_is_valid(bus, cs)) return NULL; - ss = malloc(sizeof(struct soft_spi_slave)); + ss = spi_alloc_slave(struct soft_spi_slave, bus, cs); if (!ss) return NULL; - ss->slave.bus = bus; - ss->slave.cs = cs; ss->mode = mode; /* TODO: Use max_hz to limit the SCK rate */ diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c new file mode 100644 index 0000000..cb36c5e --- /dev/null +++ b/drivers/spi/spi.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> + +void *spi_do_alloc_slave(int offset, int size, unsigned int bus, + unsigned int cs) +{ + struct spi_slave *slave; + void *ptr; + + ptr = malloc(size); + if (ptr) { + memset(ptr, '\0', size); + slave = (struct spi_slave *)(ptr + offset); + slave->bus = bus; + slave->cs = cs; + } + + return ptr; +} diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c new file mode 100644 index 0000000..b11a0a1 --- /dev/null +++ b/drivers/spi/tegra114_spi.c @@ -0,0 +1,405 @@ +/* + * NVIDIA Tegra SPI controller (T114 and later) + * + * Copyright (c) 2010-2013 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch-tegra/clk_rst.h> +#include <asm/arch-tegra114/tegra114_spi.h> +#include <spi.h> +#include <fdtdec.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* COMMAND1 */ +#define SPI_CMD1_GO (1 << 31) +#define SPI_CMD1_M_S (1 << 30) +#define SPI_CMD1_MODE_MASK 0x3 +#define SPI_CMD1_MODE_SHIFT 28 +#define SPI_CMD1_CS_SEL_MASK 0x3 +#define SPI_CMD1_CS_SEL_SHIFT 26 +#define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25) +#define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24) +#define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23) +#define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22) +#define SPI_CMD1_CS_SW_HW (1 << 21) +#define SPI_CMD1_CS_SW_VAL (1 << 20) +#define SPI_CMD1_IDLE_SDA_MASK 0x3 +#define SPI_CMD1_IDLE_SDA_SHIFT 18 +#define SPI_CMD1_BIDIR (1 << 17) +#define SPI_CMD1_LSBI_FE (1 << 16) +#define SPI_CMD1_LSBY_FE (1 << 15) +#define SPI_CMD1_BOTH_EN_BIT (1 << 14) +#define SPI_CMD1_BOTH_EN_BYTE (1 << 13) +#define SPI_CMD1_RX_EN (1 << 12) +#define SPI_CMD1_TX_EN (1 << 11) +#define SPI_CMD1_PACKED (1 << 5) +#define SPI_CMD1_BIT_LEN_MASK 0x1F +#define SPI_CMD1_BIT_LEN_SHIFT 0 + +/* COMMAND2 */ +#define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6) +#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6) +#define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0) +#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0) + +/* TRANSFER STATUS */ +#define SPI_XFER_STS_RDY (1 << 30) + +/* FIFO STATUS */ +#define SPI_FIFO_STS_CS_INACTIVE (1 << 31) +#define SPI_FIFO_STS_FRAME_END (1 << 30) +#define SPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15) +#define SPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14) +#define SPI_FIFO_STS_ERR (1 << 8) +#define SPI_FIFO_STS_TX_FIFO_OVF (1 << 7) +#define SPI_FIFO_STS_TX_FIFO_UNR (1 << 6) +#define SPI_FIFO_STS_RX_FIFO_OVF (1 << 5) +#define SPI_FIFO_STS_RX_FIFO_UNR (1 << 4) +#define SPI_FIFO_STS_TX_FIFO_FULL (1 << 3) +#define SPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2) +#define SPI_FIFO_STS_RX_FIFO_FULL (1 << 1) +#define SPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0) + +#define SPI_TIMEOUT 1000 +#define TEGRA_SPI_MAX_FREQ 52000000 + +struct spi_regs { + u32 command1; /* 000:SPI_COMMAND1 register */ + u32 command2; /* 004:SPI_COMMAND2 register */ + u32 timing1; /* 008:SPI_CS_TIM1 register */ + u32 timing2; /* 00c:SPI_CS_TIM2 register */ + u32 xfer_status;/* 010:SPI_TRANS_STATUS register */ + u32 fifo_status;/* 014:SPI_FIFO_STATUS register */ + u32 tx_data; /* 018:SPI_TX_DATA register */ + u32 rx_data; /* 01c:SPI_RX_DATA register */ + u32 dma_ctl; /* 020:SPI_DMA_CTL register */ + u32 dma_blk; /* 024:SPI_DMA_BLK register */ + u32 rsvd[56]; /* 028-107 reserved */ + u32 tx_fifo; /* 108:SPI_FIFO1 register */ + u32 rsvd2[31]; /* 10c-187 reserved */ + u32 rx_fifo; /* 188:SPI_FIFO2 register */ + u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */ +}; + +struct tegra_spi_ctrl { + struct spi_regs *regs; + unsigned int freq; + unsigned int mode; + int periph_id; + int valid; +}; + +struct tegra_spi_slave { + struct spi_slave slave; + struct tegra_spi_ctrl *ctrl; +}; + +static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA114_SPI_CTRLS]; + +static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) +{ + return container_of(slave, struct tegra_spi_slave, slave); +} + +int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + if (bus >= CONFIG_TEGRA114_SPI_CTRLS || cs > 3 || !spi_ctrls[bus].valid) + return 0; + else + return 1; +} + +struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct tegra_spi_slave *spi; + + debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__, + bus, cs, max_hz, mode); + + if (!spi_cs_is_valid(bus, cs)) { + printf("SPI error: unsupported bus %d / chip select %d\n", + bus, cs); + return NULL; + } + + if (max_hz > TEGRA_SPI_MAX_FREQ) { + printf("SPI error: unsupported frequency %d Hz. Max frequency" + " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ); + return NULL; + } + + spi = malloc(sizeof(struct tegra_spi_slave)); + if (!spi) { + printf("SPI error: malloc of SPI structure failed\n"); + return NULL; + } + spi->slave.bus = bus; + spi->slave.cs = cs; + spi->ctrl = &spi_ctrls[bus]; + if (!spi->ctrl) { + printf("SPI error: could not find controller for bus %d\n", + bus); + return NULL; + } + + if (max_hz < spi->ctrl->freq) { + debug("%s: limiting frequency from %u to %u\n", __func__, + spi->ctrl->freq, max_hz); + spi->ctrl->freq = max_hz; + } + spi->ctrl->mode = mode; + + return &spi->slave; +} + +void tegra114_spi_free_slave(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + + free(spi); +} + +int tegra114_spi_init(int *node_list, int count) +{ + struct tegra_spi_ctrl *ctrl; + int i; + int node = 0; + int found = 0; + + for (i = 0; i < count; i++) { + ctrl = &spi_ctrls[i]; + node = node_list[i]; + + ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob, + node, "reg"); + if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) { + debug("%s: no spi register found\n", __func__); + continue; + } + ctrl->freq = fdtdec_get_int(gd->fdt_blob, node, + "spi-max-frequency", 0); + if (!ctrl->freq) { + debug("%s: no spi max frequency found\n", __func__); + continue; + } + + ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node); + if (ctrl->periph_id == PERIPH_ID_NONE) { + debug("%s: could not decode periph id\n", __func__); + continue; + } + ctrl->valid = 1; + found = 1; + + debug("%s: found controller at %p, freq = %u, periph_id = %d\n", + __func__, ctrl->regs, ctrl->freq, ctrl->periph_id); + } + + return !found; +} + +int tegra114_spi_claim_bus(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + struct spi_regs *regs = spi->ctrl->regs; + + /* Change SPI clock to correct frequency, PLLP_OUT0 source */ + clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH, + spi->ctrl->freq); + + /* Clear stale status here */ + setbits_le32(®s->fifo_status, + SPI_FIFO_STS_ERR | + SPI_FIFO_STS_TX_FIFO_OVF | + SPI_FIFO_STS_TX_FIFO_UNR | + SPI_FIFO_STS_RX_FIFO_OVF | + SPI_FIFO_STS_RX_FIFO_UNR | + SPI_FIFO_STS_TX_FIFO_FULL | + SPI_FIFO_STS_TX_FIFO_EMPTY | + SPI_FIFO_STS_RX_FIFO_FULL | + SPI_FIFO_STS_RX_FIFO_EMPTY); + debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); + + /* Set master mode and sw controlled CS */ + setbits_le32(®s->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW | + (spi->ctrl->mode << SPI_CMD1_MODE_SHIFT)); + debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); + + return 0; +} + +void tegra114_spi_cs_activate(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + struct spi_regs *regs = spi->ctrl->regs; + + clrbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL); +} + +void tegra114_spi_cs_deactivate(struct spi_slave *slave) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + struct spi_regs *regs = spi->ctrl->regs; + + setbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL); +} + +int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags) +{ + struct tegra_spi_slave *spi = to_tegra_spi(slave); + struct spi_regs *regs = spi->ctrl->regs; + u32 reg, tmpdout, tmpdin = 0; + const u8 *dout = data_out; + u8 *din = data_in; + int num_bytes; + int ret; + + debug("%s: slave %u:%u dout %p din %p bitlen %u\n", + __func__, slave->bus, slave->cs, dout, din, bitlen); + if (bitlen % 8) + return -1; + num_bytes = bitlen / 8; + + ret = 0; + + /* clear all error status bits */ + reg = readl(®s->fifo_status); + writel(reg, ®s->fifo_status); + + /* clear ready bit */ + setbits_le32(®s->xfer_status, SPI_XFER_STS_RDY); + + clrsetbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL, + SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE | + (slave->cs << SPI_CMD1_CS_SEL_SHIFT)); + + /* set xfer size to 1 block (32 bits) */ + writel(0, ®s->dma_blk); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + /* handle data in 32-bit chunks */ + while (num_bytes > 0) { + int bytes; + int is_read = 0; + int tm, i; + + tmpdout = 0; + bytes = (num_bytes > 4) ? 4 : num_bytes; + + if (dout != NULL) { + for (i = 0; i < bytes; ++i) + tmpdout = (tmpdout << 8) | dout[i]; + dout += bytes; + } + + num_bytes -= bytes; + + clrsetbits_le32(®s->command1, + SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT, + (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT); + writel(tmpdout, ®s->tx_fifo); + setbits_le32(®s->command1, SPI_CMD1_GO); + + /* + * Wait for SPI transmit FIFO to empty, or to time out. + * The RX FIFO status will be read and cleared last + */ + for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { + u32 fifo_status, xfer_status; + + fifo_status = readl(®s->fifo_status); + + /* We can exit when we've had both RX and TX activity */ + if (is_read && + (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)) + break; + + xfer_status = readl(®s->xfer_status); + if (!(xfer_status & SPI_XFER_STS_RDY)) + continue; + + if (fifo_status & SPI_FIFO_STS_ERR) { + debug("%s: got a fifo error: ", __func__); + if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF) + debug("tx FIFO overflow "); + if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR) + debug("tx FIFO underrun "); + if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF) + debug("rx FIFO overflow "); + if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR) + debug("rx FIFO underrun "); + if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL) + debug("tx FIFO full "); + if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY) + debug("tx FIFO empty "); + if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL) + debug("rx FIFO full "); + if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY) + debug("rx FIFO empty "); + debug("\n"); + break; + } + + if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) { + tmpdin = readl(®s->rx_fifo); + is_read = 1; + + /* swap bytes read in */ + if (din != NULL) { + for (i = bytes - 1; i >= 0; --i) { + din[i] = tmpdin & 0xff; + tmpdin >>= 8; + } + din += bytes; + } + } + } + + if (tm >= SPI_TIMEOUT) + ret = tm; + + /* clear ACK RDY, etc. bits */ + writel(readl(®s->fifo_status), ®s->fifo_status); + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n", + __func__, tmpdin, readl(®s->fifo_status)); + + if (ret) { + printf("%s: timeout during SPI transfer, tm %d\n", + __func__, ret); + return -1; + } + + return 0; +} diff --git a/drivers/spi/tegra_spi.c b/drivers/spi/tegra20_sflash.c index ce19095..9322ce7 100644 --- a/drivers/spi/tegra_spi.c +++ b/drivers/spi/tegra20_sflash.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2012 NVIDIA Corporation + * Copyright (c) 2010-2013 NVIDIA Corporation * With help from the mpc8xxx SPI driver * With more help from omap3_spi SPI driver * @@ -28,34 +28,80 @@ #include <asm/gpio.h> #include <asm/arch/clock.h> #include <asm/arch/pinmux.h> -#include <asm/arch/uart-spi-switch.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/tegra_spi.h> +#include <asm/arch-tegra20/tegra20_sflash.h> #include <spi.h> #include <fdtdec.h> DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_SPI_CORRUPTS_UART) - #define corrupt_delay() udelay(CONFIG_SPI_CORRUPTS_UART_DLY); -#else - #define corrupt_delay() -#endif +#define SPI_CMD_GO (1 << 30) +#define SPI_CMD_ACTIVE_SCLK_SHIFT 26 +#define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT) +#define SPI_CMD_CK_SDA (1 << 21) +#define SPI_CMD_ACTIVE_SDA_SHIFT 18 +#define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT) +#define SPI_CMD_CS_POL (1 << 16) +#define SPI_CMD_TXEN (1 << 15) +#define SPI_CMD_RXEN (1 << 14) +#define SPI_CMD_CS_VAL (1 << 13) +#define SPI_CMD_CS_SOFT (1 << 12) +#define SPI_CMD_CS_DELAY (1 << 9) +#define SPI_CMD_CS3_EN (1 << 8) +#define SPI_CMD_CS2_EN (1 << 7) +#define SPI_CMD_CS1_EN (1 << 6) +#define SPI_CMD_CS0_EN (1 << 5) +#define SPI_CMD_BIT_LENGTH (1 << 4) +#define SPI_CMD_BIT_LENGTH_MASK 0x0000001F + +#define SPI_STAT_BSY (1 << 31) +#define SPI_STAT_RDY (1 << 30) +#define SPI_STAT_RXF_FLUSH (1 << 29) +#define SPI_STAT_TXF_FLUSH (1 << 28) +#define SPI_STAT_RXF_UNR (1 << 27) +#define SPI_STAT_TXF_OVF (1 << 26) +#define SPI_STAT_RXF_EMPTY (1 << 25) +#define SPI_STAT_RXF_FULL (1 << 24) +#define SPI_STAT_TXF_EMPTY (1 << 23) +#define SPI_STAT_TXF_FULL (1 << 22) +#define SPI_STAT_SEL_TXRX_N (1 << 16) +#define SPI_STAT_CUR_BLKCNT (1 << 15) + +#define SPI_TIMEOUT 1000 +#define TEGRA_SPI_MAX_FREQ 52000000 + +struct spi_regs { + u32 command; /* SPI_COMMAND_0 register */ + u32 status; /* SPI_STATUS_0 register */ + u32 rx_cmp; /* SPI_RX_CMP_0 register */ + u32 dma_ctl; /* SPI_DMA_CTL_0 register */ + u32 tx_fifo; /* SPI_TX_FIFO_0 register */ + u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */ + u32 rx_fifo; /* SPI_RX_FIFO_0 register */ +}; -struct tegra_spi_slave { - struct spi_slave slave; - struct spi_tegra *regs; +struct tegra_spi_ctrl { + struct spi_regs *regs; unsigned int freq; unsigned int mode; int periph_id; + int valid; }; +struct tegra_spi_slave { + struct spi_slave slave; + struct tegra_spi_ctrl *ctrl; +}; + +/* tegra20 only supports one SFLASH controller */ +static struct tegra_spi_ctrl spi_ctrls[1]; + static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) { return container_of(slave, struct tegra_spi_slave, slave); } -int spi_cs_is_valid(unsigned int bus, unsigned int cs) +int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs) { /* Tegra20 SPI-Flash - only 1 device ('bus/cs') */ if (bus != 0 || cs != 0) @@ -64,8 +110,8 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) return 1; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) +struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) { struct tegra_spi_slave *spi; @@ -81,93 +127,100 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; } - spi = malloc(sizeof(struct tegra_spi_slave)); + spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs); if (!spi) { printf("SPI error: malloc of SPI structure failed\n"); return NULL; } spi->slave.bus = bus; spi->slave.cs = cs; -#ifdef CONFIG_OF_CONTROL - int node = fdtdec_next_compatible(gd->fdt_blob, 0, - COMPAT_NVIDIA_TEGRA20_SFLASH); - if (node < 0) { - debug("%s: cannot locate sflash node\n", __func__); + spi->ctrl = &spi_ctrls[bus]; + if (!spi->ctrl) { + printf("SPI error: could not find controller for bus %d\n", + bus); return NULL; } - if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) { - debug("%s: sflash is disabled\n", __func__); - return NULL; - } - spi->regs = (struct spi_tegra *)fdtdec_get_addr(gd->fdt_blob, - node, "reg"); - if ((fdt_addr_t)spi->regs == FDT_ADDR_T_NONE) { - debug("%s: no sflash register found\n", __func__); - return NULL; - } - spi->freq = fdtdec_get_int(gd->fdt_blob, node, "spi-max-frequency", 0); - if (!spi->freq) { - debug("%s: no sflash max frequency found\n", __func__); - return NULL; - } - spi->periph_id = clock_decode_periph_id(gd->fdt_blob, node); - if (spi->periph_id == PERIPH_ID_NONE) { - debug("%s: could not decode periph id\n", __func__); - return NULL; - } -#else - spi->regs = (struct spi_tegra *)NV_PA_SPI_BASE; - spi->freq = TEGRA_SPI_MAX_FREQ; - spi->periph_id = PERIPH_ID_SPI1; -#endif - if (max_hz < spi->freq) { + + if (max_hz < spi->ctrl->freq) { debug("%s: limiting frequency from %u to %u\n", __func__, - spi->freq, max_hz); - spi->freq = max_hz; + spi->ctrl->freq, max_hz); + spi->ctrl->freq = max_hz; } - debug("%s: controller initialized at %p, freq = %u, periph_id = %d\n", - __func__, spi->regs, spi->freq, spi->periph_id); - spi->mode = mode; + spi->ctrl->mode = mode; return &spi->slave; } -void spi_free_slave(struct spi_slave *slave) +void tegra20_spi_free_slave(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); free(spi); } -void spi_init(void) +int tegra20_spi_init(int *node_list, int count) { - /* do nothing */ + struct tegra_spi_ctrl *ctrl; + int i; + int node = 0; + int found = 0; + + for (i = 0; i < count; i++) { + ctrl = &spi_ctrls[i]; + node = node_list[i]; + + ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob, + node, "reg"); + if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) { + debug("%s: no slink register found\n", __func__); + continue; + } + ctrl->freq = fdtdec_get_int(gd->fdt_blob, node, + "spi-max-frequency", 0); + if (!ctrl->freq) { + debug("%s: no slink max frequency found\n", __func__); + continue; + } + + ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node); + if (ctrl->periph_id == PERIPH_ID_NONE) { + debug("%s: could not decode periph id\n", __func__); + continue; + } + ctrl->valid = 1; + found = 1; + + debug("%s: found controller at %p, freq = %u, periph_id = %d\n", + __func__, ctrl->regs, ctrl->freq, ctrl->periph_id); + } + return !found; } -int spi_claim_bus(struct spi_slave *slave) +int tegra20_spi_claim_bus(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_tegra *regs = spi->regs; + struct spi_regs *regs = spi->ctrl->regs; u32 reg; /* Change SPI clock to correct frequency, PLLP_OUT0 source */ - clock_start_periph_pll(spi->periph_id, CLOCK_ID_PERIPH, spi->freq); + clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH, + spi->ctrl->freq); /* Clear stale status here */ reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \ SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF; writel(reg, ®s->status); - debug("spi_init: STATUS = %08x\n", readl(®s->status)); + debug("%s: STATUS = %08x\n", __func__, readl(®s->status)); /* * Use sw-controlled CS, so we can clock in data after ReadID, etc. */ - reg = (spi->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT; - if (spi->mode & 2) + reg = (spi->ctrl->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT; + if (spi->ctrl->mode & 2) reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT; clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK | SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg); - debug("spi_init: COMMAND = %08x\n", readl(®s->command)); + debug("%s: COMMAND = %08x\n", __func__, readl(®s->command)); /* * SPI pins on Tegra20 are muxed - change pinmux later due to UART @@ -175,58 +228,34 @@ int spi_claim_bus(struct spi_slave *slave) */ pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH); pinmux_tristate_disable(PINGRP_LSPI); + pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); -#ifndef CONFIG_SPI_UART_SWITCH - /* - * NOTE: - * Only set PinMux bits 3:2 to SPI here on boards that don't have the - * SPI UART switch or subsequent UART data won't go out! See - * spi_uart_switch(). - */ - /* TODO: pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH); */ -#endif return 0; } -void spi_release_bus(struct spi_slave *slave) -{ - /* - * We can't release UART_DISABLE and set pinmux to UART4 here since - * some code (e,g, spi_flash_probe) uses printf() while the SPI - * bus is held. That is arguably bad, but it has the advantage of - * already being in the source tree. - */ -} - -void spi_cs_activate(struct spi_slave *slave) +void tegra20_spi_cs_activate(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); - - pinmux_select_spi(); + struct spi_regs *regs = spi->ctrl->regs; /* CS is negated on Tegra, so drive a 1 to get a 0 */ - setbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); - - corrupt_delay(); /* Let UART settle */ + setbits_le32(®s->command, SPI_CMD_CS_VAL); } -void spi_cs_deactivate(struct spi_slave *slave) +void tegra20_spi_cs_deactivate(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); - - pinmux_select_uart(); + struct spi_regs *regs = spi->ctrl->regs; /* CS is negated on Tegra, so drive a 0 to get a 1 */ - clrbits_le32(&spi->regs->command, SPI_CMD_CS_VAL); - - corrupt_delay(); /* Let SPI settle */ + clrbits_le32(®s->command, SPI_CMD_CS_VAL); } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, +int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, void *data_in, unsigned long flags) { struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct spi_tegra *regs = spi->regs; + struct spi_regs *regs = spi->ctrl->regs; u32 reg, tmpdout, tmpdin = 0; const u8 *dout = data_out; u8 *din = data_in; diff --git a/drivers/spi/tegra_slink.c b/drivers/spi/tegra20_slink.c index 2c41fab..664de6e 100644 --- a/drivers/spi/tegra_slink.c +++ b/drivers/spi/tegra20_slink.c @@ -27,14 +27,68 @@ #include <asm/gpio.h> #include <asm/arch/clock.h> #include <asm/arch-tegra/clk_rst.h> -#include <asm/arch-tegra/tegra_slink.h> +#include <asm/arch-tegra20/tegra20_slink.h> #include <spi.h> #include <fdtdec.h> DECLARE_GLOBAL_DATA_PTR; +/* COMMAND */ +#define SLINK_CMD_ENB (1 << 31) +#define SLINK_CMD_GO (1 << 30) +#define SLINK_CMD_M_S (1 << 28) +#define SLINK_CMD_CK_SDA (1 << 21) +#define SLINK_CMD_CS_POL (1 << 13) +#define SLINK_CMD_CS_VAL (1 << 12) +#define SLINK_CMD_CS_SOFT (1 << 11) +#define SLINK_CMD_BIT_LENGTH (1 << 4) +#define SLINK_CMD_BIT_LENGTH_MASK 0x0000001F +/* COMMAND2 */ +#define SLINK_CMD2_TXEN (1 << 30) +#define SLINK_CMD2_RXEN (1 << 31) +#define SLINK_CMD2_SS_EN (1 << 18) +#define SLINK_CMD2_SS_EN_SHIFT 18 +#define SLINK_CMD2_SS_EN_MASK 0x000C0000 +#define SLINK_CMD2_CS_ACTIVE_BETWEEN (1 << 17) +/* STATUS */ +#define SLINK_STAT_BSY (1 << 31) +#define SLINK_STAT_RDY (1 << 30) +#define SLINK_STAT_ERR (1 << 29) +#define SLINK_STAT_RXF_FLUSH (1 << 27) +#define SLINK_STAT_TXF_FLUSH (1 << 26) +#define SLINK_STAT_RXF_OVF (1 << 25) +#define SLINK_STAT_TXF_UNR (1 << 24) +#define SLINK_STAT_RXF_EMPTY (1 << 23) +#define SLINK_STAT_RXF_FULL (1 << 22) +#define SLINK_STAT_TXF_EMPTY (1 << 21) +#define SLINK_STAT_TXF_FULL (1 << 20) +#define SLINK_STAT_TXF_OVF (1 << 19) +#define SLINK_STAT_RXF_UNR (1 << 18) +#define SLINK_STAT_CUR_BLKCNT (1 << 15) +/* STATUS2 */ +#define SLINK_STAT2_RXF_FULL_CNT (1 << 16) +#define SLINK_STAT2_TXF_FULL_CNT (1 << 0) + +#define SPI_TIMEOUT 1000 +#define TEGRA_SPI_MAX_FREQ 52000000 + +struct spi_regs { + u32 command; /* SLINK_COMMAND_0 register */ + u32 command2; /* SLINK_COMMAND2_0 reg */ + u32 status; /* SLINK_STATUS_0 register */ + u32 reserved; /* Reserved offset 0C */ + u32 mas_data; /* SLINK_MAS_DATA_0 reg */ + u32 slav_data; /* SLINK_SLAVE_DATA_0 reg */ + u32 dma_ctl; /* SLINK_DMA_CTL_0 register */ + u32 status2; /* SLINK_STATUS2_0 reg */ + u32 rsvd[56]; /* 0x20 to 0xFF reserved */ + u32 tx_fifo; /* SLINK_TX_FIFO_0 reg off 100h */ + u32 rsvd2[31]; /* 0x104 to 0x17F reserved */ + u32 rx_fifo; /* SLINK_RX_FIFO_0 reg off 180h */ +}; + struct tegra_spi_ctrl { - struct slink_tegra *regs; + struct spi_regs *regs; unsigned int freq; unsigned int mode; int periph_id; @@ -53,7 +107,7 @@ static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave) return container_of(slave, struct tegra_spi_slave, slave); } -int spi_cs_is_valid(unsigned int bus, unsigned int cs) +int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs) { if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid) return 0; @@ -61,7 +115,7 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) return 1; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, +struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int mode) { struct tegra_spi_slave *spi; @@ -81,13 +135,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; } - spi = malloc(sizeof(struct tegra_spi_slave)); + spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs); if (!spi) { printf("SPI error: malloc of SPI structure failed\n"); return NULL; } - spi->slave.bus = bus; - spi->slave.cs = cs; spi->ctrl = &spi_ctrls[bus]; if (!spi->ctrl) { printf("SPI error: could not find controller for bus %d\n", @@ -105,32 +157,26 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return &spi->slave; } -void spi_free_slave(struct spi_slave *slave) +void tegra30_spi_free_slave(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); free(spi); } -void spi_init(void) +int tegra30_spi_init(int *node_list, int count) { struct tegra_spi_ctrl *ctrl; int i; -#ifdef CONFIG_OF_CONTROL int node = 0; - int count; - int node_list[CONFIG_TEGRA_SLINK_CTRLS]; + int found = 0; - count = fdtdec_find_aliases_for_id(gd->fdt_blob, "spi", - COMPAT_NVIDIA_TEGRA20_SLINK, - node_list, - CONFIG_TEGRA_SLINK_CTRLS); for (i = 0; i < count; i++) { ctrl = &spi_ctrls[i]; node = node_list[i]; - ctrl->regs = (struct slink_tegra *)fdtdec_get_addr(gd->fdt_blob, - node, "reg"); + ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob, + node, "reg"); if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) { debug("%s: no slink register found\n", __func__); continue; @@ -148,44 +194,18 @@ void spi_init(void) continue; } ctrl->valid = 1; + found = 1; debug("%s: found controller at %p, freq = %u, periph_id = %d\n", __func__, ctrl->regs, ctrl->freq, ctrl->periph_id); } -#else - for (i = 0; i < CONFIG_TEGRA_SLINK_CTRLS; i++) { - ctrl = &spi_ctrls[i]; - u32 base_regs[] = { - NV_PA_SLINK1_BASE, - NV_PA_SLINK2_BASE, - NV_PA_SLINK3_BASE, - NV_PA_SLINK4_BASE, - NV_PA_SLINK5_BASE, - NV_PA_SLINK6_BASE, - }; - int periph_ids[] = { - PERIPH_ID_SBC1, - PERIPH_ID_SBC2, - PERIPH_ID_SBC3, - PERIPH_ID_SBC4, - PERIPH_ID_SBC5, - PERIPH_ID_SBC6, - }; - ctrl->regs = (struct slink_tegra *)base_regs[i]; - ctrl->freq = TEGRA_SPI_MAX_FREQ; - ctrl->periph_id = periph_ids[i]; - ctrl->valid = 1; - - debug("%s: found controller at %p, freq = %u, periph_id = %d\n", - __func__, ctrl->regs, ctrl->freq, ctrl->periph_id); - } -#endif + return !found; } -int spi_claim_bus(struct spi_slave *slave) +int tegra30_spi_claim_bus(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct slink_tegra *regs = spi->ctrl->regs; + struct spi_regs *regs = spi->ctrl->regs; u32 reg; /* Change SPI clock to correct frequency, PLLP_OUT0 source */ @@ -207,33 +227,29 @@ int spi_claim_bus(struct spi_slave *slave) return 0; } -void spi_release_bus(struct spi_slave *slave) -{ -} - -void spi_cs_activate(struct spi_slave *slave) +void tegra30_spi_cs_activate(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct slink_tegra *regs = spi->ctrl->regs; + struct spi_regs *regs = spi->ctrl->regs; /* CS is negated on Tegra, so drive a 1 to get a 0 */ setbits_le32(®s->command, SLINK_CMD_CS_VAL); } -void spi_cs_deactivate(struct spi_slave *slave) +void tegra30_spi_cs_deactivate(struct spi_slave *slave) { struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct slink_tegra *regs = spi->ctrl->regs; + struct spi_regs *regs = spi->ctrl->regs; /* CS is negated on Tegra, so drive a 0 to get a 1 */ clrbits_le32(®s->command, SLINK_CMD_CS_VAL); } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, +int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, void *data_in, unsigned long flags) { struct tegra_spi_slave *spi = to_tegra_spi(slave); - struct slink_tegra *regs = spi->ctrl->regs; + struct spi_regs *regs = spi->ctrl->regs; u32 reg, tmpdout, tmpdin = 0; const u8 *dout = data_out; u8 *din = data_in; diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index db01cc2..a82b056 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -85,14 +85,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; } - xilspi = malloc(sizeof(*xilspi)); + xilspi = spi_alloc_slave(struct xilinx_spi_slave, bus, cs); if (!xilspi) { printf("XILSPI error: %s: malloc of SPI structure failed\n", __func__); return NULL; } - xilspi->slave.bus = bus; - xilspi->slave.cs = cs; xilspi->regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus]; xilspi->freq = max_hz; xilspi->mode = mode; diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c index dc5ca65..fd8f8a7 100644 --- a/drivers/usb/eth/smsc95xx.c +++ b/drivers/usb/eth/smsc95xx.c @@ -265,10 +265,6 @@ static int smsc95xx_eeprom_confirm_not_busy(struct ueth_data *dev) do { smsc95xx_read_reg(dev, E2P_CMD, &val); - if (!(val & E2P_CMD_LOADED_)) { - debug("No EEPROM present\n"); - return -1; - } if (!(val & E2P_CMD_BUSY_)) return 0; udelay(40); diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 040eaba..e545b6b 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -25,15 +25,21 @@ include $(TOPDIR)/config.mk LIB := $(obj)libusb_gadget.o +# if defined(CONFIG_USB_GADGET) || defined(CONFIG_USB_ETHER) +# Everytime you forget how crufty makefiles can get things like +# this remind you... +ifneq (,$(CONFIG_USB_GADGET)$(CONFIG_USB_ETHER)) +COBJS-y += epautoconf.o config.o usbstring.o +endif + # new USB gadget layer dependencies ifdef CONFIG_USB_GADGET -COBJS-y += epautoconf.o config.o usbstring.o COBJS-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o COBJS-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o COBJS-$(CONFIG_DFU_FUNCTION) += f_dfu.o endif ifdef CONFIG_USB_ETHER -COBJS-y += ether.o epautoconf.o config.o usbstring.o +COBJS-y += ether.o COBJS-$(CONFIG_USB_ETH_RNDIS) += rndis.o COBJS-$(CONFIG_MV_UDC) += mv_udc.o COBJS-$(CONFIG_CPU_PXA25X) += pxa25x_udc.o diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index ebb5131..2c5600e 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -859,6 +859,25 @@ unknown: if (&f->list == &cdev->config->functions) f = NULL; break; + /* + * dfu-util (version 0.5) sets bmRequestType.Receipent = Device + * for non-standard request (w_value = 0x21, + * bRequest = GET_DESCRIPTOR in this case). + * When only one interface is registered (as it is done now), + * then this request shall be handled as it was requested for + * interface. + * + * In the below code it is checked if only one interface is + * present and proper function for it is extracted. Due to that + * function's setup (f->setup) is called to handle this + * special non-standard request. + */ + case USB_RECIP_DEVICE: + debug("cdev->config->next_interface_id: %d intf: %d\n", + cdev->config->next_interface_id, intf); + if (cdev->config->next_interface_id == 1) + f = cdev->config->interface[intf]; + break; } if (f && f->setup) diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c index 10547e3..a322ae5 100644 --- a/drivers/usb/gadget/f_dfu.c +++ b/drivers/usb/gadget/f_dfu.c @@ -164,6 +164,9 @@ static void handle_getstatus(struct usb_request *req) /* send status response */ dstat->bStatus = f_dfu->dfu_status; + dstat->bwPollTimeout[0] = 0; + dstat->bwPollTimeout[1] = 0; + dstat->bwPollTimeout[2] = 0; dstat->bState = f_dfu->dfu_state; dstat->iString = 0; } diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c new file mode 100644 index 0000000..c28866f --- /dev/null +++ b/drivers/usb/gadget/f_mass_storage.c @@ -0,0 +1,2793 @@ +/* + * f_mass_storage.c -- Mass Storage USB Composite Function + * + * Copyright (C) 2003-2008 Alan Stern + * Copyright (C) 2009 Samsung Electronics + * Author: Michal Nazarewicz <m.nazarewicz@samsung.com> + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation, either version 2 of that License or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/* + * The Mass Storage Function acts as a USB Mass Storage device, + * appearing to the host as a disk drive or as a CD-ROM drive. In + * addition to providing an example of a genuinely useful composite + * function for a USB device, it also illustrates a technique of + * double-buffering for increased throughput. + * + * Function supports multiple logical units (LUNs). Backing storage + * for each LUN is provided by a regular file or a block device. + * Access for each LUN can be limited to read-only. Moreover, the + * function can indicate that LUN is removable and/or CD-ROM. (The + * later implies read-only access.) + * + * MSF is configured by specifying a fsg_config structure. It has the + * following fields: + * + * nluns Number of LUNs function have (anywhere from 1 + * to FSG_MAX_LUNS which is 8). + * luns An array of LUN configuration values. This + * should be filled for each LUN that + * function will include (ie. for "nluns" + * LUNs). Each element of the array has + * the following fields: + * ->filename The path to the backing file for the LUN. + * Required if LUN is not marked as + * removable. + * ->ro Flag specifying access to the LUN shall be + * read-only. This is implied if CD-ROM + * emulation is enabled as well as when + * it was impossible to open "filename" + * in R/W mode. + * ->removable Flag specifying that LUN shall be indicated as + * being removable. + * ->cdrom Flag specifying that LUN shall be reported as + * being a CD-ROM. + * + * lun_name_format A printf-like format for names of the LUN + * devices. This determines how the + * directory in sysfs will be named. + * Unless you are using several MSFs in + * a single gadget (as opposed to single + * MSF in many configurations) you may + * leave it as NULL (in which case + * "lun%d" will be used). In the format + * you can use "%d" to index LUNs for + * MSF's with more than one LUN. (Beware + * that there is only one integer given + * as an argument for the format and + * specifying invalid format may cause + * unspecified behaviour.) + * thread_name Name of the kernel thread process used by the + * MSF. You can safely set it to NULL + * (in which case default "file-storage" + * will be used). + * + * vendor_name + * product_name + * release Information used as a reply to INQUIRY + * request. To use default set to NULL, + * NULL, 0xffff respectively. The first + * field should be 8 and the second 16 + * characters or less. + * + * can_stall Set to permit function to halt bulk endpoints. + * Disabled on some USB devices known not + * to work correctly. You should set it + * to true. + * + * If "removable" is not set for a LUN then a backing file must be + * specified. If it is set, then NULL filename means the LUN's medium + * is not loaded (an empty string as "filename" in the fsg_config + * structure causes error). The CD-ROM emulation includes a single + * data track and no audio tracks; hence there need be only one + * backing file per LUN. Note also that the CD-ROM block length is + * set to 512 rather than the more common value 2048. + * + * + * MSF includes support for module parameters. If gadget using it + * decides to use it, the following module parameters will be + * available: + * + * file=filename[,filename...] + * Names of the files or block devices used for + * backing storage. + * ro=b[,b...] Default false, boolean for read-only access. + * removable=b[,b...] + * Default true, boolean for removable media. + * cdrom=b[,b...] Default false, boolean for whether to emulate + * a CD-ROM drive. + * luns=N Default N = number of filenames, number of + * LUNs to support. + * stall Default determined according to the type of + * USB device controller (usually true), + * boolean to permit the driver to halt + * bulk endpoints. + * + * The module parameters may be prefixed with some string. You need + * to consult gadget's documentation or source to verify whether it is + * using those module parameters and if it does what are the prefixes + * (look for FSG_MODULE_PARAMETERS() macro usage, what's inside it is + * the prefix). + * + * + * Requirements are modest; only a bulk-in and a bulk-out endpoint are + * needed. The memory requirement amounts to two 16K buffers, size + * configurable by a parameter. Support is included for both + * full-speed and high-speed operation. + * + * Note that the driver is slightly non-portable in that it assumes a + * single memory/DMA buffer will be useable for bulk-in, bulk-out, and + * interrupt-in endpoints. With most device controllers this isn't an + * issue, but there may be some with hardware restrictions that prevent + * a buffer from being used by more than one endpoint. + * + * + * The pathnames of the backing files and the ro settings are + * available in the attribute files "file" and "ro" in the lun<n> (or + * to be more precise in a directory which name comes from + * "lun_name_format" option!) subdirectory of the gadget's sysfs + * directory. If the "removable" option is set, writing to these + * files will simulate ejecting/loading the medium (writing an empty + * line means eject) and adjusting a write-enable tab. Changes to the + * ro setting are not allowed when the medium is loaded or if CD-ROM + * emulation is being used. + * + * When a LUN receive an "eject" SCSI request (Start/Stop Unit), + * if the LUN is removable, the backing file is released to simulate + * ejection. + * + * + * This function is heavily based on "File-backed Storage Gadget" by + * Alan Stern which in turn is heavily based on "Gadget Zero" by David + * Brownell. The driver's SCSI command interface was based on the + * "Information technology - Small Computer System Interface - 2" + * document from X3T9.2 Project 375D, Revision 10L, 7-SEP-93, + * available at <http://www.t10.org/ftp/t10/drafts/s2/s2-r10l.pdf>. + * The single exception is opcode 0x23 (READ FORMAT CAPACITIES), which + * was based on the "Universal Serial Bus Mass Storage Class UFI + * Command Specification" document, Revision 1.0, December 14, 1998, + * available at + * <http://www.usb.org/developers/devclass_docs/usbmass-ufi10.pdf>. + */ + + +/* + * Driver Design + * + * The MSF is fairly straightforward. There is a main kernel + * thread that handles most of the work. Interrupt routines field + * callbacks from the controller driver: bulk- and interrupt-request + * completion notifications, endpoint-0 events, and disconnect events. + * Completion events are passed to the main thread by wakeup calls. Many + * ep0 requests are handled at interrupt time, but SetInterface, + * SetConfiguration, and device reset requests are forwarded to the + * thread in the form of "exceptions" using SIGUSR1 signals (since they + * should interrupt any ongoing file I/O operations). + * + * The thread's main routine implements the standard command/data/status + * parts of a SCSI interaction. It and its subroutines are full of tests + * for pending signals/exceptions -- all this polling is necessary since + * the kernel has no setjmp/longjmp equivalents. (Maybe this is an + * indication that the driver really wants to be running in userspace.) + * An important point is that so long as the thread is alive it keeps an + * open reference to the backing file. This will prevent unmounting + * the backing file's underlying filesystem and could cause problems + * during system shutdown, for example. To prevent such problems, the + * thread catches INT, TERM, and KILL signals and converts them into + * an EXIT exception. + * + * In normal operation the main thread is started during the gadget's + * fsg_bind() callback and stopped during fsg_unbind(). But it can + * also exit when it receives a signal, and there's no point leaving + * the gadget running when the thread is dead. At of this moment, MSF + * provides no way to deregister the gadget when thread dies -- maybe + * a callback functions is needed. + * + * To provide maximum throughput, the driver uses a circular pipeline of + * buffer heads (struct fsg_buffhd). In principle the pipeline can be + * arbitrarily long; in practice the benefits don't justify having more + * than 2 stages (i.e., double buffering). But it helps to think of the + * pipeline as being a long one. Each buffer head contains a bulk-in and + * a bulk-out request pointer (since the buffer can be used for both + * output and input -- directions always are given from the host's + * point of view) as well as a pointer to the buffer and various state + * variables. + * + * Use of the pipeline follows a simple protocol. There is a variable + * (fsg->next_buffhd_to_fill) that points to the next buffer head to use. + * At any time that buffer head may still be in use from an earlier + * request, so each buffer head has a state variable indicating whether + * it is EMPTY, FULL, or BUSY. Typical use involves waiting for the + * buffer head to be EMPTY, filling the buffer either by file I/O or by + * USB I/O (during which the buffer head is BUSY), and marking the buffer + * head FULL when the I/O is complete. Then the buffer will be emptied + * (again possibly by USB I/O, during which it is marked BUSY) and + * finally marked EMPTY again (possibly by a completion routine). + * + * A module parameter tells the driver to avoid stalling the bulk + * endpoints wherever the transport specification allows. This is + * necessary for some UDCs like the SuperH, which cannot reliably clear a + * halt on a bulk endpoint. However, under certain circumstances the + * Bulk-only specification requires a stall. In such cases the driver + * will halt the endpoint and set a flag indicating that it should clear + * the halt in software during the next device reset. Hopefully this + * will permit everything to work correctly. Furthermore, although the + * specification allows the bulk-out endpoint to halt when the host sends + * too much data, implementing this would cause an unavoidable race. + * The driver will always use the "no-stall" approach for OUT transfers. + * + * One subtle point concerns sending status-stage responses for ep0 + * requests. Some of these requests, such as device reset, can involve + * interrupting an ongoing file I/O operation, which might take an + * arbitrarily long time. During that delay the host might give up on + * the original ep0 request and issue a new one. When that happens the + * driver should not notify the host about completion of the original + * request, as the host will no longer be waiting for it. So the driver + * assigns to each ep0 request a unique tag, and it keeps track of the + * tag value of the request associated with a long-running exception + * (device-reset, interface-change, or configuration-change). When the + * exception handler is finished, the status-stage response is submitted + * only if the current ep0 request tag is equal to the exception request + * tag. Thus only the most recently received ep0 request will get a + * status-stage response. + * + * Warning: This driver source file is too long. It ought to be split up + * into a header file plus about 3 separate .c files, to handle the details + * of the Gadget, USB Mass Storage, and SCSI protocols. + */ + +/* #define VERBOSE_DEBUG */ +/* #define DUMP_MSGS */ + +#include <config.h> +#include <malloc.h> +#include <common.h> + +#include <linux/err.h> +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> +#include <usb_mass_storage.h> + +#include <asm/unaligned.h> +#include <linux/usb/gadget.h> +#include <linux/usb/gadget.h> +#include <linux/usb/composite.h> +#include <usb/lin_gadget_compat.h> + +/*------------------------------------------------------------------------*/ + +#define FSG_DRIVER_DESC "Mass Storage Function" +#define FSG_DRIVER_VERSION "2012/06/5" + +static const char fsg_string_interface[] = "Mass Storage"; + + +#define FSG_NO_INTR_EP 1 +#define FSG_NO_DEVICE_STRINGS 1 +#define FSG_NO_OTG 1 +#define FSG_NO_INTR_EP 1 + +#include "storage_common.c" + +/*-------------------------------------------------------------------------*/ + +#define GFP_ATOMIC ((gfp_t) 0) +#define PAGE_CACHE_SHIFT 12 +#define PAGE_CACHE_SIZE (1 << PAGE_CACHE_SHIFT) +#define kthread_create(...) __builtin_return_address(0) +#define wait_for_completion(...) do {} while (0) + +struct kref {int x; }; +struct completion {int x; }; + +inline void set_bit(int nr, volatile void *addr) +{ + int mask; + unsigned int *a = (unsigned int *) addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a |= mask; +} + +inline void clear_bit(int nr, volatile void *addr) +{ + int mask; + unsigned int *a = (unsigned int *) addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a &= ~mask; +} + +struct fsg_dev; +struct fsg_common; + +/* Data shared by all the FSG instances. */ +struct fsg_common { + struct usb_gadget *gadget; + struct fsg_dev *fsg, *new_fsg; + + struct usb_ep *ep0; /* Copy of gadget->ep0 */ + struct usb_request *ep0req; /* Copy of cdev->req */ + unsigned int ep0_req_tag; + + struct fsg_buffhd *next_buffhd_to_fill; + struct fsg_buffhd *next_buffhd_to_drain; + struct fsg_buffhd buffhds[FSG_NUM_BUFFERS]; + + int cmnd_size; + u8 cmnd[MAX_COMMAND_SIZE]; + + unsigned int nluns; + unsigned int lun; + struct fsg_lun luns[FSG_MAX_LUNS]; + + unsigned int bulk_out_maxpacket; + enum fsg_state state; /* For exception handling */ + unsigned int exception_req_tag; + + enum data_direction data_dir; + u32 data_size; + u32 data_size_from_cmnd; + u32 tag; + u32 residue; + u32 usb_amount_left; + + unsigned int can_stall:1; + unsigned int free_storage_on_release:1; + unsigned int phase_error:1; + unsigned int short_packet_received:1; + unsigned int bad_lun_okay:1; + unsigned int running:1; + + int thread_wakeup_needed; + struct completion thread_notifier; + struct task_struct *thread_task; + + /* Callback functions. */ + const struct fsg_operations *ops; + /* Gadget's private data. */ + void *private_data; + + const char *vendor_name; /* 8 characters or less */ + const char *product_name; /* 16 characters or less */ + u16 release; + + /* Vendor (8 chars), product (16 chars), release (4 + * hexadecimal digits) and NUL byte */ + char inquiry_string[8 + 16 + 4 + 1]; + + struct kref ref; +}; + +struct fsg_config { + unsigned nluns; + struct fsg_lun_config { + const char *filename; + char ro; + char removable; + char cdrom; + char nofua; + } luns[FSG_MAX_LUNS]; + + /* Callback functions. */ + const struct fsg_operations *ops; + /* Gadget's private data. */ + void *private_data; + + const char *vendor_name; /* 8 characters or less */ + const char *product_name; /* 16 characters or less */ + + char can_stall; +}; + +struct fsg_dev { + struct usb_function function; + struct usb_gadget *gadget; /* Copy of cdev->gadget */ + struct fsg_common *common; + + u16 interface_number; + + unsigned int bulk_in_enabled:1; + unsigned int bulk_out_enabled:1; + + unsigned long atomic_bitflags; +#define IGNORE_BULK_OUT 0 + + struct usb_ep *bulk_in; + struct usb_ep *bulk_out; +}; + + +static inline int __fsg_is_set(struct fsg_common *common, + const char *func, unsigned line) +{ + if (common->fsg) + return 1; + ERROR(common, "common->fsg is NULL in %s at %u\n", func, line); + WARN_ON(1); + return 0; +} + +#define fsg_is_set(common) likely(__fsg_is_set(common, __func__, __LINE__)) + + +static inline struct fsg_dev *fsg_from_func(struct usb_function *f) +{ + return container_of(f, struct fsg_dev, function); +} + + +typedef void (*fsg_routine_t)(struct fsg_dev *); + +static int exception_in_progress(struct fsg_common *common) +{ + return common->state > FSG_STATE_IDLE; +} + +/* Make bulk-out requests be divisible by the maxpacket size */ +static void set_bulk_out_req_length(struct fsg_common *common, + struct fsg_buffhd *bh, unsigned int length) +{ + unsigned int rem; + + bh->bulk_out_intended_length = length; + rem = length % common->bulk_out_maxpacket; + if (rem > 0) + length += common->bulk_out_maxpacket - rem; + bh->outreq->length = length; +} + +/*-------------------------------------------------------------------------*/ + +struct ums_board_info *ums_info; +struct fsg_common *the_fsg_common; + +static int fsg_set_halt(struct fsg_dev *fsg, struct usb_ep *ep) +{ + const char *name; + + if (ep == fsg->bulk_in) + name = "bulk-in"; + else if (ep == fsg->bulk_out) + name = "bulk-out"; + else + name = ep->name; + DBG(fsg, "%s set halt\n", name); + return usb_ep_set_halt(ep); +} + +/*-------------------------------------------------------------------------*/ + +/* These routines may be called in process context or in_irq */ + +/* Caller must hold fsg->lock */ +static void wakeup_thread(struct fsg_common *common) +{ + common->thread_wakeup_needed = 1; +} + +static void raise_exception(struct fsg_common *common, enum fsg_state new_state) +{ + /* Do nothing if a higher-priority exception is already in progress. + * If a lower-or-equal priority exception is in progress, preempt it + * and notify the main thread by sending it a signal. */ + if (common->state <= new_state) { + common->exception_req_tag = common->ep0_req_tag; + common->state = new_state; + common->thread_wakeup_needed = 1; + } +} + +/*-------------------------------------------------------------------------*/ + +static int ep0_queue(struct fsg_common *common) +{ + int rc; + + rc = usb_ep_queue(common->ep0, common->ep0req, GFP_ATOMIC); + common->ep0->driver_data = common; + if (rc != 0 && rc != -ESHUTDOWN) { + /* We can't do much more than wait for a reset */ + WARNING(common, "error in submission: %s --> %d\n", + common->ep0->name, rc); + } + return rc; +} + +/*-------------------------------------------------------------------------*/ + +/* Bulk and interrupt endpoint completion handlers. + * These always run in_irq. */ + +static void bulk_in_complete(struct usb_ep *ep, struct usb_request *req) +{ + struct fsg_common *common = ep->driver_data; + struct fsg_buffhd *bh = req->context; + + if (req->status || req->actual != req->length) + DBG(common, "%s --> %d, %u/%u\n", __func__, + req->status, req->actual, req->length); + if (req->status == -ECONNRESET) /* Request was cancelled */ + usb_ep_fifo_flush(ep); + + /* Hold the lock while we update the request and buffer states */ + bh->inreq_busy = 0; + bh->state = BUF_STATE_EMPTY; + wakeup_thread(common); +} + +static void bulk_out_complete(struct usb_ep *ep, struct usb_request *req) +{ + struct fsg_common *common = ep->driver_data; + struct fsg_buffhd *bh = req->context; + + dump_msg(common, "bulk-out", req->buf, req->actual); + if (req->status || req->actual != bh->bulk_out_intended_length) + DBG(common, "%s --> %d, %u/%u\n", __func__, + req->status, req->actual, + bh->bulk_out_intended_length); + if (req->status == -ECONNRESET) /* Request was cancelled */ + usb_ep_fifo_flush(ep); + + /* Hold the lock while we update the request and buffer states */ + bh->outreq_busy = 0; + bh->state = BUF_STATE_FULL; + wakeup_thread(common); +} + +/*-------------------------------------------------------------------------*/ + +/* Ep0 class-specific handlers. These always run in_irq. */ + +static int fsg_setup(struct usb_function *f, + const struct usb_ctrlrequest *ctrl) +{ + struct fsg_dev *fsg = fsg_from_func(f); + struct usb_request *req = fsg->common->ep0req; + u16 w_index = le16_to_cpu(ctrl->wIndex); + u16 w_value = le16_to_cpu(ctrl->wValue); + u16 w_length = le16_to_cpu(ctrl->wLength); + + if (!fsg_is_set(fsg->common)) + return -EOPNOTSUPP; + + switch (ctrl->bRequest) { + + case USB_BULK_RESET_REQUEST: + if (ctrl->bRequestType != + (USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) + break; + if (w_index != fsg->interface_number || w_value != 0) + return -EDOM; + + /* Raise an exception to stop the current operation + * and reinitialize our state. */ + DBG(fsg, "bulk reset request\n"); + raise_exception(fsg->common, FSG_STATE_RESET); + return DELAYED_STATUS; + + case USB_BULK_GET_MAX_LUN_REQUEST: + if (ctrl->bRequestType != + (USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE)) + break; + if (w_index != fsg->interface_number || w_value != 0) + return -EDOM; + VDBG(fsg, "get max LUN\n"); + *(u8 *) req->buf = fsg->common->nluns - 1; + + /* Respond with data/status */ + req->length = min((u16)1, w_length); + return ep0_queue(fsg->common); + } + + VDBG(fsg, + "unknown class-specific control req " + "%02x.%02x v%04x i%04x l%u\n", + ctrl->bRequestType, ctrl->bRequest, + le16_to_cpu(ctrl->wValue), w_index, w_length); + return -EOPNOTSUPP; +} + +/*-------------------------------------------------------------------------*/ + +/* All the following routines run in process context */ + +/* Use this for bulk or interrupt transfers, not ep0 */ +static void start_transfer(struct fsg_dev *fsg, struct usb_ep *ep, + struct usb_request *req, int *pbusy, + enum fsg_buffer_state *state) +{ + int rc; + + if (ep == fsg->bulk_in) + dump_msg(fsg, "bulk-in", req->buf, req->length); + + *pbusy = 1; + *state = BUF_STATE_BUSY; + rc = usb_ep_queue(ep, req, GFP_KERNEL); + if (rc != 0) { + *pbusy = 0; + *state = BUF_STATE_EMPTY; + + /* We can't do much more than wait for a reset */ + + /* Note: currently the net2280 driver fails zero-length + * submissions if DMA is enabled. */ + if (rc != -ESHUTDOWN && !(rc == -EOPNOTSUPP && + req->length == 0)) + WARNING(fsg, "error in submission: %s --> %d\n", + ep->name, rc); + } +} + +#define START_TRANSFER_OR(common, ep_name, req, pbusy, state) \ + if (fsg_is_set(common)) \ + start_transfer((common)->fsg, (common)->fsg->ep_name, \ + req, pbusy, state); \ + else + +#define START_TRANSFER(common, ep_name, req, pbusy, state) \ + START_TRANSFER_OR(common, ep_name, req, pbusy, state) (void)0 + +static void busy_indicator(void) +{ + static int state; + + switch (state) { + case 0: + puts("\r|"); break; + case 1: + puts("\r/"); break; + case 2: + puts("\r-"); break; + case 3: + puts("\r\\"); break; + case 4: + puts("\r|"); break; + case 5: + puts("\r/"); break; + case 6: + puts("\r-"); break; + case 7: + puts("\r\\"); break; + default: + state = 0; + } + if (state++ == 8) + state = 0; +} + +static int sleep_thread(struct fsg_common *common) +{ + int rc = 0; + int i = 0, k = 0; + + /* Wait until a signal arrives or we are woken up */ + for (;;) { + if (common->thread_wakeup_needed) + break; + + if (++i == 50000) { + busy_indicator(); + i = 0; + k++; + } + + usb_gadget_handle_interrupts(); + } + common->thread_wakeup_needed = 0; + return rc; +} + +/*-------------------------------------------------------------------------*/ + +static int do_read(struct fsg_common *common) +{ + struct fsg_lun *curlun = &common->luns[common->lun]; + u32 lba; + struct fsg_buffhd *bh; + int rc; + u32 amount_left; + loff_t file_offset; + unsigned int amount; + unsigned int partial_page; + ssize_t nread; + + /* Get the starting Logical Block Address and check that it's + * not too big */ + if (common->cmnd[0] == SC_READ_6) + lba = get_unaligned_be24(&common->cmnd[1]); + else { + lba = get_unaligned_be32(&common->cmnd[2]); + + /* We allow DPO (Disable Page Out = don't save data in the + * cache) and FUA (Force Unit Access = don't read from the + * cache), but we don't implement them. */ + if ((common->cmnd[1] & ~0x18) != 0) { + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + } + if (lba >= curlun->num_sectors) { + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + return -EINVAL; + } + file_offset = ((loff_t) lba) << 9; + + /* Carry out the file reads */ + amount_left = common->data_size_from_cmnd; + if (unlikely(amount_left == 0)) + return -EIO; /* No default reply */ + + for (;;) { + + /* Figure out how much we need to read: + * Try to read the remaining amount. + * But don't read more than the buffer size. + * And don't try to read past the end of the file. + * Finally, if we're not at a page boundary, don't read past + * the next page. + * If this means reading 0 then we were asked to read past + * the end of file. */ + amount = min(amount_left, FSG_BUFLEN); + partial_page = file_offset & (PAGE_CACHE_SIZE - 1); + if (partial_page > 0) + amount = min(amount, (unsigned int) PAGE_CACHE_SIZE - + partial_page); + + /* Wait for the next buffer to become available */ + bh = common->next_buffhd_to_fill; + while (bh->state != BUF_STATE_EMPTY) { + rc = sleep_thread(common); + if (rc) + return rc; + } + + /* If we were asked to read past the end of file, + * end with an empty buffer. */ + if (amount == 0) { + curlun->sense_data = + SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + curlun->info_valid = 1; + bh->inreq->length = 0; + bh->state = BUF_STATE_FULL; + break; + } + + /* Perform the read */ + nread = 0; + rc = ums_info->read_sector(&(ums_info->ums_dev), + file_offset / SECTOR_SIZE, + amount / SECTOR_SIZE, + (char __user *)bh->buf); + if (rc) + return -EIO; + nread = amount; + + VLDBG(curlun, "file read %u @ %llu -> %d\n", amount, + (unsigned long long) file_offset, + (int) nread); + + if (nread < 0) { + LDBG(curlun, "error in file read: %d\n", + (int) nread); + nread = 0; + } else if (nread < amount) { + LDBG(curlun, "partial file read: %d/%u\n", + (int) nread, amount); + nread -= (nread & 511); /* Round down to a block */ + } + file_offset += nread; + amount_left -= nread; + common->residue -= nread; + bh->inreq->length = nread; + bh->state = BUF_STATE_FULL; + + /* If an error occurred, report it and its position */ + if (nread < amount) { + curlun->sense_data = SS_UNRECOVERED_READ_ERROR; + curlun->info_valid = 1; + break; + } + + if (amount_left == 0) + break; /* No more left to read */ + + /* Send this buffer and go read some more */ + bh->inreq->zero = 0; + START_TRANSFER_OR(common, bulk_in, bh->inreq, + &bh->inreq_busy, &bh->state) + /* Don't know what to do if + * common->fsg is NULL */ + return -EIO; + common->next_buffhd_to_fill = bh->next; + } + + return -EIO; /* No default reply */ +} + +/*-------------------------------------------------------------------------*/ + +static int do_write(struct fsg_common *common) +{ + struct fsg_lun *curlun = &common->luns[common->lun]; + u32 lba; + struct fsg_buffhd *bh; + int get_some_more; + u32 amount_left_to_req, amount_left_to_write; + loff_t usb_offset, file_offset; + unsigned int amount; + unsigned int partial_page; + ssize_t nwritten; + int rc; + + if (curlun->ro) { + curlun->sense_data = SS_WRITE_PROTECTED; + return -EINVAL; + } + + /* Get the starting Logical Block Address and check that it's + * not too big */ + if (common->cmnd[0] == SC_WRITE_6) + lba = get_unaligned_be24(&common->cmnd[1]); + else { + lba = get_unaligned_be32(&common->cmnd[2]); + + /* We allow DPO (Disable Page Out = don't save data in the + * cache) and FUA (Force Unit Access = write directly to the + * medium). We don't implement DPO; we implement FUA by + * performing synchronous output. */ + if (common->cmnd[1] & ~0x18) { + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + } + if (lba >= curlun->num_sectors) { + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + return -EINVAL; + } + + /* Carry out the file writes */ + get_some_more = 1; + file_offset = usb_offset = ((loff_t) lba) << 9; + amount_left_to_req = common->data_size_from_cmnd; + amount_left_to_write = common->data_size_from_cmnd; + + while (amount_left_to_write > 0) { + + /* Queue a request for more data from the host */ + bh = common->next_buffhd_to_fill; + if (bh->state == BUF_STATE_EMPTY && get_some_more) { + + /* Figure out how much we want to get: + * Try to get the remaining amount. + * But don't get more than the buffer size. + * And don't try to go past the end of the file. + * If we're not at a page boundary, + * don't go past the next page. + * If this means getting 0, then we were asked + * to write past the end of file. + * Finally, round down to a block boundary. */ + amount = min(amount_left_to_req, FSG_BUFLEN); + partial_page = usb_offset & (PAGE_CACHE_SIZE - 1); + if (partial_page > 0) + amount = min(amount, + (unsigned int) PAGE_CACHE_SIZE - partial_page); + + if (amount == 0) { + get_some_more = 0; + curlun->sense_data = + SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + curlun->info_valid = 1; + continue; + } + amount -= (amount & 511); + if (amount == 0) { + + /* Why were we were asked to transfer a + * partial block? */ + get_some_more = 0; + continue; + } + + /* Get the next buffer */ + usb_offset += amount; + common->usb_amount_left -= amount; + amount_left_to_req -= amount; + if (amount_left_to_req == 0) + get_some_more = 0; + + /* amount is always divisible by 512, hence by + * the bulk-out maxpacket size */ + bh->outreq->length = amount; + bh->bulk_out_intended_length = amount; + bh->outreq->short_not_ok = 1; + START_TRANSFER_OR(common, bulk_out, bh->outreq, + &bh->outreq_busy, &bh->state) + /* Don't know what to do if + * common->fsg is NULL */ + return -EIO; + common->next_buffhd_to_fill = bh->next; + continue; + } + + /* Write the received data to the backing file */ + bh = common->next_buffhd_to_drain; + if (bh->state == BUF_STATE_EMPTY && !get_some_more) + break; /* We stopped early */ + if (bh->state == BUF_STATE_FULL) { + common->next_buffhd_to_drain = bh->next; + bh->state = BUF_STATE_EMPTY; + + /* Did something go wrong with the transfer? */ + if (bh->outreq->status != 0) { + curlun->sense_data = SS_COMMUNICATION_FAILURE; + curlun->info_valid = 1; + break; + } + + amount = bh->outreq->actual; + + /* Perform the write */ + rc = ums_info->write_sector(&(ums_info->ums_dev), + file_offset / SECTOR_SIZE, + amount / SECTOR_SIZE, + (char __user *)bh->buf); + if (rc) + return -EIO; + nwritten = amount; + + VLDBG(curlun, "file write %u @ %llu -> %d\n", amount, + (unsigned long long) file_offset, + (int) nwritten); + + if (nwritten < 0) { + LDBG(curlun, "error in file write: %d\n", + (int) nwritten); + nwritten = 0; + } else if (nwritten < amount) { + LDBG(curlun, "partial file write: %d/%u\n", + (int) nwritten, amount); + nwritten -= (nwritten & 511); + /* Round down to a block */ + } + file_offset += nwritten; + amount_left_to_write -= nwritten; + common->residue -= nwritten; + + /* If an error occurred, report it and its position */ + if (nwritten < amount) { + curlun->sense_data = SS_WRITE_ERROR; + curlun->info_valid = 1; + break; + } + + /* Did the host decide to stop early? */ + if (bh->outreq->actual != bh->outreq->length) { + common->short_packet_received = 1; + break; + } + continue; + } + + /* Wait for something to happen */ + rc = sleep_thread(common); + if (rc) + return rc; + } + + return -EIO; /* No default reply */ +} + +/*-------------------------------------------------------------------------*/ + +static int do_synchronize_cache(struct fsg_common *common) +{ + return 0; +} + +/*-------------------------------------------------------------------------*/ + +static int do_verify(struct fsg_common *common) +{ + struct fsg_lun *curlun = &common->luns[common->lun]; + u32 lba; + u32 verification_length; + struct fsg_buffhd *bh = common->next_buffhd_to_fill; + loff_t file_offset; + u32 amount_left; + unsigned int amount; + ssize_t nread; + int rc; + + /* Get the starting Logical Block Address and check that it's + * not too big */ + lba = get_unaligned_be32(&common->cmnd[2]); + if (lba >= curlun->num_sectors) { + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + return -EINVAL; + } + + /* We allow DPO (Disable Page Out = don't save data in the + * cache) but we don't implement it. */ + if (common->cmnd[1] & ~0x10) { + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + + verification_length = get_unaligned_be16(&common->cmnd[7]); + if (unlikely(verification_length == 0)) + return -EIO; /* No default reply */ + + /* Prepare to carry out the file verify */ + amount_left = verification_length << 9; + file_offset = ((loff_t) lba) << 9; + + /* Write out all the dirty buffers before invalidating them */ + + /* Just try to read the requested blocks */ + while (amount_left > 0) { + + /* Figure out how much we need to read: + * Try to read the remaining amount, but not more than + * the buffer size. + * And don't try to read past the end of the file. + * If this means reading 0 then we were asked to read + * past the end of file. */ + amount = min(amount_left, FSG_BUFLEN); + if (amount == 0) { + curlun->sense_data = + SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + curlun->info_valid = 1; + break; + } + + /* Perform the read */ + nread = 0; + rc = ums_info->read_sector(&(ums_info->ums_dev), + file_offset / SECTOR_SIZE, + amount / SECTOR_SIZE, + (char __user *)bh->buf); + if (rc) + return -EIO; + nread = amount; + + VLDBG(curlun, "file read %u @ %llu -> %d\n", amount, + (unsigned long long) file_offset, + (int) nread); + if (nread < 0) { + LDBG(curlun, "error in file verify: %d\n", + (int) nread); + nread = 0; + } else if (nread < amount) { + LDBG(curlun, "partial file verify: %d/%u\n", + (int) nread, amount); + nread -= (nread & 511); /* Round down to a sector */ + } + if (nread == 0) { + curlun->sense_data = SS_UNRECOVERED_READ_ERROR; + curlun->info_valid = 1; + break; + } + file_offset += nread; + amount_left -= nread; + } + return 0; +} + +/*-------------------------------------------------------------------------*/ + +static int do_inquiry(struct fsg_common *common, struct fsg_buffhd *bh) +{ + struct fsg_lun *curlun = &common->luns[common->lun]; + static const char vendor_id[] = "Linux "; + u8 *buf = (u8 *) bh->buf; + + if (!curlun) { /* Unsupported LUNs are okay */ + common->bad_lun_okay = 1; + memset(buf, 0, 36); + buf[0] = 0x7f; /* Unsupported, no device-type */ + buf[4] = 31; /* Additional length */ + return 36; + } + + memset(buf, 0, 8); + buf[0] = TYPE_DISK; + buf[2] = 2; /* ANSI SCSI level 2 */ + buf[3] = 2; /* SCSI-2 INQUIRY data format */ + buf[4] = 31; /* Additional length */ + /* No special options */ + sprintf((char *) (buf + 8), "%-8s%-16s%04x", (char*) vendor_id , + ums_info->name, (u16) 0xffff); + + return 36; +} + + +static int do_request_sense(struct fsg_common *common, struct fsg_buffhd *bh) +{ + struct fsg_lun *curlun = &common->luns[common->lun]; + u8 *buf = (u8 *) bh->buf; + u32 sd, sdinfo; + int valid; + + /* + * From the SCSI-2 spec., section 7.9 (Unit attention condition): + * + * If a REQUEST SENSE command is received from an initiator + * with a pending unit attention condition (before the target + * generates the contingent allegiance condition), then the + * target shall either: + * a) report any pending sense data and preserve the unit + * attention condition on the logical unit, or, + * b) report the unit attention condition, may discard any + * pending sense data, and clear the unit attention + * condition on the logical unit for that initiator. + * + * FSG normally uses option a); enable this code to use option b). + */ +#if 0 + if (curlun && curlun->unit_attention_data != SS_NO_SENSE) { + curlun->sense_data = curlun->unit_attention_data; + curlun->unit_attention_data = SS_NO_SENSE; + } +#endif + + if (!curlun) { /* Unsupported LUNs are okay */ + common->bad_lun_okay = 1; + sd = SS_LOGICAL_UNIT_NOT_SUPPORTED; + sdinfo = 0; + valid = 0; + } else { + sd = curlun->sense_data; + valid = curlun->info_valid << 7; + curlun->sense_data = SS_NO_SENSE; + curlun->info_valid = 0; + } + + memset(buf, 0, 18); + buf[0] = valid | 0x70; /* Valid, current error */ + buf[2] = SK(sd); + put_unaligned_be32(sdinfo, &buf[3]); /* Sense information */ + buf[7] = 18 - 8; /* Additional sense length */ + buf[12] = ASC(sd); + buf[13] = ASCQ(sd); + return 18; +} + +static int do_read_capacity(struct fsg_common *common, struct fsg_buffhd *bh) +{ + struct fsg_lun *curlun = &common->luns[common->lun]; + u32 lba = get_unaligned_be32(&common->cmnd[2]); + int pmi = common->cmnd[8]; + u8 *buf = (u8 *) bh->buf; + + /* Check the PMI and LBA fields */ + if (pmi > 1 || (pmi == 0 && lba != 0)) { + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + + put_unaligned_be32(curlun->num_sectors - 1, &buf[0]); + /* Max logical block */ + put_unaligned_be32(512, &buf[4]); /* Block length */ + return 8; +} + +static int do_read_header(struct fsg_common *common, struct fsg_buffhd *bh) +{ + struct fsg_lun *curlun = &common->luns[common->lun]; + int msf = common->cmnd[1] & 0x02; + u32 lba = get_unaligned_be32(&common->cmnd[2]); + u8 *buf = (u8 *) bh->buf; + + if (common->cmnd[1] & ~0x02) { /* Mask away MSF */ + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + if (lba >= curlun->num_sectors) { + curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + return -EINVAL; + } + + memset(buf, 0, 8); + buf[0] = 0x01; /* 2048 bytes of user data, rest is EC */ + store_cdrom_address(&buf[4], msf, lba); + return 8; +} + + +static int do_read_toc(struct fsg_common *common, struct fsg_buffhd *bh) +{ + struct fsg_lun *curlun = &common->luns[common->lun]; + int msf = common->cmnd[1] & 0x02; + int start_track = common->cmnd[6]; + u8 *buf = (u8 *) bh->buf; + + if ((common->cmnd[1] & ~0x02) != 0 || /* Mask away MSF */ + start_track > 1) { + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + + memset(buf, 0, 20); + buf[1] = (20-2); /* TOC data length */ + buf[2] = 1; /* First track number */ + buf[3] = 1; /* Last track number */ + buf[5] = 0x16; /* Data track, copying allowed */ + buf[6] = 0x01; /* Only track is number 1 */ + store_cdrom_address(&buf[8], msf, 0); + + buf[13] = 0x16; /* Lead-out track is data */ + buf[14] = 0xAA; /* Lead-out track number */ + store_cdrom_address(&buf[16], msf, curlun->num_sectors); + + return 20; +} + +static int do_mode_sense(struct fsg_common *common, struct fsg_buffhd *bh) +{ + struct fsg_lun *curlun = &common->luns[common->lun]; + int mscmnd = common->cmnd[0]; + u8 *buf = (u8 *) bh->buf; + u8 *buf0 = buf; + int pc, page_code; + int changeable_values, all_pages; + int valid_page = 0; + int len, limit; + + if ((common->cmnd[1] & ~0x08) != 0) { /* Mask away DBD */ + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + pc = common->cmnd[2] >> 6; + page_code = common->cmnd[2] & 0x3f; + if (pc == 3) { + curlun->sense_data = SS_SAVING_PARAMETERS_NOT_SUPPORTED; + return -EINVAL; + } + changeable_values = (pc == 1); + all_pages = (page_code == 0x3f); + + /* Write the mode parameter header. Fixed values are: default + * medium type, no cache control (DPOFUA), and no block descriptors. + * The only variable value is the WriteProtect bit. We will fill in + * the mode data length later. */ + memset(buf, 0, 8); + if (mscmnd == SC_MODE_SENSE_6) { + buf[2] = (curlun->ro ? 0x80 : 0x00); /* WP, DPOFUA */ + buf += 4; + limit = 255; + } else { /* SC_MODE_SENSE_10 */ + buf[3] = (curlun->ro ? 0x80 : 0x00); /* WP, DPOFUA */ + buf += 8; + limit = 65535; /* Should really be FSG_BUFLEN */ + } + + /* No block descriptors */ + + /* The mode pages, in numerical order. The only page we support + * is the Caching page. */ + if (page_code == 0x08 || all_pages) { + valid_page = 1; + buf[0] = 0x08; /* Page code */ + buf[1] = 10; /* Page length */ + memset(buf+2, 0, 10); /* None of the fields are changeable */ + + if (!changeable_values) { + buf[2] = 0x04; /* Write cache enable, */ + /* Read cache not disabled */ + /* No cache retention priorities */ + put_unaligned_be16(0xffff, &buf[4]); + /* Don't disable prefetch */ + /* Minimum prefetch = 0 */ + put_unaligned_be16(0xffff, &buf[8]); + /* Maximum prefetch */ + put_unaligned_be16(0xffff, &buf[10]); + /* Maximum prefetch ceiling */ + } + buf += 12; + } + + /* Check that a valid page was requested and the mode data length + * isn't too long. */ + len = buf - buf0; + if (!valid_page || len > limit) { + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + + /* Store the mode data length */ + if (mscmnd == SC_MODE_SENSE_6) + buf0[0] = len - 1; + else + put_unaligned_be16(len - 2, buf0); + return len; +} + + +static int do_start_stop(struct fsg_common *common) +{ + struct fsg_lun *curlun = &common->luns[common->lun]; + + if (!curlun) { + return -EINVAL; + } else if (!curlun->removable) { + curlun->sense_data = SS_INVALID_COMMAND; + return -EINVAL; + } + + return 0; +} + +static int do_prevent_allow(struct fsg_common *common) +{ + struct fsg_lun *curlun = &common->luns[common->lun]; + int prevent; + + if (!curlun->removable) { + curlun->sense_data = SS_INVALID_COMMAND; + return -EINVAL; + } + + prevent = common->cmnd[4] & 0x01; + if ((common->cmnd[4] & ~0x01) != 0) { /* Mask away Prevent */ + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + + if (curlun->prevent_medium_removal && !prevent) + fsg_lun_fsync_sub(curlun); + curlun->prevent_medium_removal = prevent; + return 0; +} + + +static int do_read_format_capacities(struct fsg_common *common, + struct fsg_buffhd *bh) +{ + struct fsg_lun *curlun = &common->luns[common->lun]; + u8 *buf = (u8 *) bh->buf; + + buf[0] = buf[1] = buf[2] = 0; + buf[3] = 8; /* Only the Current/Maximum Capacity Descriptor */ + buf += 4; + + put_unaligned_be32(curlun->num_sectors, &buf[0]); + /* Number of blocks */ + put_unaligned_be32(512, &buf[4]); /* Block length */ + buf[4] = 0x02; /* Current capacity */ + return 12; +} + + +static int do_mode_select(struct fsg_common *common, struct fsg_buffhd *bh) +{ + struct fsg_lun *curlun = &common->luns[common->lun]; + + /* We don't support MODE SELECT */ + if (curlun) + curlun->sense_data = SS_INVALID_COMMAND; + return -EINVAL; +} + + +/*-------------------------------------------------------------------------*/ + +static int halt_bulk_in_endpoint(struct fsg_dev *fsg) +{ + int rc; + + rc = fsg_set_halt(fsg, fsg->bulk_in); + if (rc == -EAGAIN) + VDBG(fsg, "delayed bulk-in endpoint halt\n"); + while (rc != 0) { + if (rc != -EAGAIN) { + WARNING(fsg, "usb_ep_set_halt -> %d\n", rc); + rc = 0; + break; + } + + rc = usb_ep_set_halt(fsg->bulk_in); + } + return rc; +} + +static int wedge_bulk_in_endpoint(struct fsg_dev *fsg) +{ + int rc; + + DBG(fsg, "bulk-in set wedge\n"); + rc = 0; /* usb_ep_set_wedge(fsg->bulk_in); */ + if (rc == -EAGAIN) + VDBG(fsg, "delayed bulk-in endpoint wedge\n"); + while (rc != 0) { + if (rc != -EAGAIN) { + WARNING(fsg, "usb_ep_set_wedge -> %d\n", rc); + rc = 0; + break; + } + } + return rc; +} + +static int pad_with_zeros(struct fsg_dev *fsg) +{ + struct fsg_buffhd *bh = fsg->common->next_buffhd_to_fill; + u32 nkeep = bh->inreq->length; + u32 nsend; + int rc; + + bh->state = BUF_STATE_EMPTY; /* For the first iteration */ + fsg->common->usb_amount_left = nkeep + fsg->common->residue; + while (fsg->common->usb_amount_left > 0) { + + /* Wait for the next buffer to be free */ + while (bh->state != BUF_STATE_EMPTY) { + rc = sleep_thread(fsg->common); + if (rc) + return rc; + } + + nsend = min(fsg->common->usb_amount_left, FSG_BUFLEN); + memset(bh->buf + nkeep, 0, nsend - nkeep); + bh->inreq->length = nsend; + bh->inreq->zero = 0; + start_transfer(fsg, fsg->bulk_in, bh->inreq, + &bh->inreq_busy, &bh->state); + bh = fsg->common->next_buffhd_to_fill = bh->next; + fsg->common->usb_amount_left -= nsend; + nkeep = 0; + } + return 0; +} + +static int throw_away_data(struct fsg_common *common) +{ + struct fsg_buffhd *bh; + u32 amount; + int rc; + + for (bh = common->next_buffhd_to_drain; + bh->state != BUF_STATE_EMPTY || common->usb_amount_left > 0; + bh = common->next_buffhd_to_drain) { + + /* Throw away the data in a filled buffer */ + if (bh->state == BUF_STATE_FULL) { + bh->state = BUF_STATE_EMPTY; + common->next_buffhd_to_drain = bh->next; + + /* A short packet or an error ends everything */ + if (bh->outreq->actual != bh->outreq->length || + bh->outreq->status != 0) { + raise_exception(common, + FSG_STATE_ABORT_BULK_OUT); + return -EINTR; + } + continue; + } + + /* Try to submit another request if we need one */ + bh = common->next_buffhd_to_fill; + if (bh->state == BUF_STATE_EMPTY + && common->usb_amount_left > 0) { + amount = min(common->usb_amount_left, FSG_BUFLEN); + + /* amount is always divisible by 512, hence by + * the bulk-out maxpacket size */ + bh->outreq->length = amount; + bh->bulk_out_intended_length = amount; + bh->outreq->short_not_ok = 1; + START_TRANSFER_OR(common, bulk_out, bh->outreq, + &bh->outreq_busy, &bh->state) + /* Don't know what to do if + * common->fsg is NULL */ + return -EIO; + common->next_buffhd_to_fill = bh->next; + common->usb_amount_left -= amount; + continue; + } + + /* Otherwise wait for something to happen */ + rc = sleep_thread(common); + if (rc) + return rc; + } + return 0; +} + + +static int finish_reply(struct fsg_common *common) +{ + struct fsg_buffhd *bh = common->next_buffhd_to_fill; + int rc = 0; + + switch (common->data_dir) { + case DATA_DIR_NONE: + break; /* Nothing to send */ + + /* If we don't know whether the host wants to read or write, + * this must be CB or CBI with an unknown command. We mustn't + * try to send or receive any data. So stall both bulk pipes + * if we can and wait for a reset. */ + case DATA_DIR_UNKNOWN: + if (!common->can_stall) { + /* Nothing */ + } else if (fsg_is_set(common)) { + fsg_set_halt(common->fsg, common->fsg->bulk_out); + rc = halt_bulk_in_endpoint(common->fsg); + } else { + /* Don't know what to do if common->fsg is NULL */ + rc = -EIO; + } + break; + + /* All but the last buffer of data must have already been sent */ + case DATA_DIR_TO_HOST: + if (common->data_size == 0) { + /* Nothing to send */ + + /* If there's no residue, simply send the last buffer */ + } else if (common->residue == 0) { + bh->inreq->zero = 0; + START_TRANSFER_OR(common, bulk_in, bh->inreq, + &bh->inreq_busy, &bh->state) + return -EIO; + common->next_buffhd_to_fill = bh->next; + + /* For Bulk-only, if we're allowed to stall then send the + * short packet and halt the bulk-in endpoint. If we can't + * stall, pad out the remaining data with 0's. */ + } else if (common->can_stall) { + bh->inreq->zero = 1; + START_TRANSFER_OR(common, bulk_in, bh->inreq, + &bh->inreq_busy, &bh->state) + /* Don't know what to do if + * common->fsg is NULL */ + rc = -EIO; + common->next_buffhd_to_fill = bh->next; + if (common->fsg) + rc = halt_bulk_in_endpoint(common->fsg); + } else if (fsg_is_set(common)) { + rc = pad_with_zeros(common->fsg); + } else { + /* Don't know what to do if common->fsg is NULL */ + rc = -EIO; + } + break; + + /* We have processed all we want from the data the host has sent. + * There may still be outstanding bulk-out requests. */ + case DATA_DIR_FROM_HOST: + if (common->residue == 0) { + /* Nothing to receive */ + + /* Did the host stop sending unexpectedly early? */ + } else if (common->short_packet_received) { + raise_exception(common, FSG_STATE_ABORT_BULK_OUT); + rc = -EINTR; + + /* We haven't processed all the incoming data. Even though + * we may be allowed to stall, doing so would cause a race. + * The controller may already have ACK'ed all the remaining + * bulk-out packets, in which case the host wouldn't see a + * STALL. Not realizing the endpoint was halted, it wouldn't + * clear the halt -- leading to problems later on. */ +#if 0 + } else if (common->can_stall) { + if (fsg_is_set(common)) + fsg_set_halt(common->fsg, + common->fsg->bulk_out); + raise_exception(common, FSG_STATE_ABORT_BULK_OUT); + rc = -EINTR; +#endif + + /* We can't stall. Read in the excess data and throw it + * all away. */ + } else { + rc = throw_away_data(common); + } + break; + } + return rc; +} + + +static int send_status(struct fsg_common *common) +{ + struct fsg_lun *curlun = &common->luns[common->lun]; + struct fsg_buffhd *bh; + struct bulk_cs_wrap *csw; + int rc; + u8 status = USB_STATUS_PASS; + u32 sd, sdinfo = 0; + + /* Wait for the next buffer to become available */ + bh = common->next_buffhd_to_fill; + while (bh->state != BUF_STATE_EMPTY) { + rc = sleep_thread(common); + if (rc) + return rc; + } + + if (curlun) + sd = curlun->sense_data; + else if (common->bad_lun_okay) + sd = SS_NO_SENSE; + else + sd = SS_LOGICAL_UNIT_NOT_SUPPORTED; + + if (common->phase_error) { + DBG(common, "sending phase-error status\n"); + status = USB_STATUS_PHASE_ERROR; + sd = SS_INVALID_COMMAND; + } else if (sd != SS_NO_SENSE) { + DBG(common, "sending command-failure status\n"); + status = USB_STATUS_FAIL; + VDBG(common, " sense data: SK x%02x, ASC x%02x, ASCQ x%02x;" + " info x%x\n", + SK(sd), ASC(sd), ASCQ(sd), sdinfo); + } + + /* Store and send the Bulk-only CSW */ + csw = (void *)bh->buf; + + csw->Signature = cpu_to_le32(USB_BULK_CS_SIG); + csw->Tag = common->tag; + csw->Residue = cpu_to_le32(common->residue); + csw->Status = status; + + bh->inreq->length = USB_BULK_CS_WRAP_LEN; + bh->inreq->zero = 0; + START_TRANSFER_OR(common, bulk_in, bh->inreq, + &bh->inreq_busy, &bh->state) + /* Don't know what to do if common->fsg is NULL */ + return -EIO; + + common->next_buffhd_to_fill = bh->next; + return 0; +} + + +/*-------------------------------------------------------------------------*/ + +/* Check whether the command is properly formed and whether its data size + * and direction agree with the values we already have. */ +static int check_command(struct fsg_common *common, int cmnd_size, + enum data_direction data_dir, unsigned int mask, + int needs_medium, const char *name) +{ + int i; + int lun = common->cmnd[1] >> 5; + static const char dirletter[4] = {'u', 'o', 'i', 'n'}; + char hdlen[20]; + struct fsg_lun *curlun; + + hdlen[0] = 0; + if (common->data_dir != DATA_DIR_UNKNOWN) + sprintf(hdlen, ", H%c=%u", dirletter[(int) common->data_dir], + common->data_size); + VDBG(common, "SCSI command: %s; Dc=%d, D%c=%u; Hc=%d%s\n", + name, cmnd_size, dirletter[(int) data_dir], + common->data_size_from_cmnd, common->cmnd_size, hdlen); + + /* We can't reply at all until we know the correct data direction + * and size. */ + if (common->data_size_from_cmnd == 0) + data_dir = DATA_DIR_NONE; + if (common->data_size < common->data_size_from_cmnd) { + /* Host data size < Device data size is a phase error. + * Carry out the command, but only transfer as much as + * we are allowed. */ + common->data_size_from_cmnd = common->data_size; + common->phase_error = 1; + } + common->residue = common->data_size; + common->usb_amount_left = common->data_size; + + /* Conflicting data directions is a phase error */ + if (common->data_dir != data_dir + && common->data_size_from_cmnd > 0) { + common->phase_error = 1; + return -EINVAL; + } + + /* Verify the length of the command itself */ + if (cmnd_size != common->cmnd_size) { + + /* Special case workaround: There are plenty of buggy SCSI + * implementations. Many have issues with cbw->Length + * field passing a wrong command size. For those cases we + * always try to work around the problem by using the length + * sent by the host side provided it is at least as large + * as the correct command length. + * Examples of such cases would be MS-Windows, which issues + * REQUEST SENSE with cbw->Length == 12 where it should + * be 6, and xbox360 issuing INQUIRY, TEST UNIT READY and + * REQUEST SENSE with cbw->Length == 10 where it should + * be 6 as well. + */ + if (cmnd_size <= common->cmnd_size) { + DBG(common, "%s is buggy! Expected length %d " + "but we got %d\n", name, + cmnd_size, common->cmnd_size); + cmnd_size = common->cmnd_size; + } else { + common->phase_error = 1; + return -EINVAL; + } + } + + /* Check that the LUN values are consistent */ + if (common->lun != lun) + DBG(common, "using LUN %d from CBW, not LUN %d from CDB\n", + common->lun, lun); + + /* Check the LUN */ + if (common->lun >= 0 && common->lun < common->nluns) { + curlun = &common->luns[common->lun]; + if (common->cmnd[0] != SC_REQUEST_SENSE) { + curlun->sense_data = SS_NO_SENSE; + curlun->info_valid = 0; + } + } else { + curlun = NULL; + common->bad_lun_okay = 0; + + /* INQUIRY and REQUEST SENSE commands are explicitly allowed + * to use unsupported LUNs; all others may not. */ + if (common->cmnd[0] != SC_INQUIRY && + common->cmnd[0] != SC_REQUEST_SENSE) { + DBG(common, "unsupported LUN %d\n", common->lun); + return -EINVAL; + } + } +#if 0 + /* If a unit attention condition exists, only INQUIRY and + * REQUEST SENSE commands are allowed; anything else must fail. */ + if (curlun && curlun->unit_attention_data != SS_NO_SENSE && + common->cmnd[0] != SC_INQUIRY && + common->cmnd[0] != SC_REQUEST_SENSE) { + curlun->sense_data = curlun->unit_attention_data; + curlun->unit_attention_data = SS_NO_SENSE; + return -EINVAL; + } +#endif + /* Check that only command bytes listed in the mask are non-zero */ + common->cmnd[1] &= 0x1f; /* Mask away the LUN */ + for (i = 1; i < cmnd_size; ++i) { + if (common->cmnd[i] && !(mask & (1 << i))) { + if (curlun) + curlun->sense_data = SS_INVALID_FIELD_IN_CDB; + return -EINVAL; + } + } + + return 0; +} + + +static int do_scsi_command(struct fsg_common *common) +{ + struct fsg_buffhd *bh; + int rc; + int reply = -EINVAL; + int i; + static char unknown[16]; + struct fsg_lun *curlun = &common->luns[common->lun]; + + dump_cdb(common); + + /* Wait for the next buffer to become available for data or status */ + bh = common->next_buffhd_to_fill; + common->next_buffhd_to_drain = bh; + while (bh->state != BUF_STATE_EMPTY) { + rc = sleep_thread(common); + if (rc) + return rc; + } + common->phase_error = 0; + common->short_packet_received = 0; + + down_read(&common->filesem); /* We're using the backing file */ + switch (common->cmnd[0]) { + + case SC_INQUIRY: + common->data_size_from_cmnd = common->cmnd[4]; + reply = check_command(common, 6, DATA_DIR_TO_HOST, + (1<<4), 0, + "INQUIRY"); + if (reply == 0) + reply = do_inquiry(common, bh); + break; + + case SC_MODE_SELECT_6: + common->data_size_from_cmnd = common->cmnd[4]; + reply = check_command(common, 6, DATA_DIR_FROM_HOST, + (1<<1) | (1<<4), 0, + "MODE SELECT(6)"); + if (reply == 0) + reply = do_mode_select(common, bh); + break; + + case SC_MODE_SELECT_10: + common->data_size_from_cmnd = + get_unaligned_be16(&common->cmnd[7]); + reply = check_command(common, 10, DATA_DIR_FROM_HOST, + (1<<1) | (3<<7), 0, + "MODE SELECT(10)"); + if (reply == 0) + reply = do_mode_select(common, bh); + break; + + case SC_MODE_SENSE_6: + common->data_size_from_cmnd = common->cmnd[4]; + reply = check_command(common, 6, DATA_DIR_TO_HOST, + (1<<1) | (1<<2) | (1<<4), 0, + "MODE SENSE(6)"); + if (reply == 0) + reply = do_mode_sense(common, bh); + break; + + case SC_MODE_SENSE_10: + common->data_size_from_cmnd = + get_unaligned_be16(&common->cmnd[7]); + reply = check_command(common, 10, DATA_DIR_TO_HOST, + (1<<1) | (1<<2) | (3<<7), 0, + "MODE SENSE(10)"); + if (reply == 0) + reply = do_mode_sense(common, bh); + break; + + case SC_PREVENT_ALLOW_MEDIUM_REMOVAL: + common->data_size_from_cmnd = 0; + reply = check_command(common, 6, DATA_DIR_NONE, + (1<<4), 0, + "PREVENT-ALLOW MEDIUM REMOVAL"); + if (reply == 0) + reply = do_prevent_allow(common); + break; + + case SC_READ_6: + i = common->cmnd[4]; + common->data_size_from_cmnd = (i == 0 ? 256 : i) << 9; + reply = check_command(common, 6, DATA_DIR_TO_HOST, + (7<<1) | (1<<4), 1, + "READ(6)"); + if (reply == 0) + reply = do_read(common); + break; + + case SC_READ_10: + common->data_size_from_cmnd = + get_unaligned_be16(&common->cmnd[7]) << 9; + reply = check_command(common, 10, DATA_DIR_TO_HOST, + (1<<1) | (0xf<<2) | (3<<7), 1, + "READ(10)"); + if (reply == 0) + reply = do_read(common); + break; + + case SC_READ_12: + common->data_size_from_cmnd = + get_unaligned_be32(&common->cmnd[6]) << 9; + reply = check_command(common, 12, DATA_DIR_TO_HOST, + (1<<1) | (0xf<<2) | (0xf<<6), 1, + "READ(12)"); + if (reply == 0) + reply = do_read(common); + break; + + case SC_READ_CAPACITY: + common->data_size_from_cmnd = 8; + reply = check_command(common, 10, DATA_DIR_TO_HOST, + (0xf<<2) | (1<<8), 1, + "READ CAPACITY"); + if (reply == 0) + reply = do_read_capacity(common, bh); + break; + + case SC_READ_HEADER: + if (!common->luns[common->lun].cdrom) + goto unknown_cmnd; + common->data_size_from_cmnd = + get_unaligned_be16(&common->cmnd[7]); + reply = check_command(common, 10, DATA_DIR_TO_HOST, + (3<<7) | (0x1f<<1), 1, + "READ HEADER"); + if (reply == 0) + reply = do_read_header(common, bh); + break; + + case SC_READ_TOC: + if (!common->luns[common->lun].cdrom) + goto unknown_cmnd; + common->data_size_from_cmnd = + get_unaligned_be16(&common->cmnd[7]); + reply = check_command(common, 10, DATA_DIR_TO_HOST, + (7<<6) | (1<<1), 1, + "READ TOC"); + if (reply == 0) + reply = do_read_toc(common, bh); + break; + + case SC_READ_FORMAT_CAPACITIES: + common->data_size_from_cmnd = + get_unaligned_be16(&common->cmnd[7]); + reply = check_command(common, 10, DATA_DIR_TO_HOST, + (3<<7), 1, + "READ FORMAT CAPACITIES"); + if (reply == 0) + reply = do_read_format_capacities(common, bh); + break; + + case SC_REQUEST_SENSE: + common->data_size_from_cmnd = common->cmnd[4]; + reply = check_command(common, 6, DATA_DIR_TO_HOST, + (1<<4), 0, + "REQUEST SENSE"); + if (reply == 0) + reply = do_request_sense(common, bh); + break; + + case SC_START_STOP_UNIT: + common->data_size_from_cmnd = 0; + reply = check_command(common, 6, DATA_DIR_NONE, + (1<<1) | (1<<4), 0, + "START-STOP UNIT"); + if (reply == 0) + reply = do_start_stop(common); + break; + + case SC_SYNCHRONIZE_CACHE: + common->data_size_from_cmnd = 0; + reply = check_command(common, 10, DATA_DIR_NONE, + (0xf<<2) | (3<<7), 1, + "SYNCHRONIZE CACHE"); + if (reply == 0) + reply = do_synchronize_cache(common); + break; + + case SC_TEST_UNIT_READY: + common->data_size_from_cmnd = 0; + reply = check_command(common, 6, DATA_DIR_NONE, + 0, 1, + "TEST UNIT READY"); + break; + + /* Although optional, this command is used by MS-Windows. We + * support a minimal version: BytChk must be 0. */ + case SC_VERIFY: + common->data_size_from_cmnd = 0; + reply = check_command(common, 10, DATA_DIR_NONE, + (1<<1) | (0xf<<2) | (3<<7), 1, + "VERIFY"); + if (reply == 0) + reply = do_verify(common); + break; + + case SC_WRITE_6: + i = common->cmnd[4]; + common->data_size_from_cmnd = (i == 0 ? 256 : i) << 9; + reply = check_command(common, 6, DATA_DIR_FROM_HOST, + (7<<1) | (1<<4), 1, + "WRITE(6)"); + if (reply == 0) + reply = do_write(common); + break; + + case SC_WRITE_10: + common->data_size_from_cmnd = + get_unaligned_be16(&common->cmnd[7]) << 9; + reply = check_command(common, 10, DATA_DIR_FROM_HOST, + (1<<1) | (0xf<<2) | (3<<7), 1, + "WRITE(10)"); + if (reply == 0) + reply = do_write(common); + break; + + case SC_WRITE_12: + common->data_size_from_cmnd = + get_unaligned_be32(&common->cmnd[6]) << 9; + reply = check_command(common, 12, DATA_DIR_FROM_HOST, + (1<<1) | (0xf<<2) | (0xf<<6), 1, + "WRITE(12)"); + if (reply == 0) + reply = do_write(common); + break; + + /* Some mandatory commands that we recognize but don't implement. + * They don't mean much in this setting. It's left as an exercise + * for anyone interested to implement RESERVE and RELEASE in terms + * of Posix locks. */ + case SC_FORMAT_UNIT: + case SC_RELEASE: + case SC_RESERVE: + case SC_SEND_DIAGNOSTIC: + /* Fall through */ + + default: +unknown_cmnd: + common->data_size_from_cmnd = 0; + sprintf(unknown, "Unknown x%02x", common->cmnd[0]); + reply = check_command(common, common->cmnd_size, + DATA_DIR_UNKNOWN, 0xff, 0, unknown); + if (reply == 0) { + curlun->sense_data = SS_INVALID_COMMAND; + reply = -EINVAL; + } + break; + } + up_read(&common->filesem); + + if (reply == -EINTR) + return -EINTR; + + /* Set up the single reply buffer for finish_reply() */ + if (reply == -EINVAL) + reply = 0; /* Error reply length */ + if (reply >= 0 && common->data_dir == DATA_DIR_TO_HOST) { + reply = min((u32) reply, common->data_size_from_cmnd); + bh->inreq->length = reply; + bh->state = BUF_STATE_FULL; + common->residue -= reply; + } /* Otherwise it's already set */ + + return 0; +} + +/*-------------------------------------------------------------------------*/ + +static int received_cbw(struct fsg_dev *fsg, struct fsg_buffhd *bh) +{ + struct usb_request *req = bh->outreq; + struct fsg_bulk_cb_wrap *cbw = req->buf; + struct fsg_common *common = fsg->common; + + /* Was this a real packet? Should it be ignored? */ + if (req->status || test_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags)) + return -EINVAL; + + /* Is the CBW valid? */ + if (req->actual != USB_BULK_CB_WRAP_LEN || + cbw->Signature != cpu_to_le32( + USB_BULK_CB_SIG)) { + DBG(fsg, "invalid CBW: len %u sig 0x%x\n", + req->actual, + le32_to_cpu(cbw->Signature)); + + /* The Bulk-only spec says we MUST stall the IN endpoint + * (6.6.1), so it's unavoidable. It also says we must + * retain this state until the next reset, but there's + * no way to tell the controller driver it should ignore + * Clear-Feature(HALT) requests. + * + * We aren't required to halt the OUT endpoint; instead + * we can simply accept and discard any data received + * until the next reset. */ + wedge_bulk_in_endpoint(fsg); + set_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags); + return -EINVAL; + } + + /* Is the CBW meaningful? */ + if (cbw->Lun >= FSG_MAX_LUNS || cbw->Flags & ~USB_BULK_IN_FLAG || + cbw->Length <= 0 || cbw->Length > MAX_COMMAND_SIZE) { + DBG(fsg, "non-meaningful CBW: lun = %u, flags = 0x%x, " + "cmdlen %u\n", + cbw->Lun, cbw->Flags, cbw->Length); + + /* We can do anything we want here, so let's stall the + * bulk pipes if we are allowed to. */ + if (common->can_stall) { + fsg_set_halt(fsg, fsg->bulk_out); + halt_bulk_in_endpoint(fsg); + } + return -EINVAL; + } + + /* Save the command for later */ + common->cmnd_size = cbw->Length; + memcpy(common->cmnd, cbw->CDB, common->cmnd_size); + if (cbw->Flags & USB_BULK_IN_FLAG) + common->data_dir = DATA_DIR_TO_HOST; + else + common->data_dir = DATA_DIR_FROM_HOST; + common->data_size = le32_to_cpu(cbw->DataTransferLength); + if (common->data_size == 0) + common->data_dir = DATA_DIR_NONE; + common->lun = cbw->Lun; + common->tag = cbw->Tag; + return 0; +} + + +static int get_next_command(struct fsg_common *common) +{ + struct fsg_buffhd *bh; + int rc = 0; + + /* Wait for the next buffer to become available */ + bh = common->next_buffhd_to_fill; + while (bh->state != BUF_STATE_EMPTY) { + rc = sleep_thread(common); + if (rc) + return rc; + } + + /* Queue a request to read a Bulk-only CBW */ + set_bulk_out_req_length(common, bh, USB_BULK_CB_WRAP_LEN); + bh->outreq->short_not_ok = 1; + START_TRANSFER_OR(common, bulk_out, bh->outreq, + &bh->outreq_busy, &bh->state) + /* Don't know what to do if common->fsg is NULL */ + return -EIO; + + /* We will drain the buffer in software, which means we + * can reuse it for the next filling. No need to advance + * next_buffhd_to_fill. */ + + /* Wait for the CBW to arrive */ + while (bh->state != BUF_STATE_FULL) { + rc = sleep_thread(common); + if (rc) + return rc; + } + + rc = fsg_is_set(common) ? received_cbw(common->fsg, bh) : -EIO; + bh->state = BUF_STATE_EMPTY; + + return rc; +} + + +/*-------------------------------------------------------------------------*/ + +static int enable_endpoint(struct fsg_common *common, struct usb_ep *ep, + const struct usb_endpoint_descriptor *d) +{ + int rc; + + ep->driver_data = common; + rc = usb_ep_enable(ep, d); + if (rc) + ERROR(common, "can't enable %s, result %d\n", ep->name, rc); + return rc; +} + +static int alloc_request(struct fsg_common *common, struct usb_ep *ep, + struct usb_request **preq) +{ + *preq = usb_ep_alloc_request(ep, GFP_ATOMIC); + if (*preq) + return 0; + ERROR(common, "can't allocate request for %s\n", ep->name); + return -ENOMEM; +} + +/* Reset interface setting and re-init endpoint state (toggle etc). */ +static int do_set_interface(struct fsg_common *common, struct fsg_dev *new_fsg) +{ + const struct usb_endpoint_descriptor *d; + struct fsg_dev *fsg; + int i, rc = 0; + + if (common->running) + DBG(common, "reset interface\n"); + +reset: + /* Deallocate the requests */ + if (common->fsg) { + fsg = common->fsg; + + for (i = 0; i < FSG_NUM_BUFFERS; ++i) { + struct fsg_buffhd *bh = &common->buffhds[i]; + + if (bh->inreq) { + usb_ep_free_request(fsg->bulk_in, bh->inreq); + bh->inreq = NULL; + } + if (bh->outreq) { + usb_ep_free_request(fsg->bulk_out, bh->outreq); + bh->outreq = NULL; + } + } + + /* Disable the endpoints */ + if (fsg->bulk_in_enabled) { + usb_ep_disable(fsg->bulk_in); + fsg->bulk_in_enabled = 0; + } + if (fsg->bulk_out_enabled) { + usb_ep_disable(fsg->bulk_out); + fsg->bulk_out_enabled = 0; + } + + common->fsg = NULL; + /* wake_up(&common->fsg_wait); */ + } + + common->running = 0; + if (!new_fsg || rc) + return rc; + + common->fsg = new_fsg; + fsg = common->fsg; + + /* Enable the endpoints */ + d = fsg_ep_desc(common->gadget, + &fsg_fs_bulk_in_desc, &fsg_hs_bulk_in_desc); + rc = enable_endpoint(common, fsg->bulk_in, d); + if (rc) + goto reset; + fsg->bulk_in_enabled = 1; + + d = fsg_ep_desc(common->gadget, + &fsg_fs_bulk_out_desc, &fsg_hs_bulk_out_desc); + rc = enable_endpoint(common, fsg->bulk_out, d); + if (rc) + goto reset; + fsg->bulk_out_enabled = 1; + common->bulk_out_maxpacket = le16_to_cpu(d->wMaxPacketSize); + clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags); + + /* Allocate the requests */ + for (i = 0; i < FSG_NUM_BUFFERS; ++i) { + struct fsg_buffhd *bh = &common->buffhds[i]; + + rc = alloc_request(common, fsg->bulk_in, &bh->inreq); + if (rc) + goto reset; + rc = alloc_request(common, fsg->bulk_out, &bh->outreq); + if (rc) + goto reset; + bh->inreq->buf = bh->outreq->buf = bh->buf; + bh->inreq->context = bh->outreq->context = bh; + bh->inreq->complete = bulk_in_complete; + bh->outreq->complete = bulk_out_complete; + } + + common->running = 1; + + return rc; +} + + +/****************************** ALT CONFIGS ******************************/ + + +static int fsg_set_alt(struct usb_function *f, unsigned intf, unsigned alt) +{ + struct fsg_dev *fsg = fsg_from_func(f); + fsg->common->new_fsg = fsg; + raise_exception(fsg->common, FSG_STATE_CONFIG_CHANGE); + return 0; +} + +static void fsg_disable(struct usb_function *f) +{ + struct fsg_dev *fsg = fsg_from_func(f); + fsg->common->new_fsg = NULL; + raise_exception(fsg->common, FSG_STATE_CONFIG_CHANGE); +} + +/*-------------------------------------------------------------------------*/ + +static void handle_exception(struct fsg_common *common) +{ + int i; + struct fsg_buffhd *bh; + enum fsg_state old_state; + struct fsg_lun *curlun; + unsigned int exception_req_tag; + + /* Cancel all the pending transfers */ + if (common->fsg) { + for (i = 0; i < FSG_NUM_BUFFERS; ++i) { + bh = &common->buffhds[i]; + if (bh->inreq_busy) + usb_ep_dequeue(common->fsg->bulk_in, bh->inreq); + if (bh->outreq_busy) + usb_ep_dequeue(common->fsg->bulk_out, + bh->outreq); + } + + /* Wait until everything is idle */ + for (;;) { + int num_active = 0; + for (i = 0; i < FSG_NUM_BUFFERS; ++i) { + bh = &common->buffhds[i]; + num_active += bh->inreq_busy + bh->outreq_busy; + } + if (num_active == 0) + break; + if (sleep_thread(common)) + return; + } + + /* Clear out the controller's fifos */ + if (common->fsg->bulk_in_enabled) + usb_ep_fifo_flush(common->fsg->bulk_in); + if (common->fsg->bulk_out_enabled) + usb_ep_fifo_flush(common->fsg->bulk_out); + } + + /* Reset the I/O buffer states and pointers, the SCSI + * state, and the exception. Then invoke the handler. */ + + for (i = 0; i < FSG_NUM_BUFFERS; ++i) { + bh = &common->buffhds[i]; + bh->state = BUF_STATE_EMPTY; + } + common->next_buffhd_to_fill = &common->buffhds[0]; + common->next_buffhd_to_drain = &common->buffhds[0]; + exception_req_tag = common->exception_req_tag; + old_state = common->state; + + if (old_state == FSG_STATE_ABORT_BULK_OUT) + common->state = FSG_STATE_STATUS_PHASE; + else { + for (i = 0; i < common->nluns; ++i) { + curlun = &common->luns[i]; + curlun->sense_data = SS_NO_SENSE; + curlun->info_valid = 0; + } + common->state = FSG_STATE_IDLE; + } + + /* Carry out any extra actions required for the exception */ + switch (old_state) { + case FSG_STATE_ABORT_BULK_OUT: + send_status(common); + + if (common->state == FSG_STATE_STATUS_PHASE) + common->state = FSG_STATE_IDLE; + break; + + case FSG_STATE_RESET: + /* In case we were forced against our will to halt a + * bulk endpoint, clear the halt now. (The SuperH UDC + * requires this.) */ + if (!fsg_is_set(common)) + break; + if (test_and_clear_bit(IGNORE_BULK_OUT, + &common->fsg->atomic_bitflags)) + usb_ep_clear_halt(common->fsg->bulk_in); + + if (common->ep0_req_tag == exception_req_tag) + ep0_queue(common); /* Complete the status stage */ + + break; + + case FSG_STATE_CONFIG_CHANGE: + do_set_interface(common, common->new_fsg); + break; + + case FSG_STATE_EXIT: + case FSG_STATE_TERMINATED: + do_set_interface(common, NULL); /* Free resources */ + common->state = FSG_STATE_TERMINATED; /* Stop the thread */ + break; + + case FSG_STATE_INTERFACE_CHANGE: + case FSG_STATE_DISCONNECT: + case FSG_STATE_COMMAND_PHASE: + case FSG_STATE_DATA_PHASE: + case FSG_STATE_STATUS_PHASE: + case FSG_STATE_IDLE: + break; + } +} + +/*-------------------------------------------------------------------------*/ + +int fsg_main_thread(void *common_) +{ + struct fsg_common *common = the_fsg_common; + /* The main loop */ + do { + if (exception_in_progress(common)) { + handle_exception(common); + continue; + } + + if (!common->running) { + sleep_thread(common); + continue; + } + + if (get_next_command(common)) + continue; + + if (!exception_in_progress(common)) + common->state = FSG_STATE_DATA_PHASE; + + if (do_scsi_command(common) || finish_reply(common)) + continue; + + if (!exception_in_progress(common)) + common->state = FSG_STATE_STATUS_PHASE; + + if (send_status(common)) + continue; + + if (!exception_in_progress(common)) + common->state = FSG_STATE_IDLE; + } while (0); + + common->thread_task = NULL; + + return 0; +} + +static void fsg_common_release(struct kref *ref); + +static struct fsg_common *fsg_common_init(struct fsg_common *common, + struct usb_composite_dev *cdev) +{ + struct usb_gadget *gadget = cdev->gadget; + struct fsg_buffhd *bh; + struct fsg_lun *curlun; + int nluns, i, rc; + + /* Find out how many LUNs there should be */ + nluns = 1; + if (nluns < 1 || nluns > FSG_MAX_LUNS) { + printf("invalid number of LUNs: %u\n", nluns); + return ERR_PTR(-EINVAL); + } + + /* Allocate? */ + if (!common) { + common = calloc(sizeof *common, 1); + if (!common) + return ERR_PTR(-ENOMEM); + common->free_storage_on_release = 1; + } else { + memset(common, 0, sizeof common); + common->free_storage_on_release = 0; + } + + common->ops = NULL; + common->private_data = NULL; + + common->gadget = gadget; + common->ep0 = gadget->ep0; + common->ep0req = cdev->req; + + /* Maybe allocate device-global string IDs, and patch descriptors */ + if (fsg_strings[FSG_STRING_INTERFACE].id == 0) { + rc = usb_string_id(cdev); + if (unlikely(rc < 0)) + goto error_release; + fsg_strings[FSG_STRING_INTERFACE].id = rc; + fsg_intf_desc.iInterface = rc; + } + + /* Create the LUNs, open their backing files, and register the + * LUN devices in sysfs. */ + curlun = calloc(nluns, sizeof *curlun); + if (!curlun) { + rc = -ENOMEM; + goto error_release; + } + common->nluns = nluns; + + for (i = 0; i < nluns; i++) { + common->luns[i].removable = 1; + + rc = fsg_lun_open(&common->luns[i], ""); + if (rc) + goto error_luns; + } + common->lun = 0; + + /* Data buffers cyclic list */ + bh = common->buffhds; + + i = FSG_NUM_BUFFERS; + goto buffhds_first_it; + do { + bh->next = bh + 1; + ++bh; +buffhds_first_it: + bh->inreq_busy = 0; + bh->outreq_busy = 0; + bh->buf = kmalloc(FSG_BUFLEN, GFP_KERNEL); + if (unlikely(!bh->buf)) { + rc = -ENOMEM; + goto error_release; + } + } while (--i); + bh->next = common->buffhds; + + snprintf(common->inquiry_string, sizeof common->inquiry_string, + "%-8s%-16s%04x", + "Linux ", + "File-Store Gadget", + 0xffff); + + /* Some peripheral controllers are known not to be able to + * halt bulk endpoints correctly. If one of them is present, + * disable stalls. + */ + + /* Tell the thread to start working */ + common->thread_task = + kthread_create(fsg_main_thread, common, + OR(cfg->thread_name, "file-storage")); + if (IS_ERR(common->thread_task)) { + rc = PTR_ERR(common->thread_task); + goto error_release; + } + +#undef OR + /* Information */ + INFO(common, FSG_DRIVER_DESC ", version: " FSG_DRIVER_VERSION "\n"); + INFO(common, "Number of LUNs=%d\n", common->nluns); + + return common; + +error_luns: + common->nluns = i + 1; +error_release: + common->state = FSG_STATE_TERMINATED; /* The thread is dead */ + /* Call fsg_common_release() directly, ref might be not + * initialised */ + fsg_common_release(&common->ref); + return ERR_PTR(rc); +} + +static void fsg_common_release(struct kref *ref) +{ + struct fsg_common *common = container_of(ref, struct fsg_common, ref); + + /* If the thread isn't already dead, tell it to exit now */ + if (common->state != FSG_STATE_TERMINATED) { + raise_exception(common, FSG_STATE_EXIT); + wait_for_completion(&common->thread_notifier); + } + + if (likely(common->luns)) { + struct fsg_lun *lun = common->luns; + unsigned i = common->nluns; + + /* In error recovery common->nluns may be zero. */ + for (; i; --i, ++lun) + fsg_lun_close(lun); + + kfree(common->luns); + } + + { + struct fsg_buffhd *bh = common->buffhds; + unsigned i = FSG_NUM_BUFFERS; + do { + kfree(bh->buf); + } while (++bh, --i); + } + + if (common->free_storage_on_release) + kfree(common); +} + + +/*-------------------------------------------------------------------------*/ + +/** + * usb_copy_descriptors - copy a vector of USB descriptors + * @src: null-terminated vector to copy + * Context: initialization code, which may sleep + * + * This makes a copy of a vector of USB descriptors. Its primary use + * is to support usb_function objects which can have multiple copies, + * each needing different descriptors. Functions may have static + * tables of descriptors, which are used as templates and customized + * with identifiers (for interfaces, strings, endpoints, and more) + * as needed by a given function instance. + */ +struct usb_descriptor_header ** +usb_copy_descriptors(struct usb_descriptor_header **src) +{ + struct usb_descriptor_header **tmp; + unsigned bytes; + unsigned n_desc; + void *mem; + struct usb_descriptor_header **ret; + + /* count descriptors and their sizes; then add vector size */ + for (bytes = 0, n_desc = 0, tmp = src; *tmp; tmp++, n_desc++) + bytes += (*tmp)->bLength; + bytes += (n_desc + 1) * sizeof(*tmp); + + mem = kmalloc(bytes, GFP_KERNEL); + if (!mem) + return NULL; + + /* fill in pointers starting at "tmp", + * to descriptors copied starting at "mem"; + * and return "ret" + */ + tmp = mem; + ret = mem; + mem += (n_desc + 1) * sizeof(*tmp); + while (*src) { + memcpy(mem, *src, (*src)->bLength); + *tmp = mem; + tmp++; + mem += (*src)->bLength; + src++; + } + *tmp = NULL; + + return ret; +} + + + +static void fsg_unbind(struct usb_configuration *c, struct usb_function *f) +{ + struct fsg_dev *fsg = fsg_from_func(f); + + DBG(fsg, "unbind\n"); + if (fsg->common->fsg == fsg) { + fsg->common->new_fsg = NULL; + raise_exception(fsg->common, FSG_STATE_CONFIG_CHANGE); + } + + free(fsg->function.descriptors); + free(fsg->function.hs_descriptors); + kfree(fsg); +} + +static int fsg_bind(struct usb_configuration *c, struct usb_function *f) +{ + struct fsg_dev *fsg = fsg_from_func(f); + struct usb_gadget *gadget = c->cdev->gadget; + int i; + struct usb_ep *ep; + fsg->gadget = gadget; + + /* New interface */ + i = usb_interface_id(c, f); + if (i < 0) + return i; + fsg_intf_desc.bInterfaceNumber = i; + fsg->interface_number = i; + + /* Find all the endpoints we will use */ + ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_in_desc); + if (!ep) + goto autoconf_fail; + ep->driver_data = fsg->common; /* claim the endpoint */ + fsg->bulk_in = ep; + + ep = usb_ep_autoconfig(gadget, &fsg_fs_bulk_out_desc); + if (!ep) + goto autoconf_fail; + ep->driver_data = fsg->common; /* claim the endpoint */ + fsg->bulk_out = ep; + + /* Copy descriptors */ + f->descriptors = usb_copy_descriptors(fsg_fs_function); + if (unlikely(!f->descriptors)) + return -ENOMEM; + + if (gadget_is_dualspeed(gadget)) { + /* Assume endpoint addresses are the same for both speeds */ + fsg_hs_bulk_in_desc.bEndpointAddress = + fsg_fs_bulk_in_desc.bEndpointAddress; + fsg_hs_bulk_out_desc.bEndpointAddress = + fsg_fs_bulk_out_desc.bEndpointAddress; + f->hs_descriptors = usb_copy_descriptors(fsg_hs_function); + if (unlikely(!f->hs_descriptors)) { + free(f->descriptors); + return -ENOMEM; + } + } + return 0; + +autoconf_fail: + ERROR(fsg, "unable to autoconfigure all endpoints\n"); + return -ENOTSUPP; +} + + +/****************************** ADD FUNCTION ******************************/ + +static struct usb_gadget_strings *fsg_strings_array[] = { + &fsg_stringtab, + NULL, +}; + +static int fsg_bind_config(struct usb_composite_dev *cdev, + struct usb_configuration *c, + struct fsg_common *common) +{ + struct fsg_dev *fsg; + int rc; + + fsg = calloc(1, sizeof *fsg); + if (!fsg) + return -ENOMEM; + fsg->function.name = FSG_DRIVER_DESC; + fsg->function.strings = fsg_strings_array; + fsg->function.bind = fsg_bind; + fsg->function.unbind = fsg_unbind; + fsg->function.setup = fsg_setup; + fsg->function.set_alt = fsg_set_alt; + fsg->function.disable = fsg_disable; + + fsg->common = common; + common->fsg = fsg; + /* Our caller holds a reference to common structure so we + * don't have to be worry about it being freed until we return + * from this function. So instead of incrementing counter now + * and decrement in error recovery we increment it only when + * call to usb_add_function() was successful. */ + + rc = usb_add_function(c, &fsg->function); + + if (rc) + kfree(fsg); + + return rc; +} + +int fsg_add(struct usb_configuration *c) +{ + struct fsg_common *fsg_common; + + fsg_common = fsg_common_init(NULL, c->cdev); + + fsg_common->vendor_name = 0; + fsg_common->product_name = 0; + fsg_common->release = 0xffff; + + fsg_common->ops = NULL; + fsg_common->private_data = NULL; + + the_fsg_common = fsg_common; + + return fsg_bind_config(c->cdev, c, fsg_common); +} + +int fsg_init(struct ums_board_info *ums) +{ + ums_info = ums; + + return 0; +} diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index a5a4c1f..cc3f344 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -31,6 +31,7 @@ #include "gadget_chips.h" #include "composite.c" +#include "f_mass_storage.c" /* * One needs to define the following: @@ -104,6 +105,8 @@ static int g_dnl_do_config(struct usb_configuration *c) printf("GADGET DRIVER: %s\n", s); if (!strcmp(s, "usb_dnl_dfu")) ret = dfu_add(c); + else if (!strcmp(s, "usb_dnl_ums")) + ret = fsg_add(c); return ret; } @@ -188,6 +191,9 @@ int g_dnl_register(const char *type) if (!strcmp(type, "dfu")) { strcpy(name, shortname); strcat(name, type); + } else if (!strcmp(type, "ums")) { + strcpy(name, shortname); + strcat(name, type); } else { printf("%s: unknown command: %s\n", __func__, type); return -EINVAL; diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c new file mode 100644 index 0000000..594dc10 --- /dev/null +++ b/drivers/usb/gadget/storage_common.c @@ -0,0 +1,653 @@ +/* + * storage_common.c -- Common definitions for mass storage functionality + * + * Copyright (C) 2003-2008 Alan Stern + * Copyeight (C) 2009 Samsung Electronics + * Author: Michal Nazarewicz (m.nazarewicz@samsung.com) + * + * Ported to u-boot: + * Andrzej Pietrasiewicz <andrzej.p@samsung.com> + * + * Code refactoring & cleanup: + * Łukasz Majewski <l.majewski@samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +/* + * This file requires the following identifiers used in USB strings to + * be defined (each of type pointer to char): + * - fsg_string_manufacturer -- name of the manufacturer + * - fsg_string_product -- name of the product + * - fsg_string_serial -- product's serial + * - fsg_string_config -- name of the configuration + * - fsg_string_interface -- name of the interface + * The first four are only needed when FSG_DESCRIPTORS_DEVICE_STRINGS + * macro is defined prior to including this file. + */ + +/* + * When FSG_NO_INTR_EP is defined fsg_fs_intr_in_desc and + * fsg_hs_intr_in_desc objects as well as + * FSG_FS_FUNCTION_PRE_EP_ENTRIES and FSG_HS_FUNCTION_PRE_EP_ENTRIES + * macros are not defined. + * + * When FSG_NO_DEVICE_STRINGS is defined FSG_STRING_MANUFACTURER, + * FSG_STRING_PRODUCT, FSG_STRING_SERIAL and FSG_STRING_CONFIG are not + * defined (as well as corresponding entries in string tables are + * missing) and FSG_STRING_INTERFACE has value of zero. + * + * When FSG_NO_OTG is defined fsg_otg_desc won't be defined. + */ + +/* + * When FSG_BUFFHD_STATIC_BUFFER is defined when this file is included + * the fsg_buffhd structure's buf field will be an array of FSG_BUFLEN + * characters rather then a pointer to void. + */ + + +/* #include <asm/unaligned.h> */ + + +/* + * Thanks to NetChip Technologies for donating this product ID. + * + * DO NOT REUSE THESE IDs with any other driver!! Ever!! + * Instead: allocate your own, using normal USB-IF procedures. + */ +#define FSG_VENDOR_ID 0x0525 /* NetChip */ +#define FSG_PRODUCT_ID 0xa4a5 /* Linux-USB File-backed Storage Gadget */ + +/*-------------------------------------------------------------------------*/ + +#ifndef DEBUG +#undef VERBOSE_DEBUG +#undef DUMP_MSGS +#endif /* !DEBUG */ + +#ifdef VERBOSE_DEBUG +#define VLDBG LDBG +#else +#define VLDBG(lun, fmt, args...) do { } while (0) +#endif /* VERBOSE_DEBUG */ + +/* +#define LDBG(lun, fmt, args...) dev_dbg (&(lun)->dev, fmt, ## args) +#define LERROR(lun, fmt, args...) dev_err (&(lun)->dev, fmt, ## args) +#define LWARN(lun, fmt, args...) dev_warn(&(lun)->dev, fmt, ## args) +#define LINFO(lun, fmt, args...) dev_info(&(lun)->dev, fmt, ## args) +*/ + +#define LDBG(lun, fmt, args...) do { } while (0) +#define LERROR(lun, fmt, args...) do { } while (0) +#define LWARN(lun, fmt, args...) do { } while (0) +#define LINFO(lun, fmt, args...) do { } while (0) + +/* + * Keep those macros in sync with those in + * include/linux/usb/composite.h or else GCC will complain. If they + * are identical (the same names of arguments, white spaces in the + * same places) GCC will allow redefinition otherwise (even if some + * white space is removed or added) warning will be issued. + * + * Those macros are needed here because File Storage Gadget does not + * include the composite.h header. For composite gadgets those macros + * are redundant since composite.h is included any way. + * + * One could check whether those macros are already defined (which + * would indicate composite.h had been included) or not (which would + * indicate we were in FSG) but this is not done because a warning is + * desired if definitions here differ from the ones in composite.h. + * + * We want the definitions to match and be the same in File Storage + * Gadget as well as Mass Storage Function (and so composite gadgets + * using MSF). If someone changes them in composite.h it will produce + * a warning in this file when building MSF. + */ + +#define DBG(d, fmt, args...) debug(fmt , ## args) +#define VDBG(d, fmt, args...) debug(fmt , ## args) +/* #define ERROR(d, fmt, args...) printf(fmt , ## args) */ +/* #define WARNING(d, fmt, args...) printf(fmt , ## args) */ +/* #define INFO(d, fmt, args...) printf(fmt , ## args) */ + +/* #define DBG(d, fmt, args...) do { } while (0) */ +/* #define VDBG(d, fmt, args...) do { } while (0) */ +#define ERROR(d, fmt, args...) do { } while (0) +#define WARNING(d, fmt, args...) do { } while (0) +#define INFO(d, fmt, args...) do { } while (0) + +#ifdef DUMP_MSGS + +/* dump_msg(fsg, const char * label, const u8 * buf, unsigned length); */ +# define dump_msg(fsg, label, buf, length) do { \ + if (length < 512) { \ + DBG(fsg, "%s, length %u:\n", label, length); \ + print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, \ + 16, 1, buf, length, 0); \ + } \ +} while (0) + +# define dump_cdb(fsg) do { } while (0) + +#else + +# define dump_msg(fsg, /* const char * */ label, \ + /* const u8 * */ buf, /* unsigned */ length) do { } while (0) + +# ifdef VERBOSE_DEBUG + +# define dump_cdb(fsg) \ + print_hex_dump(KERN_DEBUG, "SCSI CDB: ", DUMP_PREFIX_NONE, \ + 16, 1, (fsg)->cmnd, (fsg)->cmnd_size, 0) \ + +# else + +# define dump_cdb(fsg) do { } while (0) + +# endif /* VERBOSE_DEBUG */ + +#endif /* DUMP_MSGS */ + +/*-------------------------------------------------------------------------*/ + +/* SCSI device types */ +#define TYPE_DISK 0x00 +#define TYPE_CDROM 0x05 + +/* USB protocol value = the transport method */ +#define USB_PR_CBI 0x00 /* Control/Bulk/Interrupt */ +#define USB_PR_CB 0x01 /* Control/Bulk w/o interrupt */ +#define USB_PR_BULK 0x50 /* Bulk-only */ + +/* USB subclass value = the protocol encapsulation */ +#define USB_SC_RBC 0x01 /* Reduced Block Commands (flash) */ +#define USB_SC_8020 0x02 /* SFF-8020i, MMC-2, ATAPI (CD-ROM) */ +#define USB_SC_QIC 0x03 /* QIC-157 (tape) */ +#define USB_SC_UFI 0x04 /* UFI (floppy) */ +#define USB_SC_8070 0x05 /* SFF-8070i (removable) */ +#define USB_SC_SCSI 0x06 /* Transparent SCSI */ + +/* Bulk-only data structures */ + +/* Command Block Wrapper */ +struct fsg_bulk_cb_wrap { + __le32 Signature; /* Contains 'USBC' */ + u32 Tag; /* Unique per command id */ + __le32 DataTransferLength; /* Size of the data */ + u8 Flags; /* Direction in bit 7 */ + u8 Lun; /* LUN (normally 0) */ + u8 Length; /* Of the CDB, <= MAX_COMMAND_SIZE */ + u8 CDB[16]; /* Command Data Block */ +}; + +#define USB_BULK_CB_WRAP_LEN 31 +#define USB_BULK_CB_SIG 0x43425355 /* Spells out USBC */ +#define USB_BULK_IN_FLAG 0x80 + +/* Command Status Wrapper */ +struct bulk_cs_wrap { + __le32 Signature; /* Should = 'USBS' */ + u32 Tag; /* Same as original command */ + __le32 Residue; /* Amount not transferred */ + u8 Status; /* See below */ +}; + +#define USB_BULK_CS_WRAP_LEN 13 +#define USB_BULK_CS_SIG 0x53425355 /* Spells out 'USBS' */ +#define USB_STATUS_PASS 0 +#define USB_STATUS_FAIL 1 +#define USB_STATUS_PHASE_ERROR 2 + +/* Bulk-only class specific requests */ +#define USB_BULK_RESET_REQUEST 0xff +#define USB_BULK_GET_MAX_LUN_REQUEST 0xfe + +/* CBI Interrupt data structure */ +struct interrupt_data { + u8 bType; + u8 bValue; +}; + +#define CBI_INTERRUPT_DATA_LEN 2 + +/* CBI Accept Device-Specific Command request */ +#define USB_CBI_ADSC_REQUEST 0x00 + +/* Length of a SCSI Command Data Block */ +#define MAX_COMMAND_SIZE 16 + +/* SCSI commands that we recognize */ +#define SC_FORMAT_UNIT 0x04 +#define SC_INQUIRY 0x12 +#define SC_MODE_SELECT_6 0x15 +#define SC_MODE_SELECT_10 0x55 +#define SC_MODE_SENSE_6 0x1a +#define SC_MODE_SENSE_10 0x5a +#define SC_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1e +#define SC_READ_6 0x08 +#define SC_READ_10 0x28 +#define SC_READ_12 0xa8 +#define SC_READ_CAPACITY 0x25 +#define SC_READ_FORMAT_CAPACITIES 0x23 +#define SC_READ_HEADER 0x44 +#define SC_READ_TOC 0x43 +#define SC_RELEASE 0x17 +#define SC_REQUEST_SENSE 0x03 +#define SC_RESERVE 0x16 +#define SC_SEND_DIAGNOSTIC 0x1d +#define SC_START_STOP_UNIT 0x1b +#define SC_SYNCHRONIZE_CACHE 0x35 +#define SC_TEST_UNIT_READY 0x00 +#define SC_VERIFY 0x2f +#define SC_WRITE_6 0x0a +#define SC_WRITE_10 0x2a +#define SC_WRITE_12 0xaa + +/* SCSI Sense Key/Additional Sense Code/ASC Qualifier values */ +#define SS_NO_SENSE 0 +#define SS_COMMUNICATION_FAILURE 0x040800 +#define SS_INVALID_COMMAND 0x052000 +#define SS_INVALID_FIELD_IN_CDB 0x052400 +#define SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x052100 +#define SS_LOGICAL_UNIT_NOT_SUPPORTED 0x052500 +#define SS_MEDIUM_NOT_PRESENT 0x023a00 +#define SS_MEDIUM_REMOVAL_PREVENTED 0x055302 +#define SS_NOT_READY_TO_READY_TRANSITION 0x062800 +#define SS_RESET_OCCURRED 0x062900 +#define SS_SAVING_PARAMETERS_NOT_SUPPORTED 0x053900 +#define SS_UNRECOVERED_READ_ERROR 0x031100 +#define SS_WRITE_ERROR 0x030c02 +#define SS_WRITE_PROTECTED 0x072700 + +#define SK(x) ((u8) ((x) >> 16)) /* Sense Key byte, etc. */ +#define ASC(x) ((u8) ((x) >> 8)) +#define ASCQ(x) ((u8) (x)) + +struct device_attribute { int i; }; +struct rw_semaphore { int i; }; +#define down_write(...) do { } while (0) +#define up_write(...) do { } while (0) +#define down_read(...) do { } while (0) +#define up_read(...) do { } while (0) +#define ETOOSMALL 525 + +#include <usb_mass_storage.h> +extern struct ums_board_info *ums_info; + +/*-------------------------------------------------------------------------*/ + +struct fsg_lun { + loff_t file_length; + loff_t num_sectors; + + unsigned int initially_ro:1; + unsigned int ro:1; + unsigned int removable:1; + unsigned int cdrom:1; + unsigned int prevent_medium_removal:1; + unsigned int registered:1; + unsigned int info_valid:1; + unsigned int nofua:1; + + u32 sense_data; + u32 sense_data_info; + u32 unit_attention_data; + + struct device dev; +}; + +#define fsg_lun_is_open(curlun) ((curlun)->filp != NULL) +#if 0 +static struct fsg_lun *fsg_lun_from_dev(struct device *dev) +{ + return container_of(dev, struct fsg_lun, dev); +} +#endif + +/* Big enough to hold our biggest descriptor */ +#define EP0_BUFSIZE 256 +#define DELAYED_STATUS (EP0_BUFSIZE + 999) /* An impossibly large value */ + +/* Number of buffers we will use. 2 is enough for double-buffering */ +#define FSG_NUM_BUFFERS 2 + +/* Default size of buffer length. */ +#define FSG_BUFLEN ((u32)16384) + +/* Maximal number of LUNs supported in mass storage function */ +#define FSG_MAX_LUNS 8 + +enum fsg_buffer_state { + BUF_STATE_EMPTY = 0, + BUF_STATE_FULL, + BUF_STATE_BUSY +}; + +struct fsg_buffhd { +#ifdef FSG_BUFFHD_STATIC_BUFFER + char buf[FSG_BUFLEN]; +#else + void *buf; +#endif + enum fsg_buffer_state state; + struct fsg_buffhd *next; + + /* + * The NetChip 2280 is faster, and handles some protocol faults + * better, if we don't submit any short bulk-out read requests. + * So we will record the intended request length here. + */ + unsigned int bulk_out_intended_length; + + struct usb_request *inreq; + int inreq_busy; + struct usb_request *outreq; + int outreq_busy; +}; + +enum fsg_state { + /* This one isn't used anywhere */ + FSG_STATE_COMMAND_PHASE = -10, + FSG_STATE_DATA_PHASE, + FSG_STATE_STATUS_PHASE, + + FSG_STATE_IDLE = 0, + FSG_STATE_ABORT_BULK_OUT, + FSG_STATE_RESET, + FSG_STATE_INTERFACE_CHANGE, + FSG_STATE_CONFIG_CHANGE, + FSG_STATE_DISCONNECT, + FSG_STATE_EXIT, + FSG_STATE_TERMINATED +}; + +enum data_direction { + DATA_DIR_UNKNOWN = 0, + DATA_DIR_FROM_HOST, + DATA_DIR_TO_HOST, + DATA_DIR_NONE +}; + +/*-------------------------------------------------------------------------*/ + +static inline u32 get_unaligned_be24(u8 *buf) +{ + return 0xffffff & (u32) get_unaligned_be32(buf - 1); +} + +/*-------------------------------------------------------------------------*/ + +enum { +#ifndef FSG_NO_DEVICE_STRINGS + FSG_STRING_MANUFACTURER = 1, + FSG_STRING_PRODUCT, + FSG_STRING_SERIAL, + FSG_STRING_CONFIG, +#endif + FSG_STRING_INTERFACE +}; + +#ifndef FSG_NO_OTG +static struct usb_otg_descriptor +fsg_otg_desc = { + .bLength = sizeof fsg_otg_desc, + .bDescriptorType = USB_DT_OTG, + + .bmAttributes = USB_OTG_SRP, +}; +#endif + +/* There is only one interface. */ + +static struct usb_interface_descriptor +fsg_intf_desc = { + .bLength = sizeof fsg_intf_desc, + .bDescriptorType = USB_DT_INTERFACE, + + .bNumEndpoints = 2, /* Adjusted during fsg_bind() */ + .bInterfaceClass = USB_CLASS_MASS_STORAGE, + .bInterfaceSubClass = USB_SC_SCSI, /* Adjusted during fsg_bind() */ + .bInterfaceProtocol = USB_PR_BULK, /* Adjusted during fsg_bind() */ + .iInterface = FSG_STRING_INTERFACE, +}; + +/* + * Three full-speed endpoint descriptors: bulk-in, bulk-out, and + * interrupt-in. + */ + +static struct usb_endpoint_descriptor +fsg_fs_bulk_in_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + /* wMaxPacketSize set by autoconfiguration */ +}; + +static struct usb_endpoint_descriptor +fsg_fs_bulk_out_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bEndpointAddress = USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, + /* wMaxPacketSize set by autoconfiguration */ +}; + +#ifndef FSG_NO_INTR_EP + +static struct usb_endpoint_descriptor +fsg_fs_intr_in_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_INT, + .wMaxPacketSize = cpu_to_le16(2), + .bInterval = 32, /* frames -> 32 ms */ +}; + +#ifndef FSG_NO_OTG +# define FSG_FS_FUNCTION_PRE_EP_ENTRIES 2 +#else +# define FSG_FS_FUNCTION_PRE_EP_ENTRIES 1 +#endif + +#endif + +static struct usb_descriptor_header *fsg_fs_function[] = { +#ifndef FSG_NO_OTG + (struct usb_descriptor_header *) &fsg_otg_desc, +#endif + (struct usb_descriptor_header *) &fsg_intf_desc, + (struct usb_descriptor_header *) &fsg_fs_bulk_in_desc, + (struct usb_descriptor_header *) &fsg_fs_bulk_out_desc, +#ifndef FSG_NO_INTR_EP + (struct usb_descriptor_header *) &fsg_fs_intr_in_desc, +#endif + NULL, +}; + +/* + * USB 2.0 devices need to expose both high speed and full speed + * descriptors, unless they only run at full speed. + * + * That means alternate endpoint descriptors (bigger packets) + * and a "device qualifier" ... plus more construction options + * for the configuration descriptor. + */ +static struct usb_endpoint_descriptor +fsg_hs_bulk_in_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + /* bEndpointAddress copied from fs_bulk_in_desc during fsg_bind() */ + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = cpu_to_le16(512), +}; + +static struct usb_endpoint_descriptor +fsg_hs_bulk_out_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + /* bEndpointAddress copied from fs_bulk_out_desc during fsg_bind() */ + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = cpu_to_le16(512), + .bInterval = 1, /* NAK every 1 uframe */ +}; + +#ifndef FSG_NO_INTR_EP + +static struct usb_endpoint_descriptor +fsg_hs_intr_in_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + /* bEndpointAddress copied from fs_intr_in_desc during fsg_bind() */ + .bmAttributes = USB_ENDPOINT_XFER_INT, + .wMaxPacketSize = cpu_to_le16(2), + .bInterval = 9, /* 2**(9-1) = 256 uframes -> 32 ms */ +}; + +#ifndef FSG_NO_OTG +# define FSG_HS_FUNCTION_PRE_EP_ENTRIES 2 +#else +# define FSG_HS_FUNCTION_PRE_EP_ENTRIES 1 +#endif + +#endif + +static struct usb_descriptor_header *fsg_hs_function[] = { +#ifndef FSG_NO_OTG + (struct usb_descriptor_header *) &fsg_otg_desc, +#endif + (struct usb_descriptor_header *) &fsg_intf_desc, + (struct usb_descriptor_header *) &fsg_hs_bulk_in_desc, + (struct usb_descriptor_header *) &fsg_hs_bulk_out_desc, +#ifndef FSG_NO_INTR_EP + (struct usb_descriptor_header *) &fsg_hs_intr_in_desc, +#endif + NULL, +}; + +/* Maxpacket and other transfer characteristics vary by speed. */ +static struct usb_endpoint_descriptor * +fsg_ep_desc(struct usb_gadget *g, struct usb_endpoint_descriptor *fs, + struct usb_endpoint_descriptor *hs) +{ + if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH) + return hs; + return fs; +} + +/* Static strings, in UTF-8 (for simplicity we use only ASCII characters) */ +static struct usb_string fsg_strings[] = { +#ifndef FSG_NO_DEVICE_STRINGS + {FSG_STRING_MANUFACTURER, fsg_string_manufacturer}, + {FSG_STRING_PRODUCT, fsg_string_product}, + {FSG_STRING_SERIAL, fsg_string_serial}, + {FSG_STRING_CONFIG, fsg_string_config}, +#endif + {FSG_STRING_INTERFACE, fsg_string_interface}, + {} +}; + +static struct usb_gadget_strings fsg_stringtab = { + .language = 0x0409, /* en-us */ + .strings = fsg_strings, +}; + +/*-------------------------------------------------------------------------*/ + +/* + * If the next two routines are called while the gadget is registered, + * the caller must own fsg->filesem for writing. + */ + +static int fsg_lun_open(struct fsg_lun *curlun, const char *filename) +{ + int ro; + int rc = -EINVAL; + loff_t size; + loff_t num_sectors; + loff_t min_sectors; + + /* R/W if we can, R/O if we must */ + ro = curlun->initially_ro; + + ums_info->get_capacity(&(ums_info->ums_dev), &size); + if (size < 0) { + printf("unable to find file size: %s\n", filename); + rc = (int) size; + goto out; + } + num_sectors = size >> 9; /* File size in 512-byte blocks */ + min_sectors = 1; + if (num_sectors < min_sectors) { + printf("file too small: %s\n", filename); + rc = -ETOOSMALL; + goto out; + } + + curlun->ro = ro; + curlun->file_length = size; + curlun->num_sectors = num_sectors; + debug("open backing file: %s\n", filename); + rc = 0; + +out: + return rc; +} + +static void fsg_lun_close(struct fsg_lun *curlun) +{ +} + +/*-------------------------------------------------------------------------*/ + +/* + * Sync the file data, don't bother with the metadata. + * This code was copied from fs/buffer.c:sys_fdatasync(). + */ +static int fsg_lun_fsync_sub(struct fsg_lun *curlun) +{ + return 0; +} + +static void store_cdrom_address(u8 *dest, int msf, u32 addr) +{ + if (msf) { + /* Convert to Minutes-Seconds-Frames */ + addr >>= 2; /* Convert to 2048-byte frames */ + addr += 2*75; /* Lead-in occupies 2 seconds */ + dest[3] = addr % 75; /* Frames */ + addr /= 75; + dest[2] = addr % 60; /* Seconds */ + addr /= 60; + dest[1] = addr; /* Minutes */ + dest[0] = 0; /* Reserved */ + } else { + /* Absolute sector */ + put_unaligned_be32(addr, dest); + } +} + +/*-------------------------------------------------------------------------*/ diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 6c94794..87a5970 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -31,7 +31,6 @@ COBJS-$(CONFIG_USB_ATMEL) += ohci-at91.o COBJS-$(CONFIG_USB_OHCI_DA8XX) += ohci-da8xx.o COBJS-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o -COBJS-$(CONFIG_USB_S3C64XX) += s3c64xx-hcd.o COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o COBJS-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o @@ -54,6 +53,7 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o +COBJS-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o diff --git a/drivers/usb/host/ehci-exynos.c b/drivers/usb/host/ehci-exynos.c index 3ca4c5c..0c797aa 100644 --- a/drivers/usb/host/ehci-exynos.c +++ b/drivers/usb/host/ehci-exynos.c @@ -42,11 +42,15 @@ DECLARE_GLOBAL_DATA_PTR; */ struct exynos_ehci { struct exynos_usb_phy *usb; - unsigned int *hcd; + struct ehci_hccr *hcd; }; +static struct exynos_ehci exynos; + +#ifdef CONFIG_OF_CONTROL static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos) { + fdt_addr_t addr; unsigned int node; int depth; @@ -59,12 +63,14 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos) /* * Get the base address for EHCI controller from the device node */ - exynos->hcd = (unsigned int *)fdtdec_get_addr(blob, node, "reg"); - if (exynos->hcd == NULL) { + addr = fdtdec_get_addr(blob, node, "reg"); + if (addr == FDT_ADDR_T_NONE) { debug("Can't get the EHCI register address\n"); return -ENXIO; } + exynos->hcd = (struct ehci_hccr *)addr; + depth = 0; node = fdtdec_next_compatible_subnode(blob, node, COMPAT_SAMSUNG_EXYNOS_USB_PHY, &depth); @@ -85,6 +91,7 @@ static int exynos_usb_parse_dt(const void *blob, struct exynos_ehci *exynos) return 0; } +#endif /* Setup the EHCI host controller. */ static void setup_usb_phy(struct exynos_usb_phy *usb) @@ -144,20 +151,21 @@ static void reset_usb_phy(struct exynos_usb_phy *usb) */ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { - struct exynos_ehci *exynos = NULL; + struct exynos_ehci *ctx = &exynos; - exynos = (struct exynos_ehci *) - kzalloc(sizeof(struct exynos_ehci), GFP_KERNEL); - if (!exynos) { - debug("failed to allocate exynos ehci context\n"); - return -ENOMEM; +#ifdef CONFIG_OF_CONTROL + if (exynos_usb_parse_dt(gd->fdt_blob, ctx)) { + debug("Unable to parse device tree for ehci-exynos\n"); + return -ENODEV; } +#else + ctx->usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy(); + ctx->hcd = (struct ehci_hccr *)samsung_get_base_usb_ehci(); +#endif - exynos_usb_parse_dt(gd->fdt_blob, exynos); + setup_usb_phy(ctx->usb); - setup_usb_phy(exynos->usb); - - *hccr = (struct ehci_hccr *)(exynos->hcd); + *hccr = ctx->hcd; *hcor = (struct ehci_hcor *)((uint32_t) *hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); @@ -165,8 +173,6 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) (uint32_t)*hccr, (uint32_t)*hcor, (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - kfree(exynos); - return 0; } @@ -176,20 +182,9 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) */ int ehci_hcd_stop(int index) { - struct exynos_ehci *exynos = NULL; - - exynos = (struct exynos_ehci *) - kzalloc(sizeof(struct exynos_ehci), GFP_KERNEL); - if (!exynos) { - debug("failed to allocate exynos ehci context\n"); - return -ENOMEM; - } - - exynos_usb_parse_dt(gd->fdt_blob, exynos); - - reset_usb_phy(exynos->usb); + struct exynos_ehci *ctx = &exynos; - kfree(exynos); + reset_usb_phy(ctx->usb); return 0; } diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 7f98a63..c816878 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -21,12 +21,14 @@ * MA 02111-1307 USA */ #include <common.h> +#include <errno.h> #include <asm/byteorder.h> #include <asm/unaligned.h> #include <usb.h> #include <asm/io.h> #include <malloc.h> #include <watchdog.h> +#include <linux/compiler.h> #include "ehci.h" @@ -39,7 +41,10 @@ static struct ehci_ctrl { struct ehci_hcor *hcor; int rootdev; uint16_t portreset; - struct QH qh_list __attribute__((aligned(USB_DMA_MINALIGN))); + struct QH qh_list __aligned(USB_DMA_MINALIGN); + struct QH periodic_queue __aligned(USB_DMA_MINALIGN); + uint32_t *periodic_list; + int ntds; } ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT]; #define ALIGN_END_ADDR(type, ptr, size) \ @@ -858,6 +863,8 @@ int usb_lowlevel_init(int index, void **controller) uint32_t reg; uint32_t cmd; struct QH *qh_list; + struct QH *periodic; + int i; if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor)) return -1; @@ -870,6 +877,9 @@ int usb_lowlevel_init(int index, void **controller) if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor)) return -1; #endif + /* Set the high address word (aka segment) for 64-bit controller */ + if (ehci_readl(&ehcic[index].hccr->cr_hccparams) & 1) + ehci_writel(ehcic[index].hcor->or_ctrldssegment, 0); qh_list = &ehcic[index].qh_list; @@ -884,6 +894,40 @@ int usb_lowlevel_init(int index, void **controller) qh_list->qh_overlay.qt_token = cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED)); + /* Set async. queue head pointer. */ + ehci_writel(&ehcic[index].hcor->or_asynclistaddr, (uint32_t)qh_list); + + /* + * Set up periodic list + * Step 1: Parent QH for all periodic transfers. + */ + periodic = &ehcic[index].periodic_queue; + memset(periodic, 0, sizeof(*periodic)); + periodic->qh_link = cpu_to_hc32(QH_LINK_TERMINATE); + periodic->qh_overlay.qt_next = cpu_to_hc32(QT_NEXT_TERMINATE); + periodic->qh_overlay.qt_altnext = cpu_to_hc32(QT_NEXT_TERMINATE); + + /* + * Step 2: Setup frame-list: Every microframe, USB tries the same list. + * In particular, device specifications on polling frequency + * are disregarded. Keyboards seem to send NAK/NYet reliably + * when polled with an empty buffer. + * + * Split Transactions will be spread across microframes using + * S-mask and C-mask. + */ + ehcic[index].periodic_list = memalign(4096, 1024*4); + if (!ehcic[index].periodic_list) + return -ENOMEM; + for (i = 0; i < 1024; i++) { + ehcic[index].periodic_list[i] = (uint32_t)periodic + | QH_LINK_TYPE_QH; + } + + /* Set periodic list base address */ + ehci_writel(&ehcic[index].hcor->or_periodiclistbase, + (uint32_t)ehcic[index].periodic_list); + reg = ehci_readl(&ehcic[index].hccr->cr_hcsparams); descriptor.hub.bNbrPorts = HCS_N_PORTS(reg); debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); @@ -953,10 +997,254 @@ submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, return ehci_submit_async(dev, pipe, buffer, length, setup); } +struct int_queue { + struct QH *first; + struct QH *current; + struct QH *last; + struct qTD *tds; +}; + +#define NEXT_QH(qh) (struct QH *)((qh)->qh_link & ~0x1f) + +static int +enable_periodic(struct ehci_ctrl *ctrl) +{ + uint32_t cmd; + struct ehci_hcor *hcor = ctrl->hcor; + int ret; + + cmd = ehci_readl(&hcor->or_usbcmd); + cmd |= CMD_PSE; + ehci_writel(&hcor->or_usbcmd, cmd); + + ret = handshake((uint32_t *)&hcor->or_usbsts, + STS_PSS, STS_PSS, 100 * 1000); + if (ret < 0) { + printf("EHCI failed: timeout when enabling periodic list\n"); + return -ETIMEDOUT; + } + udelay(1000); + return 0; +} + +static int +disable_periodic(struct ehci_ctrl *ctrl) +{ + uint32_t cmd; + struct ehci_hcor *hcor = ctrl->hcor; + int ret; + + cmd = ehci_readl(&hcor->or_usbcmd); + cmd &= ~CMD_PSE; + ehci_writel(&hcor->or_usbcmd, cmd); + + ret = handshake((uint32_t *)&hcor->or_usbsts, + STS_PSS, 0, 100 * 1000); + if (ret < 0) { + printf("EHCI failed: timeout when disabling periodic list\n"); + return -ETIMEDOUT; + } + return 0; +} + +static int periodic_schedules; + +struct int_queue * +create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, + int elementsize, void *buffer) +{ + struct ehci_ctrl *ctrl = dev->controller; + struct int_queue *result = NULL; + int i; + + debug("Enter create_int_queue\n"); + if (usb_pipetype(pipe) != PIPE_INTERRUPT) { + debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe)); + return NULL; + } + + /* limit to 4 full pages worth of data - + * we can safely fit them in a single TD, + * no matter the alignment + */ + if (elementsize >= 16384) { + debug("too large elements for interrupt transfers\n"); + return NULL; + } + + result = malloc(sizeof(*result)); + if (!result) { + debug("ehci intr queue: out of memory\n"); + goto fail1; + } + result->first = memalign(32, sizeof(struct QH) * queuesize); + if (!result->first) { + debug("ehci intr queue: out of memory\n"); + goto fail2; + } + result->current = result->first; + result->last = result->first + queuesize - 1; + result->tds = memalign(32, sizeof(struct qTD) * queuesize); + if (!result->tds) { + debug("ehci intr queue: out of memory\n"); + goto fail3; + } + memset(result->first, 0, sizeof(struct QH) * queuesize); + memset(result->tds, 0, sizeof(struct qTD) * queuesize); + + for (i = 0; i < queuesize; i++) { + struct QH *qh = result->first + i; + struct qTD *td = result->tds + i; + void **buf = &qh->buffer; + + qh->qh_link = (uint32_t)(qh+1) | QH_LINK_TYPE_QH; + if (i == queuesize - 1) + qh->qh_link = QH_LINK_TERMINATE; + + qh->qh_overlay.qt_next = (uint32_t)td; + qh->qh_endpt1 = (0 << 28) | /* No NAK reload (ehci 4.9) */ + (usb_maxpacket(dev, pipe) << 16) | /* MPS */ + (1 << 14) | + QH_ENDPT1_EPS(ehci_encode_speed(dev->speed)) | + (usb_pipeendpoint(pipe) << 8) | /* Endpoint Number */ + (usb_pipedevice(pipe) << 0); + qh->qh_endpt2 = (1 << 30) | /* 1 Tx per mframe */ + (1 << 0); /* S-mask: microframe 0 */ + if (dev->speed == USB_SPEED_LOW || + dev->speed == USB_SPEED_FULL) { + debug("TT: port: %d, hub address: %d\n", + dev->portnr, dev->parent->devnum); + qh->qh_endpt2 |= (dev->portnr << 23) | + (dev->parent->devnum << 16) | + (0x1c << 8); /* C-mask: microframes 2-4 */ + } + + td->qt_next = QT_NEXT_TERMINATE; + td->qt_altnext = QT_NEXT_TERMINATE; + debug("communication direction is '%s'\n", + usb_pipein(pipe) ? "in" : "out"); + td->qt_token = (elementsize << 16) | + ((usb_pipein(pipe) ? 1 : 0) << 8) | /* IN/OUT token */ + 0x80; /* active */ + td->qt_buffer[0] = (uint32_t)buffer + i * elementsize; + td->qt_buffer[1] = (td->qt_buffer[0] + 0x1000) & ~0xfff; + td->qt_buffer[2] = (td->qt_buffer[0] + 0x2000) & ~0xfff; + td->qt_buffer[3] = (td->qt_buffer[0] + 0x3000) & ~0xfff; + td->qt_buffer[4] = (td->qt_buffer[0] + 0x4000) & ~0xfff; + + *buf = buffer + i * elementsize; + } + + if (disable_periodic(ctrl) < 0) { + debug("FATAL: periodic should never fail, but did"); + goto fail3; + } + + /* hook up to periodic list */ + struct QH *list = &ctrl->periodic_queue; + result->last->qh_link = list->qh_link; + list->qh_link = (uint32_t)result->first | QH_LINK_TYPE_QH; + + if (enable_periodic(ctrl) < 0) { + debug("FATAL: periodic should never fail, but did"); + goto fail3; + } + periodic_schedules++; + + debug("Exit create_int_queue\n"); + return result; +fail3: + if (result->tds) + free(result->tds); +fail2: + if (result->first) + free(result->first); + if (result) + free(result); +fail1: + return NULL; +} + +void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) +{ + struct QH *cur = queue->current; + + /* depleted queue */ + if (cur == NULL) { + debug("Exit poll_int_queue with completed queue\n"); + return NULL; + } + /* still active */ + if (cur->qh_overlay.qt_token & 0x80) { + debug("Exit poll_int_queue with no completed intr transfer. " + "token is %x\n", cur->qh_overlay.qt_token); + return NULL; + } + if (!(cur->qh_link & QH_LINK_TERMINATE)) + queue->current++; + else + queue->current = NULL; + debug("Exit poll_int_queue with completed intr transfer. " + "token is %x at %p (first at %p)\n", cur->qh_overlay.qt_token, + &cur->qh_overlay.qt_token, queue->first); + return cur->buffer; +} + +/* Do not free buffers associated with QHs, they're owned by someone else */ +int +destroy_int_queue(struct usb_device *dev, struct int_queue *queue) +{ + struct ehci_ctrl *ctrl = dev->controller; + int result = -1; + unsigned long timeout; + + if (disable_periodic(ctrl) < 0) { + debug("FATAL: periodic should never fail, but did"); + goto out; + } + periodic_schedules--; + + struct QH *cur = &ctrl->periodic_queue; + timeout = get_timer(0) + 500; /* abort after 500ms */ + while (!(cur->qh_link & QH_LINK_TERMINATE)) { + debug("considering %p, with qh_link %x\n", cur, cur->qh_link); + if (NEXT_QH(cur) == queue->first) { + debug("found candidate. removing from chain\n"); + cur->qh_link = queue->last->qh_link; + result = 0; + break; + } + cur = NEXT_QH(cur); + if (get_timer(0) > timeout) { + printf("Timeout destroying interrupt endpoint queue\n"); + result = -1; + goto out; + } + } + + if (periodic_schedules > 0) { + result = enable_periodic(ctrl); + if (result < 0) + debug("FATAL: periodic should never fail, but did"); + } + +out: + free(queue->tds); + free(queue->first); + free(queue); + + return result; +} + int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int length, int interval) { + void *backbuffer; + struct int_queue *queue; + unsigned long timeout; + int result = 0, ret; + debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", dev, pipe, buffer, length, interval); @@ -972,9 +1260,31 @@ submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, * not require more than a single qTD. */ if (length > usb_maxpacket(dev, pipe)) { - printf("%s: Interrupt transfers requiring several transactions " - "are not supported.\n", __func__); + printf("%s: Interrupt transfers requiring several " + "transactions are not supported.\n", __func__); return -1; } - return ehci_submit_async(dev, pipe, buffer, length, NULL); + + queue = create_int_queue(dev, pipe, 1, length, buffer); + + timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); + while ((backbuffer = poll_int_queue(dev, queue)) == NULL) + if (get_timer(0) > timeout) { + printf("Timeout poll on interrupt endpoint\n"); + result = -ETIMEDOUT; + break; + } + + if (backbuffer != buffer) { + debug("got wrong buffer back (%x instead of %x)\n", + (uint32_t)backbuffer, (uint32_t)buffer); + return -EINVAL; + } + + ret = destroy_int_queue(dev, queue); + if (ret < 0) + return ret; + + /* everything worked out fine */ + return result; } diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c index 29af02d..90d7a6f 100644 --- a/drivers/usb/host/ehci-pci.c +++ b/drivers/usb/host/ehci-pci.c @@ -19,6 +19,7 @@ */ #include <common.h> +#include <errno.h> #include <pci.h> #include <usb.h> @@ -32,31 +33,76 @@ static struct pci_device_id ehci_pci_ids[] = { {0x12D8, 0x400F}, /* Pericom */ {0, 0} }; +#else +static pci_dev_t ehci_find_class(int index) +{ + int bus; + int devnum; + pci_dev_t bdf; + uint32_t class; + + for (bus = 0; bus <= pci_last_busno(); bus++) { + for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES-1; devnum++) { + pci_read_config_dword(PCI_BDF(bus, devnum, 0), + PCI_CLASS_REVISION, &class); + if (class >> 16 == 0xffff) + continue; + + for (bdf = PCI_BDF(bus, devnum, 0); + bdf <= PCI_BDF(bus, devnum, + PCI_MAX_PCI_FUNCTIONS - 1); + bdf += PCI_BDF(0, 0, 1)) { + pci_read_config_dword(bdf, PCI_CLASS_REVISION, + &class); + if ((class >> 8 == PCI_CLASS_SERIAL_USB_EHCI) + && !index--) + return bdf; + } + } + } + + return -ENODEV; +} #endif /* * Create the appropriate control structures to manage * a new EHCI host controller. */ -int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +int ehci_hcd_init(int index, struct ehci_hccr **ret_hccr, + struct ehci_hcor **ret_hcor) { pci_dev_t pdev; + uint32_t cmd; + struct ehci_hccr *hccr; + struct ehci_hcor *hcor; +#ifdef CONFIG_PCI_EHCI_DEVICE pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE); - if (pdev == -1) { +#else + pdev = ehci_find_class(index); +#endif + if (pdev < 0) { printf("EHCI host controller not found\n"); return -1; } - *hccr = (struct ehci_hccr *)pci_map_bar(pdev, + hccr = (struct ehci_hccr *)pci_map_bar(pdev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + hcor = (struct ehci_hcor *)((uint32_t) hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", - (uint32_t)*hccr, (uint32_t)*hcor, - (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + (uint32_t)hccr, (uint32_t)hcor, + (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + *ret_hccr = hccr; + *ret_hcor = hcor; + /* enable busmaster */ + pci_read_config_dword(pdev, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER; + pci_write_config_dword(pdev, PCI_COMMAND, cmd); return 0; } diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c new file mode 100644 index 0000000..f99bd1f --- /dev/null +++ b/drivers/usb/host/ehci-spear.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2010 + * Armando Visconti, ST Micoelectronics, <armando.visconti@st.com>. + * + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <usb.h> +#include "ehci.h" +#include <asm/arch/hardware.h> + + +/* + * Create the appropriate control structures to manage + * a new EHCI host controller. + */ +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + *hccr = (struct ehci_hccr *)(CONFIG_SYS_UHC0_EHCI_BASE + 0x100); + *hcor = (struct ehci_hcor *)((uint32_t)*hccr + + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + + debug("SPEAr-ehci: init hccr %x and hcor %x hc_length %d\n", + (uint32_t)*hccr, (uint32_t)*hcor, + (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(int index) +{ + return 0; +} diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 1e3cd79..d090f0a 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -69,6 +69,7 @@ struct ehci_hcor { #define CMD_RUN (1 << 0) /* start/stop HC */ uint32_t or_usbsts; #define STS_ASS (1 << 15) +#define STS_PSS (1 << 14) #define STS_HALT (1 << 12) uint32_t or_usbintr; #define INTR_UE (1 << 0) /* USB interrupt enable */ @@ -245,7 +246,10 @@ struct QH { * Add dummy fill value to make the size of this struct * aligned to 32 bytes */ - uint8_t fill[16]; + union { + uint32_t fill[4]; + void *buffer; + }; }; /* Low level init functions */ diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c index bdbe250..bc17b85 100644 --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -66,7 +66,6 @@ #if defined(CONFIG_ARM920T) || \ defined(CONFIG_S3C24X0) || \ - defined(CONFIG_S3C6400) || \ defined(CONFIG_440EP) || \ defined(CONFIG_PCI_OHCI) || \ defined(CONFIG_MPC5200) || \ diff --git a/drivers/usb/musb-new/linux-compat.h b/drivers/usb/musb-new/linux-compat.h index 5c126ef..72c8c2b 100644 --- a/drivers/usb/musb-new/linux-compat.h +++ b/drivers/usb/musb-new/linux-compat.h @@ -12,8 +12,6 @@ #define __iomem #define __deprecated -typedef enum { false = 0, true = 1 } bool; - struct unused {}; typedef struct unused unused_t; diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c index 040a5c0..da93571 100644 --- a/drivers/usb/musb-new/musb_core.c +++ b/drivers/usb/musb-new/musb_core.c @@ -943,7 +943,9 @@ void musb_start(struct musb *musb) /* put into basic highspeed mode and start session */ musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE +#ifdef CONFIG_USB_GADGET_DUALSPEED | MUSB_POWER_HSENAB +#endif /* ENSUSPEND wedges tusb */ /* | MUSB_POWER_ENSUSPEND */ ); @@ -1421,6 +1423,7 @@ static int __devinit musb_core_init(u16 musb_type, struct musb *musb) strcat(aInfo, ", dyn FIFOs"); musb->dyn_fifo = true; } +#ifndef CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT if (reg & MUSB_CONFIGDATA_MPRXE) { strcat(aInfo, ", bulk combine"); musb->bulk_combine = true; @@ -1429,6 +1432,10 @@ static int __devinit musb_core_init(u16 musb_type, struct musb *musb) strcat(aInfo, ", bulk split"); musb->bulk_split = true; } +#else + musb->bulk_combine = false; + musb->bulk_split = false; +#endif if (reg & MUSB_CONFIGDATA_HBRXE) { strcat(aInfo, ", HB-ISO Rx"); musb->hb_iso_rx = true; diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c index 762cbc1..15d2ec0 100644 --- a/drivers/usb/musb-new/musb_uboot.c +++ b/drivers/usb/musb-new/musb_uboot.c @@ -174,7 +174,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver) { int ret; - if (!driver || driver->speed < USB_SPEED_HIGH || !driver->bind || + if (!driver || driver->speed < USB_SPEED_FULL || !driver->bind || !driver->setup) { printf("bad parameter.\n"); return -EINVAL; diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 170a358..53952ab 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -35,11 +35,13 @@ COBJS-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \ exynos_mipi_dsi_lowlevel.o COBJS-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o +COBJS-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o +COBJS-$(CONFIG_PXA_LCD) += pxa_lcd.o COBJS-$(CONFIG_S6E8AX0) += s6e8ax0.o COBJS-$(CONFIG_S6E63D6) += s6e63d6.o COBJS-$(CONFIG_LD9040) += ld9040.o COBJS-$(CONFIG_SED156X) += sed156x.o -COBJS-$(CONFIG_VIDEO_AMBA) += amba.o +COBJS-$(CONFIG_VIDEO_BCM2835) += bcm2835.o COBJS-$(CONFIG_VIDEO_COREBOOT) += coreboot_fb.o COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o COBJS-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o diff --git a/drivers/video/amba.c b/drivers/video/amba.c deleted file mode 100644 index ffa1c39..0000000 --- a/drivers/video/amba.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Driver for AMBA PrimeCell CLCD - * - * Copyright (C) 2009 Alessandro Rubini - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <lcd.h> -#include <amba_clcd.h> - -/* These variables are required by lcd.c -- although it sets them by itself */ -int lcd_line_length; -int lcd_color_fg; -int lcd_color_bg; -void *lcd_base; -void *lcd_console_address; -short console_col; -short console_row; - -/* - * To use this driver you need to provide the following in board files: - * a panel_info definition - * an lcd_enable function (can't define a weak default with current code) - */ - -/* There is nothing to do with color registers, we use true color */ -void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) -{ - return; -} - -/* Low level initialization of the logic cell: depends on panel_info */ -void lcd_ctrl_init(void *lcdbase) -{ - struct clcd_config *config; - struct clcd_registers *regs; - u32 cntl; - - config = panel_info.priv; - regs = config->address; - cntl = config->cntl & ~CNTL_LCDEN; - - /* Lazily, just copy the registers over: first control with disable */ - writel(cntl, ®s->cntl); - - writel(config->tim0, ®s->tim0); - writel(config->tim1, ®s->tim1); - writel(config->tim2, ®s->tim2); - writel(config->tim3, ®s->tim3); - writel((u32)lcdbase, ®s->ubas); - /* finally, enable */ - writel(cntl | CNTL_LCDEN, ®s->cntl); -} - -/* This is trivial, and copied from atmel_lcdfb.c */ -ulong calc_fbsize(void) -{ - return ((panel_info.vl_col * panel_info.vl_row * - NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE; -} diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index b10ca4b..fc95897 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -29,16 +29,6 @@ #include <lcd.h> #include <atmel_hlcdc.h> -int lcd_line_length; -int lcd_color_fg; -int lcd_color_bg; - -void *lcd_base; /* Start of framebuffer memory */ -void *lcd_console_address; /* Start of console buffer */ - -short console_col; -short console_row; - /* configurable parameters */ #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 #define ATMEL_LCDC_DMA_BURST_LEN 8 diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index c02ffd8..2afeab2 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -29,16 +29,6 @@ #include <lcd.h> #include <atmel_lcdc.h> -int lcd_line_length; -int lcd_color_fg; -int lcd_color_bg; - -void *lcd_base; /* Start of framebuffer memory */ -void *lcd_console_address; /* Start of console buffer */ - -short console_col; -short console_row; - /* configurable parameters */ #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 #define ATMEL_LCDC_DMA_BURST_LEN 8 diff --git a/drivers/video/bcm2835.c b/drivers/video/bcm2835.c new file mode 100644 index 0000000..0c77d17 --- /dev/null +++ b/drivers/video/bcm2835.c @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2012 Stephen Warren + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <common.h> +#include <lcd.h> +#include <asm/arch/mbox.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Global variables that lcd.c expects to exist */ +vidinfo_t panel_info; + +struct msg_query { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_physical_w_h physical_w_h; + u32 end_tag; +}; + +struct msg_setup { + struct bcm2835_mbox_hdr hdr; + struct bcm2835_mbox_tag_physical_w_h physical_w_h; + struct bcm2835_mbox_tag_virtual_w_h virtual_w_h; + struct bcm2835_mbox_tag_depth depth; + struct bcm2835_mbox_tag_pixel_order pixel_order; + struct bcm2835_mbox_tag_alpha_mode alpha_mode; + struct bcm2835_mbox_tag_virtual_offset virtual_offset; + struct bcm2835_mbox_tag_overscan overscan; + struct bcm2835_mbox_tag_allocate_buffer allocate_buffer; + u32 end_tag; +}; + +void lcd_ctrl_init(void *lcdbase) +{ + ALLOC_ALIGN_BUFFER(struct msg_query, msg_query, 1, 16); + ALLOC_ALIGN_BUFFER(struct msg_setup, msg_setup, 1, 16); + int ret; + u32 w, h; + + debug("bcm2835: Query resolution...\n"); + + BCM2835_MBOX_INIT_HDR(msg_query); + BCM2835_MBOX_INIT_TAG_NO_REQ(&msg_query->physical_w_h, + GET_PHYSICAL_W_H); + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_query->hdr); + if (ret) { + printf("bcm2835: Could not query display resolution\n"); + /* FIXME: How to disable the LCD to prevent errors? hang()? */ + return; + } + + w = msg_query->physical_w_h.body.resp.width; + h = msg_query->physical_w_h.body.resp.height; + + debug("bcm2835: Setting up display for %d x %d\n", w, h); + + BCM2835_MBOX_INIT_HDR(msg_setup); + BCM2835_MBOX_INIT_TAG(&msg_setup->physical_w_h, SET_PHYSICAL_W_H); + msg_setup->physical_w_h.body.req.width = w; + msg_setup->physical_w_h.body.req.height = h; + BCM2835_MBOX_INIT_TAG(&msg_setup->virtual_w_h, SET_VIRTUAL_W_H); + msg_setup->virtual_w_h.body.req.width = w; + msg_setup->virtual_w_h.body.req.height = h; + BCM2835_MBOX_INIT_TAG(&msg_setup->depth, SET_DEPTH); + msg_setup->depth.body.req.bpp = 16; + BCM2835_MBOX_INIT_TAG(&msg_setup->pixel_order, SET_PIXEL_ORDER); + msg_setup->pixel_order.body.req.order = BCM2835_MBOX_PIXEL_ORDER_BGR; + BCM2835_MBOX_INIT_TAG(&msg_setup->alpha_mode, SET_ALPHA_MODE); + msg_setup->alpha_mode.body.req.alpha = BCM2835_MBOX_ALPHA_MODE_IGNORED; + BCM2835_MBOX_INIT_TAG(&msg_setup->virtual_offset, SET_VIRTUAL_OFFSET); + msg_setup->virtual_offset.body.req.x = 0; + msg_setup->virtual_offset.body.req.y = 0; + BCM2835_MBOX_INIT_TAG(&msg_setup->overscan, SET_OVERSCAN); + msg_setup->overscan.body.req.top = 0; + msg_setup->overscan.body.req.bottom = 0; + msg_setup->overscan.body.req.left = 0; + msg_setup->overscan.body.req.right = 0; + BCM2835_MBOX_INIT_TAG(&msg_setup->allocate_buffer, ALLOCATE_BUFFER); + msg_setup->allocate_buffer.body.req.alignment = 0x100; + + ret = bcm2835_mbox_call_prop(BCM2835_MBOX_PROP_CHAN, &msg_setup->hdr); + if (ret) { + printf("bcm2835: Could not configure display\n"); + /* FIXME: How to disable the LCD to prevent errors? hang()? */ + return; + } + + w = msg_setup->physical_w_h.body.resp.width; + h = msg_setup->physical_w_h.body.resp.height; + + debug("bcm2835: Final resolution is %d x %d\n", w, h); + + panel_info.vl_col = w; + panel_info.vl_row = h; + panel_info.vl_bpix = LCD_COLOR16; + + gd->fb_base = msg_setup->allocate_buffer.body.resp.fb_address; +} + +void lcd_enable(void) +{ +} diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 26f673a..61e1058 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -1515,13 +1515,6 @@ int video_display_bitmap(ulong bmp_image, int x, int y) padded_line = (((width * bpp + 7) / 8) + 3) & ~0x3; - /* - * Just ignore elements which are completely beyond screen - * dimensions. - */ - if ((x >= VIDEO_VISIBLE_COLS) || (y >= VIDEO_VISIBLE_ROWS)) - return 0; - #ifdef CONFIG_SPLASH_SCREEN_ALIGN if (x == BMP_ALIGN_CENTER) x = max(0, (VIDEO_VISIBLE_COLS - width) / 2); @@ -1534,6 +1527,13 @@ int video_display_bitmap(ulong bmp_image, int x, int y) y = max(0, VIDEO_VISIBLE_ROWS - height + y + 1); #endif /* CONFIG_SPLASH_SCREEN_ALIGN */ + /* + * Just ignore elements which are completely beyond screen + * dimensions. + */ + if ((x >= VIDEO_VISIBLE_COLS) || (y >= VIDEO_VISIBLE_ROWS)) + return 0; + if ((x + width) > VIDEO_VISIBLE_COLS) width = VIDEO_VISIBLE_COLS - x; if ((y + height) > VIDEO_VISIBLE_ROWS) diff --git a/drivers/video/exynos_dp.c b/drivers/video/exynos_dp.c index d72fa56..87bb907 100644 --- a/drivers/video/exynos_dp.c +++ b/drivers/video/exynos_dp.c @@ -27,11 +27,21 @@ #include <asm/arch/cpu.h> #include <asm/arch/dp_info.h> #include <asm/arch/dp.h> +#include <fdtdec.h> +#include <libfdt.h> #include "exynos_dp_lowlevel.h" +DECLARE_GLOBAL_DATA_PTR; + static struct exynos_dp_platform_data *dp_pd; +void __exynos_set_dp_phy(unsigned int onoff) +{ +} +void exynos_set_dp_phy(unsigned int onoff) + __attribute__((weak, alias("__exynos_set_dp_phy"))); + static void exynos_dp_disp_info(struct edp_disp_info *disp_info) { disp_info->h_total = disp_info->h_res + disp_info->h_sync_width + @@ -853,6 +863,62 @@ static unsigned int exynos_dp_config_video(struct edp_device_info *edp_info) return ret; } +#ifdef CONFIG_OF_CONTROL +int exynos_dp_parse_dt(const void *blob, struct edp_device_info *edp_info) +{ + unsigned int node = fdtdec_next_compatible(blob, 0, + COMPAT_SAMSUNG_EXYNOS5_DP); + if (node <= 0) { + debug("exynos_dp: Can't get device node for dp\n"); + return -ENODEV; + } + + edp_info->disp_info.h_res = fdtdec_get_int(blob, node, + "samsung,h-res", 0); + edp_info->disp_info.h_sync_width = fdtdec_get_int(blob, node, + "samsung,h-sync-width", 0); + edp_info->disp_info.h_back_porch = fdtdec_get_int(blob, node, + "samsung,h-back-porch", 0); + edp_info->disp_info.h_front_porch = fdtdec_get_int(blob, node, + "samsung,h-front-porch", 0); + edp_info->disp_info.v_res = fdtdec_get_int(blob, node, + "samsung,v-res", 0); + edp_info->disp_info.v_sync_width = fdtdec_get_int(blob, node, + "samsung,v-sync-width", 0); + edp_info->disp_info.v_back_porch = fdtdec_get_int(blob, node, + "samsung,v-back-porch", 0); + edp_info->disp_info.v_front_porch = fdtdec_get_int(blob, node, + "samsung,v-front-porch", 0); + edp_info->disp_info.v_sync_rate = fdtdec_get_int(blob, node, + "samsung,v-sync-rate", 0); + + edp_info->lt_info.lt_status = fdtdec_get_int(blob, node, + "samsung,lt-status", 0); + + edp_info->video_info.master_mode = fdtdec_get_int(blob, node, + "samsung,master-mode", 0); + edp_info->video_info.bist_mode = fdtdec_get_int(blob, node, + "samsung,bist-mode", 0); + edp_info->video_info.bist_pattern = fdtdec_get_int(blob, node, + "samsung,bist-pattern", 0); + edp_info->video_info.h_sync_polarity = fdtdec_get_int(blob, node, + "samsung,h-sync-polarity", 0); + edp_info->video_info.v_sync_polarity = fdtdec_get_int(blob, node, + "samsung,v-sync-polarity", 0); + edp_info->video_info.interlaced = fdtdec_get_int(blob, node, + "samsung,interlaced", 0); + edp_info->video_info.color_space = fdtdec_get_int(blob, node, + "samsung,color-space", 0); + edp_info->video_info.dynamic_range = fdtdec_get_int(blob, node, + "samsung,dynamic-range", 0); + edp_info->video_info.ycbcr_coeff = fdtdec_get_int(blob, node, + "samsung,ycbcr-coeff", 0); + edp_info->video_info.color_depth = fdtdec_get_int(blob, node, + "samsung,color-depth", 0); + return 0; +} +#endif + unsigned int exynos_init_dp(void) { unsigned int ret; @@ -864,16 +930,22 @@ unsigned int exynos_init_dp(void) return -EFAULT; } +#ifdef CONFIG_OF_CONTROL + if (exynos_dp_parse_dt(gd->fdt_blob, edp_info)) + debug("unable to parse DP DT node\n"); +#else edp_info = dp_pd->edp_dev_info; if (edp_info == NULL) { debug("failed to get edp_info data.\n"); return -EFAULT; } +#endif + + exynos_dp_set_base_addr(); exynos_dp_disp_info(&edp_info->disp_info); - if (dp_pd->phy_enable) - dp_pd->phy_enable(1); + exynos_set_dp_phy(1); ret = exynos_dp_init_dp(); if (ret != EXYNOS_DP_SUCCESS) { diff --git a/drivers/video/exynos_dp_lowlevel.c b/drivers/video/exynos_dp_lowlevel.c index 7b54c80..748d9b8 100644 --- a/drivers/video/exynos_dp_lowlevel.c +++ b/drivers/video/exynos_dp_lowlevel.c @@ -25,11 +25,34 @@ #include <asm/arch/cpu.h> #include <asm/arch/dp_info.h> #include <asm/arch/dp.h> +#include <fdtdec.h> +#include <libfdt.h> + +/* Declare global data pointer */ +DECLARE_GLOBAL_DATA_PTR; + +struct exynos_dp *dp_regs; + +void exynos_dp_set_base_addr(void) +{ +#ifdef CONFIG_OF_CONTROL + unsigned int node = fdtdec_next_compatible(gd->fdt_blob, + 0, COMPAT_SAMSUNG_EXYNOS5_DP); + if (node <= 0) + debug("exynos_dp: Can't get device node for dp\n"); + + dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob, + node, "reg"); + if (dp_regs == NULL) + debug("Can't get the DP base address\n"); +#else + dp_regs = (struct exynos_dp *)samsung_get_base_dp(); +#endif +} static void exynos_dp_enable_video_input(unsigned int enable) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = readl(&dp_regs->video_ctl1); reg &= ~VIDEO_EN_MASK; @@ -47,7 +70,6 @@ void exynos_dp_enable_video_bist(unsigned int enable) { /*enable video bist*/ unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = readl(&dp_regs->video_ctl4); reg &= ~VIDEO_BIST_MASK; @@ -64,7 +86,6 @@ void exynos_dp_enable_video_bist(unsigned int enable) void exynos_dp_enable_video_mute(unsigned int enable) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = readl(&dp_regs->video_ctl1); reg &= ~(VIDEO_MUTE_MASK); @@ -80,7 +101,6 @@ void exynos_dp_enable_video_mute(unsigned int enable) static void exynos_dp_init_analog_param(void) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* * Set termination @@ -129,7 +149,6 @@ static void exynos_dp_init_analog_param(void) static void exynos_dp_init_interrupt(void) { - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Set interrupt registers to initial states */ /* @@ -158,7 +177,6 @@ static void exynos_dp_init_interrupt(void) void exynos_dp_reset(void) { unsigned int reg_func_1; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /*dp tx sw reset*/ writel(RESET_DP_TX, &dp_regs->tx_sw_reset); @@ -186,7 +204,6 @@ void exynos_dp_reset(void) void exynos_dp_enable_sw_func(unsigned int enable) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = readl(&dp_regs->func_en1); reg &= ~(SW_FUNC_EN_N); @@ -202,7 +219,6 @@ void exynos_dp_enable_sw_func(unsigned int enable) unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = readl(&dp_regs->phy_pd); switch (block) { @@ -256,7 +272,6 @@ unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable) unsigned int exynos_dp_get_pll_lock_status(void) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = readl(&dp_regs->debug_ctl); @@ -269,7 +284,6 @@ unsigned int exynos_dp_get_pll_lock_status(void) static void exynos_dp_set_pll_power(unsigned int enable) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = readl(&dp_regs->pll_ctl); reg &= ~(DP_PLL_PD); @@ -285,7 +299,6 @@ int exynos_dp_init_analog_func(void) int ret = EXYNOS_DP_SUCCESS; unsigned int retry_cnt = 10; unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /*Power On All Analog block */ exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE); @@ -335,7 +348,6 @@ int exynos_dp_init_analog_func(void) void exynos_dp_init_hpd(void) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Clear interrupts releated to Hot Plug Dectect */ reg = HOTPLUG_CHG | HPD_LOST | PLUG; @@ -354,7 +366,6 @@ void exynos_dp_init_hpd(void) static inline void exynos_dp_reset_aux(void) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Disable AUX channel module */ reg = readl(&dp_regs->func_en2); @@ -367,7 +378,6 @@ static inline void exynos_dp_reset_aux(void) void exynos_dp_init_aux(void) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Clear inerrupts related to AUX channel */ reg = RPLY_RECEIV | AUX_ERR; @@ -395,7 +405,6 @@ void exynos_dp_init_aux(void) void exynos_dp_config_interrupt(void) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* 0: mask, 1: unmask */ reg = COMMON_INT_MASK_1; @@ -419,7 +428,6 @@ void exynos_dp_config_interrupt(void) unsigned int exynos_dp_get_plug_in_status(void) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = readl(&dp_regs->sys_ctl3); if (reg & HPD_STATUS) @@ -449,7 +457,6 @@ unsigned int exynos_dp_start_aux_transaction(void) unsigned int reg; unsigned int ret = 0; unsigned int retry_cnt; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Enable AUX CH operation */ reg = readl(&dp_regs->aux_ch_ctl2); @@ -498,7 +505,6 @@ unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr, unsigned char data) { unsigned int reg, ret; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Clear AUX CH data buffer */ reg = BUF_CLR; @@ -539,7 +545,6 @@ unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr, { unsigned int reg; int retval; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Clear AUX CH data buffer */ reg = BUF_CLR; @@ -583,7 +588,6 @@ unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr, unsigned int cur_data_idx; unsigned int retry_cnt; unsigned int ret = 0; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Clear AUX CH data buffer */ reg = BUF_CLR; @@ -649,7 +653,6 @@ unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr, unsigned int cur_data_idx; unsigned int retry_cnt; unsigned int ret = 0; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Clear AUX CH data buffer */ reg = BUF_CLR; @@ -711,7 +714,6 @@ int exynos_dp_select_i2c_device(unsigned int device_addr, { unsigned int reg; int retval; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Set EDID device address */ reg = device_addr; @@ -746,7 +748,6 @@ int exynos_dp_read_byte_from_i2c(unsigned int device_addr, unsigned int reg; int i; int retval; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); for (i = 0; i < 10; i++) { /* Clear AUX CH data buffer */ @@ -790,7 +791,6 @@ int exynos_dp_read_bytes_from_i2c(unsigned int device_addr, unsigned int cur_data_idx; unsigned int defer = 0; int retval = 0; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); for (i = 0; i < count; i += 16) { /* use 16 burst */ for (j = 0; j < 100; j++) { @@ -854,7 +854,6 @@ int exynos_dp_read_bytes_from_i2c(unsigned int device_addr, void exynos_dp_reset_macro(void) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = readl(&dp_regs->phy_test); reg |= MACRO_RST; @@ -870,7 +869,6 @@ void exynos_dp_reset_macro(void) void exynos_dp_set_link_bandwidth(unsigned char bwtype) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = (unsigned int)bwtype; @@ -883,7 +881,6 @@ unsigned char exynos_dp_get_link_bandwidth(void) { unsigned char ret; unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = readl(&dp_regs->link_bw_set); ret = (unsigned char)reg; @@ -894,7 +891,6 @@ unsigned char exynos_dp_get_link_bandwidth(void) void exynos_dp_set_lane_count(unsigned char count) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = (unsigned int)count; @@ -906,7 +902,6 @@ void exynos_dp_set_lane_count(unsigned char count) unsigned int exynos_dp_get_lane_count(void) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = readl(&dp_regs->lane_count_set); @@ -915,7 +910,6 @@ unsigned int exynos_dp_get_lane_count(void) unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt) { - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); unsigned int reg_list[DP_LANE_CNT_4] = { (unsigned int)&dp_regs->ln0_link_training_ctl, (unsigned int)&dp_regs->ln1_link_training_ctl, @@ -929,7 +923,6 @@ unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt) void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val, unsigned char lanecnt) { - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); unsigned int reg_list[DP_LANE_CNT_4] = { (unsigned int)&dp_regs->ln0_link_training_ctl, (unsigned int)&dp_regs->ln1_link_training_ctl, @@ -944,7 +937,6 @@ void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt) { unsigned char i; unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); unsigned int reg_list[DP_LANE_CNT_4] = { (unsigned int)&dp_regs->ln0_link_training_ctl, (unsigned int)&dp_regs->ln1_link_training_ctl, @@ -967,7 +959,6 @@ void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt) void exynos_dp_set_training_pattern(unsigned int pattern) { unsigned int reg = 0; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); switch (pattern) { case PRBS7: @@ -996,7 +987,6 @@ void exynos_dp_set_training_pattern(unsigned int pattern) void exynos_dp_enable_enhanced_mode(unsigned char enable) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = readl(&dp_regs->sys_ctl4); reg &= ~ENHANCED; @@ -1010,7 +1000,6 @@ void exynos_dp_enable_enhanced_mode(unsigned char enable) void exynos_dp_enable_scrambling(unsigned int enable) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = readl(&dp_regs->training_ptn_set); reg &= ~(SCRAMBLING_DISABLE); @@ -1024,7 +1013,6 @@ void exynos_dp_enable_scrambling(unsigned int enable) int exynos_dp_init_video(void) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */ reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; @@ -1040,7 +1028,6 @@ int exynos_dp_init_video(void) void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Video Slave mode setting */ reg = readl(&dp_regs->func_en1); @@ -1074,7 +1061,6 @@ void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info) void exynos_dp_set_video_color_format(struct edp_video_info *video_info) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Configure the input color depth, color space, dynamic range */ reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) | @@ -1097,7 +1083,6 @@ int exynos_dp_config_video_bist(struct edp_device_info *edp_info) unsigned int reg; unsigned int bist_type = 0; struct edp_video_info video_info = edp_info->video_info; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* For master mode, you don't need to set the video format */ if (video_info.master_mode == 0) { @@ -1186,7 +1171,6 @@ int exynos_dp_config_video_bist(struct edp_device_info *edp_info) unsigned int exynos_dp_is_slave_video_stream_clock_on(void) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Update Video stream clk detect status */ reg = readl(&dp_regs->sys_ctl1); @@ -1206,7 +1190,6 @@ void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value, unsigned int n_value) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); if (type == REGISTER_M) { reg = readl(&dp_regs->sys_ctl4); @@ -1235,7 +1218,6 @@ void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value, void exynos_dp_set_video_timing_mode(unsigned int type) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = readl(&dp_regs->video_ctl10); reg &= ~FORMAT_SEL; @@ -1249,7 +1231,6 @@ void exynos_dp_set_video_timing_mode(unsigned int type) void exynos_dp_enable_video_master(unsigned int enable) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); reg = readl(&dp_regs->soc_general_ctl); if (enable) { @@ -1266,7 +1247,6 @@ void exynos_dp_enable_video_master(unsigned int enable) void exynos_dp_start_video(void) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Enable Video input and disable Mute */ reg = readl(&dp_regs->video_ctl1); @@ -1277,7 +1257,6 @@ void exynos_dp_start_video(void) unsigned int exynos_dp_is_video_stream_on(void) { unsigned int reg; - struct exynos_dp *dp_regs = (struct exynos_dp *)samsung_get_base_dp(); /* Update STRM_VALID */ reg = readl(&dp_regs->sys_ctl3); diff --git a/drivers/video/exynos_dp_lowlevel.h b/drivers/video/exynos_dp_lowlevel.h index a041a7a..2c0ae12 100644 --- a/drivers/video/exynos_dp_lowlevel.h +++ b/drivers/video/exynos_dp_lowlevel.h @@ -76,5 +76,6 @@ void exynos_dp_set_video_timing_mode(unsigned int type); void exynos_dp_enable_video_master(unsigned int enable); void exynos_dp_start_video(void); unsigned int exynos_dp_is_video_stream_on(void); +void exynos_dp_set_base_addr(void); #endif /* _EXYNOS_DP_LOWLEVEL_H */ diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index ee0ed06..ed0823b 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -23,6 +23,8 @@ #include <config.h> #include <common.h> #include <lcd.h> +#include <fdtdec.h> +#include <libfdt.h> #include <asm/io.h> #include <asm/arch/cpu.h> #include <asm/arch/clock.h> @@ -30,21 +32,28 @@ #include <asm/arch/mipi_dsim.h> #include <asm/arch/dp_info.h> #include <asm/arch/system.h> +#include <asm-generic/errno.h> #include "exynos_fb.h" -int lcd_line_length; -int lcd_color_fg; -int lcd_color_bg; - -void *lcd_base; -void *lcd_console_address; - -short console_col; -short console_row; +DECLARE_GLOBAL_DATA_PTR; static unsigned int panel_width, panel_height; +/* + * board_init_f(arch/arm/lib/board.c) calls lcd_setmem() which needs + * panel_info.vl_col, panel_info.vl_row and panel_info.vl_bpix to reserve + * FB memory at a very early stage, i.e even before exynos_fimd_parse_dt() + * is called. So, we are forced to statically assign it. + */ +#ifdef CONFIG_OF_CONTROL +vidinfo_t panel_info = { + .vl_col = LCD_XRES, + .vl_row = LCD_YRES, + .vl_bpix = LCD_COLOR16, +}; +#endif + static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid) { unsigned long palette_size; @@ -52,11 +61,9 @@ static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid) fb_size = vid->vl_row * vid->vl_col * (NBITS(vid->vl_bpix) >> 3); - lcd_base = lcdbase; - palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16; - exynos_fimd_lcd_init_mem((unsigned long)lcd_base, + exynos_fimd_lcd_init_mem((unsigned long)lcdbase, (unsigned long)fb_size, palette_size); } @@ -93,47 +100,226 @@ static void draw_logo(void) } #endif +void __exynos_cfg_lcd_gpio(void) +{ +} +void exynos_cfg_lcd_gpio(void) + __attribute__((weak, alias("__exynos_cfg_lcd_gpio"))); + +void __exynos_backlight_on(unsigned int onoff) +{ +} +void exynos_backlight_on(unsigned int onoff) + __attribute__((weak, alias("__exynos_cfg_lcd_gpio"))); + +void __exynos_reset_lcd(void) +{ +} +void exynos_reset_lcd(void) + __attribute__((weak, alias("__exynos_reset_lcd"))); + +void __exynos_lcd_power_on(void) +{ +} +void exynos_lcd_power_on(void) + __attribute__((weak, alias("__exynos_lcd_power_on"))); + +void __exynos_cfg_ldo(void) +{ +} +void exynos_cfg_ldo(void) + __attribute__((weak, alias("__exynos_cfg_ldo"))); + +void __exynos_enable_ldo(unsigned int onoff) +{ +} +void exynos_enable_ldo(unsigned int onoff) + __attribute__((weak, alias("__exynos_enable_ldo"))); + +void __exynos_backlight_reset(void) +{ +} +void exynos_backlight_reset(void) + __attribute__((weak, alias("__exynos_backlight_reset"))); + static void lcd_panel_on(vidinfo_t *vid) { udelay(vid->init_delay); - if (vid->backlight_reset) - vid->backlight_reset(); + exynos_backlight_reset(); - if (vid->cfg_gpio) - vid->cfg_gpio(); + exynos_cfg_lcd_gpio(); - if (vid->lcd_power_on) - vid->lcd_power_on(); + exynos_lcd_power_on(); udelay(vid->power_on_delay); if (vid->dp_enabled) exynos_init_dp(); - if (vid->reset_lcd) { - vid->reset_lcd(); - udelay(vid->reset_delay); - } + exynos_reset_lcd(); + + udelay(vid->reset_delay); - if (vid->backlight_on) - vid->backlight_on(1); + exynos_backlight_on(1); - if (vid->cfg_ldo) - vid->cfg_ldo(); + exynos_cfg_ldo(); - if (vid->enable_ldo) - vid->enable_ldo(1); + exynos_enable_ldo(1); if (vid->mipi_enabled) exynos_mipi_dsi_init(); } +#ifdef CONFIG_OF_CONTROL +int exynos_fimd_parse_dt(const void *blob) +{ + unsigned int node; + node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS_FIMD); + if (node <= 0) { + debug("exynos_fb: Can't get device node for fimd\n"); + return -ENODEV; + } + + panel_info.vl_col = fdtdec_get_int(blob, node, "samsung,vl-col", 0); + if (panel_info.vl_col == 0) { + debug("Can't get XRES\n"); + return -ENXIO; + } + + panel_info.vl_row = fdtdec_get_int(blob, node, "samsung,vl-row", 0); + if (panel_info.vl_row == 0) { + debug("Can't get YRES\n"); + return -ENXIO; + } + + panel_info.vl_width = fdtdec_get_int(blob, node, + "samsung,vl-width", 0); + + panel_info.vl_height = fdtdec_get_int(blob, node, + "samsung,vl-height", 0); + + panel_info.vl_freq = fdtdec_get_int(blob, node, "samsung,vl-freq", 0); + if (panel_info.vl_freq == 0) { + debug("Can't get refresh rate\n"); + return -ENXIO; + } + + if (fdtdec_get_bool(blob, node, "samsung,vl-clkp")) + panel_info.vl_clkp = CONFIG_SYS_LOW; + + if (fdtdec_get_bool(blob, node, "samsung,vl-oep")) + panel_info.vl_oep = CONFIG_SYS_LOW; + + if (fdtdec_get_bool(blob, node, "samsung,vl-hsp")) + panel_info.vl_hsp = CONFIG_SYS_LOW; + + if (fdtdec_get_bool(blob, node, "samsung,vl-vsp")) + panel_info.vl_vsp = CONFIG_SYS_LOW; + + if (fdtdec_get_bool(blob, node, "samsung,vl-dp")) + panel_info.vl_dp = CONFIG_SYS_LOW; + + panel_info.vl_bpix = fdtdec_get_int(blob, node, "samsung,vl-bpix", 0); + if (panel_info.vl_bpix == 0) { + debug("Can't get bits per pixel\n"); + return -ENXIO; + } + + panel_info.vl_hspw = fdtdec_get_int(blob, node, "samsung,vl-hspw", 0); + if (panel_info.vl_hspw == 0) { + debug("Can't get hsync width\n"); + return -ENXIO; + } + + panel_info.vl_hfpd = fdtdec_get_int(blob, node, "samsung,vl-hfpd", 0); + if (panel_info.vl_hfpd == 0) { + debug("Can't get right margin\n"); + return -ENXIO; + } + + panel_info.vl_hbpd = (u_char)fdtdec_get_int(blob, node, + "samsung,vl-hbpd", 0); + if (panel_info.vl_hbpd == 0) { + debug("Can't get left margin\n"); + return -ENXIO; + } + + panel_info.vl_vspw = (u_char)fdtdec_get_int(blob, node, + "samsung,vl-vspw", 0); + if (panel_info.vl_vspw == 0) { + debug("Can't get vsync width\n"); + return -ENXIO; + } + + panel_info.vl_vfpd = fdtdec_get_int(blob, node, + "samsung,vl-vfpd", 0); + if (panel_info.vl_vfpd == 0) { + debug("Can't get lower margin\n"); + return -ENXIO; + } + + panel_info.vl_vbpd = fdtdec_get_int(blob, node, "samsung,vl-vbpd", 0); + if (panel_info.vl_vbpd == 0) { + debug("Can't get upper margin\n"); + return -ENXIO; + } + + panel_info.vl_cmd_allow_len = fdtdec_get_int(blob, node, + "samsung,vl-cmd-allow-len", 0); + + panel_info.win_id = fdtdec_get_int(blob, node, "samsung,winid", 0); + panel_info.init_delay = fdtdec_get_int(blob, node, + "samsung,init-delay", 0); + panel_info.power_on_delay = fdtdec_get_int(blob, node, + "samsung,power-on-delay", 0); + panel_info.reset_delay = fdtdec_get_int(blob, node, + "samsung,reset-delay", 0); + panel_info.interface_mode = fdtdec_get_int(blob, node, + "samsung,interface-mode", 0); + panel_info.mipi_enabled = fdtdec_get_int(blob, node, + "samsung,mipi-enabled", 0); + panel_info.dp_enabled = fdtdec_get_int(blob, node, + "samsung,dp-enabled", 0); + panel_info.cs_setup = fdtdec_get_int(blob, node, + "samsung,cs-setup", 0); + panel_info.wr_setup = fdtdec_get_int(blob, node, + "samsung,wr-setup", 0); + panel_info.wr_act = fdtdec_get_int(blob, node, "samsung,wr-act", 0); + panel_info.wr_hold = fdtdec_get_int(blob, node, "samsung,wr-hold", 0); + + panel_info.logo_on = fdtdec_get_int(blob, node, "samsung,logo-on", 0); + if (panel_info.logo_on) { + panel_info.logo_width = fdtdec_get_int(blob, node, + "samsung,logo-width", 0); + panel_info.logo_height = fdtdec_get_int(blob, node, + "samsung,logo-height", 0); + panel_info.logo_addr = fdtdec_get_int(blob, node, + "samsung,logo-addr", 0); + } + + panel_info.rgb_mode = fdtdec_get_int(blob, node, + "samsung,rgb-mode", 0); + panel_info.pclk_name = fdtdec_get_int(blob, node, + "samsung,pclk-name", 0); + panel_info.sclk_div = fdtdec_get_int(blob, node, + "samsung,sclk-div", 0); + panel_info.dual_lcd_enabled = fdtdec_get_int(blob, node, + "samsung,dual-lcd-enabled", 0); + + return 0; +} +#endif + void lcd_ctrl_init(void *lcdbase) { set_system_display_ctrl(); set_lcd_clk(); +#ifdef CONFIG_OF_CONTROL + if (exynos_fimd_parse_dt(gd->fdt_blob)) + debug("Can't get proper panel info\n"); +#endif /* initialize parameters which is specific to panel. */ init_panel_info(&panel_info); @@ -148,7 +334,7 @@ void lcd_ctrl_init(void *lcdbase) void lcd_enable(void) { if (panel_info.logo_on) { - memset(lcd_base, 0, panel_width * panel_height * + memset((void *) gd->fb_base, 0, panel_width * panel_height * (NBITS(panel_info.vl_bpix) >> 3)); #ifdef CONFIG_CMD_BMP draw_logo(); diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c index 2efe6a6..3359949 100644 --- a/drivers/video/exynos_fimd.c +++ b/drivers/video/exynos_fimd.c @@ -25,13 +25,18 @@ #include <asm/io.h> #include <lcd.h> #include <div64.h> +#include <fdtdec.h> +#include <libfdt.h> #include <asm/arch/clk.h> #include <asm/arch/clock.h> #include <asm/arch/cpu.h> #include "exynos_fb.h" +DECLARE_GLOBAL_DATA_PTR; + static unsigned long *lcd_base_addr; static vidinfo_t *pvid; +static struct exynos_fb *fimd_ctrl; void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, u_long palette_size) @@ -41,8 +46,6 @@ void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size, static void exynos_fimd_set_dualrgb(unsigned int enabled) { - struct exynos_fb *fimd_ctrl = - (struct exynos_fb *)samsung_get_base_fimd(); unsigned int cfg = 0; if (enabled) { @@ -59,9 +62,6 @@ static void exynos_fimd_set_dualrgb(unsigned int enabled) static void exynos_fimd_set_dp_clkcon(unsigned int enabled) { - - struct exynos_fb *fimd_ctrl = - (struct exynos_fb *)samsung_get_base_fimd(); unsigned int cfg = 0; if (enabled) @@ -73,8 +73,6 @@ static void exynos_fimd_set_dp_clkcon(unsigned int enabled) static void exynos_fimd_set_par(unsigned int win_id) { unsigned int cfg = 0; - struct exynos_fb *fimd_ctrl = - (struct exynos_fb *)samsung_get_base_fimd(); /* set window control */ cfg = readl((unsigned int)&fimd_ctrl->wincon0 + @@ -126,8 +124,6 @@ static void exynos_fimd_set_par(unsigned int win_id) static void exynos_fimd_set_buffer_address(unsigned int win_id) { unsigned long start_addr, end_addr; - struct exynos_fb *fimd_ctrl = - (struct exynos_fb *)samsung_get_base_fimd(); start_addr = (unsigned long)lcd_base_addr; end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) * @@ -144,8 +140,6 @@ static void exynos_fimd_set_clock(vidinfo_t *pvid) unsigned int cfg = 0, div = 0, remainder, remainder_div; unsigned long pixel_clock; unsigned long long src_clock; - struct exynos_fb *fimd_ctrl = - (struct exynos_fb *)samsung_get_base_fimd(); if (pvid->dual_lcd_enabled) { pixel_clock = pvid->vl_freq * @@ -197,8 +191,6 @@ static void exynos_fimd_set_clock(vidinfo_t *pvid) void exynos_set_trigger(void) { unsigned int cfg = 0; - struct exynos_fb *fimd_ctrl = - (struct exynos_fb *)samsung_get_base_fimd(); cfg = readl(&fimd_ctrl->trigcon); @@ -211,8 +203,6 @@ int exynos_is_i80_frame_done(void) { unsigned int cfg = 0; int status; - struct exynos_fb *fimd_ctrl = - (struct exynos_fb *)samsung_get_base_fimd(); cfg = readl(&fimd_ctrl->trigcon); @@ -226,8 +216,6 @@ int exynos_is_i80_frame_done(void) static void exynos_fimd_lcd_on(void) { unsigned int cfg = 0; - struct exynos_fb *fimd_ctrl = - (struct exynos_fb *)samsung_get_base_fimd(); /* display on */ cfg = readl(&fimd_ctrl->vidcon0); @@ -238,8 +226,6 @@ static void exynos_fimd_lcd_on(void) static void exynos_fimd_window_on(unsigned int win_id) { unsigned int cfg = 0; - struct exynos_fb *fimd_ctrl = - (struct exynos_fb *)samsung_get_base_fimd(); /* enable window */ cfg = readl((unsigned int)&fimd_ctrl->wincon0 + @@ -256,8 +242,6 @@ static void exynos_fimd_window_on(unsigned int win_id) void exynos_fimd_lcd_off(void) { unsigned int cfg = 0; - struct exynos_fb *fimd_ctrl = - (struct exynos_fb *)samsung_get_base_fimd(); cfg = readl(&fimd_ctrl->vidcon0); cfg &= (EXYNOS_VIDCON0_ENVID_DISABLE | EXYNOS_VIDCON0_ENVID_F_DISABLE); @@ -267,8 +251,6 @@ void exynos_fimd_lcd_off(void) void exynos_fimd_window_off(unsigned int win_id) { unsigned int cfg = 0; - struct exynos_fb *fimd_ctrl = - (struct exynos_fb *)samsung_get_base_fimd(); cfg = readl((unsigned int)&fimd_ctrl->wincon0 + EXYNOS_WINCON(win_id)); @@ -286,8 +268,20 @@ void exynos_fimd_lcd_init(vidinfo_t *vid) { unsigned int cfg = 0, rgb_mode; unsigned int offset; - struct exynos_fb *fimd_ctrl = - (struct exynos_fb *)samsung_get_base_fimd(); +#ifdef CONFIG_OF_CONTROL + unsigned int node; + + node = fdtdec_next_compatible(gd->fdt_blob, + 0, COMPAT_SAMSUNG_EXYNOS_FIMD); + if (node <= 0) + debug("exynos_fb: Can't get device node for fimd\n"); + + fimd_ctrl = (struct exynos_fb *)fdtdec_get_addr(gd->fdt_blob, + node, "reg"); + if (fimd_ctrl == NULL) + debug("Can't get the FIMD base address\n"); +#endif + fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd(); offset = exynos_fimd_get_base_offset(); diff --git a/arch/powerpc/cpu/mpc8xx/lcd.c b/drivers/video/mpc8xx_lcd.c index 4b88b21..f0f728e 100644 --- a/arch/powerpc/cpu/mpc8xx/lcd.c +++ b/drivers/video/mpc8xx_lcd.c @@ -253,40 +253,6 @@ vidinfo_t panel_info = { LCD_BPP, 0, 0, 0, 0, 33, 0, 0, 0 }; #endif -/*----------------------------------------------------------------------*/ - - -int lcd_line_length; - -int lcd_color_fg; -int lcd_color_bg; - -/* - * Frame buffer memory information - */ -void *lcd_base; /* Start of framebuffer memory */ -void *lcd_console_address; /* Start of console buffer */ - -short console_col; -short console_row; - -/************************************************************************/ - -void lcd_ctrl_init (void *lcdbase); -void lcd_enable (void); -#if LCD_BPP == LCD_COLOR8 -void lcd_setcolreg (ushort regno, - ushort red, ushort green, ushort blue); -#endif -#if LCD_BPP == LCD_MONOCHROME -void lcd_initcolregs (void); -#endif - -#if defined(CONFIG_RBC823) -void lcd_disable (void); -#endif - -/************************************************************************/ /************************************************************************/ /* ----------------- chipset specific functions ----------------------- */ @@ -401,8 +367,8 @@ void lcd_ctrl_init (void *lcdbase) * BIG NOTE: This has to be modified to load A and B depending * upon the split mode of the LCD. */ - lcdp->lcd_lcfaa = (ulong)lcd_base; - lcdp->lcd_lcfba = (ulong)lcd_base; + lcdp->lcd_lcfaa = (ulong)lcdbase; + lcdp->lcd_lcfba = (ulong)lcdbase; /* MORE HACKS...This must be updated according to 823 manual * for different panels. @@ -432,29 +398,6 @@ void lcd_ctrl_init (void *lcdbase) /*----------------------------------------------------------------------*/ -#ifdef NOT_USED_SO_FAR -static void -lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue) -{ - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile cpm8xx_t *cp = &(immr->im_cpm); - unsigned short colreg, *cmap_ptr; - - cmap_ptr = (unsigned short *)&cp->lcd_cmap[regno * 2]; - - colreg = *cmap_ptr; -#ifdef CONFIG_SYS_INVERT_COLORS - colreg ^= 0x0FFF; -#endif - - *red = (colreg >> 8) & 0x0F; - *green = (colreg >> 4) & 0x0F; - *blue = colreg & 0x0F; -} -#endif /* NOT_USED_SO_FAR */ - -/*----------------------------------------------------------------------*/ - #if LCD_BPP == LCD_COLOR8 void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) diff --git a/arch/arm/cpu/pxa/pxafb.c b/drivers/video/pxa_lcd.c index 987fa06..b40ec36 100644 --- a/arch/arm/cpu/pxa/pxafb.c +++ b/drivers/video/pxa_lcd.c @@ -317,36 +317,10 @@ vidinfo_t panel_info = { /*----------------------------------------------------------------------*/ -#if LCD_BPP == LCD_COLOR8 -void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue); -#endif -#if LCD_BPP == LCD_MONOCHROME -void lcd_initcolregs (void); -#endif - -#ifdef NOT_USED_SO_FAR -void lcd_disable (void); -void lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue); -#endif /* NOT_USED_SO_FAR */ - -void lcd_ctrl_init (void *lcdbase); -void lcd_enable (void); - -int lcd_line_length; -int lcd_color_fg; -int lcd_color_bg; - -void *lcd_base; /* Start of framebuffer memory */ -void *lcd_console_address; /* Start of console buffer */ - -short console_col; -short console_row; - static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid); static void pxafb_setup_gpio (vidinfo_t *vid); static void pxafb_enable_controller (vidinfo_t *vid); static int pxafb_init (vidinfo_t *vid); -/************************************************************************/ /************************************************************************/ /* --------------- PXA chipset specific functions ------------------- */ @@ -361,14 +335,6 @@ void lcd_ctrl_init (void *lcdbase) } /*----------------------------------------------------------------------*/ -#ifdef NOT_USED_SO_FAR -void -lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue) -{ -} -#endif /* NOT_USED_SO_FAR */ - -/*----------------------------------------------------------------------*/ #if LCD_BPP == LCD_COLOR8 void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) @@ -416,15 +382,6 @@ void lcd_enable (void) { } -/*----------------------------------------------------------------------*/ -#ifdef NOT_USED_SO_FAR -static void lcd_disable (void) -{ -} -#endif /* NOT_USED_SO_FAR */ - -/*----------------------------------------------------------------------*/ - /************************************************************************/ /* ** PXA255 specific routines */ /************************************************************************/ diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index afcb008..8d53395 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -60,77 +60,15 @@ enum { LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */ }; -int lcd_line_length; -int lcd_color_fg; -int lcd_color_bg; - -void *lcd_base; /* Start of framebuffer memory */ -void *lcd_console_address; /* Start of console buffer */ - -short console_col; -short console_row; - vidinfo_t panel_info = { /* Insert a value here so that we don't end up in the BSS */ .vl_col = -1, }; -char lcd_cursor_enabled; - -ushort lcd_cursor_width; -ushort lcd_cursor_height; - #ifndef CONFIG_OF_CONTROL #error "You must enable CONFIG_OF_CONTROL to get Tegra LCD support" #endif -void lcd_cursor_size(ushort width, ushort height) -{ - lcd_cursor_width = width; - lcd_cursor_height = height; -} - -void lcd_toggle_cursor(void) -{ - ushort x, y; - uchar *dest; - ushort row; - - x = console_col * lcd_cursor_width; - y = console_row * lcd_cursor_height; - dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / - 8); - - for (row = 0; row < lcd_cursor_height; ++row, dest += lcd_line_length) { - ushort *d = (ushort *)dest; - ushort color; - int i; - - for (i = 0; i < lcd_cursor_width; ++i) { - color = *d; - color ^= lcd_color_fg; - *d = color; - ++d; - } - } -} - -void lcd_cursor_on(void) -{ - lcd_cursor_enabled = 1; - lcd_toggle_cursor(); -} -void lcd_cursor_off(void) -{ - lcd_cursor_enabled = 0; - lcd_toggle_cursor(); -} - -char lcd_is_cursor_enabled(void) -{ - return lcd_cursor_enabled; -} - static void update_panel_size(struct fdt_disp_config *config) { panel_info.vl_col = config->width; @@ -150,8 +88,6 @@ void lcd_ctrl_init(void *lcdbase) assert(disp_config); - lcd_base = (void *)disp_config->frame_buffer; - /* Make sure that we can acommodate the selected LCD */ assert(disp_config->width <= LCD_MAX_WIDTH); assert(disp_config->height <= LCD_MAX_HEIGHT); @@ -172,7 +108,7 @@ void lcd_ctrl_init(void *lcdbase) /* Enable flushing after LCD writes if requested */ lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH); - debug("LCD frame buffer at %p\n", lcd_base); + debug("LCD frame buffer at %08X\n", disp_config->frame_buffer); } ulong calc_fbsize(void) diff --git a/dts/Makefile b/dts/Makefile index 6f36153..03e163e 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -27,9 +27,11 @@ include $(TOPDIR)/config.mk LIB = $(obj)libdts.o +ifeq ($(DEVICE_TREE),) $(if $(CONFIG_DEFAULT_DEVICE_TREE),,\ $(error Please define CONFIG_DEFAULT_DEVICE_TREE in your board header file)) DEVICE_TREE = $(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE)) +endif $(if $(CONFIG_ARCH_DEVICE_TREE),,\ $(error Your architecture does not have device tree support enabled. \ diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c index 15e9afc..8fb1765 100644 --- a/examples/standalone/stubs.c +++ b/examples/standalone/stubs.c @@ -217,16 +217,15 @@ void __attribute__((unused)) dummy(void) #include <_exports.h> } -extern unsigned long __bss_start, _end; +#include <asm/sections.h> void app_startup(char * const *argv) { - unsigned char * cp = (unsigned char *) &__bss_start; + char *cp = __bss_start; /* Zero out BSS */ - while (cp < (unsigned char *)&_end) { + while (cp < _end) *cp++ = 0; - } #if defined(CONFIG_X86) /* x86 does not have a dedicated register for passing global_data */ diff --git a/fs/ext4/ext4_common.h b/fs/ext4/ext4_common.h index 87cab16..72cd020 100644 --- a/fs/ext4/ext4_common.h +++ b/fs/ext4/ext4_common.h @@ -44,8 +44,6 @@ #define YES 1 #define NO 0 -#define TRUE 1 -#define FALSE 0 #define RECOVER 1 #define SCAN 0 diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c index 9f01708..ba4a7bb 100644 --- a/fs/ext4/ext4_journal.c +++ b/fs/ext4/ext4_journal.c @@ -37,7 +37,7 @@ static struct revoke_blk_list *revk_blk_list; static struct revoke_blk_list *prev_node; -static int first_node = TRUE; +static int first_node = true; int gindex; int gd_index; @@ -268,10 +268,10 @@ void ext4fs_push_revoke_blk(char *buffer) return; memcpy(node->content, buffer, fs->blksz); - if (first_node == TRUE) { + if (first_node == true) { revk_blk_list = node; prev_node = node; - first_node = FALSE; + first_node = false; } else { prev_node->next = node; prev_node = node; @@ -298,7 +298,7 @@ void ext4fs_free_revoke_blks(void) revk_blk_list = NULL; prev_node = NULL; - first_node = TRUE; + first_node = true; } int check_blknr_for_revoke(long int blknr, int sequence_no) diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h index 0af471a..633631e 100644 --- a/fs/ubifs/ubifs.h +++ b/fs/ubifs/ubifs.h @@ -463,8 +463,12 @@ static inline ino_t parent_ino(struct dentry *dentry) #define UBIFS_VERSION 1 /* Normal UBIFS messages */ +#ifdef CONFIG_UBIFS_SILENCE_MSG +#define ubifs_msg(fmt, ...) +#else #define ubifs_msg(fmt, ...) \ printk(KERN_NOTICE "UBIFS: " fmt "\n", ##__VA_ARGS__) +#endif /* UBIFS error messages */ #define ubifs_err(fmt, ...) \ printk(KERN_ERR "UBIFS error (pid %d): %s: " fmt "\n", 0, \ diff --git a/board/samsung/smdk6400/smdk6400_nand_spl.c b/include/ansi.h index a023284..0e40b1d 100644 --- a/board/samsung/smdk6400/smdk6400_nand_spl.c +++ b/include/ansi.h @@ -1,13 +1,6 @@ /* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> + * (C) Copyright 2012 + * Pali Rohár <pali.rohar@gmail.com> * * See file CREDITS for list of people who contributed to this * project. @@ -28,10 +21,22 @@ * MA 02111-1307 USA */ -#include <common.h> +/* + * ANSI terminal + */ -void board_init_f(unsigned long bootflag) -{ - relocate_code(CONFIG_SYS_TEXT_BASE - TOTAL_MALLOC_LEN, NULL, - CONFIG_SYS_TEXT_BASE); -} +#define ANSI_CURSOR_UP "\e[%dA" +#define ANSI_CURSOR_DOWN "\e[%dB" +#define ANSI_CURSOR_FORWARD "\e[%dC" +#define ANSI_CURSOR_BACK "\e[%dD" +#define ANSI_CURSOR_NEXTLINE "\e[%dE" +#define ANSI_CURSOR_PREVIOUSLINE "\e[%dF" +#define ANSI_CURSOR_COLUMN "\e[%dG" +#define ANSI_CURSOR_POSITION "\e[%d;%dH" +#define ANSI_CURSOR_SHOW "\e[?25h" +#define ANSI_CURSOR_HIDE "\e[?25l" +#define ANSI_CLEAR_CONSOLE "\e[2J" +#define ANSI_CLEAR_LINE_TO_END "\e[0K" +#define ANSI_CLEAR_LINE "\e[2K" +#define ANSI_COLOR_RESET "\e[0m" +#define ANSI_COLOR_REVERSE "\e[7m" diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index b8ac024..5416f46 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -40,7 +40,7 @@ typedef struct global_data { bd_t *bd; unsigned long flags; - unsigned long baudrate; + unsigned int baudrate; unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long bus_clk; /* We cannot bracket this with CONFIG_PCI due to mpc5xxx */ @@ -81,6 +81,8 @@ typedef struct global_data { unsigned long reloc_off; struct global_data *new_gd; /* relocated global data */ const void *fdt_blob; /* Our device tree, NULL if none */ + void *new_fdt; /* Relocated FDT */ + unsigned long fdt_size; /* Space reserved for relocated FDT */ void **jt; /* jump table */ char env_buf[32]; /* buffer for getenv() before reloc. */ struct arch_global_data arch; /* architecture-specific data */ diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h new file mode 100644 index 0000000..cca1edb --- /dev/null +++ b/include/asm-generic/sections.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Taken from Linux kernel, commit f56c3196 */ + +#ifndef _ASM_GENERIC_SECTIONS_H_ +#define _ASM_GENERIC_SECTIONS_H_ + +/* References to section boundaries */ + +extern char _text[], _stext[], _etext[]; +extern char _data[], _sdata[], _edata[]; +extern char __bss_start[], __bss_stop[]; +extern char __init_begin[], __init_end[]; +extern char _sinittext[], _einittext[]; +extern char _end[]; +extern char __per_cpu_load[], __per_cpu_start[], __per_cpu_end[]; +extern char __kprobes_text_start[], __kprobes_text_end[]; +extern char __entry_text_start[], __entry_text_end[]; +extern char __initdata_begin[], __initdata_end[]; +extern char __start_rodata[], __end_rodata[]; + +/* Start and end of .ctors section - used for constructor calls. */ +extern char __ctors_start[], __ctors_end[]; + +/* function descriptor handling (if any). Override + * in asm/sections.h */ +#ifndef dereference_function_descriptor +#define dereference_function_descriptor(p) (p) +#endif + +/* random extra sections (if any). Override + * in asm/sections.h */ +#ifndef arch_is_kernel_text +static inline int arch_is_kernel_text(unsigned long addr) +{ + return 0; +} +#endif + +#ifndef arch_is_kernel_data +static inline int arch_is_kernel_data(unsigned long addr) +{ + return 0; +} +#endif + +/* U-Boot-specific things begin here */ + +/* Start of U-Boot text region */ +extern char __text_start[]; + +/* This marks the end of the text region which must be relocated */ +extern char __image_copy_end[]; + +/* + * This is the U-Boot entry point - prior to relocation it should be same + * as __text_start + */ +extern void _start(void); + +/* + * ARM needs to use offsets for symbols, since the values of some symbols + * are not resolved prior to relocation (and are just 0). Maybe this can be + * resolved, or maybe other architectures are similar, iwc this should be + * promoted to an architecture option. + */ +#ifdef CONFIG_ARM +#define CONFIG_SYS_SYM_OFFSETS +#endif + +#ifdef CONFIG_SYS_SYM_OFFSETS +/* Start/end of the relocation entries, as an offset from _start */ +extern ulong _rel_dyn_start_ofs; +extern ulong _rel_dyn_end_ofs; + +/* Start/end of the relocation symbol table, as an offset from _start */ +extern ulong _dynsym_start_ofs; + +/* End of the region to be relocated, as an offset form _start */ +extern ulong _image_copy_end_ofs; + +extern ulong _bss_start_ofs; /* BSS start relative to _start */ +extern ulong _bss_end_ofs; /* BSS end relative to _start */ +extern ulong _end_ofs; /* end of image relative to _start */ + +extern ulong _TEXT_BASE; /* code start */ + +#else /* don't use offsets: */ + +/* Exports from the Linker Script */ +extern ulong __data_end; +extern ulong __rel_dyn_start; +extern ulong __rel_dyn_end; +extern ulong __bss_end; + +extern ulong _TEXT_BASE; /* code start */ + +#endif + +#endif /* _ASM_GENERIC_SECTIONS_H_ */ diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h new file mode 100644 index 0000000..a9aa8ba --- /dev/null +++ b/include/asm-generic/u-boot.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * (C) Copyright 2000 - 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef __ASM_GENERIC_U_BOOT_H__ +#define __ASM_GENERIC_U_BOOT_H__ + +/* + * Board information passed to Linux kernel from U-Boot + * + * include/asm-ppc/u-boot.h + */ + +#ifndef __ASSEMBLY__ + +typedef struct bd_info { + unsigned long bi_memstart; /* start of DRAM memory */ + phys_size_t bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* reserved area for startup monitor */ + unsigned long bi_sramstart; /* start of SRAM memory */ + unsigned long bi_sramsize; /* size of SRAM memory */ +#ifdef CONFIG_ARM + unsigned long bi_arm_freq; /* arm frequency */ + unsigned long bi_dsp_freq; /* dsp core frequency */ + unsigned long bi_ddr_freq; /* ddr frequency */ +#endif +#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \ + || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) + unsigned long bi_immr_base; /* base of IMMR register */ +#endif +#if defined(CONFIG_MPC5xxx) + unsigned long bi_mbar_base; /* base of internal registers */ +#endif +#if defined(CONFIG_MPC83xx) + unsigned long bi_immrbar; +#endif +#if defined(CONFIG_MPC8220) + unsigned long bi_mbar_base; /* base of internal registers */ + unsigned long bi_inpfreq; /* Input Freq, In MHz */ + unsigned long bi_pcifreq; /* PCI Freq, in MHz */ + unsigned long bi_pevfreq; /* PEV Freq, in MHz */ + unsigned long bi_flbfreq; /* Flexbus Freq, in MHz */ + unsigned long bi_vcofreq; /* VCO Freq, in MHz */ +#endif + unsigned long bi_bootflags; /* boot / reboot flag (Unused) */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */ + unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ + unsigned long bi_intfreq; /* Internal Freq, in MHz */ + unsigned long bi_busfreq; /* Bus Freq, in MHz */ +#if defined(CONFIG_CPM2) + unsigned long bi_cpmfreq; /* CPM_CLK Freq, in MHz */ + unsigned long bi_brgfreq; /* BRG_CLK Freq, in MHz */ + unsigned long bi_sccfreq; /* SCC_CLK Freq, in MHz */ + unsigned long bi_vco; /* VCO Out from PLL, in MHz */ +#endif +#if defined(CONFIG_MPC512X) + unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */ +#endif /* CONFIG_MPC512X */ +#if defined(CONFIG_MPC5xxx) + unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ + unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ +#endif + unsigned int bi_baudrate; /* Console Baudrate */ +#if defined(CONFIG_405) || \ + defined(CONFIG_405GP) || \ + defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || \ + defined(CONFIG_405EZ) || \ + defined(CONFIG_405EX) || \ + defined(CONFIG_440) + unsigned char bi_s_version[4]; /* Version of this structure */ + unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ + unsigned int bi_procfreq; /* CPU (Internal) Freq, in Hz */ + unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ + unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ + unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ +#endif +#if defined(CONFIG_HYMOD) + hymod_conf_t bi_hymod_conf; /* hymod configuration information */ +#endif + +#ifdef CONFIG_HAS_ETH1 + unsigned char bi_enet1addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH2 + unsigned char bi_enet2addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH3 + unsigned char bi_enet3addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH4 + unsigned char bi_enet4addr[6]; /* OLD: see README.enetaddr */ +#endif +#ifdef CONFIG_HAS_ETH5 + unsigned char bi_enet5addr[6]; /* OLD: see README.enetaddr */ +#endif + +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ + defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ + defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) + unsigned int bi_opbfreq; /* OPB clock in Hz */ + int bi_iic_fast[2]; /* Use fast i2c mode */ +#endif +#if defined(CONFIG_NX823) + unsigned char bi_sernum[8]; +#endif +#if defined(CONFIG_4xx) +#if defined(CONFIG_440GX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) + int bi_phynum[4]; /* Determines phy mapping */ + int bi_phymode[4]; /* Determines phy mode */ +#elif defined(CONFIG_405EP) || defined(CONFIG_405EX) || defined(CONFIG_440) + int bi_phynum[2]; /* Determines phy mapping */ + int bi_phymode[2]; /* Determines phy mode */ +#else + int bi_phynum[1]; /* Determines phy mapping */ + int bi_phymode[1]; /* Determines phy mode */ +#endif +#endif /* defined(CONFIG_4xx) */ + ulong bi_arch_number; /* unique id for this board */ + ulong bi_boot_params; /* where this board expects params */ +#ifdef CONFIG_NR_DRAM_BANKS + struct { /* RAM configuration */ + ulong start; + ulong size; + } bi_dram[CONFIG_NR_DRAM_BANKS]; +#endif /* CONFIG_NR_DRAM_BANKS */ +} bd_t; + +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_GENERIC_U_BOOT_H__ */ diff --git a/include/at91rm9200_net.h b/include/at91rm9200_net.h index f799206..804105f 100644 --- a/include/at91rm9200_net.h +++ b/include/at91rm9200_net.h @@ -23,10 +23,6 @@ #include <asm/io.h> #include <asm/arch/hardware.h> -#define FALSE 0 -#define TRUE 1 - - #define ETHERNET_ADDRESS_SIZE 6 typedef unsigned char UCHAR; diff --git a/include/bedbug/ppc.h b/include/bedbug/ppc.h index 46bf8db..76d86fd 100644 --- a/include/bedbug/ppc.h +++ b/include/bedbug/ppc.h @@ -296,11 +296,6 @@ struct operand { ((rc) & 0x1)) #define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1) -#ifndef FALSE -#define FALSE 0 -#define TRUE (!FALSE) -#endif - #define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr)) #define MAX_OPERANDS 8 diff --git a/include/common.h b/include/common.h index 6d52924..0cfa6a8 100644 --- a/include/common.h +++ b/include/common.h @@ -311,6 +311,8 @@ extern ulong monitor_flash_len; int mac_read_from_eeprom(void); extern u8 _binary_dt_dtb_start[]; /* embedded device tree blob */ int set_cpu_clk_info(void); +int print_cpuinfo(void); +int update_flash_size(int flash_size); /** * Show the DRAM size in a board-specific way @@ -528,7 +530,11 @@ int dcache_status (void); void dcache_enable (void); void dcache_disable(void); void mmu_disable(void); -void relocate_code (ulong, gd_t *, ulong) __attribute__ ((noreturn)); +#if defined(CONFIG_ARM) +void relocate_code(ulong); +#else +void relocate_code(ulong, gd_t *, ulong) __attribute__ ((noreturn)); +#endif ulong get_endaddr (void); void trap_init (ulong); #if defined (CONFIG_4xx) || \ @@ -641,7 +647,6 @@ ulong get_PCI_freq (void); #endif #if defined(CONFIG_S3C24X0) || \ defined(CONFIG_LH7A40X) || \ - defined(CONFIG_S3C6400) || \ defined(CONFIG_EP93XX) ulong get_FCLK (void); ulong get_HCLK (void); diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index 0930781..53a2f05 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -57,7 +57,8 @@ #define CONFIG_CMD_LOADB /* loadb */ #define CONFIG_CMD_LOADS /* loads */ #define CONFIG_CMD_MEMINFO /* meminfo */ -#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop */ +#define CONFIG_CMD_MEMTEST /* mtest */ #define CONFIG_CMD_MFSL /* FSL support for Microblaze */ #define CONFIG_CMD_MII /* MII support */ #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ diff --git a/include/config_cmd_default.h b/include/config_cmd_default.h index 6e3903c..a521103 100644 --- a/include/config_cmd_default.h +++ b/include/config_cmd_default.h @@ -30,7 +30,8 @@ #endif #define CONFIG_CMD_LOADB /* loadb */ #define CONFIG_CMD_LOADS /* loads */ -#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop */ +#define CONFIG_CMD_MEMTEST /* mtest */ #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #define CONFIG_CMD_NFS /* NFS support */ diff --git a/include/config_defaults.h b/include/config_defaults.h index d023c63..567b46c 100644 --- a/include/config_defaults.h +++ b/include/config_defaults.h @@ -12,6 +12,7 @@ /* Support bootm-ing different OSes */ #define CONFIG_BOOTM_LINUX 1 #define CONFIG_BOOTM_NETBSD 1 +#define CONFIG_BOOTM_PLAN9 1 #define CONFIG_BOOTM_RTEMS 1 #define CONFIG_GZIP 1 diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index 9298d0e..e59ee96 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -9,6 +9,22 @@ #ifndef __CONFIG_FALLBACKS_H #define __CONFIG_FALLBACKS_H +#ifdef CONFIG_SPL +#ifdef CONFIG_SPL_PAD_TO +#ifdef CONFIG_SPL_MAX_SIZE +#if CONFIG_SPL_PAD_TO && CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE +#error CONFIG_SPL_PAD_TO < CONFIG_SPL_MAX_SIZE +#endif +#endif +#else +#ifdef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE +#else +#define CONFIG_SPL_PAD_TO 0 +#endif +#endif +#endif + #ifndef CONFIG_SYS_BAUDRATE_TABLE #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #endif diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 275d4f2..c28dfe0 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -52,7 +52,7 @@ #define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SPL_MAX_SIZE (4 * 1024) -#define CONFIG_SPL_PAD_TO 0xfff04000 +#define CONFIG_SPL_PAD_TO 0x4000 #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h deleted file mode 100644 index 90cee88..0000000 --- a/include/configs/PCIPPC2.h +++ /dev/null @@ -1,251 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the PCIPPC-2 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_PREBOOT "" -#define CONFIG_BOOTDELAY 5 - -#ifndef __ASSEMBLY__ -#include <galileo/core.h> -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SNTP - -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#define CONFIG_SYS_FLASH_MAX_SIZE 0x00100000 -/* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 /* 512Mb */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \ - CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_INIT_RAM_LOCK - -/* - * Temporary buffer for serial data until the real serial driver - * is initialised (memtest will destroy this buffer) - */ -#define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_SCONSOLE_SIZE 0x0002000 - -/* SDRAM 0 - 256MB - */ -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | \ - BATU_BL_256M | BATU_VS | BATU_VP) -/* SDRAM 1 - 256MB - */ -#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \ - BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \ - BATU_BL_256M | BATU_VS | BATU_VP) - -/* Init RAM in the CPU DCache (no backing memory) - */ -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | \ - BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | \ - BATU_BL_128K | BATU_VS | BATU_VP) - -/* I/O and PCI memory at 0xf0000000 - */ -#define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT0L CONFIG_SYS_DBAT0L -#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U -#define CONFIG_SYS_IBAT1L CONFIG_SYS_DBAT1L -#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U -#define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_IBAT3L CONFIG_SYS_DBAT3L -#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the PCIPPC2 user's manual. - */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */ -#define CONFIG_SYS_CPU_CLK 300000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -/* - * Note: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000) -#define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * L2 cache - */ -#undef CONFIG_SYS_L2 -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/*----------------------------------------------------------------------- - RTC m48t59 -*/ -#define CONFIG_RTC_MK48T59 - -#define CONFIG_WATCHDOG - - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_TULIP - -#endif /* __CONFIG_H */ diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h deleted file mode 100644 index 10b81c1..0000000 --- a/include/configs/PCIPPC6.h +++ /dev/null @@ -1,265 +0,0 @@ -/* - * (C) Copyright 2002-2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * - * Configuration settings for the PCIPPC-6 board. - * - */ - -/* ------------------------------------------------------------------------- */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */ - -#define CONFIG_SYS_TEXT_BASE 0xfff00000 - -#define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 - -#define CONFIG_PREBOOT "" -#define CONFIG_BOOTDELAY 5 - -#ifndef __ASSEMBLY__ -#include <galileo/core.h> -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_BSP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SCSI -#define CONFIG_CMD_SNTP - - -#define CONFIG_PCI 1 -#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFF00000 -#define CONFIG_SYS_FLASH_MAX_SIZE 0x00100000 -/* Maximum amount of RAM. - */ -#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 /* 512Mb */ - -#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \ - CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area - */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_INIT_RAM_LOCK - -/* - * Temporary buffer for serial data until the real serial driver - * is initialised (memtest will destroy this buffer) - */ -#define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_SCONSOLE_SIZE 0x0002000 - -/* SDRAM 0 - 256MB - */ -#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | \ - BATU_BL_256M | BATU_VS | BATU_VP) -/* SDRAM 1 - 256MB - */ -#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \ - BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \ - BATU_BL_256M | BATU_VS | BATU_VP) - -/* Init RAM in the CPU DCache (no backing memory) - */ -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | \ - BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | \ - BATU_BL_128K | BATU_VS | BATU_VP) - -/* I/O and PCI memory at 0xf0000000 - */ -#define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) -#define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) - -#define CONFIG_SYS_IBAT0L CONFIG_SYS_DBAT0L -#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U -#define CONFIG_SYS_IBAT1L CONFIG_SYS_DBAT1L -#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U -#define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#define CONFIG_SYS_IBAT3L CONFIG_SYS_DBAT3L -#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * For the detail description refer to the PCIPPC2 user's manual. - */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */ -#define CONFIG_SYS_CPU_CLK 300000000 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -/* - * Note: environment is not EMBEDDED in the U-Boot code. - * It's stored in flash separately. - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000) -#define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * L2 cache - */ -#undef CONFIG_SYS_L2 -#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ - L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) -#define L2_ENABLE (L2_INIT | L2CR_L2E) - -/*----------------------------------------------------------------------- - RTC m48t59 -*/ -#define CONFIG_RTC_MK48T59 - -#define CONFIG_WATCHDOG - - -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ -#define CONFIG_TULIP - - -#define CONFIG_SCSI_SYM53C8XX -#define CONFIG_SCSI_DEV_ID 0x000B /* 53c896 */ -#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */ -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 15 /* maximum SCSI ID (0..6) */ -#define CONFIG_SYS_SCSI_MAX_DEVICE CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN /* maximum Target devices */ -#define CONFIG_SYS_SCSI_SPIN_UP_TIME 2 -#define CONFIG_SYS_SCSI_SCAN_BUS_REVERSE 0 -#define CONFIG_DOS_PARTITION -#define CONFIG_MAC_PARTITION -#define CONFIG_ISO_PARTITION - -#endif /* __CONFIG_H */ diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h index 868a0b8..60cccff 100644 --- a/include/configs/R360MPI.h +++ b/include/configs/R360MPI.h @@ -39,6 +39,7 @@ #define CONFIG_SYS_TEXT_BASE 0x40000000 #define CONFIG_LCD +#define CONFIG_MPC8XX_LCD #undef CONFIG_EDT32F10 #define CONFIG_SHARP_LQ057Q3DC02 diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index b042c67..d4bcc62 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -47,6 +47,7 @@ #endif #define CONFIG_KEYBOARD 1 /* This board has a custom keybpard */ #define CONFIG_LCD 1 /* use LCD controller ... */ +#define CONFIG_MPC8XX_LCD #define CONFIG_HITACHI_SP19X001_Z1A /* The LCD type we use */ #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h index 67ab1e9..d8e28d5 100644 --- a/include/configs/RPXlite_DW.h +++ b/include/configs/RPXlite_DW.h @@ -54,6 +54,7 @@ #define CONFIG_SYS_TEXT_BASE 0xff000000 #ifdef CONFIG_LCD /* with LCD controller ? */ +#define CONFIG_MPC8XX_LCD #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ #endif diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h index e2b22f0..e2ea016 100644 --- a/include/configs/RRvision.h +++ b/include/configs/RRvision.h @@ -110,7 +110,9 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#ifndef CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_MPC8XX_LCD +#else #define CONFIG_VIDEO 1 /* To enable the video initialization */ /* Video related */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 9fac5d1..cccf3af 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -39,6 +39,7 @@ #define CONFIG_SYS_TEXT_BASE 0x40000000 #ifdef CONFIG_LCD /* with LCD controller ? */ +#define CONFIG_MPC8XX_LCD #define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ #define CONFIG_LCD_INFO 1 /* ... and some board info */ #define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 932f158..b2d1af0 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -39,6 +39,7 @@ #define CONFIG_SYS_TEXT_BASE 0x40000000 #ifdef CONFIG_LCD /* with LCD controller ? */ +#define CONFIG_MPC8XX_LCD /* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ #endif diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index fb7d922..2b3d59f 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -77,6 +77,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_BSP #define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_YAFFS #define CONFIG_BOARD_LATE_INIT diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h index df3b4ae..13f3226 100644 --- a/include/configs/a3m071.h +++ b/include/configs/a3m071.h @@ -26,15 +26,22 @@ #define CONFIG_MPC5200 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_A3M071 /* ... on A3M071 board */ -#define CONFIG_MPC5200_DDR /* ... use DDR RAM */ #define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */ +#define CONFIG_SPL_TARGET "u-boot-img.bin" + #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ #define CONFIG_MISC_INIT_R #define CONFIG_SYS_LOWBOOT /* Enable lowboot */ +#ifdef CONFIG_A4M2K +#define CONFIG_HOSTNAME a4m2k +#else +#define CONFIG_HOSTNAME a3m071 +#endif + /* * Serial console configuration */ @@ -50,9 +57,6 @@ #define CONFIG_CMD_BSP #define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_REGINFO @@ -61,7 +65,11 @@ */ #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ /* define for 66MHz speed - undef for 33MHz PCI clock speed */ +#ifdef CONFIG_A4M2K +#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 +#else #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 +#endif /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT @@ -76,33 +84,10 @@ #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" /* - * I2C configuration - */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* * NOR flash configuration */ #define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_SIZE 0x01000000 +#define CONFIG_SYS_FLASH_SIZE 0x02000000 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) #define CONFIG_SYS_MAX_FLASH_BANKS 1 @@ -153,7 +138,11 @@ */ #define CONFIG_MPC5xxx_FEC #define CONFIG_MPC5xxx_FEC_MII100 +#ifdef CONFIG_A4M2K +#define CONFIG_PHY_ADDR 0x01 +#else #define CONFIG_PHY_ADDR 0x00 +#endif /* * GPIO configuration @@ -166,19 +155,28 @@ * 2 means fpga ok */ +#ifdef CONFIG_A4M2K +#define CONFIG_SYS_GPS_PORT_CONFIG 0x0005C805 +#else /* for failsave-level 0 - full failsave */ #define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005 /* for failsave-level 1 - only digiboard ok */ #define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C005 /* for failsave-level 2 - all ok */ #define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C005 +#endif + +#define CONFIG_WDOG_GPIO_PIN GPIO_WKUP_7 +#if defined(CONFIG_A4M2K) && !defined(CONFIG_SPL_BUILD) +#define CONFIG_HW_WATCHDOG /* Use external HW-Watchdog */ +#endif /* * Configuration matrix * MSB LSB - * failsave 0 0x1005C005 00010000000001011100000001100101 ( full failsave ) - * failsave 1 0x1005C005 00010000000001011100000001100101 ( digib.-ver ok ) - * failsave 2 0x1005C005 00010000000001011100000001100101 ( all ok ) + * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave ) + * failsave 1 0x1005C005 00010000000001011100000000000101 ( digib.-ver ok ) + * failsave 2 0x1005C005 00010000000001011100000000000101 ( all ok ) * || ||| || | ||| | | | | * || ||| || | ||| | | | | bit rev name * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1 @@ -254,30 +252,47 @@ #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE + +#ifdef CONFIG_A4M2K +/* external MRAM */ +#define CONFIG_SYS_CS1_START 0xf1000000 +#define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */ +#endif + #define CONFIG_SYS_CS2_START 0xe0000000 #define CONFIG_SYS_CS2_SIZE 0x00100000 -/* FPGA slave io (512kiB) - see ticket #66 */ +/* FPGA slave io (512kiB / 1MiB) - see ticket #66 */ #define CONFIG_SYS_CS3_START 0xE9000000 +#ifdef CONFIG_A4M2K +#define CONFIG_SYS_CS3_SIZE 0x00100000 +#else #define CONFIG_SYS_CS3_SIZE 0x00080000 +#endif /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */ #define CONFIG_SYS_CS3_CFG 0x0032B900 +#ifndef CONFIG_A4M2K /* Diagnosis Interface - see ticket #63 */ #define CONFIG_SYS_CS4_START 0xEA000000 #define CONFIG_SYS_CS4_SIZE 0x00000001 /* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */ #define CONFIG_SYS_CS4_CFG 0x0002B900 +#endif -/* FPGA master io (64kiB) - see ticket #66 */ +/* FPGA master io (64kiB / 1MiB) - see ticket #66 */ #define CONFIG_SYS_CS5_START 0xE8000000 +#ifdef CONFIG_A4M2K +#define CONFIG_SYS_CS5_SIZE 0x00100000 +#else #define CONFIG_SYS_CS5_SIZE 0x00010000 +#endif /* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */ #define CONFIG_SYS_CS5_CFG 0x0032B900 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */ #define CONFIG_SYS_BOOTCS_CFG 0x0006F900 -#define CONFIG_SYS_CS1_CFG 0x0004FB00 +#define CONFIG_SYS_CS1_CFG 0x0008FD00 #define CONFIG_SYS_CS2_CFG 0x0006F90C #else /* for pci_clk = 33 MHz */ #define CONFIG_SYS_BOOTCS_CFG 0x0002F900 @@ -311,17 +326,25 @@ #define CONFIG_SYS_OS_BASE 0xfc080000 #define CONFIG_SYS_FDT_BASE 0xfc060000 -#define xstr(s) str(s) -#define str(s) #s - #define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \ "netdev=eth0\0" \ "verify=no\0" \ + "loadaddr=200000\0" \ + "kernel_addr=" __stringify(CONFIG_SYS_OS_BASE) "\0" \ + "kernel_addr_r=1000000\0" \ + "fdt_addr=" __stringify(CONFIG_SYS_FDT_BASE) "\0" \ + "fdt_addr_r=1800000\0" \ + "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \ + "fdtfile=" __stringify(CONFIG_HOSTNAME) "/" \ + __stringify(CONFIG_HOSTNAME) ".dtb\0" \ + "rootpath=/opt/eldk-5.2.1/powerpc/" \ + "core-image-minimal-mtdutils-dropbear-generic\0" \ "consoledev=ttyPSC0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0"\ + "mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ @@ -332,18 +355,18 @@ "flash_mtd=run mtdargs addip addtty;" \ "bootm ${kernel_addr} - ${fdtaddr}\0" \ "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \ - "net_nfs=sleep 2; tftp ${loadaddr} ${bootfile};" \ - "tftp c00000 ${fdtfile};" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ "run nfsargs addip addtty;" \ - "bootm ${loadaddr} - c00000\0" \ - "load=tftp ${loadaddr} u-boot.bin\0" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "load=tftp ${loadaddr} " __stringify(CONFIG_HOSTNAME) \ + "/u-boot-img.bin\0" \ "update=protect off fc000000 fc03ffff; " \ - "era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0"\ + "era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0" \ "upd=run load;run update\0" \ - "fdtaddr=" xstr(CONFIG_SYS_FDT_BASE) "\0" \ - "fdtfile=dtbFile\0" \ - "kernel_addr=" xstr(CONFIG_SYS_OS_BASE) "\0" \ + "bootdelay=3\0" \ + "bootcmd=run net_nfs\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_mtd" @@ -353,6 +376,7 @@ */ #define CONFIG_SPL #define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BOARD_INIT #define CONFIG_SPL_NOR_SUPPORT #define CONFIG_SPL_TEXT_BASE 0xfc000000 #define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx" diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h new file mode 100644 index 0000000..ac7e877 --- /dev/null +++ b/include/configs/ac14xx.h @@ -0,0 +1,591 @@ +/* + * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> + * (C) Copyright 2010 DAVE Srl <www.dave.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * ifm AC14xx (MPC5121e based) board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_AC14XX 1 +/* + * Memory map for the ifm AC14xx board: + * + * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB) + * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB) + * 0x8000_0000-0x803F_FFFF IMMR (4 MB) + * 0xE000_0000-0xEFFF_FFFF several LPB attached hardware (CSx) + * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB) + */ + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC512X 1 /* MPC512X family */ + +#define CONFIG_SYS_TEXT_BASE 0xFFF00000 + +#if defined(CONFIG_VIDEO) +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#endif + +#define CONFIG_SYS_MPC512X_CLKIN 25000000 /* in Hz */ +#define SCFR1_IPS_DIV 2 +#define SCFR1_LPC_DIV 2 +#define SCFR1_NFC_DIV 2 +#define SCFR1_DIU_DIV 240 + +#define CONFIG_MISC_INIT_R + +#define CONFIG_SYS_IMMR 0x80000000 +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100) + +/* more aggressive 'mtest' over a wider address range */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x0FE00000 + +/* + * DDR Setup - manually set all parameters as there's no SPD etc. + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#define CONFIG_SYS_DDR_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 + +/* + * DDR Controller Configuration XXX TODO + * + * SYS_CFG: + * [31:31] MDDRC Soft Reset: Diabled + * [30:30] DRAM CKE pin: Enabled + * [29:29] DRAM CLK: Enabled + * [28:28] Command Mode: Enabled (For initialization only) + * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] + * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] + * [20:19] Read Test: DON'T USE + * [18:18] Self Refresh: Enabled + * [17:17] 16bit Mode: Disabled + * [16:13] Ready Delay: 2 + * [12:12] Half DQS Delay: Disabled + * [11:11] Quarter DQS Delay: Disabled + * [10:08] Write Delay: 2 + * [07:07] Early ODT: Disabled + * [06:06] On DIE Termination: Disabled + * [05:05] FIFO Overflow Clear: DON'T USE here + * [04:04] FIFO Underflow Clear: DON'T USE here + * [03:03] FIFO Overflow Pending: DON'T USE here + * [02:02] FIFO Underlfow Pending: DON'T USE here + * [01:01] FIFO Overlfow Enabled: Enabled + * [00:00] FIFO Underflow Enabled: Enabled + * TIME_CFG0 + * [31:16] DRAM Refresh Time: 0 CSB clocks + * [15:8] DRAM Command Time: 0 CSB clocks + * [07:00] DRAM Precharge Time: 0 CSB clocks + * TIME_CFG1 + * [31:26] DRAM tRFC: + * [25:21] DRAM tWR1: + * [20:17] DRAM tWRT1: + * [16:11] DRAM tDRR: + * [10:05] DRAM tRC: + * [04:00] DRAM tRAS: + * TIME_CFG2 + * [31:28] DRAM tRCD: + * [27:23] DRAM tFAW: + * [22:19] DRAM tRTW1: + * [18:15] DRAM tCCD: + * [14:10] DRAM tRTP: + * [09:05] DRAM tRP: + * [04:00] DRAM tRPA + */ + +/* + * NOTE: although this board uses DDR1 only, the common source brings defaults + * for DDR2 init sequences, that's why we have to keep those here as well + */ + +/* DDR1 -- 32bit, drive strength (pad configuration) 3 for control and data */ +#define CONFIG_SYS_IOCTRL_MUX_DDR ((0 << 6) | (3 << 3) | (3 << 0)) + +#define CONFIG_SYS_MDDRC_SYS_CFG (/* 0xEAA09100 */ 0 \ + | (1 << 31) /* RST_B */ \ + | (1 << 30) /* CKE */ \ + | (1 << 29) /* CLK_ON */ \ + | (0 << 28) /* CMD_MODE */ \ + | (5 << 25) /* DRAM_ROW_SELECT */ \ + | (5 << 21) /* DRAM_BANK_SELECT */ \ + | (0 << 18) /* SELF_REF_EN */ \ + | (0 << 17) /* 16BIT_MODE */ \ + | (4 << 13) /* RDLY */ \ + | (1 << 12) /* HALF_DQS_DLY */ \ + | (0 << 11) /* QUART_DQS_DLY */ \ + | (1 << 8) /* WDLY */ \ + | (0 << 7) /* EARLY_ODT */ \ + | (0 << 6) /* ON_DIE_TERMINATE */ \ + | (0 << 5) /* FIFO_OV_CLEAR */ \ + | (0 << 4) /* FIFO_UV_CLEAR */ \ + | (0 << 1) /* FIFO_OV_EN */ \ + | (0 << 0) /* FIFO_UV_EN */ \ + ) + +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x04E03124 +#define CONFIG_SYS_MDDRC_TIME_CFG1 0x30CA1147 +#define CONFIG_SYS_MDDRC_TIME_CFG2 0x32B10864 + +/* register address only, i.e. template without values */ +#define CONFIG_SYS_MICRON_BMODE 0x01000000 +#define CONFIG_SYS_MICRON_EMODE 0x01010000 +#define CONFIG_SYS_MICRON_EMODE2 0x01020000 +#define CONFIG_SYS_MICRON_EMODE3 0x01030000 +/* + * values for mode registers (without mode register address) + */ +/* CAS 2.5 (6), burst seq (0) and length 4 (2) */ +#define CONFIG_SYS_MICRON_BMODE_PARAM 0x00000062 +#define CONFIG_SYS_MICRON_BMODE_RSTDLL 0x00000100 +/* DLL enable, reduced drive strength */ +#define CONFIG_SYS_MICRON_EMODE_PARAM 0x00000002 + +#define CONFIG_SYS_DDRCMD_NOP 0x01380000 +#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 +#define CONFIG_SYS_MICRON_EMR ((1 << 24) | /* CMD_REQ */ \ + (0 << 22) | /* DRAM_CS */ \ + (0 << 21) | /* DRAM_RAS */ \ + (0 << 20) | /* DRAM_CAS */ \ + (0 << 19) | /* DRAM_WEB */ \ + (1 << 16) | /* DRAM_BS[2:0] */ \ + (0 << 15) | /* */ \ + (0 << 12) | /* A12->out */ \ + (0 << 11) | /* A11->RDQS */ \ + (0 << 10) | /* A10->DQS# */ \ + (0 << 7) | /* OCD program */ \ + (0 << 6) | /* Rtt1 */ \ + (0 << 3) | /* posted CAS# */ \ + (0 << 2) | /* Rtt0 */ \ + (1 << 1) | /* ODS */ \ + (0 << 0) /* DLL */ \ + ) +#define CONFIG_SYS_MICRON_EMR2 0x01020000 +#define CONFIG_SYS_MICRON_EMR3 0x01030000 +#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 +#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 +#define CONFIG_SYS_MICRON_EMR_OCD ((1 << 24) | /* CMD_REQ */ \ + (0 << 22) | /* DRAM_CS */ \ + (0 << 21) | /* DRAM_RAS */ \ + (0 << 20) | /* DRAM_CAS */ \ + (0 << 19) | /* DRAM_WEB */ \ + (1 << 16) | /* DRAM_BS[2:0] */ \ + (0 << 15) | /* */ \ + (0 << 12) | /* A12->out */ \ + (0 << 11) | /* A11->RDQS */ \ + (1 << 10) | /* A10->DQS# */ \ + (7 << 7) | /* OCD program */ \ + (0 << 6) | /* Rtt1 */ \ + (0 << 3) | /* posted CAS# */ \ + (1 << 2) | /* Rtt0 */ \ + (0 << 1) | /* ODS */ \ + (0 << 0) /* DLL */ \ + ) + +/* + * Backward compatible definitions, + * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c + */ +#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) +#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) +#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR) +#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) + +/* DDR Priority Manager Configuration */ +#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 +#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 +#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 +#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 +#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 +#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 +#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 +#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 +#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 +#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 + +/* + * NOR FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the CFI code */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* max flash size */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST { \ + CONFIG_SYS_FLASH_BASE + 0 * CONFIG_SYS_FLASH_SIZE, \ + } +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_PROTECTION + +/* + * SRAM support + */ +#define CONFIG_SYS_SRAM_BASE 0x30000000 +#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ + +/* + * CS related parameters + * TODO document these + */ +/* CS0 Flash */ +#define CONFIG_SYS_CS0_CFG 0x00031110 +#define CONFIG_SYS_CS0_START 0xFC000000 +#define CONFIG_SYS_CS0_SIZE 0x04000000 +/* CS1 FRAM */ +#define CONFIG_SYS_CS1_CFG 0x00011000 +#define CONFIG_SYS_CS1_START 0xE0000000 +#define CONFIG_SYS_CS1_SIZE 0x00010000 +/* CS2 AS-i 1 */ +#define CONFIG_SYS_CS2_CFG 0x00009100 +#define CONFIG_SYS_CS2_START 0xE0100000 +#define CONFIG_SYS_CS2_SIZE 0x00080000 +/* CS3 netX */ +#define CONFIG_SYS_CS3_CFG 0x000A1140 +#define CONFIG_SYS_CS3_START 0xE0300000 +#define CONFIG_SYS_CS3_SIZE 0x00020000 +/* CS5 safety */ +#define CONFIG_SYS_CS5_CFG 0x0011F000 +#define CONFIG_SYS_CS5_START 0xE0400000 +#define CONFIG_SYS_CS5_SIZE 0x00010000 +/* CS6 AS-i 2 */ +#define CONFIG_SYS_CS6_CFG 0x00009100 +#define CONFIG_SYS_CS6_START 0xE0200000 +#define CONFIG_SYS_CS6_SIZE 0x00080000 + +/* Don't use alternative CS timing for any CS */ +#define CONFIG_SYS_CS_ALETIMING 0x00000000 +#define CONFIG_SYS_CS_BURST 0x00000000 +#define CONFIG_SYS_CS_DEADCYCLE 0x00000020 +#define CONFIG_SYS_CS_HOLDCYCLE 0x00000020 + +/* Use SRAM for initial stack */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE +#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE + +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) + +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) +#else +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) +#endif + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */ +#define CONFIG_SYS_PSC3 +#if CONFIG_PSC_CONSOLE != 3 +#error CONFIG_PSC_CONSOLE must be 3 +#endif + +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE +#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR +#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE +#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR + +/* + * Clocks in use + */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSC_EN(7) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_TPR_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_DIU_EN | \ + CLOCK_SCCR2_I2C_EN) + + +#define CONFIG_CMDLINE_EDITING 1 /* command line history */ + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_I2C_MULTI_BUS + +/* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x7F + +/* + * EEPROM configuration for Atmel AT24C01: + * 8-bit addresses, 30ms write delay, 32-Byte Page Write Mode + */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 30 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 + +/* + * Ethernet configuration + */ +#define CONFIG_MPC512x_FEC 1 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_ADDR 0x1F +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_FEC_AN_TIMEOUT 1 +#define CONFIG_HAS_ETH0 + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +/* This has to be a multiple of the flash sector size */ +#define CONFIG_ENV_ADDR 0xFFF40000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#define CONFIG_LOADS_ECHO 1 +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 + +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_FUSE +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_IDE +#undef CONFIG_CMD_EXT2 +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#endif + +#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2) +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION +#endif /* defined(CONFIG_CMD_IDE) */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "ac14xx> " /* Monitor Command Prompt */ + +#ifdef CONFIG_CMD_KGDB +# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 32 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* decrementer freq: 1ms ticks */ +#define CONFIG_SYS_HZ 1000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 32768 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */ +#endif + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ICE) +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 +#define BOOTFLAG_WARM 0x02 + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_TIMESTAMP + +#define CONFIG_HOSTNAME ac14xx +#define CONFIG_BOOTFILE "ac14xx/uImage" +#define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" + +/* default load addr for tftp and bootm */ +#define CONFIG_LOADADDR 400000 + +#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */ + +/* XXX TODO need to specify the builtin environment */ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS_DEVEL \ + "muster_nr=00\0" \ + "fromram=run ramargs addip addtty; " \ + "tftp ${fdt_addr_r} k6m2/ac14xx.dtb-${muster_nr}; " \ + "tftp ${kernel_addr_r} k6m2/uImage-${muster_nr}; " \ + "tftp ${ramdisk_addr_r} k6m2/uFS-${muster_nr}; " \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ + "fromnfs=run nfsargs addip addtty; " \ + "tftp ${fdt_addr_r} k6m2/ac14xx.dtb-${muster_nr}; " \ + "tftp ${kernel_addr_r} k6m2/uImage-${muster_nr}; " \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "fromflash=run nfsargs addip addtty; " \ + "bootm fc020000 - fc000000\0" \ + "mtdargsrec=setenv bootargs root=/dev/mtdblock1 ro\0" \ + "recovery=run mtdargsrec addip addtty; " \ + "bootm ffd20000 - ffee0000\0" \ + "production=run ramargs addip addtty; " \ + "bootm fc020000 fc400000 fc000000\0" \ + "mtdargs=setenv bootargs root=/dev/mtdblock1 ro\0" \ + "prodmtd=run mtdargs addip addtty; " \ + "bootm fc020000 - fc000000\0" \ + "" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "u-boot_addr_r=200000\0" \ + "kernel_addr_r=600000\0" \ + "fdt_addr_r=a00000\0" \ + "ramdisk_addr_r=b00000\0" \ + "u-boot_addr=FFF00000\0" \ + "kernel_addr=FC020000\0" \ + "fdt_addr=FC000000\0" \ + "ramdisk_addr=FC400000\0" \ + "verify=n\0" \ + "ramdiskfile=ac14xx/uRamdisk\0" \ + "u-boot=ac14xx/u-boot.bin\0" \ + "bootfile=ac14xx/uImage\0" \ + "fdtfile=ac14xx/ac14xx.dtb\0" \ + "rootpath=/opt/eldk/ppc_6xx\n" \ + "netdev=eth0\0" \ + "consdev=ttyPSC0\0" \ + "hostname=ac14xx\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}-${muster_nr}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run nfsargs addip addtty;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "net_self=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run ramargs addip addtty;" \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ + "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ + "update=protect off ${u-boot_addr} +${filesize};" \ + "era ${u-boot_addr} +${filesize};" \ + "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ + CONFIG_EXTRA_ENV_SETTINGS_DEVEL \ + "upd=run load update\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run production" + +#define CONFIG_FIT 1 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 + +#define OF_CPU "PowerPC,5121@0" +#define OF_SOC_COMPAT "fsl,mpc5121-immr" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc@80000000/serial@11300" + +#endif /* __CONFIG_H */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 9eada95..ef00306 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -18,8 +18,7 @@ #define CONFIG_AM33XX -#include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> #define CONFIG_DMA_COHERENT #define CONFIG_DMA_COHERENT_SIZE (1 << 20) @@ -40,6 +39,8 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* commands to include */ #include <config_cmd_default.h> @@ -56,13 +57,20 @@ "fdtaddr=0x80F80000\0" \ "fdt_high=0xffffffff\0" \ "rdaddr=0x81000000\0" \ - "bootfile=/boot/uImage\0" \ + "bootdir=/boot\0" \ + "bootfile=uImage\0" \ "fdtfile=\0" \ "console=ttyO0,115200n8\0" \ "optargs=\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "dfu_alt_info_mmc=" DFU_ALT_INFO_MMC "\0" \ + "dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \ + "dfu_alt_info_nand=" DFU_ALT_INFO_NAND "\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 ro\0" \ "mmcrootfstype=ext4 rootwait\0" \ + "bootpart=0:2\0" \ "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ "nandrootfstype=ubifs rootwait=1\0" \ "nandsrcaddr=0x280000\0" \ @@ -96,19 +104,19 @@ "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ "ip=dhcp\0" \ "bootenv=uEnv.txt\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t $loadaddr $filesize\0" \ "ramargs=setenv bootargs console=${console} " \ "${optargs} " \ "root=${ramroot} " \ "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ - "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ + "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "loaduimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "bootm ${loadaddr}\0" \ + "bootm ${loadaddr} - ${fdtaddr}\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \ @@ -122,14 +130,17 @@ "setenv autoload no; " \ "dhcp; " \ "tftp ${loadaddr} ${bootfile}; " \ + "tftp ${fdtaddr} ${fdtfile}; " \ "run netargs; " \ - "bootm ${loadaddr}\0" \ + "bootm ${loadaddr} - ${fdtaddr}\0" \ "ramboot=echo Booting from ramdisk ...; " \ "run ramargs; " \ - "bootm ${loadaddr}\0" \ + "bootm ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ "findfdt="\ "if test $board_name = A335BONE; then " \ "setenv fdtfile am335x-bone.dtb; fi; " \ + "if test $board_name = A335BNLT; then " \ + "setenv fdtfile am335x-boneblack.dtb; fi; " \ "if test $board_name = A33515BB; then " \ "setenv fdtfile am335x-evm.dtb; fi; " \ "if test $board_name = A335X_SK; then " \ @@ -138,6 +149,7 @@ #endif #define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ "if run loadbootenv; then " \ @@ -149,6 +161,7 @@ "run uenvcmd;" \ "fi;" \ "if run loaduimage; then " \ + "run loadfdt;" \ "run mmcboot;" \ "fi;" \ "else " \ @@ -161,8 +174,8 @@ #define CONFIG_CMD_ECHO -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 64 /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 512 @@ -191,7 +204,10 @@ #define CONFIG_CMD_MMC #define CONFIG_DOS_PARTITION #define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE #define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 +#define CONFIG_CMD_FS_GENERIC #define CONFIG_SPI #define CONFIG_OMAP3_SPI @@ -201,6 +217,38 @@ #define CONFIG_CMD_SF #define CONFIG_SF_DEFAULT_SPEED (24000000) +/* USB Composite download gadget - g_dnl */ +#define CONFIG_USB_GADGET +#define CONFIG_USBDOWNLOAD_GADGET + +/* USB TI's IDs */ +#define CONFIG_USBD_HS +#define CONFIG_G_DNL_VENDOR_NUM 0x0403 +#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 +#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" + +/* USB Device Firmware Update support */ +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_DFU_NAND +#define CONFIG_CMD_DFU +#define DFU_ALT_INFO_MMC \ + "boot part 0 1;" \ + "rootfs part 0 2;" \ + "MLO fat 0 1;" \ + "MLO.raw mmc 100 100;" \ + "u-boot.img.raw mmc 300 3C0;" \ + "u-boot.img fat 0 1;" \ + "uEnv.txt fat 0 1" +#define DFU_ALT_INFO_NAND \ + "SPL part 0 1;" \ + "SPL.backup1 part 0 2;" \ + "SPL.backup2 part 0 3;" \ + "SPL.backup3 part 0 4;" \ + "u-boot part 0 5;" \ + "kernel part 0 7;" \ + "rootfs part 0 8" + /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ @@ -344,7 +392,9 @@ #define CONFIG_ARCH_MISC_INIT #define CONFIG_MUSB_GADGET #define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT #define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_MUSB_HOST #define CONFIG_AM335X_USB0 #define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL @@ -416,6 +466,13 @@ /* NAND support */ #ifdef CONFIG_NAND #define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ + "128k(SPL.backup1)," \ + "128k(SPL.backup2)," \ + "128k(SPL.backup3),1920k(u-boot)," \ + "128k(u-boot-env),5m(kernel),-(rootfs)" #define CONFIG_NAND_OMAP_GPMC #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ diff --git a/include/configs/aria.h b/include/configs/aria.h index 0b31c50..b425399 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -64,7 +64,6 @@ #define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */ -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R #define CONFIG_SYS_IMMR 0x80000000 @@ -266,11 +265,16 @@ #define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \ CONFIG_SYS_SRAM_SIZE) #define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */ +#define CONFIG_SYS_CS6_START CONFIG_SYS_ARIA_SRAM_BASE +#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_ARIA_SRAM_SIZE #define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \ CONFIG_SYS_ARIA_SRAM_SIZE) #define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */ +#define CONFIG_SYS_CS2_START CONFIG_SYS_ARIA_FPGA_BASE +#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_ARIA_FPGA_SIZE + #define CONFIG_SYS_CS0_CFG 0x05059150 #define CONFIG_SYS_CS2_CFG ( (5 << 24) | \ (5 << 16) | \ @@ -643,4 +647,21 @@ #define FSL_ATA_CTRL_DMA_WRITE 0x02000000 #define FSL_ATA_CTRL_IORDY_EN 0x01000000 +/* Clocks in use */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_NFC_EN | \ + CLOCK_SCCR1_PATA_EN | \ + CLOCK_SCCR1_PCI_EN | \ + CLOCK_SCCR1_TPR_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_DIU_EN | \ + CLOCK_SCCR2_I2C_EN) + #endif /* __CONFIG_H */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h index 55dc83d..6a99175 100644 --- a/include/configs/cardhu.h +++ b/include/configs/cardhu.h @@ -60,7 +60,7 @@ #define CONFIG_SYS_MMC_ENV_PART 2 /* SPI */ -#define CONFIG_TEGRA_SLINK +#define CONFIG_TEGRA20_SLINK #define CONFIG_TEGRA_SLINK_CTRLS 6 #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_WINBOND diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 8d79ffd..726714d 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -344,5 +344,9 @@ #define LCD_BPP LCD_COLOR16 #define CONFIG_LCD +#define CONFIG_SPLASH_SCREEN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_SPLASH_SCREEN_PREPARE #endif /* __CONFIG_H */ diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 49f05de..a4aa8f7 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -179,6 +179,8 @@ #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_SETGETDCR #define CONFIG_CMD_SOURCE +#define CONFIG_CMD_TIME +#define CONFIG_CMD_GETTIME #define CONFIG_CMD_XIMG #define CONFIG_CMD_SCSI @@ -257,10 +259,16 @@ /*----------------------------------------------------------------------- * FLASH configuration */ +#define CONFIG_ICH_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_MACRONIX +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SPI_FLASH_GIGADEVICE #define CONFIG_SYS_NO_FLASH -#undef CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_MAX_FLASH_SECT 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_CMD_SF +#define CONFIG_CMD_SF_TEST +#define CONFIG_CMD_SPI +#define CONFIG_SPI /*----------------------------------------------------------------------- * Environment configuration @@ -273,6 +281,23 @@ */ #define CONFIG_PCI +/*----------------------------------------------------------------------- + * USB configuration + */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_PCI +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL + +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX + +#define CONFIG_CMD_USB + #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_STD_DEVICES_SETTINGS diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index b1a6e34..7b68f7c 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -50,10 +50,31 @@ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_CMD_I2C -#define CONFIG_ENV_IS_NOWHERE +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_ENV_OFFSET ((4096 * 1024) - CONFIG_ENV_SIZE) #define MACH_TYPE_DALMORE 4304 /* not yet in mach-types.h */ +/* SPI */ +#define CONFIG_TEGRA114_SPI +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + #include "tegra-common-post.h" #endif /* __CONFIG_H */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 10a4939..28a306b 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -28,6 +28,8 @@ #ifndef __CONFIG_DRA7XX_EVM_H #define __CONFIG_DRA7XX_EVM_H +#define CONFIG_ENV_IS_NOWHERE /* For now. */ + #include <configs/omap5_common.h> #define CONFIG_DRA7XX /* in a TI DRA7XX core */ diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index cabd2f2..496a194 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -33,6 +33,7 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_ARCH_CPU_INIT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -45,6 +46,10 @@ /* Keep L2 Cache Disabled */ #define CONFIG_SYS_DCACHE_OFF +/* Enable ACE acceleration for SHA1 and SHA256 */ +#define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_SHA_HW_ACCEL + #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_TEXT_BASE 0x43E00000 @@ -113,10 +118,16 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_NET +#define CONFIG_CMD_HASH #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK +/* Thermal Management Unit */ +#define CONFIG_EXYNOS_TMU +#define CONFIG_CMD_DTT +#define CONFIG_TMU_CMD_DTT + /* USB */ #define CONFIG_CMD_USB #define CONFIG_USB_EHCI @@ -296,6 +307,7 @@ #ifdef CONFIG_CMD_SOUND #define CONFIG_SOUND #define CONFIG_I2S +#define CONFIG_SOUND_MAX98095 #define CONFIG_SOUND_WM8994 #endif @@ -318,4 +330,7 @@ #define LCD_BPP LCD_COLOR16 #endif +/* Enable Time Command */ +#define CONFIG_CMD_TIME + #endif /* __CONFIG_H */ diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 559e375..1d8090b 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -55,7 +55,8 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 -#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ /* * NS16550 Configuration @@ -68,9 +69,6 @@ #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -/* define to avoid U-Boot to hang while waiting for TEMT */ -#define CONFIG_SYS_NS16550_BROKEN_TEMT - /* select serial console configuration */ #define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h index 564b418..905b279 100644 --- a/include/configs/integrator-common.h +++ b/include/configs/integrator-common.h @@ -41,6 +41,7 @@ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_OF_LIBFDT /* enable passing a Device Tree */ #define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ /* diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 796f330..3b15c4e 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -24,10 +24,6 @@ #ifndef __CONFIG_KEYMILE_H #define __CONFIG_KEYMILE_H -/* Do boardspecific init for all boards */ -#define CONFIG_BOARD_EARLY_INIT_R -#define CONFIG_LAST_STAGE_INIT - #define CONFIG_BOOTCOUNT_LIMIT /* diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index bd5bdbc..b84f12d 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -24,6 +24,10 @@ #ifndef __CONFIG_KEYMILE_POWERPC_H #define __CONFIG_KEYMILE_POWERPC_H +/* Do boardspecific init for all boards */ +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_LAST_STAGE_INIT + #define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_CMD_DTT diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 549278d..766d76e 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -50,6 +50,9 @@ #define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD +#define CONFIG_NAND_ECC_BCH +#define CONFIG_BCH + /* include common defines/options for all Keymile boards */ #include "keymile-common.h" @@ -320,6 +323,6 @@ int get_scl(void); #define CONFIG_CMD_DIAG /* we do the whole PCIe FPGA config stuff here */ -#define BOARD_LATE_INIT +#define CONFIG_BOARD_LATE_INIT #endif /* _CONFIG_KM_ARM_H */ diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h index 762cc10..83bb7aa 100644 --- a/include/configs/km_kirkwood.h +++ b/include/configs/km_kirkwood.h @@ -98,6 +98,14 @@ #define KM_IVM_BUS "pca9544a:70:9" /* I2C2 (Mux-Port 1)*/ #define CONFIG_KM_PIGGY4_88E6061 +/* KM_SUV31 */ +#elif defined(CONFIG_KM_SUV31) +#define KM_IVM_BUS "pca9547:70:9" /* I2C2 (Mux-Port 1)*/ +#define CONFIG_IDENT_STRING "\nKeymile SUV31" +#define CONFIG_HOSTNAME kmsuv31 +#define CONFIG_KM_ENV_IS_IN_SPI_NOR +#define CONFIG_KM_FPGA_CONFIG + #else #error ("Board unsupported") #endif diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 5886a15..b99a056 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -38,6 +38,7 @@ #define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */ #define CONFIG_LCD 1 #ifdef CONFIG_LCD +#define CONFIG_PXA_LCD #define CONFIG_SHARP_LM8V31 #endif #define CONFIG_MMC diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h index df49781..3c02b73 100644 --- a/include/configs/lwmon.h +++ b/include/configs/lwmon.h @@ -54,6 +54,7 @@ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ #define CONFIG_LCD 1 /* use LCD controller ... */ +#define CONFIG_MPC8XX_LCD #define CONFIG_HLD1045 1 /* ... with a HLD1045 display */ #define CONFIG_LCD_LOGO 1 /* print our logo on the LCD */ diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index cafc273..af30257 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -191,6 +191,10 @@ #define CONFIG_SYS_SRAM_BASE 0x30000000 #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ +/* Initialize Local Window for NOR FLASH access */ +#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE + /* ALE active low, data size 4bytes */ #define CONFIG_SYS_CS0_CFG 0x05051150 @@ -201,6 +205,9 @@ #define CONFIG_SYS_CS1_CFG 0x1f1f3090 #define CONFIG_SYS_VPC3_BASE 0x82000000 /* start of VPC3 space */ #define CONFIG_SYS_VPC3_SIZE 0x00010000 /* max VPC3 size */ +/* Initialize Local Window for VPC3 access */ +#define CONFIG_SYS_CS1_START CONFIG_SYS_VPC3_BASE +#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_VPC3_SIZE /* Use SRAM for initial stack */ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM addr */ @@ -235,6 +242,23 @@ #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR +/* + * Clocks in use + */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_NFC_EN | \ + CLOCK_SCCR1_PCI_EN | \ + CLOCK_SCCR1_TPR_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_I2C_EN) + + #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 3f55d35..6e6af62 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -258,6 +258,8 @@ */ #define CONFIG_SYS_CPLD_BASE 0x82000000 #define CONFIG_SYS_CPLD_SIZE 0x00010000 /* 64 KB */ +#define CONFIG_SYS_CS2_START CONFIG_SYS_CPLD_BASE +#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_CPLD_SIZE #define CONFIG_SYS_SRAM_BASE 0x30000000 #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ @@ -310,6 +312,27 @@ #endif /* + * Clocks in use + */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_NFC_EN | \ + CLOCK_SCCR1_PATA_EN | \ + CLOCK_SCCR1_PCI_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_TPR_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \ + CLOCK_SCCR2_I2C_EN | \ + CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_USB1_EN | \ + CLOCK_SCCR2_USB2_EN) + +/* * PCI */ #ifdef CONFIG_PCI diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 34e4295..1754595 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -45,7 +45,16 @@ #define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SPL +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_MAX_SIZE 2048 +#define CONFIG_SPL_NAND_SUPPORT + +#define CONFIG_SPL_TEXT_BASE 0x87dc0000 +#define CONFIG_SYS_TEXT_BASE 0x87e00000 + +#ifndef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT #endif @@ -60,8 +69,6 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_HW_WATCHDOG -#define CONFIG_IMX_WATCHDOG #define CONFIG_MXC_GPIO #define CONFIG_HARD_SPI @@ -116,7 +123,7 @@ "bootcmd=run bootcmd_net\0" \ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ "tftpboot 0x81000000 uImage-mx31; bootm\0" \ - "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \ + "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ "nand erase 0x0 0x40000; " \ "nand write 0x81000000 0x0 0x40000\0" @@ -163,7 +170,7 @@ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) + CONFIG_SYS_INIT_RAM_SIZE) /*----------------------------------------------------------------------- * FLASH and environment organization @@ -189,10 +196,10 @@ /* NAND configuration for the NAND_SPL */ /* Start copying real U-boot from the second page */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 /* Load U-Boot to this address */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 62cb42b..148f7a2 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -41,6 +41,16 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MXC_GPIO +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI +#define CONFIG_NAND_MXC +#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI +#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_MXC_NAND_HWECC +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_CMD_NAND + #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 8506604..965330a 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -148,6 +148,7 @@ #define CONFIG_CMDLINE_EDITING /* add command line history */ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_CMD_BOOTMENU /* ANSI terminal Boot Menu */ #define CONFIG_CMD_CLEAR /* ANSI terminal clear screen command */ #ifdef ONENAND_SUPPORT @@ -287,8 +288,6 @@ int rx51_kp_getc(void); #endif /* Environment information */ -#define CONFIG_BOOTDELAY 3 - #define CONFIG_EXTRA_ENV_SETTINGS \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ "usbtty=cdc_acm\0" \ @@ -360,10 +359,40 @@ int rx51_kp_getc(void); "fi\0" \ "emmcboot=setenv mmcnum 1; run trymmcboot\0" \ "sdboot=setenv mmcnum 0; run trymmcboot\0" \ + "menucmd=bootmenu\0" \ + "bootmenu_0=Attached kernel=run attachboot\0" \ + "bootmenu_1=Internal eMMC=run emmcboot\0" \ + "bootmenu_2=External SD card=run sdboot\0" \ + "bootmenu_3=U-Boot boot order=boot\0" \ + "bootmenu_delay=30\0" \ "" #define CONFIG_PREBOOT \ - "if run slide; then true; else run attachboot; fi;" \ + "setenv mmcnum 1; setenv mmcpart 1;" \ + "setenv mmcscriptfile bootmenu.scr;" \ + "if run switchmmc; then " \ + "setenv mmcdone true;" \ + "setenv mmctype fat;" \ + "if run scriptload; then true; else " \ + "setenv mmctype ext2;" \ + "if run scriptload; then true; else " \ + "setenv mmctype ext4;" \ + "if run scriptload; then true; else " \ + "setenv mmcdone false;" \ + "fi;" \ + "fi;" \ + "fi;" \ + "if ${mmcdone}; then " \ + "run scriptboot;" \ + "fi;" \ + "fi;" \ + "if run slide; then true; else " \ + "setenv bootmenu_delay 0;" \ + "setenv bootdelay 0;" \ + "fi" + +#define CONFIG_POSTBOOTMENU \ + "echo;" \ "echo Extra commands:;" \ "echo run sercon - Use serial port for control.;" \ "echo run usbcon - Use usbtty for control.;" \ @@ -379,6 +408,11 @@ int rx51_kp_getc(void); "run attachboot;" \ "echo" +#define CONFIG_BOOTDELAY 30 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_MENU +#define CONFIG_MENU_SHOW + /* * Miscellaneous configurable options */ diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 1abf259..04e8d3a 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -67,6 +67,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 +#define CONFIG_OF_LIBFDT /* * Size of malloc() pool @@ -189,7 +190,7 @@ #define CONFIG_SYS_TIMERBASE OMAP2420_GPT2 #define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) +#define CONFIG_SYS_HZ 1000 /*----------------------------------------------------------------------- * Physical Memory Map @@ -220,7 +221,7 @@ #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_OFFSET 0x80000 /* environment starts here */ #else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_128K) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + SZ_256K) #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE #define CONFIG_ENV_OFFSET ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */ diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 6ae6a0f..1fd3097 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -138,6 +138,10 @@ */ #define CONFIG_BOOTDELAY 3 +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 #define CONFIG_ENV_OVERWRITE @@ -145,6 +149,10 @@ "loadaddr=0x82000000\0" \ "console=ttyO2,115200n8\0" \ "fdt_high=0xffffffff\0" \ + "fdtaddr=0x80f80000\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ "usbtty=cdc_acm\0" \ "vram=16M\0" \ "mmcdev=0\0" \ @@ -160,12 +168,19 @@ "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ "env import -t ${loadaddr} ${filesize}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ "mmcboot=echo Booting from mmc${mmcdev} ...; " \ "run mmcargs; " \ - "bootm ${loadaddr}\0" \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "findfdt="\ + "if test $board_name = sdp4430; then " \ + "setenv fdtfile omap4-sdp.dtb; fi; " \ + "if test $board_name = panda; then " \ + "setenv fdtfile omap4-panda-es.dtb; fi\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ #define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ "if run loadbootscript; then " \ @@ -179,7 +194,8 @@ "run uenvcmd;" \ "fi;" \ "fi;" \ - "if run loaduimage; then " \ + "if run loadimage; then " \ + "run loadfdt;" \ "run mmcboot; " \ "fi; " \ "fi" diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h index 40ca9bb..c5797a2 100644 --- a/include/configs/omap5912osk.h +++ b/include/configs/omap5912osk.h @@ -134,7 +134,7 @@ */ #define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ #define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) +#define CONFIG_SYS_HZ 1000 /*----------------------------------------------------------------------- * Physical Memory Map @@ -178,12 +178,15 @@ */ #define CONFIG_ENV_IS_IN_FLASH 1 /* addr of environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */ +#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_OFFSET 0x40000 /* environment starts here */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR PHYS_SRAM +#define CONFIG_SYS_INIT_RAM_SIZE (250 * 1024) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE) #endif /* __CONFIG_H */ diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index af97564..c21c387 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -85,8 +85,7 @@ #define CONFIG_SYS_NS16550_COM3 UART3_BASE #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} + /* I2C */ #define CONFIG_HARD_I2C #define CONFIG_SYS_I2C_SPEED 100000 @@ -94,19 +93,12 @@ #define CONFIG_DRIVER_OMAP34XX_I2C #define CONFIG_I2C_MULTI_BUS - /* MMC */ #define CONFIG_GENERIC_MMC #define CONFIG_MMC #define CONFIG_OMAP_HSMMC #define CONFIG_DOS_PARTITION -/* MMC ENV related defines */ -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ -#define CONFIG_ENV_OFFSET 0xE0000 -#define CONFIG_CMD_SAVEENV - #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Flash */ @@ -124,7 +116,6 @@ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_I2C /* I2C serial bus support */ #define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_SAVEENV /* Disabled commands */ #undef CONFIG_CMD_NET @@ -137,17 +128,31 @@ */ #define CONFIG_BOOTDELAY 3 +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_EXT4 #define CONFIG_ENV_OVERWRITE +#ifndef PARTS_DEFAULT +#define PARTS_DEFAULT +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyO2,115200n8\0" \ + "fdt_high=0xffffffff\0" \ + "fdtaddr=0x80f80000\0" \ + "bootpart=0:2\0" \ + "bootdir=/boot\0" \ + "bootfile=zImage\0" \ "usbtty=cdc_acm\0" \ "vram=16M\0" \ + "partitions=" PARTS_DEFAULT "\0" \ "mmcdev=0\0" \ "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ + "mmcrootfstype=ext4 rootwait\0" \ "mmcargs=setenv bootargs console=${console} " \ "vram=${vram} " \ "root=${mmcroot} " \ @@ -155,19 +160,35 @@ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ + "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ + "env import -t ${loadaddr} ${filesize}\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ "mmcboot=echo Booting from mmc${mmcdev} ...; " \ "run mmcargs; " \ - "bootm ${loadaddr}\0" \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ + "findfdt="\ + "if test $board_name = omap5_uevm; then " \ + "setenv fdtfile omap5-uevm.dtb; fi;\0 " \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile};\0" \ #define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "fi; " \ + "if run loadbootenv; then " \ + "run importbootenv; " \ + "fi;" \ + "if test -n ${uenvcmd}; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "fi;" \ + "if run loadimage; then " \ + "run loadfdt; " \ + "run mmcboot; " \ "fi; " \ "fi" diff --git a/include/configs/omap5_evm.h b/include/configs/omap5_uevm.h index 22a8e13..240fdfc 100644 --- a/include/configs/omap5_evm.h +++ b/include/configs/omap5_uevm.h @@ -28,6 +28,11 @@ #ifndef __CONFIG_OMAP5_EVM_H #define __CONFIG_OMAP5_EVM_H +/* Define the default GPT table for eMMC */ +#define PARTS_DEFAULT \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" + #include <configs/omap5_common.h> /* TWL6035 */ @@ -35,6 +40,18 @@ #define CONFIG_TWL6035_POWER #endif +/* MMC ENV related defines */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ +#define CONFIG_ENV_OFFSET 0xE0000 +#define CONFIG_CMD_SAVEENV + +/* Enhance our eMMC support / experience. */ +#define CONFIG_CMD_GPT +#define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + #define CONFIG_SYS_PROMPT "OMAP5430 EVM # " #endif /* __CONFIG_OMAP5_EVM_H */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 964bfcd..7ed634b 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -164,7 +164,7 @@ #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_TEXT_BASE 0xfffff000 -#define CONFIG_SPL_MAX_SIZE (4 * 1024) +#define CONFIG_SPL_MAX_SIZE 4096 #ifdef CONFIG_SYS_INIT_L2_ADDR /* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */ diff --git a/include/configs/palmld.h b/include/configs/palmld.h index 3f9802c..4ee2e46 100644 --- a/include/configs/palmld.h +++ b/include/configs/palmld.h @@ -72,6 +72,7 @@ #define CONFIG_CMD_MMC #define CONFIG_CMD_IDE #define CONFIG_LCD +#define CONFIG_PXA_LCD /* * MMC Card Configuration diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h index 64771e7..70fe05c 100644 --- a/include/configs/palmtc.h +++ b/include/configs/palmtc.h @@ -74,6 +74,7 @@ #define CONFIG_CMD_ENV #define CONFIG_CMD_MMC #define CONFIG_LCD +#define CONFIG_PXA_LCD /* * MMC Card Configuration diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 63ab123..d0ea74e 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -21,8 +21,7 @@ #define CONFIG_AM33XX -#include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> #define CONFIG_DMA_COHERENT #define CONFIG_DMA_COHERENT_SIZE (1 << 20) diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h index 671e9eb..306abcc 100644 --- a/include/configs/pdm360ng.h +++ b/include/configs/pdm360ng.h @@ -68,7 +68,6 @@ #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R #define CONFIG_SYS_IMMR 0x80000000 @@ -206,6 +205,9 @@ #define CONFIG_SYS_SRAM_BASE 0x50000000 #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ +#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH1_BASE +#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE + /* ALE active low, data size 4 bytes */ #define CONFIG_SYS_CS0_CFG 0x05059350 /* ALE active low, data size 4 bytes */ @@ -213,6 +215,9 @@ #define CONFIG_SYS_MRAM_BASE 0x50040000 #define CONFIG_SYS_MRAM_SIZE 0x00020000 +#define CONFIG_SYS_CS2_START CONFIG_SYS_MRAM_BASE +#define CONFIG_SYS_CS2_SIZE CONFIG_SYS_MRAM_SIZE + /* ALE active low, data size 4 bytes */ #define CONFIG_SYS_CS2_CFG 0x05059110 @@ -296,6 +301,23 @@ #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC6_RX_ADDR /* + * Clocks in use + */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_NFC_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN | \ + CLOCK_SCCR1_TPR_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_DIU_EN | \ + CLOCK_SCCR2_I2C_EN) + +/* * Used PSC UART devices */ #define CONFIG_SYS_PSC1 diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 5a15af6..39c167f 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -59,6 +59,7 @@ #undef CONFIG_LCD #ifdef CONFIG_LCD +#define CONFIG_PXA_LCD #define CONFIG_SHARP_LM8V31 #endif diff --git a/include/configs/rpi_b.h b/include/configs/rpi_b.h index cf62e45..c18b35b 100644 --- a/include/configs/rpi_b.h +++ b/include/configs/rpi_b.h @@ -23,6 +23,7 @@ #define CONFIG_ARM1176 #define CONFIG_BCM2835 #define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_DCACHE_OFF /* * 2835 is a SKU in a series for which the 2708 is the first or primary SoC, * so 2708 has historically been used rather than a dedicated 2835 ID. @@ -30,7 +31,7 @@ #define CONFIG_MACH_TYPE MACH_TYPE_BCM2708 /* Timer */ -#define CONFIG_SYS_HZ 1000000 +#define CONFIG_SYS_HZ 1000 /* Memory layout */ #define CONFIG_NR_DRAM_BANKS 1 @@ -50,6 +51,7 @@ #define CONFIG_SYS_MALLOC_LEN SZ_4M #define CONFIG_SYS_MEMTEST_START 0x00100000 #define CONFIG_SYS_MEMTEST_END 0x00200000 +#define CONFIG_LOADADDR 0x00200000 /* Flash */ #define CONFIG_SYS_NO_FLASH @@ -57,6 +59,24 @@ /* Devices */ /* GPIO */ #define CONFIG_BCM2835_GPIO +/* LCD */ +#define CONFIG_LCD +#define LCD_BPP LCD_COLOR16 +/* + * Prevent allocation of RAM for FB; the real FB address is queried + * dynamically from the VideoCore co-processor, and comes from RAM + * not owned by the ARM CPU. + */ +#define CONFIG_FB_ADDR 0 +#define CONFIG_VIDEO_BCM2835 +#define CONFIG_SYS_WHITE_ON_BLACK + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_MMC_SDHCI_IO_ACCESSORS +#define CONFIG_BCM2835_SDHCI /* Console UART */ #define CONFIG_PL011_SERIAL @@ -73,7 +93,59 @@ /* Environment */ #define CONFIG_ENV_SIZE SZ_16K #define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_SYS_LOAD_ADDR 0x1000000 +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it low in memory to avoid conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "stdin=serial\0" \ + "stderr=serial,lcd\0" \ + "stdout=serial,lcd\0" \ + "scriptaddr=0x00000000\0" \ + "kernel_addr_r=0x01000000\0" \ + "fdt_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x02100000\0" \ + "boot_targets=mmc0\0" \ + \ + "script_boot=" \ + "if fatload ${devtype} ${devnum}:1 " \ + "${scriptaddr} boot.scr.uimg; then " \ + "source ${scriptaddr}; " \ + "fi;\0" \ + \ + "mmc_boot=" \ + "setenv devtype mmc; " \ + "if mmc dev ${devnum}; then " \ + "run script_boot; " \ + "fi\0" \ + \ + "bootcmd_mmc0=setenv devnum 0; run mmc_boot\0" \ + +#define CONFIG_BOOTCOMMAND \ + "for target in ${boot_targets}; do run bootcmd_${target}; done" + +#define CONFIG_BOOTDELAY 2 /* Shell */ #define CONFIG_SYS_HUSH_PARSER @@ -88,6 +160,13 @@ #include <config_cmd_default.h> #define CONFIG_CMD_BOOTZ #define CONFIG_CMD_GPIO +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART +#define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT /* Some things don't make sense on this HW or yet */ #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_NET diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h deleted file mode 100644 index d4dc8ef..0000000 --- a/include/configs/smdk6400.h +++ /dev/null @@ -1,296 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * Gary Jennejohn <garyj@denx.de> - * David Mueller <d.mueller@elsoft.ch> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_S3C6400 1 /* in a SAMSUNG S3C6400 SoC */ -#define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */ -#define CONFIG_SMDK6400 1 /* on a SAMSUNG SMDK6400 Board */ - -#define CONFIG_PERIPORT_REMAP -#define CONFIG_PERIPORT_BASE 0x70000000 -#define CONFIG_PERIPORT_SIZE 0x13 - -#define CONFIG_SYS_IRAM_BASE 0x0c000000 /* Internal SRAM base address */ -#define CONFIG_SYS_IRAM_SIZE 0x2000 /* 8 KB of internal SRAM memory */ -#define CONFIG_SYS_IRAM_END (CONFIG_SYS_IRAM_BASE + CONFIG_SYS_IRAM_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IRAM_END - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_SDRAM_BASE 0x50000000 - -/* input clock of PLL: SMDK6400 has 12MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000) -#define CONFIG_ENABLE_MMU -#endif - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG - -/* - * Architecture magic and machine type - */ -#define CONFIG_MACH_TYPE 1270 - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - -/* - * Hardware drivers - */ -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x18800300 -#define CONFIG_CS8900_BUS16 /* follow the Linux driver */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK6400 */ - -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ - -#define CONFIG_CMDLINE_EDITING - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -/*********************************************************** - * Command definition - ***********************************************************/ -#include <config_cmd_default.h> - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_NAND -#if defined(CONFIG_BOOT_ONENAND) -#define CONFIG_CMD_ONENAND -#endif -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 - -#define CONFIG_BOOTDELAY 3 - -#define CONFIG_ZERO_BOOTDELAY_CHECK - -#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "SMDK6400 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load address */ - -#define CONFIG_SYS_HZ 1000 - -/********************************** - Support Clock Settings - ********************************** - Setting SYNC ASYNC - ---------------------------------- - 667_133_66 X O - 533_133_66 O O - 400_133_66 X O - 400_100_50 O O - **********************************/ - -/*#define CONFIG_CLK_667_133_66*/ -#define CONFIG_CLK_533_133_66 -/* -#define CONFIG_CLK_400_100_50 -#define CONFIG_CLK_400_133_66 -#define CONFIG_SYNC_MODE -*/ - -/* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB in Bank #1 */ - -#define CONFIG_SYS_FLASH_BASE 0x10000000 -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -/* AM29LV160B has 35 sectors, AM29LV800B - 19 */ -#define CONFIG_SYS_MAX_FLASH_SECT 40 - -#define CONFIG_AMD_LV800 -#define CONFIG_SYS_FLASH_CFI 1 /* Use CFI parameters (needed?) */ -/* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant */ -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_LEGACY_512Kx16 - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* - * SMDK6400 board specific data - */ - -#define CONFIG_IDENT_STRING " for SMDK6400" - -/* base address for uboot */ -#define CONFIG_SYS_PHY_UBOOT_BASE (CONFIG_SYS_SDRAM_BASE + 0x07e00000) -/* total memory available to uboot */ -#define CONFIG_SYS_UBOOT_SIZE (1024 * 1024) - -/* Put environment copies after the end of U-Boot owned RAM */ -#define CONFIG_NAND_ENV_DST (CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE) - -#ifdef CONFIG_ENABLE_MMU -#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000 -#define CONFIG_BOOTCOMMAND "nand read 0xc0018000 0x60000 0x1c0000;" \ - "bootm 0xc0018000" -#else -#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE -#define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \ - "bootm 0x50018000" -#endif - -/* NAND U-Boot load and start address */ -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_MAPPED_RAM_BASE + 0x07e00000) - -#define CONFIG_ENV_OFFSET 0x0040000 - -/* NAND configuration */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x70200010 -#define CONFIG_SYS_S3C_NAND_HWECC - -#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ -#define CONFIG_SYS_NAND_WP 1 -#define CONFIG_SYS_NAND_YAFFS_WRITE 1 /* support yaffs write */ -#define CONFIG_SYS_NAND_BBT_2NDPAGE 1 /* bad-block markers in 1st and 2nd pages */ - -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_PHY_UBOOT_BASE /* NUB load-addr */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* NUB start-addr */ - -#define CONFIG_SYS_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */ - -/* NAND chip page size */ -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -/* NAND chip block size */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -/* NAND chip page per block count */ -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -/* Location of the bad-block label */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -/* Extra address cycle for > 128MiB */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE - -/* Size of the block protected by one OOB (Spare Area in Samsung terminology) */ -#define CONFIG_SYS_NAND_ECCSIZE CONFIG_SYS_NAND_PAGE_SIZE -/* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */ -#define CONFIG_SYS_NAND_ECCBYTES 4 -/* Size of a single OOB region */ -#define CONFIG_SYS_NAND_OOBSIZE 64 -/* ECC byte positions */ -#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, \ - 56, 57, 58, 59, 60, 61, 62, 63} - -/* Boot configuration (define only one of next 3) */ -#define CONFIG_BOOT_NAND -/* None of these are currently implemented. Left from the original Samsung - * version for reference -#define CONFIG_BOOT_NOR -#define CONFIG_BOOT_MOVINAND -#define CONFIG_BOOT_ONENAND -*/ - -#define CONFIG_NAND -#define CONFIG_NAND_S3C64XX -/* Unimplemented or unsupported. See comment above. -#define CONFIG_ONENAND -#define CONFIG_MOVINAND -*/ - -/* Settings as above boot configuration */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_BOOTARGS "console=ttySAC,115200" - -#if !defined(CONFIG_ENABLE_MMU) -#define CONFIG_CMD_USB 1 -#define CONFIG_USB_S3C64XX -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x74300000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "s3c6400" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 - -#define CONFIG_USB_STORAGE 1 -#endif -#define CONFIG_DOS_PARTITION 1 - -#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_ENABLE_MMU) -# error "usb_ohci.c is currently broken with MMU enabled." -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/snow.h b/include/configs/snow.h new file mode 100644 index 0000000..b8460fd --- /dev/null +++ b/include/configs/snow.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 Snow board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_SNOW_H +#define __CONFIG_SNOW_H + +#include <configs/exynos5250-dt.h> + +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-snow + +#endif /* __CONFIG_SNOW_H */ diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h index 2b24997..3c8c74d 100644 --- a/include/configs/svm_sc8xx.h +++ b/include/configs/svm_sc8xx.h @@ -38,6 +38,7 @@ /* SC85T,SC860T, FEL8xx-AT(855T/860T) */ /*#define CONFIG_FEL8xx_AT */ /*#define CONFIG_LCD */ +/*#define CONFIG_MPC8XX_LCD*/ /* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */ /* #define CONFIG_50MHz */ /* #define CONFIG_66MHz */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index f2a70b1..bf18699 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -150,6 +150,10 @@ MEM_LAYOUT_ENV_SETTINGS \ BOOTCMDS_COMMON +#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) +#define CONFIG_FDT_SPI +#endif + /* overrides for SPL build here */ #ifdef CONFIG_SPL_BUILD diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 4cc35e5..036ded0 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -167,6 +167,7 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SYS_GENERIC_BOARD /* Misc utility code */ #define CONFIG_BOUNCE_BUFFER diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index e464e06..395a657 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -28,6 +28,7 @@ /* * Errata configuration */ +#define CONFIG_ARM_ERRATA_716044 #define CONFIG_ARM_ERRATA_742230 #define CONFIG_ARM_ERRATA_751472 diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h new file mode 100644 index 0000000..16547e3 --- /dev/null +++ b/include/configs/ti814x_evm.h @@ -0,0 +1,221 @@ +/* + * ti814x_evm.h + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __CONFIG_TI814X_EVM_H +#define __CONFIG_TI814X_EVM_H + +#define CONFIG_TI81XX +#define CONFIG_TI814X +#define CONFIG_SYS_NO_FLASH + +#include <asm/arch/omap.h> + +#define CONFIG_DMA_COHERENT +#define CONFIG_DMA_COHERENT_SIZE (1 << 20) + +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* Use HUSH for command parsing */ +#define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_SYS_NO_FLASH +#define CONFIG_MACH_TYPE MACH_TYPE_TI8148EVM + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG /* for ramdisk support */ + +/* commands to include */ +# include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_VERSION_VARIABLE + +#define CONFIG_BOOTDELAY 1 /* negative for no autoboot */ +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x80F80000\0" \ + "rdaddr=0x81000000\0" \ + "bootfile=/boot/uImage\0" \ + "fdtfile=\0" \ + "console=ttyO0,115200n8\0" \ + "optargs=\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 ro\0" \ + "mmcrootfstype=ext4 rootwait\0" \ + "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ + "ramrootfstype=ext2\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ + "bootenv=uEnv.txt\0" \ + "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "ramargs=setenv bootargs console=${console} " \ + "${optargs} " \ + "root=${ramroot} " \ + "rootfstype=${ramrootfstype}\0" \ + "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ + "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ + "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "ramboot=echo Booting from ramdisk ...; " \ + "run ramargs; " \ + "bootm ${loadaddr}\0" \ + "fdtfile=ti814x-evm.dtb\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "echo SD/MMC found on device ${mmcdev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loaduimage; then " \ + "run mmcboot;" \ + "fi;" \ + "fi;" \ + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#define CONFIG_CMD_ECHO + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MEMTEST_START PHYS_DRAM_1 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ + + PHYS_DRAM_1_SIZE - (8 << 12)) + +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */ +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ + +#define CONFIG_OMAP_GPIO +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +/** + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 banks of DRAM */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ +#define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + +/** + * Platform/Board specific defs + */ +#define CONFIG_SYS_TIMERBASE 0x4802E000 +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +#define CONFIG_ENV_IS_NOWHERE + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x40300000 +#define CONFIG_SPL_MAX_SIZE ((128 - 18) * 1024) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_BOARD_INIT + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80800000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80800000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* Unsupported features */ +#undef CONFIG_USE_IRQ + +#endif /* ! __CONFIG_TI814X_EVM_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index 63745ac..fd58558 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -199,6 +199,7 @@ "splfile=falcon.bin\0" \ "spl_export=" \ "setexpr spl_imgsize ${splsize} + 8 ;" \ + "setenv spl_imgsize 0x${spl_imgsize};" \ "setexpr spl_imgaddr ${spladdr} - 8 ;" \ "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ @@ -316,4 +317,9 @@ #define CONFIG_VIDEO_BMP_GZIP #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12)) +#define CONFIG_CMD_USB_MASS_STORAGE +#if defined(CONFIG_CMD_USB_MASS_STORAGE) +#define CONFIG_USB_GADGET_MASS_STORAGE +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index ebd7a25..4c75cc5 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -125,6 +125,8 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ +#define CONFIG_NAND_OMAP_BCH8 +#define CONFIG_BCH /* commands to include */ #include <config_cmd_default.h> @@ -290,7 +292,7 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ -#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ +#define CONFIG_SPL_MAX_SIZE (55 * 1024) /* 7 KB for stack */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ @@ -303,11 +305,14 @@ #define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCPOS {12, 13, 14, 15, 16, 17, 18, 19, 20,\ + 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\ + 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46,\ + 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,\ + 60, 61, 62, 63} #define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCBYTES 13 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h index 0644f7a..b925314 100644 --- a/include/configs/trimslice.h +++ b/include/configs/trimslice.h @@ -46,7 +46,7 @@ #define CONFIG_BOARD_EARLY_INIT_F /* SPI */ -#define CONFIG_TEGRA_SPI +#define CONFIG_TEGRA20_SFLASH #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_WINBOND #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 diff --git a/include/configs/tx25.h b/include/configs/tx25.h index 80194d8..e72f8f6 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -21,6 +21,7 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/arch/imx-regs.h> /* * KARO TX25 board - SoC Configuration @@ -31,8 +32,14 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 kB for U-Boot */ -/* NAND BOOT is the only boot method */ -#define CONFIG_NAND_U_BOOT +#define CONFIG_SPL +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_MAX_SIZE 2048 +#define CONFIG_SPL_NAND_SUPPORT + +#define CONFIG_SPL_TEXT_BASE 0x810c0000 +#define CONFIG_SYS_TEXT_BASE 0x81200000 #ifndef MACH_TYPE_TX25 #define MACH_TYPE_TX25 2177 @@ -40,16 +47,16 @@ #define CONFIG_MACH_TYPE MACH_TYPE_TX25 -#ifdef CONFIG_NAND_SPL +#ifdef CONFIG_SPL_BUILD /* Start copying real U-boot from the second page */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 -#define CONFIG_SYS_NAND_U_BOOT_DST (0x81200000) +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_SPARE_SIZE 64 +#define CONFIG_SYS_NAND_OOBSIZE 64 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_SIZE (128 * 1024 * 1024) @@ -173,7 +180,6 @@ /* additions for new relocation code, must be added to all boards */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (IMX_RAM_BASE + IMX_RAM_SIZE) #endif /* __CONFIG_H */ diff --git a/include/configs/v37.h b/include/configs/v37.h index e36d249..f9965db 100644 --- a/include/configs/v37.h +++ b/include/configs/v37.h @@ -39,6 +39,7 @@ #define CONFIG_SYS_TEXT_BASE 0x40000000 #define CONFIG_LCD +#define CONFIG_MPC8XX_LCD #define CONFIG_SHARP_LQ084V1DG21 #undef CONFIG_LCD_LOGO diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index b92f70b..f79dd3b 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -103,6 +103,7 @@ #ifdef CONFIG_CMD_SPI #define CONFIG_SOFT_SPI #define CONFIG_LCD +#define CONFIG_PXA_LCD #define CONFIG_LMS283GF05 #define CONFIG_VIDEO_LOGO #define CONFIG_CMD_BMP diff --git a/include/dfu.h b/include/dfu.h index 5350d79..a107f4b 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -52,14 +52,26 @@ struct mmc_internal_data { unsigned int part; }; +struct nand_internal_data { + /* RAW programming */ + u64 start; + u64 size; + + unsigned int dev; + unsigned int part; +}; + static inline unsigned int get_mmc_blk_size(int dev) { return find_mmc_device(dev)->read_bl_len; } -#define DFU_NAME_SIZE 32 -#define DFU_CMD_BUF_SIZE 128 -#define DFU_DATA_BUF_SIZE (1024*1024*4) /* 4 MiB */ +#define DFU_NAME_SIZE 32 +#define DFU_CMD_BUF_SIZE 128 +#define DFU_DATA_BUF_SIZE (1024*1024*8) /* 8 MiB */ +#ifndef CONFIG_SYS_DFU_MAX_FILE_SIZE +#define CONFIG_SYS_DFU_MAX_FILE_SIZE (4 << 20) /* 4 MiB */ +#endif struct dfu_entity { char name[DFU_NAME_SIZE]; @@ -71,12 +83,32 @@ struct dfu_entity { union { struct mmc_internal_data mmc; + struct nand_internal_data nand; } data; - int (*read_medium)(struct dfu_entity *dfu, void *buf, long *len); - int (*write_medium)(struct dfu_entity *dfu, void *buf, long *len); + int (*read_medium)(struct dfu_entity *dfu, + u64 offset, void *buf, long *len); + + int (*write_medium)(struct dfu_entity *dfu, + u64 offset, void *buf, long *len); + + int (*flush_medium)(struct dfu_entity *dfu); struct list_head list; + + /* on the fly state */ + u32 crc; + u64 offset; + int i_blk_seq_num; + u8 *i_buf; + u8 *i_buf_start; + u8 *i_buf_end; + long r_left; + long b_left; + + u32 bad_skip; /* for nand use */ + + unsigned int inited:1; }; int dfu_config_entities(char *s, char *interface, int num); @@ -100,4 +132,15 @@ static inline int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *s) return -1; } #endif + +#ifdef CONFIG_DFU_NAND +extern int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s); +#else +static inline int dfu_fill_entity_nand(struct dfu_entity *dfu, char *s) +{ + puts("NAND support not available!\n"); + return -1; +} +#endif + #endif /* __DFU_ENTITY_H_ */ diff --git a/include/env_callback.h b/include/env_callback.h index e89b6da..b856000 100644 --- a/include/env_callback.h +++ b/include/env_callback.h @@ -67,7 +67,6 @@ struct env_clbk_tbl { int flags); }; -struct env_clbk_tbl *find_env_callback(const char *); void env_callback_init(ENTRY *var_entry); /* diff --git a/include/environment.h b/include/environment.h index e64b43d..4c6a37b 100644 --- a/include/environment.h +++ b/include/environment.h @@ -96,6 +96,24 @@ extern unsigned long nand_env_oob_offset; # endif #endif /* CONFIG_ENV_IS_IN_NAND */ +#if defined(CONFIG_ENV_IS_IN_UBI) +# ifndef CONFIG_ENV_UBI_PART +# error "Need to define CONFIG_ENV_UBI_PART when using CONFIG_ENV_IS_IN_UBI" +# endif +# ifndef CONFIG_ENV_UBI_VOLUME +# error "Need to define CONFIG_ENV_UBI_VOLUME when using CONFIG_ENV_IS_IN_UBI" +# endif +# if defined(CONFIG_ENV_UBI_VOLUME_REDUND) +# define CONFIG_SYS_REDUNDAND_ENVIRONMENT +# endif +# ifndef CONFIG_ENV_SIZE +# error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_UBI" +# endif +# ifndef CONFIG_CMD_UBI +# error "Need to define CONFIG_CMD_UBI when using CONFIG_ENV_IS_IN_UBI" +# endif +#endif /* CONFIG_ENV_IS_IN_UBI */ + /* Embedded env is only supported for some flash types */ #ifdef CONFIG_ENV_IS_EMBEDDED # if !defined(CONFIG_ENV_IS_IN_FLASH) && \ diff --git a/include/fdtdec.h b/include/fdtdec.h index 2189483..844991e 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -38,11 +38,13 @@ */ #ifdef CONFIG_PHYS_64BIT typedef u64 fdt_addr_t; +typedef u64 fdt_size_t; #define FDT_ADDR_T_NONE (-1ULL) #define fdt_addr_to_cpu(reg) be64_to_cpu(reg) #define fdt_size_to_cpu(reg) be64_to_cpu(reg) #else typedef u32 fdt_addr_t; +typedef u32 fdt_size_t; #define FDT_ADDR_T_NONE (-1U) #define fdt_addr_to_cpu(reg) be32_to_cpu(reg) #define fdt_size_to_cpu(reg) be32_to_cpu(reg) @@ -75,6 +77,7 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */ COMPAT_NVIDIA_TEGRA20_SLINK, /* Tegra 2 SPI SLINK controller */ + COMPAT_NVIDIA_TEGRA114_SPI, /* Tegra 114 SPI controller */ COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */ COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */ COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */ @@ -83,7 +86,12 @@ enum fdt_compat_id { COMPAT_SAMSUNG_EXYNOS_SPI, /* Exynos SPI */ COMPAT_SAMSUNG_EXYNOS_EHCI, /* Exynos EHCI controller */ COMPAT_SAMSUNG_EXYNOS_USB_PHY, /* Exynos phy controller for usb2.0 */ + COMPAT_SAMSUNG_EXYNOS_TMU, /* Exynos TMU */ + COMPAT_SAMSUNG_EXYNOS_FIMD, /* Exynos Display controller */ + COMPAT_SAMSUNG_EXYNOS5_DP, /* Exynos Display port controller */ COMPAT_MAXIM_MAX77686_PMIC, /* MAX77686 PMIC */ + COMPAT_GENERIC_SPI_FLASH, /* Generic SPI Flash chip */ + COMPAT_MAXIM_98095_CODEC, /* MAX98095 Codec */ COMPAT_COUNT, }; @@ -200,6 +208,19 @@ fdt_addr_t fdtdec_get_addr(const void *blob, int node, const char *prop_name); /** + * Look up an address property in a node and return it as an address. + * The property must hold one address with a length. This is only tested + * on 32-bit machines. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @return address, if found, or FDT_ADDR_T_NONE if not + */ +fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, + const char *prop_name, fdt_size_t *sizep); + +/** * Look up a 32-bit integer property in a node and return it. The property * must have at least 4 bytes of data. The value of the first cell is * returned. diff --git a/include/fpga.h b/include/fpga.h index e0b1fe7..30a4e6a 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -31,14 +31,6 @@ #define CONFIG_MAX_FPGA_DEVICES 5 #endif -/* these probably belong somewhere else */ -#ifndef FALSE -#define FALSE (0) -#endif -#ifndef TRUE -#define TRUE (!FALSE) -#endif - /* CONFIG_FPGA bit assignments */ #define CONFIG_SYS_FPGA_MAN(x) (x) #define CONFIG_SYS_FPGA_DEV(x) ((x) << 8 ) diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h deleted file mode 100644 index ff537b4..0000000 --- a/include/fsl_nfc.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __FSL_NFC_H -#define __FSL_NFC_H - -/* - * Register map and bit definitions for the Freescale NAND Flash Controller - * present in various i.MX devices. - * - * MX31 and MX27 have version 1, which has: - * 4 512-byte main buffers and - * 4 16-byte spare buffers - * to support up to 2K byte pagesize nand. - * Reading or writing a 2K page requires 4 FDI/FDO cycles. - * - * MX25 and MX35 have version 2.1, which has: - * 8 512-byte main buffers and - * 8 64-byte spare buffers - * to support up to 4K byte pagesize nand. - * Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle. - * Also some of registers are moved and/or changed meaning as seen below. - */ -#if defined(CONFIG_MX27) || defined(CONFIG_MX31) -#define MXC_NFC_V1 -#define is_mxc_nfc_1() 1 -#define is_mxc_nfc_21() 0 -#elif defined(CONFIG_MX25) || defined(CONFIG_MX35) -#define MXC_NFC_V2_1 -#define is_mxc_nfc_1() 0 -#define is_mxc_nfc_21() 1 -#else -#error "MXC NFC implementation not supported" -#endif - -#if defined(MXC_NFC_V1) -#define NAND_MXC_NR_BUFS 4 -#define NAND_MXC_SPARE_BUF_SIZE 16 -#define NAND_MXC_REG_OFFSET 0xe00 -#define NAND_MXC_2K_MULTI_CYCLE -#elif defined(MXC_NFC_V2_1) -#define NAND_MXC_NR_BUFS 8 -#define NAND_MXC_SPARE_BUF_SIZE 64 -#define NAND_MXC_REG_OFFSET 0x1e00 -#endif - -struct fsl_nfc_regs { - u8 main_area[NAND_MXC_NR_BUFS][0x200]; - u8 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE]; - /* - * reserved size is offset of nfc registers - * minus total main and spare sizes - */ - u8 reserved1[NAND_MXC_REG_OFFSET - - NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)]; -#if defined(MXC_NFC_V1) - u16 buf_size; - u16 reserved2; - u16 buf_addr; - u16 flash_addr; - u16 flash_cmd; - u16 config; - u16 ecc_status_result; - u16 rsltmain_area; - u16 rsltspare_area; - u16 wrprot; - u16 unlockstart_blkaddr; - u16 unlockend_blkaddr; - u16 nf_wrprst; - u16 config1; - u16 config2; -#elif defined(MXC_NFC_V2_1) - u16 reserved2[2]; - u16 buf_addr; - u16 flash_addr; - u16 flash_cmd; - u16 config; - u32 ecc_status_result; - u16 spare_area_size; - u16 wrprot; - u16 reserved3[2]; - u16 nf_wrprst; - u16 config1; - u16 config2; - u16 reserved4; - u16 unlockstart_blkaddr; - u16 unlockend_blkaddr; - u16 unlockstart_blkaddr1; - u16 unlockend_blkaddr1; - u16 unlockstart_blkaddr2; - u16 unlockend_blkaddr2; - u16 unlockstart_blkaddr3; - u16 unlockend_blkaddr3; -#endif -}; - -/* - * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command - * operation - */ -#define NFC_CMD 0x1 - -/* - * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address - * operation - */ -#define NFC_ADDR 0x2 - -/* - * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input - * operation - */ -#define NFC_INPUT 0x4 - -/* - * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data - * Output operation - */ -#define NFC_OUTPUT 0x8 - -/* - * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID - * operation - */ -#define NFC_ID 0x10 - -/* - * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read - * Status operation - */ -#define NFC_STATUS 0x20 - -/* - * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status - * operation - */ -#define NFC_INT 0x8000 - -#ifdef MXC_NFC_V2_1 -#define NFC_4_8N_ECC (1 << 0) -#endif -#define NFC_SP_EN (1 << 2) -#define NFC_ECC_EN (1 << 3) -#define NFC_INT_MSK (1 << 4) -#define NFC_BIG (1 << 5) -#define NFC_RST (1 << 6) -#define NFC_CE (1 << 7) -#define NFC_ONE_CYCLE (1 << 8) -#define NFC_FP_INT (1 << 11) - -#endif /* __FSL_NFC_H */ diff --git a/include/galileo/core.h b/include/galileo/core.h index c277509..95013fa 100644 --- a/include/galileo/core.h +++ b/include/galileo/core.h @@ -14,6 +14,7 @@ space). The macros take care of Big/Little endian conversions. /* includes */ #include "gt64260R.h" +#include <stdbool.h> extern unsigned int INTERNAL_REG_BASE_ADDR; @@ -110,11 +111,6 @@ extern unsigned int INTERNAL_REG_BASE_ADDR; #define _1G 0x40000000 #define _2G 0x80000000 -#ifndef BOOL_WAS_DEFINED -#define BOOL_WAS_DEFINED -typedef enum _bool{false,true} bool; -#endif - /* Little to Big endian conversion macros */ #ifdef LE /* Little Endian */ diff --git a/include/hw_sha.h b/include/hw_sha.h new file mode 100644 index 0000000..264936c --- /dev/null +++ b/include/hw_sha.h @@ -0,0 +1,50 @@ +/* + * Header file for SHA hardware acceleration + * + * Copyright (c) 2012 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ +#ifndef __HW_SHA_H +#define __HW_SHA_H + + +/** + * Computes hash value of input pbuf using h/w acceleration + * + * @param in_addr A pointer to the input buffer + * @param bufleni Byte length of input buffer + * @param out_addr A pointer to the output buffer. When complete + * 32 bytes are copied to pout[0]...pout[31]. Thus, a user + * should allocate at least 32 bytes at pOut in advance. + * @param chunk_size chunk size for sha256 + */ +void hw_sha256(const uchar * in_addr, uint buflen, + uchar * out_addr, uint chunk_size); + +/** + * Computes hash value of input pbuf using h/w acceleration + * + * @param in_addr A pointer to the input buffer + * @param bufleni Byte length of input buffer + * @param out_addr A pointer to the output buffer. When complete + * 32 bytes are copied to pout[0]...pout[31]. Thus, a user + * should allocate at least 32 bytes at pOut in advance. + * @param chunk_size chunk_size for sha1 + */ +void hw_sha1(const uchar * in_addr, uint buflen, + uchar * out_addr, uint chunk_size); +#endif diff --git a/include/ide.h b/include/ide.h index 158e1be..afea85c 100644 --- a/include/ide.h +++ b/include/ide.h @@ -85,4 +85,11 @@ void ide_output_data(int dev, const ulong *sect_buf, int words); void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts); void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts); +/** + * board_start_ide() - Start up the board IDE interfac + * + * @return 0 if ok + */ +int board_start_ide(void); + #endif /* _IDE_H */ diff --git a/include/image.h b/include/image.h index 8e285f9..4ad0e6b 100644 --- a/include/image.h +++ b/include/image.h @@ -84,6 +84,7 @@ #define IH_OS_UNITY 20 /* Unity OS */ #define IH_OS_INTEGRITY 21 /* INTEGRITY */ #define IH_OS_OSE 22 /* OSE */ +#define IH_OS_PLAN9 23 /* Plan 9 */ /* * CPU Architecture Codes (supported by Linux) diff --git a/arch/arm/cpu/arm1176/s3c64xx/reset.S b/include/initcall.h index eae572e..9e54fa5 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/reset.S +++ b/include/initcall.h @@ -1,6 +1,5 @@ /* - * Copyright (c) 2009 Samsung Electronics. - * Minkyu Kang <mk7.kang@samsung.com> + * Copyright (c) 2011 The Chromium OS Authors. * * See file CREDITS for list of people who contributed to this * project. @@ -12,7 +11,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -21,14 +20,6 @@ * MA 02111-1307 USA */ -#include <asm/arch/s3c6400.h> +typedef int (*init_fnc_t)(void); -.globl reset_cpu -reset_cpu: - ldr r1, =ELFIN_CLOCK_POWER_BASE - ldr r2, [r1, #SYS_ID_OFFSET] - ldr r3, =0xffff - and r2, r3, r2, lsr #12 - str r2, [r1, #SW_RST_OFFSET] -_loop_forever: - b _loop_forever +int initcall_run_list(init_fnc_t init_sequence[]); diff --git a/include/lcd.h b/include/lcd.h index 4ac4ddd..c6e7fc5 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -32,31 +32,22 @@ extern char lcd_is_enabled; extern int lcd_line_length; -extern int lcd_color_fg; -extern int lcd_color_bg; -/* - * Frame buffer memory information - */ -extern void *lcd_base; /* Start of framebuffer memory */ -extern void *lcd_console_address; /* Start of console buffer */ - -extern short console_col; -extern short console_row; extern struct vidinfo panel_info; -extern void lcd_ctrl_init (void *lcdbase); -extern void lcd_enable (void); -extern int board_splash_screen_prepare(void); +void lcd_ctrl_init(void *lcdbase); +void lcd_enable(void); +int board_splash_screen_prepare(void); /* setcolreg used in 8bpp/16bpp; initcolregs used in monochrome */ -extern void lcd_setcolreg (ushort regno, - ushort red, ushort green, ushort blue); -extern void lcd_initcolregs (void); +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue); +void lcd_initcolregs(void); + +int lcd_getfgcolor(void); /* gunzip_bmp used if CONFIG_VIDEO_BMP_GZIP */ -extern struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp); -extern int bmp_display(ulong addr, int x, int y); +struct bmp_image *gunzip_bmp(unsigned long addr, unsigned long *lenp); +int bmp_display(ulong addr, int x, int y); /** * Set whether we need to flush the dcache when changing the LCD image. This @@ -234,15 +225,6 @@ typedef struct vidinfo { u_char vl_vbpd; /* Wait end of frame */ u_char vl_cmd_allow_len; /* Wait end of frame */ - void (*cfg_gpio)(void); - void (*backlight_on)(unsigned int onoff); - void (*reset_lcd)(void); - void (*lcd_power_on)(void); - void (*cfg_ldo)(void); - void (*enable_ldo)(unsigned int onoff); - void (*mipi_power)(void); - void (*backlight_reset)(void); - unsigned int win_id; unsigned int init_delay; unsigned int power_on_delay; @@ -267,7 +249,6 @@ typedef struct vidinfo { unsigned int sclk_div; unsigned int dual_lcd_enabled; - } vidinfo_t; void init_panel_info(vidinfo_t *vid); @@ -292,14 +273,12 @@ extern vidinfo_t panel_info; /* Video functions */ #if defined(CONFIG_RBC823) -void lcd_disable (void); +void lcd_disable(void); #endif - -/* int lcd_init (void *lcdbase); */ -void lcd_putc (const char c); -void lcd_puts (const char *s); -void lcd_printf (const char *fmt, ...); +void lcd_putc(const char c); +void lcd_puts(const char *s); +void lcd_printf(const char *fmt, ...); void lcd_clear(void); int lcd_display_bitmap(ulong bmp_image, int x, int y); @@ -359,7 +338,7 @@ int lcd_get_size(int *line_length); * is connected, as we can't autodetect anything. */ #define CONFIG_SYS_HIGH 0 /* Pins are active high */ -#define CONFIG_SYS_LOW 1 /* Pins are active low */ +#define CONFIG_SYS_LOW 1 /* Pins are active low */ #define LCD_MONOCHROME 0 #define LCD_COLOR2 1 @@ -373,10 +352,10 @@ int lcd_get_size(int *line_length); # define LCD_INFO_Y (BMP_LOGO_HEIGHT + VIDEO_FONT_HEIGHT) #elif defined(CONFIG_LCD_LOGO) # define LCD_INFO_X (BMP_LOGO_WIDTH + 4 * VIDEO_FONT_WIDTH) -# define LCD_INFO_Y (VIDEO_FONT_HEIGHT) +# define LCD_INFO_Y VIDEO_FONT_HEIGHT #else -# define LCD_INFO_X (VIDEO_FONT_WIDTH) -# define LCD_INFO_Y (VIDEO_FONT_HEIGHT) +# define LCD_INFO_X VIDEO_FONT_WIDTH +# define LCD_INFO_Y VIDEO_FONT_HEIGHT #endif /* Default to 8bpp if bit depth not specified */ @@ -433,33 +412,5 @@ int lcd_get_size(int *line_length); #endif /************************************************************************/ -/* ** CONSOLE DEFINITIONS & FUNCTIONS */ -/************************************************************************/ -#if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) -# define CONSOLE_ROWS ((panel_info.vl_row-BMP_LOGO_HEIGHT) \ - / VIDEO_FONT_HEIGHT) -#else -# define CONSOLE_ROWS (panel_info.vl_row / VIDEO_FONT_HEIGHT) -#endif - -#define CONSOLE_COLS (panel_info.vl_col / VIDEO_FONT_WIDTH) -#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * lcd_line_length) -#define CONSOLE_ROW_FIRST (lcd_console_address) -#define CONSOLE_ROW_SECOND (lcd_console_address + CONSOLE_ROW_SIZE) -#define CONSOLE_ROW_LAST (lcd_console_address + CONSOLE_SIZE \ - - CONSOLE_ROW_SIZE) -#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS) -#define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE) - -#if LCD_BPP == LCD_MONOCHROME -# define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \ - (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) -#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) -# define COLOR_MASK(c) (c) -#else -# error Unsupported LCD BPP. -#endif - -/************************************************************************/ #endif /* _LCD_H_ */ diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index e9e9045..98bf255 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -180,7 +180,7 @@ typedef enum { */ #define BBT_AUTO_REFRESH 0x00000080 /* - * Chip does not require ready check on read. True + * Chip does not require ready check on read. true * for all large page devices, as they do not support * autoincrement. */ diff --git a/include/linux/types.h b/include/linux/types.h index 1b0b4a4..f07ba41 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -7,6 +7,7 @@ #include <linux/posix_types.h> #include <asm/types.h> +#include <stdbool.h> #ifndef __KERNEL_STRICT_NAMES diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index eba865e..220d068 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -421,11 +421,11 @@ struct device { * driver setup() requests * @ep_list: List of other endpoints supported by the device. * @speed: Speed of current connection to USB host. - * @is_dualspeed: True if the controller supports both high and full speed + * @is_dualspeed: true if the controller supports both high and full speed * operation. If it does, the gadget driver must also support both. - * @is_otg: True if the USB device port uses a Mini-AB jack, so that the + * @is_otg: true if the USB device port uses a Mini-AB jack, so that the * gadget driver must provide a USB OTG descriptor. - * @is_a_peripheral: False unless is_otg, the "A" end of a USB cable + * @is_a_peripheral: false unless is_otg, the "A" end of a USB cable * is in the Mini-AB jack, and HNP has been used to switch roles * so that the "A" device currently acts as A-Peripheral, not A-Host. * @a_hnp_support: OTG device feature flag, indicating that the A-Host diff --git a/include/malloc.h b/include/malloc.h index 6295929..c33f3b4 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -196,7 +196,7 @@ MORECORE_FAILURE (default: -1) The value returned upon failure of MORECORE. MORECORE_CLEARS (default 1) - True (1) if the routine mapped to MORECORE zeroes out memory (which + true (1) if the routine mapped to MORECORE zeroes out memory (which holds for sbrk). DEFAULT_TRIM_THRESHOLD DEFAULT_TOP_PAD diff --git a/include/menu.h b/include/menu.h index 7af5fdb..d8200ee 100644 --- a/include/menu.h +++ b/include/menu.h @@ -21,12 +21,15 @@ struct menu; struct menu *menu_create(char *title, int timeout, int prompt, - void (*item_data_print)(void *)); + void (*item_data_print)(void *), + char *(*item_choice)(void *), + void *item_choice_data); int menu_default_set(struct menu *m, char *item_key); int menu_get_choice(struct menu *m, void **choice); int menu_item_add(struct menu *m, char *item_key, void *item_data); int menu_destroy(struct menu *m); void menu_display_statusline(struct menu *m); +int menu_default_choice(struct menu *m, void **choice); #if defined(CONFIG_MENU_SHOW) int menu_show(int bootdelay); diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h index 966b5e0..9bd76eb 100644 --- a/include/mtd/cfi_flash.h +++ b/include/mtd/cfi_flash.h @@ -78,29 +78,30 @@ #define FLASH_CONTINUATION_CODE 0x7F #define FLASH_OFFSET_MANUFACTURER_ID 0x00 -#define FLASH_OFFSET_DEVICE_ID 0x01 -#define FLASH_OFFSET_DEVICE_ID2 0x0E -#define FLASH_OFFSET_DEVICE_ID3 0x0F -#define FLASH_OFFSET_CFI 0x55 +#define FLASH_OFFSET_DEVICE_ID 0x02 +#define FLASH_OFFSET_DEVICE_ID2 0x1C +#define FLASH_OFFSET_DEVICE_ID3 0x1E +#define FLASH_OFFSET_CFI 0xAA + #define FLASH_OFFSET_CFI_ALT 0x555 -#define FLASH_OFFSET_CFI_RESP 0x10 -#define FLASH_OFFSET_PRIMARY_VENDOR 0x13 +#define FLASH_OFFSET_CFI_RESP 0x20 +#define FLASH_OFFSET_PRIMARY_VENDOR 0x26 /* extended query table primary address */ -#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 +#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x2A #define FLASH_OFFSET_WTOUT 0x1F -#define FLASH_OFFSET_WBTOUT 0x20 -#define FLASH_OFFSET_ETOUT 0x21 -#define FLASH_OFFSET_CETOUT 0x22 -#define FLASH_OFFSET_WMAX_TOUT 0x23 -#define FLASH_OFFSET_WBMAX_TOUT 0x24 -#define FLASH_OFFSET_EMAX_TOUT 0x25 -#define FLASH_OFFSET_CEMAX_TOUT 0x26 -#define FLASH_OFFSET_SIZE 0x27 -#define FLASH_OFFSET_INTERFACE 0x28 -#define FLASH_OFFSET_BUFFER_SIZE 0x2A -#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C -#define FLASH_OFFSET_ERASE_REGIONS 0x2D -#define FLASH_OFFSET_PROTECT 0x02 +#define FLASH_OFFSET_WBTOUT 0x40 +#define FLASH_OFFSET_ETOUT 0x4A +#define FLASH_OFFSET_CETOUT 0x44 +#define FLASH_OFFSET_WMAX_TOUT 0x46 +#define FLASH_OFFSET_WBMAX_TOUT 0x48 +#define FLASH_OFFSET_EMAX_TOUT 0x4A +#define FLASH_OFFSET_CEMAX_TOUT 0x4C +#define FLASH_OFFSET_SIZE 0x4E +#define FLASH_OFFSET_INTERFACE 0x50 +#define FLASH_OFFSET_BUFFER_SIZE 0x54 +#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x58 +#define FLASH_OFFSET_ERASE_REGIONS 0x5A +#define FLASH_OFFSET_PROTECT 0x04 #define FLASH_OFFSET_USER_PROTECTION 0x85 #define FLASH_OFFSET_INTEL_PROTECTION 0x81 diff --git a/include/nand.h b/include/nand.h index dded4e2..f0f3bf9 100644 --- a/include/nand.h +++ b/include/nand.h @@ -129,7 +129,7 @@ struct nand_erase_options { typedef struct nand_erase_options nand_erase_options_t; int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, - u_char *buffer); + size_t *actual, loff_t lim, u_char *buffer); #define WITH_YAFFS_OOB (1 << 0) /* whether write with yaffs format. This flag * is a 'mode' meaning it cannot be mixed with @@ -137,7 +137,7 @@ int nand_read_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, #define WITH_DROP_FFS (1 << 1) /* drop trailing all-0xff pages */ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, - u_char *buffer, int flags); + size_t *actual, loff_t lim, u_char *buffer, int flags); int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts); int nand_torture(nand_info_t *nand, loff_t offset); diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h index f321d8a..fd01040 100644 --- a/include/onenand_uboot.h +++ b/include/onenand_uboot.h @@ -48,10 +48,6 @@ extern int flexonenand_region(struct mtd_info *mtd, loff_t addr); extern int flexonenand_set_boundary(struct mtd_info *mtd, int die, int boundary, int lock); -/* S3C64xx */ -extern void s3c64xx_onenand_init(struct mtd_info *); -extern void s3c64xx_set_width_regs(struct onenand_chip *); - /* SPL */ void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst); diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h index d949ace..fdc7ca9 100644 --- a/include/power/max77686_pmic.h +++ b/include/power/max77686_pmic.h @@ -155,4 +155,36 @@ enum { EN_LDO = (0x3 << 6), }; +/* Buck1 1 volt value */ +#define MAX77686_BUCK1OUT_1V 0x5 +#define MAX77686_BUCK1CTRL_EN (3 << 0) +/* Buck2 1.3 volt value */ +#define MAX77686_BUCK2DVS1_1_3V 0x38 +#define MAX77686_BUCK2CTRL_ON (1 << 4) +/* Buck3 1.0125 volt value */ +#define MAX77686_BUCK3DVS1_1_0125V 0x21 +#define MAX77686_BUCK3CTRL_ON (1 << 4) +/* Buck4 1.2 volt value */ +#define MAX77686_BUCK4DVS1_1_2V 0x30 +#define MAX77686_BUCK4CTRL_ON (1 << 4) +/* LDO2 1.5 volt value */ +#define MAX77686_LD02CTRL1_1_5V 0x1c +/* LDO3 1.8 volt value */ +#define MAX77686_LD03CTRL1_1_8V 0x14 +/* LDO5 1.8 volt value */ +#define MAX77686_LD05CTRL1_1_8V 0x14 +/* LDO10 1.8 volt value */ +#define MAX77686_LD10CTRL1_1_8V 0x14 +/* + * MAX77686_REG_PMIC_32KHZ set to 32KH CP + * output is activated + */ +#define MAX77686_32KHCP_EN (1 << 1) +/* + * MAX77686_REG_PMIC_BBAT set to + * Back up batery charger on and + * limit voltage setting to 3.5v + */ +#define MAX77686_BBCHOSTEN (1 << 0) +#define MAX77686_BBCVS_3_5V (3 << 3) #endif /* __MAX77686_PMIC_H_ */ diff --git a/include/scsi.h b/include/scsi.h index 9da764b..c764e15 100644 --- a/include/scsi.h +++ b/include/scsi.h @@ -204,12 +204,4 @@ int scsi_get_disk_count(void); #define SCSI_INT_STATE 0x00010000 /* unknown Interrupt number is stored in 16 LSB */ - -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - #endif /* _SCSI_H */ diff --git a/include/sound.h b/include/sound.h index d73839d..94922f6 100644 --- a/include/sound.h +++ b/include/sound.h @@ -28,6 +28,7 @@ enum en_sound_codec { CODEC_WM_8994, CODEC_WM_8995, + CODEC_MAX_98095, CODEC_MAX }; diff --git a/include/spi.h b/include/spi.h index 60e85db..3fe2e1e 100644 --- a/include/spi.h +++ b/include/spi.h @@ -49,10 +49,13 @@ * * bus: ID of the bus that the slave is attached to. * cs: ID of the chip select connected to the slave. + * max_write_size: If non-zero, the maximum number of bytes which can + * be written at once, excluding command bytes. */ struct spi_slave { unsigned int bus; unsigned int cs; + unsigned int max_write_size; }; /*----------------------------------------------------------------------- @@ -62,6 +65,47 @@ struct spi_slave { */ void spi_init(void); +/** + * spi_do_alloc_slave - Allocate a new SPI slave (internal) + * + * Allocate and zero all fields in the spi slave, and set the bus/chip + * select. Use the helper macro spi_alloc_slave() to call this. + * + * @offset: Offset of struct spi_slave within slave structure + * @size: Size of slave structure + * @bus: Bus ID of the slave chip. + * @cs: Chip select ID of the slave chip on the specified bus. + */ +void *spi_do_alloc_slave(int offset, int size, unsigned int bus, + unsigned int cs); + +/** + * spi_alloc_slave - Allocate a new SPI slave + * + * Allocate and zero all fields in the spi slave, and set the bus/chip + * select. + * + * @_struct: Name of structure to allocate (e.g. struct tegra_spi). This + * structure must contain a member 'struct spi_slave *slave'. + * @bus: Bus ID of the slave chip. + * @cs: Chip select ID of the slave chip on the specified bus. + */ +#define spi_alloc_slave(_struct, bus, cs) \ + spi_do_alloc_slave(offsetof(_struct, slave), \ + sizeof(_struct), bus, cs) + +/** + * spi_alloc_slave_base - Allocate a new SPI slave with no private data + * + * Allocate and zero all fields in the spi slave, and set the bus/chip + * select. + * + * @bus: Bus ID of the slave chip. + * @cs: Chip select ID of the slave chip on the specified bus. + */ +#define spi_alloc_slave_base(bus, cs) \ + spi_do_alloc_slave(0, sizeof(struct spi_slave), bus, cs) + /*----------------------------------------------------------------------- * Set up communications parameters for a SPI slave. * diff --git a/include/spi_flash.h b/include/spi_flash.h index 9da9062..3b6a44e 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -39,6 +39,7 @@ struct spi_flash { /* Erase (sector) size */ u32 sector_size; + void *memory_map; /* Address of read-only SPI flash access */ int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf); int (*write)(struct spi_flash *flash, u32 offset, @@ -47,6 +48,44 @@ struct spi_flash { size_t len); }; +/** + * spi_flash_do_alloc - Allocate a new spi flash structure + * + * The structure is allocated and cleared with default values for + * read, write and erase, which the caller can modify. The caller must set + * up size, page_size and sector_size. + * + * Use the helper macro spi_flash_alloc() to call this. + * + * @offset: Offset of struct spi_slave within slave structure + * @size: Size of slave structure + * @spi: SPI slave + * @name: Name of SPI flash device + */ +void *spi_flash_do_alloc(int offset, int size, struct spi_slave *spi, + const char *name); + +/** + * spi_flash_alloc - Allocate a new SPI flash structure + * + * @_struct: Name of structure to allocate (e.g. struct ramtron_spi_fram). This + * structure must contain a member 'struct spi_flash *flash'. + * @spi: SPI slave + * @name: Name of SPI flash device + */ +#define spi_flash_alloc(_struct, spi, name) \ + spi_flash_do_alloc(offsetof(_struct, flash), sizeof(_struct), \ + spi, name) + +/** + * spi_flash_alloc_base - Allocate a new SPI flash structure with no private data + * + * @spi: SPI slave + * @name: Name of SPI flash device + */ +#define spi_flash_alloc_base(spi, name) \ + spi_flash_do_alloc(0, sizeof(struct spi_flash), spi, name) + struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, unsigned int max_hz, unsigned int spi_mode); void spi_flash_free(struct spi_flash *flash); diff --git a/include/sym53c8xx.h b/include/sym53c8xx.h index 7d3ded5..9696db0 100644 --- a/include/sym53c8xx.h +++ b/include/sym53c8xx.h @@ -568,11 +568,4 @@ #define SCSI_IDENTIFY 0xC0 -#ifndef TRUE -#define TRUE 1 -#endif -#ifndef FALSE -#define FALSE 0 -#endif - #endif diff --git a/include/tmu.h b/include/tmu.h new file mode 100644 index 0000000..da07a22 --- /dev/null +++ b/include/tmu.h @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Akshay Saraswat <akshay.s@samsung.com> + * + * Thermal Management Unit + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TMU_H +#define _TMU_H + +enum tmu_status_t { + TMU_STATUS_INIT = -1, + TMU_STATUS_NORMAL = 0, + TMU_STATUS_WARNING, + TMU_STATUS_TRIPPED, +}; + +/* + * Monitors status of the TMU device and exynos temperature + * + * @param temp pointer to the current temperature value + * @return enum tmu_status_t value, code indicating event to execute + * and -1 on error + */ +enum tmu_status_t tmu_monitor(int *temp); + +/* + * Initialize TMU device + * + * @param blob FDT blob + * @return int value, 0 for success + */ +int tmu_init(const void *blob); +#endif /* _THERMAL_H_ */ diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index 69006e2..7f72022 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -214,6 +214,9 @@ static inline long IS_ERR(const void *ptr) extern int ubi_mtd_param_parse(const char *val, struct kernel_param *kp); extern int ubi_init(void); extern void ubi_exit(void); +extern int ubi_part(char *part_name, const char *vid_header_offset); +extern int ubi_volume_write(char *volume, void *buf, size_t size); +extern int ubi_volume_read(char *volume, char *buf, size_t size); extern struct ubi_device *ubi_devices[]; diff --git a/include/usb_mass_storage.h b/include/usb_mass_storage.h new file mode 100644 index 0000000..ffc3a13 --- /dev/null +++ b/include/usb_mass_storage.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2011 Samsung Electrnoics + * Lukasz Majewski <l.majewski@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * aloong with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __USB_MASS_STORAGE_H__ +#define __USB_MASS_STORAGE_H__ + +#define SECTOR_SIZE 0x200 + +#include <mmc.h> + +struct ums_device { + struct mmc *mmc; + int dev_num; + int offset; + int part_size; +}; + +struct ums_board_info { + int (*read_sector)(struct ums_device *ums_dev, + ulong start, lbaint_t blkcnt, void *buf); + int (*write_sector)(struct ums_device *ums_dev, + ulong start, lbaint_t blkcnt, const void *buf); + void (*get_capacity)(struct ums_device *ums_dev, + long long int *capacity); + const char *name; + struct ums_device ums_dev; +}; + +extern void board_usb_init(void); + +extern int fsg_init(struct ums_board_info *); +extern void fsg_cleanup(void); +extern struct ums_board_info *board_ums_init(unsigned int, + unsigned int, unsigned int); +extern int usb_gadget_handle_interrupts(void); +extern int fsg_main_thread(void *); + +#endif /* __USB_MASS_STORAGE_H__ */ diff --git a/include/usbdevice.h b/include/usbdevice.h index 3edaf8b..265ba4a 100644 --- a/include/usbdevice.h +++ b/include/usbdevice.h @@ -475,7 +475,9 @@ typedef struct urb_link { * function driver to inform it that data has arrived. */ -#define URB_BUF_SIZE 128 /* in linux we'd malloc this, but in u-boot we prefer static data */ +/* in linux we'd malloc this, but in u-boot we prefer static data */ +#define URB_BUF_SIZE 512 + struct urb { struct usb_endpoint_instance *endpoint; @@ -674,8 +676,8 @@ struct usb_device_descriptor *usbd_device_device_descriptor(struct #if defined(CONFIG_USBD_HS) /* * is_usbd_high_speed routine needs to be defined by specific gadget driver - * It returns TRUE if device enumerates at High speed - * Retuns FALSE otherwise + * It returns true if device enumerates at High speed + * Retuns false otherwise */ int is_usbd_high_speed(void); #endif diff --git a/include/watchdog.h b/include/watchdog.h index 8c92a0b..97ec186 100644 --- a/include/watchdog.h +++ b/include/watchdog.h @@ -27,6 +27,24 @@ #ifndef _WATCHDOG_H_ #define _WATCHDOG_H_ +#if !defined(__ASSEMBLY__) +/* + * Reset the watchdog timer, always returns 0 + * + * This function is here since it is shared between board_f() and board_r(), + * and the legacy arch/<arch>/board.c code. + */ +int init_func_watchdog_reset(void); +#endif + +#ifdef CONFIG_WATCHDOG +#define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init, +#define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset, +#else +#define INIT_FUNC_WATCHDOG_INIT +#define INIT_FUNC_WATCHDOG_RESET +#endif + #if defined(CONFIG_HW_WATCHDOG) && defined(CONFIG_WATCHDOG) # error "Configuration error: CONFIG_HW_WATCHDOG and CONFIG_WATCHDOG can't be used together." #endif diff --git a/include/xyzModem.h b/include/xyzModem.h index f437bbd..a3ea768 100644 --- a/include/xyzModem.h +++ b/include/xyzModem.h @@ -97,14 +97,6 @@ typedef struct { #endif } connection_info_t; -#ifndef BOOL_WAS_DEFINED -#define BOOL_WAS_DEFINED -typedef unsigned int bool; -#endif - -#define false 0 -#define true 1 - #endif diff --git a/lib/Makefile b/lib/Makefile index 86ca1a6..5d71b80 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -27,7 +27,6 @@ LIB = $(obj)libgeneric.o ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_ADDR_MAP) += addr_map.o -COBJS-$(CONFIG_BCH) += bch.o COBJS-$(CONFIG_AES) += aes.o COBJS-$(CONFIG_BZIP2) += bzlib.o COBJS-$(CONFIG_BZIP2) += bzlib_crctable.o @@ -44,6 +43,7 @@ COBJS-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o COBJS-$(CONFIG_GZIP) += gunzip.o COBJS-$(CONFIG_GZIP_COMPRESSED) += gzip.o COBJS-y += hashtable.o +COBJS-y += initcall.o COBJS-$(CONFIG_LMB) += lmb.o COBJS-y += ldiv.o COBJS-$(CONFIG_MD5) += md5.o @@ -66,6 +66,7 @@ COBJS-$(CONFIG_SPL_NET_SUPPORT) += errno.o COBJS-$(CONFIG_SPL_NET_SUPPORT) += hashtable.o COBJS-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o endif +COBJS-$(CONFIG_BCH) += bch.o COBJS-y += crc32.o COBJS-y += ctype.o COBJS-y += div64.o diff --git a/lib/display_options.c b/lib/display_options.c index 0339970..e6d684b 100644 --- a/lib/display_options.c +++ b/lib/display_options.c @@ -115,14 +115,15 @@ int print_buffer(ulong addr, const void *data, uint width, uint count, linelen = DEFAULT_LINE_LENGTH_BYTES / width; while (count) { + uint thislinelen = linelen; printf("%08lx:", addr); /* check for overflow condition */ - if (count < linelen) - linelen = count; + if (count < thislinelen) + thislinelen = count; /* Copy from memory into linebuf and print hex values */ - for (i = 0; i < linelen; i++) { + for (i = 0; i < thislinelen; i++) { uint32_t x; if (width == 4) x = lb.ui[i] = *(volatile uint32_t *)data; @@ -134,8 +135,15 @@ int print_buffer(ulong addr, const void *data, uint width, uint count, data += width; } + while (thislinelen < linelen) { + /* fill line with whitespace for nice ASCII print */ + for (i=0; i<width*2+1; i++) + puts(" "); + linelen--; + } + /* Print data in ASCII characters */ - for (i = 0; i < linelen * width; i++) { + for (i = 0; i < thislinelen * width; i++) { if (!isprint(lb.uc[i]) || lb.uc[i] >= 0x80) lb.uc[i] = '.'; } @@ -143,8 +151,8 @@ int print_buffer(ulong addr, const void *data, uint width, uint count, printf(" %s\n", lb.uc); /* update references */ - addr += linelen * width; - count -= linelen; + addr += thislinelen * width; + count -= thislinelen; if (ctrlc()) return -1; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 43f29f5..403babd 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -50,6 +50,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"), COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"), COMPAT(NVIDIA_TEGRA20_SLINK, "nvidia,tegra20-slink"), + COMPAT(NVIDIA_TEGRA114_SPI, "nvidia,tegra114-spi"), COMPAT(SMSC_LAN9215, "smsc,lan9215"), COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"), COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"), @@ -58,7 +59,12 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(SAMSUNG_EXYNOS_SPI, "samsung,exynos-spi"), COMPAT(SAMSUNG_EXYNOS_EHCI, "samsung,exynos-ehci"), COMPAT(SAMSUNG_EXYNOS_USB_PHY, "samsung,exynos-usb-phy"), + COMPAT(SAMSUNG_EXYNOS_TMU, "samsung,exynos-tmu"), + COMPAT(SAMSUNG_EXYNOS_FIMD, "samsung,exynos-fimd"), + COMPAT(SAMSUNG_EXYNOS5_DP, "samsung,exynos5-dp"), COMPAT(MAXIM_MAX77686_PMIC, "maxim,max77686_pmic"), + COMPAT(GENERIC_SPI_FLASH, "spi-flash"), + COMPAT(MAXIM_98095_CODEC, "maxim,max98095-codec"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) @@ -68,25 +74,40 @@ const char *fdtdec_get_compatible(enum fdt_compat_id id) return compat_names[id]; } -fdt_addr_t fdtdec_get_addr(const void *blob, int node, - const char *prop_name) +fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, + const char *prop_name, fdt_size_t *sizep) { const fdt_addr_t *cell; int len; debug("%s: %s: ", __func__, prop_name); cell = fdt_getprop(blob, node, prop_name, &len); - if (cell && (len == sizeof(fdt_addr_t) || - len == sizeof(fdt_addr_t) * 2)) { + if (cell && ((!sizep && len == sizeof(fdt_addr_t)) || + len == sizeof(fdt_addr_t) * 2)) { fdt_addr_t addr = fdt_addr_to_cpu(*cell); - - debug("%p\n", (void *)addr); + if (sizep) { + const fdt_size_t *size; + + size = (fdt_size_t *)((char *)cell + + sizeof(fdt_addr_t)); + *sizep = fdt_size_to_cpu(*size); + debug("addr=%p, size=%p\n", (void *)addr, + (void *)*sizep); + } else { + debug("%p\n", (void *)addr); + } return addr; } debug("(not found)\n"); return FDT_ADDR_T_NONE; } +fdt_addr_t fdtdec_get_addr(const void *blob, int node, + const char *prop_name) +{ + return fdtdec_get_addr_size(blob, node, prop_name, NULL); +} + s32 fdtdec_get_int(const void *blob, int node, const char *prop_name, s32 default_val) { diff --git a/drivers/usb/host/s3c64xx-hcd.c b/lib/initcall.c index cd295da..fc91bf6 100644 --- a/drivers/usb/host/s3c64xx-hcd.c +++ b/lib/initcall.c @@ -1,8 +1,5 @@ /* - * URB OHCI HCD (Host Controller Driver) initialization for USB on the S3C64XX. - * - * Copyright (C) 2008, - * Guennadi Liakhovetski, DENX Software Engineering <lg@denx.de> + * Copyright (c) 2013 The Chromium OS Authors. * * See file CREDITS for list of people who contributed to this * project. @@ -21,25 +18,22 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA - * */ #include <common.h> -#include <asm/arch/s3c6400.h> +#include <initcall.h> -int usb_cpu_init(void) +int initcall_run_list(init_fnc_t init_sequence[]) { - OTHERS_REG |= 0x10000; - return 0; -} + init_fnc_t *init_fnc_ptr; -int usb_cpu_stop(void) -{ - OTHERS_REG &= ~0x10000; + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + debug("initcall: %p\n", *init_fnc_ptr); + if ((*init_fnc_ptr)()) { + debug("initcall sequence %p failed at call %p\n", + init_sequence, *init_fnc_ptr); + return -1; + } + } return 0; } - -void usb_cpu_init_fail(void) -{ - OTHERS_REG &= ~0x10000; -} @@ -29,15 +29,6 @@ if [ \( $# -eq 2 \) -a \( "$1" = "-A" \) ] ; then set ${line} # add default board name if needed [ $# = 3 ] && set ${line} ${1} -elif [ "${MAKEFLAGS+set}${MAKELEVEL+set}" = "setset" ] ; then - # only warn when using a config target in the Makefile - cat <<-EOF - - warning: Please migrate to boards.cfg. Failure to do so will - mean removal of your board in the next release. - - EOF - sleep 5 fi while [ $# -gt 0 ] ; do diff --git a/nand_spl/board/amcc/acadia/u-boot.lds b/nand_spl/board/amcc/acadia/u-boot.lds index 44a6f81..5e14b0c 100644 --- a/nand_spl/board/amcc/acadia/u-boot.lds +++ b/nand_spl/board/amcc/acadia/u-boot.lds @@ -60,5 +60,5 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; } diff --git a/nand_spl/board/amcc/bamboo/u-boot.lds b/nand_spl/board/amcc/bamboo/u-boot.lds index d4ea67a..d8edffe 100644 --- a/nand_spl/board/amcc/bamboo/u-boot.lds +++ b/nand_spl/board/amcc/bamboo/u-boot.lds @@ -62,5 +62,5 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; } diff --git a/nand_spl/board/amcc/canyonlands/u-boot.lds b/nand_spl/board/amcc/canyonlands/u-boot.lds index 794f041..70001bf 100644 --- a/nand_spl/board/amcc/canyonlands/u-boot.lds +++ b/nand_spl/board/amcc/canyonlands/u-boot.lds @@ -62,5 +62,5 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; } diff --git a/nand_spl/board/amcc/kilauea/u-boot.lds b/nand_spl/board/amcc/kilauea/u-boot.lds index 4e860ad..0d7e6de 100644 --- a/nand_spl/board/amcc/kilauea/u-boot.lds +++ b/nand_spl/board/amcc/kilauea/u-boot.lds @@ -60,5 +60,5 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; } diff --git a/nand_spl/board/amcc/sequoia/u-boot.lds b/nand_spl/board/amcc/sequoia/u-boot.lds index 8ff6ac5..d28fe61 100644 --- a/nand_spl/board/amcc/sequoia/u-boot.lds +++ b/nand_spl/board/amcc/sequoia/u-boot.lds @@ -62,5 +62,5 @@ SECTIONS . = ALIGN(4); } - __bss_end__ = . ; + __bss_end = . ; } diff --git a/nand_spl/board/freescale/mpc8315erdb/u-boot.lds b/nand_spl/board/freescale/mpc8315erdb/u-boot.lds index d140453..870b47d 100644 --- a/nand_spl/board/freescale/mpc8315erdb/u-boot.lds +++ b/nand_spl/board/freescale/mpc8315erdb/u-boot.lds @@ -49,7 +49,7 @@ SECTIONS .bss (NOLOAD) : { *(.*bss) } - __bss_end__ = .; + __bss_end = .; } ENTRY(_start) -ASSERT(__bss_end__ <= 0xfff01000, "NAND bootstrap too big"); +ASSERT(__bss_end <= 0xfff01000, "NAND bootstrap too big"); diff --git a/nand_spl/board/freescale/mx31pdk/Makefile b/nand_spl/board/freescale/mx31pdk/Makefile deleted file mode 100644 index 3d57059..0000000 --- a/nand_spl/board/freescale/mx31pdk/Makefile +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_NAND_SPL = y -PAD_TO := 2048 - -include $(TOPDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL - -SOBJS = start.o crt0.o lowlevel_init.o -COBJS = nand_boot_fsl_nfc.o - -SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c -SRCS += $(SRCTREE)/arch/arm/cpu/arm1136/start.S -SRCS += $(SRCTREE)/arch/arm/lib/crt0.S -SRCS += $(SRCTREE)/board/freescale/mx31pdk/lowlevel_init.S -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $@ - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ - -ansi -D__ASSEMBLY__ -P - <$< >$@ - -######################################################################### - -$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm1136/%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/arch/arm/lib/%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/board/freescale/mx31pdk/%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/nand_spl/%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/freescale/mx31pdk/u-boot.lds b/nand_spl/board/freescale/mx31pdk/u-boot.lds deleted file mode 100644 index 0656176..0000000 --- a/nand_spl/board/freescale/mx31pdk/u-boot.lds +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2009 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - start.o (.text) - lowlevel_init.o (.text) - nand_boot_fsl_nfc.o (.text) - *(.text) - . = 2K; - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = ALIGN(4); - .u_boot_list : { - *(SORT(.u_boot_list*)); - } - - . = ALIGN(4); - - __image_copy_end = .; - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.bss*) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/nand_spl/board/karo/tx25/Makefile b/nand_spl/board/karo/tx25/Makefile deleted file mode 100644 index 9f9c589..0000000 --- a/nand_spl/board/karo/tx25/Makefile +++ /dev/null @@ -1,84 +0,0 @@ -# -# (C) Copyright 2009 DENX Software Engineering -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundatio; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -CONFIG_NAND_SPL = y - -include $(TOPDIR)/config.mk -include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL - -SOBJS = start.o crt0.o lowlevel_init.o -COBJS = nand_boot_fsl_nfc.o - -SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c -SRCS += $(SRCTREE)/arch/arm/cpu/arm926ejs/start.S -SRCS += $(SRCTREE)/arch/arm/lib/crt0.S -SRCS += $(SRCTREE)/board/karo/tx25/lowlevel_init.S -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $@ - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ - -ansi -D__ASSEMBLY__ -P - <$< >$@ - -######################################################################### - -$(obj)%.o: $(SRCTREE)/arch/arm/cpu/arm926ejs/%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/arch/arm/lib/%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/board/karo/tx25/%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(SRCTREE)/nand_spl/%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/karo/tx25/config.mk b/nand_spl/board/karo/tx25/config.mk deleted file mode 100644 index 68afbf1..0000000 --- a/nand_spl/board/karo/tx25/config.mk +++ /dev/null @@ -1 +0,0 @@ -PAD_TO := 2048 diff --git a/nand_spl/board/karo/tx25/u-boot.lds b/nand_spl/board/karo/tx25/u-boot.lds deleted file mode 100644 index ea84d64..0000000 --- a/nand_spl/board/karo/tx25/u-boot.lds +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2009 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - start.o (.text) - lowlevel_init.o (.text) - nand_boot_fsl_nfc.o (.text) - *(.text) - . = 2K; - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { - *(.data) - } - - . = ALIGN(4); - - . = ALIGN(4); - .u_boot_list : { - *(SORT(.u_boot_list*)); - } - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } - - /DISCARD/ : { *(.bss*) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } -} diff --git a/nand_spl/board/samsung/smdk6400/Makefile b/nand_spl/board/samsung/smdk6400/Makefile deleted file mode 100644 index c9e75ba..0000000 --- a/nand_spl/board/samsung/smdk6400/Makefile +++ /dev/null @@ -1,117 +0,0 @@ -# -# (C) Copyright 2006-2007 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# (C) Copyright 2008 -# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -CONFIG_NAND_SPL = y - -include $(TOPDIR)/config.mk -include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk - -nandobj := $(OBJTREE)/nand_spl/ - -LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds -LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ - $(LDFLAGS_FINAL) -gc-sections -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL -ffunction-sections - -SOBJS = start.o cpu_init.o lowlevel_init.o -COBJS = nand_boot.o nand_ecc.o s3c64xx.o smdk6400_nand_spl.o nand_base.o - -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) -__OBJS := $(SOBJS) $(COBJS) -LNDIR := $(nandobj)board/$(BOARDDIR) - -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin - -all: $(obj).depend $(ALL) - -$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ - -$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl - $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ - -$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds - cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ - -Map $(nandobj)u-boot-spl.map \ - -o $(nandobj)u-boot-spl - -$(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ - -# create symbolic links for common files - -# from cpu directory -$(obj)start.S: - @rm -f $@ - @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/start.S $@ - -# from SoC directory -$(obj)cpu_init.S: - @rm -f $@ - @ln -s $(TOPDIR)/arch/arm/cpu/arm1176/s3c64xx/cpu_init.S $@ - -# from board directory -$(obj)lowlevel_init.S: - @rm -f $@ - @ln -s $(TOPDIR)/board/samsung/smdk6400/lowlevel_init.S $@ - -# from nand_spl directory -$(obj)nand_boot.c: - @rm -f $@ - @ln -s $(TOPDIR)/nand_spl/nand_boot.c $@ - -# from drivers/mtd/nand directory -$(obj)nand_ecc.c: - @rm -f $@ - @ln -s $(TOPDIR)/drivers/mtd/nand/nand_ecc.c $@ - -$(obj)s3c64xx.c: - @rm -f $@ - @ln -s $(TOPDIR)/drivers/mtd/nand/s3c64xx.c $@ - -$(obj)smdk6400_nand_spl.c: - @rm -f $@ - @ln -s $(TOPDIR)/board/samsung/smdk6400/smdk6400_nand_spl.c $@ - -$(obj)nand_base.c: - @rm -f $@ - @ln -s $(TOPDIR)/drivers/mtd/nand/nand_base.c $@ -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/nand_spl/board/samsung/smdk6400/config.mk b/nand_spl/board/samsung/smdk6400/config.mk deleted file mode 100644 index 8bea498..0000000 --- a/nand_spl/board/samsung/smdk6400/config.mk +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2006 -# Stefan Roese, DENX Software Engineering, sr@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# -# Samsung S3C64xx Reference Platform (smdk6400) board - -# CONFIG_SYS_TEXT_BASE for SPL: -# -# On S3C64xx platforms the SPL is located in SRAM at 0. -# -# CONFIG_SYS_TEXT_BASE = 0 - -include $(TOPDIR)/board/$(BOARDDIR)/config.mk - -# PAD_TO used to generate a 4kByte binary needed for the combined image -# -> PAD_TO = CONFIG_SYS_TEXT_BASE + 4096 -PAD_TO := $(shell expr $$[$(CONFIG_SYS_TEXT_BASE) + 4096]) - -ifeq ($(debug),1) -PLATFORM_CPPFLAGS += -DDEBUG -endif diff --git a/nand_spl/board/samsung/smdk6400/u-boot.lds b/nand_spl/board/samsung/smdk6400/u-boot.lds deleted file mode 100644 index 66b412e..0000000 --- a/nand_spl/board/samsung/smdk6400/u-boot.lds +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - start.o (.text) - cpu_init.o (.text) - nand_boot.o (.text) - - *(.text) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - - . = ALIGN(4); - .u_boot_list : { - *(SORT(.u_boot_list*)); - } - - . = ALIGN(4); - - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - _end = .; - - .bss __rel_dyn_start (OVERLAY) : { - __bss_start = .; - *(.bss) - . = ALIGN(4); - __bss_end__ = .; - } -} diff --git a/nand_spl/board/sheldon/simpc8313/u-boot.lds b/nand_spl/board/sheldon/simpc8313/u-boot.lds index 534a0c8..7ab408b 100644 --- a/nand_spl/board/sheldon/simpc8313/u-boot.lds +++ b/nand_spl/board/sheldon/simpc8313/u-boot.lds @@ -48,7 +48,7 @@ SECTIONS . = ALIGN(8); __bss_start = .; .bss (NOLOAD) : { *(.*bss) } - __bss_end__ = .; + __bss_end = .; } ENTRY(_start) -ASSERT(__bss_end__ <= 0xfff01000, "NAND bootstrap too big"); +ASSERT(__bss_end <= 0xfff01000, "NAND bootstrap too big"); diff --git a/spl/Makefile b/spl/Makefile index 14095c8..b5a8de7 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -84,7 +84,7 @@ LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TI814X),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif diff --git a/tools/buildman/.gitignore b/tools/buildman/.gitignore new file mode 100644 index 0000000..0d20b64 --- /dev/null +++ b/tools/buildman/.gitignore @@ -0,0 +1 @@ +*.pyc diff --git a/tools/buildman/README b/tools/buildman/README new file mode 100644 index 0000000..7221007 --- /dev/null +++ b/tools/buildman/README @@ -0,0 +1,679 @@ +# Copyright (c) 2013 The Chromium OS Authors. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +What is this? +============= + +This tool handles building U-Boot to check that you have not broken it +with your patch series. It can build each individual commit and report +which boards fail on which commits, and which errors come up. It aims +to make full use of multi-processor machines. + +A key feature of buildman is its output summary, which allows warnings, +errors or image size increases in a particular commit or board to be +quickly identified and the offending commit pinpointed. This can be a big +help for anyone working with >10 patches at a time. + + +Caveats +======= + +Buildman is still in its infancy. It is already a very useful tool, but +expect to find problems and send patches. + +Buildman can be stopped and restarted, in which case it will continue +where it left off. This should happen cleanly and without side-effects. +If not, it is a bug, for which a patch would be welcome. + +Buildman gets so tied up in its work that it can ignore the outside world. +You may need to press Ctrl-C several times to quit it. Also it will print +out various exceptions when stopped. + + +Theory of Operation +=================== + +(please read this section in full twice or you will be perpetually confused) + +Buildman is a builder. It is not make, although it runs make. It does not +produce any useful output on the terminal while building, except for +progress information. All the output (errors, warnings and binaries if you +are ask for them) is stored in output directories, which you can look at +while the build is progressing, or when it is finished. + +Buildman produces a concise summary of which boards succeeded and failed. +It shows which commit introduced which board failure using a simple +red/green colour coding. Full error information can be requested, in which +case it is de-duped and displayed against the commit that introduced the +error. An example workflow is below. + +Buildman stores image size information and can report changes in image size +from commit to commit. An example of this is below. + +Buildman starts multiple threads, and each thread builds for one board at +a time. A thread starts at the first commit, configures the source for your +board and builds it. Then it checks out the next commit and does an +incremental build. Eventually the thread reaches the last commit and stops. +If errors or warnings are found along the way, the thread will reconfigure +after every commit, and your build will be very slow. This is because a +file that produces just a warning would not normally be rebuilt in an +incremental build. + +Buildman works in an entirely separate place from your U-Boot repository. +It creates a separate working directory for each thread, and puts the +output files in the working directory, organised by commit name and board +name, in a two-level hierarchy. + +Buildman is invoked in your U-Boot directory, the one with the .git +directory. It clones this repository into a copy for each thread, and the +threads do not affect the state of your git repository. Any checkouts done +by the thread affect only the working directory for that thread. + +Buildman automatically selects the correct toolchain for each board. You +must supply suitable toolchains, but buildman takes care of selecting the +right one. + +Buildman always builds a branch, and always builds the upstream commit as +well, for comparison. It cannot build individual commits at present, unless +(maybe) you point it at an empty branch. Put all your commits in a branch, +set the branch's upstream to a valid value, and all will be well. Otherwise +buildman will perform random actions. Use -n to check what the random +actions might be. + +Buildman is optimised for building many commits at once, for many boards. +On multi-core machines, Buildman is fast because it uses most of the +available CPU power. When it gets to the end, or if you are building just +a few commits or boards, it will be pretty slow. As a tip, if you don't +plan to use your machine for anything else, you can use -T to increase the +number of threads beyond the default. + +Buildman lets you build all boards, or a subset. Specify the subset using +the board name, architecture name, SOC name, or anything else in the +boards.cfg file. So 'at91' will build all AT91 boards (arm), powerpc will +build all PowerPC boards. + +Buildman does not store intermediate object files. It optionally copies +the binary output into a directory when a build is successful. Size +information is always recorded. It needs a fair bit of disk space to work, +typically 250MB per thread. + + +Setting up +========== + +1. Get the U-Boot source. You probably already have it, but if not these +steps should get you started with a repo and some commits for testing. + +$ cd /path/to/u-boot +$ git clone git://git.denx.de/u-boot.git . +$ git checkout -b my-branch origin/master +$ # Add some commits to the branch, reading for testing + +2. Create ~/.buildman to tell buildman where to find tool chains. As an +example: + +# Buildman settings file + +[toolchain] +root: / +rest: /toolchains/* +eldk: /opt/eldk-4.2 + +[toolchain-alias] +x86: i386 +blackfin: bfin +sh: sh4 +nds32: nds32le +openrisc: or32 + + +This selects the available toolchain paths. Add the base directory for +each of your toolchains here. Buildman will search inside these directories +and also in any '/usr' and '/usr/bin' subdirectories. + +Make sure the tags (here root: rest: and eldk:) are unique. + +The toolchain-alias section indicates that the i386 toolchain should be used +to build x86 commits. + + +2. Check the available toolchains + +Run this check to make sure that you have a toolchain for every architecture. + +$ ./tools/buildman/buildman --list-tool-chains +Scanning for tool chains + - scanning path '/' + - looking in '/.' + - looking in '/bin' + - looking in '/usr/bin' + - found '/usr/bin/gcc' +Tool chain test: OK + - found '/usr/bin/c89-gcc' +Tool chain test: OK + - found '/usr/bin/c99-gcc' +Tool chain test: OK + - found '/usr/bin/x86_64-linux-gnu-gcc' +Tool chain test: OK + - scanning path '/toolchains/powerpc-linux' + - looking in '/toolchains/powerpc-linux/.' + - looking in '/toolchains/powerpc-linux/bin' + - found '/toolchains/powerpc-linux/bin/powerpc-linux-gcc' +Tool chain test: OK + - looking in '/toolchains/powerpc-linux/usr/bin' + - scanning path '/toolchains/nds32le-linux-glibc-v1f' + - looking in '/toolchains/nds32le-linux-glibc-v1f/.' + - looking in '/toolchains/nds32le-linux-glibc-v1f/bin' + - found '/toolchains/nds32le-linux-glibc-v1f/bin/nds32le-linux-gcc' +Tool chain test: OK + - looking in '/toolchains/nds32le-linux-glibc-v1f/usr/bin' + - scanning path '/toolchains/nios2' + - looking in '/toolchains/nios2/.' + - looking in '/toolchains/nios2/bin' + - found '/toolchains/nios2/bin/nios2-linux-gcc' +Tool chain test: OK + - found '/toolchains/nios2/bin/nios2-linux-uclibc-gcc' +Tool chain test: OK + - looking in '/toolchains/nios2/usr/bin' + - found '/toolchains/nios2/usr/bin/nios2-linux-gcc' +Tool chain test: OK + - found '/toolchains/nios2/usr/bin/nios2-linux-uclibc-gcc' +Tool chain test: OK + - scanning path '/toolchains/microblaze-unknown-linux-gnu' + - looking in '/toolchains/microblaze-unknown-linux-gnu/.' + - looking in '/toolchains/microblaze-unknown-linux-gnu/bin' + - found '/toolchains/microblaze-unknown-linux-gnu/bin/microblaze-unknown-linux-gnu-gcc' +Tool chain test: OK + - found '/toolchains/microblaze-unknown-linux-gnu/bin/mb-linux-gcc' +Tool chain test: OK + - looking in '/toolchains/microblaze-unknown-linux-gnu/usr/bin' + - scanning path '/toolchains/mips-linux' + - looking in '/toolchains/mips-linux/.' + - looking in '/toolchains/mips-linux/bin' + - found '/toolchains/mips-linux/bin/mips-linux-gcc' +Tool chain test: OK + - looking in '/toolchains/mips-linux/usr/bin' + - scanning path '/toolchains/old' + - looking in '/toolchains/old/.' + - looking in '/toolchains/old/bin' + - looking in '/toolchains/old/usr/bin' + - scanning path '/toolchains/i386-linux' + - looking in '/toolchains/i386-linux/.' + - looking in '/toolchains/i386-linux/bin' + - found '/toolchains/i386-linux/bin/i386-linux-gcc' +Tool chain test: OK + - looking in '/toolchains/i386-linux/usr/bin' + - scanning path '/toolchains/bfin-uclinux' + - looking in '/toolchains/bfin-uclinux/.' + - looking in '/toolchains/bfin-uclinux/bin' + - found '/toolchains/bfin-uclinux/bin/bfin-uclinux-gcc' +Tool chain test: OK + - looking in '/toolchains/bfin-uclinux/usr/bin' + - scanning path '/toolchains/sparc-elf' + - looking in '/toolchains/sparc-elf/.' + - looking in '/toolchains/sparc-elf/bin' + - found '/toolchains/sparc-elf/bin/sparc-elf-gcc' +Tool chain test: OK + - looking in '/toolchains/sparc-elf/usr/bin' + - scanning path '/toolchains/arm-2010q1' + - looking in '/toolchains/arm-2010q1/.' + - looking in '/toolchains/arm-2010q1/bin' + - found '/toolchains/arm-2010q1/bin/arm-none-linux-gnueabi-gcc' +Tool chain test: OK + - looking in '/toolchains/arm-2010q1/usr/bin' + - scanning path '/toolchains/from' + - looking in '/toolchains/from/.' + - looking in '/toolchains/from/bin' + - looking in '/toolchains/from/usr/bin' + - scanning path '/toolchains/sh4-gentoo-linux-gnu' + - looking in '/toolchains/sh4-gentoo-linux-gnu/.' + - looking in '/toolchains/sh4-gentoo-linux-gnu/bin' + - found '/toolchains/sh4-gentoo-linux-gnu/bin/sh4-gentoo-linux-gnu-gcc' +Tool chain test: OK + - looking in '/toolchains/sh4-gentoo-linux-gnu/usr/bin' + - scanning path '/toolchains/avr32-linux' + - looking in '/toolchains/avr32-linux/.' + - looking in '/toolchains/avr32-linux/bin' + - found '/toolchains/avr32-linux/bin/avr32-gcc' +Tool chain test: OK + - looking in '/toolchains/avr32-linux/usr/bin' + - scanning path '/toolchains/m68k-linux' + - looking in '/toolchains/m68k-linux/.' + - looking in '/toolchains/m68k-linux/bin' + - found '/toolchains/m68k-linux/bin/m68k-linux-gcc' +Tool chain test: OK + - looking in '/toolchains/m68k-linux/usr/bin' +List of available toolchains (17): +arm : /toolchains/arm-2010q1/bin/arm-none-linux-gnueabi-gcc +avr32 : /toolchains/avr32-linux/bin/avr32-gcc +bfin : /toolchains/bfin-uclinux/bin/bfin-uclinux-gcc +c89 : /usr/bin/c89-gcc +c99 : /usr/bin/c99-gcc +i386 : /toolchains/i386-linux/bin/i386-linux-gcc +m68k : /toolchains/m68k-linux/bin/m68k-linux-gcc +mb : /toolchains/microblaze-unknown-linux-gnu/bin/mb-linux-gcc +microblaze: /toolchains/microblaze-unknown-linux-gnu/bin/microblaze-unknown-linux-gnu-gcc +mips : /toolchains/mips-linux/bin/mips-linux-gcc +nds32le : /toolchains/nds32le-linux-glibc-v1f/bin/nds32le-linux-gcc +nios2 : /toolchains/nios2/bin/nios2-linux-gcc +powerpc : /toolchains/powerpc-linux/bin/powerpc-linux-gcc +sandbox : /usr/bin/gcc +sh4 : /toolchains/sh4-gentoo-linux-gnu/bin/sh4-gentoo-linux-gnu-gcc +sparc : /toolchains/sparc-elf/bin/sparc-elf-gcc +x86_64 : /usr/bin/x86_64-linux-gnu-gcc + + +You can see that everything is covered, even some strange ones that won't +be used (c88 and c99). This is a feature. + + +How to run it +============= + +First do a dry run using the -n flag: (replace <branch> with a real, local +branch with a valid upstream) + +$ ./tools/buildman/buildman -b <branch> -n + +If it can't detect the upstream branch, try checking out the branch, and +doing something like 'git branch --set-upstream <branch> upstream/master' +or something similar. + +As an exmmple: + +Dry run, so not doing much. But I would do this: + +Building 18 commits for 1059 boards (4 threads, 1 job per thread) +Build directory: ../lcd9b + 5bb3505 Merge branch 'master' of git://git.denx.de/u-boot-arm + c18f1b4 tegra: Use const for pinmux_config_pingroup/table() + 2f043ae tegra: Add display support to funcmux + e349900 tegra: fdt: Add pwm binding and node + 424a5f0 tegra: fdt: Add LCD definitions for Tegra + 0636ccf tegra: Add support for PWM + a994fe7 tegra: Add SOC support for display/lcd + fcd7350 tegra: Add LCD driver + 4d46e9d tegra: Add LCD support to Nvidia boards + 991bd48 arm: Add control over cachability of memory regions + 54e8019 lcd: Add CONFIG_LCD_ALIGNMENT to select frame buffer alignment + d92aff7 lcd: Add support for flushing LCD fb from dcache after update + dbd0677 tegra: Align LCD frame buffer to section boundary + 0cff9b8 tegra: Support control of cache settings for LCD + 9c56900 tegra: fdt: Add LCD definitions for Seaboard + 5cc29db lcd: Add CONFIG_CONSOLE_SCROLL_LINES option to speed console + cac5a23 tegra: Enable display/lcd support on Seaboard + 49ff541 wip + +Total boards to build for each commit: 1059 + +This shows that it will build all 1059 boards, using 4 threads (because +we have a 4-core CPU). Each thread will run with -j1, meaning that each +make job will use a single CPU. The list of commits to be built helps you +confirm that things look about right. Notice that buildman has chosen a +'base' directory for you, immediately above your source tree. + +Buildman works entirely inside the base directory, here ../lcd9b, +creating a working directory for each thread, and creating output +directories for each commit and board. + + +Suggested Workflow +================== + +To run the build for real, take off the -n: + +$ ./tools/buildman/buildman -b <branch> + +Buildman will set up some working directories, and get started. After a +minute or so it will settle down to a steady pace, with a display like this: + +Building 18 commits for 1059 boards (4 threads, 1 job per thread) + 528 36 124 /19062 1:13:30 : SIMPC8313_SP + +This means that it is building 19062 board/commit combinations. So far it +has managed to succesfully build 528. Another 36 have built with warnings, +and 124 more didn't build at all. Buildman expects to complete the process +in an hour and 15 minutes. Use this time to buy a faster computer. + + +To find out how the build went, ask for a summary with -s. You can do this +either before the build completes (presumably in another terminal) or or +afterwards. Let's work through an example of how this is used: + +$ ./tools/buildman/buildman -b lcd9b -s +... +01: Merge branch 'master' of git://git.denx.de/u-boot-arm + powerpc: + galaxy5200_LOWBOOT +02: tegra: Use const for pinmux_config_pingroup/table() +03: tegra: Add display support to funcmux +04: tegra: fdt: Add pwm binding and node +05: tegra: fdt: Add LCD definitions for Tegra +06: tegra: Add support for PWM +07: tegra: Add SOC support for display/lcd +08: tegra: Add LCD driver +09: tegra: Add LCD support to Nvidia boards +10: arm: Add control over cachability of memory regions +11: lcd: Add CONFIG_LCD_ALIGNMENT to select frame buffer alignment +12: lcd: Add support for flushing LCD fb from dcache after update + arm: + lubbock +13: tegra: Align LCD frame buffer to section boundary +14: tegra: Support control of cache settings for LCD +15: tegra: fdt: Add LCD definitions for Seaboard +16: lcd: Add CONFIG_CONSOLE_SCROLL_LINES option to speed console +17: tegra: Enable display/lcd support on Seaboard +18: wip + +This shows which commits have succeeded and which have failed. In this case +the build is still in progress so many boards are not built yet (use -u to +see which ones). But still we can see a few failures. The galaxy5200_LOWBOOT +never builds correctly. This could be a problem with our toolchain, or it +could be a bug in the upstream. The good news is that we probably don't need +to blame our commits. The bad news is it isn't tested on that board. + +Commit 12 broke lubbock. That's what the '+ lubbock' means. The failure +is never fixed by a later commit, or you would see lubbock again, in green, +without the +. + +To see the actual error: + +$ ./tools/buildman/buildman -b <branch> -se lubbock +... +12: lcd: Add support for flushing LCD fb from dcache after update + arm: + lubbock ++common/libcommon.o: In function `lcd_sync': ++/u-boot/lcd9b/.bm-work/00/common/lcd.c:120: undefined reference to `flush_dcache_range' ++arm-none-linux-gnueabi-ld: BFD (Sourcery G++ Lite 2010q1-202) 2.19.51.20090709 assertion fail /scratch/julian/2010q1-release-linux-lite/obj/binutils-src-2010q1-202-arm-none-linux-gnueabi-i686-pc-linux-gnu/bfd/elf32-arm.c:12572 ++make: *** [/u-boot/lcd9b/.bm-work/00/build/u-boot] Error 139 +13: tegra: Align LCD frame buffer to section boundary +14: tegra: Support control of cache settings for LCD +15: tegra: fdt: Add LCD definitions for Seaboard +16: lcd: Add CONFIG_CONSOLE_SCROLL_LINES option to speed console +-/u-boot/lcd9b/.bm-work/00/common/lcd.c:120: undefined reference to `flush_dcache_range' ++/u-boot/lcd9b/.bm-work/00/common/lcd.c:125: undefined reference to `flush_dcache_range' +17: tegra: Enable display/lcd support on Seaboard +18: wip + +So the problem is in lcd.c, due to missing cache operations. This information +should be enough to work out what that commit is doing to break these +boards. (In this case pxa did not have cache operations defined). + +If you see error lines marked with - that means that the errors were fixed +by that commit. Sometimes commits can be in the wrong order, so that a +breakage is introduced for a few commits and fixed by later commits. This +shows up clearly with buildman. You can then reorder the commits and try +again. + +At commit 16, the error moves - you can see that the old error at line 120 +is fixed, but there is a new one at line 126. This is probably only because +we added some code and moved the broken line futher down the file. + +If many boards have the same error, then -e will display the error only +once. This makes the output as concise as possible. + +The full build output in this case is available in: + +../lcd9b/12_of_18_gd92aff7_lcd--Add-support-for/lubbock/ + + done: Indicates the build was done, and holds the return code from make. + This is 0 for a good build, typically 2 for a failure. + + err: Output from stderr, if any. Errors and warnings appear here. + + log: Output from stdout. Normally there isn't any since buildman runs + in silent mode for now. + + toolchain: Shows information about the toolchain used for the build. + + sizes: Shows image size information. + +It is possible to get the build output there also. Use the -k option for +this. In that case you will also see some output files, like: + + System.map toolchain u-boot u-boot.bin u-boot.map autoconf.mk + (also SPL versions u-boot-spl and u-boot-spl.bin if available) + + +Checking Image Sizes +==================== + +A key requirement for U-Boot is that you keep code/data size to a minimum. +Where a new feature increases this noticeably it should normally be put +behind a CONFIG flag so that boards can leave it off and keep the image +size more or less the same with each new release. + +To check the impact of your commits on image size, use -S. For example: + +$ ./tools/buildman/buildman -b us-x86 -sS +Summary of 10 commits for 1066 boards (4 threads, 1 job per thread) +01: MAKEALL: add support for per architecture toolchains +02: x86: Add function to get top of usable ram + x86: (for 1/3 boards) text -272.0 rodata +41.0 +03: x86: Add basic cache operations +04: x86: Permit bootstage and timer data to be used prior to relocation + x86: (for 1/3 boards) data +16.0 +05: x86: Add an __end symbol to signal the end of the U-Boot binary + x86: (for 1/3 boards) text +76.0 +06: x86: Rearrange the output input to remove BSS + x86: (for 1/3 boards) bss -2140.0 +07: x86: Support relocation of FDT on start-up + x86: + coreboot-x86 +08: x86: Add error checking to x86 relocation code +09: x86: Adjust link device tree include file +10: x86: Enable CONFIG_OF_CONTROL on coreboot + + +You can see that image size only changed on x86, which is good because this +series is not supposed to change any other board. From commit 7 onwards the +build fails so we don't get code size numbers. The numbers are fractional +because they are an average of all boards for that architecture. The +intention is to allow you to quickly find image size problems introduced by +your commits. + +Note that the 'text' region and 'rodata' are split out. You should add the +two together to get the total read-only size (reported as the first column +in the output from binutil's 'size' utility). + +A useful option is --step which lets you skip some commits. For example +--step 2 will show the image sizes for only every 2nd commit (so it will +compare the image sizes of the 1st, 3rd, 5th... commits). You can also use +--step 0 which will compare only the first and last commits. This is useful +for an overview of how your entire series affects code size. + +You can also use -d to see a detailed size breakdown for each board. This +list is sorted in order from largest growth to largest reduction. + +It is possible to go a little further with the -B option (--bloat). This +shows where U-Boot has bloted, breaking the size change down to the function +level. Example output is below: + +$ ./tools/buildman/buildman -b us-mem4 -sSdB +... +19: Roll crc32 into hash infrastructure + arm: (for 10/10 boards) all -143.4 bss +1.2 data -4.8 rodata -48.2 text -91.6 + paz00 : all +23 bss -4 rodata -29 text +56 + u-boot: add: 1/0, grow: 3/-2 bytes: 168/-104 (64) + function old new delta + hash_command 80 160 +80 + crc32_wd_buf - 56 +56 + ext4fs_read_file 540 568 +28 + insert_var_value_sub 688 692 +4 + run_list_real 1996 1992 -4 + do_mem_crc 168 68 -100 + trimslice : all -9 bss +16 rodata -29 text +4 + u-boot: add: 1/0, grow: 1/-3 bytes: 136/-124 (12) + function old new delta + hash_command 80 160 +80 + crc32_wd_buf - 56 +56 + ext4fs_iterate_dir 672 668 -4 + ext4fs_read_file 568 548 -20 + do_mem_crc 168 68 -100 + whistler : all -9 bss +16 rodata -29 text +4 + u-boot: add: 1/0, grow: 1/-3 bytes: 136/-124 (12) + function old new delta + hash_command 80 160 +80 + crc32_wd_buf - 56 +56 + ext4fs_iterate_dir 672 668 -4 + ext4fs_read_file 568 548 -20 + do_mem_crc 168 68 -100 + seaboard : all -9 bss -28 rodata -29 text +48 + u-boot: add: 1/0, grow: 3/-2 bytes: 160/-104 (56) + function old new delta + hash_command 80 160 +80 + crc32_wd_buf - 56 +56 + ext4fs_read_file 548 568 +20 + run_list_real 1996 2000 +4 + do_nandboot 760 756 -4 + do_mem_crc 168 68 -100 + colibri_t20_iris: all -9 rodata -29 text +20 + u-boot: add: 1/0, grow: 2/-3 bytes: 140/-112 (28) + function old new delta + hash_command 80 160 +80 + crc32_wd_buf - 56 +56 + read_abs_bbt 204 208 +4 + do_nandboot 760 756 -4 + ext4fs_read_file 576 568 -8 + do_mem_crc 168 68 -100 + ventana : all -37 bss -12 rodata -29 text +4 + u-boot: add: 1/0, grow: 1/-3 bytes: 136/-124 (12) + function old new delta + hash_command 80 160 +80 + crc32_wd_buf - 56 +56 + ext4fs_iterate_dir 672 668 -4 + ext4fs_read_file 568 548 -20 + do_mem_crc 168 68 -100 + harmony : all -37 bss -16 rodata -29 text +8 + u-boot: add: 1/0, grow: 2/-3 bytes: 140/-124 (16) + function old new delta + hash_command 80 160 +80 + crc32_wd_buf - 56 +56 + nand_write_oob_syndrome 428 432 +4 + ext4fs_iterate_dir 672 668 -4 + ext4fs_read_file 568 548 -20 + do_mem_crc 168 68 -100 + medcom-wide : all -417 bss +28 data -16 rodata -93 text -336 + u-boot: add: 1/-1, grow: 1/-2 bytes: 88/-376 (-288) + function old new delta + crc32_wd_buf - 56 +56 + do_fat_read_at 2872 2904 +32 + hash_algo 16 - -16 + do_mem_crc 168 68 -100 + hash_command 420 160 -260 + tec : all -449 bss -4 data -16 rodata -93 text -336 + u-boot: add: 1/-1, grow: 1/-2 bytes: 88/-376 (-288) + function old new delta + crc32_wd_buf - 56 +56 + do_fat_read_at 2872 2904 +32 + hash_algo 16 - -16 + do_mem_crc 168 68 -100 + hash_command 420 160 -260 + plutux : all -481 bss +16 data -16 rodata -93 text -388 + u-boot: add: 1/-1, grow: 1/-3 bytes: 68/-408 (-340) + function old new delta + crc32_wd_buf - 56 +56 + do_load_serial_bin 1688 1700 +12 + hash_algo 16 - -16 + do_fat_read_at 2904 2872 -32 + do_mem_crc 168 68 -100 + hash_command 420 160 -260 + powerpc: (for 5/5 boards) all +37.4 data -3.2 rodata -41.8 text +82.4 + MPC8610HPCD : all +55 rodata -29 text +84 + u-boot: add: 1/0, grow: 0/-1 bytes: 176/-96 (80) + function old new delta + hash_command - 176 +176 + do_mem_crc 184 88 -96 + MPC8641HPCN : all +55 rodata -29 text +84 + u-boot: add: 1/0, grow: 0/-1 bytes: 176/-96 (80) + function old new delta + hash_command - 176 +176 + do_mem_crc 184 88 -96 + MPC8641HPCN_36BIT: all +55 rodata -29 text +84 + u-boot: add: 1/0, grow: 0/-1 bytes: 176/-96 (80) + function old new delta + hash_command - 176 +176 + do_mem_crc 184 88 -96 + sbc8641d : all +55 rodata -29 text +84 + u-boot: add: 1/0, grow: 0/-1 bytes: 176/-96 (80) + function old new delta + hash_command - 176 +176 + do_mem_crc 184 88 -96 + xpedite517x : all -33 data -16 rodata -93 text +76 + u-boot: add: 1/-1, grow: 0/-1 bytes: 176/-112 (64) + function old new delta + hash_command - 176 +176 + hash_algo 16 - -16 + do_mem_crc 184 88 -96 +... + + +This shows that commit 19 has increased text size for arm (although only one +board was built) and by 96 bytes for powerpc. This increase was offset in both +cases by reductions in rodata and data/bss. + +Shown below the summary lines is the sizes for each board. Below each board +is the sizes for each function. This information starts with: + + add - number of functions added / removed + grow - number of functions which grew / shrunk + bytes - number of bytes of code added to / removed from all functions, + plus the total byte change in brackets + +The change seems to be that hash_command() has increased by more than the +do_mem_crc() function has decreased. The function sizes typically add up to +roughly the text area size, but note that every read-only section except +rodata is included in 'text', so the function total does not exactly +correspond. + +It is common when refactoring code for the rodata to decrease as the text size +increases, and vice versa. + + +Other options +============= + +Buildman has various other command line options. Try --help to see them. + + +TODO +==== + +This has mostly be written in my spare time as a response to my difficulties +in testing large series of patches. Apart from tidying up there is quite a +bit of scope for improvement. Things like better error diffs, easier access +to log files, error display while building. Also it would be nice it buildman +could 'hunt' for problems, perhaps by building a few boards for each arch, +or checking commits for changed files and building only boards which use +those files. + + +Credits +======= + +Thanks to Grant Grundler <grundler@chromium.org> for his ideas for improving +the build speed by building all commits for a board instead of the other +way around. + + + +Simon Glass +sjg@chromium.org +Halloween 2012 +Updated 12-12-12 +Updated 23-02-13 diff --git a/tools/buildman/board.py b/tools/buildman/board.py new file mode 100644 index 0000000..9f50aba --- /dev/null +++ b/tools/buildman/board.py @@ -0,0 +1,167 @@ +# Copyright (c) 2012 The Chromium OS Authors. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +class Board: + """A particular board that we can build""" + def __init__(self, target, arch, cpu, board_name, vendor, soc, options): + """Create a new board type. + + Args: + target: Target name (use make <target>_config to configure) + arch: Architecture name (e.g. arm) + cpu: Cpu name (e.g. arm1136) + board_name: Name of board (e.g. integrator) + vendor: Name of vendor (e.g. armltd) + soc: Name of SOC, or '' if none (e.g. mx31) + options: board-specific options (e.g. integratorcp:CM1136) + """ + self.target = target + self.arch = arch + self.cpu = cpu + self.board_name = board_name + self.vendor = vendor + self.soc = soc + self.props = [self.target, self.arch, self.cpu, self.board_name, + self.vendor, self.soc] + self.options = options + self.build_it = False + + +class Boards: + """Manage a list of boards.""" + def __init__(self): + # Use a simple list here, sinc OrderedDict requires Python 2.7 + self._boards = [] + + def AddBoard(self, board): + """Add a new board to the list. + + The board's target member must not already exist in the board list. + + Args: + board: board to add + """ + self._boards.append(board) + + def ReadBoards(self, fname): + """Read a list of boards from a board file. + + Create a board object for each and add it to our _boards list. + + Args: + fname: Filename of boards.cfg file + """ + with open(fname, 'r') as fd: + for line in fd: + if line[0] == '#': + continue + fields = line.split() + if not fields: + continue + for upto in range(len(fields)): + if fields[upto] == '-': + fields[upto] = '' + while len(fields) < 7: + fields.append('') + + board = Board(*fields) + self.AddBoard(board) + + + def GetList(self): + """Return a list of available boards. + + Returns: + List of Board objects + """ + return self._boards + + def GetDict(self): + """Build a dictionary containing all the boards. + + Returns: + Dictionary: + key is board.target + value is board + """ + board_dict = {} + for board in self._boards: + board_dict[board.target] = board + return board_dict + + def GetSelectedDict(self): + """Return a dictionary containing the selected boards + + Returns: + List of Board objects that are marked selected + """ + board_dict = {} + for board in self._boards: + if board.build_it: + board_dict[board.target] = board + return board_dict + + def GetSelected(self): + """Return a list of selected boards + + Returns: + List of Board objects that are marked selected + """ + return [board for board in self._boards if board.build_it] + + def GetSelectedNames(self): + """Return a list of selected boards + + Returns: + List of board names that are marked selected + """ + return [board.target for board in self._boards if board.build_it] + + def SelectBoards(self, args): + """Mark boards selected based on args + + Args: + List of strings specifying boards to include, either named, or + by their target, architecture, cpu, vendor or soc. If empty, all + boards are selected. + + Returns: + Dictionary which holds the number of boards which were selected + due to each argument, arranged by argument. + """ + result = {} + for arg in args: + result[arg] = 0 + result['all'] = 0 + + for board in self._boards: + if args: + for arg in args: + if arg in board.props: + if not board.build_it: + board.build_it = True + result[arg] += 1 + result['all'] += 1 + else: + board.build_it = True + result['all'] += 1 + + return result diff --git a/tools/buildman/bsettings.py b/tools/buildman/bsettings.py new file mode 100644 index 0000000..7e66c63 --- /dev/null +++ b/tools/buildman/bsettings.py @@ -0,0 +1,60 @@ +# Copyright (c) 2012 The Chromium OS Authors. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +import ConfigParser +import os + + +def Setup(fname=''): + """Set up the buildman settings module by reading config files + + Args: + config_fname: Config filename to read ('' for default) + """ + global settings + global config_fname + + settings = ConfigParser.SafeConfigParser() + config_fname = fname + if config_fname == '': + config_fname = '%s/.buildman' % os.getenv('HOME') + if config_fname: + settings.read(config_fname) + +def GetItems(section): + """Get the items from a section of the config. + + Args: + section: name of section to retrieve + + Returns: + List of (name, value) tuples for the section + """ + try: + return settings.items(section) + except ConfigParser.NoSectionError as e: + print e + print ("Warning: No tool chains - please add a [toolchain] section " + "to your buildman config file %s. See README for details" % + config_fname) + return [] + except: + raise diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py new file mode 100644 index 0000000..e426442 --- /dev/null +++ b/tools/buildman/builder.py @@ -0,0 +1,1445 @@ +# Copyright (c) 2013 The Chromium OS Authors. +# +# Bloat-o-meter code used here Copyright 2004 Matt Mackall <mpm@selenic.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +import collections +import errno +from datetime import datetime, timedelta +import glob +import os +import re +import Queue +import shutil +import string +import sys +import threading +import time + +import command +import gitutil +import terminal +import toolchain + + +""" +Theory of Operation + +Please see README for user documentation, and you should be familiar with +that before trying to make sense of this. + +Buildman works by keeping the machine as busy as possible, building different +commits for different boards on multiple CPUs at once. + +The source repo (self.git_dir) contains all the commits to be built. Each +thread works on a single board at a time. It checks out the first commit, +configures it for that board, then builds it. Then it checks out the next +commit and builds it (typically without re-configuring). When it runs out +of commits, it gets another job from the builder and starts again with that +board. + +Clearly the builder threads could work either way - they could check out a +commit and then built it for all boards. Using separate directories for each +commit/board pair they could leave their build product around afterwards +also. + +The intent behind building a single board for multiple commits, is to make +use of incremental builds. Since each commit is built incrementally from +the previous one, builds are faster. Reconfiguring for a different board +removes all intermediate object files. + +Many threads can be working at once, but each has its own working directory. +When a thread finishes a build, it puts the output files into a result +directory. + +The base directory used by buildman is normally '../<branch>', i.e. +a directory higher than the source repository and named after the branch +being built. + +Within the base directory, we have one subdirectory for each commit. Within +that is one subdirectory for each board. Within that is the build output for +that commit/board combination. + +Buildman also create working directories for each thread, in a .bm-work/ +subdirectory in the base dir. + +As an example, say we are building branch 'us-net' for boards 'sandbox' and +'seaboard', and say that us-net has two commits. We will have directories +like this: + +us-net/ base directory + 01_of_02_g4ed4ebc_net--Add-tftp-speed-/ + sandbox/ + u-boot.bin + seaboard/ + u-boot.bin + 02_of_02_g4ed4ebc_net--Check-tftp-comp/ + sandbox/ + u-boot.bin + seaboard/ + u-boot.bin + .bm-work/ + 00/ working directory for thread 0 (contains source checkout) + build/ build output + 01/ working directory for thread 1 + build/ build output + ... +u-boot/ source directory + .git/ repository +""" + +# Possible build outcomes +OUTCOME_OK, OUTCOME_WARNING, OUTCOME_ERROR, OUTCOME_UNKNOWN = range(4) + +# Translate a commit subject into a valid filename +trans_valid_chars = string.maketrans("/: ", "---") + + +def Mkdir(dirname): + """Make a directory if it doesn't already exist. + + Args: + dirname: Directory to create + """ + try: + os.mkdir(dirname) + except OSError as err: + if err.errno == errno.EEXIST: + pass + else: + raise + +class BuilderJob: + """Holds information about a job to be performed by a thread + + Members: + board: Board object to build + commits: List of commit options to build. + """ + def __init__(self): + self.board = None + self.commits = [] + + +class ResultThread(threading.Thread): + """This thread processes results from builder threads. + + It simply passes the results on to the builder. There is only one + result thread, and this helps to serialise the build output. + """ + def __init__(self, builder): + """Set up a new result thread + + Args: + builder: Builder which will be sent each result + """ + threading.Thread.__init__(self) + self.builder = builder + + def run(self): + """Called to start up the result thread. + + We collect the next result job and pass it on to the build. + """ + while True: + result = self.builder.out_queue.get() + self.builder.ProcessResult(result) + self.builder.out_queue.task_done() + + +class BuilderThread(threading.Thread): + """This thread builds U-Boot for a particular board. + + An input queue provides each new job. We run 'make' to build U-Boot + and then pass the results on to the output queue. + + Members: + builder: The builder which contains information we might need + thread_num: Our thread number (0-n-1), used to decide on a + temporary directory + """ + def __init__(self, builder, thread_num): + """Set up a new builder thread""" + threading.Thread.__init__(self) + self.builder = builder + self.thread_num = thread_num + + def Make(self, commit, brd, stage, cwd, *args, **kwargs): + """Run 'make' on a particular commit and board. + + The source code will already be checked out, so the 'commit' + argument is only for information. + + Args: + commit: Commit object that is being built + brd: Board object that is being built + stage: Stage of the build. Valid stages are: + distclean - can be called to clean source + config - called to configure for a board + build - the main make invocation - it does the build + args: A list of arguments to pass to 'make' + kwargs: A list of keyword arguments to pass to command.RunPipe() + + Returns: + CommandResult object + """ + return self.builder.do_make(commit, brd, stage, cwd, *args, + **kwargs) + + def RunCommit(self, commit_upto, brd, work_dir, do_config, force_build): + """Build a particular commit. + + If the build is already done, and we are not forcing a build, we skip + the build and just return the previously-saved results. + + Args: + commit_upto: Commit number to build (0...n-1) + brd: Board object to build + work_dir: Directory to which the source will be checked out + do_config: True to run a make <board>_config on the source + force_build: Force a build even if one was previously done + + Returns: + tuple containing: + - CommandResult object containing the results of the build + - boolean indicating whether 'make config' is still needed + """ + # Create a default result - it will be overwritte by the call to + # self.Make() below, in the event that we do a build. + result = command.CommandResult() + result.return_code = 0 + out_dir = os.path.join(work_dir, 'build') + + # Check if the job was already completed last time + done_file = self.builder.GetDoneFile(commit_upto, brd.target) + result.already_done = os.path.exists(done_file) + if result.already_done and not force_build: + # Get the return code from that build and use it + with open(done_file, 'r') as fd: + result.return_code = int(fd.readline()) + err_file = self.builder.GetErrFile(commit_upto, brd.target) + if os.path.exists(err_file) and os.stat(err_file).st_size: + result.stderr = 'bad' + else: + # We are going to have to build it. First, get a toolchain + if not self.toolchain: + try: + self.toolchain = self.builder.toolchains.Select(brd.arch) + except ValueError as err: + result.return_code = 10 + result.stdout = '' + result.stderr = str(err) + # TODO(sjg@chromium.org): This gets swallowed, but needs + # to be reported. + + if self.toolchain: + # Checkout the right commit + if commit_upto is not None: + commit = self.builder.commits[commit_upto] + if self.builder.checkout: + git_dir = os.path.join(work_dir, '.git') + gitutil.Checkout(commit.hash, git_dir, work_dir, + force=True) + else: + commit = self.builder.commit # Ick, fix this for BuildCommits() + + # Set up the environment and command line + env = self.toolchain.MakeEnvironment() + Mkdir(out_dir) + args = ['O=build', '-s'] + if self.builder.num_jobs is not None: + args.extend(['-j', str(self.builder.num_jobs)]) + config_args = ['%s_config' % brd.target] + config_out = '' + + # If we need to reconfigure, do that now + if do_config: + result = self.Make(commit, brd, 'distclean', work_dir, + 'distclean', *args, env=env) + result = self.Make(commit, brd, 'config', work_dir, + *(args + config_args), env=env) + config_out = result.combined + do_config = False # No need to configure next time + if result.return_code == 0: + result = self.Make(commit, brd, 'build', work_dir, *args, + env=env) + result.stdout = config_out + result.stdout + else: + result.return_code = 1 + result.stderr = 'No tool chain for %s\n' % brd.arch + result.already_done = False + + result.toolchain = self.toolchain + result.brd = brd + result.commit_upto = commit_upto + result.out_dir = out_dir + return result, do_config + + def _WriteResult(self, result, keep_outputs): + """Write a built result to the output directory. + + Args: + result: CommandResult object containing result to write + keep_outputs: True to store the output binaries, False + to delete them + """ + # Fatal error + if result.return_code < 0: + return + + # Aborted? + if result.stderr and 'No child processes' in result.stderr: + return + + if result.already_done: + return + + # Write the output and stderr + output_dir = self.builder._GetOutputDir(result.commit_upto) + Mkdir(output_dir) + build_dir = self.builder.GetBuildDir(result.commit_upto, + result.brd.target) + Mkdir(build_dir) + + outfile = os.path.join(build_dir, 'log') + with open(outfile, 'w') as fd: + if result.stdout: + fd.write(result.stdout) + + errfile = self.builder.GetErrFile(result.commit_upto, + result.brd.target) + if result.stderr: + with open(errfile, 'w') as fd: + fd.write(result.stderr) + elif os.path.exists(errfile): + os.remove(errfile) + + if result.toolchain: + # Write the build result and toolchain information. + done_file = self.builder.GetDoneFile(result.commit_upto, + result.brd.target) + with open(done_file, 'w') as fd: + fd.write('%s' % result.return_code) + with open(os.path.join(build_dir, 'toolchain'), 'w') as fd: + print >>fd, 'gcc', result.toolchain.gcc + print >>fd, 'path', result.toolchain.path + print >>fd, 'cross', result.toolchain.cross + print >>fd, 'arch', result.toolchain.arch + fd.write('%s' % result.return_code) + + with open(os.path.join(build_dir, 'toolchain'), 'w') as fd: + print >>fd, 'gcc', result.toolchain.gcc + print >>fd, 'path', result.toolchain.path + + # Write out the image and function size information and an objdump + env = result.toolchain.MakeEnvironment() + lines = [] + for fname in ['u-boot', 'spl/u-boot-spl']: + cmd = ['%snm' % self.toolchain.cross, '--size-sort', fname] + nm_result = command.RunPipe([cmd], capture=True, + capture_stderr=True, cwd=result.out_dir, + raise_on_error=False, env=env) + if nm_result.stdout: + nm = self.builder.GetFuncSizesFile(result.commit_upto, + result.brd.target, fname) + with open(nm, 'w') as fd: + print >>fd, nm_result.stdout, + + cmd = ['%sobjdump' % self.toolchain.cross, '-h', fname] + dump_result = command.RunPipe([cmd], capture=True, + capture_stderr=True, cwd=result.out_dir, + raise_on_error=False, env=env) + rodata_size = '' + if dump_result.stdout: + objdump = self.builder.GetObjdumpFile(result.commit_upto, + result.brd.target, fname) + with open(objdump, 'w') as fd: + print >>fd, dump_result.stdout, + for line in dump_result.stdout.splitlines(): + fields = line.split() + if len(fields) > 5 and fields[1] == '.rodata': + rodata_size = fields[2] + + cmd = ['%ssize' % self.toolchain.cross, fname] + size_result = command.RunPipe([cmd], capture=True, + capture_stderr=True, cwd=result.out_dir, + raise_on_error=False, env=env) + if size_result.stdout: + lines.append(size_result.stdout.splitlines()[1] + ' ' + + rodata_size) + + # Write out the image sizes file. This is similar to the output + # of binutil's 'size' utility, but it omits the header line and + # adds an additional hex value at the end of each line for the + # rodata size + if len(lines): + sizes = self.builder.GetSizesFile(result.commit_upto, + result.brd.target) + with open(sizes, 'w') as fd: + print >>fd, '\n'.join(lines) + + # Now write the actual build output + if keep_outputs: + patterns = ['u-boot', '*.bin', 'u-boot.dtb', '*.map', + 'include/autoconf.mk', 'spl/u-boot-spl', + 'spl/u-boot-spl.bin'] + for pattern in patterns: + file_list = glob.glob(os.path.join(result.out_dir, pattern)) + for fname in file_list: + shutil.copy(fname, build_dir) + + + def RunJob(self, job): + """Run a single job + + A job consists of a building a list of commits for a particular board. + + Args: + job: Job to build + """ + brd = job.board + work_dir = self.builder.GetThreadDir(self.thread_num) + self.toolchain = None + if job.commits: + # Run 'make board_config' on the first commit + do_config = True + commit_upto = 0 + force_build = False + for commit_upto in range(0, len(job.commits), job.step): + result, request_config = self.RunCommit(commit_upto, brd, + work_dir, do_config, + force_build or self.builder.force_build) + failed = result.return_code or result.stderr + if failed and not do_config: + # If our incremental build failed, try building again + # with a reconfig. + if self.builder.force_config_on_failure: + result, request_config = self.RunCommit(commit_upto, + brd, work_dir, True, True) + do_config = request_config + + # If we built that commit, then config is done. But if we got + # an warning, reconfig next time to force it to build the same + # files that created warnings this time. Otherwise an + # incremental build may not build the same file, and we will + # think that the warning has gone away. + # We could avoid this by using -Werror everywhere... + # For errors, the problem doesn't happen, since presumably + # the build stopped and didn't generate output, so will retry + # that file next time. So we could detect warnings and deal + # with them specially here. For now, we just reconfigure if + # anything goes work. + # Of course this is substantially slower if there are build + # errors/warnings (e.g. 2-3x slower even if only 10% of builds + # have problems). + if (failed and not result.already_done and not do_config and + self.builder.force_config_on_failure): + # If this build failed, try the next one with a + # reconfigure. + # Sometimes if the board_config.h file changes it can mess + # with dependencies, and we get: + # make: *** No rule to make target `include/autoconf.mk', + # needed by `depend'. + do_config = True + force_build = True + else: + force_build = False + if self.builder.force_config_on_failure: + if failed: + do_config = True + result.commit_upto = commit_upto + if result.return_code < 0: + raise ValueError('Interrupt') + + # We have the build results, so output the result + self._WriteResult(result, job.keep_outputs) + self.builder.out_queue.put(result) + else: + # Just build the currently checked-out build + result = self.RunCommit(None, True) + result.commit_upto = self.builder.upto + self.builder.out_queue.put(result) + + def run(self): + """Our thread's run function + + This thread picks a job from the queue, runs it, and then goes to the + next job. + """ + alive = True + while True: + job = self.builder.queue.get() + try: + if self.builder.active and alive: + self.RunJob(job) + except Exception as err: + alive = False + print err + self.builder.queue.task_done() + + +class Builder: + """Class for building U-Boot for a particular commit. + + Public members: (many should ->private) + active: True if the builder is active and has not been stopped + already_done: Number of builds already completed + base_dir: Base directory to use for builder + checkout: True to check out source, False to skip that step. + This is used for testing. + col: terminal.Color() object + count: Number of commits to build + do_make: Method to call to invoke Make + fail: Number of builds that failed due to error + force_build: Force building even if a build already exists + force_config_on_failure: If a commit fails for a board, disable + incremental building for the next commit we build for that + board, so that we will see all warnings/errors again. + git_dir: Git directory containing source repository + last_line_len: Length of the last line we printed (used for erasing + it with new progress information) + num_jobs: Number of jobs to run at once (passed to make as -j) + num_threads: Number of builder threads to run + out_queue: Queue of results to process + re_make_err: Compiled regular expression for ignore_lines + queue: Queue of jobs to run + threads: List of active threads + toolchains: Toolchains object to use for building + upto: Current commit number we are building (0.count-1) + warned: Number of builds that produced at least one warning + + Private members: + _base_board_dict: Last-summarised Dict of boards + _base_err_lines: Last-summarised list of errors + _build_period_us: Time taken for a single build (float object). + _complete_delay: Expected delay until completion (timedelta) + _next_delay_update: Next time we plan to display a progress update + (datatime) + _show_unknown: Show unknown boards (those not built) in summary + _timestamps: List of timestamps for the completion of the last + last _timestamp_count builds. Each is a datetime object. + _timestamp_count: Number of timestamps to keep in our list. + _working_dir: Base working directory containing all threads + """ + class Outcome: + """Records a build outcome for a single make invocation + + Public Members: + rc: Outcome value (OUTCOME_...) + err_lines: List of error lines or [] if none + sizes: Dictionary of image size information, keyed by filename + - Each value is itself a dictionary containing + values for 'text', 'data' and 'bss', being the integer + size in bytes of each section. + func_sizes: Dictionary keyed by filename - e.g. 'u-boot'. Each + value is itself a dictionary: + key: function name + value: Size of function in bytes + """ + def __init__(self, rc, err_lines, sizes, func_sizes): + self.rc = rc + self.err_lines = err_lines + self.sizes = sizes + self.func_sizes = func_sizes + + def __init__(self, toolchains, base_dir, git_dir, num_threads, num_jobs, + checkout=True, show_unknown=True, step=1): + """Create a new Builder object + + Args: + toolchains: Toolchains object to use for building + base_dir: Base directory to use for builder + git_dir: Git directory containing source repository + num_threads: Number of builder threads to run + num_jobs: Number of jobs to run at once (passed to make as -j) + checkout: True to check out source, False to skip that step. + This is used for testing. + show_unknown: Show unknown boards (those not built) in summary + step: 1 to process every commit, n to process every nth commit + """ + self.toolchains = toolchains + self.base_dir = base_dir + self._working_dir = os.path.join(base_dir, '.bm-work') + self.threads = [] + self.active = True + self.do_make = self.Make + self.checkout = checkout + self.num_threads = num_threads + self.num_jobs = num_jobs + self.already_done = 0 + self.force_build = False + self.git_dir = git_dir + self._show_unknown = show_unknown + self._timestamp_count = 10 + self._build_period_us = None + self._complete_delay = None + self._next_delay_update = datetime.now() + self.force_config_on_failure = True + self._step = step + + self.col = terminal.Color() + + self.queue = Queue.Queue() + self.out_queue = Queue.Queue() + for i in range(self.num_threads): + t = BuilderThread(self, i) + t.setDaemon(True) + t.start() + self.threads.append(t) + + self.last_line_len = 0 + t = ResultThread(self) + t.setDaemon(True) + t.start() + self.threads.append(t) + + ignore_lines = ['(make.*Waiting for unfinished)', '(Segmentation fault)'] + self.re_make_err = re.compile('|'.join(ignore_lines)) + + def __del__(self): + """Get rid of all threads created by the builder""" + for t in self.threads: + del t + + def _AddTimestamp(self): + """Add a new timestamp to the list and record the build period. + + The build period is the length of time taken to perform a single + build (one board, one commit). + """ + now = datetime.now() + self._timestamps.append(now) + count = len(self._timestamps) + delta = self._timestamps[-1] - self._timestamps[0] + seconds = delta.total_seconds() + + # If we have enough data, estimate build period (time taken for a + # single build) and therefore completion time. + if count > 1 and self._next_delay_update < now: + self._next_delay_update = now + timedelta(seconds=2) + if seconds > 0: + self._build_period = float(seconds) / count + todo = self.count - self.upto + self._complete_delay = timedelta(microseconds= + self._build_period * todo * 1000000) + # Round it + self._complete_delay -= timedelta( + microseconds=self._complete_delay.microseconds) + + if seconds > 60: + self._timestamps.popleft() + count -= 1 + + def ClearLine(self, length): + """Clear any characters on the current line + + Make way for a new line of length 'length', by outputting enough + spaces to clear out the old line. Then remember the new length for + next time. + + Args: + length: Length of new line, in characters + """ + if length < self.last_line_len: + print ' ' * (self.last_line_len - length), + print '\r', + self.last_line_len = length + sys.stdout.flush() + + def SelectCommit(self, commit, checkout=True): + """Checkout the selected commit for this build + """ + self.commit = commit + if checkout and self.checkout: + gitutil.Checkout(commit.hash) + + def Make(self, commit, brd, stage, cwd, *args, **kwargs): + """Run make + + Args: + commit: Commit object that is being built + brd: Board object that is being built + stage: Stage that we are at (distclean, config, build) + cwd: Directory where make should be run + args: Arguments to pass to make + kwargs: Arguments to pass to command.RunPipe() + """ + cmd = ['make'] + list(args) + result = command.RunPipe([cmd], capture=True, capture_stderr=True, + cwd=cwd, raise_on_error=False, **kwargs) + return result + + def ProcessResult(self, result): + """Process the result of a build, showing progress information + + Args: + result: A CommandResult object + """ + col = terminal.Color() + if result: + target = result.brd.target + + if result.return_code < 0: + self.active = False + command.StopAll() + return + + self.upto += 1 + if result.return_code != 0: + self.fail += 1 + elif result.stderr: + self.warned += 1 + if result.already_done: + self.already_done += 1 + else: + target = '(starting)' + + # Display separate counts for ok, warned and fail + ok = self.upto - self.warned - self.fail + line = '\r' + self.col.Color(self.col.GREEN, '%5d' % ok) + line += self.col.Color(self.col.YELLOW, '%5d' % self.warned) + line += self.col.Color(self.col.RED, '%5d' % self.fail) + + name = ' /%-5d ' % self.count + + # Add our current completion time estimate + self._AddTimestamp() + if self._complete_delay: + name += '%s : ' % self._complete_delay + # When building all boards for a commit, we can print a commit + # progress message. + if result and result.commit_upto is None: + name += 'commit %2d/%-3d' % (self.commit_upto + 1, + self.commit_count) + + name += target + print line + name, + length = 13 + len(name) + self.ClearLine(length) + + def _GetOutputDir(self, commit_upto): + """Get the name of the output directory for a commit number + + The output directory is typically .../<branch>/<commit>. + + Args: + commit_upto: Commit number to use (0..self.count-1) + """ + commit = self.commits[commit_upto] + subject = commit.subject.translate(trans_valid_chars) + commit_dir = ('%02d_of_%02d_g%s_%s' % (commit_upto + 1, + self.commit_count, commit.hash, subject[:20])) + output_dir = os.path.join(self.base_dir, commit_dir) + return output_dir + + def GetBuildDir(self, commit_upto, target): + """Get the name of the build directory for a commit number + + The build directory is typically .../<branch>/<commit>/<target>. + + Args: + commit_upto: Commit number to use (0..self.count-1) + target: Target name + """ + output_dir = self._GetOutputDir(commit_upto) + return os.path.join(output_dir, target) + + def GetDoneFile(self, commit_upto, target): + """Get the name of the done file for a commit number + + Args: + commit_upto: Commit number to use (0..self.count-1) + target: Target name + """ + return os.path.join(self.GetBuildDir(commit_upto, target), 'done') + + def GetSizesFile(self, commit_upto, target): + """Get the name of the sizes file for a commit number + + Args: + commit_upto: Commit number to use (0..self.count-1) + target: Target name + """ + return os.path.join(self.GetBuildDir(commit_upto, target), 'sizes') + + def GetFuncSizesFile(self, commit_upto, target, elf_fname): + """Get the name of the funcsizes file for a commit number and ELF file + + Args: + commit_upto: Commit number to use (0..self.count-1) + target: Target name + elf_fname: Filename of elf image + """ + return os.path.join(self.GetBuildDir(commit_upto, target), + '%s.sizes' % elf_fname.replace('/', '-')) + + def GetObjdumpFile(self, commit_upto, target, elf_fname): + """Get the name of the objdump file for a commit number and ELF file + + Args: + commit_upto: Commit number to use (0..self.count-1) + target: Target name + elf_fname: Filename of elf image + """ + return os.path.join(self.GetBuildDir(commit_upto, target), + '%s.objdump' % elf_fname.replace('/', '-')) + + def GetErrFile(self, commit_upto, target): + """Get the name of the err file for a commit number + + Args: + commit_upto: Commit number to use (0..self.count-1) + target: Target name + """ + output_dir = self.GetBuildDir(commit_upto, target) + return os.path.join(output_dir, 'err') + + def FilterErrors(self, lines): + """Filter out errors in which we have no interest + + We should probably use map(). + + Args: + lines: List of error lines, each a string + Returns: + New list with only interesting lines included + """ + out_lines = [] + for line in lines: + if not self.re_make_err.search(line): + out_lines.append(line) + return out_lines + + def ReadFuncSizes(self, fname, fd): + """Read function sizes from the output of 'nm' + + Args: + fd: File containing data to read + fname: Filename we are reading from (just for errors) + + Returns: + Dictionary containing size of each function in bytes, indexed by + function name. + """ + sym = {} + for line in fd.readlines(): + try: + size, type, name = line[:-1].split() + except: + print "Invalid line in file '%s': '%s'" % (fname, line[:-1]) + continue + if type in 'tTdDbB': + # function names begin with '.' on 64-bit powerpc + if '.' in name[1:]: + name = 'static.' + name.split('.')[0] + sym[name] = sym.get(name, 0) + int(size, 16) + return sym + + def GetBuildOutcome(self, commit_upto, target, read_func_sizes): + """Work out the outcome of a build. + + Args: + commit_upto: Commit number to check (0..n-1) + target: Target board to check + read_func_sizes: True to read function size information + + Returns: + Outcome object + """ + done_file = self.GetDoneFile(commit_upto, target) + sizes_file = self.GetSizesFile(commit_upto, target) + sizes = {} + func_sizes = {} + if os.path.exists(done_file): + with open(done_file, 'r') as fd: + return_code = int(fd.readline()) + err_lines = [] + err_file = self.GetErrFile(commit_upto, target) + if os.path.exists(err_file): + with open(err_file, 'r') as fd: + err_lines = self.FilterErrors(fd.readlines()) + + # Decide whether the build was ok, failed or created warnings + if return_code: + rc = OUTCOME_ERROR + elif len(err_lines): + rc = OUTCOME_WARNING + else: + rc = OUTCOME_OK + + # Convert size information to our simple format + if os.path.exists(sizes_file): + with open(sizes_file, 'r') as fd: + for line in fd.readlines(): + values = line.split() + rodata = 0 + if len(values) > 6: + rodata = int(values[6], 16) + size_dict = { + 'all' : int(values[0]) + int(values[1]) + + int(values[2]), + 'text' : int(values[0]) - rodata, + 'data' : int(values[1]), + 'bss' : int(values[2]), + 'rodata' : rodata, + } + sizes[values[5]] = size_dict + + if read_func_sizes: + pattern = self.GetFuncSizesFile(commit_upto, target, '*') + for fname in glob.glob(pattern): + with open(fname, 'r') as fd: + dict_name = os.path.basename(fname).replace('.sizes', + '') + func_sizes[dict_name] = self.ReadFuncSizes(fname, fd) + + return Builder.Outcome(rc, err_lines, sizes, func_sizes) + + return Builder.Outcome(OUTCOME_UNKNOWN, [], {}, {}) + + def GetResultSummary(self, boards_selected, commit_upto, read_func_sizes): + """Calculate a summary of the results of building a commit. + + Args: + board_selected: Dict containing boards to summarise + commit_upto: Commit number to summarize (0..self.count-1) + read_func_sizes: True to read function size information + + Returns: + Tuple: + Dict containing boards which passed building this commit. + keyed by board.target + List containing a summary of error/warning lines + """ + board_dict = {} + err_lines_summary = [] + + for board in boards_selected.itervalues(): + outcome = self.GetBuildOutcome(commit_upto, board.target, + read_func_sizes) + board_dict[board.target] = outcome + for err in outcome.err_lines: + if err and not err.rstrip() in err_lines_summary: + err_lines_summary.append(err.rstrip()) + return board_dict, err_lines_summary + + def AddOutcome(self, board_dict, arch_list, changes, char, color): + """Add an output to our list of outcomes for each architecture + + This simple function adds failing boards (changes) to the + relevant architecture string, so we can print the results out + sorted by architecture. + + Args: + board_dict: Dict containing all boards + arch_list: Dict keyed by arch name. Value is a string containing + a list of board names which failed for that arch. + changes: List of boards to add to arch_list + color: terminal.Colour object + """ + done_arch = {} + for target in changes: + if target in board_dict: + arch = board_dict[target].arch + else: + arch = 'unknown' + str = self.col.Color(color, ' ' + target) + if not arch in done_arch: + str = self.col.Color(color, char) + ' ' + str + done_arch[arch] = True + if not arch in arch_list: + arch_list[arch] = str + else: + arch_list[arch] += str + + + def ColourNum(self, num): + color = self.col.RED if num > 0 else self.col.GREEN + if num == 0: + return '0' + return self.col.Color(color, str(num)) + + def ResetResultSummary(self, board_selected): + """Reset the results summary ready for use. + + Set up the base board list to be all those selected, and set the + error lines to empty. + + Following this, calls to PrintResultSummary() will use this + information to work out what has changed. + + Args: + board_selected: Dict containing boards to summarise, keyed by + board.target + """ + self._base_board_dict = {} + for board in board_selected: + self._base_board_dict[board] = Builder.Outcome(0, [], [], {}) + self._base_err_lines = [] + + def PrintFuncSizeDetail(self, fname, old, new): + grow, shrink, add, remove, up, down = 0, 0, 0, 0, 0, 0 + delta, common = [], {} + + for a in old: + if a in new: + common[a] = 1 + + for name in old: + if name not in common: + remove += 1 + down += old[name] + delta.append([-old[name], name]) + + for name in new: + if name not in common: + add += 1 + up += new[name] + delta.append([new[name], name]) + + for name in common: + diff = new.get(name, 0) - old.get(name, 0) + if diff > 0: + grow, up = grow + 1, up + diff + elif diff < 0: + shrink, down = shrink + 1, down - diff + delta.append([diff, name]) + + delta.sort() + delta.reverse() + + args = [add, -remove, grow, -shrink, up, -down, up - down] + if max(args) == 0: + return + args = [self.ColourNum(x) for x in args] + indent = ' ' * 15 + print ('%s%s: add: %s/%s, grow: %s/%s bytes: %s/%s (%s)' % + tuple([indent, self.col.Color(self.col.YELLOW, fname)] + args)) + print '%s %-38s %7s %7s %+7s' % (indent, 'function', 'old', 'new', + 'delta') + for diff, name in delta: + if diff: + color = self.col.RED if diff > 0 else self.col.GREEN + msg = '%s %-38s %7s %7s %+7d' % (indent, name, + old.get(name, '-'), new.get(name,'-'), diff) + print self.col.Color(color, msg) + + + def PrintSizeDetail(self, target_list, show_bloat): + """Show details size information for each board + + Args: + target_list: List of targets, each a dict containing: + 'target': Target name + 'total_diff': Total difference in bytes across all areas + <part_name>: Difference for that part + show_bloat: Show detail for each function + """ + targets_by_diff = sorted(target_list, reverse=True, + key=lambda x: x['_total_diff']) + for result in targets_by_diff: + printed_target = False + for name in sorted(result): + diff = result[name] + if name.startswith('_'): + continue + if diff != 0: + color = self.col.RED if diff > 0 else self.col.GREEN + msg = ' %s %+d' % (name, diff) + if not printed_target: + print '%10s %-15s:' % ('', result['_target']), + printed_target = True + print self.col.Color(color, msg), + if printed_target: + print + if show_bloat: + target = result['_target'] + outcome = result['_outcome'] + base_outcome = self._base_board_dict[target] + for fname in outcome.func_sizes: + self.PrintFuncSizeDetail(fname, + base_outcome.func_sizes[fname], + outcome.func_sizes[fname]) + + + def PrintSizeSummary(self, board_selected, board_dict, show_detail, + show_bloat): + """Print a summary of image sizes broken down by section. + + The summary takes the form of one line per architecture. The + line contains deltas for each of the sections (+ means the section + got bigger, - means smaller). The nunmbers are the average number + of bytes that a board in this section increased by. + + For example: + powerpc: (622 boards) text -0.0 + arm: (285 boards) text -0.0 + nds32: (3 boards) text -8.0 + + Args: + board_selected: Dict containing boards to summarise, keyed by + board.target + board_dict: Dict containing boards for which we built this + commit, keyed by board.target. The value is an Outcome object. + show_detail: Show detail for each board + show_bloat: Show detail for each function + """ + arch_list = {} + arch_count = {} + + # Calculate changes in size for different image parts + # The previous sizes are in Board.sizes, for each board + for target in board_dict: + if target not in board_selected: + continue + base_sizes = self._base_board_dict[target].sizes + outcome = board_dict[target] + sizes = outcome.sizes + + # Loop through the list of images, creating a dict of size + # changes for each image/part. We end up with something like + # {'target' : 'snapper9g45, 'data' : 5, 'u-boot-spl:text' : -4} + # which means that U-Boot data increased by 5 bytes and SPL + # text decreased by 4. + err = {'_target' : target} + for image in sizes: + if image in base_sizes: + base_image = base_sizes[image] + # Loop through the text, data, bss parts + for part in sorted(sizes[image]): + diff = sizes[image][part] - base_image[part] + col = None + if diff: + if image == 'u-boot': + name = part + else: + name = image + ':' + part + err[name] = diff + arch = board_selected[target].arch + if not arch in arch_count: + arch_count[arch] = 1 + else: + arch_count[arch] += 1 + if not sizes: + pass # Only add to our list when we have some stats + elif not arch in arch_list: + arch_list[arch] = [err] + else: + arch_list[arch].append(err) + + # We now have a list of image size changes sorted by arch + # Print out a summary of these + for arch, target_list in arch_list.iteritems(): + # Get total difference for each type + totals = {} + for result in target_list: + total = 0 + for name, diff in result.iteritems(): + if name.startswith('_'): + continue + total += diff + if name in totals: + totals[name] += diff + else: + totals[name] = diff + result['_total_diff'] = total + result['_outcome'] = board_dict[result['_target']] + + count = len(target_list) + printed_arch = False + for name in sorted(totals): + diff = totals[name] + if diff: + # Display the average difference in this name for this + # architecture + avg_diff = float(diff) / count + color = self.col.RED if avg_diff > 0 else self.col.GREEN + msg = ' %s %+1.1f' % (name, avg_diff) + if not printed_arch: + print '%10s: (for %d/%d boards)' % (arch, count, + arch_count[arch]), + printed_arch = True + print self.col.Color(color, msg), + + if printed_arch: + print + if show_detail: + self.PrintSizeDetail(target_list, show_bloat) + + + def PrintResultSummary(self, board_selected, board_dict, err_lines, + show_sizes, show_detail, show_bloat): + """Compare results with the base results and display delta. + + Only boards mentioned in board_selected will be considered. This + function is intended to be called repeatedly with the results of + each commit. It therefore shows a 'diff' between what it saw in + the last call and what it sees now. + + Args: + board_selected: Dict containing boards to summarise, keyed by + board.target + board_dict: Dict containing boards for which we built this + commit, keyed by board.target. The value is an Outcome object. + err_lines: A list of errors for this commit, or [] if there is + none, or we don't want to print errors + show_sizes: Show image size deltas + show_detail: Show detail for each board + show_bloat: Show detail for each function + """ + better = [] # List of boards fixed since last commit + worse = [] # List of new broken boards since last commit + new = [] # List of boards that didn't exist last time + unknown = [] # List of boards that were not built + + for target in board_dict: + if target not in board_selected: + continue + + # If the board was built last time, add its outcome to a list + if target in self._base_board_dict: + base_outcome = self._base_board_dict[target].rc + outcome = board_dict[target] + if outcome.rc == OUTCOME_UNKNOWN: + unknown.append(target) + elif outcome.rc < base_outcome: + better.append(target) + elif outcome.rc > base_outcome: + worse.append(target) + else: + new.append(target) + + # Get a list of errors that have appeared, and disappeared + better_err = [] + worse_err = [] + for line in err_lines: + if line not in self._base_err_lines: + worse_err.append('+' + line) + for line in self._base_err_lines: + if line not in err_lines: + better_err.append('-' + line) + + # Display results by arch + if better or worse or unknown or new or worse_err or better_err: + arch_list = {} + self.AddOutcome(board_selected, arch_list, better, '', + self.col.GREEN) + self.AddOutcome(board_selected, arch_list, worse, '+', + self.col.RED) + self.AddOutcome(board_selected, arch_list, new, '*', self.col.BLUE) + if self._show_unknown: + self.AddOutcome(board_selected, arch_list, unknown, '?', + self.col.MAGENTA) + for arch, target_list in arch_list.iteritems(): + print '%10s: %s' % (arch, target_list) + if better_err: + print self.col.Color(self.col.GREEN, '\n'.join(better_err)) + if worse_err: + print self.col.Color(self.col.RED, '\n'.join(worse_err)) + + if show_sizes: + self.PrintSizeSummary(board_selected, board_dict, show_detail, + show_bloat) + + # Save our updated information for the next call to this function + self._base_board_dict = board_dict + self._base_err_lines = err_lines + + # Get a list of boards that did not get built, if needed + not_built = [] + for board in board_selected: + if not board in board_dict: + not_built.append(board) + if not_built: + print "Boards not built (%d): %s" % (len(not_built), + ', '.join(not_built)) + + + def ShowSummary(self, commits, board_selected, show_errors, show_sizes, + show_detail, show_bloat): + """Show a build summary for U-Boot for a given board list. + + Reset the result summary, then repeatedly call GetResultSummary on + each commit's results, then display the differences we see. + + Args: + commit: Commit objects to summarise + board_selected: Dict containing boards to summarise + show_errors: Show errors that occured + show_sizes: Show size deltas + show_detail: Show detail for each board + show_bloat: Show detail for each function + """ + self.commit_count = len(commits) + self.commits = commits + self.ResetResultSummary(board_selected) + + for commit_upto in range(0, self.commit_count, self._step): + board_dict, err_lines = self.GetResultSummary(board_selected, + commit_upto, read_func_sizes=show_bloat) + msg = '%02d: %s' % (commit_upto + 1, commits[commit_upto].subject) + print self.col.Color(self.col.BLUE, msg) + self.PrintResultSummary(board_selected, board_dict, + err_lines if show_errors else [], show_sizes, show_detail, + show_bloat) + + + def SetupBuild(self, board_selected, commits): + """Set up ready to start a build. + + Args: + board_selected: Selected boards to build + commits: Selected commits to build + """ + # First work out how many commits we will build + count = (len(commits) + self._step - 1) / self._step + self.count = len(board_selected) * count + self.upto = self.warned = self.fail = 0 + self._timestamps = collections.deque() + + def BuildBoardsForCommit(self, board_selected, keep_outputs): + """Build all boards for a single commit""" + self.SetupBuild(board_selected) + self.count = len(board_selected) + for brd in board_selected.itervalues(): + job = BuilderJob() + job.board = brd + job.commits = None + job.keep_outputs = keep_outputs + self.queue.put(brd) + + self.queue.join() + self.out_queue.join() + print + self.ClearLine(0) + + def BuildCommits(self, commits, board_selected, show_errors, keep_outputs): + """Build all boards for all commits (non-incremental)""" + self.commit_count = len(commits) + + self.ResetResultSummary(board_selected) + for self.commit_upto in range(self.commit_count): + self.SelectCommit(commits[self.commit_upto]) + self.SelectOutputDir() + Mkdir(self.output_dir) + + self.BuildBoardsForCommit(board_selected, keep_outputs) + board_dict, err_lines = self.GetResultSummary() + self.PrintResultSummary(board_selected, board_dict, + err_lines if show_errors else []) + + if self.already_done: + print '%d builds already done' % self.already_done + + def GetThreadDir(self, thread_num): + """Get the directory path to the working dir for a thread. + + Args: + thread_num: Number of thread to check. + """ + return os.path.join(self._working_dir, '%02d' % thread_num) + + def _PrepareThread(self, thread_num): + """Prepare the working directory for a thread. + + This clones or fetches the repo into the thread's work directory. + + Args: + thread_num: Thread number (0, 1, ...) + """ + thread_dir = self.GetThreadDir(thread_num) + Mkdir(thread_dir) + git_dir = os.path.join(thread_dir, '.git') + + # Clone the repo if it doesn't already exist + # TODO(sjg@chromium): Perhaps some git hackery to symlink instead, so + # we have a private index but uses the origin repo's contents? + if self.git_dir: + src_dir = os.path.abspath(self.git_dir) + if os.path.exists(git_dir): + gitutil.Fetch(git_dir, thread_dir) + else: + print 'Cloning repo for thread %d' % thread_num + gitutil.Clone(src_dir, thread_dir) + + def _PrepareWorkingSpace(self, max_threads): + """Prepare the working directory for use. + + Set up the git repo for each thread. + + Args: + max_threads: Maximum number of threads we expect to need. + """ + Mkdir(self._working_dir) + for thread in range(max_threads): + self._PrepareThread(thread) + + def _PrepareOutputSpace(self): + """Get the output directories ready to receive files. + + We delete any output directories which look like ones we need to + create. Having left over directories is confusing when the user wants + to check the output manually. + """ + dir_list = [] + for commit_upto in range(self.commit_count): + dir_list.append(self._GetOutputDir(commit_upto)) + + for dirname in glob.glob(os.path.join(self.base_dir, '*')): + if dirname not in dir_list: + shutil.rmtree(dirname) + + def BuildBoards(self, commits, board_selected, show_errors, keep_outputs): + """Build all commits for a list of boards + + Args: + commits: List of commits to be build, each a Commit object + boards_selected: Dict of selected boards, key is target name, + value is Board object + show_errors: True to show summarised error/warning info + keep_outputs: True to save build output files + """ + self.commit_count = len(commits) + self.commits = commits + + self.ResetResultSummary(board_selected) + Mkdir(self.base_dir) + self._PrepareWorkingSpace(min(self.num_threads, len(board_selected))) + self._PrepareOutputSpace() + self.SetupBuild(board_selected, commits) + self.ProcessResult(None) + + # Create jobs to build all commits for each board + for brd in board_selected.itervalues(): + job = BuilderJob() + job.board = brd + job.commits = commits + job.keep_outputs = keep_outputs + job.step = self._step + self.queue.put(job) + + # Wait until all jobs are started + self.queue.join() + + # Wait until we have processed all output + self.out_queue.join() + print + self.ClearLine(0) diff --git a/tools/buildman/buildman b/tools/buildman/buildman new file mode 120000 index 0000000..e4fba2d --- /dev/null +++ b/tools/buildman/buildman @@ -0,0 +1 @@ +buildman.py
\ No newline at end of file diff --git a/tools/buildman/buildman.py b/tools/buildman/buildman.py new file mode 100755 index 0000000..7b05d0f --- /dev/null +++ b/tools/buildman/buildman.py @@ -0,0 +1,126 @@ +#!/usr/bin/python +# +# Copyright (c) 2012 The Chromium OS Authors. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +"""See README for more information""" + +import multiprocessing +from optparse import OptionParser +import os +import re +import sys +import unittest + +# Bring in the patman libraries +our_path = os.path.dirname(os.path.realpath(__file__)) +sys.path.append(os.path.join(our_path, '../patman')) + +# Our modules +import board +import builder +import checkpatch +import command +import control +import doctest +import gitutil +import patchstream +import terminal +import toolchain + +def RunTests(): + import test + + sys.argv = [sys.argv[0]] + suite = unittest.TestLoader().loadTestsFromTestCase(test.TestBuild) + result = unittest.TestResult() + suite.run(result) + + # TODO: Surely we can just 'print' result? + print result + for test, err in result.errors: + print err + for test, err in result.failures: + print err + + +parser = OptionParser() +parser.add_option('-b', '--branch', type='string', + help='Branch name to build') +parser.add_option('-B', '--bloat', dest='show_bloat', + action='store_true', default=False, + help='Show changes in function code size for each board') +parser.add_option('-c', '--count', dest='count', type='int', + default=-1, help='Run build on the top n commits') +parser.add_option('-e', '--show_errors', action='store_true', + default=False, help='Show errors and warnings') +parser.add_option('-f', '--force-build', dest='force_build', + action='store_true', default=False, + help='Force build of boards even if already built') +parser.add_option('-d', '--detail', dest='show_detail', + action='store_true', default=False, + help='Show detailed information for each board in summary') +parser.add_option('-g', '--git', type='string', + help='Git repo containing branch to build', default='.') +parser.add_option('-H', '--full-help', action='store_true', dest='full_help', + default=False, help='Display the README file') +parser.add_option('-j', '--jobs', dest='jobs', type='int', + default=None, help='Number of jobs to run at once (passed to make)') +parser.add_option('-k', '--keep-outputs', action='store_true', + default=False, help='Keep all build output files (e.g. binaries)') +parser.add_option('--list-tool-chains', action='store_true', default=False, + help='List available tool chains') +parser.add_option('-n', '--dry-run', action='store_true', dest='dry_run', + default=False, help="Do a try run (describe actions, but no nothing)") +parser.add_option('-Q', '--quick', action='store_true', + default=False, help='Do a rough build, with limited warning resolution') +parser.add_option('-s', '--summary', action='store_true', + default=False, help='Show a build summary') +parser.add_option('-S', '--show-sizes', action='store_true', + default=False, help='Show image size variation in summary') +parser.add_option('--step', type='int', + default=1, help='Only build every n commits (0=just first and last)') +parser.add_option('-t', '--test', action='store_true', dest='test', + default=False, help='run tests') +parser.add_option('-T', '--threads', type='int', + default=None, help='Number of builder threads to use') +parser.add_option('-u', '--show_unknown', action='store_true', + default=False, help='Show boards with unknown build result') + +parser.usage = """buildman -b <branch> [options] + +Build U-Boot for all commits in a branch. Use -n to do a dry run""" + +(options, args) = parser.parse_args() + +# Run our meagre tests +if options.test: + RunTests() +elif options.full_help: + pager = os.getenv('PAGER') + if not pager: + pager = 'more' + fname = os.path.join(os.path.dirname(sys.argv[0]), 'README') + command.Run(pager, fname) + +# Build selected commits for selected boards +else: + control.DoBuildman(options, args) diff --git a/tools/buildman/control.py b/tools/buildman/control.py new file mode 100644 index 0000000..8d7b9b5 --- /dev/null +++ b/tools/buildman/control.py @@ -0,0 +1,181 @@ +# Copyright (c) 2013 The Chromium OS Authors. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +import multiprocessing +import os +import sys + +import board +import bsettings +from builder import Builder +import gitutil +import patchstream +import terminal +import toolchain + +def GetPlural(count): + """Returns a plural 's' if count is not 1""" + return 's' if count != 1 else '' + +def GetActionSummary(is_summary, count, selected, options): + """Return a string summarising the intended action. + + Returns: + Summary string. + """ + count = (count + options.step - 1) / options.step + str = '%s %d commit%s for %d boards' % ( + 'Summary of' if is_summary else 'Building', count, GetPlural(count), + len(selected)) + str += ' (%d thread%s, %d job%s per thread)' % (options.threads, + GetPlural(options.threads), options.jobs, GetPlural(options.jobs)) + return str + +def ShowActions(series, why_selected, boards_selected, builder, options): + """Display a list of actions that we would take, if not a dry run. + + Args: + series: Series object + why_selected: Dictionary where each key is a buildman argument + provided by the user, and the value is the boards brought + in by that argument. For example, 'arm' might bring in + 400 boards, so in this case the key would be 'arm' and + the value would be a list of board names. + boards_selected: Dict of selected boards, key is target name, + value is Board object + builder: The builder that will be used to build the commits + options: Command line options object + """ + col = terminal.Color() + print 'Dry run, so not doing much. But I would do this:' + print + print GetActionSummary(False, len(series.commits), boards_selected, + options) + print 'Build directory: %s' % builder.base_dir + for upto in range(0, len(series.commits), options.step): + commit = series.commits[upto] + print ' ', col.Color(col.YELLOW, commit.hash, bright=False), + print commit.subject + print + for arg in why_selected: + if arg != 'all': + print arg, ': %d boards' % why_selected[arg] + print ('Total boards to build for each commit: %d\n' % + why_selected['all']) + +def DoBuildman(options, args): + """The main control code for buildman + + Args: + options: Command line options object + args: Command line arguments (list of strings) + """ + gitutil.Setup() + + bsettings.Setup() + options.git_dir = os.path.join(options.git, '.git') + + toolchains = toolchain.Toolchains() + toolchains.Scan(options.list_tool_chains) + if options.list_tool_chains: + toolchains.List() + print + return + + # Work out how many commits to build. We want to build everything on the + # branch. We also build the upstream commit as a control so we can see + # problems introduced by the first commit on the branch. + col = terminal.Color() + count = options.count + if count == -1: + if not options.branch: + str = 'Please use -b to specify a branch to build' + print col.Color(col.RED, str) + sys.exit(1) + count = gitutil.CountCommitsInBranch(options.git_dir, options.branch) + count += 1 # Build upstream commit also + + if not count: + str = ("No commits found to process in branch '%s': " + "set branch's upstream or use -c flag" % options.branch) + print col.Color(col.RED, str) + sys.exit(1) + + # Work out what subset of the boards we are building + boards = board.Boards() + boards.ReadBoards(os.path.join(options.git, 'boards.cfg')) + why_selected = boards.SelectBoards(args) + selected = boards.GetSelected() + if not len(selected): + print col.Color(col.RED, 'No matching boards found') + sys.exit(1) + + # Read the metadata from the commits. First look at the upstream commit, + # then the ones in the branch. We would like to do something like + # upstream/master~..branch but that isn't possible if upstream/master is + # a merge commit (it will list all the commits that form part of the + # merge) + range_expr = gitutil.GetRangeInBranch(options.git_dir, options.branch) + upstream_commit = gitutil.GetUpstream(options.git_dir, options.branch) + series = patchstream.GetMetaDataForList(upstream_commit, options.git_dir, + 1) + series = patchstream.GetMetaDataForList(range_expr, options.git_dir, None, + series) + + # By default we have one thread per CPU. But if there are not enough jobs + # we can have fewer threads and use a high '-j' value for make. + if not options.threads: + options.threads = min(multiprocessing.cpu_count(), len(selected)) + if not options.jobs: + options.jobs = max(1, (multiprocessing.cpu_count() + + len(selected) - 1) / len(selected)) + + if not options.step: + options.step = len(series.commits) - 1 + + # Create a new builder with the selected options + output_dir = os.path.join('..', options.branch) + builder = Builder(toolchains, output_dir, options.git_dir, + options.threads, options.jobs, checkout=True, + show_unknown=options.show_unknown, step=options.step) + builder.force_config_on_failure = not options.quick + + # For a dry run, just show our actions as a sanity check + if options.dry_run: + ShowActions(series, why_selected, selected, builder, options) + else: + builder.force_build = options.force_build + + # Work out which boards to build + board_selected = boards.GetSelectedDict() + + print GetActionSummary(options.summary, count, board_selected, options) + + if options.summary: + # We can't show function sizes without board details at present + if options.show_bloat: + options.show_detail = True + builder.ShowSummary(series.commits, board_selected, + options.show_errors, options.show_sizes, + options.show_detail, options.show_bloat) + else: + builder.BuildBoards(series.commits, board_selected, + options.show_errors, options.keep_outputs) diff --git a/tools/buildman/test.py b/tools/buildman/test.py new file mode 100644 index 0000000..9330fa5 --- /dev/null +++ b/tools/buildman/test.py @@ -0,0 +1,185 @@ +# +# Copyright (c) 2012 The Chromium OS Authors. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +import os +import shutil +import sys +import tempfile +import time +import unittest + +# Bring in the patman libraries +our_path = os.path.dirname(os.path.realpath(__file__)) +sys.path.append(os.path.join(our_path, '../patman')) + +import board +import bsettings +import builder +import control +import command +import commit +import toolchain + +errors = [ + '''main.c: In function 'main_loop': +main.c:260:6: warning: unused variable 'joe' [-Wunused-variable] +''', + '''main.c: In function 'main_loop': +main.c:295:2: error: 'fred' undeclared (first use in this function) +main.c:295:2: note: each undeclared identifier is reported only once for each function it appears in +make[1]: *** [main.o] Error 1 +make: *** [common/libcommon.o] Error 2 +Make failed +''', + '''main.c: In function 'main_loop': +main.c:280:6: warning: unused variable 'mary' [-Wunused-variable] +''', + '''powerpc-linux-ld: warning: dot moved backwards before `.bss' +powerpc-linux-ld: warning: dot moved backwards before `.bss' +powerpc-linux-ld: u-boot: section .text lma 0xfffc0000 overlaps previous sections +powerpc-linux-ld: u-boot: section .rodata lma 0xfffef3ec overlaps previous sections +powerpc-linux-ld: u-boot: section .reloc lma 0xffffa400 overlaps previous sections +powerpc-linux-ld: u-boot: section .data lma 0xffffcd38 overlaps previous sections +powerpc-linux-ld: u-boot: section .u_boot_cmd lma 0xffffeb40 overlaps previous sections +powerpc-linux-ld: u-boot: section .bootpg lma 0xfffff198 overlaps previous sections +''' +] + + +# hash, subject, return code, list of errors/warnings +commits = [ + ['1234', 'upstream/master, ok', 0, []], + ['5678', 'Second commit, a warning', 0, errors[0:1]], + ['9012', 'Third commit, error', 1, errors[0:2]], + ['3456', 'Fourth commit, warning', 0, [errors[0], errors[2]]], + ['7890', 'Fifth commit, link errors', 1, [errors[0], errors[3]]], + ['abcd', 'Sixth commit, fixes all errors', 0, []] +] + +boards = [ + ['board0', 'arm', 'armv7', 'ARM Board 1', 'Tester', '', ''], + ['board1', 'arm', 'armv7', 'ARM Board 2', 'Tester', '', ''], + ['board2', 'powerpc', 'powerpc', 'PowerPC board 1', 'Tester', '', ''], + ['board3', 'powerpc', 'mpc5xx', 'PowerPC board 2', 'Tester', '', ''], + ['board4', 'sandbox', 'sandbox', 'Sandbox board', 'Tester', '', ''] +] + +class Options: + """Class that holds build options""" + pass + +class TestBuild(unittest.TestCase): + """Test buildman + + TODO: Write tests for the rest of the functionality + """ + def setUp(self): + # Set up commits to build + self.commits = [] + sequence = 0 + for commit_info in commits: + comm = commit.Commit(commit_info[0]) + comm.subject = commit_info[1] + comm.return_code = commit_info[2] + comm.error_list = commit_info[3] + comm.sequence = sequence + sequence += 1 + self.commits.append(comm) + + # Set up boards to build + self.boards = board.Boards() + for brd in boards: + self.boards.AddBoard(board.Board(*brd)) + self.boards.SelectBoards([]) + + # Set up the toolchains + bsettings.Setup() + self.toolchains = toolchain.Toolchains() + self.toolchains.Add('arm-linux-gcc', test=False) + self.toolchains.Add('sparc-linux-gcc', test=False) + self.toolchains.Add('powerpc-linux-gcc', test=False) + self.toolchains.Add('gcc', test=False) + + def Make(self, commit, brd, stage, *args, **kwargs): + result = command.CommandResult() + boardnum = int(brd.target[-1]) + result.return_code = 0 + result.stderr = '' + result.stdout = ('This is the test output for board %s, commit %s' % + (brd.target, commit.hash)) + if boardnum >= 1 and boardnum >= commit.sequence: + result.return_code = commit.return_code + result.stderr = ''.join(commit.error_list) + if stage == 'build': + target_dir = None + for arg in args: + if arg.startswith('O='): + target_dir = arg[2:] + + if not os.path.isdir(target_dir): + os.mkdir(target_dir) + #time.sleep(.2 + boardnum * .2) + + result.combined = result.stdout + result.stderr + return result + + def testBasic(self): + """Test basic builder operation""" + output_dir = tempfile.mkdtemp() + if not os.path.isdir(output_dir): + os.mkdir(output_dir) + build = builder.Builder(self.toolchains, output_dir, None, 1, 2, + checkout=False, show_unknown=False) + build.do_make = self.Make + board_selected = self.boards.GetSelectedDict() + + #build.BuildCommits(self.commits, board_selected, False) + build.BuildBoards(self.commits, board_selected, False, False) + build.ShowSummary(self.commits, board_selected, True, False, + False, False) + + def _testGit(self): + """Test basic builder operation by building a branch""" + base_dir = tempfile.mkdtemp() + if not os.path.isdir(base_dir): + os.mkdir(base_dir) + options = Options() + options.git = os.getcwd() + options.summary = False + options.jobs = None + options.dry_run = False + #options.git = os.path.join(base_dir, 'repo') + options.branch = 'test-buildman' + options.force_build = False + options.list_tool_chains = False + options.count = -1 + options.git_dir = None + options.threads = None + options.show_unknown = False + options.quick = False + options.show_errors = False + options.keep_outputs = False + args = ['tegra20'] + control.DoBuildman(options, args) + +if __name__ == "__main__": + unittest.main() diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py new file mode 100644 index 0000000..e0a6970 --- /dev/null +++ b/tools/buildman/toolchain.py @@ -0,0 +1,185 @@ +# Copyright (c) 2012 The Chromium OS Authors. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +import glob +import os + +import bsettings +import command + +class Toolchain: + """A single toolchain + + Public members: + gcc: Full path to C compiler + path: Directory path containing C compiler + cross: Cross compile string, e.g. 'arm-linux-' + arch: Architecture of toolchain as determined from the first + component of the filename. E.g. arm-linux-gcc becomes arm + """ + + def __init__(self, fname, test, verbose=False): + """Create a new toolchain object. + + Args: + fname: Filename of the gcc component + test: True to run the toolchain to test it + """ + self.gcc = fname + self.path = os.path.dirname(fname) + self.cross = os.path.basename(fname)[:-3] + pos = self.cross.find('-') + self.arch = self.cross[:pos] if pos != -1 else 'sandbox' + + env = self.MakeEnvironment() + + # As a basic sanity check, run the C compiler with --version + cmd = [fname, '--version'] + if test: + result = command.RunPipe([cmd], capture=True, env=env) + self.ok = result.return_code == 0 + if verbose: + print 'Tool chain test: ', + if self.ok: + print 'OK' + else: + print 'BAD' + print 'Command: ', cmd + print result.stdout + print result.stderr + else: + self.ok = True + self.priority = self.GetPriority(fname) + + def GetPriority(self, fname): + """Return the priority of the toolchain. + + Toolchains are ranked according to their suitability by their + filename prefix. + + Args: + fname: Filename of toolchain + Returns: + Priority of toolchain, 0=highest, 20=lowest. + """ + priority_list = ['-elf', '-unknown-linux-gnu', '-linux', '-elf', + '-none-linux-gnueabi', '-uclinux', '-none-eabi', + '-gentoo-linux-gnu', '-linux-gnueabi', '-le-linux', '-uclinux'] + for prio in range(len(priority_list)): + if priority_list[prio] in fname: + return prio + return prio + + def MakeEnvironment(self): + """Returns an environment for using the toolchain. + + Thie takes the current environment, adds CROSS_COMPILE and + augments PATH so that the toolchain will operate correctly. + """ + env = dict(os.environ) + env['CROSS_COMPILE'] = self.cross + env['PATH'] += (':' + self.path) + return env + + +class Toolchains: + """Manage a list of toolchains for building U-Boot + + We select one toolchain for each architecture type + + Public members: + toolchains: Dict of Toolchain objects, keyed by architecture name + paths: List of paths to check for toolchains (may contain wildcards) + """ + + def __init__(self): + self.toolchains = {} + self.paths = [] + for name, value in bsettings.GetItems('toolchain'): + if '*' in value: + self.paths += glob.glob(value) + else: + self.paths.append(value) + + + def Add(self, fname, test=True, verbose=False): + """Add a toolchain to our list + + We select the given toolchain as our preferred one for its + architecture if it is a higher priority than the others. + + Args: + fname: Filename of toolchain's gcc driver + test: True to run the toolchain to test it + """ + toolchain = Toolchain(fname, test, verbose) + add_it = toolchain.ok + if toolchain.arch in self.toolchains: + add_it = (toolchain.priority < + self.toolchains[toolchain.arch].priority) + if add_it: + self.toolchains[toolchain.arch] = toolchain + + def Scan(self, verbose): + """Scan for available toolchains and select the best for each arch. + + We look for all the toolchains we can file, figure out the + architecture for each, and whether it works. Then we select the + highest priority toolchain for each arch. + + Args: + verbose: True to print out progress information + """ + if verbose: print 'Scanning for tool chains' + for path in self.paths: + if verbose: print " - scanning path '%s'" % path + for subdir in ['.', 'bin', 'usr/bin']: + dirname = os.path.join(path, subdir) + if verbose: print " - looking in '%s'" % dirname + for fname in glob.glob(dirname + '/*gcc'): + if verbose: print " - found '%s'" % fname + self.Add(fname, True, verbose) + + def List(self): + """List out the selected toolchains for each architecture""" + print 'List of available toolchains (%d):' % len(self.toolchains) + if len(self.toolchains): + for key, value in sorted(self.toolchains.iteritems()): + print '%-10s: %s' % (key, value.gcc) + else: + print 'None' + + def Select(self, arch): + """Returns the toolchain for a given architecture + + Args: + args: Name of architecture (e.g. 'arm', 'ppc_8xx') + + returns: + toolchain object, or None if none found + """ + for name, value in bsettings.GetItems('toolchain-alias'): + if arch == name: + arch = value + + if not arch in self.toolchains: + raise ValueError, ("No tool chain found for arch '%s'" % arch) + return self.toolchains[arch] diff --git a/tools/checkpatch.pl b/tools/checkpatch.pl index c7475f9..9f23901 100755 --- a/tools/checkpatch.pl +++ b/tools/checkpatch.pl @@ -33,6 +33,7 @@ my %ignore_type = (); my @ignore = (); my $help = 0; my $configuration_file = ".checkpatch.conf"; +my $max_line_length = 80; sub help { my ($exitcode) = @_; @@ -51,6 +52,7 @@ Options: -f, --file treat FILE as regular source file --subjective, --strict enable more subjective tests --ignore TYPE(,TYPE2...) ignore various comma separated message types + --max-line-length=n set the maximum line length, if exceeded, warn --show-types show the message "types" in the output --root=PATH PATH to the kernel tree root --no-summary suppress the per-file summary @@ -107,6 +109,7 @@ GetOptions( 'strict!' => \$check, 'ignore=s' => \@ignore, 'show-types!' => \$show_types, + 'max-line-length=i' => \$max_line_length, 'root=s' => \$root, 'summary!' => \$summary, 'mailback!' => \$mailback, @@ -227,8 +230,12 @@ our $Inline = qr{inline|__always_inline|noinline}; our $Member = qr{->$Ident|\.$Ident|\[[^]]*\]}; our $Lval = qr{$Ident(?:$Member)*}; -our $Constant = qr{(?:[0-9]+|0x[0-9a-fA-F]+)[UL]*}; -our $Assignment = qr{(?:\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=)}; +our $Float_hex = qr{(?i)0x[0-9a-f]+p-?[0-9]+[fl]?}; +our $Float_dec = qr{(?i)(?:[0-9]+\.[0-9]*|[0-9]*\.[0-9]+)(?:e-?[0-9]+)?[fl]?}; +our $Float_int = qr{(?i)[0-9]+e-?[0-9]+[fl]?}; +our $Float = qr{$Float_hex|$Float_dec|$Float_int}; +our $Constant = qr{$Float|(?i)(?:0x[0-9a-f]+|[0-9]+)[ul]*}; +our $Assignment = qr{\*\=|/=|%=|\+=|-=|<<=|>>=|&=|\^=|\|=|=}; our $Compare = qr{<=|>=|==|!=|<|>}; our $Operators = qr{ <=|>=|==|!=| @@ -240,9 +247,8 @@ our $NonptrType; our $Type; our $Declare; -our $UTF8 = qr { - [\x09\x0A\x0D\x20-\x7E] # ASCII - | [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte +our $NON_ASCII_UTF8 = qr{ + [\xC2-\xDF][\x80-\xBF] # non-overlong 2-byte | \xE0[\xA0-\xBF][\x80-\xBF] # excluding overlongs | [\xE1-\xEC\xEE\xEF][\x80-\xBF]{2} # straight 3-byte | \xED[\x80-\x9F][\x80-\xBF] # excluding surrogates @@ -251,6 +257,11 @@ our $UTF8 = qr { | \xF4[\x80-\x8F][\x80-\xBF]{2} # plane 16 }x; +our $UTF8 = qr{ + [\x09\x0A\x0D\x20-\x7E] # ASCII + | $NON_ASCII_UTF8 +}x; + our $typeTypedefs = qr{(?x: (?:__)?(?:u|s|be|le)(?:8|16|32|64)| atomic_t @@ -261,6 +272,7 @@ our $logFunctions = qr{(?x: [a-z0-9]+_(?:printk|emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)(?:_ratelimited|_once|)| WARN(?:_RATELIMIT|_ONCE|)| panic| + debug| MODULE_[A-Z_]+ )}; @@ -311,7 +323,7 @@ sub build_types { $NonptrType = qr{ (?:$Modifier\s+|const\s+)* (?: - (?:typeof|__typeof__)\s*\(\s*\**\s*$Ident\s*\)| + (?:typeof|__typeof__)\s*\([^\)]*\)| (?:$typeTypedefs\b)| (?:${all}\b) ) @@ -319,17 +331,23 @@ sub build_types { }x; $Type = qr{ $NonptrType - (?:[\s\*]+\s*const|[\s\*]+|(?:\s*\[\s*\])+)? + (?:(?:\s|\*|\[\])+\s*const|(?:\s|\*|\[\])+|(?:\s*\[\s*\])+)? (?:\s+$Inline|\s+$Modifier)* }x; $Declare = qr{(?:$Storage\s+)?$Type}; } build_types(); -our $match_balanced_parentheses = qr/(\((?:[^\(\)]+|(-1))*\))/; our $Typecast = qr{\s*(\(\s*$NonptrType\s*\)){0,1}\s*}; -our $LvalOrFunc = qr{($Lval)\s*($match_balanced_parentheses{0,1})\s*}; + +# Using $balanced_parens, $LvalOrFunc, or $FuncArg +# requires at least perl version v5.10.0 +# Any use must be runtime checked with $^V + +our $balanced_parens = qr/(\((?:[^\(\)]++|(?-1))*\))/; +our $LvalOrFunc = qr{($Lval)\s*($balanced_parens{0,1})\s*}; +our $FuncArg = qr{$Typecast{0,1}($LvalOrFunc|$Constant)}; sub deparenthesize { my ($string) = @_; @@ -342,27 +360,6 @@ sub deparenthesize { $chk_signoff = 0 if ($file); -my @dep_includes = (); -my @dep_functions = (); -my $removal = "Documentation/feature-removal-schedule.txt"; -if ($tree && -f "$root/$removal") { - open(my $REMOVE, '<', "$root/$removal") || - die "$P: $removal: open failed - $!\n"; - while (<$REMOVE>) { - if (/^Check:\s+(.*\S)/) { - for my $entry (split(/[, ]+/, $1)) { - if ($entry =~ m@include/(.*)@) { - push(@dep_includes, $1); - - } elsif ($entry !~ m@/@) { - push(@dep_functions, $entry); - } - } - } - } - close($REMOVE); -} - my @rawlines = (); my @lines = (); my $vname; @@ -411,7 +408,7 @@ sub top_of_kernel_tree { } } return 1; - } +} sub parse_email { my ($formatted_email) = @_; @@ -672,6 +669,10 @@ sub ctx_statement_block { if ($off >= $len) { last; } + if ($level == 0 && substr($blk, $off) =~ /^.\s*#\s*define/) { + $level++; + $type = '#'; + } } $p = $c; $c = substr($blk, $off, 1); @@ -734,6 +735,13 @@ sub ctx_statement_block { last; } } + # Preprocessor commands end at the newline unless escaped. + if ($type eq '#' && $c eq "\n" && $p ne "\\") { + $level--; + $type = ''; + $off++; + last; + } $off++; } # We are truly at the end, so shuffle to the next line. @@ -1016,7 +1024,7 @@ sub annotate_values { } elsif ($cur =~ /^(\(\s*$Type\s*)\)/ && $av_pending eq '_') { print "CAST($1)\n" if ($dbg_values > 1); push(@av_paren_type, $type); - $type = 'C'; + $type = 'c'; } elsif ($cur =~ /^($Type)\s*(?:$Ident|,|\)|\(|\s*$)/) { print "DECLARE($1)\n" if ($dbg_values > 1); @@ -1208,7 +1216,9 @@ sub possible { case| else| asm|__asm__| - do + do| + \#| + \#\#| )(?:\s|$)| ^(?:typedef|struct|enum)\b )}x; @@ -1312,6 +1322,36 @@ sub check_absolute_file { } } +sub pos_last_openparen { + my ($line) = @_; + + my $pos = 0; + + my $opens = $line =~ tr/\(/\(/; + my $closes = $line =~ tr/\)/\)/; + + my $last_openparen = 0; + + if (($opens == 0) || ($closes >= $opens)) { + return -1; + } + + my $len = length($line); + + for ($pos = 0; $pos < $len; $pos++) { + my $string = substr($line, $pos); + if ($string =~ /^($FuncArg|$balanced_parens)/) { + $pos += length($1) - 1; + } elsif (substr($line, $pos, 1) eq '(') { + $last_openparen = $pos; + } elsif (index($string, '(') == -1) { + last; + } + } + + return $last_openparen + 1; +} + sub process { my $filename = shift; @@ -1330,6 +1370,11 @@ sub process { my $signoff = 0; my $is_patch = 0; + my $in_header_lines = 1; + my $in_commit_log = 0; #Scanning lines before patch + + my $non_utf8_charset = 0; + our @report = (); our $cnt_lines = 0; our $cnt_error = 0; @@ -1352,6 +1397,9 @@ sub process { my %suppress_ifbraces; my %suppress_whiletrailers; my %suppress_export; + my $suppress_statement = 0; + + my %camelcase = (); # Pre-scan the patch sanitizing the lines. # Pre-scan the patch looking for any __setup documentation. @@ -1461,6 +1509,7 @@ sub process { %suppress_ifbraces = (); %suppress_whiletrailers = (); %suppress_export = (); + $suppress_statement = 0; next; # track the line number as we move through the hunk, note that @@ -1497,10 +1546,11 @@ sub process { if ($line =~ /^diff --git.*?(\S+)$/) { $realfile = $1; $realfile =~ s@^([^/]*)/@@; - + $in_commit_log = 0; } elsif ($line =~ /^\+\+\+\s+(\S+)/) { $realfile = $1; $realfile =~ s@^([^/]*)/@@; + $in_commit_log = 0; $p1_prefix = $1; if (!$file && $tree && $p1_prefix ne '' && @@ -1536,16 +1586,22 @@ sub process { # Check the patch for a signoff: if ($line =~ /^\s*signed-off-by:/i) { $signoff++; + $in_commit_log = 0; } # Check signature styles - if ($line =~ /^(\s*)($signature_tags)(\s*)(.*)/) { + if (!$in_header_lines && + $line =~ /^(\s*)([a-z0-9_-]+by:|$signature_tags)(\s*)(.*)/i) { my $space_before = $1; my $sign_off = $2; my $space_after = $3; my $email = $4; my $ucfirst_sign_off = ucfirst(lc($sign_off)); + if ($sign_off !~ /$signature_tags/) { + WARN("BAD_SIGN_OFF", + "Non-standard signature: $sign_off\n" . $herecurr); + } if (defined $space_before && $space_before ne "") { WARN("BAD_SIGN_OFF", "Do not use whitespace before $ucfirst_sign_off\n" . $herecurr); @@ -1613,6 +1669,28 @@ sub process { "Invalid UTF-8, patch and commit message should be encoded in UTF-8\n" . $hereptr); } +# Check if it's the start of a commit log +# (not a header line and we haven't seen the patch filename) + if ($in_header_lines && $realfile =~ /^$/ && + $rawline !~ /^(commit\b|from\b|[\w-]+:).+$/i) { + $in_header_lines = 0; + $in_commit_log = 1; + } + +# Check if there is UTF-8 in a commit log when a mail header has explicitly +# declined it, i.e defined some charset where it is missing. + if ($in_header_lines && + $rawline =~ /^Content-Type:.+charset="(.+)".*$/ && + $1 !~ /utf-8/i) { + $non_utf8_charset = 1; + } + + if ($in_commit_log && $non_utf8_charset && $realfile =~ /^$/ && + $rawline =~ /$NON_ASCII_UTF8/) { + WARN("UTF8_BEFORE_PATCH", + "8-bit UTF-8 used in possible commit log\n" . $herecurr); + } + # ignore non-hunk lines and lines being removed next if (!$hunk_line || $line =~ /^-/); @@ -1633,19 +1711,26 @@ sub process { # Only applies when adding the entry originally, after that we do not have # sufficient context to determine whether it is indeed long enough. if ($realfile =~ /Kconfig/ && - $line =~ /\+\s*(?:---)?help(?:---)?$/) { + $line =~ /.\s*config\s+/) { my $length = 0; my $cnt = $realcnt; my $ln = $linenr + 1; my $f; + my $is_start = 0; my $is_end = 0; - while ($cnt > 0 && defined $lines[$ln - 1]) { + for (; $cnt > 0 && defined $lines[$ln - 1]; $ln++) { $f = $lines[$ln - 1]; $cnt-- if ($lines[$ln - 1] !~ /^-/); $is_end = $lines[$ln - 1] =~ /^\+/; - $ln++; next if ($f =~ /^-/); + + if ($lines[$ln - 1] =~ /.\s*(?:bool|tristate)\s*\"/) { + $is_start = 1; + } elsif ($lines[$ln - 1] =~ /.\s*(?:---)?help(?:---)?$/) { + $length = -1; + } + $f =~ s/^.//; $f =~ s/#.*//; $f =~ s/^\s+//; @@ -1657,22 +1742,58 @@ sub process { $length++; } WARN("CONFIG_DESCRIPTION", - "please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_end && $length < 4); - #print "is_end<$is_end> length<$length>\n"; + "please write a paragraph that describes the config symbol fully\n" . $herecurr) if ($is_start && $is_end && $length < 4); + #print "is_start<$is_start> is_end<$is_end> length<$length>\n"; + } + +# discourage the addition of CONFIG_EXPERIMENTAL in Kconfig. + if ($realfile =~ /Kconfig/ && + $line =~ /.\s*depends on\s+.*\bEXPERIMENTAL\b/) { + WARN("CONFIG_EXPERIMENTAL", + "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n"); + } + + if (($realfile =~ /Makefile.*/ || $realfile =~ /Kbuild.*/) && + ($line =~ /\+(EXTRA_[A-Z]+FLAGS).*/)) { + my $flag = $1; + my $replacement = { + 'EXTRA_AFLAGS' => 'asflags-y', + 'EXTRA_CFLAGS' => 'ccflags-y', + 'EXTRA_CPPFLAGS' => 'cppflags-y', + 'EXTRA_LDFLAGS' => 'ldflags-y', + }; + + WARN("DEPRECATED_VARIABLE", + "Use of $flag is deprecated, please use \`$replacement->{$flag} instead.\n" . $herecurr) if ($replacement->{$flag}); } # check we are in a valid source file if not then ignore this hunk next if ($realfile !~ /\.(h|c|s|S|pl|sh)$/); -#80 column limit +#line length limit if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ && $rawline !~ /^.\s*\*\s*\@$Ident\s/ && !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:|,|\)\s*;)\s*$/ || $line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) && - $length > 80) + $length > $max_line_length) { WARN("LONG_LINE", - "line over 80 characters\n" . $herecurr); + "line over $max_line_length characters\n" . $herecurr); + } + +# Check for user-visible strings broken across lines, which breaks the ability +# to grep for the string. Limited to strings used as parameters (those +# following an open parenthesis), which almost completely eliminates false +# positives, as well as warning only once per parameter rather than once per +# line of the string. Make an exception when the previous string ends in a +# newline (multiple lines in one string constant) or \n\t (common in inline +# assembly to indent the instruction on the following line). + if ($line =~ /^\+\s*"/ && + $prevline =~ /"\s*$/ && + $prevline =~ /\(/ && + $prevrawline !~ /\\n(?:\\t)*"\s*$/) { + WARN("SPLIT_STRING", + "quoted string split across lines\n" . $hereprev); } # check for spaces before a quoted newline @@ -1721,6 +1842,58 @@ sub process { "please, no space before tabs\n" . $herevet); } +# check for && or || at the start of a line + if ($rawline =~ /^\+\s*(&&|\|\|)/) { + CHK("LOGICAL_CONTINUATIONS", + "Logical continuations should be on the previous line\n" . $hereprev); + } + +# check multi-line statement indentation matches previous line + if ($^V && $^V ge 5.10.0 && + $prevline =~ /^\+(\t*)(if \(|$Ident\().*(\&\&|\|\||,)\s*$/) { + $prevline =~ /^\+(\t*)(.*)$/; + my $oldindent = $1; + my $rest = $2; + + my $pos = pos_last_openparen($rest); + if ($pos >= 0) { + $line =~ /^(\+| )([ \t]*)/; + my $newindent = $2; + + my $goodtabindent = $oldindent . + "\t" x ($pos / 8) . + " " x ($pos % 8); + my $goodspaceindent = $oldindent . " " x $pos; + + if ($newindent ne $goodtabindent && + $newindent ne $goodspaceindent) { + CHK("PARENTHESIS_ALIGNMENT", + "Alignment should match open parenthesis\n" . $hereprev); + } + } + } + + if ($line =~ /^\+.*\*[ \t]*\)[ \t]+/) { + CHK("SPACING", + "No space is necessary after a cast\n" . $hereprev); + } + + if ($realfile =~ m@^(drivers/net/|net/)@ && + $rawline =~ /^\+[ \t]*\/\*[ \t]*$/ && + $prevrawline =~ /^\+[ \t]*$/) { + WARN("NETWORKING_BLOCK_COMMENT_STYLE", + "networking block comments don't use an empty /* line, use /* Comment...\n" . $hereprev); + } + + if ($realfile =~ m@^(drivers/net/|net/)@ && + $rawline !~ m@^\+[ \t]*\*/[ \t]*$@ && #trailing */ + $rawline !~ m@^\+.*/\*.*\*/[ \t]*$@ && #inline /*...*/ + $rawline !~ m@^\+.*\*{2,}/[ \t]*$@ && #trailing **/ + $rawline =~ m@^\+[ \t]*.+\*\/[ \t]*$@) { #non blank */ + WARN("NETWORKING_BLOCK_COMMENT_STYLE", + "networking block comments put the trailing */ on a separate line\n" . $herecurr); + } + # check for spaces at the beginning of a line. # Exceptions: # 1) within comments @@ -1735,6 +1908,12 @@ sub process { # check we are in a valid C source file if not then ignore this hunk next if ($realfile !~ /\.(h|c)$/); +# discourage the addition of CONFIG_EXPERIMENTAL in #if(def). + if ($line =~ /^\+\s*\#\s*if.*\bCONFIG_EXPERIMENTAL\b/) { + WARN("CONFIG_EXPERIMENTAL", + "Use of CONFIG_EXPERIMENTAL is deprecated. For alternatives, see https://lkml.org/lkml/2012/10/23/580\n"); + } + # check for RCS/CVS revision markers if ($rawline =~ /^\+.*\$(Revision|Log|Id)(?:\$|)/) { WARN("CVS_KEYWORD", @@ -1753,15 +1932,33 @@ sub process { "use the SSYNC() macro in asm/blackfin.h\n" . $herevet); } +# check for old HOTPLUG __dev<foo> section markings + if ($line =~ /\b(__dev(init|exit)(data|const|))\b/) { + WARN("HOTPLUG_SECTION", + "Using $1 is unnecessary\n" . $herecurr); + } + # Check for potential 'bare' types my ($stat, $cond, $line_nr_next, $remain_next, $off_next, $realline_next); - if ($realcnt && $line =~ /.\s*\S/) { +#print "LINE<$line>\n"; + if ($linenr >= $suppress_statement && + $realcnt && $line =~ /.\s*\S/) { ($stat, $cond, $line_nr_next, $remain_next, $off_next) = ctx_statement_block($linenr, $realcnt, 0); $stat =~ s/\n./\n /g; $cond =~ s/\n./\n /g; +#print "linenr<$linenr> <$stat>\n"; + # If this statement has no statement boundaries within + # it there is no point in retrying a statement scan + # until we hit end of it. + my $frag = $stat; $frag =~ s/;+\s*$//; + if ($frag !~ /(?:{|;)/) { +#print "skip<$line_nr_next>\n"; + $suppress_statement = $line_nr_next; + } + # Find the real next line. $realline_next = $line_nr_next; if (defined $realline_next && @@ -1850,6 +2047,12 @@ sub process { my $pre_ctx = "$1$2"; my ($level, @ctx) = ctx_statement_level($linenr, $realcnt, 0); + + if ($line =~ /^\+\t{6,}/) { + WARN("DEEP_INDENTATION", + "Too many leading tabs - consider code refactoring\n" . $herecurr); + } + my $ctx_cnt = $realcnt - $#ctx - 1; my $ctx = join("\n", @ctx); @@ -1887,6 +2090,9 @@ sub process { # Check relative indent for conditionals and blocks. if ($line =~ /\b(?:(?:if|while|for)\s*\(|do\b)/ && $line !~ /^.\s*#/ && $line !~ /\}\s*while\s*/) { + ($stat, $cond, $line_nr_next, $remain_next, $off_next) = + ctx_statement_block($linenr, $realcnt, 0) + if (!defined $stat); my ($s, $c) = ($stat, $cond); substr($s, 0, length($c), ''); @@ -2027,8 +2233,11 @@ sub process { my $path = $1; if ($path =~ m{//}) { ERROR("MALFORMED_INCLUDE", - "malformed #include filename\n" . - $herecurr); + "malformed #include filename\n" . $herecurr); + } + if ($path =~ "^uapi/" && $realfile =~ m@\binclude/uapi/@) { + ERROR("UAPI_INCLUDE", + "No #include in ...include/uapi/... should use a uapi/ path prefix\n" . $herecurr); } } @@ -2054,7 +2263,7 @@ sub process { # XXX(foo); # EXPORT_SYMBOL(something_foo); my $name = $1; - if ($stat =~ /^.([A-Z_]+)\s*\(\s*($Ident)/ && + if ($stat =~ /^(?:.\s*}\s*\n)?.([A-Z_]+)\s*\(\s*($Ident)/ && $name =~ /^${Ident}_$2/) { #print "FOO C name<$name>\n"; $suppress_export{$realline_next} = 1; @@ -2132,8 +2341,9 @@ sub process { # * goes on variable not on type # (char*[ const]) - if ($line =~ m{\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\)}) { - my ($from, $to) = ($1, $1); + while ($line =~ m{(\($NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)\))}g) { + #print "AA<$1>\n"; + my ($from, $to) = ($2, $2); # Should start with a space. $to =~ s/^(\S)/ $1/; @@ -2148,8 +2358,10 @@ sub process { ERROR("POINTER_LOCATION", "\"(foo$from)\" should be \"(foo$to)\"\n" . $herecurr); } - } elsif ($line =~ m{\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident)}) { - my ($from, $to, $ident) = ($1, $1, $2); + } + while ($line =~ m{(\b$NonptrType(\s*(?:$Modifier\b\s*|\*\s*)+)($Ident))}g) { + #print "BB<$1>\n"; + my ($from, $to, $ident) = ($2, $2, $3); # Should start with a space. $to =~ s/^(\S)/ $1/; @@ -2210,6 +2422,30 @@ sub process { } } + if ($line =~ /\bprintk\s*\(\s*KERN_([A-Z]+)/) { + my $orig = $1; + my $level = lc($orig); + $level = "warn" if ($level eq "warning"); + my $level2 = $level; + $level2 = "dbg" if ($level eq "debug"); + WARN("PREFER_PR_LEVEL", + "Prefer netdev_$level2(netdev, ... then dev_$level2(dev, ... then pr_$level(... to printk(KERN_$orig ...\n" . $herecurr); + } + + if ($line =~ /\bpr_warning\s*\(/) { + WARN("PREFER_PR_LEVEL", + "Prefer pr_warn(... to pr_warning(...\n" . $herecurr); + } + + if ($line =~ /\bdev_printk\s*\(\s*KERN_([A-Z]+)/) { + my $orig = $1; + my $level = lc($orig); + $level = "warn" if ($level eq "warning"); + $level = "dbg" if ($level eq "debug"); + WARN("PREFER_DEV_LEVEL", + "Prefer dev_$level(... to dev_printk(KERN_$orig, ...\n" . $herecurr); + } + # function brace can't be on same line, except for #defines of do while, # or if closed on same line if (($line=~/$Type\s*$Ident\(.*\).*\s{/) and @@ -2239,7 +2475,7 @@ sub process { my ($where, $prefix) = ($-[1], $1); if ($prefix !~ /$Type\s+$/ && ($where != 0 || $prefix !~ /^.\s+$/) && - $prefix !~ /{\s+$/) { + $prefix !~ /[{,]\s+$/) { ERROR("BRACKET_SPACE", "space prohibited before open square bracket '['\n" . $herecurr); } @@ -2276,6 +2512,13 @@ sub process { "space prohibited between function name and open parenthesis '('\n" . $herecurr); } } + +# check for whitespace before a non-naked semicolon + if ($line =~ /^\+.*\S\s+;/) { + CHK("SPACING", + "space prohibited before semicolon\n" . $herecurr); + } + # Check operator spacing. if (!($line=~/\#\s*include/)) { my $ops = qr{ @@ -2532,7 +2775,7 @@ sub process { # Flatten any parentheses $value =~ s/\(/ \(/g; $value =~ s/\)/\) /g; - while ($value =~ s/\[[^\{\}]*\]/1/ || + while ($value =~ s/\[[^\[\]]*\]/1/ || $value !~ /(?:$Ident|-?$Constant)\s* $Compare\s* (?:$Ident|-?$Constant)/x && @@ -2557,28 +2800,6 @@ sub process { } } -# typecasts on min/max could be min_t/max_t - if ($line =~ /^\+(?:.*?)\b(min|max)\s*\($Typecast{0,1}($LvalOrFunc)\s*,\s*$Typecast{0,1}($LvalOrFunc)\s*\)/) { - if (defined $2 || defined $8) { - my $call = $1; - my $cast1 = deparenthesize($2); - my $arg1 = $3; - my $cast2 = deparenthesize($8); - my $arg2 = $9; - my $cast; - - if ($cast1 ne "" && $cast2 ne "") { - $cast = "$cast1 or $cast2"; - } elsif ($cast1 ne "") { - $cast = $cast1; - } else { - $cast = $cast2; - } - WARN("MINMAX", - "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . $herecurr); - } - } - # Need a space before open parenthesis after if, while etc if ($line=~/\b(if|while|for|switch)\(/) { ERROR("SPACING", "space required before the open parenthesis '('\n" . $herecurr); @@ -2587,6 +2808,9 @@ sub process { # Check for illegal assignment in if conditional -- and check for trailing # statements after the conditional. if ($line =~ /do\s*(?!{)/) { + ($stat, $cond, $line_nr_next, $remain_next, $off_next) = + ctx_statement_block($linenr, $realcnt, 0) + if (!defined $stat); my ($stat_next) = ctx_statement_block($line_nr_next, $remain_next, $off_next); $stat_next =~ s/\n./\n /g; @@ -2702,12 +2926,18 @@ sub process { } } -#studly caps, commented out until figure out how to distinguish between use of existing and adding new -# if (($line=~/[\w_][a-z\d]+[A-Z]/) and !($line=~/print/)) { -# print "No studly caps, use _\n"; -# print "$herecurr"; -# $clean = 0; -# } +#CamelCase + while ($line =~ m{($Constant|$Lval)}g) { + my $var = $1; + if ($var !~ /$Constant/ && + $var =~ /[A-Z]\w*[a-z]|[a-z]\w*[A-Z]/ && + $var !~ /"^(?:Clear|Set|TestClear|TestSet|)Page[A-Z]/ && + !defined $camelcase{$var}) { + $camelcase{$var} = 1; + WARN("CAMELCASE", + "Avoid CamelCase: <$var>\n" . $herecurr); + } + } #no spaces allowed after \ in define if ($line=~/\#\s*define.*\\\s$/) { @@ -2742,47 +2972,13 @@ sub process { my $cnt = $realcnt; my ($off, $dstat, $dcond, $rest); my $ctx = ''; - - my $args = defined($1); - - # Find the end of the macro and limit our statement - # search to that. - while ($cnt > 0 && defined $lines[$ln - 1] && - $lines[$ln - 1] =~ /^(?:-|..*\\$)/) - { - $ctx .= $rawlines[$ln - 1] . "\n"; - $cnt-- if ($lines[$ln - 1] !~ /^-/); - $ln++; - } - $ctx .= $rawlines[$ln - 1]; - ($dstat, $dcond, $ln, $cnt, $off) = - ctx_statement_block($linenr, $ln - $linenr + 1, 0); + ctx_statement_block($linenr, $realcnt, 0); + $ctx = $dstat; #print "dstat<$dstat> dcond<$dcond> cnt<$cnt> off<$off>\n"; #print "LINE<$lines[$ln-1]> len<" . length($lines[$ln-1]) . "\n"; - # Extract the remainder of the define (if any) and - # rip off surrounding spaces, and trailing \'s. - $rest = ''; - while ($off != 0 || ($cnt > 0 && $rest =~ /\\\s*$/)) { - #print "ADDING cnt<$cnt> $off <" . substr($lines[$ln - 1], $off) . "> rest<$rest>\n"; - if ($off != 0 || $lines[$ln - 1] !~ /^-/) { - $rest .= substr($lines[$ln - 1], $off) . "\n"; - $cnt--; - } - $ln++; - $off = 0; - } - $rest =~ s/\\\n.//g; - $rest =~ s/^\s*//s; - $rest =~ s/\s*$//s; - - # Clean up the original statement. - if ($args) { - substr($dstat, 0, length($dcond), ''); - } else { - $dstat =~ s/^.\s*\#\s*define\s+$Ident\s*//; - } + $dstat =~ s/^.\s*\#\s*define\s+$Ident(?:\([^\)]*\))?\s*//; $dstat =~ s/$;//g; $dstat =~ s/\\\n.//g; $dstat =~ s/^\s*//s; @@ -2791,14 +2987,20 @@ sub process { # Flatten any parentheses and braces while ($dstat =~ s/\([^\(\)]*\)/1/ || $dstat =~ s/\{[^\{\}]*\}/1/ || - $dstat =~ s/\[[^\{\}]*\]/1/) + $dstat =~ s/\[[^\[\]]*\]/1/) + { + } + + # Flatten any obvious string concatentation. + while ($dstat =~ s/("X*")\s*$Ident/$1/ || + $dstat =~ s/$Ident\s*("X*")/$1/) { } my $exceptions = qr{ $Declare| module_param_named| - MODULE_PARAM_DESC| + MODULE_PARM_DESC| DECLARE_PER_CPU| DEFINE_PER_CPU| __typeof__\(| @@ -2808,23 +3010,84 @@ sub process { ^\"|\"$ }x; #print "REST<$rest> dstat<$dstat> ctx<$ctx>\n"; - if ($rest ne '' && $rest ne ',') { - if ($rest !~ /while\s*\(/ && - $dstat !~ /$exceptions/) - { - ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE", - "Macros with multiple statements should be enclosed in a do - while loop\n" . "$here\n$ctx\n"); + if ($dstat ne '' && + $dstat !~ /^(?:$Ident|-?$Constant),$/ && # 10, // foo(), + $dstat !~ /^(?:$Ident|-?$Constant);$/ && # foo(); + $dstat !~ /^[!~-]?(?:$Ident|$Constant)$/ && # 10 // foo() // !foo // ~foo // -foo + $dstat !~ /^'X'$/ && # character constants + $dstat !~ /$exceptions/ && + $dstat !~ /^\.$Ident\s*=/ && # .foo = + $dstat !~ /^do\s*$Constant\s*while\s*$Constant;?$/ && # do {...} while (...); // do {...} while (...) + $dstat !~ /^for\s*$Constant$/ && # for (...) + $dstat !~ /^for\s*$Constant\s+(?:$Ident|-?$Constant)$/ && # for (...) bar() + $dstat !~ /^do\s*{/ && # do {... + $dstat !~ /^\({/) # ({... + { + $ctx =~ s/\n*$//; + my $herectx = $here . "\n"; + my $cnt = statement_rawlines($ctx); + + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; } - } elsif ($ctx !~ /;/) { - if ($dstat ne '' && - $dstat !~ /^(?:$Ident|-?$Constant)$/ && - $dstat !~ /$exceptions/ && - $dstat !~ /^\.$Ident\s*=/ && - $dstat =~ /$Operators/) - { + if ($dstat =~ /;/) { + ERROR("MULTISTATEMENT_MACRO_USE_DO_WHILE", + "Macros with multiple statements should be enclosed in a do - while loop\n" . "$herectx"); + } else { ERROR("COMPLEX_MACRO", - "Macros with complex values should be enclosed in parenthesis\n" . "$here\n$ctx\n"); + "Macros with complex values should be enclosed in parenthesis\n" . "$herectx"); + } + } + +# check for line continuations outside of #defines, preprocessor #, and asm + + } else { + if ($prevline !~ /^..*\\$/ && + $line !~ /^\+\s*\#.*\\$/ && # preprocessor + $line !~ /^\+.*\b(__asm__|asm)\b.*\\$/ && # asm + $line =~ /^\+.*\\$/) { + WARN("LINE_CONTINUATIONS", + "Avoid unnecessary line continuations\n" . $herecurr); + } + } + +# do {} while (0) macro tests: +# single-statement macros do not need to be enclosed in do while (0) loop, +# macro should not end with a semicolon + if ($^V && $^V ge 5.10.0 && + $realfile !~ m@/vmlinux.lds.h$@ && + $line =~ /^.\s*\#\s*define\s+$Ident(\()?/) { + my $ln = $linenr; + my $cnt = $realcnt; + my ($off, $dstat, $dcond, $rest); + my $ctx = ''; + ($dstat, $dcond, $ln, $cnt, $off) = + ctx_statement_block($linenr, $realcnt, 0); + $ctx = $dstat; + + $dstat =~ s/\\\n.//g; + + if ($dstat =~ /^\+\s*#\s*define\s+$Ident\s*${balanced_parens}\s*do\s*{(.*)\s*}\s*while\s*\(\s*0\s*\)\s*([;\s]*)\s*$/) { + my $stmts = $2; + my $semis = $3; + + $ctx =~ s/\n*$//; + my $cnt = statement_rawlines($ctx); + my $herectx = $here . "\n"; + + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; + } + + if (($stmts =~ tr/;/;/) == 1 && + $stmts !~ /^\s*(if|while|for|switch)\b/) { + WARN("SINGLE_STATEMENT_DO_WHILE_MACRO", + "Single statement macros should not use a do {} while (0) loop\n" . "$herectx"); + } + if (defined $semis && $semis ne "") { + WARN("DO_WHILE_MACRO_WITH_TRAILING_SEMICOLON", + "do {} while (0) macros should not be semicolon terminated\n" . "$herectx"); } } } @@ -2846,7 +3109,8 @@ sub process { #print "chunks<$#chunks> linenr<$linenr> endln<$endln> level<$level>\n"; #print "APW: <<$chunks[1][0]>><<$chunks[1][1]>>\n"; if ($#chunks > 0 && $level == 0) { - my $allowed = 0; + my @allowed = (); + my $allow = 0; my $seen = 0; my $herectx = $here . "\n"; my $ln = $linenr - 1; @@ -2857,6 +3121,7 @@ sub process { my ($whitespace) = ($cond =~ /^((?:\s*\n[+-])*\s*)/s); my $offset = statement_rawlines($whitespace) - 1; + $allowed[$allow] = 0; #print "COND<$cond> whitespace<$whitespace> offset<$offset>\n"; # We have looked at and allowed this specific line. @@ -2869,23 +3134,34 @@ sub process { $seen++ if ($block =~ /^\s*{/); - #print "cond<$cond> block<$block> allowed<$allowed>\n"; + #print "cond<$cond> block<$block> allowed<$allowed[$allow]>\n"; if (statement_lines($cond) > 1) { #print "APW: ALLOWED: cond<$cond>\n"; - $allowed = 1; + $allowed[$allow] = 1; } if ($block =~/\b(?:if|for|while)\b/) { #print "APW: ALLOWED: block<$block>\n"; - $allowed = 1; + $allowed[$allow] = 1; } if (statement_block_size($block) > 1) { #print "APW: ALLOWED: lines block<$block>\n"; - $allowed = 1; + $allowed[$allow] = 1; } + $allow++; } - if ($seen && !$allowed) { - WARN("BRACES", - "braces {} are not necessary for any arm of this statement\n" . $herectx); + if ($seen) { + my $sum_allowed = 0; + foreach (@allowed) { + $sum_allowed += $_; + } + if ($sum_allowed == 0) { + WARN("BRACES", + "braces {} are not necessary for any arm of this statement\n" . $herectx); + } elsif ($sum_allowed != $allow && + $seen != $allow) { + CHK("BRACES", + "braces {} should be used on all arms of this statement\n" . $herectx); + } } } } @@ -2932,11 +3208,11 @@ sub process { } } if ($level == 0 && $block =~ /^\s*\{/ && !$allowed) { - my $herectx = $here . "\n";; + my $herectx = $here . "\n"; my $cnt = statement_rawlines($block); for (my $n = 0; $n < $cnt; $n++) { - $herectx .= raw_line($linenr, $n) . "\n";; + $herectx .= raw_line($linenr, $n) . "\n"; } WARN("BRACES", @@ -2944,20 +3220,14 @@ sub process { } } -# don't include deprecated include files (uses RAW line) - for my $inc (@dep_includes) { - if ($rawline =~ m@^.\s*\#\s*include\s*\<$inc>@) { - ERROR("DEPRECATED_INCLUDE", - "Don't use <$inc>: see Documentation/feature-removal-schedule.txt\n" . $herecurr); - } +# check for unnecessary blank lines around braces + if (($line =~ /^..*}\s*$/ && $prevline =~ /^.\s*$/)) { + CHK("BRACES", + "Blank lines aren't necessary before a close brace '}'\n" . $hereprev); } - -# don't use deprecated functions - for my $func (@dep_functions) { - if ($line =~ /\b$func\b/) { - ERROR("DEPRECATED_FUNCTION", - "Don't use $func(): see Documentation/feature-removal-schedule.txt\n" . $herecurr); - } + if (($line =~ /^.\s*$/ && $prevline =~ /^..*{\s*$/)) { + CHK("BRACES", + "Blank lines aren't necessary after an open brace '{'\n" . $hereprev); } # no volatiles please @@ -2974,27 +3244,19 @@ sub process { $herecurr); } -# check for needless kfree() checks - if ($prevline =~ /\bif\s*\(([^\)]*)\)/) { - my $expr = $1; - if ($line =~ /\bkfree\(\Q$expr\E\);/) { - WARN("NEEDLESS_KFREE", - "kfree(NULL) is safe this check is probably not required\n" . $hereprev); - } - } -# check for needless usb_free_urb() checks - if ($prevline =~ /\bif\s*\(([^\)]*)\)/) { - my $expr = $1; - if ($line =~ /\busb_free_urb\(\Q$expr\E\);/) { - WARN("NEEDLESS_USB_FREE_URB", - "usb_free_urb(NULL) is safe this check is probably not required\n" . $hereprev); +# check for needless "if (<foo>) fn(<foo>)" uses + if ($prevline =~ /\bif\s*\(\s*($Lval)\s*\)/) { + my $expr = '\s*\(\s*' . quotemeta($1) . '\s*\)\s*;'; + if ($line =~ /\b(kfree|usb_free_urb|debugfs_remove(?:_recursive)?)$expr/) { + WARN('NEEDLESS_IF', + "$1(NULL) is safe this check is probably not required\n" . $hereprev); } } # prefer usleep_range over udelay - if ($line =~ /\budelay\s*\(\s*(\w+)\s*\)/) { + if ($line =~ /\budelay\s*\(\s*(\d+)\s*\)/) { # ignore udelay's < 10, however - if (! (($1 =~ /(\d+)/) && ($1 < 10)) ) { + if (! ($1 < 10) ) { CHK("USLEEP_RANGE", "usleep_range is preferred over udelay; see Documentation/timers/timers-howto.txt\n" . $line); } @@ -3075,18 +3337,100 @@ sub process { "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr); } +# Check for __attribute__ format(printf, prefer __printf + if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*printf/) { + WARN("PREFER_PRINTF", + "__printf(string-index, first-to-check) is preferred over __attribute__((format(printf, string-index, first-to-check)))\n" . $herecurr); + } + +# Check for __attribute__ format(scanf, prefer __scanf + if ($line =~ /\b__attribute__\s*\(\s*\(\s*format\s*\(\s*scanf\b/) { + WARN("PREFER_SCANF", + "__scanf(string-index, first-to-check) is preferred over __attribute__((format(scanf, string-index, first-to-check)))\n" . $herecurr); + } + # check for sizeof(&) if ($line =~ /\bsizeof\s*\(\s*\&/) { WARN("SIZEOF_ADDRESS", "sizeof(& should be avoided\n" . $herecurr); } +# check for sizeof without parenthesis + if ($line =~ /\bsizeof\s+((?:\*\s*|)$Lval|$Type(?:\s+$Lval|))/) { + WARN("SIZEOF_PARENTHESIS", + "sizeof $1 should be sizeof($1)\n" . $herecurr); + } + # check for line continuations in quoted strings with odd counts of " if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) { WARN("LINE_CONTINUATIONS", "Avoid line continuations in quoted strings\n" . $herecurr); } +# check for struct spinlock declarations + if ($line =~ /^.\s*\bstruct\s+spinlock\s+\w+\s*;/) { + WARN("USE_SPINLOCK_T", + "struct spinlock should be spinlock_t\n" . $herecurr); + } + +# Check for misused memsets + if ($^V && $^V ge 5.10.0 && + defined $stat && + $stat =~ /^\+(?:.*?)\bmemset\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\,\s*$FuncArg\s*\)/s) { + + my $ms_addr = $2; + my $ms_val = $7; + my $ms_size = $12; + + if ($ms_size =~ /^(0x|)0$/i) { + ERROR("MEMSET", + "memset to 0's uses 0 as the 2nd argument, not the 3rd\n" . "$here\n$stat\n"); + } elsif ($ms_size =~ /^(0x|)1$/i) { + WARN("MEMSET", + "single byte memset is suspicious. Swapped 2nd/3rd argument?\n" . "$here\n$stat\n"); + } + } + +# typecasts on min/max could be min_t/max_t + if ($^V && $^V ge 5.10.0 && + defined $stat && + $stat =~ /^\+(?:.*?)\b(min|max)\s*\(\s*$FuncArg\s*,\s*$FuncArg\s*\)/) { + if (defined $2 || defined $7) { + my $call = $1; + my $cast1 = deparenthesize($2); + my $arg1 = $3; + my $cast2 = deparenthesize($7); + my $arg2 = $8; + my $cast; + + if ($cast1 ne "" && $cast2 ne "" && $cast1 ne $cast2) { + $cast = "$cast1 or $cast2"; + } elsif ($cast1 ne "") { + $cast = $cast1; + } else { + $cast = $cast2; + } + WARN("MINMAX", + "$call() should probably be ${call}_t($cast, $arg1, $arg2)\n" . "$here\n$stat\n"); + } + } + +# check usleep_range arguments + if ($^V && $^V ge 5.10.0 && + defined $stat && + $stat =~ /^\+(?:.*?)\busleep_range\s*\(\s*($FuncArg)\s*,\s*($FuncArg)\s*\)/) { + my $min = $1; + my $max = $7; + if ($min eq $max) { + WARN("USLEEP_RANGE", + "usleep_range should not use min == max args; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n"); + } elsif ($min =~ /^\d+$/ && $max =~ /^\d+$/ && + $min > $max) { + WARN("USLEEP_RANGE", + "usleep_range args reversed, use min then max; see Documentation/timers/timers-howto.txt\n" . "$here\n$stat\n"); + } + } + # check for new externs in .c files. if ($realfile =~ /\.c$/ && defined $stat && $stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s) @@ -3133,16 +3477,30 @@ sub process { "unnecessary cast may hide bugs, see http://c-faq.com/malloc/mallocnocast.html\n" . $herecurr); } +# check for alloc argument mismatch + if ($line =~ /\b(kcalloc|kmalloc_array)\s*\(\s*sizeof\b/) { + WARN("ALLOC_ARRAY_ARGS", + "$1 uses number as first arg, sizeof is generally wrong\n" . $herecurr); + } + # check for multiple semicolons if ($line =~ /;\s*;\s*$/) { - WARN("ONE_SEMICOLON", - "Statements terminations use 1 semicolon\n" . $herecurr); + WARN("ONE_SEMICOLON", + "Statements terminations use 1 semicolon\n" . $herecurr); } -# check for whitespace before semicolon - not allowed at end-of-line - if ($line =~ /\s+;$/) { - WARN("SPACEBEFORE_SEMICOLON", - "Whitespace before semicolon\n" . $herecurr); +# check for switch/default statements without a break; + if ($^V && $^V ge 5.10.0 && + defined $stat && + $stat =~ /^\+[$;\s]*(?:case[$;\s]+\w+[$;\s]*:[$;\s]*|)*[$;\s]*\bdefault[$;\s]*:[$;\s]*;/g) { + my $ctx = ''; + my $herectx = $here . "\n"; + my $cnt = statement_rawlines($stat); + for (my $n = 0; $n < $cnt; $n++) { + $herectx .= raw_line($linenr, $n) . "\n"; + } + WARN("DEFAULT_NO_BREAK", + "switch default: should use break\n" . $herectx); } # check for gcc specific __FUNCTION__ @@ -3151,22 +3509,30 @@ sub process { "__func__ should be used instead of gcc specific __FUNCTION__\n" . $herecurr); } +# check for use of yield() + if ($line =~ /\byield\s*\(\s*\)/) { + WARN("YIELD", + "Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)\n" . $herecurr); + } + # check for semaphores initialized locked if ($line =~ /^.\s*sema_init.+,\W?0\W?\)/) { WARN("CONSIDER_COMPLETION", "consider using a completion\n" . $herecurr); - } -# recommend kstrto* over simple_strto* - if ($line =~ /\bsimple_(strto.*?)\s*\(/) { + +# recommend kstrto* over simple_strto* and strict_strto* + if ($line =~ /\b((simple|strict)_(strto(l|ll|ul|ull)))\s*\(/) { WARN("CONSIDER_KSTRTO", - "consider using kstrto* in preference to simple_$1\n" . $herecurr); + "$1 is obsolete, use k$3 instead\n" . $herecurr); } + # check for __initcall(), use device_initcall() explicitly please if ($line =~ /^.\s*__initcall\s*\(/) { WARN("USE_DEVICE_INITCALL", "please use device_initcall() instead of __initcall()\n" . $herecurr); } + # check for various ops structs, ensure they are const. my $struct_ops = qr{acpi_dock_ops| address_space_operations| @@ -3264,12 +3630,6 @@ sub process { WARN("EXPORTED_WORLD_WRITABLE", "Exporting world writable files is usually an error. Consider more restrictive permissions.\n" . $herecurr); } - - # Check for memset with swapped arguments - if ($line =~ /memset.*\,(\ |)(0x|)0(\ |0|)\);/) { - ERROR("MEMSET", - "memset size is 3rd argument, not the second.\n" . $herecurr); - } } # If we have no input at all, then there is nothing to report on @@ -3309,6 +3669,12 @@ sub process { } if ($quiet == 0) { + + if ($^V lt 5.10.0) { + print("NOTE: perl $^V is not modern enough to detect all possible issues.\n"); + print("An upgrade to at least perl v5.10.0 is suggested.\n\n"); + } + # If there were whitespace errors which cleanpatch can fix # then suggest that. if ($rpt_cleaners) { @@ -3318,13 +3684,12 @@ sub process { } } - if (keys %ignore_type) { + if ($quiet == 0 && keys %ignore_type) { print "NOTE: Ignored message types:"; foreach my $ignore (sort keys %ignore_type) { print " $ignore"; } - print "\n"; - print "\n" if ($quiet == 0); + print "\n\n"; } if ($clean == 1 && $quiet == 0) { diff --git a/tools/env/README b/tools/env/README index df020e4..1020b57 100644 --- a/tools/env/README +++ b/tools/env/README @@ -8,7 +8,7 @@ In order to cross-compile fw_printenv, run in the root directory of the U-Boot distribution. For example, make HOSTCC=arm-linux-gcc env -For the run-time utiltity configuration uncomment the line +For the run-time utility configuration uncomment the line #define CONFIG_FILE "/etc/fw_env.config" in fw_env.h. @@ -34,7 +34,7 @@ following lines are relevant: #define DEVICE2_ESIZE 0x4000 #define DEVICE2_ENVSECTORS 2 -Un-define HAVE_REDUND, if you want to use the utlities on a system +Un-define HAVE_REDUND, if you want to use the utilities on a system that does not have support for redundant environment enabled. If HAVE_REDUND is undefined, DEVICE2_NAME is ignored, as is ENV2_SIZE and DEVICE2_ESIZE. diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 37b60b80..01fc1d4 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -836,9 +836,9 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, erase.start = blockstart; ioctl (fd, MEMUNLOCK, &erase); - - /* Dataflash does not need an explicit erase cycle */ - if (mtd_type != MTD_DATAFLASH) + /* These do not need an explicit erase cycle */ + if (mtd_type != MTD_ABSENT && + mtd_type != MTD_DATAFLASH) if (ioctl (fd, MEMERASE, &erase) != 0) { fprintf (stderr, "MTD erase error on %s: %s\n", DEVNAME (dev), @@ -949,19 +949,34 @@ static int flash_write (int fd_current, int fd_target, int dev_target) static int flash_read (int fd) { struct mtd_info_user mtdinfo; + struct stat st; int rc; - rc = ioctl (fd, MEMGETINFO, &mtdinfo); + rc = fstat(fd, &st); if (rc < 0) { - perror ("Cannot get MTD information"); + fprintf(stderr, "Cannot stat the file %s\n", + DEVNAME(dev_current)); return -1; } - if (mtdinfo.type != MTD_NORFLASH && - mtdinfo.type != MTD_NANDFLASH && - mtdinfo.type != MTD_DATAFLASH) { - fprintf (stderr, "Unsupported flash type %u\n", mtdinfo.type); - return -1; + if (S_ISCHR(st.st_mode)) { + rc = ioctl(fd, MEMGETINFO, &mtdinfo); + if (rc < 0) { + fprintf(stderr, "Cannot get MTD information for %s\n", + DEVNAME(dev_current)); + return -1; + } + if (mtdinfo.type != MTD_NORFLASH && + mtdinfo.type != MTD_NANDFLASH && + mtdinfo.type != MTD_DATAFLASH && + mtdinfo.type != MTD_UBIVOLUME) { + fprintf (stderr, "Unsupported flash type %u on %s\n", + mtdinfo.type, DEVNAME(dev_current)); + return -1; + } + } else { + memset(&mtdinfo, 0, sizeof(mtdinfo)); + mtdinfo.type = MTD_ABSENT; } DEVTYPE(dev_current) = mtdinfo.type; @@ -1134,6 +1149,9 @@ int fw_env_open(void) } else if (DEVTYPE(dev_current) == MTD_DATAFLASH && DEVTYPE(!dev_current) == MTD_DATAFLASH) { environment.flag_scheme = FLAG_BOOLEAN; + } else if (DEVTYPE(dev_current) == MTD_UBIVOLUME && + DEVTYPE(!dev_current) == MTD_UBIVOLUME) { + environment.flag_scheme = FLAG_INCREMENTAL; } else { fprintf (stderr, "Incompatible flash types!\n"); return -1; diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config index 9d3b1a4..90e499d 100644 --- a/tools/env/fw_env.config +++ b/tools/env/fw_env.config @@ -17,3 +17,6 @@ # NAND example #/dev/mtd0 0x4000 0x4000 0x20000 2 + +# Block device example +#/dev/mmcblk0 0xc0000 0x20000 diff --git a/tools/logos/atmel.bmp b/tools/logos/atmel.bmp Binary files differindex 3c445c9..5c659ce 100644 --- a/tools/logos/atmel.bmp +++ b/tools/logos/atmel.bmp diff --git a/tools/patman/README b/tools/patman/README index 1832ebd..8cffcd1 100644 --- a/tools/patman/README +++ b/tools/patman/README @@ -68,7 +68,7 @@ will get a consistent result each time. How to configure it =================== -For most cases of using patman for U-Boot developement patman will +For most cases of using patman for U-Boot development, patman will locate and use the file 'doc/git-mailrc' in your U-Boot directory. This contains most of the aliases you will need. @@ -182,6 +182,10 @@ END Sets the cover letter contents for the series. The first line will become the subject of the cover letter +Cover-letter-cc: email / alias + Additional email addresses / aliases to send cover letter to (you + can add this multiple times) + Series-notes: blah blah blah blah @@ -198,8 +202,9 @@ END override the default signoff that patman automatically adds. Tested-by: Their Name <email> + Reviewed-by: Their Name <email> Acked-by: Their Name <email> - These indicate that someone has acked or tested your patch. + These indicate that someone has tested/reviewed/acked your patch. When you get this reply on the mailing list, you can add this tag to the relevant commit and the script will include it when you send out the next version. If 'Tested-by:' is set to @@ -220,9 +225,16 @@ Series-changes: n to update the log there and then, knowing that the script will do the rest. -Cc: Their Name <email> + Cc: Their Name <email> This copies a single patch to another email address. +Series-process-log: sort, uniq + This tells patman to sort and/or uniq the change logs. It is + assumed that each change log entry is only a single line long. + Use 'sort' to sort the entries, and 'uniq' to include only + unique entries. If omitted, no change log processing is done. + Separate each tag with a comma. + Various other tags are silently removed, like these Chrome OS and Gerrit tags: @@ -231,7 +243,6 @@ TEST=... Change-Id: Review URL: Reviewed-on: -Reviewed-by: Exercise for the reader: Try adding some tags to one of your current @@ -263,7 +274,13 @@ will create a patch which is copied to x86, arm, sandbox, mikef, ag and afleming. If you have a cover letter it will get sent to the union of the CC lists of -all of the other patches. +all of the other patches. If you want to sent it to additional people you +can add a tag: + +Cover-letter-cc: <list of addresses> + +These people will get the cover letter even if they are not on the To/Cc +list for any of the patches. Example Work Flow diff --git a/tools/patman/checkpatch.py b/tools/patman/checkpatch.py index d3a0477..83aaf71 100644 --- a/tools/patman/checkpatch.py +++ b/tools/patman/checkpatch.py @@ -19,6 +19,7 @@ # MA 02111-1307 USA # +import collections import command import gitutil import os @@ -57,63 +58,86 @@ def CheckPatch(fname, verbose=False): """Run checkpatch.pl on a file. Returns: - 4-tuple containing: - result: False=failure, True=ok + namedtuple containing: + ok: False=failure, True=ok problems: List of problems, each a dict: 'type'; error or warning 'msg': text message 'file' : filename 'line': line number + errors: Number of errors + warnings: Number of warnings + checks: Number of checks lines: Number of lines + stdout: Full output of checkpatch """ - result = False - error_count, warning_count, lines = 0, 0, 0 - problems = [] + fields = ['ok', 'problems', 'errors', 'warnings', 'checks', 'lines', + 'stdout'] + result = collections.namedtuple('CheckPatchResult', fields) + result.ok = False + result.errors, result.warning, result.checks = 0, 0, 0 + result.lines = 0 + result.problems = [] chk = FindCheckPatch() item = {} - stdout = command.Output(chk, '--no-tree', fname) + result.stdout = command.Output(chk, '--no-tree', fname) #pipe = subprocess.Popen(cmd, stdout=subprocess.PIPE) #stdout, stderr = pipe.communicate() # total: 0 errors, 0 warnings, 159 lines checked + # or: + # total: 0 errors, 2 warnings, 7 checks, 473 lines checked re_stats = re.compile('total: (\\d+) errors, (\d+) warnings, (\d+)') + re_stats_full = re.compile('total: (\\d+) errors, (\d+) warnings, (\d+)' + ' checks, (\d+)') re_ok = re.compile('.*has no obvious style problems') re_bad = re.compile('.*has style problems, please review') re_error = re.compile('ERROR: (.*)') re_warning = re.compile('WARNING: (.*)') + re_check = re.compile('CHECK: (.*)') re_file = re.compile('#\d+: FILE: ([^:]*):(\d+):') - for line in stdout.splitlines(): + for line in result.stdout.splitlines(): if verbose: print line # A blank line indicates the end of a message if not line and item: - problems.append(item) + result.problems.append(item) item = {} - match = re_stats.match(line) + match = re_stats_full.match(line) + if not match: + match = re_stats.match(line) if match: - error_count = int(match.group(1)) - warning_count = int(match.group(2)) - lines = int(match.group(3)) + result.errors = int(match.group(1)) + result.warnings = int(match.group(2)) + if len(match.groups()) == 4: + result.checks = int(match.group(3)) + result.lines = int(match.group(4)) + else: + result.lines = int(match.group(3)) elif re_ok.match(line): - result = True + result.ok = True elif re_bad.match(line): - result = False - match = re_error.match(line) - if match: - item['msg'] = match.group(1) + result.ok = False + err_match = re_error.match(line) + warn_match = re_warning.match(line) + file_match = re_file.match(line) + check_match = re_check.match(line) + if err_match: + item['msg'] = err_match.group(1) item['type'] = 'error' - match = re_warning.match(line) - if match: - item['msg'] = match.group(1) + elif warn_match: + item['msg'] = warn_match.group(1) item['type'] = 'warning' - match = re_file.match(line) - if match: - item['file'] = match.group(1) - item['line'] = int(match.group(2)) + elif check_match: + item['msg'] = check_match.group(1) + item['type'] = 'check' + elif file_match: + item['file'] = file_match.group(1) + item['line'] = int(file_match.group(2)) - return result, problems, error_count, warning_count, lines, stdout + return result def GetWarningMsg(col, msg_type, fname, line, msg): '''Create a message for a given file/line @@ -128,37 +152,39 @@ def GetWarningMsg(col, msg_type, fname, line, msg): msg_type = col.Color(col.YELLOW, msg_type) elif msg_type == 'error': msg_type = col.Color(col.RED, msg_type) + elif msg_type == 'check': + msg_type = col.Color(col.MAGENTA, msg_type) return '%s: %s,%d: %s' % (msg_type, fname, line, msg) def CheckPatches(verbose, args): '''Run the checkpatch.pl script on each patch''' - error_count = 0 - warning_count = 0 + error_count, warning_count, check_count = 0, 0, 0 col = terminal.Color() for fname in args: - ok, problems, errors, warnings, lines, stdout = CheckPatch(fname, - verbose) - if not ok: - error_count += errors - warning_count += warnings - print '%d errors, %d warnings for %s:' % (errors, - warnings, fname) - if len(problems) != error_count + warning_count: + result = CheckPatch(fname, verbose) + if not result.ok: + error_count += result.errors + warning_count += result.warnings + check_count += result.checks + print '%d errors, %d warnings, %d checks for %s:' % (result.errors, + result.warnings, result.checks, col.Color(col.BLUE, fname)) + if (len(result.problems) != result.errors + result.warnings + + result.checks): print "Internal error: some problems lost" - for item in problems: - print GetWarningMsg(col, item['type'], + for item in result.problems: + print GetWarningMsg(col, item.get('type', '<unknown>'), item.get('file', '<unknown>'), - item.get('line', 0), item['msg']) + item.get('line', 0), item.get('msg', 'message')) + print #print stdout - if error_count != 0 or warning_count != 0: - str = 'checkpatch.pl found %d error(s), %d warning(s)' % ( - error_count, warning_count) + if error_count or warning_count or check_count: + str = 'checkpatch.pl found %d error(s), %d warning(s), %d checks(s)' color = col.GREEN if warning_count: color = col.YELLOW if error_count: color = col.RED - print col.Color(color, str) + print col.Color(color, str % (error_count, warning_count, check_count)) return False return True diff --git a/tools/patman/command.py b/tools/patman/command.py index 4b00250..e6af6ed 100644 --- a/tools/patman/command.py +++ b/tools/patman/command.py @@ -20,53 +20,98 @@ # import os -import subprocess +import cros_subprocess """Shell command ease-ups for Python.""" -def RunPipe(pipeline, infile=None, outfile=None, - capture=False, oneline=False, hide_stderr=False): +class CommandResult: + """A class which captures the result of executing a command. + + Members: + stdout: stdout obtained from command, as a string + stderr: stderr obtained from command, as a string + return_code: Return code from command + exception: Exception received, or None if all ok + """ + def __init__(self): + self.stdout = None + self.stderr = None + self.return_code = None + self.exception = None + + +def RunPipe(pipe_list, infile=None, outfile=None, + capture=False, capture_stderr=False, oneline=False, + raise_on_error=True, cwd=None, **kwargs): """ Perform a command pipeline, with optional input/output filenames. - hide_stderr Don't allow output of stderr (default False) + Args: + pipe_list: List of command lines to execute. Each command line is + piped into the next, and is itself a list of strings. For + example [ ['ls', '.git'] ['wc'] ] will pipe the output of + 'ls .git' into 'wc'. + infile: File to provide stdin to the pipeline + outfile: File to store stdout + capture: True to capture output + capture_stderr: True to capture stderr + oneline: True to strip newline chars from output + kwargs: Additional keyword arguments to cros_subprocess.Popen() + Returns: + CommandResult object """ + result = CommandResult() last_pipe = None + pipeline = list(pipe_list) + user_pipestr = '|'.join([' '.join(pipe) for pipe in pipe_list]) while pipeline: cmd = pipeline.pop(0) - kwargs = {} if last_pipe is not None: kwargs['stdin'] = last_pipe.stdout elif infile: kwargs['stdin'] = open(infile, 'rb') if pipeline or capture: - kwargs['stdout'] = subprocess.PIPE + kwargs['stdout'] = cros_subprocess.PIPE elif outfile: kwargs['stdout'] = open(outfile, 'wb') - if hide_stderr: - kwargs['stderr'] = open('/dev/null', 'wb') + if capture_stderr: + kwargs['stderr'] = cros_subprocess.PIPE - last_pipe = subprocess.Popen(cmd, **kwargs) + try: + last_pipe = cros_subprocess.Popen(cmd, cwd=cwd, **kwargs) + except Exception, err: + result.exception = err + if raise_on_error: + raise Exception("Error running '%s': %s" % (user_pipestr, str)) + result.return_code = 255 + return result if capture: - ret = last_pipe.communicate()[0] - if not ret: - return None - elif oneline: - return ret.rstrip('\r\n') - else: - return ret + result.stdout, result.stderr, result.combined = ( + last_pipe.CommunicateFilter(None)) + if result.stdout and oneline: + result.output = result.stdout.rstrip('\r\n') + result.return_code = last_pipe.wait() else: - return os.waitpid(last_pipe.pid, 0)[1] == 0 + result.return_code = os.waitpid(last_pipe.pid, 0)[1] + if raise_on_error and result.return_code: + raise Exception("Error running '%s'" % user_pipestr) + return result def Output(*cmd): - return RunPipe([cmd], capture=True) + return RunPipe([cmd], capture=True, raise_on_error=False).stdout -def OutputOneLine(*cmd): - return RunPipe([cmd], capture=True, oneline=True) +def OutputOneLine(*cmd, **kwargs): + raise_on_error = kwargs.pop('raise_on_error', True) + return (RunPipe([cmd], capture=True, oneline=True, + raise_on_error=raise_on_error, + **kwargs).stdout.strip()) def Run(*cmd, **kwargs): - return RunPipe([cmd], **kwargs) + return RunPipe([cmd], **kwargs).stdout def RunList(cmd): - return RunPipe([cmd], capture=True) + return RunPipe([cmd], capture=True).stdout + +def StopAll(): + cros_subprocess.stay_alive = False diff --git a/tools/patman/commit.py b/tools/patman/commit.py index 7144e54..468b50c 100644 --- a/tools/patman/commit.py +++ b/tools/patman/commit.py @@ -22,7 +22,7 @@ import re # Separates a tag: at the beginning of the subject from the rest of it -re_subject_tag = re.compile('([^:]*):\s*(.*)') +re_subject_tag = re.compile('([^:\s]*):\s*(.*)') class Commit: """Holds information about a single commit/patch in the series. @@ -61,9 +61,10 @@ class Commit: Subject tags look like this: - propounder: Change the widget to propound correctly + propounder: fort: Change the widget to propound correctly - Multiple tags are supported. The list is updated in self.tag + Here the tags are propounder and fort. Multiple tags are supported. + The list is updated in self.tag. Returns: None if ok, else the name of a tag with no email alias diff --git a/tools/patman/cros_subprocess.py b/tools/patman/cros_subprocess.py new file mode 100644 index 0000000..0fc4a06 --- /dev/null +++ b/tools/patman/cros_subprocess.py @@ -0,0 +1,397 @@ +# Copyright (c) 2012 The Chromium OS Authors. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Copyright (c) 2003-2005 by Peter Astrand <astrand@lysator.liu.se> +# Licensed to PSF under a Contributor Agreement. +# See http://www.python.org/2.4/license for licensing details. + +"""Subprocress execution + +This module holds a subclass of subprocess.Popen with our own required +features, mainly that we get access to the subprocess output while it +is running rather than just at the end. This makes it easiler to show +progress information and filter output in real time. +""" + +import errno +import os +import pty +import select +import subprocess +import sys +import unittest + + +# Import these here so the caller does not need to import subprocess also. +PIPE = subprocess.PIPE +STDOUT = subprocess.STDOUT +PIPE_PTY = -3 # Pipe output through a pty +stay_alive = True + + +class Popen(subprocess.Popen): + """Like subprocess.Popen with ptys and incremental output + + This class deals with running a child process and filtering its output on + both stdout and stderr while it is running. We do this so we can monitor + progress, and possibly relay the output to the user if requested. + + The class is similar to subprocess.Popen, the equivalent is something like: + + Popen(args, stdout=subprocess.PIPE, stderr=subprocess.PIPE) + + But this class has many fewer features, and two enhancement: + + 1. Rather than getting the output data only at the end, this class sends it + to a provided operation as it arrives. + 2. We use pseudo terminals so that the child will hopefully flush its output + to us as soon as it is produced, rather than waiting for the end of a + line. + + Use CommunicateFilter() to handle output from the subprocess. + + """ + + def __init__(self, args, stdin=None, stdout=PIPE_PTY, stderr=PIPE_PTY, + shell=False, cwd=None, env=None, **kwargs): + """Cut-down constructor + + Args: + args: Program and arguments for subprocess to execute. + stdin: See subprocess.Popen() + stdout: See subprocess.Popen(), except that we support the sentinel + value of cros_subprocess.PIPE_PTY. + stderr: See subprocess.Popen(), except that we support the sentinel + value of cros_subprocess.PIPE_PTY. + shell: See subprocess.Popen() + cwd: Working directory to change to for subprocess, or None if none. + env: Environment to use for this subprocess, or None to inherit parent. + kwargs: No other arguments are supported at the moment. Passing other + arguments will cause a ValueError to be raised. + """ + stdout_pty = None + stderr_pty = None + + if stdout == PIPE_PTY: + stdout_pty = pty.openpty() + stdout = os.fdopen(stdout_pty[1]) + if stderr == PIPE_PTY: + stderr_pty = pty.openpty() + stderr = os.fdopen(stderr_pty[1]) + + super(Popen, self).__init__(args, stdin=stdin, + stdout=stdout, stderr=stderr, shell=shell, cwd=cwd, env=env, + **kwargs) + + # If we're on a PTY, we passed the slave half of the PTY to the subprocess. + # We want to use the master half on our end from now on. Setting this here + # does make some assumptions about the implementation of subprocess, but + # those assumptions are pretty minor. + + # Note that if stderr is STDOUT, then self.stderr will be set to None by + # this constructor. + if stdout_pty is not None: + self.stdout = os.fdopen(stdout_pty[0]) + if stderr_pty is not None: + self.stderr = os.fdopen(stderr_pty[0]) + + # Insist that unit tests exist for other arguments we don't support. + if kwargs: + raise ValueError("Unit tests do not test extra args - please add tests") + + def CommunicateFilter(self, output): + """Interact with process: Read data from stdout and stderr. + + This method runs until end-of-file is reached, then waits for the + subprocess to terminate. + + The output function is sent all output from the subprocess and must be + defined like this: + + def Output([self,] stream, data) + Args: + stream: the stream the output was received on, which will be + sys.stdout or sys.stderr. + data: a string containing the data + + Note: The data read is buffered in memory, so do not use this + method if the data size is large or unlimited. + + Args: + output: Function to call with each fragment of output. + + Returns: + A tuple (stdout, stderr, combined) which is the data received on + stdout, stderr and the combined data (interleaved stdout and stderr). + + Note that the interleaved output will only be sensible if you have + set both stdout and stderr to PIPE or PIPE_PTY. Even then it depends on + the timing of the output in the subprocess. If a subprocess flips + between stdout and stderr quickly in succession, by the time we come to + read the output from each we may see several lines in each, and will read + all the stdout lines, then all the stderr lines. So the interleaving + may not be correct. In this case you might want to pass + stderr=cros_subprocess.STDOUT to the constructor. + + This feature is still useful for subprocesses where stderr is + rarely used and indicates an error. + + Note also that if you set stderr to STDOUT, then stderr will be empty + and the combined output will just be the same as stdout. + """ + + read_set = [] + write_set = [] + stdout = None # Return + stderr = None # Return + + if self.stdin: + # Flush stdio buffer. This might block, if the user has + # been writing to .stdin in an uncontrolled fashion. + self.stdin.flush() + if input: + write_set.append(self.stdin) + else: + self.stdin.close() + if self.stdout: + read_set.append(self.stdout) + stdout = [] + if self.stderr and self.stderr != self.stdout: + read_set.append(self.stderr) + stderr = [] + combined = [] + + input_offset = 0 + while read_set or write_set: + try: + rlist, wlist, _ = select.select(read_set, write_set, [], 0.2) + except select.error, e: + if e.args[0] == errno.EINTR: + continue + raise + + if not stay_alive: + self.terminate() + + if self.stdin in wlist: + # When select has indicated that the file is writable, + # we can write up to PIPE_BUF bytes without risk + # blocking. POSIX defines PIPE_BUF >= 512 + chunk = input[input_offset : input_offset + 512] + bytes_written = os.write(self.stdin.fileno(), chunk) + input_offset += bytes_written + if input_offset >= len(input): + self.stdin.close() + write_set.remove(self.stdin) + + if self.stdout in rlist: + data = "" + # We will get an error on read if the pty is closed + try: + data = os.read(self.stdout.fileno(), 1024) + except OSError: + pass + if data == "": + self.stdout.close() + read_set.remove(self.stdout) + else: + stdout.append(data) + combined.append(data) + if output: + output(sys.stdout, data) + if self.stderr in rlist: + data = "" + # We will get an error on read if the pty is closed + try: + data = os.read(self.stderr.fileno(), 1024) + except OSError: + pass + if data == "": + self.stderr.close() + read_set.remove(self.stderr) + else: + stderr.append(data) + combined.append(data) + if output: + output(sys.stderr, data) + + # All data exchanged. Translate lists into strings. + if stdout is not None: + stdout = ''.join(stdout) + else: + stdout = '' + if stderr is not None: + stderr = ''.join(stderr) + else: + stderr = '' + combined = ''.join(combined) + + # Translate newlines, if requested. We cannot let the file + # object do the translation: It is based on stdio, which is + # impossible to combine with select (unless forcing no + # buffering). + if self.universal_newlines and hasattr(file, 'newlines'): + if stdout: + stdout = self._translate_newlines(stdout) + if stderr: + stderr = self._translate_newlines(stderr) + + self.wait() + return (stdout, stderr, combined) + + +# Just being a unittest.TestCase gives us 14 public methods. Unless we +# disable this, we can only have 6 tests in a TestCase. That's not enough. +# +# pylint: disable=R0904 + +class TestSubprocess(unittest.TestCase): + """Our simple unit test for this module""" + + class MyOperation: + """Provides a operation that we can pass to Popen""" + def __init__(self, input_to_send=None): + """Constructor to set up the operation and possible input. + + Args: + input_to_send: a text string to send when we first get input. We will + add \r\n to the string. + """ + self.stdout_data = '' + self.stderr_data = '' + self.combined_data = '' + self.stdin_pipe = None + self._input_to_send = input_to_send + if input_to_send: + pipe = os.pipe() + self.stdin_read_pipe = pipe[0] + self._stdin_write_pipe = os.fdopen(pipe[1], 'w') + + def Output(self, stream, data): + """Output handler for Popen. Stores the data for later comparison""" + if stream == sys.stdout: + self.stdout_data += data + if stream == sys.stderr: + self.stderr_data += data + self.combined_data += data + + # Output the input string if we have one. + if self._input_to_send: + self._stdin_write_pipe.write(self._input_to_send + '\r\n') + self._stdin_write_pipe.flush() + + def _BasicCheck(self, plist, oper): + """Basic checks that the output looks sane.""" + self.assertEqual(plist[0], oper.stdout_data) + self.assertEqual(plist[1], oper.stderr_data) + self.assertEqual(plist[2], oper.combined_data) + + # The total length of stdout and stderr should equal the combined length + self.assertEqual(len(plist[0]) + len(plist[1]), len(plist[2])) + + def test_simple(self): + """Simple redirection: Get process list""" + oper = TestSubprocess.MyOperation() + plist = Popen(['ps']).CommunicateFilter(oper.Output) + self._BasicCheck(plist, oper) + + def test_stderr(self): + """Check stdout and stderr""" + oper = TestSubprocess.MyOperation() + cmd = 'echo fred >/dev/stderr && false || echo bad' + plist = Popen([cmd], shell=True).CommunicateFilter(oper.Output) + self._BasicCheck(plist, oper) + self.assertEqual(plist [0], 'bad\r\n') + self.assertEqual(plist [1], 'fred\r\n') + + def test_shell(self): + """Check with and without shell works""" + oper = TestSubprocess.MyOperation() + cmd = 'echo test >/dev/stderr' + self.assertRaises(OSError, Popen, [cmd], shell=False) + plist = Popen([cmd], shell=True).CommunicateFilter(oper.Output) + self._BasicCheck(plist, oper) + self.assertEqual(len(plist [0]), 0) + self.assertEqual(plist [1], 'test\r\n') + + def test_list_args(self): + """Check with and without shell works using list arguments""" + oper = TestSubprocess.MyOperation() + cmd = ['echo', 'test', '>/dev/stderr'] + plist = Popen(cmd, shell=False).CommunicateFilter(oper.Output) + self._BasicCheck(plist, oper) + self.assertEqual(plist [0], ' '.join(cmd[1:]) + '\r\n') + self.assertEqual(len(plist [1]), 0) + + oper = TestSubprocess.MyOperation() + + # this should be interpreted as 'echo' with the other args dropped + cmd = ['echo', 'test', '>/dev/stderr'] + plist = Popen(cmd, shell=True).CommunicateFilter(oper.Output) + self._BasicCheck(plist, oper) + self.assertEqual(plist [0], '\r\n') + + def test_cwd(self): + """Check we can change directory""" + for shell in (False, True): + oper = TestSubprocess.MyOperation() + plist = Popen('pwd', shell=shell, cwd='/tmp').CommunicateFilter(oper.Output) + self._BasicCheck(plist, oper) + self.assertEqual(plist [0], '/tmp\r\n') + + def test_env(self): + """Check we can change environment""" + for add in (False, True): + oper = TestSubprocess.MyOperation() + env = os.environ + if add: + env ['FRED'] = 'fred' + cmd = 'echo $FRED' + plist = Popen(cmd, shell=True, env=env).CommunicateFilter(oper.Output) + self._BasicCheck(plist, oper) + self.assertEqual(plist [0], add and 'fred\r\n' or '\r\n') + + def test_extra_args(self): + """Check we can't add extra arguments""" + self.assertRaises(ValueError, Popen, 'true', close_fds=False) + + def test_basic_input(self): + """Check that incremental input works + + We set up a subprocess which will prompt for name. When we see this prompt + we send the name as input to the process. It should then print the name + properly to stdout. + """ + oper = TestSubprocess.MyOperation('Flash') + prompt = 'What is your name?: ' + cmd = 'echo -n "%s"; read name; echo Hello $name' % prompt + plist = Popen([cmd], stdin=oper.stdin_read_pipe, + shell=True).CommunicateFilter(oper.Output) + self._BasicCheck(plist, oper) + self.assertEqual(len(plist [1]), 0) + self.assertEqual(plist [0], prompt + 'Hello Flash\r\r\n') + + def test_isatty(self): + """Check that ptys appear as terminals to the subprocess""" + oper = TestSubprocess.MyOperation() + cmd = ('if [ -t %d ]; then echo "terminal %d" >&%d; ' + 'else echo "not %d" >&%d; fi;') + both_cmds = '' + for fd in (1, 2): + both_cmds += cmd % (fd, fd, fd, fd, fd) + plist = Popen(both_cmds, shell=True).CommunicateFilter(oper.Output) + self._BasicCheck(plist, oper) + self.assertEqual(plist [0], 'terminal 1\r\n') + self.assertEqual(plist [1], 'terminal 2\r\n') + + # Now try with PIPE and make sure it is not a terminal + oper = TestSubprocess.MyOperation() + plist = Popen(both_cmds, stdout=subprocess.PIPE, stderr=subprocess.PIPE, + shell=True).CommunicateFilter(oper.Output) + self._BasicCheck(plist, oper) + self.assertEqual(plist [0], 'not 1\n') + self.assertEqual(plist [1], 'not 2\n') + +if __name__ == '__main__': + unittest.main() diff --git a/tools/patman/gitutil.py b/tools/patman/gitutil.py index ca3ba4a..f485750 100644 --- a/tools/patman/gitutil.py +++ b/tools/patman/gitutil.py @@ -23,11 +23,12 @@ import command import re import os import series -import settings import subprocess import sys import terminal +import settings + def CountCommitsToBranch(): """Returns number of commits between HEAD and the tracking branch. @@ -40,10 +41,123 @@ def CountCommitsToBranch(): """ pipe = [['git', 'log', '--no-color', '--oneline', '@{upstream}..'], ['wc', '-l']] - stdout = command.RunPipe(pipe, capture=True, oneline=True) + stdout = command.RunPipe(pipe, capture=True, oneline=True).stdout + patch_count = int(stdout) + return patch_count + +def GetUpstream(git_dir, branch): + """Returns the name of the upstream for a branch + + Args: + git_dir: Git directory containing repo + branch: Name of branch + + Returns: + Name of upstream branch (e.g. 'upstream/master') or None if none + """ + remote = command.OutputOneLine('git', '--git-dir', git_dir, 'config', + 'branch.%s.remote' % branch) + merge = command.OutputOneLine('git', '--git-dir', git_dir, 'config', + 'branch.%s.merge' % branch) + if remote == '.': + return merge + elif remote and merge: + leaf = merge.split('/')[-1] + return '%s/%s' % (remote, leaf) + else: + raise ValueError, ("Cannot determine upstream branch for branch " + "'%s' remote='%s', merge='%s'" % (branch, remote, merge)) + + +def GetRangeInBranch(git_dir, branch, include_upstream=False): + """Returns an expression for the commits in the given branch. + + Args: + git_dir: Directory containing git repo + branch: Name of branch + Return: + Expression in the form 'upstream..branch' which can be used to + access the commits. + """ + upstream = GetUpstream(git_dir, branch) + return '%s%s..%s' % (upstream, '~' if include_upstream else '', branch) + +def CountCommitsInBranch(git_dir, branch, include_upstream=False): + """Returns the number of commits in the given branch. + + Args: + git_dir: Directory containing git repo + branch: Name of branch + Return: + Number of patches that exist on top of the branch + """ + range_expr = GetRangeInBranch(git_dir, branch, include_upstream) + pipe = [['git', '--git-dir', git_dir, 'log', '--oneline', range_expr], + ['wc', '-l']] + result = command.RunPipe(pipe, capture=True, oneline=True) + patch_count = int(result.stdout) + return patch_count + +def CountCommits(commit_range): + """Returns the number of commits in the given range. + + Args: + commit_range: Range of commits to count (e.g. 'HEAD..base') + Return: + Number of patches that exist on top of the branch + """ + pipe = [['git', 'log', '--oneline', commit_range], + ['wc', '-l']] + stdout = command.RunPipe(pipe, capture=True, oneline=True).stdout patch_count = int(stdout) return patch_count +def Checkout(commit_hash, git_dir=None, work_tree=None, force=False): + """Checkout the selected commit for this build + + Args: + commit_hash: Commit hash to check out + """ + pipe = ['git'] + if git_dir: + pipe.extend(['--git-dir', git_dir]) + if work_tree: + pipe.extend(['--work-tree', work_tree]) + pipe.append('checkout') + if force: + pipe.append('-f') + pipe.append(commit_hash) + result = command.RunPipe([pipe], capture=True, raise_on_error=False) + if result.return_code != 0: + raise OSError, 'git checkout (%s): %s' % (pipe, result.stderr) + +def Clone(git_dir, output_dir): + """Checkout the selected commit for this build + + Args: + commit_hash: Commit hash to check out + """ + pipe = ['git', 'clone', git_dir, '.'] + result = command.RunPipe([pipe], capture=True, cwd=output_dir) + if result.return_code != 0: + raise OSError, 'git clone: %s' % result.stderr + +def Fetch(git_dir=None, work_tree=None): + """Fetch from the origin repo + + Args: + commit_hash: Commit hash to check out + """ + pipe = ['git'] + if git_dir: + pipe.extend(['--git-dir', git_dir]) + if work_tree: + pipe.extend(['--work-tree', work_tree]) + pipe.append('fetch') + result = command.RunPipe([pipe], capture=True) + if result.return_code != 0: + raise OSError, 'git fetch: %s' % result.stderr + def CreatePatches(start, count, series): """Create a series of patches from the top of the current branch. @@ -159,7 +273,7 @@ def ApplyPatches(verbose, args, start_point): print stdout, stderr return error_count == 0 -def BuildEmailList(in_list, tag=None, alias=None): +def BuildEmailList(in_list, tag=None, alias=None, raise_on_error=True): """Build a list of email addresses based on an input list. Takes a list of email addresses and aliases, and turns this into a list @@ -172,6 +286,9 @@ def BuildEmailList(in_list, tag=None, alias=None): Args: in_list: List of aliases/email addresses tag: Text to put before each address + alias: Alias dictionary + raise_on_error: True to raise an error when an alias fails to match, + False to just print a message. Returns: List of email addresses @@ -193,7 +310,7 @@ def BuildEmailList(in_list, tag=None, alias=None): quote = '"' if tag and tag[0] == '-' else '' raw = [] for item in in_list: - raw += LookupEmail(item, alias) + raw += LookupEmail(item, alias, raise_on_error=raise_on_error) result = [] for item in raw: if not item in result: @@ -202,8 +319,8 @@ def BuildEmailList(in_list, tag=None, alias=None): return ['%s %s%s%s' % (tag, quote, email, quote) for email in result] return result -def EmailPatches(series, cover_fname, args, dry_run, cc_fname, - self_only=False, alias=None): +def EmailPatches(series, cover_fname, args, dry_run, raise_on_error, cc_fname, + self_only=False, alias=None, in_reply_to=None): """Email a patch series. Args: @@ -211,8 +328,12 @@ def EmailPatches(series, cover_fname, args, dry_run, cc_fname, cover_fname: filename of cover letter args: list of filenames of patch files dry_run: Just return the command that would be run + raise_on_error: True to raise an error when an alias fails to match, + False to just print a message. cc_fname: Filename of Cc file for per-commit Cc self_only: True to just email to yourself as a test + in_reply_to: If set we'll pass this to git as --in-reply-to. + Should be a message ID that this is in reply to. Returns: Git command that was/would be run @@ -231,20 +352,21 @@ def EmailPatches(series, cover_fname, args, dry_run, cc_fname, >>> series = series.Series() >>> series.to = ['fred'] >>> series.cc = ['mary'] - >>> EmailPatches(series, 'cover', ['p1', 'p2'], True, 'cc-fname', False, \ - alias) + >>> EmailPatches(series, 'cover', ['p1', 'p2'], True, True, 'cc-fname', \ + False, alias) 'git send-email --annotate --to "f.bloggs@napier.co.nz" --cc \ "m.poppins@cloud.net" --cc-cmd "./patman --cc-cmd cc-fname" cover p1 p2' - >>> EmailPatches(series, None, ['p1'], True, 'cc-fname', False, alias) + >>> EmailPatches(series, None, ['p1'], True, True, 'cc-fname', False, \ + alias) 'git send-email --annotate --to "f.bloggs@napier.co.nz" --cc \ "m.poppins@cloud.net" --cc-cmd "./patman --cc-cmd cc-fname" p1' >>> series.cc = ['all'] - >>> EmailPatches(series, 'cover', ['p1', 'p2'], True, 'cc-fname', True, \ - alias) + >>> EmailPatches(series, 'cover', ['p1', 'p2'], True, True, 'cc-fname', \ + True, alias) 'git send-email --annotate --to "this-is-me@me.com" --cc-cmd "./patman \ --cc-cmd cc-fname" cover p1 p2' - >>> EmailPatches(series, 'cover', ['p1', 'p2'], True, 'cc-fname', False, \ - alias) + >>> EmailPatches(series, 'cover', ['p1', 'p2'], True, True, 'cc-fname', \ + False, alias) 'git send-email --annotate --to "f.bloggs@napier.co.nz" --cc \ "f.bloggs@napier.co.nz" --cc "j.bloggs@napier.co.nz" --cc \ "m.poppins@cloud.net" --cc-cmd "./patman --cc-cmd cc-fname" cover p1 p2' @@ -252,16 +374,19 @@ def EmailPatches(series, cover_fname, args, dry_run, cc_fname, # Restore argv[0] since we clobbered it. >>> sys.argv[0] = _old_argv0 """ - to = BuildEmailList(series.get('to'), '--to', alias) + to = BuildEmailList(series.get('to'), '--to', alias, raise_on_error) if not to: print ("No recipient, please add something like this to a commit\n" "Series-to: Fred Bloggs <f.blogs@napier.co.nz>") return - cc = BuildEmailList(series.get('cc'), '--cc', alias) + cc = BuildEmailList(series.get('cc'), '--cc', alias, raise_on_error) if self_only: - to = BuildEmailList([os.getenv('USER')], '--to', alias) + to = BuildEmailList([os.getenv('USER')], '--to', alias, raise_on_error) cc = [] cmd = ['git', 'send-email', '--annotate'] + if in_reply_to: + cmd.append('--in-reply-to="%s"' % in_reply_to) + cmd += to cmd += cc cmd += ['--cc-cmd', '"%s --cc-cmd %s"' % (sys.argv[0], cc_fname)] @@ -274,13 +399,16 @@ def EmailPatches(series, cover_fname, args, dry_run, cc_fname, return str -def LookupEmail(lookup_name, alias=None, level=0): +def LookupEmail(lookup_name, alias=None, raise_on_error=True, level=0): """If an email address is an alias, look it up and return the full name TODO: Why not just use git's own alias feature? Args: lookup_name: Alias or email address to look up + alias: Dictionary containing aliases (None to use settings default) + raise_on_error: True to raise an error when an alias fails to match, + False to just print a message. Returns: tuple: @@ -314,6 +442,15 @@ def LookupEmail(lookup_name, alias=None, level=0): Traceback (most recent call last): ... OSError: Recursive email alias at 'other' + >>> LookupEmail('odd', alias, raise_on_error=False) + \033[1;31mAlias 'odd' not found\033[0m + [] + >>> # In this case the loop part will effectively be ignored. + >>> LookupEmail('loop', alias, raise_on_error=False) + \033[1;31mRecursive email alias at 'other'\033[0m + \033[1;31mRecursive email alias at 'john'\033[0m + \033[1;31mRecursive email alias at 'mary'\033[0m + ['j.bloggs@napier.co.nz', 'm.poppins@cloud.net'] """ if not alias: alias = settings.alias @@ -322,16 +459,27 @@ def LookupEmail(lookup_name, alias=None, level=0): return [lookup_name] lookup_name = lookup_name.lower() + col = terminal.Color() + out_list = [] if level > 10: - raise OSError, "Recursive email alias at '%s'" % lookup_name + msg = "Recursive email alias at '%s'" % lookup_name + if raise_on_error: + raise OSError, msg + else: + print col.Color(col.RED, msg) + return out_list - out_list = [] if lookup_name: if not lookup_name in alias: - raise ValueError, "Alias '%s' not found" % lookup_name + msg = "Alias '%s' not found" % lookup_name + if raise_on_error: + raise ValueError, msg + else: + print col.Color(col.RED, msg) + return out_list for item in alias[lookup_name]: - todo = LookupEmail(item, alias, level + 1) + todo = LookupEmail(item, alias, raise_on_error, level + 1) for new_item in todo: if not new_item in out_list: out_list.append(new_item) @@ -359,7 +507,8 @@ def GetAliasFile(): Returns: Filename of git alias file, or None if none """ - fname = command.OutputOneLine('git', 'config', 'sendemail.aliasesfile') + fname = command.OutputOneLine('git', 'config', 'sendemail.aliasesfile', + raise_on_error=False) if fname: fname = os.path.join(GetTopLevel(), fname.strip()) return fname @@ -389,6 +538,14 @@ def Setup(): if alias_fname: settings.ReadGitAliases(alias_fname) +def GetHead(): + """Get the hash of the current HEAD + + Returns: + Hash of HEAD + """ + return command.OutputOneLine('git', 'show', '-s', '--pretty=format:%H') + if __name__ == "__main__": import doctest diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py index f7ee75a..7334ed3 100644 --- a/tools/patman/patchstream.py +++ b/tools/patman/patchstream.py @@ -31,7 +31,7 @@ from series import Series # Tags that we detect and remove re_remove = re.compile('^BUG=|^TEST=|^BRANCH=|^Change-Id:|^Review URL:' - '|Reviewed-on:|Reviewed-by:|Commit-Ready:') + '|Reviewed-on:|Commit-\w*:') # Lines which are allowed after a TEST= line re_allowed_after_test = re.compile('^Signed-off-by:') @@ -42,14 +42,17 @@ re_signoff = re.compile('^Signed-off-by:') # The start of the cover letter re_cover = re.compile('^Cover-letter:') +# A cover letter Cc +re_cover_cc = re.compile('^Cover-letter-cc: *(.*)') + # Patch series tag -re_series = re.compile('^Series-(\w*): *(.*)') +re_series = re.compile('^Series-([a-z-]*): *(.*)') # Commit tags that we want to collect and keep -re_tag = re.compile('^(Tested-by|Acked-by|Cc): (.*)') +re_tag = re.compile('^(Tested-by|Acked-by|Reviewed-by|Cc): (.*)') # The start of a new commit in the git log -re_commit = re.compile('^commit (.*)') +re_commit = re.compile('^commit ([0-9a-f]*)$') # We detect these since checkpatch doesn't always do it re_space_before_tab = re.compile('^[+].* \t') @@ -153,6 +156,7 @@ class PatchStream: # Handle state transition and skipping blank lines series_match = re_series.match(line) commit_match = re_commit.match(line) if self.is_log else None + cover_cc_match = re_cover_cc.match(line) tag_match = None if self.state == STATE_PATCH_HEADER: tag_match = re_tag.match(line) @@ -205,6 +209,10 @@ class PatchStream: self.in_section = 'cover' self.skip_blank = False + elif cover_cc_match: + value = cover_cc_match.group(1) + self.AddToSeries(line, 'cover-cc', value) + # If we are in a change list, key collected lines until a blank one elif self.in_change: if is_blank: @@ -237,7 +245,8 @@ class PatchStream: # Detect the start of a new commit elif commit_match: self.CloseCommit() - self.commit = commit.Commit(commit_match.group(1)[:7]) + # TODO: We should store the whole hash, and just display a subset + self.commit = commit.Commit(commit_match.group(1)[:8]) # Detect tags in the commit message elif tag_match: @@ -334,26 +343,47 @@ class PatchStream: self.Finalize() -def GetMetaData(start, count): +def GetMetaDataForList(commit_range, git_dir=None, count=None, + series = Series()): """Reads out patch series metadata from the commits This does a 'git log' on the relevant commits and pulls out the tags we are interested in. Args: - start: Commit to start from: 0=HEAD, 1=next one, etc. - count: Number of commits to list + commit_range: Range of commits to count (e.g. 'HEAD..base') + git_dir: Path to git repositiory (None to use default) + count: Number of commits to list, or None for no limit + series: Series object to add information into. By default a new series + is started. + Returns: + A Series object containing information about the commits. """ - pipe = [['git', 'log', '--no-color', '--reverse', 'HEAD~%d' % start, - '-n%d' % count]] - stdout = command.RunPipe(pipe, capture=True) - series = Series() + params = ['git', 'log', '--no-color', '--reverse', commit_range] + if count is not None: + params[2:2] = ['-n%d' % count] + if git_dir: + params[1:1] = ['--git-dir', git_dir] + pipe = [params] + stdout = command.RunPipe(pipe, capture=True).stdout ps = PatchStream(series, is_log=True) for line in stdout.splitlines(): ps.ProcessLine(line) ps.Finalize() return series +def GetMetaData(start, count): + """Reads out patch series metadata from the commits + + This does a 'git log' on the relevant commits and pulls out the tags we + are interested in. + + Args: + start: Commit to start from: 0=HEAD, 1=next one, etc. + count: Number of commits to list + """ + return GetMetaDataForList('HEAD~%d' % start, None, count) + def FixPatch(backup_dir, fname, series, commit): """Fix up a patch file, by adding/removing as required. diff --git a/tools/patman/patman.py b/tools/patman/patman.py index e049081..a8061a9 100755 --- a/tools/patman/patman.py +++ b/tools/patman/patman.py @@ -41,6 +41,9 @@ import test parser = OptionParser() +parser.add_option('-a', '--no-apply', action='store_false', + dest='apply_patches', default=True, + help="Don't test-apply patches with git am") parser.add_option('-H', '--full-help', action='store_true', dest='full_help', default=False, help='Display the README file') parser.add_option('-c', '--count', dest='count', type='int', @@ -49,13 +52,17 @@ parser.add_option('-i', '--ignore-errors', action='store_true', dest='ignore_errors', default=False, help='Send patches email even if patch errors are found') parser.add_option('-n', '--dry-run', action='store_true', dest='dry_run', - default=False, help="Do a try run (create but don't email patches)") + default=False, help="Do a dry run (create but don't email patches)") parser.add_option('-p', '--project', default=project.DetectProject(), help="Project name; affects default option values and " "aliases [default: %default]") +parser.add_option('-r', '--in-reply-to', type='string', action='store', + help="Message ID that this series is in reply to") parser.add_option('-s', '--start', dest='start', type='int', default=0, help='Commit to start creating patches from (0 = HEAD)') -parser.add_option('-t', '--test', action='store_true', dest='test', +parser.add_option('-t', '--ignore-bad-tags', action='store_true', + default=False, help='Ignore bad tags / aliases') +parser.add_option('--test', action='store_true', dest='test', default=False, help='run tests') parser.add_option('-v', '--verbose', action='store_true', dest='verbose', default=False, help='Verbose output of errors and warnings') @@ -70,7 +77,7 @@ parser.add_option('--no-tags', action='store_false', dest='process_tags', parser.usage = """patman [options] Create patches from commits in a branch, check them and email them as -specified by tags you place in the commits. Use -n to """ +specified by tags you place in the commits. Use -n to do a dry run first.""" # Parse options twice: first to get the project and second to handle @@ -153,17 +160,20 @@ else: ok = checkpatch.CheckPatches(options.verbose, args) else: ok = True - if not gitutil.ApplyPatches(options.verbose, args, - options.count + options.start): - ok = False + if options.apply_patches: + if not gitutil.ApplyPatches(options.verbose, args, + options.count + options.start): + ok = False - cc_file = series.MakeCcFile(options.process_tags, cover_fname) + cc_file = series.MakeCcFile(options.process_tags, cover_fname, + not options.ignore_bad_tags) # Email the patches out (giving the user time to check / cancel) cmd = '' if ok or options.ignore_errors: cmd = gitutil.EmailPatches(series, cover_fname, args, - options.dry_run, cc_file) + options.dry_run, not options.ignore_bad_tags, cc_file, + in_reply_to=options.in_reply_to) # For a dry run, just show our actions as a sanity check if options.dry_run: diff --git a/tools/patman/series.py b/tools/patman/series.py index 6c5c570..783b3dd 100644 --- a/tools/patman/series.py +++ b/tools/patman/series.py @@ -27,7 +27,8 @@ import gitutil import terminal # Series-xxx tags that we understand -valid_series = ['to', 'cc', 'version', 'changes', 'prefix', 'notes', 'name']; +valid_series = ['to', 'cc', 'version', 'changes', 'prefix', 'notes', 'name', + 'cover-cc', 'process_log'] class Series(dict): """Holds information about a patch series, including all tags. @@ -43,6 +44,7 @@ class Series(dict): def __init__(self): self.cc = [] self.to = [] + self.cover_cc = [] self.commits = [] self.cover = None self.notes = [] @@ -69,6 +71,7 @@ class Series(dict): value: Tag value (part after 'Series-xxx: ') """ # If we already have it, then add to our list + name = name.replace('-', '_') if name in self: values = value.split(',') values = [str.strip() for str in values] @@ -140,7 +143,8 @@ class Series(dict): print 'Prefix:\t ', self.get('prefix') if self.cover: print 'Cover: %d lines' % len(self.cover) - all_ccs = itertools.chain(*self._generated_cc.values()) + cover_cc = gitutil.BuildEmailList(self.get('cover_cc', '')) + all_ccs = itertools.chain(cover_cc, *self._generated_cc.values()) for email in set(all_ccs): print ' Cc: ',email if cmd: @@ -163,15 +167,20 @@ class Series(dict): etc. """ final = [] + process_it = self.get('process_log', '').split(',') + process_it = [item.strip() for item in process_it] need_blank = False for change in sorted(self.changes, reverse=True): out = [] for this_commit, text in self.changes[change]: if commit and this_commit != commit: continue - out.append(text) + if 'uniq' not in process_it or text not in out: + out.append(text) line = 'Changes in v%d:' % change have_changes = len(out) > 0 + if 'sort' in process_it: + out = sorted(out) if have_changes: out.insert(0, line) else: @@ -206,7 +215,7 @@ class Series(dict): str = 'Change log exists, but no version is set' print col.Color(col.RED, str) - def MakeCcFile(self, process_tags, cover_fname): + def MakeCcFile(self, process_tags, cover_fname, raise_on_error): """Make a cc file for us to use for per-commit Cc automation Also stores in self._generated_cc to make ShowActions() faster. @@ -214,6 +223,8 @@ class Series(dict): Args: process_tags: Process tags as if they were aliases cover_fname: If non-None the name of the cover letter. + raise_on_error: True to raise an error when an alias fails to match, + False to just print a message. Return: Filename of temp file created """ @@ -224,15 +235,18 @@ class Series(dict): for commit in self.commits: list = [] if process_tags: - list += gitutil.BuildEmailList(commit.tags) - list += gitutil.BuildEmailList(commit.cc_list) + list += gitutil.BuildEmailList(commit.tags, + raise_on_error=raise_on_error) + list += gitutil.BuildEmailList(commit.cc_list, + raise_on_error=raise_on_error) list += get_maintainer.GetMaintainer(commit.patch) all_ccs += list print >>fd, commit.patch, ', '.join(list) self._generated_cc[commit.patch] = list if cover_fname: - print >>fd, cover_fname, ', '.join(set(all_ccs)) + cover_cc = gitutil.BuildEmailList(self.get('cover_cc', '')) + print >>fd, cover_fname, ', '.join(set(cover_cc + all_ccs)) fd.close() return fname diff --git a/tools/patman/terminal.py b/tools/patman/terminal.py index 838c828..337a2a4 100644 --- a/tools/patman/terminal.py +++ b/tools/patman/terminal.py @@ -24,24 +24,32 @@ This module handles terminal interaction including ANSI color codes. """ +import os +import sys + +# Selection of when we want our output to be colored +COLOR_IF_TERMINAL, COLOR_ALWAYS, COLOR_NEVER = range(3) + class Color(object): """Conditionally wraps text in ANSI color escape sequences.""" BLACK, RED, GREEN, YELLOW, BLUE, MAGENTA, CYAN, WHITE = range(8) BOLD = -1 - COLOR_START = '\033[1;%dm' + BRIGHT_START = '\033[1;%dm' + NORMAL_START = '\033[22;%dm' BOLD_START = '\033[1m' RESET = '\033[0m' - def __init__(self, enabled=True): + def __init__(self, colored=COLOR_IF_TERMINAL): """Create a new Color object, optionally disabling color output. Args: enabled: True if color output should be enabled. If False then this class will not add color codes at all. """ - self._enabled = enabled + self._enabled = (colored == COLOR_ALWAYS or + (colored == COLOR_IF_TERMINAL and os.isatty(sys.stdout.fileno()))) - def Start(self, color): + def Start(self, color, bright=True): """Returns a start color code. Args: @@ -52,7 +60,8 @@ class Color(object): otherwise returns empty string """ if self._enabled: - return self.COLOR_START % (color + 30) + base = self.BRIGHT_START if bright else self.NORMAL_START + return base % (color + 30) return '' def Stop(self): @@ -63,10 +72,10 @@ class Color(object): returns empty string """ if self._enabled: - return self.RESET + return self.RESET return '' - def Color(self, color, text): + def Color(self, color, text, bright=True): """Returns text with conditionally added color escape sequences. Keyword arguments: @@ -78,9 +87,10 @@ class Color(object): returns text with color escape sequences based on the value of color. """ if not self._enabled: - return text + return text if color == self.BOLD: - start = self.BOLD_START + start = self.BOLD_START else: - start = self.COLOR_START % (color + 30) + base = self.BRIGHT_START if bright else self.NORMAL_START + start = base % (color + 30) return start + text + self.RESET diff --git a/tools/patman/test.py b/tools/patman/test.py index f801ced..8cd2647 100644 --- a/tools/patman/test.py +++ b/tools/patman/test.py @@ -190,6 +190,11 @@ index 0000000..2234c87 + rec->time_us = (uint32_t)timer_get_us(); + rec->name = name; + } ++ if (!rec->name && ++ %ssomething_else) { ++ rec->time_us = (uint32_t)timer_get_us(); ++ rec->name = name; ++ } +%sreturn rec->time_us; +} -- @@ -197,15 +202,18 @@ index 0000000..2234c87 ''' signoff = 'Signed-off-by: Simon Glass <sjg@chromium.org>\n' tab = ' ' + indent = ' ' if data_type == 'good': pass elif data_type == 'no-signoff': signoff = '' elif data_type == 'spaces': tab = ' ' + elif data_type == 'indent': + indent = tab else: print 'not implemented' - return data % (signoff, tab, tab) + return data % (signoff, tab, indent, tab) def SetupData(self, data_type): inhandle, inname = tempfile.mkstemp() @@ -215,33 +223,49 @@ index 0000000..2234c87 infd.close() return inname - def testCheckpatch(self): + def testGood(self): """Test checkpatch operation""" inf = self.SetupData('good') - result, problems, err, warn, lines, stdout = checkpatch.CheckPatch(inf) - self.assertEqual(result, True) - self.assertEqual(problems, []) - self.assertEqual(err, 0) - self.assertEqual(warn, 0) - self.assertEqual(lines, 67) + result = checkpatch.CheckPatch(inf) + self.assertEqual(result.ok, True) + self.assertEqual(result.problems, []) + self.assertEqual(result.errors, 0) + self.assertEqual(result.warnings, 0) + self.assertEqual(result.checks, 0) + self.assertEqual(result.lines, 67) os.remove(inf) + def testNoSignoff(self): inf = self.SetupData('no-signoff') - result, problems, err, warn, lines, stdout = checkpatch.CheckPatch(inf) - self.assertEqual(result, False) - self.assertEqual(len(problems), 1) - self.assertEqual(err, 1) - self.assertEqual(warn, 0) - self.assertEqual(lines, 67) + result = checkpatch.CheckPatch(inf) + self.assertEqual(result.ok, False) + self.assertEqual(len(result.problems), 1) + self.assertEqual(result.errors, 1) + self.assertEqual(result.warnings, 0) + self.assertEqual(result.checks, 0) + self.assertEqual(result.lines, 67) os.remove(inf) + def testSpaces(self): inf = self.SetupData('spaces') - result, problems, err, warn, lines, stdout = checkpatch.CheckPatch(inf) - self.assertEqual(result, False) - self.assertEqual(len(problems), 2) - self.assertEqual(err, 0) - self.assertEqual(warn, 2) - self.assertEqual(lines, 67) + result = checkpatch.CheckPatch(inf) + self.assertEqual(result.ok, False) + self.assertEqual(len(result.problems), 1) + self.assertEqual(result.errors, 0) + self.assertEqual(result.warnings, 1) + self.assertEqual(result.checks, 0) + self.assertEqual(result.lines, 67) + os.remove(inf) + + def testIndent(self): + inf = self.SetupData('indent') + result = checkpatch.CheckPatch(inf) + self.assertEqual(result.ok, False) + self.assertEqual(len(result.problems), 1) + self.assertEqual(result.errors, 0) + self.assertEqual(result.warnings, 0) + self.assertEqual(result.checks, 1) + self.assertEqual(result.lines, 67) os.remove(inf) diff --git a/tools/scripts/define2mk.sed b/tools/scripts/define2mk.sed index 13e2845..c641edf 100644 --- a/tools/scripts/define2mk.sed +++ b/tools/scripts/define2mk.sed @@ -24,6 +24,8 @@ s/="\([0-9][0-9]*\)"/=\1/; # ... and from hex numbers s/="\(0[Xx][0-9a-fA-F][0-9a-fA-F]*\)"/=\1/; + # ... and from configs defined from other configs + s/="\(CONFIG_[A-Za-z0-9_][A-Za-z0-9_]*\)"/=$(\1)/; # Change '1' and empty values to "y" (not perfect, but # supports conditional compilation in the makefiles s/=$/=y/; |
