diff options
206 files changed, 7112 insertions, 2773 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index b8c1fdc..bf0ebb1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -303,8 +303,11 @@ Stefan Roese <sr@denx.de> bamboo PPC440EP bunbinga PPC405EP ebony PPC440GP + haleakala PPC405EXr katmai PPC440SPe + kilauea PPC405EX lwmon5 PPC440EPx + makalu PPC405EX ocotea PPC440GX p3p440 PPC440GP pcs440ep PPC440EP @@ -180,6 +180,8 @@ LIST_4xx=" \ ERIC \ EXBITGEN \ G2000 \ + haleakala \ + haleakala_nand \ hcu4 \ hcu5 \ HH405 \ @@ -187,8 +189,11 @@ LIST_4xx=" \ JSE \ KAREF \ katmai \ + kilauea \ + kilauea_nand \ luan \ lwmon5 \ + makalu \ METROBOX \ MIP405 \ MIP405T \ @@ -1217,12 +1217,29 @@ KAREF_config: unconfig katmai_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx katmai amcc +# Kilauea & Haleakala images are identical (recognized via PVR) +kilauea_config \ +haleakala_config: unconfig + @$(MKCONFIG) -n $@ -a kilauea ppc ppc4xx kilauea amcc + +kilauea_nand_config \ +haleakala_nand_config: unconfig + @mkdir -p $(obj)include $(obj)board/amcc/kilauea + @mkdir -p $(obj)nand_spl/board/amcc/kilauea + @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h + @$(MKCONFIG) -n $@ -a kilauea ppc ppc4xx kilauea amcc + @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/kilauea/config.tmp + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk + luan_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc lwmon5_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx lwmon5 +makalu_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx makalu amcc + METROBOX_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx metrobox sandburst diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 00c793a..c4eace5 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -67,13 +67,13 @@ const unsigned char cfg_simulate_spd_eeprom[128] = { 0x00, /* Module data width continued: +0 */ 0x04, /* 2.5 Volt */ 0x75, /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */ + 0x00, /* SDRAM Access from clock */ #ifdef CONFIG_DDR_ECC 0x02, /* ECC ON : 02 OFF : 00 */ #else 0x00, /* ECC ON : 02 OFF : 00 */ #endif - 0x82, /* refresh Rate Type: Normal (15.625us) + Self refresh */ - 0, + 0x82, /* refresh Rate Type: Normal (7.8us) + Self refresh */ 0, 0, 0x01, /* wcsbc = 1 */ diff --git a/board/amcc/bubinga/u-boot.lds b/board/amcc/bubinga/u-boot.lds index be03092..b08c999 100644 --- a/board/amcc/bubinga/u-boot.lds +++ b/board/amcc/bubinga/u-boot.lds @@ -62,19 +62,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/ebony/u-boot.lds b/board/amcc/ebony/u-boot.lds index 5a1c5b1..e32b030 100644 --- a/board/amcc/ebony/u-boot.lds +++ b/board/amcc/ebony/u-boot.lds @@ -68,19 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/ebony/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index a49066f..39a3ef1 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -24,21 +24,14 @@ #include <common.h> #include <ppc4xx.h> -#include <asm/processor.h> #include <i2c.h> -#include <asm-ppc/io.h> -#include <asm-ppc/gpio.h> - -#include "../cpu/ppc4xx/440spe_pcie.h" - -#undef PCIE_ENDPOINT -/* #define PCIE_ENDPOINT 1 */ +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/4xx_pcie.h> DECLARE_GLOBAL_DATA_PTR; -int ppc440spe_init_pcie_rootport(int port); -void ppc440spe_setup_pcie(struct pci_controller *hose, int port); - int board_early_init_f (void) { unsigned long mfr; @@ -224,10 +217,9 @@ int board_early_init_f (void) mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/ mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/ -/* SDR0_MFR should be part of Ethernet init */ - mfsdr (sdr_mfr, mfr); - mfr &= ~SDR0_MFR_ECS_MASK; -/* mtsdr(sdr_mfr, mfr); */ + mfsdr(sdr_mfr, mfr); + mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ + mtsdr(sdr_mfr, mfr); mtsdr(SDR0_PFC0, CFG_PFC0); @@ -396,6 +388,7 @@ void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + int ret = 0; char *env; unsigned int delay; @@ -409,12 +402,13 @@ void pcie_setup_hoses(int busno) if (!katmai_pcie_card_present(i)) continue; -#ifdef PCIE_ENDPOINT - if (ppc440spe_init_pcie_endport(i)) { -#else - if (ppc440spe_init_pcie_rootport(i)) { -#endif - printf("PCIE%d: initialization failed\n", i); + if (is_end_point(i)) + ret = ppc4xx_init_pcie_endport(i); + else + ret = ppc4xx_init_pcie_rootport(i); + if (ret) { + printf("PCIE%d: initialization as %s failed\n", i, + is_end_point(i) ? "endpoint" : "root-complex"); continue; } @@ -428,35 +422,33 @@ void pcie_setup_hoses(int busno) CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMSIZE, - PCI_REGION_MEM - ); + PCI_REGION_MEM); hose->region_count = 1; pci_register_hose(hose); -#ifdef PCIE_ENDPOINT - ppc440spe_setup_pcie_endpoint(hose, i); - /* - * Reson for no scanning is endpoint can not generate - * upstream configuration accesses. - */ -#else - ppc440spe_setup_pcie_rootpoint(hose, i); - - env = getenv ("pciscandelay"); - if (env != NULL) { - delay = simple_strtoul (env, NULL, 10); - if (delay > 5) - printf ("Warning, expect noticable delay before PCIe" - "scan due to 'pciscandelay' value!\n"); - mdelay (delay * 1000); + if (is_end_point(i)) { + ppc4xx_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ + } else { + ppc4xx_setup_pcie_rootpoint(hose, i); + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); + if (delay > 5) + printf("Warning, expect noticable delay before " + "PCIe scan due to 'pciscandelay' value!\n"); + mdelay(delay * 1000); + } + + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; } - - /* - * Config access can only go down stream - */ - hose->last_busno = pci_hose_scan(hose); - bus = hose->last_busno + 1; -#endif } } #endif /* defined(CONFIG_PCI) */ diff --git a/board/amcc/kilauea/Makefile b/board/amcc/kilauea/Makefile new file mode 100644 index 0000000..b8da25f --- /dev/null +++ b/board/amcc/kilauea/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o cmd_pll.o memory.o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/kilauea/cmd_pll.c b/board/amcc/kilauea/cmd_pll.c new file mode 100644 index 0000000..b2666dd --- /dev/null +++ b/board/amcc/kilauea/cmd_pll.c @@ -0,0 +1,297 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * ehnus: change pll frequency. + * Wed Sep 5 11:45:17 CST 2007 + * hsun@udtech.com.cn + */ + + +#include <common.h> +#include <config.h> +#include <command.h> +#include <i2c.h> + +#ifdef CONFIG_CMD_EEPROM + +#define EEPROM_CONF_OFFSET 0 +#define EEPROM_TEST_OFFSET 16 +#define EEPROM_SDSTP_PARAM 16 + +#define PLL_NAME_MAX 12 +#define BUF_STEP 8 + +/* eeprom_wirtes 8Byte per op. */ +#define EEPROM_ALTER_FREQ(freq) \ + do { \ + int __i; \ + for (__i = 0; __i < 2; __i++) \ + eeprom_write (CFG_I2C_EEPROM_ADDR, \ + EEPROM_CONF_OFFSET + __i*BUF_STEP, \ + pll_select[freq], \ + BUF_STEP + __i*BUF_STEP); \ + } while (0) + +#define PDEBUG +#ifdef PDEBUG +#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET) +#else +#define PLL_DEBUG +#endif + +typedef enum { + PLL_ebc20, + PLL_333, + PLL_4001, + PLL_4002, + PLL_533, + PLL_600, + PLL_666, /* For now, kilauea can't support */ + RCONF, + WTEST, + PLL_TOTAL +} pll_freq_t; + +static const char +pll_name[][PLL_NAME_MAX] = { + "PLL_ebc20", + "PLL_333", + "PLL_400@1", + "PLL_400@2", + "PLL_533", + "PLL_600", + "PLL_666", + "RCONF", + "WTEST", + "" +}; + +/* + * ehnus: + */ +static uchar +pll_select[][EEPROM_SDSTP_PARAM] = { + /* 0: CPU 333MHz EBC 20MHz, for test only */ + { + 0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 0: 333 */ + { + 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 1: 400_266 */ + { + 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 2: 400 */ + { + 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 3: 533 */ + { + 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 4: 600 */ + { + 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 5: 666 */ + { + 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + {} +}; + +static uchar +testbuf[EEPROM_SDSTP_PARAM] = { + 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff +}; + +static void +pll_debug(int off) +{ + int i; + uchar buffer[EEPROM_SDSTP_PARAM]; + + memset(buffer, 0, sizeof(buffer)); + eeprom_read(CFG_I2C_EEPROM_ADDR, off, + buffer, EEPROM_SDSTP_PARAM); + + printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off); + for (i = 0; i < EEPROM_SDSTP_PARAM; i++) + printf("%02x ", buffer[i]); + printf("\n"); +} + +static void +test_write(void) +{ + printf("Debug: test eeprom_write ... "); + + /* + * Write twice, 8 bytes per write + */ + eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET, + testbuf, 8); + eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8, + testbuf, 16); + printf("done\n"); + + pll_debug(EEPROM_TEST_OFFSET); +} + +int +do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char c = '\0'; + pll_freq_t pll_freq; + if (argc < 2) { + printf("Usage: \n%s\n", cmdtp->usage); + goto ret; + } + + for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) + if (!strcmp(pll_name[pll_freq], argv[1])) + break; + + switch (pll_freq) { + case PLL_ebc20: + case PLL_333: + case PLL_4001: + case PLL_4002: + case PLL_533: + case PLL_600: + EEPROM_ALTER_FREQ(pll_freq); + break; + + case PLL_666: /* not support */ + printf("Choose this option will result in a boot failure." + "\nContinue? (Y/N): "); + + c = getc(); putc('\n'); + + if ((c == 'y') || (c == 'Y')) { + EEPROM_ALTER_FREQ(pll_freq); + break; + } + goto ret; + + case RCONF: + pll_debug(EEPROM_CONF_OFFSET); + goto ret; + case WTEST: + printf("DEBUG: write test\n"); + test_write(); + goto ret; + + default: + printf("Invalid options" + "\n\nUsage: \n%s\n", cmdtp->usage); + goto ret; + } + + printf("PLL set to %s, " + "reset the board to take effect\n", pll_name[pll_freq]); + + PLL_DEBUG; +ret: + return 0; +} + +U_BOOT_CMD( + pllalter, CFG_MAXARGS, 1, do_pll_alter, + "pllalter- change pll frequence \n", + "pllalter <selection> - change pll frequence \n\n\ + ** New freq take effect after reset. ** \n\ + ----------------------------------------------\n\ + PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\ + \t Same as PLL_333 \n\ + \t except \n\ + \t EBC: 20 MHz \n\ + ----------------------------------------------\n\ + PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 666 MHz \n\ + \t CPU: 333 MHz \n\ + \t PLB: 166 MHz \n\ + \t OPB: 83 MHz \n\ + \t DDR: 83 MHz \n\ + ------------------------------------------------\n\ + PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 800 MHz \n\ + \t CPU: 400 MHz \n\ + \t PLB: 133 MHz \n\ + \t OPB: 66 MHz \n\ + \t DDR: 133 MHz \n\ + ------------------------------------------------\n\ + PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 800 MHz \n\ + \t CPU: 400 MHz \n\ + \t PLB: 200 MHz \n\ + \t OPB: 100 MHz \n\ + \t DDR: 200 MHz \n\ + ----------------------------------------------\n\ + PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 1066 MHz \n\ + \t CPU: 533 MHz \n\ + \t PLB: 177 MHz \n\ + \t OPB: 88 MHz \n\ + \t DDR: 177 MHz \n\ + ----------------------------------------------\n\ + PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 1200 MHz \n\ + \t CPU: 600 MHz \n\ + \t PLB: 200 MHz \n\ + \t OPB: 100 MHz \n\ + \t DDR: 200 MHz \n\ + ----------------------------------------------\n\ + PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 1333 MHz \n\ + \t CPU: 666 MHz \n\ + \t PLB: 166 MHz \n\ + \t OPB: 83 MHz \n\ + \t DDR: 166 MHz \n\ + -----------------------------------------------\n\ + RCONF: Read current eeprom configuration. \n\ + -----------------------------------------------\n\ + WTEST: Test EEPROM write with predefined values\n\ + -----------------------------------------------\n" + ); + +#endif /* (CONFIG_COMMANDS & CFG_CMD_EEPROM) */ diff --git a/board/amcc/kilauea/config.mk b/board/amcc/kilauea/config.mk new file mode 100644 index 0000000..f5800eb --- /dev/null +++ b/board/amcc/kilauea/config.mk @@ -0,0 +1,32 @@ +# +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE +TEXT_BASE = 0xFFFA0000 +endif + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S new file mode 100644 index 0000000..4338744 --- /dev/null +++ b/board/amcc/kilauea/init.S @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Based on code provided from UDTech and AMCC + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <ppc4xx.h> + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#define mtsdram_as(reg, value) \ + addi r4,0,reg ; \ + mtdcr memcfga,r4 ; \ + addis r4,0,value@h ; \ + ori r4,r4,value@l ; \ + mtdcr memcfgd,r4 ; + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + + /* + * DDR2 setup + */ + + /* Following the DDR Core Manual, here is the initialization */ + + /* Step 1 */ + + /* Step 2 */ + + /* Step 3 */ + + /* base=00000000, size=256MByte (6), mode=7 (n*10*8) */ + mtsdram_as(SDRAM_MB0CF, 0x00006701); + + /* SET SDRAM_MB1CF - Not enabled */ + mtsdram_as(SDRAM_MB1CF, 0x00000000); + + /* SET SDRAM_MB2CF - Not enabled */ + mtsdram_as(SDRAM_MB2CF, 0x00000000); + + /* SET SDRAM_MB3CF - Not enabled */ + mtsdram_as(SDRAM_MB3CF, 0x00000000); + + /* SDRAM_CLKTR: Adv Addr clock by 90 deg */ + mtsdram_as(SDRAM_CLKTR, 0x80000000); + + /* Refresh Time register (0x30) Refresh every 7.8125uS */ + mtsdram_as(SDRAM_RTR, 0x06180000); + + /* SDRAM_SDTR1 */ + mtsdram_as(SDRAM_SDTR1, 0x80201000); + + /* SDRAM_SDTR2 */ + mtsdram_as(SDRAM_SDTR2, 0x32204232); + + /* SDRAM_SDTR3 */ + mtsdram_as(SDRAM_SDTR3, 0x080b0d1a); + + mtsdram_as(SDRAM_MMODE, 0x00000442); + mtsdram_as(SDRAM_MEMODE, 0x00000404); + + /* SDRAM0_MCOPT1 (0X20) No ECC Gen */ + mtsdram_as(SDRAM_MCOPT1, 0x04322000); + + /* NOP */ + mtsdram_as(SDRAM_INITPLR0, 0xa8380000); + /* precharge 3 DDR clock cycle */ + mtsdram_as(SDRAM_INITPLR1, 0x81900400); + /* EMR2 twr = 2tck */ + mtsdram_as(SDRAM_INITPLR2, 0x81020000); + /* EMR3 twr = 2tck */ + mtsdram_as(SDRAM_INITPLR3, 0x81030000); + /* EMR DLL ENABLE twr = 2tck */ + mtsdram_as(SDRAM_INITPLR4, 0x81010404); + /* MR w/ DLL reset + * Note: 5 is CL. May need to be changed + */ + mtsdram_as(SDRAM_INITPLR5, 0x81000542); + /* precharge 3 DDR clock cycle */ + mtsdram_as(SDRAM_INITPLR6, 0x81900400); + /* Auto-refresh trfc = 26tck */ + mtsdram_as(SDRAM_INITPLR7, 0x8D080000); + /* Auto-refresh trfc = 26tck */ + mtsdram_as(SDRAM_INITPLR8, 0x8D080000); + /* Auto-refresh */ + mtsdram_as(SDRAM_INITPLR9, 0x8D080000); + /* Auto-refresh */ + mtsdram_as(SDRAM_INITPLR10, 0x8D080000); + /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */ + mtsdram_as(SDRAM_INITPLR11, 0x81000442); + mtsdram_as(SDRAM_INITPLR12, 0x81010780); + mtsdram_as(SDRAM_INITPLR13, 0x81010400); + mtsdram_as(SDRAM_INITPLR14, 0x00000000); + mtsdram_as(SDRAM_INITPLR15, 0x00000000); + + /* SET MCIF0_CODT Die Termination On */ + mtsdram_as(SDRAM_CODT, 0x0080f837); + mtsdram_as(SDRAM_MODT0, 0x01800000); + mtsdram_as(SDRAM_MODT1, 0x00000000); + + mtsdram_as(SDRAM_WRDTR, 0x00000000); + + /* SDRAM0_MCOPT2 (0X21) Start initialization */ + mtsdram_as(SDRAM_MCOPT2, 0x20000000); + + /* Step 5 */ + lis r3,0x1 /* 400000 = wait 100ms */ + mtctr r3 + +pll_wait: + bdnz pll_wait + + /* Step 6 */ + + /* SDRAM_DLCR */ + mtsdram_as(SDRAM_DLCR, 0x030000a5); + + /* SDRAM_RDCC */ + mtsdram_as(SDRAM_RDCC, 0x40000000); + + /* SDRAM_RQDC */ + mtsdram_as(SDRAM_RQDC, 0x80000038); + + /* SDRAM_RFDC */ + mtsdram_as(SDRAM_RFDC, 0x00000209); + + /* Enable memory controller */ + mtsdram_as(SDRAM_MCOPT2, 0x28000000); +#endif /* #ifndef CONFIG_NAND_U_BOOT */ + + blr diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c new file mode 100644 index 0000000..96c0dd4 --- /dev/null +++ b/board/amcc/kilauea/kilauea.c @@ -0,0 +1,391 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <ppc405.h> +#include <libfdt.h> +#include <asm/processor.h> +#include <asm/io.h> + +#if defined(CONFIG_PCI) +#include <pci.h> +#include <asm/4xx_pcie.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * Board early initialization function + */ +int board_early_init_f (void) +{ + u32 val; + + /*--------------------------------------------------------------------+ + | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board. + +--------------------------------------------------------------------+ + +---------------------------------------------------------------------+ + |Interrupt| Source | Pol. | Sensi.| Crit. | + +---------+-----------------------------------+-------+-------+-------+ + | IRQ 00 | UART0 | High | Level | Non | + | IRQ 01 | UART1 | High | Level | Non | + | IRQ 02 | IIC0 | High | Level | Non | + | IRQ 03 | TBD | High | Level | Non | + | IRQ 04 | TBD | High | Level | Non | + | IRQ 05 | EBM | High | Level | Non | + | IRQ 06 | BGI | High | Level | Non | + | IRQ 07 | IIC1 | Rising| Edge | Non | + | IRQ 08 | SPI | High | Lvl/ed| Non | + | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | + | IRQ 10 | MAL TX EOB | High | Level | Non | + | IRQ 11 | MAL RX EOB | High | Level | Non | + | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | + | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | + | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | + | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | + | IRQ 16 | PCIE0 AL | high | Level | Non | + | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | + | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | + | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | + | IRQ 20 | PCIE0 TCR | High | Level | Non | + | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | + | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | + | IRQ 23 | Security EIP-94 | High | Level | Non | + | IRQ 24 | EMAC0 interrupt | High | Level | Non | + | IRQ 25 | EMAC1 interrupt | High | Level | Non | + | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | + | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | + | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | + | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | + | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | + | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | + |---------------------------------------------------------------------- + | IRQ 32 | MAL Serr | High | Level | Non | + | IRQ 33 | MAL Txde | High | Level | Non | + | IRQ 34 | MAL Rxde | High | Level | Non | + | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | + | IRQ 36 | PCIE0 DCR Error | High | Level | Non | + | IRQ 37 | EBC | High |Lvl Edg| Non | + | IRQ 38 | NDFC | High | Level | Non | + | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | + | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | + | IRQ 41 | PCIE1 AL | high | Level | Non | + | IRQ 42 | PCIE1 VPD access | rising| edge | Non | + | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | + | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | + | IRQ 45 | PCIE1 TCR | High | Level | Non | + | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | + | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | + | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | + | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | + | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | + | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | + | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | + | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | + | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | + | IRQ 55 | Serial ROM | High | Level | Non | + | IRQ 56 | GPT Decrement Pulse | High | Level | Non | + | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | + | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | + | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | + | IRQ 60 | EMAC0 Wake-up | High | Level | Non | + | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | + | IRQ 62 | EMAC1 Wake-up | High | Level | Non | + |---------------------------------------------------------------------- + | IRQ 64 | PE0 AL | High | Level | Non | + | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | + | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | + | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | + | IRQ 68 | PE0 TCR | High | Level | Non | + | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | + | IRQ 70 | PE0 DCR Error | High | Level | Non | + | IRQ 71 | Reserved | N/A | N/A | Non | + | IRQ 72 | PE1 AL | High | Level | Non | + | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | + | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | + | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | + | IRQ 76 | PE1 TCR | High | Level | Non | + | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | + | IRQ 78 | PE1 DCR Error | High | Level | Non | + | IRQ 79 | Reserved | N/A | N/A | Non | + | IRQ 80 | PE2 AL | High | Level | Non | + | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | + | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | + | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | + | IRQ 84 | PE2 TCR | High | Level | Non | + | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | + | IRQ 86 | PE2 DCR Error | High | Level | Non | + | IRQ 87 | Reserved | N/A | N/A | Non | + | IRQ 88 | External IRQ(5) | Progr | Progr | Non | + | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | + | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | + | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | + | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | + | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | + | IRQ 94 | Reserved | N/A | N/A | Non | + | IRQ 95 | Reserved | N/A | N/A | Non | + |--------------------------------------------------------------------- + +---------+-----------------------------------+-------+-------+------*/ + /*--------------------------------------------------------------------+ + | Initialise UIC registers. Clear all interrupts. Disable all + | interrupts. + | Set critical interrupt values. Set interrupt polarities. Set + | interrupt trigger levels. Make bit 0 High priority. Clear all + | interrupts again. + +-------------------------------------------------------------------*/ + + mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic2er, 0x00000000); /* disable all interrupts */ + mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */ + mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */ + mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ + + mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic1er, 0x00000000); /* disable all interrupts */ + mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */ + mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */ + mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic1sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */ + + mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */ + /* Except cascade UIC0 and UIC1 */ + mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */ + mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */ + mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ + + /* + * Note: Some cores are still in reset when the chip starts, so + * take them out of reset + */ + mtsdr(SDR0_SRST, 0); + + /* + * Configure FPGA register with PCIe reset + */ + out_be32((void *)CFG_FPGA_BASE, 0xff570cc0); /* assert PCIe reset */ + mdelay(50); + out_be32((void *)CFG_FPGA_BASE, 0xff570cc3); /* deassert PCIe reset */ + + /* Configure 405EX for NAND usage */ + val = SDR0_CUST0_MUX_NDFC_SEL | + SDR0_CUST0_NDFC_ENABLE | + SDR0_CUST0_NDFC_BW_8_BIT | + SDR0_CUST0_NRB_BUSY | + (0x80000000 >> (28 + CFG_NAND_CS)); + mtsdr(SDR0_CUST0, val); + + /* + * Configure PFC (Pin Function Control) registers + * -> Enable USB + */ + val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; + mtsdr(SDR0_PFC1, val); + + return 0; +} + +int misc_init_r(void) +{ +#ifdef CFG_ENV_IS_IN_FLASH + /* Monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); +#endif + + return 0; +} + +int board_emac_count(void) +{ + u32 pvr = get_pvr(); + + /* + * 405EXr only has one EMAC interface, 405EX has two + */ + if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA)) + return 1; + else + return 2; +} + +static int board_pcie_count(void) +{ + u32 pvr = get_pvr(); + + /* + * 405EXr only has one EMAC interface, 405EX has two + */ + if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA)) + return 1; + else + return 2; +} + +int checkboard (void) +{ + char *s = getenv("serial#"); + u32 pvr = get_pvr(); + + if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA)) + printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board"); + else + printf("Board: Kilauea - AMCC PPC405EX Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int pci_pre_init(struct pci_controller * hose ) +{ + return 0; +} +#endif /* defined(CONFIG_PCI) */ + +#ifdef CONFIG_PCI +static struct pci_controller pcie_hose[2] = {{0},{0}}; + +void pcie_setup_hoses(int busno) +{ + struct pci_controller *hose; + int i, bus; + int ret = 0; + bus = busno; + char *env; + unsigned int delay; + + for (i = 0; i < board_pcie_count(); i++) { + + if (is_end_point(i)) + ret = ppc4xx_init_pcie_endport(i); + else + ret = ppc4xx_init_pcie_rootport(i); + if (ret) { + printf("PCIE%d: initialization as %s failed\n", i, + is_end_point(i) ? "endpoint" : "root-complex"); + continue; + } + + hose = &pcie_hose[i]; + hose->first_busno = bus; + hose->last_busno = bus; + hose->current_busno = bus; + + /* setup mem resource */ + pci_set_region(hose->regions + 0, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMSIZE, + PCI_REGION_MEM); + hose->region_count = 1; + pci_register_hose(hose); + + if (is_end_point(i)) { + ppc4xx_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ + } else { + ppc4xx_setup_pcie_rootpoint(hose, i); + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); + if (delay > 5) + printf("Warning, expect noticable delay before " + "PCIe scan due to 'pciscandelay' value!\n"); + mdelay(delay * 1000); + } + + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; + } + } +} +#endif + +#if defined(CONFIG_POST) +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} +#endif /* CONFIG_POST */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 0; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/amcc/kilauea/memory.c b/board/amcc/kilauea/memory.c new file mode 100644 index 0000000..1d7a3fa --- /dev/null +++ b/board/amcc/kilauea/memory.c @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <i2c.h> + +void sdram_init(void) +{ + return; +} + +long int initdram(int board_type) +{ + return (CFG_MBYTES_SDRAM << 20); +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + printf ("testdram\n"); +#if defined (CONFIG_NAND_U_BOOT) + return 0; +#endif + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) 0x00001000; + uint *p; + + for (p = pstart; p < pend; p++) { + *p = 0xaaaaaaaa; + } + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { +#if !defined (CONFIG_NAND_SPL) + printf ("SDRAM test fails at: %08x\n", (uint) p); +#endif + return 1; + } + } + + for (p = pstart; p < pend; p++) { + *p = 0x55555555; + } + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { +#if !defined (CONFIG_NAND_SPL) + printf ("SDRAM test fails at: %08x\n", (uint) p); +#endif + return 1; + } + } +#if !defined (CONFIG_NAND_SPL) + printf ("SDRAM test passed!!!\n"); +#endif + return 0; +} +#endif diff --git a/board/amcc/yucca/u-boot.lds.debug b/board/amcc/kilauea/u-boot-nand.lds index 474f922..a5dae0e 100644 --- a/board/amcc/yucca/u-boot.lds.debug +++ b/board/amcc/kilauea/u-boot-nand.lds @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002-2004 + * (C) Copyright 2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -23,8 +23,6 @@ OUTPUT_ARCH(powerpc) SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ SECTIONS { /* Read-only sections, merged into text segment: */ @@ -33,43 +31,36 @@ SECTIONS .hash : { *(.hash) } .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } .rela.ctors : { *(.rela.ctors) } .rel.dtors : { *(.rel.dtors) } .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } .plt : { *(.plt) } .text : { /* WARNING - the following is hand-optimized to fit within */ /* the sector layout of our flash chips! XXX FIXME XXX */ - cpu/ppc4xx/start.o (.text) - board/amcc/yucca/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) + cpu/ppc4xx/start.o (.text) -/* common/environment.o(.text) */ + /* Align to next NAND block */ + . = ALIGN(0x4000); + common/environment.o (.ppcenv) + /* Keep some space here for redundant env and potential bad env blocks */ + . = ALIGN(0x10000); *(.text) *(.fixup) @@ -82,14 +73,13 @@ SECTIONS *(.rodata) *(.rodata1) *(.rodata.str1.4) - *(.eh_frame) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } .dtors : { *(.dtors) } /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; + . = (. + 0x00FF) & 0xFFFFFF00; _erotext = .; PROVIDE (erotext = .); .reloc : @@ -141,6 +131,7 @@ SECTIONS *(.bss) *(COMMON) } + _end = . ; PROVIDE (end = .); } diff --git a/board/amcc/kilauea/u-boot.lds b/board/amcc/kilauea/u-boot.lds new file mode 100644 index 0000000..390b3f3 --- /dev/null +++ b/board/amcc/kilauea/u-boot.lds @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ +/* To compile successfully, uncomment the following section. + * To go in ram, remove the section. + * Added by SunHe. + */ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 0067ce0..f964511 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -39,6 +39,8 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ ************************************************************************/ int board_early_init_f(void) { + u32 mfr; + mtebc( pb0ap, 0x03800000 ); /* set chip selects */ mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ mtebc( pb1ap, 0x03800000 ); @@ -64,6 +66,10 @@ int board_early_init_f(void) mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ mtdcr( uic0sr, 0xffffffff ); + mfsdr(sdr_mfr, mfr); + mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ + mtsdr(sdr_mfr, mfr); + return 0; } diff --git a/board/amcc/makalu/Makefile b/board/amcc/makalu/Makefile new file mode 100644 index 0000000..b8da25f --- /dev/null +++ b/board/amcc/makalu/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o cmd_pll.o memory.o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend *~ + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/amcc/makalu/cmd_pll.c b/board/amcc/makalu/cmd_pll.c new file mode 100644 index 0000000..b2666dd --- /dev/null +++ b/board/amcc/makalu/cmd_pll.c @@ -0,0 +1,297 @@ +/* + * (C) Copyright 2000, 2001 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * ehnus: change pll frequency. + * Wed Sep 5 11:45:17 CST 2007 + * hsun@udtech.com.cn + */ + + +#include <common.h> +#include <config.h> +#include <command.h> +#include <i2c.h> + +#ifdef CONFIG_CMD_EEPROM + +#define EEPROM_CONF_OFFSET 0 +#define EEPROM_TEST_OFFSET 16 +#define EEPROM_SDSTP_PARAM 16 + +#define PLL_NAME_MAX 12 +#define BUF_STEP 8 + +/* eeprom_wirtes 8Byte per op. */ +#define EEPROM_ALTER_FREQ(freq) \ + do { \ + int __i; \ + for (__i = 0; __i < 2; __i++) \ + eeprom_write (CFG_I2C_EEPROM_ADDR, \ + EEPROM_CONF_OFFSET + __i*BUF_STEP, \ + pll_select[freq], \ + BUF_STEP + __i*BUF_STEP); \ + } while (0) + +#define PDEBUG +#ifdef PDEBUG +#define PLL_DEBUG pll_debug(EEPROM_CONF_OFFSET) +#else +#define PLL_DEBUG +#endif + +typedef enum { + PLL_ebc20, + PLL_333, + PLL_4001, + PLL_4002, + PLL_533, + PLL_600, + PLL_666, /* For now, kilauea can't support */ + RCONF, + WTEST, + PLL_TOTAL +} pll_freq_t; + +static const char +pll_name[][PLL_NAME_MAX] = { + "PLL_ebc20", + "PLL_333", + "PLL_400@1", + "PLL_400@2", + "PLL_533", + "PLL_600", + "PLL_666", + "RCONF", + "WTEST", + "" +}; + +/* + * ehnus: + */ +static uchar +pll_select[][EEPROM_SDSTP_PARAM] = { + /* 0: CPU 333MHz EBC 20MHz, for test only */ + { + 0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 0: 333 */ + { + 0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 1: 400_266 */ + { + 0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 2: 400 */ + { + 0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 3: 533 */ + { + 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 4: 600 */ + { + 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + /* 5: 666 */ + { + 0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + }, + + {} +}; + +static uchar +testbuf[EEPROM_SDSTP_PARAM] = { + 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff +}; + +static void +pll_debug(int off) +{ + int i; + uchar buffer[EEPROM_SDSTP_PARAM]; + + memset(buffer, 0, sizeof(buffer)); + eeprom_read(CFG_I2C_EEPROM_ADDR, off, + buffer, EEPROM_SDSTP_PARAM); + + printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off); + for (i = 0; i < EEPROM_SDSTP_PARAM; i++) + printf("%02x ", buffer[i]); + printf("\n"); +} + +static void +test_write(void) +{ + printf("Debug: test eeprom_write ... "); + + /* + * Write twice, 8 bytes per write + */ + eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET, + testbuf, 8); + eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8, + testbuf, 16); + printf("done\n"); + + pll_debug(EEPROM_TEST_OFFSET); +} + +int +do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + char c = '\0'; + pll_freq_t pll_freq; + if (argc < 2) { + printf("Usage: \n%s\n", cmdtp->usage); + goto ret; + } + + for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++) + if (!strcmp(pll_name[pll_freq], argv[1])) + break; + + switch (pll_freq) { + case PLL_ebc20: + case PLL_333: + case PLL_4001: + case PLL_4002: + case PLL_533: + case PLL_600: + EEPROM_ALTER_FREQ(pll_freq); + break; + + case PLL_666: /* not support */ + printf("Choose this option will result in a boot failure." + "\nContinue? (Y/N): "); + + c = getc(); putc('\n'); + + if ((c == 'y') || (c == 'Y')) { + EEPROM_ALTER_FREQ(pll_freq); + break; + } + goto ret; + + case RCONF: + pll_debug(EEPROM_CONF_OFFSET); + goto ret; + case WTEST: + printf("DEBUG: write test\n"); + test_write(); + goto ret; + + default: + printf("Invalid options" + "\n\nUsage: \n%s\n", cmdtp->usage); + goto ret; + } + + printf("PLL set to %s, " + "reset the board to take effect\n", pll_name[pll_freq]); + + PLL_DEBUG; +ret: + return 0; +} + +U_BOOT_CMD( + pllalter, CFG_MAXARGS, 1, do_pll_alter, + "pllalter- change pll frequence \n", + "pllalter <selection> - change pll frequence \n\n\ + ** New freq take effect after reset. ** \n\ + ----------------------------------------------\n\ + PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\ + \t Same as PLL_333 \n\ + \t except \n\ + \t EBC: 20 MHz \n\ + ----------------------------------------------\n\ + PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 666 MHz \n\ + \t CPU: 333 MHz \n\ + \t PLB: 166 MHz \n\ + \t OPB: 83 MHz \n\ + \t DDR: 83 MHz \n\ + ------------------------------------------------\n\ + PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 800 MHz \n\ + \t CPU: 400 MHz \n\ + \t PLB: 133 MHz \n\ + \t OPB: 66 MHz \n\ + \t DDR: 133 MHz \n\ + ------------------------------------------------\n\ + PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 800 MHz \n\ + \t CPU: 400 MHz \n\ + \t PLB: 200 MHz \n\ + \t OPB: 100 MHz \n\ + \t DDR: 200 MHz \n\ + ----------------------------------------------\n\ + PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 1066 MHz \n\ + \t CPU: 533 MHz \n\ + \t PLB: 177 MHz \n\ + \t OPB: 88 MHz \n\ + \t DDR: 177 MHz \n\ + ----------------------------------------------\n\ + PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 1200 MHz \n\ + \t CPU: 600 MHz \n\ + \t PLB: 200 MHz \n\ + \t OPB: 100 MHz \n\ + \t DDR: 200 MHz \n\ + ----------------------------------------------\n\ + PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\ + \t VCO: 1333 MHz \n\ + \t CPU: 666 MHz \n\ + \t PLB: 166 MHz \n\ + \t OPB: 83 MHz \n\ + \t DDR: 166 MHz \n\ + -----------------------------------------------\n\ + RCONF: Read current eeprom configuration. \n\ + -----------------------------------------------\n\ + WTEST: Test EEPROM write with predefined values\n\ + -----------------------------------------------\n" + ); + +#endif /* (CONFIG_COMMANDS & CFG_CMD_EEPROM) */ diff --git a/board/amcc/makalu/config.mk b/board/amcc/makalu/config.mk new file mode 100644 index 0000000..a46b197 --- /dev/null +++ b/board/amcc/makalu/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2000 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFFA0000 diff --git a/board/amcc/makalu/init.S b/board/amcc/makalu/init.S new file mode 100644 index 0000000..57c1774 --- /dev/null +++ b/board/amcc/makalu/init.S @@ -0,0 +1,148 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Based on code provided from Senao and AMCC + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <ppc4xx.h> + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#define mtsdram_as(reg, value) \ + addi r4,0,reg ; \ + mtdcr memcfga,r4 ; \ + addis r4,0,value@h ; \ + ori r4,r4,value@l ; \ + mtdcr memcfgd,r4 ; + + .globl ext_bus_cntlr_init +ext_bus_cntlr_init: + + /* + * DDR2 setup + */ + + /* Following the DDR Core Manual, here is the initialization */ + + /* Step 1 */ + + /* Step 2 */ + + /* Step 3 */ + + /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */ + mtsdram_as(SDRAM_MB0CF, 0x00005201); + + /* base=08000000, size=128MByte (5), mode=2 (n*10*4) */ + mtsdram_as(SDRAM_MB1CF, (0x08000000 >> 3) | 0x5201); + + /* SDRAM_CLKTR: Adv Addr clock by 90 deg */ + mtsdram_as(SDRAM_CLKTR,0x80000000); + + /* Refresh Time register (0x30) Refresh every 7.8125uS */ + mtsdram_as(SDRAM_RTR, 0x06180000); + + /* SDRAM_SDTR1 */ + mtsdram_as(SDRAM_SDTR1, 0x80201000); + + /* SDRAM_SDTR2 */ + mtsdram_as(SDRAM_SDTR2, 0x32204232); + + /* SDRAM_SDTR3 */ + mtsdram_as(SDRAM_SDTR3, 0x080b0d1a); + + mtsdram_as(SDRAM_MMODE, 0x00000442); + mtsdram_as(SDRAM_MEMODE, 0x00000404); + + /* SDRAM0_MCOPT1 (0X20) No ECC Gen */ + mtsdram_as(SDRAM_MCOPT1, 0x04322000); + + /* NOP */ + mtsdram_as(SDRAM_INITPLR0, 0xa8380000); + /* precharge 3 DDR clock cycle */ + mtsdram_as(SDRAM_INITPLR1, 0x81900400); + /* EMR2 twr = 2tck */ + mtsdram_as(SDRAM_INITPLR2, 0x81020000); + /* EMR3 twr = 2tck */ + mtsdram_as(SDRAM_INITPLR3, 0x81030000); + /* EMR DLL ENABLE twr = 2tck */ + mtsdram_as(SDRAM_INITPLR4, 0x81010404); + /* MR w/ DLL reset + * Note: 5 is CL. May need to be changed + */ + mtsdram_as(SDRAM_INITPLR5, 0x81000542); + /* precharge 3 DDR clock cycle */ + mtsdram_as(SDRAM_INITPLR6, 0x81900400); + /* Auto-refresh trfc = 26tck */ + mtsdram_as(SDRAM_INITPLR7, 0x8D080000); + /* Auto-refresh trfc = 26tck */ + mtsdram_as(SDRAM_INITPLR8, 0x8D080000); + /* Auto-refresh */ + mtsdram_as(SDRAM_INITPLR9, 0x8D080000); + /* Auto-refresh */ + mtsdram_as(SDRAM_INITPLR10, 0x8D080000); + /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */ + mtsdram_as(SDRAM_INITPLR11, 0x81000442); + mtsdram_as(SDRAM_INITPLR12, 0x81010780); + mtsdram_as(SDRAM_INITPLR13, 0x81010400); + mtsdram_as(SDRAM_INITPLR14, 0x00000000); + mtsdram_as(SDRAM_INITPLR15, 0x00000000); + + /* SET MCIF0_CODT Die Termination On */ + mtsdram_as(SDRAM_CODT, 0x0080f837); + mtsdram_as(SDRAM_MODT0, 0x01800000); +#if 0 /* test-only: not sure if 0 is ok when 2nd bank is used */ + mtsdram_as(SDRAM_MODT1, 0x00000000); +#endif + + mtsdram_as(SDRAM_WRDTR, 0x00000000); + + /* SDRAM0_MCOPT2 (0X21) Start initialization */ + mtsdram_as(SDRAM_MCOPT2, 0x20000000); + + /* Step 5 */ + lis r3,0x1 /* 400000 = wait 100ms */ + mtctr r3 + +pll_wait: + bdnz pll_wait + + /* Step 6 */ + + /* SDRAM_DLCR */ + mtsdram_as(SDRAM_DLCR, 0x030000a5); + + /* SDRAM_RDCC */ + mtsdram_as(SDRAM_RDCC, 0x40000000); + + /* SDRAM_RQDC */ + mtsdram_as(SDRAM_RQDC, 0x80000038); + + /* SDRAM_RFDC */ + mtsdram_as(SDRAM_RFDC, 0x00000209); + + /* Enable memory controller */ + mtsdram_as(SDRAM_MCOPT2, 0x28000000); + + blr diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c new file mode 100644 index 0000000..15e51f4 --- /dev/null +++ b/board/amcc/makalu/makalu.c @@ -0,0 +1,352 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <ppc4xx.h> +#include <ppc405.h> +#include <libfdt.h> +#include <asm/processor.h> +#include <asm/gpio.h> +#include <asm/io.h> + +#if defined(CONFIG_PCI) +#include <pci.h> +#include <asm/4xx_pcie.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * Board early initialization function + */ +int board_early_init_f (void) +{ + u32 val; + + /*--------------------------------------------------------------------+ + | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board. + +--------------------------------------------------------------------+ + +---------------------------------------------------------------------+ + |Interrupt| Source | Pol. | Sensi.| Crit. | + +---------+-----------------------------------+-------+-------+-------+ + | IRQ 00 | UART0 | High | Level | Non | + | IRQ 01 | UART1 | High | Level | Non | + | IRQ 02 | IIC0 | High | Level | Non | + | IRQ 03 | TBD | High | Level | Non | + | IRQ 04 | TBD | High | Level | Non | + | IRQ 05 | EBM | High | Level | Non | + | IRQ 06 | BGI | High | Level | Non | + | IRQ 07 | IIC1 | Rising| Edge | Non | + | IRQ 08 | SPI | High | Lvl/ed| Non | + | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | + | IRQ 10 | MAL TX EOB | High | Level | Non | + | IRQ 11 | MAL RX EOB | High | Level | Non | + | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | + | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | + | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | + | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | + | IRQ 16 | PCIE0 AL | high | Level | Non | + | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | + | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | + | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | + | IRQ 20 | PCIE0 TCR | High | Level | Non | + | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | + | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | + | IRQ 23 | Security EIP-94 | High | Level | Non | + | IRQ 24 | EMAC0 interrupt | High | Level | Non | + | IRQ 25 | EMAC1 interrupt | High | Level | Non | + | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | + | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | + | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | + | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | + | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | + | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | + |---------------------------------------------------------------------- + | IRQ 32 | MAL Serr | High | Level | Non | + | IRQ 33 | MAL Txde | High | Level | Non | + | IRQ 34 | MAL Rxde | High | Level | Non | + | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | + | IRQ 36 | PCIE0 DCR Error | High | Level | Non | + | IRQ 37 | EBC | High |Lvl Edg| Non | + | IRQ 38 | NDFC | High | Level | Non | + | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | + | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | + | IRQ 41 | PCIE1 AL | high | Level | Non | + | IRQ 42 | PCIE1 VPD access | rising| edge | Non | + | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | + | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | + | IRQ 45 | PCIE1 TCR | High | Level | Non | + | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | + | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | + | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | + | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | + | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | + | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | + | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | + | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | + | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | + | IRQ 55 | Serial ROM | High | Level | Non | + | IRQ 56 | GPT Decrement Pulse | High | Level | Non | + | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | + | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | + | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | + | IRQ 60 | EMAC0 Wake-up | High | Level | Non | + | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | + | IRQ 62 | EMAC1 Wake-up | High | Level | Non | + |---------------------------------------------------------------------- + | IRQ 64 | PE0 AL | High | Level | Non | + | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | + | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | + | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | + | IRQ 68 | PE0 TCR | High | Level | Non | + | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | + | IRQ 70 | PE0 DCR Error | High | Level | Non | + | IRQ 71 | Reserved | N/A | N/A | Non | + | IRQ 72 | PE1 AL | High | Level | Non | + | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | + | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | + | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | + | IRQ 76 | PE1 TCR | High | Level | Non | + | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | + | IRQ 78 | PE1 DCR Error | High | Level | Non | + | IRQ 79 | Reserved | N/A | N/A | Non | + | IRQ 80 | PE2 AL | High | Level | Non | + | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | + | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | + | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | + | IRQ 84 | PE2 TCR | High | Level | Non | + | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | + | IRQ 86 | PE2 DCR Error | High | Level | Non | + | IRQ 87 | Reserved | N/A | N/A | Non | + | IRQ 88 | External IRQ(5) | Progr | Progr | Non | + | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | + | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | + | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | + | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | + | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | + | IRQ 94 | Reserved | N/A | N/A | Non | + | IRQ 95 | Reserved | N/A | N/A | Non | + |--------------------------------------------------------------------- + +---------+-----------------------------------+-------+-------+------*/ + /*--------------------------------------------------------------------+ + | Initialise UIC registers. Clear all interrupts. Disable all + | interrupts. + | Set critical interrupt values. Set interrupt polarities. Set + | interrupt trigger levels. Make bit 0 High priority. Clear all + | interrupts again. + +-------------------------------------------------------------------*/ + + mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic2er, 0x00000000); /* disable all interrupts */ + mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */ + mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */ + mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ + + mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic1er, 0x00000000); /* disable all interrupts */ + mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */ + mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */ + mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic1sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */ + + mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ + mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */ + /* Except cascade UIC0 and UIC1 */ + mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */ + mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */ + mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */ + mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ + mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ + mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ + + /* + * Note: Some cores are still in reset when the chip starts, so + * take them out of reset + */ + mtsdr(SDR0_SRST, 0); + + /* Reset PCIe slots */ + gpio_write_bit(CFG_GPIO_PCIE_RST, 0); + udelay(100); + gpio_write_bit(CFG_GPIO_PCIE_RST, 1); + + /* + * Configure PFC (Pin Function Control) registers + * -> Enable USB + */ + val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; + mtsdr(SDR0_PFC1, val); + + return 0; +} + +int misc_init_r(void) +{ +#ifdef CFG_ENV_IS_IN_FLASH + /* Monitor protection ON by default */ + flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); +#endif + + return 0; +} + +int checkboard (void) +{ + char *s = getenv("serial#"); + + printf("Board: Makalu - AMCC PPC405EX Evaluation Board"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int pci_pre_init(struct pci_controller * hose ) +{ + return 0; +} +#endif /* defined(CONFIG_PCI) */ + +#ifdef CONFIG_PCI +static struct pci_controller pcie_hose[2] = {{0},{0}}; + +void pcie_setup_hoses(int busno) +{ + struct pci_controller *hose; + int i, bus; + int ret = 0; + bus = busno; + char *env; + unsigned int delay; + + for (i = 0; i < 2; i++) { + + if (is_end_point(i)) + ret = ppc4xx_init_pcie_endport(i); + else + ret = ppc4xx_init_pcie_rootport(i); + if (ret) { + printf("PCIE%d: initialization as %s failed\n", i, + is_end_point(i) ? "endpoint" : "root-complex"); + continue; + } + + hose = &pcie_hose[i]; + hose->first_busno = bus; + hose->last_busno = bus; + hose->current_busno = bus; + + /* setup mem resource */ + pci_set_region(hose->regions + 0, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, + CFG_PCIE_MEMSIZE, + PCI_REGION_MEM); + hose->region_count = 1; + pci_register_hose(hose); + + if (is_end_point(i)) { + ppc4xx_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ + } else { + ppc4xx_setup_pcie_rootpoint(hose, i); + env = getenv ("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); + if (delay > 5) + printf("Warning, expect noticable delay before " + "PCIe scan due to 'pciscandelay' value!\n"); + mdelay(delay * 1000); + } + + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; + } + } +} +#endif + +#if defined(CONFIG_POST) +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} +#endif /* CONFIG_POST */ + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 0; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/amcc/makalu/memory.c b/board/amcc/makalu/memory.c new file mode 100644 index 0000000..b03b60b --- /dev/null +++ b/board/amcc/makalu/memory.c @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> + +void sdram_init(void) +{ + return; +} + +long int initdram(int board_type) +{ + /* + * Same as on Kilauea, Makalu generates exception 0x200 + * (machine check) after trap_init() in board_init_f, + * when SDRAM is initialized here (late) and d-cache is + * used earlier as INIT_RAM. + * So for now, initialize DDR2 in init.S very early and + * also use it for INIT_RAM. Then this exception doesn't + * occur. + */ +#if 0 + u32 val; + + /* base=00000000, size=128MByte (5), mode=2 (n*10*4) */ + mtsdram(SDRAM_MB0CF, 0x00005201); + + /* SET SDRAM_MB1CF - Not enabled */ + mtsdram(SDRAM_MB1CF, 0x00000000); + + /* SET SDRAM_MB2CF - Not enabled */ + mtsdram(SDRAM_MB2CF, 0x00000000); + + /* SET SDRAM_MB3CF - Not enabled */ + mtsdram(SDRAM_MB3CF, 0x00000000); + + /* SDRAM_CLKTR: Adv Addr clock by 90 deg */ + mtsdram(SDRAM_CLKTR, 0x80000000); + + /* Refresh Time register (0x30) Refresh every 7.8125uS */ + mtsdram(SDRAM_RTR, 0x06180000); + + /* SDRAM_SDTR1 */ + mtsdram(SDRAM_SDTR1, 0x80201000); + + /* SDRAM_SDTR2 */ + mtsdram(SDRAM_SDTR2, 0x32204232); + + /* SDRAM_SDTR3 */ + mtsdram(SDRAM_SDTR3, 0x080b0d1a); + + mtsdram(SDRAM_MMODE, 0x00000442); + mtsdram(SDRAM_MEMODE, 0x00000404); + + /* SDRAM0_MCOPT1 (0X20) No ECC Gen */ + mtsdram(SDRAM_MCOPT1, 0x04322000); + + /* NOP */ + mtsdram(SDRAM_INITPLR0, 0xa8380000); + /* precharge 3 DDR clock cycle */ + mtsdram(SDRAM_INITPLR1, 0x81900400); + /* EMR2 twr = 2tck */ + mtsdram(SDRAM_INITPLR2, 0x81020000); + /* EMR3 twr = 2tck */ + mtsdram(SDRAM_INITPLR3, 0x81030000); + /* EMR DLL ENABLE twr = 2tck */ + mtsdram(SDRAM_INITPLR4, 0x81010404); + /* MR w/ DLL reset + * Note: 5 is CL. May need to be changed + */ + mtsdram(SDRAM_INITPLR5, 0x81000542); + /* precharge 3 DDR clock cycle */ + mtsdram(SDRAM_INITPLR6, 0x81900400); + /* Auto-refresh trfc = 26tck */ + mtsdram(SDRAM_INITPLR7, 0x8D080000); + /* Auto-refresh trfc = 26tck */ + mtsdram(SDRAM_INITPLR8, 0x8D080000); + /* Auto-refresh */ + mtsdram(SDRAM_INITPLR9, 0x8D080000); + /* Auto-refresh */ + mtsdram(SDRAM_INITPLR10, 0x8D080000); + /* MRS - normal operation; wait 2 cycle (set wait to tMRD) */ + mtsdram(SDRAM_INITPLR11, 0x81000442); + mtsdram(SDRAM_INITPLR12, 0x81010780); + mtsdram(SDRAM_INITPLR13, 0x81010400); + mtsdram(SDRAM_INITPLR14, 0x00000000); + mtsdram(SDRAM_INITPLR15, 0x00000000); + + /* SET MCIF0_CODT Die Termination On */ + mtsdram(SDRAM_CODT, 0x0080f837); + mtsdram(SDRAM_MODT0, 0x01800000); + mtsdram(SDRAM_MODT1, 0x00000000); + + mtsdram(SDRAM_WRDTR, 0x00000000); + + /* SDRAM0_MCOPT2 (0X21) Start initialization */ + mtsdram(SDRAM_MCOPT2, 0x20000000); + + /* Step 5 */ + do { + mfsdram(SDRAM_MCSTAT, val); + } while ((val & SDRAM_MCSTAT_MIC_COMP) != SDRAM_MCSTAT_MIC_COMP); + + /* Step 6 */ + + /* SDRAM_DLCR */ + mtsdram(SDRAM_DLCR, 0x030000a5); + + /* SDRAM_RDCC */ + mtsdram(SDRAM_RDCC, 0x40000000); + + /* SDRAM_RQDC */ + mtsdram(SDRAM_RQDC, 0x80000038); + + /* SDRAM_RFDC */ + mtsdram(SDRAM_RFDC, 0x00000209); + + /* Enable memory controller */ + mfsdram(SDRAM_MCOPT2, val); + val |= SDRAM_MCOPT2_DCEN_ENABLE; + mtsdram(SDRAM_MCOPT2, val); +#endif + return (CFG_MBYTES_SDRAM << 20); +} + +#if defined(CFG_DRAM_TEST) +int testdram (void) +{ + printf ("testdram\n"); +#if defined (CONFIG_NAND_U_BOOT) + return 0; +#endif + uint *pstart = (uint *) 0x00000000; + uint *pend = (uint *) 0x00001000; + uint *p; + + for (p = pstart; p < pend; p++) { + *p = 0xaaaaaaaa; + } + + for (p = pstart; p < pend; p++) { + if (*p != 0xaaaaaaaa) { +#if !defined (CONFIG_NAND_SPL) + printf ("SDRAM test fails at: %08x\n", (uint) p); +#endif + return 1; + } + } + + for (p = pstart; p < pend; p++) { + *p = 0x55555555; + } + + for (p = pstart; p < pend; p++) { + if (*p != 0x55555555) { +#if !defined (CONFIG_NAND_SPL) + printf ("SDRAM test fails at: %08x\n", (uint) p); +#endif + return 1; + } + } +#if !defined (CONFIG_NAND_SPL) + printf ("SDRAM test passed!!!\n"); +#endif + return 0; +} +#endif diff --git a/board/amcc/makalu/u-boot.lds b/board/amcc/makalu/u-boot.lds new file mode 100644 index 0000000..390b3f3 --- /dev/null +++ b/board/amcc/makalu/u-boot.lds @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ +/* To compile successfully, uncomment the following section. + * To go in ram, remove the section. + * Added by SunHe. + */ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/amcc/ocotea/u-boot.lds b/board/amcc/ocotea/u-boot.lds index 316fee8..0daca70 100644 --- a/board/amcc/ocotea/u-boot.lds +++ b/board/amcc/ocotea/u-boot.lds @@ -68,19 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/ocotea/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S index 5fe3af9..c7da521 100644 --- a/board/amcc/sequoia/init.S +++ b/board/amcc/sequoia/init.S @@ -98,7 +98,11 @@ tlbtab: #endif /* TLB-entry for DDR SDRAM (Up to 2GB) */ +#ifdef CONFIG_4xx_DCACHE + tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) +#else tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) +#endif #ifdef CFG_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ diff --git a/board/amcc/taihu/u-boot.lds b/board/amcc/taihu/u-boot.lds index be03092..b08c999 100644 --- a/board/amcc/taihu/u-boot.lds +++ b/board/amcc/taihu/u-boot.lds @@ -62,19 +62,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c index 57b9d1c..040b800 100644 --- a/board/amcc/taishan/showinfo.c +++ b/board/amcc/taishan/showinfo.c @@ -33,25 +33,25 @@ void show_reset_reg(void) /* read clock regsiter */ printf("===== Display reset and initialize register Start =========\n"); - mfclk(clk_pllc,reg); + mfcpr(clk_pllc,reg); printf("cpr_pllc = %#010x\n",reg); - mfclk(clk_plld,reg); + mfcpr(clk_plld,reg); printf("cpr_plld = %#010x\n",reg); - mfclk(clk_primad,reg); + mfcpr(clk_primad,reg); printf("cpr_primad = %#010x\n",reg); - mfclk(clk_primbd,reg); + mfcpr(clk_primbd,reg); printf("cpr_primbd = %#010x\n",reg); - mfclk(clk_opbd,reg); + mfcpr(clk_opbd,reg); printf("cpr_opbd = %#010x\n",reg); - mfclk(clk_perd,reg); + mfcpr(clk_perd,reg); printf("cpr_perd = %#010x\n",reg); - mfclk(clk_mald,reg); + mfcpr(clk_mald,reg); printf("cpr_mald = %#010x\n",reg); /* read sdr register */ diff --git a/board/amcc/taishan/u-boot.lds b/board/amcc/taishan/u-boot.lds index 664716e..b2be352 100644 --- a/board/amcc/taishan/u-boot.lds +++ b/board/amcc/taishan/u-boot.lds @@ -68,19 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/taishan/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/walnut/u-boot.lds b/board/amcc/walnut/u-boot.lds index 1dcbab5..fa75dde 100644 --- a/board/amcc/walnut/u-boot.lds +++ b/board/amcc/walnut/u-boot.lds @@ -62,19 +62,6 @@ SECTIONS /* the sector layout of our flash chips! XXX FIXME XXX */ cpu/ppc4xx/start.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/yosemite/u-boot.lds b/board/amcc/yosemite/u-boot.lds index a9a7b0a..978319f 100644 --- a/board/amcc/yosemite/u-boot.lds +++ b/board/amcc/yosemite/u-boot.lds @@ -68,19 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/yosemite/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/yucca/u-boot.lds b/board/amcc/yucca/u-boot.lds index 9df4f92..c9cf4db 100644 --- a/board/amcc/yucca/u-boot.lds +++ b/board/amcc/yucca/u-boot.lds @@ -68,19 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/amcc/yucca/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index d7cc384..52486cc 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -27,29 +27,17 @@ #include <common.h> #include <ppc4xx.h> -#include <asm/processor.h> #include <i2c.h> -#include <asm-ppc/io.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/4xx_pcie.h> #include "yucca.h" -#include "../cpu/ppc4xx/440spe_pcie.h" DECLARE_GLOBAL_DATA_PTR; -#undef PCIE_ENDPOINT -/* #define PCIE_ENDPOINT 1 */ - void fpga_init (void); -void get_sys_info(PPC440_SYS_INFO *board_cfg ); -int compare_to_true(char *str ); -char *remove_l_w_space(char *in_str ); -char *remove_t_w_space(char *in_str ); -int get_console_port(void); - -int ppc440spe_init_pcie_rootport(int port); -void ppc440spe_setup_pcie(struct pci_controller *hose, int port); - #define DEBUG_ENV #ifdef DEBUG_ENV #define DEBUGF(fmt,args...) printf(fmt ,##args) @@ -541,10 +529,10 @@ int board_early_init_f (void) mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ - /* SDR0_MFR should be part of Ethernet init */ - mfsdr (sdr_mfr, mfr); - mfr &= ~SDR0_MFR_ECS_MASK; - /*mtsdr(sdr_mfr, mfr);*/ + mfsdr(sdr_mfr, mfr); + mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ + mtsdr(sdr_mfr, mfr); + fpga_init(); return 0; @@ -850,6 +838,7 @@ void pcie_setup_hoses(int busno) { struct pci_controller *hose; int i, bus; + int ret = 0; char *env; unsigned int delay; @@ -863,14 +852,16 @@ void pcie_setup_hoses(int busno) if (!yucca_pcie_card_present(i)) continue; -#ifdef PCIE_ENDPOINT - yucca_setup_pcie_fpga_endpoint(i); - if (ppc440spe_init_pcie_endport(i)) { -#else - yucca_setup_pcie_fpga_rootpoint(i); - if (ppc440spe_init_pcie_rootport(i)) { -#endif - printf("PCIE%d: initialization failed\n", i); + if (is_end_point(i)) { + yucca_setup_pcie_fpga_endpoint(i); + ret = ppc4xx_init_pcie_endport(i); + } else { + yucca_setup_pcie_fpga_rootpoint(i); + ret = ppc4xx_init_pcie_rootport(i); + } + if (ret) { + printf("PCIE%d: initialization as %s failed\n", i, + is_end_point(i) ? "endpoint" : "root-complex"); continue; } @@ -884,35 +875,33 @@ void pcie_setup_hoses(int busno) CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, CFG_PCIE_MEMSIZE, - PCI_REGION_MEM - ); + PCI_REGION_MEM); hose->region_count = 1; pci_register_hose(hose); -#ifdef PCIE_ENDPOINT - ppc440spe_setup_pcie_endpoint(hose, i); - /* - * Reson for no scanning is endpoint can not generate - * upstream configuration accesses. - */ -#else - ppc440spe_setup_pcie_rootpoint(hose, i); - - env = getenv ("pciscandelay"); - if (env != NULL) { - delay = simple_strtoul (env, NULL, 10); - if (delay > 5) - printf ("Warning, expect noticable delay before PCIe" - "scan due to 'pciscandelay' value!\n"); - mdelay (delay * 1000); - } + if (is_end_point(i)) { + ppc4xx_setup_pcie_endpoint(hose, i); + /* + * Reson for no scanning is endpoint can not generate + * upstream configuration accesses. + */ + } else { + ppc4xx_setup_pcie_rootpoint(hose, i); + env = getenv("pciscandelay"); + if (env != NULL) { + delay = simple_strtoul(env, NULL, 10); + if (delay > 5) + printf("Warning, expect noticable delay before " + "PCIe scan due to 'pciscandelay' value!\n"); + mdelay(delay * 1000); + } - /* - * Config access can only go down stream - */ - hose->last_busno = pci_hose_scan(hose); - bus = hose->last_busno + 1; -#endif + /* + * Config access can only go down stream + */ + hose->last_busno = pci_hose_scan(hose); + bus = hose->last_busno + 1; + } } } #endif /* defined(CONFIG_PCI) */ diff --git a/board/amirix/ap1000/u-boot.lds b/board/amirix/ap1000/u-boot.lds index 109e7fe..3d5b575 100644 --- a/board/amirix/ap1000/u-boot.lds +++ b/board/amirix/ap1000/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/cray/L1/u-boot.lds b/board/cray/L1/u-boot.lds index cf4bbb9..6d3e171 100644 --- a/board/cray/L1/u-boot.lds +++ b/board/cray/L1/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS board/cray/L1/init.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/csb272/u-boot.lds b/board/csb272/u-boot.lds index d75d6d1..a664d0f 100644 --- a/board/csb272/u-boot.lds +++ b/board/csb272/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/csb472/u-boot.lds b/board/csb472/u-boot.lds index 14ac3fb..8765016 100644 --- a/board/csb472/u-boot.lds +++ b/board/csb472/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds index 481d291..d40ee62 100644 --- a/board/dave/PPChameleonEVB/u-boot.lds +++ b/board/dave/PPChameleonEVB/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/eric/u-boot.lds b/board/eric/u-boot.lds index 4a0e5b4..de51b3f 100644 --- a/board/eric/u-boot.lds +++ b/board/eric/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/esd/apc405/u-boot.lds b/board/esd/apc405/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/apc405/u-boot.lds +++ b/board/esd/apc405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/ar405/u-boot.lds b/board/esd/ar405/u-boot.lds index 3b9aa7c..64293d2 100644 --- a/board/esd/ar405/u-boot.lds +++ b/board/esd/ar405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/esd/ash405/u-boot.lds b/board/esd/ash405/u-boot.lds index 95854f2..b49e3ff 100644 --- a/board/esd/ash405/u-boot.lds +++ b/board/esd/ash405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/canbt/u-boot.lds b/board/esd/canbt/u-boot.lds index ff15b3f..aaaccbe 100644 --- a/board/esd/canbt/u-boot.lds +++ b/board/esd/canbt/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/cms700/u-boot.lds b/board/esd/cms700/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/cms700/u-boot.lds +++ b/board/esd/cms700/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/cpci2dp/u-boot.lds b/board/esd/cpci2dp/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/cpci2dp/u-boot.lds +++ b/board/esd/cpci2dp/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/cpci405/u-boot.lds b/board/esd/cpci405/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/cpci405/u-boot.lds +++ b/board/esd/cpci405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/cpci440/cpci440.c b/board/esd/cpci440/cpci440.c index 43d8a3b..caa6d55 100644 --- a/board/esd/cpci440/cpci440.c +++ b/board/esd/cpci440/cpci440.c @@ -79,7 +79,7 @@ int checkboard (void) printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor/1000000); printf("\tPLB: %lu MHz\n", sysinfo.freqPLB/1000000); printf("\tOPB: %lu MHz\n", sysinfo.freqOPB/1000000); - printf("\tEPB: %lu MHz\n", sysinfo.freqEPB/1000000); + printf("\tEBC: %lu MHz\n", sysinfo.freqEBC/1000000); /* * Disable sleep mode in LXT971 diff --git a/board/esd/cpci440/u-boot.lds b/board/esd/cpci440/u-boot.lds index 57220d3..b1b4ad2 100644 --- a/board/esd/cpci440/u-boot.lds +++ b/board/esd/cpci440/u-boot.lds @@ -73,7 +73,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/cpciiser4/u-boot.lds b/board/esd/cpciiser4/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/cpciiser4/u-boot.lds +++ b/board/esd/cpciiser4/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds index fef5b52..497177d 100644 --- a/board/esd/dasa_sim/u-boot.lds +++ b/board/esd/dasa_sim/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/iop480_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/dp405/u-boot.lds b/board/esd/dp405/u-boot.lds index 43f7765..43fe6ca 100644 --- a/board/esd/dp405/u-boot.lds +++ b/board/esd/dp405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/esd/du405/u-boot.lds b/board/esd/du405/u-boot.lds index 1cf375f..21c5044 100644 --- a/board/esd/du405/u-boot.lds +++ b/board/esd/du405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/hh405/u-boot.lds b/board/esd/hh405/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/hh405/u-boot.lds +++ b/board/esd/hh405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/hub405/u-boot.lds b/board/esd/hub405/u-boot.lds index 98338e9..852e9ed 100644 --- a/board/esd/hub405/u-boot.lds +++ b/board/esd/hub405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/esd/ocrtc/cmd_ocrtc.c b/board/esd/ocrtc/cmd_ocrtc.c index 4177f68..f83dfe8 100644 --- a/board/esd/ocrtc/cmd_ocrtc.c +++ b/board/esd/ocrtc/cmd_ocrtc.c @@ -25,7 +25,7 @@ #include <command.h> #include <pci.h> #include <pci_ids.h> -#include <405gp_pci.h> +#include <asm/4xx_pci.h> #if defined(CONFIG_CMD_BSP) diff --git a/board/esd/ocrtc/u-boot.lds b/board/esd/ocrtc/u-boot.lds index 476b4a0..8ff25fa 100644 --- a/board/esd/ocrtc/u-boot.lds +++ b/board/esd/ocrtc/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/pci405/cmd_pci405.c b/board/esd/pci405/cmd_pci405.c index 5b5ad8c..9a0bf1e 100644 --- a/board/esd/pci405/cmd_pci405.c +++ b/board/esd/pci405/cmd_pci405.c @@ -27,7 +27,7 @@ #include <net.h> #include <asm/io.h> #include <pci.h> -#include <405gp_pci.h> +#include <asm/4xx_pci.h> #include <asm/processor.h> #include "pci405.h" diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index e5d2273..c4ab072 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -26,7 +26,7 @@ #include <command.h> #include <malloc.h> #include <pci.h> -#include <405gp_pci.h> +#include <asm/4xx_pci.h> #include "pci405.h" diff --git a/board/esd/pci405/u-boot.lds b/board/esd/pci405/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/pci405/u-boot.lds +++ b/board/esd/pci405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/plu405/u-boot.lds b/board/esd/plu405/u-boot.lds index 43f7765..43fe6ca 100644 --- a/board/esd/plu405/u-boot.lds +++ b/board/esd/plu405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/esd/pmc405/u-boot.lds b/board/esd/pmc405/u-boot.lds index e84d69e..898963c 100644 --- a/board/esd/pmc405/u-boot.lds +++ b/board/esd/pmc405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/voh405/u-boot.lds b/board/esd/voh405/u-boot.lds index 43f7765..43fe6ca 100644 --- a/board/esd/voh405/u-boot.lds +++ b/board/esd/voh405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/esd/vom405/u-boot.lds b/board/esd/vom405/u-boot.lds index f7a20d1..8ba6ad5 100644 --- a/board/esd/vom405/u-boot.lds +++ b/board/esd/vom405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/esd/wuh405/u-boot.lds b/board/esd/wuh405/u-boot.lds index 95854f2..b49e3ff 100644 --- a/board/esd/wuh405/u-boot.lds +++ b/board/esd/wuh405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/exbitgen/u-boot.lds b/board/exbitgen/u-boot.lds index d5dea82..b482aea 100644 --- a/board/exbitgen/u-boot.lds +++ b/board/exbitgen/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/g2000/u-boot.lds b/board/g2000/u-boot.lds index 43f7765..43fe6ca 100644 --- a/board/g2000/u-boot.lds +++ b/board/g2000/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index d4547e2..399da8a 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -71,7 +71,7 @@ static u32 is_ecc_enabled(void) void board_add_ram_info(int use_default) { - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; u32 val; if (is_ecc_enabled()) diff --git a/board/ml2/u-boot.lds b/board/ml2/u-boot.lds index f8e9e33..26df77b 100644 --- a/board/ml2/u-boot.lds +++ b/board/ml2/u-boot.lds @@ -61,7 +61,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c index 278ad5c..8d4cbe8 100644 --- a/board/mpl/common/common_util.c +++ b/board/mpl/common/common_util.c @@ -36,11 +36,11 @@ #ifdef CONFIG_PIP405 #include "../pip405/pip405.h" -#include <405gp_pci.h> +#include <asm/4xx_pci.h> #endif #ifdef CONFIG_MIP405 #include "../mip405/mip405.h" -#include <405gp_pci.h> +#include <asm/4xx_pci.h> #endif DECLARE_GLOBAL_DATA_PTR; @@ -587,7 +587,7 @@ extern int get_boot_mode(void); void video_get_info_str (int line_number, char *info) { /* init video info strings for graphic console */ - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; char rev; int i,boot; unsigned long pvr; diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c index fd43008..6f53192 100644 --- a/board/mpl/common/flash.c +++ b/board/mpl/common/flash.c @@ -47,7 +47,7 @@ #if defined(CONFIG_PIP405) #include "../pip405/pip405.h" #endif -#include <405gp_pci.h> +#include <asm/4xx_pci.h> #else /* defined(CONFIG_PATI) */ #include <mpc5xx.h> #endif diff --git a/board/mpl/mip405/u-boot.lds b/board/mpl/mip405/u-boot.lds index ad5f273..dceb390 100644 --- a/board/mpl/mip405/u-boot.lds +++ b/board/mpl/mip405/u-boot.lds @@ -70,7 +70,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/mpl/pip405/u-boot.lds b/board/mpl/pip405/u-boot.lds index 11819a4..685f903 100644 --- a/board/mpl/pip405/u-boot.lds +++ b/board/mpl/pip405/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 9ee9ab5..cbb2839 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -72,7 +72,7 @@ void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); void board_add_ram_info(int use_default) { - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; u32 val; mfsdram(DDR0_22, val); val &= DDR0_22_CTRL_RAW_MASK; diff --git a/board/prodrive/alpr/u-boot.lds b/board/prodrive/alpr/u-boot.lds index 4f04089..697801e 100644 --- a/board/prodrive/alpr/u-boot.lds +++ b/board/prodrive/alpr/u-boot.lds @@ -68,19 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/prodrive/alpr/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/prodrive/p3p440/u-boot.lds b/board/prodrive/p3p440/u-boot.lds index 92bb740..0540a46 100644 --- a/board/prodrive/p3p440/u-boot.lds +++ b/board/prodrive/p3p440/u-boot.lds @@ -68,19 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/prodrive/p3p440/init.o (.text) - cpu/ppc4xx/kgdb.o (.text) - cpu/ppc4xx/traps.o (.text) - cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) - cpu/ppc4xx/cpu_init.o (.text) - cpu/ppc4xx/speed.o (.text) - common/dlmalloc.o (.text) - lib_generic/crc32.o (.text) - lib_ppc/extable.o (.text) - lib_generic/zlib.o (.text) - -/* . = env_offset;*/ -/* common/environment.o(.text)*/ *(.text) *(.fixup) diff --git a/board/sandburst/karef/u-boot.lds b/board/sandburst/karef/u-boot.lds index 9e9e990..36420ad 100644 --- a/board/sandburst/karef/u-boot.lds +++ b/board/sandburst/karef/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug index 47d80fa..b934c89 100644 --- a/board/sandburst/karef/u-boot.lds.debug +++ b/board/sandburst/karef/u-boot.lds.debug @@ -62,7 +62,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/sandburst/metrobox/u-boot.lds b/board/sandburst/metrobox/u-boot.lds index a17401a..e2178d2 100644 --- a/board/sandburst/metrobox/u-boot.lds +++ b/board/sandburst/metrobox/u-boot.lds @@ -72,7 +72,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug index fef4c42..914ff9c 100644 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ b/board/sandburst/metrobox/u-boot.lds.debug @@ -62,7 +62,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/sbc405/u-boot.lds b/board/sbc405/u-boot.lds index 39fba61..0c5b809 100644 --- a/board/sbc405/u-boot.lds +++ b/board/sbc405/u-boot.lds @@ -64,7 +64,7 @@ SECTIONS cpu/ppc4xx/start.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/sc3/u-boot.lds b/board/sc3/u-boot.lds index dc255d2..05052e5 100644 --- a/board/sc3/u-boot.lds +++ b/board/sc3/u-boot.lds @@ -66,7 +66,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/xilinx/ml300/ml300.c b/board/xilinx/ml300/ml300.c index 60f0bc2..58bfac0 100644 --- a/board/xilinx/ml300/ml300.c +++ b/board/xilinx/ml300/ml300.c @@ -108,7 +108,7 @@ ulong get_PCI_freq(void) { ulong val; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; get_sys_info(&sys_info); val = sys_info.freqPCI; diff --git a/board/xilinx/ml300/u-boot.lds b/board/xilinx/ml300/u-boot.lds index b6d748e..8c0edb7 100644 --- a/board/xilinx/ml300/u-boot.lds +++ b/board/xilinx/ml300/u-boot.lds @@ -62,7 +62,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) cpu/ppc4xx/4xx_enet.o (.text) diff --git a/board/xpedite1k/u-boot.lds b/board/xpedite1k/u-boot.lds index 0f08637..7484111 100644 --- a/board/xpedite1k/u-boot.lds +++ b/board/xpedite1k/u-boot.lds @@ -71,7 +71,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/board/xpedite1k/u-boot.lds.debug b/board/xpedite1k/u-boot.lds.debug index 5066326..6631793 100644 --- a/board/xpedite1k/u-boot.lds.debug +++ b/board/xpedite1k/u-boot.lds.debug @@ -61,7 +61,7 @@ SECTIONS cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/interrupts.o (.text) - cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/4xx_uart.o (.text) cpu/ppc4xx/cpu_init.o (.text) cpu/ppc4xx/speed.o (.text) common/dlmalloc.o (.text) diff --git a/common/serial.c b/common/serial.c index dee1cc0..b9916e2 100644 --- a/common/serial.c +++ b/common/serial.c @@ -41,7 +41,8 @@ struct serial_device *default_serial_console (void) || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) return &serial_scc_device; #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ - || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx) + || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \ + || defined(CONFIG_MPC5xxx) #if defined(CONFIG_CONS_INDEX) && defined(CFG_NS16550_SERIAL) #if (CONFIG_CONS_INDEX==1) return &eserial1_device; @@ -91,7 +92,8 @@ void serial_initialize (void) #endif #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ - || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx) + || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \ + || defined(CONFIG_MPC5xxx) serial_register(&serial0_device); serial_register(&serial1_device); #endif diff --git a/common/usb.c b/common/usb.c index 933afa9..4df01ea 100644 --- a/common/usb.c +++ b/common/usb.c @@ -53,7 +53,7 @@ #include <usb.h> #ifdef CONFIG_4xx -#include <405gp_pci.h> +#include <asm/4xx_pci.h> #endif #undef USB_DEBUG diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c index 19c4f76..42fd7fb 100644 --- a/cpu/ppc4xx/40x_spd_sdram.c +++ b/cpu/ppc4xx/40x_spd_sdram.c @@ -148,7 +148,7 @@ long int spd_sdram(int(read_spd)(uint addr)) int t_rc; int min_cas; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; unsigned long bus_period_x_10; /* diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index 4a4c6f2..b9cf5cb 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -251,10 +251,10 @@ void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")) * memory. * * If at some time this restriction doesn't apply anymore, just define - * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * CONFIG_4xx_DCACHE in the board config file and this code should setup * everything correctly. */ -#ifdef CFG_ENABLE_SDRAM_CACHE +#ifdef CONFIG_4xx_DCACHE #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ #else #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ @@ -345,7 +345,7 @@ long int spd_sdram(void) { */ check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); -#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) /* * Soft-reset SDRAM controller. */ @@ -645,7 +645,7 @@ static void program_rtr(unsigned long *dimm_populated, unsigned char refresh_rate_type; unsigned long refresh_interval; unsigned long sdram_rtr; - PPC440_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; /* * get the board info @@ -721,7 +721,7 @@ static void program_tr0(unsigned long *dimm_populated, unsigned long tcyc_2_0_ns_x_10; unsigned long tcyc_reg; unsigned long bus_period_x_10; - PPC440_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; unsigned long residue; /* @@ -1065,7 +1065,7 @@ static void program_tr1(void) unsigned char window_found; unsigned char fail_found; unsigned char pass_found; - PPC440_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; /* * get the board info @@ -1197,9 +1197,6 @@ static void program_tr1(void) } rdclt_average = ((max_start + max_end) >> 1); - if (rdclt_average >= 0x60) - while (1) - ; if (rdclt_average < 0) { rdclt_average = 0; diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 67ba5bd..e199294 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -120,10 +120,10 @@ * memory. * * If at some time this restriction doesn't apply anymore, just define - * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * CONFIG_4xx_DCACHE in the board config file and this code should setup * everything correctly. */ -#ifdef CFG_ENABLE_SDRAM_CACHE +#ifdef CONFIG_4xx_DCACHE #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ #else #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ @@ -623,7 +623,7 @@ static void get_spd_info(unsigned long *dimm_populated, void board_add_ram_info(int use_default) { - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; u32 val; if (is_ecc_enabled()) @@ -741,7 +741,7 @@ static void check_frequency(unsigned long *dimm_populated, unsigned long calc_cycle_time; unsigned long sdram_freq; unsigned long sdr_ddrpll; - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; /*------------------------------------------------------------------ * Get the board configuration info. @@ -1353,7 +1353,7 @@ static void program_mode(unsigned long *dimm_populated, unsigned long max_4_0_tcyc_ns_x_100; unsigned long max_5_0_tcyc_ns_x_100; unsigned long cycle_time_ns_x_100[3]; - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; unsigned char cas_2_0_available; unsigned char cas_2_5_available; unsigned char cas_3_0_available; @@ -1640,7 +1640,7 @@ static void program_rtr(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks) { - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; unsigned long max_refresh_rate; unsigned long dimm_num; unsigned long refresh_rate_type; @@ -1737,7 +1737,7 @@ static void program_tr(unsigned long *dimm_populated, unsigned long sdram_freq; unsigned long sdr_ddrpll; - PPC440_SYS_INFO board_cfg; + PPC4xx_SYS_INFO board_cfg; /*------------------------------------------------------------------ * Get the board configuration info. @@ -2048,14 +2048,10 @@ static void program_bxcf(unsigned long *dimm_populated, /*------------------------------------------------------------------ * Set the BxCF regs. First, wipe out the bank config registers. *-----------------------------------------------------------------*/ - mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF); - mtdcr(SDRAMC_CFGDATA, 0x00000000); - mtdcr(SDRAMC_CFGADDR, SDRAM_MB1CF); - mtdcr(SDRAMC_CFGDATA, 0x00000000); - mtdcr(SDRAMC_CFGADDR, SDRAM_MB2CF); - mtdcr(SDRAMC_CFGDATA, 0x00000000); - mtdcr(SDRAMC_CFGADDR, SDRAM_MB3CF); - mtdcr(SDRAMC_CFGDATA, 0x00000000); + mtsdram(SDRAM_MB0CF, 0x00000000); + mtsdram(SDRAM_MB1CF, 0x00000000); + mtsdram(SDRAM_MB2CF, 0x00000000); + mtsdram(SDRAM_MB3CF, 0x00000000); mode = SDRAM_BXCF_M_BE_ENABLE; @@ -2107,8 +2103,9 @@ static void program_bxcf(unsigned long *dimm_populated, bank_0_populated = 1; for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) { - mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF + ((dimm_num + bank_0_populated + ind_rank) << 2)); - mtdcr(SDRAMC_CFGDATA, mode); + mtsdram(SDRAM_MB0CF + + ((dimm_num + bank_0_populated + ind_rank) << 2), + mode); } } } diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 71a9e37..c20dc73 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -81,6 +81,9 @@ #include <common.h> #include <net.h> #include <asm/processor.h> +#include <asm/io.h> +#include <asm/cache.h> +#include <asm/mmu.h> #include <commproc.h> #include <ppc4xx.h> #include <ppc4xx_enet.h> @@ -105,7 +108,7 @@ #endif #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */ -#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */ +#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */ /* Ethernet Transmit and Receive Buffers */ /* AS.HARNOIS @@ -133,13 +136,15 @@ #define BI_PHYMODE_GMII 3 #define BI_PHYMODE_RTBI 4 #define BI_PHYMODE_TBI 5 -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #define BI_PHYMODE_SMII 6 #define BI_PHYMODE_MII 7 #endif -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || \ - defined(CONFIG_440GRX) || defined(CONFIG_440SP) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) #endif @@ -156,7 +161,14 @@ struct eth_device *emac0_dev = NULL; /* * Get count of EMAC devices (doesn't have to be the max. possible number * supported by the cpu) + * + * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the + * EMAC count is possible. As it is needed for the Kilauea/Haleakala + * 405EX/405EXr eval board, using the same binary. */ +#if defined(CONFIG_BOARD_EMAC_COUNT) +#define LAST_EMAC_NUM board_emac_count() +#else /* CONFIG_BOARD_EMAC_COUNT */ #if defined(CONFIG_HAS_ETH3) #define LAST_EMAC_NUM 4 #elif defined(CONFIG_HAS_ETH2) @@ -166,12 +178,23 @@ struct eth_device *emac0_dev = NULL; #else #define LAST_EMAC_NUM 1 #endif +#endif /* CONFIG_BOARD_EMAC_COUNT */ /* normal boards start with EMAC0 */ #if !defined(CONFIG_EMAC_NR_START) #define CONFIG_EMAC_NR_START 0 #endif +#if defined(CONFIG_405EX) || defined(CONFIG_440EPX) +#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev))) +#else +#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2)) +#endif + +#define MAL_RX_DESC_SIZE 2048 +#define MAL_TX_DESC_SIZE 2048 +#define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE) + /*-----------------------------------------------------------------------------+ * Prototypes and externals. *-----------------------------------------------------------------------------*/ @@ -189,6 +212,8 @@ extern int emac4xx_miiphy_read (char *devname, unsigned char addr, extern int emac4xx_miiphy_write (char *devname, unsigned char addr, unsigned char reg, unsigned short value); +int board_emac_count(void); + /*-----------------------------------------------------------------------------+ | ppc_4xx_eth_halt | Disable MAL channel, and EMACn @@ -197,11 +222,13 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) { EMAC_4XX_HW_PST hw_p = dev->priv; uint32_t failsafe = 10000; -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) unsigned long mfr; #endif - out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ + out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ /* 1st reset MAL channel */ /* Note: writing a 0 to a channel has no effect */ @@ -221,16 +248,20 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) } /* EMAC RESET */ -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) /* provide clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); mtsdr(sdr_mfr, mfr); #endif - out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); + out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) /* remove clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); @@ -329,8 +360,8 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) /* Ensure we setup mdio for this devnum and ONLY this devnum */ zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); - out32 (ZMII_FER, zmiifer); - out32 (RGMII_FER, rmiifer); + out_be32((void *)ZMII_FER, zmiifer); + out_be32((void *)RGMII_FER, rmiifer); return ((int)pfc1); } @@ -348,31 +379,31 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) switch (pfc1) { case SDR0_PFC1_SELECT_CONFIG_2: /* 1 x GMII port */ - out32 (ZMII_FER, 0x00); - out32 (RGMII_FER, 0x00000037); + out_be32((void *)ZMII_FER, 0x00); + out_be32((void *)RGMII_FER, 0x00000037); bis->bi_phymode[0] = BI_PHYMODE_GMII; bis->bi_phymode[1] = BI_PHYMODE_NONE; break; case SDR0_PFC1_SELECT_CONFIG_4: /* 2 x RGMII ports */ - out32 (ZMII_FER, 0x00); - out32 (RGMII_FER, 0x00000055); + out_be32((void *)ZMII_FER, 0x00); + out_be32((void *)RGMII_FER, 0x00000055); bis->bi_phymode[0] = BI_PHYMODE_RGMII; bis->bi_phymode[1] = BI_PHYMODE_RGMII; break; case SDR0_PFC1_SELECT_CONFIG_6: /* 2 x SMII ports */ - out32 (ZMII_FER, - ((ZMII_FER_SMII) << ZMII_FER_V(0)) | - ((ZMII_FER_SMII) << ZMII_FER_V(1))); - out32 (RGMII_FER, 0x00000000); + out_be32((void *)ZMII_FER, + ((ZMII_FER_SMII) << ZMII_FER_V(0)) | + ((ZMII_FER_SMII) << ZMII_FER_V(1))); + out_be32((void *)RGMII_FER, 0x00000000); bis->bi_phymode[0] = BI_PHYMODE_SMII; bis->bi_phymode[1] = BI_PHYMODE_SMII; break; case SDR0_PFC1_SELECT_CONFIG_1_2: /* only 1 x MII supported */ - out32 (ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); - out32 (RGMII_FER, 0x00000000); + out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); + out_be32((void *)RGMII_FER, 0x00000000); bis->bi_phymode[0] = BI_PHYMODE_MII; bis->bi_phymode[1] = BI_PHYMODE_NONE; break; @@ -381,17 +412,55 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) } /* Ensure we setup mdio for this devnum and ONLY this devnum */ - zmiifer = in32 (ZMII_FER); + zmiifer = in_be32((void *)ZMII_FER); zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); - out32 (ZMII_FER, zmiifer); + out_be32((void *)ZMII_FER, zmiifer); return ((int)0x0); } #endif /* CONFIG_440EPX */ +#if defined(CONFIG_405EX) +int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) +{ + u32 gmiifer = 0; + + /* + * Right now only 2*RGMII is supported. Please extend when needed. + * sr - 2007-09-19 + */ + switch (1) { + case 1: + /* 2 x RGMII ports */ + out_be32((void *)RGMII_FER, 0x00000055); + bis->bi_phymode[0] = BI_PHYMODE_RGMII; + bis->bi_phymode[1] = BI_PHYMODE_RGMII; + break; + case 2: + /* 2 x SMII ports */ + break; + default: + break; + } + + /* Ensure we setup mdio for this devnum and ONLY this devnum */ + gmiifer = in_be32((void *)RGMII_FER); + gmiifer |= (1 << (19-devnum)); + out_be32((void *)RGMII_FER, gmiifer); + + return ((int)0x0); +} +#endif /* CONFIG_405EX */ + +static inline void *malloc_aligned(u32 size, u32 align) +{ + return (void *)(((u32)malloc(size + align) + align - 1) & + ~(align - 1)); +} + static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) { - int i, j; + int i; unsigned long reg = 0; unsigned long msr; unsigned long speed; @@ -402,18 +471,22 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) unsigned short reg_short; #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) sys_info_t sysinfo; #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) int ethgroup = -1; #endif #endif #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) unsigned long mfr; #endif - + u32 bd_cached; + u32 bd_uncached = 0; EMAC_4XX_HW_PST hw_p = dev->priv; @@ -426,7 +499,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) /* Need to get the OPB frequency so we can access the PHY */ get_sys_info (&sysinfo); #endif @@ -476,53 +550,57 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* NOTE: Therefore, disable all other EMACS, since we handle */ /* NOTE: only one emac at a time */ reg = 0; - out32 (ZMII_FER, 0); + out_be32((void *)ZMII_FER, 0); udelay (100); #if defined(CONFIG_440EP) || defined(CONFIG_440GR) - out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); + out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); #elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); #elif defined(CONFIG_440GP) /* set RMII mode */ - out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0); + out_be32((void *)ZMII_FER, ZMII_RMII | ZMII_MDI0); #else if ((devnum == 0) || (devnum == 1)) { - out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); + out_be32((void *)ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); } else { /* ((devnum == 2) || (devnum == 3)) */ - out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); - out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | - (RGMII_FER_RGMII << RGMII_FER_V (3)))); + out_be32((void *)ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum)); + out_be32((void *)RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) | + (RGMII_FER_RGMII << RGMII_FER_V (3)))); } #endif - out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); + out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ +#if defined(CONFIG_405EX) + ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); +#endif __asm__ volatile ("eieio"); /* reset emac so we have access to the phy */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) /* provide clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum); mtsdr(sdr_mfr, mfr); #endif - out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); - __asm__ volatile ("eieio"); + out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); failsafe = 1000; - while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { + while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { udelay (1000); failsafe--; } if (failsafe <= 0) printf("\nProblem resetting EMAC!\n"); -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) /* remove clocks for EMAC internal loopback */ mfsdr (sdr_mfr, mfr); mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum); @@ -531,7 +609,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) /* Whack the M1 register */ mode_reg = 0x0; mode_reg &= ~0x00000038; @@ -545,7 +624,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) else mode_reg |= EMAC_M1_OBCI_GT100; - out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); + out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ /* wait for PHY to complete auto negotiation */ @@ -591,7 +670,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) #if defined(CONFIG_CIS8201_PHY) /* @@ -702,11 +782,11 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif /* Set ZMII/RGMII speed according to the phy link speed */ - reg = in32 (ZMII_SSR); + reg = in_be32((void *)ZMII_SSR); if ( (speed == 100) || (speed == 1000) ) - out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); + out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); else - out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); + out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); if ((devnum == 2) || (devnum == 3)) { if (speed == 1000) @@ -719,11 +799,12 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) printf("Error in RGMII Speed\n"); return -1; } - out32 (RGMII_SSR, reg); + out_be32((void *)RGMII_SSR, reg); } #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) if (speed == 1000) reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); else if (speed == 100) @@ -734,13 +815,14 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) printf("Error in RGMII Speed\n"); return -1; } - out32 (RGMII_SSR, reg); + out_be32((void *)RGMII_SSR, reg); #endif /* set the Mal configuration reg */ #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); #else @@ -751,91 +833,58 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) } #endif - /* Free "old" buffers */ - if (hw_p->alloc_tx_buf) - free (hw_p->alloc_tx_buf); - if (hw_p->alloc_rx_buf) - free (hw_p->alloc_rx_buf); - /* * Malloc MAL buffer desciptors, make sure they are * aligned on cache line boundary size * (401/403/IOP480 = 16, 405 = 32) * and doesn't cross cache block boundaries. */ - hw_p->alloc_tx_buf = - (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) + - ((2 * CFG_CACHELINE_SIZE) - 2)); - if (NULL == hw_p->alloc_tx_buf) - return -1; - if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) { - hw_p->tx = - (mal_desc_t *) ((int) hw_p->alloc_tx_buf + - CFG_CACHELINE_SIZE - - ((int) hw_p-> - alloc_tx_buf & CACHELINE_MASK)); - } else { - hw_p->tx = hw_p->alloc_tx_buf; - } + if (hw_p->first_init == 0) { + debug("*** Allocating descriptor memory ***\n"); - hw_p->alloc_rx_buf = - (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) + - ((2 * CFG_CACHELINE_SIZE) - 2)); - if (NULL == hw_p->alloc_rx_buf) { - free(hw_p->alloc_tx_buf); - hw_p->alloc_tx_buf = NULL; - return -1; - } + bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096); + if (!bd_cached) { + printf("%s: Error allocating MAL descriptor buffers!\n"); + return -1; + } - if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) { - hw_p->rx = - (mal_desc_t *) ((int) hw_p->alloc_rx_buf + - CFG_CACHELINE_SIZE - - ((int) hw_p-> - alloc_rx_buf & CACHELINE_MASK)); - } else { - hw_p->rx = hw_p->alloc_rx_buf; +#ifdef CONFIG_4xx_DCACHE + flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE - 1); + bd_uncached = bis->bi_memsize; + program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE, + TLB_WORD2_I_ENABLE); +#else + bd_uncached = bd_cached; +#endif + hw_p->tx_phys = bd_cached; + hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE; + hw_p->tx = (mal_desc_t *)(bd_uncached); + hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE); + debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx); } for (i = 0; i < NUM_TX_BUFF; i++) { hw_p->tx[i].ctrl = 0; hw_p->tx[i].data_len = 0; - if (hw_p->first_init == 0) { - hw_p->txbuf_ptr = - (char *) malloc (ENET_MAX_MTU_ALIGNED); - if (NULL == hw_p->txbuf_ptr) { - free(hw_p->alloc_rx_buf); - free(hw_p->alloc_tx_buf); - hw_p->alloc_rx_buf = NULL; - hw_p->alloc_tx_buf = NULL; - for(j = 0; j < i; j++) { - free(hw_p->tx[i].data_ptr); - hw_p->tx[i].data_ptr = NULL; - } - } - } + if (hw_p->first_init == 0) + hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE, + L1_CACHE_BYTES); hw_p->tx[i].data_ptr = hw_p->txbuf_ptr; if ((NUM_TX_BUFF - 1) == i) hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP; hw_p->tx_run[i] = -1; -#if 0 - printf ("TX_BUFF %d @ 0x%08lx\n", i, - (ulong) hw_p->tx[i].data_ptr); -#endif + debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr); } for (i = 0; i < NUM_RX_BUFF; i++) { hw_p->rx[i].ctrl = 0; hw_p->rx[i].data_len = 0; - /* rx[i].data_ptr = (char *) &rx_buff[i]; */ - hw_p->rx[i].data_ptr = (char *) NetRxPackets[i]; + hw_p->rx[i].data_ptr = (char *)NetRxPackets[i]; if ((NUM_RX_BUFF - 1) == i) hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP; hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; hw_p->rx_ready[i] = -1; -#if 0 - printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) hw_p->rx[i].data_ptr); -#endif + debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr); } reg = 0x00000000; @@ -844,7 +893,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) reg = reg << 8; reg |= dev->enetaddr[1]; - out32 (EMAC_IAH + hw_p->hw_addr, reg); + out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg); reg = 0x00000000; reg |= dev->enetaddr[2]; /* set low address */ @@ -855,21 +904,21 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) reg = reg << 8; reg |= dev->enetaddr[5]; - out32 (EMAC_IAL + hw_p->hw_addr, reg); + out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg); switch (devnum) { case 1: /* setup MAL tx & rx channel pointers */ #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) - mtdcr (maltxctp2r, hw_p->tx); + mtdcr (maltxctp2r, hw_p->tx_phys); #else - mtdcr (maltxctp1r, hw_p->tx); + mtdcr (maltxctp1r, hw_p->tx_phys); #endif #if defined(CONFIG_440) mtdcr (maltxbattr, 0x0); mtdcr (malrxbattr, 0x0); #endif - mtdcr (malrxctp1r, hw_p->rx); + mtdcr (malrxctp1r, hw_p->rx_phys); /* set RX buffer size */ mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); break; @@ -878,17 +927,17 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* setup MAL tx & rx channel pointers */ mtdcr (maltxbattr, 0x0); mtdcr (malrxbattr, 0x0); - mtdcr (maltxctp2r, hw_p->tx); - mtdcr (malrxctp2r, hw_p->rx); + mtdcr (maltxctp2r, hw_p->tx_phys); + mtdcr (malrxctp2r, hw_p->rx_phys); /* set RX buffer size */ mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16); break; case 3: /* setup MAL tx & rx channel pointers */ mtdcr (maltxbattr, 0x0); - mtdcr (maltxctp3r, hw_p->tx); + mtdcr (maltxctp3r, hw_p->tx_phys); mtdcr (malrxbattr, 0x0); - mtdcr (malrxctp3r, hw_p->rx); + mtdcr (malrxctp3r, hw_p->rx_phys); /* set RX buffer size */ mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); break; @@ -900,8 +949,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) mtdcr (maltxbattr, 0x0); mtdcr (malrxbattr, 0x0); #endif - mtdcr (maltxctp0r, hw_p->tx); - mtdcr (malrxctp0r, hw_p->rx); + mtdcr (maltxctp0r, hw_p->tx_phys); + mtdcr (malrxctp0r, hw_p->rx_phys); /* set RX buffer size */ mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16); break; @@ -916,10 +965,10 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); /* set transmit enable & receive enable */ - out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); + out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); /* set receive fifo to 4k and tx fifo to 2k */ - mode_reg = in32 (EMAC_M1 + hw_p->hw_addr); + mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K; /* set speed */ @@ -940,46 +989,46 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) if (duplex == FULL) mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; - out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); + out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); /* Enable broadcast and indvidual address */ /* TBS: enabling runts as some misbehaved nics will send runts */ - out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); + out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); /* we probably need to set the tx mode1 reg? maybe at tx time */ /* set transmit request threshold register */ - out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ + out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ /* set receive low/high water mark register */ #if defined(CONFIG_440) /* 440s has a 64 byte burst length */ - out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); + out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); #else /* 405s have a 16 byte burst length */ - out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); + out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); #endif /* defined(CONFIG_440) */ - out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); + out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); /* Set fifo limit entry in tx mode 0 */ - out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003); + out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003); /* Frame gap set */ - out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); + out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); /* Set EMAC IER */ hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; if (speed == _100BASET) hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; - out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ - out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); + out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ + out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); if (hw_p->first_init == 0) { /* * Connect interrupt service routines */ - irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2), - (interrupt_handler_t *) enetInt, dev); + irq_install_handler(ETH_IRQ_NUM(hw_p->devnum), + (interrupt_handler_t *) enetInt, dev); } mtmsr (msr); /* enable interrupts again */ @@ -1015,6 +1064,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); + flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len - 1); /*-----------------------------------------------------------------------+ * set TX Buffer busy, and send it @@ -1030,8 +1080,8 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, __asm__ volatile ("eieio"); - out32 (EMAC_TXM0 + hw_p->hw_addr, - in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); + out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, + in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); #ifdef INFO_4XX_ENET hw_p->stats.pkts_tx++; #endif @@ -1041,7 +1091,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, *-----------------------------------------------------------------------*/ time_start = get_timer (0); while (1) { - temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr); + temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr); /* loop until either TINT turns on or 3 seconds elapse */ if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { /* transmit is done, so now check for errors @@ -1059,7 +1109,7 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, } -#if defined (CONFIG_440) +#if defined (CONFIG_440) || defined(CONFIG_405EX) #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) /* @@ -1073,7 +1123,8 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, #define UIC0SR uic0sr #endif -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #define UICMSR_ETHX uic0msr #define UICSR_ETHX uic0sr #else @@ -1149,7 +1200,7 @@ int enetInt (struct eth_device *dev) /* port by port dispatch of emac interrupts */ if (hw_p->devnum == 0) { if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */ - emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); + emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); serviced = 1; @@ -1168,7 +1219,7 @@ int enetInt (struct eth_device *dev) #if !defined(CONFIG_440SP) if (hw_p->devnum == 1) { if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */ - emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); + emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); serviced = 1; @@ -1186,7 +1237,7 @@ int enetInt (struct eth_device *dev) #if defined (CONFIG_440GX) if (hw_p->devnum == 2) { if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */ - emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); + emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); serviced = 1; @@ -1204,7 +1255,7 @@ int enetInt (struct eth_device *dev) if (hw_p->devnum == 3) { if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */ - emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); + emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); serviced = 1; @@ -1316,7 +1367,7 @@ int enetInt (struct eth_device *dev) /* port by port dispatch of emac interrupts */ if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */ - emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); + emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); if ((hw_p->emac_ier & emac_isr) != 0) { emac_err (dev, emac_isr); serviced = 1; @@ -1390,7 +1441,7 @@ static void emac_err (struct eth_device *dev, unsigned long isr) EMAC_4XX_HW_PST hw_p = dev->priv; printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); - out32 (EMAC_ISR + hw_p->hw_addr, isr); + out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr); } /*-----------------------------------------------------------------------------+ @@ -1513,6 +1564,9 @@ static int ppc_4xx_eth_rx (struct eth_device *dev) /* Pass the packet up to the protocol layers. */ /* NetReceive(NetRxPackets[rxIdx], length - 4); */ /* NetReceive(NetRxPackets[i], length); */ + invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr, + (u32)hw_p->rx[user_index].data_ptr + + length - 4 - 1); NetReceive (NetRxPackets[user_index], length - 4); /* Free Recv Buffer */ hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; @@ -1601,7 +1655,11 @@ int ppc_4xx_eth_initialize (bd_t * bis) bis->bi_phynum[3] = CONFIG_PHY3_ADDR; bis->bi_phymode[2] = 2; bis->bi_phymode[3] = 2; +#endif +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) ppc_4xx_eth_setup_bridge(0, bis); #endif @@ -1649,7 +1707,9 @@ int ppc_4xx_eth_initialize (bd_t * bis) if (0 == virgin) { /* set the MAL IER ??? names may change with new spec ??? */ -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) mal_ier = MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE | MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ; diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/4xx_pci.c index 282e7a1..a68c419 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -72,7 +72,7 @@ #include <common.h> #include <command.h> #if !defined(CONFIG_440) -#include <405gp_pci.h> +#include <asm/4xx_pci.h> #endif #include <asm/processor.h> #include <pci.h> @@ -592,4 +592,15 @@ void pci_init_board(void) } #endif /* CONFIG_440 */ + +#if defined(CONFIG_405EX) +void pci_init_board(void) +{ +#ifdef CONFIG_PCI_SCAN_SHOW + printf("PCI: Bus Dev VenId DevId Class Int\n"); +#endif + pcie_setup_hoses(0); +} +#endif /* CONFIG_405EX */ + #endif /* CONFIG_PCI */ diff --git a/cpu/ppc4xx/440spe_pcie.c b/cpu/ppc4xx/4xx_pcie.c index 3eac0ae..3af9862 100644 --- a/cpu/ppc4xx/440spe_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -20,15 +20,21 @@ * */ +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + #include <asm/processor.h> #include <asm-ppc/io.h> #include <ppc4xx.h> #include <common.h> #include <pci.h> -#if defined(CONFIG_440SPE) && defined(CONFIG_PCI) +#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX)) && \ + defined(CONFIG_PCI) -#include "440spe_pcie.h" +#include <asm/4xx_pcie.h> enum { PTYPE_ENDPOINT = 0x0, @@ -40,6 +46,20 @@ enum { LNKW_X8 = 0x8 }; +static int validate_endpoint(struct pci_controller *hose) +{ + if (hose->cfg_data == (u8 *)CFG_PCIE0_CFGBASE) + return (is_end_point(0)); + else if (hose->cfg_data == (u8 *)CFG_PCIE1_CFGBASE) + return (is_end_point(1)); +#if CFG_PCIE_NR_PORTS > 2 + else if (hose->cfg_data == (u8 *)CFG_PCIE2_CFGBASE) + return (is_end_point(2)); +#endif + + return 0; +} + static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) { u8 *base = (u8*)hose->cfg_data; @@ -50,8 +70,10 @@ static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) base = (u8*)CFG_PCIE0_XCFGBASE; if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE) base = (u8*)CFG_PCIE1_XCFGBASE; +#if CFG_PCIE_NR_PORTS > 2 if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE) base = (u8*)CFG_PCIE2_XCFGBASE; +#endif } return base; @@ -63,8 +85,10 @@ static void pcie_dmer_disable(void) mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA); mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE), mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA); +#if CFG_PCIE_NR_PORTS > 2 mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE), mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA); +#endif } static void pcie_dmer_enable(void) @@ -73,8 +97,10 @@ static void pcie_dmer_enable(void) mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA); mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE), mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA); +#if CFG_PCIE_NR_PORTS > 2 mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE), mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); +#endif } static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, @@ -83,6 +109,9 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, u8 *address; *val = 0; + if (validate_endpoint(hose)) + return 0; /* No upstream config access */ + /* * Bus numbers are relative to hose->first_busno */ @@ -115,6 +144,7 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, */ pcie_dmer_disable (); + debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset); switch (len) { case 1: *val = in_8(hose->cfg_data + offset); @@ -137,6 +167,9 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, u8 *address; + if (validate_endpoint(hose)) + return 0; /* No upstream config access */ + /* * Bus numbers are relative to hose->first_busno */ @@ -222,7 +255,8 @@ int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val); } -static void ppc440spe_setup_utl(u32 port) { +#if defined(CONFIG_440SPE) +static void ppc4xx_setup_utl(u32 port) { volatile void *utl_base = NULL; @@ -333,7 +367,7 @@ static int check_error(void) /* * Initialize PCI Express core */ -int ppc440spe_init_pcie(void) +int ppc4xx_init_pcie(void) { int time_out = 20; @@ -366,13 +400,223 @@ int ppc440spe_init_pcie(void) } return 0; } +#else +static void ppc4xx_setup_utl(u32 port) +{ + u32 utl_base; + + /* + * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK + */ + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CFG_PCIE0_UTLBASE); + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); + break; + + case 1: + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CFG_PCIE1_UTLBASE); + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); + + break; + } + utl_base = (port==0) ? CFG_PCIE0_UTLBASE : CFG_PCIE1_UTLBASE; + + /* + * Set buffer allocations and then assert VRB and TXE. + */ + out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000); + out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000); + out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000); + out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000); + out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000); + out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000); + out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000); + out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066); + + out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c); + out_be32((u32 *)(utl_base + PEUTL_RCSTA), + in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000); +} + +int ppc4xx_init_pcie(void) +{ + /* + * Nothing to do on 405EX + */ + return 0; +} +#endif /* - * Yucca board as End point and root point setup + * Board-specific pcie initialization + * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed + */ + +/* + * Initialize various parts of the PCI Express core for our port: + * + * - Set as a root port and enable max width + * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). + * - Set up UTL configuration. + * - Increase SERDES drive strength to levels suggested by AMCC. + * - De-assert RSTPYN, RSTDL and RSTGU. + * + * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it + * with default setting 0x11310000. The register has new fields, + * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core + * hang. + */ +#if defined(CONFIG_440SPE) +int __ppc4xx_init_pcie_port_hw(int port, int rootport) +{ + u32 val = 1 << 24; + u32 utlset1; + + if (rootport) { + val = PTYPE_ROOT_PORT << 20; + utlset1 = 0x21222222; + } else { + val = PTYPE_LEGACY_ENDPOINT << 20; + utlset1 = 0x20222222; + } + + if (port == 0) + val |= LNKW_X8 << 12; + else + val |= LNKW_X4 << 12; + + SDR_WRITE(SDRN_PESDR_DLPSET(port), val); + SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1); + if (!ppc440spe_revB()) + SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000); + SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000); + SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000); + SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000); + SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000); + if (port == 0) { + SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); + } + SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) & + ~(1 << 24 | 1 << 16)) | 1 << 12); + + return 0; +} +#endif /* CONFIG_440SPE */ + +#if defined(CONFIG_405EX) +int __ppc4xx_init_pcie_port_hw(int port, int rootport) +{ + u32 val; + + if (rootport) + val = 0x00401000; + else + val = 0x00101000; + + SDR_WRITE(SDRN_PESDR_DLPSET(port), val); + SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000); + SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000); + SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000); + SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003); + + /* Assert the PE0_PHY reset */ + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000); + udelay(1000); + + /* deassert the PE0_hotreset */ + if (is_end_point(port)) + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000); + else + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000); + + /* poll for phy !reset */ + while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000)) + ; + + /* deassert the PE0_gpl_utl_reset */ + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000); + + if (port == 0) + mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */ + else + mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */ + + return 0; +} +#endif /* CONFIG_405EX */ + +int ppc4xx_init_pcie_port_hw(int port, int rootport) +__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw"))); + +/* + * We map PCI Express configuration access into the 512MB regions + * + * NOTICE: revB is very strict about PLB real addressess and ranges to + * be mapped for config space; it seems to only work with d_nnnn_nnnn + * range (hangs the core upon config transaction attempts when set + * otherwise) while revA uses c_nnnn_nnnn. + * + * For revA: + * PCIE0: 0xc_4000_0000 + * PCIE1: 0xc_8000_0000 + * PCIE2: 0xc_c000_0000 + * + * For revB: + * PCIE0: 0xd_0000_0000 + * PCIE1: 0xd_2000_0000 + * PCIE2: 0xd_4000_0000 + * + * For 405EX: + * PCIE0: 0xa000_0000 + * PCIE1: 0xc000_0000 + */ +static inline u64 ppc4xx_get_cfgaddr(int port) +{ +#if defined(CONFIG_405EX) + if (port == 0) + return (u64)CFG_PCIE0_CFGBASE; + else + return (u64)CFG_PCIE1_CFGBASE; +#endif +#if defined(CONFIG_440SPE) + if (ppc440spe_revB()) { + switch (port) { + default: /* to satisfy compiler */ + case 0: + return 0x0000000d00000000ULL; + case 1: + return 0x0000000d20000000ULL; + case 2: + return 0x0000000d40000000ULL; + } + } else { + switch (port) { + default: /* to satisfy compiler */ + case 0: + return 0x0000000c40000000ULL; + case 1: + return 0x0000000c80000000ULL; + case 2: + return 0x0000000cc0000000ULL; + } + } +#endif +} + +/* + * 4xx boards as end point and root point setup * and * testing inbound and out bound windows * - * YUCCA board can be plugged into another yucca board or you can get PCI-E + * 4xx boards can be plugged into another 4xx boards or you can get PCI-E * cable which can be used to setup loop back from one port to another port. * Please rememeber that unless there is a endpoint plugged in to root port it * will not initialize. It is the same in case of endpoint , unless there is @@ -386,110 +630,47 @@ int ppc440spe_init_pcie(void) * /proc/bus/pci/devices. Where you can see the configuration registers * of end point device attached to the port. * - * Enpoint cofiguration can be verified by connecting Yucca board to any - * host or another yucca board. Then try to scan the device. In case of + * Enpoint cofiguration can be verified by connecting 4xx board to any + * host or another 4xx board. Then try to scan the device. In case of * linux use "lspci" or appripriate os command. * - * How do I verify the inbound and out bound windows ?(yucca to yucca) + * How do I verify the inbound and out bound windows ? (4xx to 4xx) * in this configuration inbound and outbound windows are setup to access * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000, * This is waere your POM(PLB out bound memory window) mapped. then - * read the data from other yucca board's u-boot prompt at address + * read the data from other 4xx board's u-boot prompt at address * 0x9000 0000(SRAM). Data should match. * In case of inbound , write data to u-boot command prompt at 0xb000 0000 * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check * data at 0x9000 0000(SRAM).Data should match. */ -int ppc440spe_init_pcie_rootport(int port) +int ppc4xx_init_pcie_port(int port, int rootport) { static int core_init; volatile u32 val = 0; int attempts; + u64 addr; + u32 low, high; if (!core_init) { - ++core_init; - if (ppc440spe_init_pcie()) + if (ppc4xx_init_pcie()) return -1; + ++core_init; } /* - * Initialize various parts of the PCI Express core for our port: - * - * - Set as a root port and enable max width - * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). - * - Set up UTL configuration. - * - Increase SERDES drive strength to levels suggested by AMCC. - * - De-assert RSTPYN, RSTDL and RSTGU. - * - * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with - * default setting 0x11310000. The register has new fields, - * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core - * hang. + * Initialize various parts of the PCI Express core for our port */ - switch (port) { - case 0: - SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12); - - SDR_WRITE(PESDR0_UTLSET1, 0x21222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR0_UTLSET2, 0x11000000); - SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); - SDR_WRITE(PESDR0_RCSSET, - (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; + ppc4xx_init_pcie_port_hw(port, rootport); - case 1: - SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); - SDR_WRITE(PESDR1_UTLSET1, 0x21222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR1_UTLSET2, 0x11000000); - SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR1_RCSSET, - (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - - case 2: - SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); - SDR_WRITE(PESDR2_UTLSET1, 0x21222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR2_UTLSET2, 0x11000000); - SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR2_RCSSET, - (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - } /* * Notice: the following delay has critical impact on device * initialization - if too short (<50ms) the link doesn't get up. */ mdelay(100); - switch (port) { - case 0: - val = SDR_READ(PESDR0_RCSSTS); - break; - case 1: - val = SDR_READ(PESDR1_RCSSTS); - break; - case 2: - val = SDR_READ(PESDR2_RCSSTS); - break; - } - + val = SDR_READ(SDRN_PESDR_RCSSTS(port)); if (val & (1 << 20)) { printf("PCIE%d: PGRST failed %08x\n", port, val); return -1; @@ -498,18 +679,7 @@ int ppc440spe_init_pcie_rootport(int port) /* * Verify link is up */ - val = 0; - switch (port) { - case 0: - val = SDR_READ(PESDR0_LOOP); - break; - case 1: - val = SDR_READ(PESDR1_LOOP); - break; - case 2: - val = SDR_READ(PESDR2_LOOP); - break; - } + val = SDR_READ(SDRN_PESDR_LOOP(port)); if (!(val & 0x00001000)) { printf("PCIE%d: link is not up.\n", port); return -1; @@ -520,331 +690,75 @@ int ppc440spe_init_pcie_rootport(int port) * We use default settings for revB chip. */ if (!ppc440spe_revB()) - ppc440spe_setup_utl(port); + ppc4xx_setup_utl(port); /* * We map PCI Express configuration access into the 512MB regions - * - * NOTICE: revB is very strict about PLB real addressess and ranges to - * be mapped for config space; it seems to only work with d_nnnn_nnnn - * range (hangs the core upon config transaction attempts when set - * otherwise) while revA uses c_nnnn_nnnn. - * - * For revA: - * PCIE0: 0xc_4000_0000 - * PCIE1: 0xc_8000_0000 - * PCIE2: 0xc_c000_0000 - * - * For revB: - * PCIE0: 0xd_0000_0000 - * PCIE1: 0xd_2000_0000 - * PCIE2: 0xd_4000_0000 */ + addr = ppc4xx_get_cfgaddr(port); + low = U64_TO_U32_LOW(addr); + high = U64_TO_U32_HIGH(addr); switch (port) { case 0: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000); - } else { - /* revA */ - mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000); - } + mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low); mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ break; - case 1: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000); - } else { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000); - } + mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low); mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ break; - +#if CFG_PCIE_NR_PORTS > 2 case 2: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000); - } else { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000); - } + mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low); mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ break; +#endif } /* * Check for VC0 active and assert RDY. */ attempts = 10; - switch (port) { - case 0: - while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE0: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20); - break; - case 1: - while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE1: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - - SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20); - break; - case 2: - while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE2: VC0 not active\n"); - return -1; - } - mdelay(1000); + while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE%d: VC0 not active\n", port); + return -1; } - - SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20); - break; + mdelay(1000); } + SDR_WRITE(SDRN_PESDR_RCSSET(port), + SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20); mdelay(100); return 0; } -int ppc440spe_init_pcie_endport(int port) +int ppc4xx_init_pcie_rootport(int port) { - static int core_init; - volatile u32 val = 0; - int attempts; - - if (!core_init) { - ++core_init; - if (ppc440spe_init_pcie()) - return -1; - } - - /* - * Initialize various parts of the PCI Express core for our port: - * - * - Set as a end port and enable max width - * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). - * - Set up UTL configuration. - * - Increase SERDES drive strength to levels suggested by AMCC. - * - De-assert RSTPYN, RSTDL and RSTGU. - * - * NOTICE for revB chip: PESDRn_UTLSET2 is not set - we leave it with - * default setting 0x11310000. The register has new fields, - * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core - * hang. - */ - switch (port) { - case 0: - SDR_WRITE(PESDR0_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X8 << 12); - - SDR_WRITE(PESDR0_UTLSET1, 0x20222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR0_UTLSET2, 0x11000000); - SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); - SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); - SDR_WRITE(PESDR0_RCSSET, - (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - - case 1: - SDR_WRITE(PESDR1_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12); - SDR_WRITE(PESDR1_UTLSET1, 0x20222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR1_UTLSET2, 0x11000000); - SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR1_RCSSET, - (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - - case 2: - SDR_WRITE(PESDR2_DLPSET, 1 << 24 | PTYPE_LEGACY_ENDPOINT << 20 | LNKW_X4 << 12); - SDR_WRITE(PESDR2_UTLSET1, 0x20222222); - if (!ppc440spe_revB()) - SDR_WRITE(PESDR2_UTLSET2, 0x11000000); - SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); - SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); - SDR_WRITE(PESDR2_RCSSET, - (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); - break; - } - /* - * Notice: the following delay has critical impact on device - * initialization - if too short (<50ms) the link doesn't get up. - */ - mdelay(100); - - switch (port) { - case 0: val = SDR_READ(PESDR0_RCSSTS); break; - case 1: val = SDR_READ(PESDR1_RCSSTS); break; - case 2: val = SDR_READ(PESDR2_RCSSTS); break; - } - - if (val & (1 << 20)) { - printf("PCIE%d: PGRST failed %08x\n", port, val); - return -1; - } - - /* - * Verify link is up - */ - val = 0; - switch (port) - { - case 0: - val = SDR_READ(PESDR0_LOOP); - break; - case 1: - val = SDR_READ(PESDR1_LOOP); - break; - case 2: - val = SDR_READ(PESDR2_LOOP); - break; - } - if (!(val & 0x00001000)) { - printf("PCIE%d: link is not up.\n", port); - return -1; - } - - /* - * Setup UTL registers - but only on revA! - * We use default settings for revB chip. - */ - if (!ppc440spe_revB()) - ppc440spe_setup_utl(port); - - /* - * We map PCI Express configuration access into the 512MB regions - * - * NOTICE: revB is very strict about PLB real addressess and ranges to - * be mapped for config space; it seems to only work with d_nnnn_nnnn - * range (hangs the core upon config transaction attempts when set - * otherwise) while revA uses c_nnnn_nnnn. - * - * For revA: - * PCIE0: 0xc_4000_0000 - * PCIE1: 0xc_8000_0000 - * PCIE2: 0xc_c000_0000 - * - * For revB: - * PCIE0: 0xd_0000_0000 - * PCIE1: 0xd_2000_0000 - * PCIE2: 0xd_4000_0000 - */ - switch (port) { - case 0: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x00000000); - } else { - /* revA */ - mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000); - } - mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ - break; - - case 1: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x20000000); - } else { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000); - } - mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ - break; - - case 2: - if (ppc440spe_revB()) { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0x40000000); - } else { - mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c); - mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000); - } - mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ - break; - } - - /* - * Check for VC0 active and assert RDY. - */ - attempts = 10; - switch (port) { - case 0: - while(!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE0: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20); - break; - case 1: - while(!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE1: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - - SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20); - break; - case 2: - while(!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) { - if (!(attempts--)) { - printf("PCIE2: VC0 not active\n"); - return -1; - } - mdelay(1000); - } - - SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20); - break; - } - mdelay(100); + return ppc4xx_init_pcie_port(port, 1); +} - return 0; +int ppc4xx_init_pcie_endport(int port) +{ + return ppc4xx_init_pcie_port(port, 0); } -void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) +void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) { volatile void *mbase = NULL; volatile void *rmbase = NULL; pci_set_ops(hose, - pcie_read_config_byte, - pcie_read_config_word, - pcie_read_config_dword, - pcie_write_config_byte, - pcie_write_config_word, - pcie_write_config_dword); + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); switch (port) { case 0: @@ -857,11 +771,13 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) rmbase = (u32 *)CFG_PCIE1_CFGBASE; hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; break; +#if CFG_PCIE_NR_PORTS > 2 case 2: mbase = (u32 *)CFG_PCIE2_XCFGBASE; rmbase = (u32 *)CFG_PCIE2_CFGBASE; hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; break; +#endif } /* @@ -878,33 +794,53 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) * subregions and to enable the outbound translation. */ out_le32(mbase + PECFG_POM0LAH, 0x00000000); - out_le32(mbase + PECFG_POM0LAL, 0x00000000); + out_le32(mbase + PECFG_POM0LAL, CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); + debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH), + in_le32(mbase + PECFG_POM0LAL)); switch (port) { case 0: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CFG_PCIE_MEMSIZE - 1) | 3); + debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", + mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)), + mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)), + mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)), + mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0))); break; case 1: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), - ~(CFG_PCIE_MEMSIZE - 1) | 3); - break; + ~(CFG_PCIE_MEMSIZE - 1) | 3); + debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", + mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)), + mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)), + mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)), + mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1))); + break; +#if CFG_PCIE_NR_PORTS > 2 case 2: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CFG_PCIE_MEMSIZE - 1) | 3); + debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", + mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)), + mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)), + mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)), + mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2))); break; +#endif } /* Set up 16GB inbound memory window at 0 */ @@ -917,41 +853,26 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port) out_le32(mbase + PECFG_PIM01SAL, 0x00000000); out_le32(mbase + PECFG_PIM0LAL, 0); out_le32(mbase + PECFG_PIM0LAH, 0); - out_le32(mbase + PECFG_PIM1LAL, 0x00000000); - out_le32(mbase + PECFG_PIM1LAH, 0x00000004); + out_le32(mbase + PECFG_PIM1LAL, 0x00000000); + out_le32(mbase + PECFG_PIM1LAH, 0x00000004); out_le32(mbase + PECFG_PIMEN, 0x1); /* Enable I/O, Mem, and Busmaster cycles */ out_le16((u16 *)(mbase + PCI_COMMAND), in_le16((u16 *)(mbase + PCI_COMMAND)) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - printf("PCIE:%d successfully set as rootpoint\n",port); /* Set Device and Vendor Id */ - switch (port) { - case 0: - out_le16(mbase + 0x200, 0xaaa0); - out_le16(mbase + 0x202, 0xbed0); - break; - case 1: - out_le16(mbase + 0x200, 0xaaa1); - out_le16(mbase + 0x202, 0xbed1); - break; - case 2: - out_le16(mbase + 0x200, 0xaaa2); - out_le16(mbase + 0x202, 0xbed2); - break; - default: - out_le16(mbase + 0x200, 0xaaa3); - out_le16(mbase + 0x202, 0xbed3); - } + out_le16(mbase + 0x200, 0xaaa0 + port); + out_le16(mbase + 0x202, 0xbed0 + port); /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ out_le32(mbase + 0x208, 0x06040001); + printf("PCIE%d: successfully set as root-complex\n", port); } -int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port) +int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) { volatile void *mbase = NULL; int attempts = 0; @@ -973,10 +894,12 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port) mbase = (u32 *)CFG_PCIE1_XCFGBASE; hose->cfg_data = (u8 *)CFG_PCIE1_CFGBASE; break; +#if defined(CFG_PCIE2_CFGBASE) case 2: mbase = (u32 *)CFG_PCIE2_XCFGBASE; hose->cfg_data = (u8 *)CFG_PCIE2_CFGBASE; break; +#endif } /* @@ -990,77 +913,73 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port) switch (port) { case 0: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CFG_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CFG_PCIE_MEMSIZE - 1) | 3); break; case 1: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), (CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CFG_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CFG_PCIE_MEMSIZE - 1) | 3); break; +#if CFG_PCIE_NR_PORTS > 2 case 2: - mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); - mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), (CFG_PCIE_MEMBASE + - port * CFG_PCIE_MEMSIZE)); + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CFG_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CFG_PCIE_MEMBASE + + port * CFG_PCIE_MEMSIZE); mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), - ~(CFG_PCIE_MEMSIZE - 1) | 3); + ~(CFG_PCIE_MEMSIZE - 1) | 3); break; +#endif } - /* Set up 16GB inbound memory window at 0 */ + /* Set up 64MB inbound memory window at 0 */ out_le32(mbase + PCI_BASE_ADDRESS_0, 0); out_le32(mbase + PCI_BASE_ADDRESS_1, 0); - out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); - out_le32(mbase + PECFG_BAR0LMPA, 0); - out_le32(mbase + PECFG_PIM0LAL, 0x00000000); - out_le32(mbase + PECFG_PIM0LAH, 0x00000004); /* pointing to SRAM */ + + out_le32(mbase + PECFG_PIM01SAH, 0xffffffff); + out_le32(mbase + PECFG_PIM01SAL, 0xfc000000); + + /* Setup BAR0 */ + out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff); + out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64); + + /* Disable BAR1 & BAR2 */ + out_le32(mbase + PECFG_BAR1MPA, 0); + out_le32(mbase + PECFG_BAR2HMPA, 0); + out_le32(mbase + PECFG_BAR2LMPA, 0); + + out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CFG_PCIE_INBOUND_BASE)); + out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CFG_PCIE_INBOUND_BASE)); out_le32(mbase + PECFG_PIMEN, 0x1); /* Enable I/O, Mem, and Busmaster cycles */ out_le16((u16 *)(mbase + PCI_COMMAND), - in_le16((u16 *)(mbase + PCI_COMMAND)) | - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */ - out_le16(mbase + 0x202,0xfeed); /* Setting device ID */ + in_le16((u16 *)(mbase + PCI_COMMAND)) | + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */ + out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */ + + /* Set Class Code to Processor/PPC */ + out_le32(mbase + 0x208, 0x0b200001); + attempts = 10; - switch (port) { - case 0: - while (!(SDR_READ(PESDR0_RCSSTS) & (1 << 8))) { - if (!(attempts--)) { - printf("PCIE0: BMEN is not active\n"); - return -1; - } - mdelay(1000); - } - break; - case 1: - while (!(SDR_READ(PESDR1_RCSSTS) & (1 << 8))) { - if (!(attempts--)) { - printf("PCIE1: BMEN is not active\n"); - return -1; - } - mdelay(1000); - } - break; - case 2: - while (!(SDR_READ(PESDR2_RCSSTS) & (1 << 8))) { - if (!(attempts--)) { - printf("PCIE2: BMEN is not active\n"); - return -1; - } - mdelay(1000); + while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) { + if (!(attempts--)) { + printf("PCIE%d: BME not active\n", port); + return -1; } - break; + mdelay(1000); } - printf("PCIE:%d successfully set as endpoint\n",port); + + printf("PCIE%d: successfully set as endpoint\n", port); return 0; } diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/4xx_uart.c index 60712b1..ac2b12b 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/4xx_uart.c @@ -20,7 +20,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -/*------------------------------------------------------------------------------+ */ + /* * This source code has been made available to you by IBM on an AS-IS * basis. Anyone receiving this source is licensed under IBM @@ -40,14 +40,11 @@ * COPYRIGHT I B M CORPORATION 1995 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------------- */ -/* - * Travis Sawyer 15 September 2004 - * Added CONFIG_SERIAL_MULTI support - */ + #include <common.h> #include <commproc.h> #include <asm/processor.h> +#include <asm/io.h> #include <watchdog.h> #include "vecnum.h" @@ -61,212 +58,9 @@ DECLARE_GLOBAL_DATA_PTR; -/*****************************************************************************/ -#ifdef CONFIG_IOP480 - -#define SPU_BASE 0x40000000 - -#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */ -#define spu_LineStat_w 0x04 /* Line Status Register (Set) */ -#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */ -#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */ -#define spu_BRateDivh 0x10 /* Baud rate divisor high */ -#define spu_BRateDivl 0x14 /* Baud rate divisor low */ -#define spu_CtlReg 0x18 /* Control Register */ -#define spu_RxCmd 0x1c /* Rx Command Register */ -#define spu_TxCmd 0x20 /* Tx Command Register */ -#define spu_RxBuff 0x24 /* Rx data buffer */ -#define spu_TxBuff 0x24 /* Tx data buffer */ - -/*-----------------------------------------------------------------------------+ - | Line Status Register. - +-----------------------------------------------------------------------------*/ -#define asyncLSRport1 0x40000000 -#define asyncLSRport1set 0x40000004 -#define asyncLSRDataReady 0x80 -#define asyncLSRFramingError 0x40 -#define asyncLSROverrunError 0x20 -#define asyncLSRParityError 0x10 -#define asyncLSRBreakInterrupt 0x08 -#define asyncLSRTxHoldEmpty 0x04 -#define asyncLSRTxShiftEmpty 0x02 - -/*-----------------------------------------------------------------------------+ - | Handshake Status Register. - +-----------------------------------------------------------------------------*/ -#define asyncHSRport1 0x40000008 -#define asyncHSRport1set 0x4000000c -#define asyncHSRDsr 0x80 -#define asyncLSRCts 0x40 - -/*-----------------------------------------------------------------------------+ - | Control Register. - +-----------------------------------------------------------------------------*/ -#define asyncCRport1 0x40000018 -#define asyncCRNormal 0x00 -#define asyncCRLoopback 0x40 -#define asyncCRAutoEcho 0x80 -#define asyncCRDtr 0x20 -#define asyncCRRts 0x10 -#define asyncCRWordLength7 0x00 -#define asyncCRWordLength8 0x08 -#define asyncCRParityDisable 0x00 -#define asyncCRParityEnable 0x04 -#define asyncCREvenParity 0x00 -#define asyncCROddParity 0x02 -#define asyncCRStopBitsOne 0x00 -#define asyncCRStopBitsTwo 0x01 -#define asyncCRDisableDtrRts 0x00 - -/*-----------------------------------------------------------------------------+ - | Receiver Command Register. - +-----------------------------------------------------------------------------*/ -#define asyncRCRport1 0x4000001c -#define asyncRCRDisable 0x00 -#define asyncRCREnable 0x80 -#define asyncRCRIntDisable 0x00 -#define asyncRCRIntEnabled 0x20 -#define asyncRCRDMACh2 0x40 -#define asyncRCRDMACh3 0x60 -#define asyncRCRErrorInt 0x10 -#define asyncRCRPauseEnable 0x08 - -/*-----------------------------------------------------------------------------+ - | Transmitter Command Register. - +-----------------------------------------------------------------------------*/ -#define asyncTCRport1 0x40000020 -#define asyncTCRDisable 0x00 -#define asyncTCREnable 0x80 -#define asyncTCRIntDisable 0x00 -#define asyncTCRIntEnabled 0x20 -#define asyncTCRDMACh2 0x40 -#define asyncTCRDMACh3 0x60 -#define asyncTCRTxEmpty 0x10 -#define asyncTCRErrorInt 0x08 -#define asyncTCRStopPause 0x04 -#define asyncTCRBreakGen 0x02 - -/*-----------------------------------------------------------------------------+ - | Miscellanies defines. - +-----------------------------------------------------------------------------*/ -#define asyncTxBufferport1 0x40000024 -#define asyncRxBufferport1 0x40000024 -#define asyncDLABLsbport1 0x40000014 -#define asyncDLABMsbport1 0x40000010 -#define asyncXOFFchar 0x13 -#define asyncXONchar 0x11 - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -int serial_init (void) -{ - volatile char val; - unsigned short br_reg; - - br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); - - /* - * Init onboard UART - */ - out8 (SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */ - out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */ - out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ - out8 (SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */ - out8 (SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */ - out8 (SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */ - out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ - val = in8 (SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */ - - return (0); -} - -void serial_setbrg (void) -{ - unsigned short br_reg; - - br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); - - out8 (SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */ - out8 (SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ -} - -void serial_putc (const char c) -{ - if (c == '\n') - serial_putc ('\r'); - - /* load status from handshake register */ - if (in8 (SPU_BASE + spu_Handshk_rc) != 00) - out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ - - out8 (SPU_BASE + spu_TxBuff, c); /* Put char */ - - while ((in8 (SPU_BASE + spu_LineStat_rc) & 04) != 04) { - if (in8 (SPU_BASE + spu_Handshk_rc) != 00) - out8 (SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ - } -} - -void serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -int serial_getc () -{ - unsigned char status = 0; - - while (1) { - status = in8 (asyncLSRport1); - if ((status & asyncLSRDataReady) != 0x0) { - break; - } - if ((status & ( asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt )) != 0) { - (void) out8 (asyncLSRport1, - asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt ); - } - } - return (0x000000ff & (int) in8 (asyncRxBufferport1)); -} - -int serial_tstc () -{ - unsigned char status; - - status = in8 (asyncLSRport1); - if ((status & asyncLSRDataReady) != 0x0) { - return (1); - } - if ((status & ( asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt )) != 0) { - (void) out8 (asyncLSRport1, - asyncLSRFramingError | - asyncLSROverrunError | - asyncLSRParityError | - asyncLSRBreakInterrupt); - } - return 0; -} - -#endif /* CONFIG_IOP480 */ - -/*****************************************************************************/ #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_440) + defined(CONFIG_405EX) || defined(CONFIG_440) #if defined(CONFIG_440) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -318,6 +112,15 @@ int serial_tstc () #define UCR0_UDIV_POS 0 #define UCR1_UDIV_POS 8 #define UDIV_MAX 127 +#elif defined(CONFIG_405EX) +#define UART0_BASE 0xef600200 +#define UART1_BASE 0xef600300 +#define CR0_MASK 0x000000ff +#define CR0_EXTCLK_ENA 0x00800000 +#define CR0_UDIV_POS 0 +#define UDIV_SUBTRACT 0 +#define UART0_SDR sdr_uart0 +#define UART1_SDR sdr_uart1 #else /* CONFIG_405GP || CONFIG_405CR */ #define UART0_BASE 0xef600300 #define UART1_BASE 0xef600400 @@ -336,12 +139,6 @@ int serial_tstc () #define ACTING_UART1_BASE UART1_BASE #endif -#if defined(CONFIG_SERIAL_MULTI) -#define UART_BASE dev_base -#else -#define UART_BASE ACTING_UART0_BASE -#endif - #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK) #error "External serial clock not supported on AMCC PPC405EP!" #endif @@ -362,7 +159,6 @@ int serial_tstc () /*-----------------------------------------------------------------------------+ | Line Status Register. +-----------------------------------------------------------------------------*/ -/*#define asyncLSRport1 ACTING_UART0_BASE+0x05 */ #define asyncLSRDataReady1 0x01 #define asyncLSROverrunError1 0x02 #define asyncLSRParityError1 0x04 @@ -372,12 +168,6 @@ int serial_tstc () #define asyncLSRTxShiftEmpty1 0x40 #define asyncLSRRxFifoError1 0x80 -/*-----------------------------------------------------------------------------+ - | Miscellanies defines. - +-----------------------------------------------------------------------------*/ -/*#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 */ -/*#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 */ - #ifdef CONFIG_SERIAL_SOFTWARE_FIFO /*-----------------------------------------------------------------------------+ | Fifo @@ -391,7 +181,36 @@ typedef struct { volatile static serial_buffer_t buf_info; #endif -#if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK) +static void serial_init_common(u32 base, u32 udiv, u16 bdiv) +{ + PPC4xx_SYS_INFO sys_info; + u8 val; + + get_sys_info(&sys_info); + + /* Correct UART frequency in bd-info struct now that + * the UART divisor is available + */ +#ifdef CFG_EXT_SERIAL_CLOCK + gd->uart_clk = CFG_EXT_SERIAL_CLOCK; +#else + gd->uart_clk = sys_info.freqUART / udiv; +#endif + + out_8((u8 *)base + UART_LCR, 0x80); /* set DLAB bit */ + out_8((u8 *)base + UART_DLL, bdiv); /* set baudrate divisor */ + out_8((u8 *)base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ + out_8((u8 *)base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out_8((u8 *)base + UART_FCR, 0x00); /* disable FIFO */ + out_8((u8 *)base + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in_8((u8 *)base + UART_LSR); /* clear line status */ + val = in_8((u8 *)base + UART_RBR); /* read receive buffer */ + out_8((u8 *)base + UART_SCR, 0x00); /* set scratchpad */ + out_8((u8 *)base + UART_IER, 0x00); /* set interrupt enable reg */ +} + +#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \ + !defined(CFG_EXT_SERIAL_CLOCK) static void serial_divs (int baudrate, unsigned long *pudiv, unsigned short *pbdiv) { @@ -457,8 +276,8 @@ static void serial_divs (int baudrate, unsigned long *pudiv, get_sys_info(&sysinfo); plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? - sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) / - sysinfo.pllFwdDivB); + sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * + sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB); udiv = 256; /* Assume lowest possible serial clk */ div = plloutb / (16 * baudrate); /* total divisor */ umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */ @@ -496,16 +315,11 @@ static void serial_divs (int baudrate, unsigned long *pudiv, */ #if defined(CONFIG_440) -#if defined(CONFIG_SERIAL_MULTI) -int serial_init_dev (unsigned long dev_base) -#else -int serial_init(void) -#endif +int serial_init_dev(unsigned long base) { unsigned long reg; unsigned long udiv; unsigned short bdiv; - volatile char val; #ifdef CFG_EXT_SERIAL_CLOCK unsigned long tmp; #endif @@ -543,36 +357,46 @@ int serial_init(void) MTREG(UART3_SDR, reg); #endif - out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */ - out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8(UART_BASE + UART_LSR); /* clear line status */ - val = in8(UART_BASE + UART_RBR); /* read receive buffer */ - out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */ + serial_init_common(base, udiv, bdiv); return (0); } #else /* !defined(CONFIG_440) */ -#if defined(CONFIG_SERIAL_MULTI) -int serial_init_dev (unsigned long dev_base) -#else -int serial_init (void) -#endif +int serial_init_dev (unsigned long base) { unsigned long reg; unsigned long tmp; unsigned long clk; unsigned long udiv; unsigned short bdiv; - volatile char val; -#if defined(CONFIG_405EZ) +#ifdef CONFIG_405EX + clk = tmp = 0; + mfsdr(UART0_SDR, reg); + reg &= ~CR0_MASK; +#ifdef CFG_EXT_SERIAL_CLOCK + reg |= CR0_EXTCLK_ENA; + udiv = 1; + tmp = gd->baudrate * 16; + bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; +#else + serial_divs(gd->baudrate, &udiv, &bdiv); +#endif + reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ + + /* + * Configure input clock to baudrate generator for all + * available serial ports here + */ + mtsdr(UART0_SDR, reg); + +#if defined(UART1_SDR) + mtsdr(UART1_SDR, reg); +#endif + +#elif defined(CONFIG_405EZ) serial_divs(gd->baudrate, &udiv, &bdiv); clk = tmp = reg = 0; #else @@ -608,81 +432,44 @@ int serial_init (void) #endif /* CONFIG_405EP */ tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; -#endif /* CONFIG_405EZ */ - - out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ - out8(UART_BASE + UART_DLM, bdiv >> 8); /* set baudrate divisor */ - out8(UART_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out8(UART_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8(UART_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8(UART_BASE + UART_LSR); /* clear line status */ - val = in8(UART_BASE + UART_RBR); /* read receive buffer */ - out8(UART_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8(UART_BASE + UART_IER, 0x00); /* set interrupt enable reg */ +#endif /* CONFIG_405EX */ + + serial_init_common(base, udiv, bdiv); return (0); } #endif /* if defined(CONFIG_440) */ -#if defined(CONFIG_SERIAL_MULTI) -void serial_setbrg_dev (unsigned long dev_base) -#else -void serial_setbrg (void) -#endif +void serial_setbrg_dev(unsigned long base) { -#if defined(CONFIG_SERIAL_MULTI) - serial_init_dev(dev_base); -#else - serial_init(); -#endif + serial_init_dev(base); } -#if defined(CONFIG_SERIAL_MULTI) -void serial_putc_dev (unsigned long dev_base, const char c) -#else -void serial_putc (const char c) -#endif +void serial_putc_dev(unsigned long base, const char c) { int i; if (c == '\n') -#if defined(CONFIG_SERIAL_MULTI) - serial_putc_dev (dev_base, '\r'); -#else - serial_putc ('\r'); -#endif + serial_putc_dev(base, '\r'); /* check THRE bit, wait for transmiter available */ for (i = 1; i < 3500; i++) { - if ((in8 (UART_BASE + UART_LSR) & 0x20) == 0x20) + if ((in_8((u8 *)base + UART_LSR) & 0x20) == 0x20) break; udelay (100); } - out8 (UART_BASE + UART_THR, c); /* put character out */ + + out_8((u8 *)base + UART_THR, c); /* put character out */ } -#if defined(CONFIG_SERIAL_MULTI) -void serial_puts_dev (unsigned long dev_base, const char *s) -#else -void serial_puts (const char *s) -#endif +void serial_puts_dev (unsigned long base, const char *s) { - while (*s) { -#if defined(CONFIG_SERIAL_MULTI) - serial_putc_dev (dev_base, *s++); -#else - serial_putc (*s++); -#endif - } + while (*s) + serial_putc_dev (base, *s++); } -#if defined(CONFIG_SERIAL_MULTI) -int serial_getc_dev (unsigned long dev_base) -#else -int serial_getc (void) -#endif +int serial_getc_dev (unsigned long base) { unsigned char status = 0; @@ -690,46 +477,45 @@ int serial_getc (void) #if defined(CONFIG_HW_WATCHDOG) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ #endif /* CONFIG_HW_WATCHDOG */ - status = in8 (UART_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { + + status = in_8((u8 *)base + UART_LSR); + if ((status & asyncLSRDataReady1) != 0x0) break; - } + if ((status & ( asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1 )) != 0) { - out8 (UART_BASE + UART_LSR, + out_8((u8 *)base + UART_LSR, asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1); } } - return (0x000000ff & (int) in8 (UART_BASE)); + + return (0x000000ff & (int) in_8((u8 *)base)); } -#if defined(CONFIG_SERIAL_MULTI) -int serial_tstc_dev (unsigned long dev_base) -#else -int serial_tstc (void) -#endif +int serial_tstc_dev (unsigned long base) { unsigned char status; - status = in8 (UART_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { + status = in_8((u8 *)base + UART_LSR); + if ((status & asyncLSRDataReady1) != 0x0) return (1); - } + if ((status & ( asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1 )) != 0) { - out8 (UART_BASE + UART_LSR, + out_8((u8 *)base + UART_LSR, asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1); } + return 0; } @@ -742,11 +528,11 @@ void serial_isr (void *arg) const int rx_get = buf_info.rx_get; int rx_put = buf_info.rx_put; - if (rx_get <= rx_put) { + if (rx_get <= rx_put) space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); - } else { + else space = rx_get - rx_put; - } + while (serial_tstc_dev (ACTING_UART0_BASE)) { c = serial_getc_dev (ACTING_UART0_BASE); if (space) { @@ -757,8 +543,9 @@ void serial_isr (void *arg) rx_put = 0; if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { /* Stop flow by setting RTS inactive */ - out8 (ACTING_UART0_BASE + UART_MCR, - in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02)); + out_8((u8 *)ACTING_UART0_BASE + UART_MCR, + in_8((u8 *)ACTING_UART0_BASE + UART_MCR) & + (0xFF ^ 0x02)); } } buf_info.rx_put = rx_put; @@ -771,35 +558,35 @@ void serial_buffered_init (void) buf_info.rx_put = 0; buf_info.rx_get = 0; - if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) { + if (in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10) serial_puts ("Check CTS signal present on serial port: OK.\n"); - } else { + else serial_puts ("WARNING: CTS signal not present on serial port.\n"); - } irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ , serial_isr /*interrupt_handler_t *handler */ , (void *) &buf_info /*void *arg */ ); /* Enable "RX Data Available" Interrupt on UART */ - /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */ - out8 (ACTING_UART0_BASE + UART_IER, 0x01); + out_8(ACTING_UART0_BASE + UART_IER, 0x01); /* Set DTR active */ - out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01); + out_8(ACTING_UART0_BASE + UART_MCR, + in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x01); /* Start flow by setting RTS active */ - out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); + out_8(ACTING_UART0_BASE + UART_MCR, + in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02); /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */ - out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1); + out_8(ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1); } void serial_buffered_putc (const char c) { /* Wait for CTS */ #if defined(CONFIG_HW_WATCHDOG) - while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)) + while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)) WATCHDOG_RESET (); #else - while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10)); + while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)); #endif serial_putc (c); } @@ -828,14 +615,15 @@ int serial_buffered_getc (void) buf_info.rx_get = rx_get; rx_put = buf_info.rx_put; - if (rx_get <= rx_put) { + if (rx_get <= rx_put) space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); - } else { + else space = rx_get - rx_put; - } + if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { /* Start flow by setting RTS active */ - out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02); + out_8(ACTING_UART0_BASE + UART_MCR, + in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02); } return c; @@ -860,8 +648,8 @@ int serial_buffered_tstc (void) #if (CONFIG_KGDB_SER_INDEX & 2) void kgdb_serial_init (void) { - volatile char val; - unsigned short br_reg; + u8 val; + u16 br_reg; get_clocks (); br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) + @@ -869,16 +657,16 @@ void kgdb_serial_init (void) /* * Init onboard 16550 UART */ - out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ - out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ - out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ - out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ - out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */ - val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */ - out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ - out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ + out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ + out_8((u8 *)ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ + out_8((u8 *)ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ + out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ + out_8((u8 *)ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ + out_8((u8 *)ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); /* clear line status */ + val = in_8((u8 *)ACTING_UART1_BASE + UART_RBR); /* read receive buffer */ + out_8((u8 *)ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ + out_8((u8 *)ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ } void putDebugChar (const char c) @@ -886,17 +674,16 @@ void putDebugChar (const char c) if (c == '\n') serial_putc ('\r'); - out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */ + out_8((u8 *)ACTING_UART1_BASE + UART_THR, c); /* put character out */ /* check THRE bit, wait for transfer done */ - while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20); + while ((in_8((u8 *)ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20); } void putDebugStr (const char *s) { - while (*s) { + while (*s) serial_putc (*s++); - } } int getDebugChar (void) @@ -904,22 +691,23 @@ int getDebugChar (void) unsigned char status = 0; while (1) { - status = in8 (ACTING_UART1_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) { + status = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); + if ((status & asyncLSRDataReady1) != 0x0) break; - } - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - out8 (ACTING_UART1_BASE + UART_LSR, + + if ((status & (asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) { + out_8((u8 *)ACTING_UART1_BASE + UART_LSR, asyncLSRFramingError1 | asyncLSROverrunError1 | asyncLSRParityError1 | asyncLSRBreakInterrupt1); } } - return (0x000000ff & (int) in8 (ACTING_UART1_BASE)); + + return (0x000000ff & (int) in_8((u8 *)ACTING_UART1_BASE)); } void kgdb_interruptible (int yes) @@ -967,10 +755,12 @@ int serial1_init(void) { return (serial_init_dev(UART1_BASE)); } + void serial0_setbrg (void) { serial_setbrg_dev(UART0_BASE); } + void serial1_setbrg (void) { serial_setbrg_dev(UART1_BASE); @@ -985,6 +775,7 @@ void serial1_putc(const char c) { serial_putc_dev(UART1_BASE, c); } + void serial0_puts(const char *s) { serial_puts_dev(UART0_BASE, s); @@ -1004,6 +795,7 @@ int serial1_getc(void) { return(serial_getc_dev(UART1_BASE)); } + int serial0_tstc(void) { return (serial_tstc_dev(UART0_BASE)); @@ -1037,6 +829,39 @@ struct serial_device serial1_device = serial1_putc, serial1_puts, }; +#else +/* + * Wrapper functions + */ +int serial_init(void) +{ + return serial_init_dev(ACTING_UART0_BASE); +} + +void serial_setbrg(void) +{ + serial_setbrg_dev(ACTING_UART0_BASE); +} + +void serial_putc(const char c) +{ + serial_putc_dev(ACTING_UART0_BASE, c); +} + +void serial_puts(const char *s) +{ + serial_puts_dev(ACTING_UART0_BASE, s); +} + +int serial_getc(void) +{ + return serial_getc_dev(ACTING_UART0_BASE); +} + +int serial_tstc(void) +{ + return serial_tstc_dev(ACTING_UART0_BASE); +} #endif /* CONFIG_SERIAL_MULTI */ #endif /* CONFIG_405GP || CONFIG_405CR */ diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index af9da5b..9155e9a 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -25,15 +25,38 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o resetvec.o kgdb.o -SOBJS = dcr.o -COBJS = 405gp_pci.o 440spe_pcie.o 4xx_enet.o \ - bedbug_405.o commproc.o \ - cpu.o cpu_init.o gpio.o i2c.o interrupts.o \ - miiphy.o ndfc.o sdram.o serial.o \ - 40x_spd_sdram.o 44x_spd_ddr.o 44x_spd_ddr2.o speed.o \ - tlb.o traps.o usb_ohci.o usb.o usbdev.o \ - 440spe_pcie.o +START := resetvec.o +START += start.o + +SOBJS := cache.o +SOBJS += dcr.o +SOBJS += kgdb.o + +COBJS := 40x_spd_sdram.o +COBJS += 44x_spd_ddr.o +COBJS += 44x_spd_ddr2.o +COBJS += 4xx_enet.o +COBJS += 4xx_pci.o +COBJS += 4xx_pcie.o +COBJS += 4xx_uart.o +COBJS += bedbug_405.o +COBJS += commproc.o +COBJS += cpu.o +COBJS += cpu_init.o +COBJS += fdt.o +COBJS += gpio.o +COBJS += i2c.o +COBJS += interrupts.o +COBJS += iop480_uart.o +COBJS += miiphy.o +COBJS += ndfc.o +COBJS += sdram.o +COBJS += speed.o +COBJS += tlb.o +COBJS += traps.o +COBJS += usb.o +COBJS += usb_ohci.o +COBJS += usbdev.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/ppc4xx/cache.S b/cpu/ppc4xx/cache.S new file mode 100644 index 0000000..5124dec --- /dev/null +++ b/cpu/ppc4xx/cache.S @@ -0,0 +1,233 @@ +/* + * This file contains miscellaneous low-level functions. + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) + * and Paul Mackerras. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#include <config.h> +#include <config.h> +#include <ppc4xx.h> +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/cache.h> +#include <asm/mmu.h> + +/* + * Flush instruction cache. + */ +_GLOBAL(invalidate_icache) + iccci r0,r0 + isync + blr + +/* + * Write any modified data cache blocks out to memory + * and invalidate the corresponding instruction cache blocks. + * + * flush_icache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(flush_icache_range) + li r5,L1_CACHE_BYTES-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,L1_CACHE_SHIFT + beqlr + mtctr r4 + mr r6,r3 +1: dcbst 0,r3 + addi r3,r3,L1_CACHE_BYTES + bdnz 1b + sync /* wait for dcbst's to get to ram */ + mtctr r4 +2: icbi 0,r6 + addi r6,r6,L1_CACHE_BYTES + bdnz 2b + sync /* additional sync needed on g4 */ + isync + blr + +/* + * Write any modified data cache blocks out to memory. + * Does not invalidate the corresponding cache lines (especially for + * any corresponding instruction cache). + * + * clean_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(clean_dcache_range) + li r5,L1_CACHE_BYTES-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,L1_CACHE_SHIFT + beqlr + mtctr r4 + +1: dcbst 0,r3 + addi r3,r3,L1_CACHE_BYTES + bdnz 1b + sync /* wait for dcbst's to get to ram */ + blr + +/* + * Write any modified data cache blocks out to memory and invalidate them. + * Does not invalidate the corresponding instruction cache blocks. + * + * flush_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(flush_dcache_range) + li r5,L1_CACHE_BYTES-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,L1_CACHE_SHIFT + beqlr + mtctr r4 + +1: dcbf 0,r3 + addi r3,r3,L1_CACHE_BYTES + bdnz 1b + sync /* wait for dcbst's to get to ram */ + blr + +/* + * Like above, but invalidate the D-cache. This is used by the 8xx + * to invalidate the cache so the PPC core doesn't get stale data + * from the CPM (no cache snooping here :-). + * + * invalidate_dcache_range(unsigned long start, unsigned long stop) + */ +_GLOBAL(invalidate_dcache_range) + li r5,L1_CACHE_BYTES-1 + andc r3,r3,r5 + subf r4,r3,r4 + add r4,r4,r5 + srwi. r4,r4,L1_CACHE_SHIFT + beqlr + mtctr r4 + +1: dcbi 0,r3 + addi r3,r3,L1_CACHE_BYTES + bdnz 1b + sync /* wait for dcbi's to get to ram */ + blr + +/* + * 40x cores have 8K or 16K dcache and 32 byte line size. + * 44x has a 32K dcache and 32 byte line size. + * 8xx has 1, 2, 4, 8K variants. + * For now, cover the worst case of the 44x. + * Must be called with external interrupts disabled. + */ +#define CACHE_NWAYS 64 +#define CACHE_NLINES 32 + +_GLOBAL(flush_dcache) + li r4,(2 * CACHE_NWAYS * CACHE_NLINES) + mtctr r4 + lis r5,0 +1: lwz r3,0(r5) /* Load one word from every line */ + addi r5,r5,L1_CACHE_BYTES + bdnz 1b + sync + blr + +_GLOBAL(invalidate_dcache) + addi r6,0,0x0000 /* clear GPR 6 */ + /* Do loop for # of dcache congruence classes. */ + lis r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha /* TBS for large sized cache */ + ori r7,r7,(CFG_DCACHE_SIZE / L1_CACHE_BYTES / 2)@l + /* NOTE: dccci invalidates both */ + mtctr r7 /* ways in the D cache */ +..dcloop: + dccci 0,r6 /* invalidate line */ + addi r6,r6,L1_CACHE_BYTES /* bump to next line */ + bdnz ..dcloop + sync + blr + +/* + * Cache functions. + * + * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM, + * although for some cache-ralated calls stubs have to be provided to satisfy + * symbols resolution. + * Icache-related functions are used in POST framework. + * + */ +#ifdef CONFIG_440 + + .globl dcache_disable + .globl icache_disable + .globl icache_enable +dcache_disable: +icache_disable: +icache_enable: + blr + + .globl dcache_status + .globl icache_status +dcache_status: +icache_status: + mr r3, 0 + blr + +#else /* CONFIG_440 */ + + .globl icache_enable +icache_enable: + mflr r8 + bl invalidate_icache + mtlr r8 + isync + addis r3,r0, 0xc000 /* set bit 0 */ + mticcr r3 + blr + + .globl icache_disable +icache_disable: + addis r3,r0, 0x0000 /* clear bit 0 */ + mticcr r3 + isync + blr + + .globl icache_status +icache_status: + mficcr r3 + srwi r3, r3, 31 /* >>31 => select bit 0 */ + blr + + .globl dcache_enable +dcache_enable: + mflr r8 + bl invalidate_dcache + mtlr r8 + isync + addis r3,r0, 0x8000 /* set bit 0 */ + mtdccr r3 + blr + + .globl dcache_disable +dcache_disable: + mflr r8 + bl flush_dcache + mtlr r8 + addis r3,r0, 0x0000 /* clear bit 0 */ + mtdccr r3 + blr + + .globl dcache_status +dcache_status: + mfdccr r3 + srwi r3, r3, 31 /* >>31 => select bit 0 */ + blr + +#endif /* CONFIG_440 */ diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index c07bc0c..9e9c685 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2006 + * (C) Copyright 2000-2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -37,22 +37,9 @@ #include <asm/cache.h> #include <ppc4xx.h> -#if !defined(CONFIG_405) DECLARE_GLOBAL_DATA_PTR; -#endif -#if defined(CONFIG_BOARD_RESET) void board_reset(void); -#endif - -#if defined(CONFIG_440) -#define FREQ_EBC (sys_info.freqEPB) -#elif defined(CONFIG_405EZ) -#define FREQ_EBC ((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \ - sys_info.pllExtBusDiv) -#else -#define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv) -#endif #if defined(CONFIG_405GP) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -60,7 +47,7 @@ void board_reset(void); #define PCI_ASYNC -int pci_async_enabled(void) +static int pci_async_enabled(void) { #if defined(CONFIG_405GP) return (mfdcr(strap) & PSR_PCI_ASYNC_EN); @@ -76,8 +63,9 @@ int pci_async_enabled(void) } #endif -#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && !defined(CONFIG_405) -int pci_arbiter_enabled(void) +#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \ + !defined(CONFIG_405) && !defined(CONFIG_405EX) +static int pci_arbiter_enabled(void) { #if defined(CONFIG_405GP) return (mfdcr(strap) & PSR_PCI_ARBIT_EN); @@ -107,14 +95,10 @@ int pci_arbiter_enabled(void) } #endif -#if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) - +#if defined(CONFIG_405EP) #define I2C_BOOTROM -int i2c_bootrom_enabled(void) +static int i2c_bootrom_enabled(void) { #if defined(CONFIG_405EP) return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP); @@ -207,6 +191,21 @@ static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \ 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' }; #endif +#if defined(CONFIG_405EX) +#define SDR0_PINSTP_SHIFT 29 +static char *bootstrap_str[] = { + "EBC (8 bits)", + "EBC (16 bits)", + "EBC (16 bits)", + "NAND (8 bits)", + "NAND (8 bits)", + "I2C (Addr 0x54)", + "EBC (8 bits)", + "I2C (Addr 0x52)", +}; +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; +#endif + #if defined(SDR0_PINSTP_SHIFT) static int bootstrap_option(void) { @@ -219,7 +218,19 @@ static int bootstrap_option(void) #if defined(CONFIG_440) -static int do_chip_reset(unsigned long sys0, unsigned long sys1); +static int do_chip_reset (unsigned long sys0, unsigned long sys1) +{ + /* Changes to cpc0_sys0 and cpc0_sys1 require chip + * reset. + */ + mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */ + mtdcr (cpc0_sys0, sys0); + mtdcr (cpc0_sys1, sys1); + mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ + mtspr (dbcr0, 0x20000000); /* Reset the chip */ + + return 1; +} #endif @@ -241,7 +252,8 @@ int checkcpu (void) puts("AMCC PowerPC 4"); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405EZ) + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_405EX) puts("05"); #endif #if defined(CONFIG_440) @@ -293,6 +305,26 @@ int checkcpu (void) puts("EZ Rev. A"); break; + case PVR_405EX1_RA: + puts("EX Rev. A"); + strcpy(addstr, "Security support"); + break; + + case PVR_405EX2_RA: + puts("EX Rev. A"); + strcpy(addstr, "No Security support"); + break; + + case PVR_405EXR1_RA: + puts("EXr Rev. A"); + strcpy(addstr, "Security support"); + break; + + case PVR_405EXR2_RA: + puts("EXr Rev. A"); + strcpy(addstr, "No Security support"); + break; + #if defined(CONFIG_440) case PVR_440GP_RB: puts("GP Rev. B"); @@ -424,7 +456,7 @@ int checkcpu (void) printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), sys_info.freqPLB / 1000000, get_OPB_freq() / 1000000, - FREQ_EBC / 1000000); + sys_info.freqEBC / 1000000); if (addstr[0] != 0) printf(" %s\n", addstr); @@ -437,7 +469,7 @@ int checkcpu (void) printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); #endif /* SDR0_PINSTP_SHIFT */ -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && !defined(CONFIG_405EX) printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); #endif @@ -450,11 +482,11 @@ int checkcpu (void) } #endif -#if defined(CONFIG_PCI) +#if defined(CONFIG_PCI) && !defined(CONFIG_405EX) putc('\n'); #endif -#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) +#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) printf (" 16 kB I-Cache 16 kB D-Cache"); #elif defined(CONFIG_440) printf (" 32 kB I-Cache 32 kB D-Cache"); @@ -478,7 +510,6 @@ int checkcpu (void) return 0; } -#if defined (CONFIG_440SPE) int ppc440spe_revB() { unsigned int pvr; @@ -488,7 +519,6 @@ int ppc440spe_revB() { else return 0; } -#endif /* ------------------------------------------------------------------------- */ @@ -510,22 +540,6 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } -#if defined(CONFIG_440) -static int do_chip_reset (unsigned long sys0, unsigned long sys1) -{ - /* Changes to cpc0_sys0 and cpc0_sys1 require chip - * reset. - */ - mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */ - mtdcr (cpc0_sys0, sys0); - mtdcr (cpc0_sys1, sys1); - mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ - mtspr (dbcr0, 0x20000000); /* Reset the chip */ - - return 1; -} -#endif - /* * Get timebase clock frequency @@ -545,16 +559,14 @@ unsigned long get_tbclk (void) #if defined(CONFIG_WATCHDOG) -void -watchdog_reset(void) +void watchdog_reset(void) { int re_enable = disable_interrupts(); reset_4xx_watchdog(); if (re_enable) enable_interrupts(); } -void -reset_4xx_watchdog(void) +void reset_4xx_watchdog(void) { /* * Clear TSR(WIS) bit diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 351da36..01ab523 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2006 + * (C) Copyright 2000-2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -112,7 +112,7 @@ cpu_init_f (void) unsigned long val; #endif -#if defined(CONFIG_405EP) +#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && !defined(CFG_4xx_GPIO_TABLE) /* * GPIO0 setup (select GPIO or alternate function) */ @@ -128,17 +128,25 @@ cpu_init_f (void) out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ out32(GPIO0_TSRL, CFG_GPIO0_TSRL); +#if defined(CFG_GPIO0_ISR2H) + out32(GPIO0_ISR2H, CFG_GPIO0_ISR2H); + out32(GPIO0_ISR2L, CFG_GPIO0_ISR2L); +#endif +#if defined (CFG_GPIO0_TCR) out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ +#endif +#if defined (CONFIG_450EP) /* * Set EMAC noise filter bits */ mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); #endif /* CONFIG_405EP */ +#endif /* CONFIG_405EP */ -#if defined(CFG_440_GPIO_TABLE) +#if defined(CFG_4xx_GPIO_TABLE) gpio_set_chip_configuration(); -#endif /* CFG_440_GPIO_TABLE */ +#endif /* CFG_4xx_GPIO_TABLE */ /* * External Bus Controller (EBC) Setup @@ -146,7 +154,7 @@ cpu_init_f (void) #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_405)) + defined(CONFIG_405EX) || defined(CONFIG_405)) /* * Move the next instructions into icache, since these modify the flash * we are running from! diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c new file mode 100644 index 0000000..dcedbbb --- /dev/null +++ b/cpu/ppc4xx/fdt.c @@ -0,0 +1,178 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include <common.h> +#include <watchdog.h> +#include <command.h> +#include <asm/cache.h> +#include <ppc4xx.h> + +#if defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#include <libfdt_env.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void do_fixup(void *fdt, const char *node, const char *prop, + const void *val, int len, int create) +{ +#if defined(DEBUG) + int i; + debug("Updating property '%s/%s' = ", node, prop); + for (i = 0; i < len; i++) + debug(" %.2x", *(u8*)(val+i)); + debug("(%d)\n", *(u32 *)val); +#endif + int rc = fdt_find_and_setprop(fdt, node, prop, val, len, create); + if (rc) + printf("Unable to update property %s:%s, err=%s\n", + node, prop, fdt_strerror(rc)); +} + +static void do_fixup_macaddr(void *fdt, int offset, const void *val, int i) +{ + int rc; + + debug("Updating node EMAC%d\n", i); + + rc = fdt_setprop(fdt, offset, "mac-address", val, 6); + if (rc) + printf("Unable to update property %s, err=%s\n", + "mac-address", fdt_strerror(rc)); + rc = fdt_setprop(fdt, offset, "local-mac-address", val, 6); + if (rc) + printf("Unable to update property %s, err=%s\n", + "local-mac-address", fdt_strerror(rc)); +} + +static void do_fixup_u32(void *fdt, const char *node, const char *prop, + u32 val, int create) +{ + val = cpu_to_fdt32(val); + do_fixup(fdt, node, prop, &val, sizeof(val), create); +} + +static void do_fixup_uart(void *fdt, int offset, int i, bd_t *bd) +{ + int rc; + u32 val; + PPC4xx_SYS_INFO sys_info; + + get_sys_info(&sys_info); + + debug("Updating node UART%d: clock-frequency=%d\n", i, gd->uart_clk); + + val = cpu_to_fdt32(gd->uart_clk); + rc = fdt_setprop(fdt, offset, "clock-frequency", &val, 4); + if (rc) + printf("Unable to update node UART, err=%s\n", fdt_strerror(rc)); + + val = cpu_to_fdt32(bd->bi_baudrate); + rc = fdt_setprop(fdt, offset, "current-speed", &val, 4); + if (rc) + printf("Unable to update node UART, err=%s\n", fdt_strerror(rc)); +} + +void ft_cpu_setup(void *blob, bd_t *bd) +{ + char * cpu_path = "/cpus/" OF_CPU; + sys_info_t sys_info; + int offset; + int i; + int tmp[2]; + + get_sys_info (&sys_info); + + do_fixup_u32(blob, cpu_path, "timebase-frequency", bd->bi_intfreq, 1); + do_fixup_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1); + do_fixup_u32(blob, "/plb", "clock-frequency", sys_info.freqPLB, 1); + do_fixup_u32(blob, "/plb/opb", "clock-frequency", sys_info.freqOPB, 1); + do_fixup_u32(blob, "/plb/opb/ebc", "clock-frequency", sys_info.freqEBC, 1); + + /* update, or add and update /memory node */ + offset = fdt_find_node_by_path(blob, "/memory"); + if (offset < 0) { + offset = fdt_add_subnode(blob, 0, "memory"); + if (offset < 0) + debug("failed to add /memory node: %s\n", + fdt_strerror(offset)); + } + if (offset >= 0) { + fdt_setprop(blob, offset, "device_type", + "memory", sizeof("memory")); + tmp[0] = cpu_to_fdt32(bd->bi_memstart); + tmp[1] = cpu_to_fdt32(bd->bi_memsize); + fdt_setprop(blob, offset, "reg", tmp, sizeof(tmp)); + debug("Updating /memory node to %d:%d\n", + bd->bi_memstart, bd->bi_memsize); + } + + /* + * Setup all baudrates for the UARTs + */ + offset = 0; + for (i = 0; i < 4; i++) { + offset = fdt_find_node_by_type(blob, offset, "serial"); + if (offset < 0) + break; + + do_fixup_uart(blob, offset, i, bd); + } + + /* + * Setup all MAC addresses in fdt + */ + offset = 0; + for (i = 0; i < 4; i++) { + offset = fdt_find_node_by_type(blob, offset, "network"); + if (offset < 0) + break; + + switch (i) { + case 0: + do_fixup_macaddr(blob, offset, bd->bi_enetaddr, 0); + break; +#ifdef CONFIG_HAS_ETH1 + case 1: + do_fixup_macaddr(blob, offset, bd->bi_enet1addr, 1); + break; +#endif +#ifdef CONFIG_HAS_ETH2 + case 2: + do_fixup_macaddr(blob, offset, bd->bi_enet2addr, 2); + break; +#endif +#ifdef CONFIG_HAS_ETH3 + case 3: + do_fixup_macaddr(blob, offset, bd->bi_enet3addr, 3); + break; +#endif + } + } +} +#endif /* CONFIG_OF_LIBFDT */ diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c index 50f2fdf..dcf1fba 100644 --- a/cpu/ppc4xx/gpio.c +++ b/cpu/ppc4xx/gpio.c @@ -26,8 +26,8 @@ #include <asm/io.h> #include <asm/gpio.h> -#if defined(CFG_440_GPIO_TABLE) -gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE; +#if defined(CFG_4xx_GPIO_TABLE) +gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_4xx_GPIO_TABLE; #endif #if defined(GPIO0_OSRL) @@ -55,10 +55,10 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val) mask2 = 0xc0000000 >> (pin2 << 1); /* first set TCR to 0 */ - out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) & ~mask); + out_be32((void *)GPIO0_TCR + offs, in_be32((void *)GPIO0_TCR + offs) & ~mask); if (in_out == GPIO_OUT) { - val = in32(GPIO0_OSRL + offs + offs2) & ~mask2; + val = in_be32((void *)GPIO0_OSRL + offs + offs2) & ~mask2; switch (gpio_alt) { case GPIO_ALT1: val |= GPIO_ALT1_SEL >> pin2; @@ -70,20 +70,23 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val) val |= GPIO_ALT3_SEL >> pin2; break; } - out32(GPIO0_OSRL + offs + offs2, val); + out_be32((void *)GPIO0_OSRL + offs + offs2, val); /* setup requested output value */ if (out_val == GPIO_OUT_0) - out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~mask); + out_be32((void *)GPIO0_OR + offs, + in_be32((void *)GPIO0_OR + offs) & ~mask); else if (out_val == GPIO_OUT_1) - out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | mask); + out_be32((void *)GPIO0_OR + offs, + in_be32((void *)GPIO0_OR + offs) | mask); /* now configure TCR to drive output if selected */ - out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) | mask); + out_be32((void *)GPIO0_TCR + offs, + in_be32((void *)GPIO0_TCR + offs) | mask); } else { - val = in32(GPIO0_ISR1L + offs + offs2) & ~mask2; + val = in_be32((void *)GPIO0_ISR1L + offs + offs2) & ~mask2; val |= GPIO_IN_SEL >> pin2; - out32(GPIO0_ISR1L + offs + offs2, val); + out_be32((void *)GPIO0_ISR1L + offs + offs2, val); } } #endif /* GPIO_OSRL */ @@ -98,9 +101,11 @@ void gpio_write_bit(int pin, int val) } if (val) - out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | GPIO_VAL(pin)); + out_be32((void *)GPIO0_OR + offs, + in_be32((void *)GPIO0_OR + offs) | GPIO_VAL(pin)); else - out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin)); + out_be32((void *)GPIO0_OR + offs, + in_be32((void *)GPIO0_OR + offs) & ~GPIO_VAL(pin)); } int gpio_read_out_bit(int pin) @@ -112,10 +117,10 @@ int gpio_read_out_bit(int pin) pin -= GPIO_MAX; } - return (in32(GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0); + return (in_be32((void *)GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0); } -#if defined(CFG_440_GPIO_TABLE) +#if defined(CFG_4xx_GPIO_TABLE) void gpio_set_chip_configuration(void) { unsigned char i=0, j=0, offs=0, gpio_core; @@ -141,24 +146,24 @@ void gpio_set_chip_configuration(void) break; case GPIO_ALT1: - reg = in32(GPIO_IS1(core_add+offs)) + reg = in_be32((void *)GPIO_IS1(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS1(core_add+offs), reg); + out_be32((void *)GPIO_IS1(core_add+offs), reg); break; case GPIO_ALT2: - reg = in32(GPIO_IS2(core_add+offs)) + reg = in_be32((void *)GPIO_IS2(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS2(core_add+offs), reg); + out_be32((void *)GPIO_IS2(core_add+offs), reg); break; case GPIO_ALT3: - reg = in32(GPIO_IS3(core_add+offs)) + reg = in_be32((void *)GPIO_IS3(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_IN_SEL >> (j*2)); - out32(GPIO_IS3(core_add+offs), reg); + out_be32((void *)GPIO_IS3(core_add+offs), reg); break; } } @@ -168,87 +173,66 @@ void gpio_set_chip_configuration(void) switch (gpio_tab[gpio_core][i].alt_nb) { case GPIO_SEL: - if (gpio_core == GPIO0) { - /* - * Setup output value - * 1 -> high level - * 0 -> low level - * else -> don't touch - */ - reg = in32(GPIO0_OR); - if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) - reg |= (0x80000000 >> (i)); - else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0) - reg &= ~(0x80000000 >> (i)); - out32(GPIO0_OR, reg); - - reg = in32(GPIO0_TCR) | (0x80000000 >> (i)); - out32(GPIO0_TCR, reg); - } - -#ifdef GPIO1 - if (gpio_core == GPIO1) { - /* - * Setup output value - * 1 -> high level - * 0 -> low level - * else -> don't touch - */ - reg = in32(GPIO1_OR); - if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) - reg |= (0x80000000 >> (i)); - else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0) - reg &= ~(0x80000000 >> (i)); - out32(GPIO1_OR, reg); - - reg = in32(GPIO1_TCR) | (0x80000000 >> (i)); - out32(GPIO1_TCR, reg); - } -#endif /* GPIO1 */ - - reg = in32(GPIO_OS(core_add+offs)) + /* + * Setup output value + * 1 -> high level + * 0 -> low level + * else -> don't touch + */ + reg = in_be32((void *)GPIO_OR(core_add)); + if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) + reg |= (0x80000000 >> (i)); + else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0) + reg &= ~(0x80000000 >> (i)); + out_be32((void *)GPIO_OR(core_add), reg); + + reg = in_be32((void *)GPIO_TCR(core_add)) | + (0x80000000 >> (i)); + out_be32((void *)GPIO_TCR(core_add), reg); + + reg = in_be32((void *)GPIO_OS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); - out32(GPIO_OS(core_add+offs), reg); - reg = in32(GPIO_TS(core_add+offs)) + out_be32((void *)GPIO_OS(core_add+offs), reg); + reg = in_be32((void *)GPIO_TS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); - out32(GPIO_TS(core_add+offs), reg); + out_be32((void *)GPIO_TS(core_add+offs), reg); break; case GPIO_ALT1: - reg = in32(GPIO_OS(core_add+offs)) + reg = in_be32((void *)GPIO_OS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_ALT1_SEL >> (j*2)); - out32(GPIO_OS(core_add+offs), reg); - reg = in32(GPIO_TS(core_add+offs)) + out_be32((void *)GPIO_OS(core_add+offs), reg); + reg = in_be32((void *)GPIO_TS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_ALT1_SEL >> (j*2)); - out32(GPIO_TS(core_add+offs), reg); + out_be32((void *)GPIO_TS(core_add+offs), reg); break; case GPIO_ALT2: - reg = in32(GPIO_OS(core_add+offs)) + reg = in_be32((void *)GPIO_OS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_ALT2_SEL >> (j*2)); - out32(GPIO_OS(core_add+offs), reg); - reg = in32(GPIO_TS(core_add+offs)) + out_be32((void *)GPIO_OS(core_add+offs), reg); + reg = in_be32((void *)GPIO_TS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_ALT2_SEL >> (j*2)); - out32(GPIO_TS(core_add+offs), reg); + out_be32((void *)GPIO_TS(core_add+offs), reg); break; case GPIO_ALT3: - reg = in32(GPIO_OS(core_add+offs)) + reg = in_be32((void *)GPIO_OS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_ALT3_SEL >> (j*2)); - out32(GPIO_OS(core_add+offs), reg); - reg = in32(GPIO_TS(core_add+offs)) + out_be32((void *)GPIO_OS(core_add+offs), reg); + reg = in_be32((void *)GPIO_TS(core_add+offs)) & ~(GPIO_MASK >> (j*2)); reg = reg | (GPIO_ALT3_SEL >> (j*2)); - out32(GPIO_TS(core_add+offs), reg); + out_be32((void *)GPIO_TS(core_add+offs), reg); break; } } } } } -#endif /* CFG_440_GPIO_TABLE */ +#endif /* CFG_4xx_GPIO_TABLE */ diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index ca565cc..2026cc9 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c @@ -52,7 +52,7 @@ struct irq_action { static struct irq_action irq_vecs[32]; void uic0_interrupt( void * parms); /* UIC0 handler */ -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) static struct irq_action irq_vecs1[32]; /* For UIC1 */ void uic1_interrupt( void * parms); /* UIC1 handler */ @@ -116,7 +116,7 @@ int interrupt_init_cpu (unsigned *decrementer_count) irq_vecs[vec].handler = NULL; irq_vecs[vec].arg = NULL; irq_vecs[vec].count = 0; -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) irq_vecs1[vec].handler = NULL; irq_vecs1[vec].arg = NULL; irq_vecs1[vec].count = 0; @@ -172,7 +172,7 @@ int interrupt_init_cpu (unsigned *decrementer_count) */ set_evpr(0x00000000); -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) #if !defined(CONFIG_440GX) /* Install the UIC1 handlers */ irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0); @@ -378,7 +378,7 @@ void uic0_interrupt( void * parms) #endif /* CONFIG_440GX */ -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) /* Handler for UIC1 interrupt */ void uic1_interrupt( void * parms) { @@ -525,7 +525,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) struct irq_action *irqa = irq_vecs; int i = vec; -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) if ((vec > 31) && (vec < 64)) { @@ -553,7 +553,7 @@ void irq_install_handler (int vec, interrupt_handler_t * handler, void *arg) irqa[i].handler = handler; irqa[i].arg = arg; -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) if ((vec > 31) && (vec < 64)) @@ -577,7 +577,7 @@ void irq_free_handler (int vec) struct irq_action *irqa = irq_vecs; int i = vec; -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) if ((vec > 31) && (vec < 64)) { @@ -599,7 +599,7 @@ void irq_free_handler (int vec) vec, irq_vecs[vec].handler); #endif -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) if ((vec > 31) && (vec < 64)) @@ -641,7 +641,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) int vec; printf ("\nInterrupt-Information:\n"); -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) printf ("\nUIC 0\n"); #endif printf ("Nr Routine Arg Count\n"); @@ -656,7 +656,7 @@ do_irqinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } } -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) printf ("\nUIC 1\n"); printf ("Nr Routine Arg Count\n"); diff --git a/cpu/ppc4xx/iop480_uart.c b/cpu/ppc4xx/iop480_uart.c new file mode 100644 index 0000000..8dd2267 --- /dev/null +++ b/cpu/ppc4xx/iop480_uart.c @@ -0,0 +1,238 @@ +/* + * (C) Copyright 2000-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <commproc.h> +#include <asm/processor.h> +#include <asm/io.h> +#include <watchdog.h> +#include "vecnum.h" + +#ifdef CONFIG_SERIAL_MULTI +#include <serial.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_IOP480 + +#define SPU_BASE 0x40000000 + +#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */ +#define spu_LineStat_w 0x04 /* Line Status Register (Set) */ +#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */ +#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */ +#define spu_BRateDivh 0x10 /* Baud rate divisor high */ +#define spu_BRateDivl 0x14 /* Baud rate divisor low */ +#define spu_CtlReg 0x18 /* Control Register */ +#define spu_RxCmd 0x1c /* Rx Command Register */ +#define spu_TxCmd 0x20 /* Tx Command Register */ +#define spu_RxBuff 0x24 /* Rx data buffer */ +#define spu_TxBuff 0x24 /* Tx data buffer */ + +/*-----------------------------------------------------------------------------+ + | Line Status Register. + +-----------------------------------------------------------------------------*/ +#define asyncLSRport1 0x40000000 +#define asyncLSRport1set 0x40000004 +#define asyncLSRDataReady 0x80 +#define asyncLSRFramingError 0x40 +#define asyncLSROverrunError 0x20 +#define asyncLSRParityError 0x10 +#define asyncLSRBreakInterrupt 0x08 +#define asyncLSRTxHoldEmpty 0x04 +#define asyncLSRTxShiftEmpty 0x02 + +/*-----------------------------------------------------------------------------+ + | Handshake Status Register. + +-----------------------------------------------------------------------------*/ +#define asyncHSRport1 0x40000008 +#define asyncHSRport1set 0x4000000c +#define asyncHSRDsr 0x80 +#define asyncLSRCts 0x40 + +/*-----------------------------------------------------------------------------+ + | Control Register. + +-----------------------------------------------------------------------------*/ +#define asyncCRport1 0x40000018 +#define asyncCRNormal 0x00 +#define asyncCRLoopback 0x40 +#define asyncCRAutoEcho 0x80 +#define asyncCRDtr 0x20 +#define asyncCRRts 0x10 +#define asyncCRWordLength7 0x00 +#define asyncCRWordLength8 0x08 +#define asyncCRParityDisable 0x00 +#define asyncCRParityEnable 0x04 +#define asyncCREvenParity 0x00 +#define asyncCROddParity 0x02 +#define asyncCRStopBitsOne 0x00 +#define asyncCRStopBitsTwo 0x01 +#define asyncCRDisableDtrRts 0x00 + +/*-----------------------------------------------------------------------------+ + | Receiver Command Register. + +-----------------------------------------------------------------------------*/ +#define asyncRCRport1 0x4000001c +#define asyncRCRDisable 0x00 +#define asyncRCREnable 0x80 +#define asyncRCRIntDisable 0x00 +#define asyncRCRIntEnabled 0x20 +#define asyncRCRDMACh2 0x40 +#define asyncRCRDMACh3 0x60 +#define asyncRCRErrorInt 0x10 +#define asyncRCRPauseEnable 0x08 + +/*-----------------------------------------------------------------------------+ + | Transmitter Command Register. + +-----------------------------------------------------------------------------*/ +#define asyncTCRport1 0x40000020 +#define asyncTCRDisable 0x00 +#define asyncTCREnable 0x80 +#define asyncTCRIntDisable 0x00 +#define asyncTCRIntEnabled 0x20 +#define asyncTCRDMACh2 0x40 +#define asyncTCRDMACh3 0x60 +#define asyncTCRTxEmpty 0x10 +#define asyncTCRErrorInt 0x08 +#define asyncTCRStopPause 0x04 +#define asyncTCRBreakGen 0x02 + +/*-----------------------------------------------------------------------------+ + | Miscellanies defines. + +-----------------------------------------------------------------------------*/ +#define asyncTxBufferport1 0x40000024 +#define asyncRxBufferport1 0x40000024 +#define asyncDLABLsbport1 0x40000014 +#define asyncDLABMsbport1 0x40000010 +#define asyncXOFFchar 0x13 +#define asyncXONchar 0x11 + +/* + * Minimal serial functions needed to use one of the SMC ports + * as serial console interface. + */ + +int serial_init (void) +{ + volatile char val; + unsigned short br_reg; + + br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); + + /* + * Init onboard UART + */ + out_8((u8 *)SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */ + out_8((u8 *)SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */ + out_8((u8 *)SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */ + out_8((u8 *)SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */ + out_8((u8 *)SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */ + out_8((u8 *)SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */ + out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ + val = in_8((u8 *)SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */ + + return (0); +} + +void serial_setbrg (void) +{ + unsigned short br_reg; + + br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1); + + out_8((u8 *)SPU_BASE + spu_BRateDivl, + (br_reg & 0x00ff)); /* Set baud rate divisor... */ + out_8((u8 *)SPU_BASE + spu_BRateDivh, + ((br_reg & 0xff00) >> 8)); /* ... */ +} + +void serial_putc (const char c) +{ + if (c == '\n') + serial_putc ('\r'); + + /* load status from handshake register */ + if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00) + out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ + + out_8((u8 *)SPU_BASE + spu_TxBuff, c); /* Put char */ + + while ((in_8((u8 *)SPU_BASE + spu_LineStat_rc) & 04) != 04) { + if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00) + out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */ + } +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc () +{ + unsigned char status = 0; + + while (1) { + status = in_8((u8 *)asyncLSRport1); + if ((status & asyncLSRDataReady) != 0x0) { + break; + } + if ((status & ( asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt )) != 0) { + (void) out_8((u8 *)asyncLSRport1, + asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt ); + } + } + return (0x000000ff & (int) in_8((u8 *)asyncRxBufferport1)); +} + +int serial_tstc () +{ + unsigned char status; + + status = in_8((u8 *)asyncLSRport1); + if ((status & asyncLSRDataReady) != 0x0) { + return (1); + } + if ((status & ( asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt )) != 0) { + (void) out_8((u8 *)asyncLSRport1, + asyncLSRFramingError | + asyncLSROverrunError | + asyncLSRParityError | + asyncLSRBreakInterrupt); + } + return 0; +} + +#endif /* CONFIG_IOP480 */ diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S index 8c4bbf2..42b9546 100644 --- a/cpu/ppc4xx/kgdb.S +++ b/cpu/ppc4xx/kgdb.S @@ -56,21 +56,21 @@ kgdb_flush_cache_all: .globl kgdb_flush_cache_range kgdb_flush_cache_range: - li r5,CFG_CACHELINE_SIZE-1 + li r5,L1_CACHE_BYTES-1 andc r3,r3,r5 subf r4,r3,r4 add r4,r4,r5 - srwi. r4,r4,CFG_CACHELINE_SHIFT + srwi. r4,r4,L1_CACHE_SHIFT beqlr mtctr r4 mr r6,r3 1: dcbst 0,r3 - addi r3,r3,CFG_CACHELINE_SIZE + addi r3,r3,L1_CACHE_BYTES bdnz 1b sync /* wait for dcbst's to get to ram */ mtctr r4 2: icbi 0,r6 - addi r6,r6,CFG_CACHELINE_SIZE + addi r6,r6,L1_CACHE_BYTES bdnz 2b SYNC blr diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index 6b98025..98ba0a7 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -44,6 +44,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/io.h> #include <ppc_asm.tmpl> #include <commproc.h> #include <ppc4xx_enet.h> @@ -113,7 +114,7 @@ unsigned int miiphy_getemac_offset (void) unsigned long eoffset; /* Need to find out which mdi port we're using */ - zmii = in32 (ZMII_FER); + zmii = in_be32((void *)ZMII_FER); if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) { /* using port 0 */ @@ -131,16 +132,26 @@ unsigned int miiphy_getemac_offset (void) /* None of the mdi ports are enabled! */ /* enable port 0 */ zmii |= ZMII_FER_MDI << ZMII_FER_V (0); - out32 (ZMII_FER, zmii); + out_be32((void *)ZMII_FER, zmii); eoffset = 0; /* need to soft reset port 0 */ - zmii = in32 (EMAC_M0); + zmii = in_be32((void *)EMAC_M0); zmii |= EMAC_M0_SRST; - out32 (EMAC_M0, zmii); + out_be32((void *)EMAC_M0, zmii); } return (eoffset); #else + +#if defined(CONFIG_NET_MULTI) && defined(CONFIG_405EX) + unsigned long rgmii; + int devnum = 1; + + rgmii = in_be32((void *)RGMII_FER); + if (rgmii & (1 << (19 - devnum))) + return 0x100; +#endif + return 0; #endif } @@ -159,11 +170,11 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, i = 0; /* see if it is ready for sec */ - while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { + while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { udelay (7); if (i > 5) { #ifdef ET_DEBUG - sta_reg = in32 (EMAC_STACR + emac_reg); + sta_reg = in_be32((void *)EMAC_STACR + emac_reg); printf ("read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ printf ("read err 1\n"); #endif @@ -174,7 +185,8 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_READ; #else @@ -186,17 +198,18 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, #if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ - !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) + !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ + !defined(CONFIG_405EX) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; #endif sta_reg = sta_reg | (addr << 5); /* Phy address */ sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ - out32 (EMAC_STACR + emac_reg, sta_reg); + out_be32((void *)EMAC_STACR + emac_reg, sta_reg); #ifdef ET_DEBUG printf ("a2: write: EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif - sta_reg = in32 (EMAC_STACR + emac_reg); + sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG printf ("a21: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif @@ -207,7 +220,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, return -1; } i++; - sta_reg = in32 (EMAC_STACR + emac_reg); + sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG printf ("a22: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif @@ -238,7 +251,7 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, /* see if it is ready for 1000 nsec */ i = 0; - while ((in32 (EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { + while ((in_be32((void *)EMAC_STACR + emac_reg) & EMAC_STACR_OC) == EMAC_STACR_OC_MASK) { if (i > 5) return -1; udelay (7); @@ -248,7 +261,8 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | EMAC_STACR_WRITE; #else @@ -260,18 +274,19 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, #if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) && \ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ - !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) + !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ + !defined(CONFIG_405EX) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ #endif sta_reg = sta_reg | ((unsigned long) addr << 5);/* Phy address */ sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ memcpy (&sta_reg, &value, 2); /* put in data */ - out32 (EMAC_STACR + emac_reg, sta_reg); + out_be32((void *)EMAC_STACR + emac_reg, sta_reg); /* wait for completion */ i = 0; - sta_reg = in32 (EMAC_STACR + emac_reg); + sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG printf ("a31: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif @@ -280,7 +295,7 @@ int emac4xx_miiphy_write (char *devname, unsigned char addr, if (i > 5) return -1; i++; - sta_reg = in32 (EMAC_STACR + emac_reg); + sta_reg = in_be32((void *)EMAC_STACR + emac_reg); #ifdef ET_DEBUG printf ("a32: read : EMAC_STACR=0x%0x\n", sta_reg); /* test-only */ #endif diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index 3984577..ec1b38c 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -34,7 +34,7 @@ #if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY) && \ (defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EZ)) + defined(CONFIG_405EZ) || defined(CONFIG_405EX)) #include <nand.h> #include <linux/mtd/ndfc.h> @@ -222,6 +222,7 @@ int board_nand_init(struct nand_chip *nand) */ board_nand_select_device(nand, cs); out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), 0x80002222); + return 0; } diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index da5330a..9006614 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000 + * (C) Copyright 2000-2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_405GP) || defined(CONFIG_405CR) -void get_sys_info (PPC405_SYS_INFO * sysInfo) +void get_sys_info (PPC4xx_SYS_INFO * sysInfo) { unsigned long pllmr; unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000); @@ -162,6 +162,8 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv; } } + + sysInfo->freqUART = sysInfo->freqProcessor; } @@ -173,7 +175,7 @@ ulong get_OPB_freq (void) { ulong val = 0; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; get_sys_info (&sys_info); val = sys_info.freqPLB / sys_info.pllOpbDiv; @@ -189,7 +191,7 @@ ulong get_OPB_freq (void) ulong get_PCI_freq (void) { ulong val; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; get_sys_info (&sys_info); val = sys_info.freqPLB / sys_info.pllPciDiv; @@ -216,7 +218,7 @@ void get_sys_info (sys_info_t *sysInfo) */ /* Decode CPR0_PLLD0 for divisors */ - mfclk(clk_plld, reg); + mfcpr(clk_plld, reg); temp = (reg & PLLD_FWDVA_MASK) >> 16; sysInfo->pllFwdDivA = temp ? temp : 16; temp = (reg & PLLD_FWDVB_MASK) >> 8; @@ -225,19 +227,19 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->pllFbkDiv = temp ? temp : 32; lfdiv = reg & PLLD_LFBDV_MASK; - mfclk(clk_opbd, reg); + mfcpr(clk_opbd, reg); temp = (reg & OPBDDV_MASK) >> 24; sysInfo->pllOpbDiv = temp ? temp : 4; - mfclk(clk_perd, reg); + mfcpr(clk_perd, reg); temp = (reg & PERDV_MASK) >> 24; sysInfo->pllExtBusDiv = temp ? temp : 8; - mfclk(clk_primbd, reg); + mfcpr(clk_primbd, reg); temp = (reg & PRBDV_MASK) >> 24; prbdv0 = temp ? temp : 8; - mfclk(clk_spcid, reg); + mfcpr(clk_spcid, reg); temp = (reg & SPCID_MASK) >> 24; sysInfo->pllPciDiv = temp ? temp : 4; @@ -246,7 +248,7 @@ void get_sys_info (sys_info_t *sysInfo) temp = (reg & PLLSYS0_SEL_MASK) >> 27; if (temp == 0) { /* PLL output */ /* Figure which pll to use */ - mfclk(clk_pllc, reg); + mfcpr(clk_pllc, reg); temp = (reg & PLLC_SRC_MASK) >> 29; if (!temp) /* PLLOUTA */ m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA; @@ -263,8 +265,9 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0; sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; - sysInfo->freqEPB = sysInfo->freqPLB/sysInfo->pllExtBusDiv; + sysInfo->freqEBC = sysInfo->freqPLB/sysInfo->pllExtBusDiv; sysInfo->freqPCI = sysInfo->freqPLB/sysInfo->pllPciDiv; + sysInfo->freqUART = sysInfo->freqPLB; /* Figure which timer source to use */ if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */ @@ -277,6 +280,7 @@ void get_sys_info (sys_info_t *sysInfo) else /* Internal clock */ sysInfo->freqTmrClk = sysInfo->freqProcessor; } + /******************************************** * get_PCI_freq * return PCI bus freq in Hz @@ -317,8 +321,8 @@ void get_sys_info (sys_info_t * sysInfo) if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */ sysInfo->freqPLB >>= 1; sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; - sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv; - + sysInfo->freqEBC = sysInfo->freqOPB/sysInfo->pllExtBusDiv; + sysInfo->freqUART = sysInfo->freqPLB; } #else void get_sys_info (sys_info_t * sysInfo) @@ -393,7 +397,7 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA; sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0; sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; - sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv; + sysInfo->freqEBC = sysInfo->freqOPB/sysInfo->pllExtBusDiv; #if defined(CONFIG_YUCCA) /* Determine PCI Clock Period */ @@ -403,7 +407,7 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); #endif - + sysInfo->freqUART = sysInfo->freqPLB; } #endif @@ -632,7 +636,8 @@ extern void get_sys_info (sys_info_t * sysInfo); extern ulong get_PCI_freq (void); #elif defined(CONFIG_AP1000) -void get_sys_info (sys_info_t * sysInfo) { +void get_sys_info (sys_info_t * sysInfo) +{ sysInfo->freqProcessor = 240 * 1000 * 1000; sysInfo->freqPLB = 80 * 1000 * 1000; sysInfo->freqPCI = 33 * 1000 * 1000; @@ -640,17 +645,16 @@ void get_sys_info (sys_info_t * sysInfo) { #elif defined(CONFIG_405) -void get_sys_info (sys_info_t * sysInfo) { - +void get_sys_info (sys_info_t * sysInfo) +{ sysInfo->freqVCOMhz=3125000; sysInfo->freqProcessor=12*1000*1000; sysInfo->freqPLB=50*1000*1000; sysInfo->freqPCI=66*1000*1000; - } #elif defined(CONFIG_405EP) -void get_sys_info (PPC405_SYS_INFO * sysInfo) +void get_sys_info (PPC4xx_SYS_INFO * sysInfo) { unsigned long pllmr0; unsigned long pllmr1; @@ -678,9 +682,8 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) * Determine FBK_DIV. */ sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20); - if (sysInfo->pllFbkDiv == 0) { + if (sysInfo->pllFbkDiv == 0) sysInfo->pllFbkDiv = 16; - } /* * Determine PLB_DIV. @@ -733,6 +736,10 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) * Determine PLB clock frequency */ sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv; + + sysInfo->freqEBC = sysInfo->freqPLB / sysInfo->pllExtBusDiv; + + sysInfo->freqUART = sysInfo->freqProcessor * pllmr0_ccdv; } @@ -744,7 +751,7 @@ ulong get_OPB_freq (void) { ulong val = 0; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; get_sys_info (&sys_info); val = sys_info.freqPLB / sys_info.pllOpbDiv; @@ -760,7 +767,7 @@ ulong get_OPB_freq (void) ulong get_PCI_freq (void) { ulong val; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; get_sys_info (&sys_info); val = sys_info.freqPLB / sys_info.pllPciDiv; @@ -768,7 +775,7 @@ ulong get_PCI_freq (void) } #elif defined(CONFIG_405EZ) -void get_sys_info (PPC405_SYS_INFO * sysInfo) +void get_sys_info (PPC4xx_SYS_INFO * sysInfo) { unsigned long cpr_plld; unsigned long cpr_pllc; @@ -806,6 +813,7 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) * Read CPR_PRIMAD register */ mfcpr(cprprimad, cpr_primad); + /* * Determine PLB_DIV. */ @@ -856,6 +864,11 @@ void get_sys_info (PPC405_SYS_INFO * sysInfo) */ sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * m) / sysInfo->pllFwdDiv / sysInfo->pllPlbDiv; + + sysInfo->freqEBC = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / + sysInfo->pllExtBusDiv; + + sysInfo->freqUART = sysInfo->freqVCOHz; } /******************************************** @@ -866,7 +879,7 @@ ulong get_OPB_freq (void) { ulong val = 0; - PPC405_SYS_INFO sys_info; + PPC4xx_SYS_INFO sys_info; get_sys_info (&sys_info); val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv; @@ -874,13 +887,176 @@ ulong get_OPB_freq (void) return val; } +#elif defined(CONFIG_405EX) + +/* + * TODO: We need to get the CPR registers and calculate these values correctly!!!! + * We need the specs!!!! + */ +static unsigned char get_fbdv(unsigned char index) +{ + unsigned char ret = 0; + /* This is table should be 256 bytes. + * Only take first 52 values. + */ + unsigned char fbdv_tb[] = { + 0x00, 0xff, 0x7f, 0xfd, + 0x7a, 0xf5, 0x6a, 0xd5, + 0x2a, 0xd4, 0x29, 0xd3, + 0x26, 0xcc, 0x19, 0xb3, + 0x67, 0xce, 0x1d, 0xbb, + 0x77, 0xee, 0x5d, 0xba, + 0x74, 0xe9, 0x52, 0xa5, + 0x4b, 0x96, 0x2c, 0xd8, + 0x31, 0xe3, 0x46, 0x8d, + 0x1b, 0xb7, 0x6f, 0xde, + 0x3d, 0xfb, 0x76, 0xed, + 0x5a, 0xb5, 0x6b, 0xd6, + 0x2d, 0xdb, 0x36, 0xec, + + }; + + if ((index & 0x7f) == 0) + return 1; + while (ret < sizeof (fbdv_tb)) { + if (fbdv_tb[ret] == index) + break; + ret++; + } + ret++; + + return ret; +} + +#define PLL_FBK_PLL_LOCAL 0 +#define PLL_FBK_CPU 1 +#define PLL_FBK_PERCLK 5 + +void get_sys_info (sys_info_t * sysInfo) +{ + unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000); + unsigned long m = 1; + unsigned int tmp; + unsigned char fwdva[16] = { + 1, 2, 14, 9, 4, 11, 16, 13, + 12, 5, 6, 15, 10, 7, 8, 3, + }; + unsigned char sel, cpudv0, plb2xDiv; + + mfcpr(cpr0_plld, tmp); + + /* + * Determine forward divider A + */ + sysInfo->pllFwdDiv = fwdva[((tmp >> 16) & 0x0f)]; /* FWDVA */ + + /* + * Determine FBK_DIV. + */ + sysInfo->pllFbkDiv = get_fbdv(((tmp >> 24) & 0x0ff)); /* FBDV */ + + /* + * Determine PLBDV0 + */ + sysInfo->pllPlbDiv = 2; + + /* + * Determine PERDV0 + */ + mfcpr(cpr0_perd, tmp); + tmp = (tmp >> 24) & 0x03; + sysInfo->pllExtBusDiv = (tmp == 0) ? 4 : tmp; + + /* + * Determine OPBDV0 + */ + mfcpr(cpr0_opbd, tmp); + tmp = (tmp >> 24) & 0x03; + sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp; + + /* Determine PLB2XDV0 */ + mfcpr(cpr0_plbd, tmp); + tmp = (tmp >> 16) & 0x07; + plb2xDiv = (tmp == 0) ? 8 : tmp; + + /* Determine CPUDV0 */ + mfcpr(cpr0_cpud, tmp); + tmp = (tmp >> 24) & 0x07; + cpudv0 = (tmp == 0) ? 8 : tmp; + + /* Determine SEL(5:7) in CPR0_PLLC */ + mfcpr(cpr0_pllc, tmp); + sel = (tmp >> 24) & 0x07; + + /* + * Determine the M factor + * PLL local: M = FBDV + * CPU clock: M = FBDV * FWDVA * CPUDV0 + * PerClk : M = FBDV * FWDVA * PLB2XDV0 * PLBDV0(2) * OPBDV0 * PERDV0 + * + */ + switch (sel) { + case PLL_FBK_CPU: + m = sysInfo->pllFwdDiv * cpudv0; + break; + case PLL_FBK_PERCLK: + m = sysInfo->pllFwdDiv * plb2xDiv * 2 + * sysInfo->pllOpbDiv * sysInfo->pllExtBusDiv; + break; + case PLL_FBK_PLL_LOCAL: + break; + default: + printf("%s unknown m\n", __FUNCTION__); + return; + + } + m *= sysInfo->pllFbkDiv; + + /* + * Determine VCO clock frequency + */ + sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) / + (unsigned long long)sysClkPeriodPs; + + /* + * Determine CPU clock frequency + */ + sysInfo->freqProcessor = sysInfo->freqVCOHz / (sysInfo->pllFwdDiv * cpudv0); + + /* + * Determine PLB clock frequency, ddr1x should be the same + */ + sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDiv * plb2xDiv * 2); + sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv; + sysInfo->freqDDR = sysInfo->freqPLB; + sysInfo->freqEBC = sysInfo->freqOPB / sysInfo->pllExtBusDiv; + sysInfo->freqUART = sysInfo->freqPLB; +} + +/******************************************** + * get_OPB_freq + * return OPB bus freq in Hz + *********************************************/ +ulong get_OPB_freq (void) +{ + ulong val = 0; + + PPC4xx_SYS_INFO sys_info; + + get_sys_info (&sys_info); + val = sys_info.freqPLB / sys_info.pllOpbDiv; + + return val; +} + #endif int get_clocks (void) { #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_440) || defined(CONFIG_405) + defined(CONFIG_405EX) || defined(CONFIG_405) || \ + defined(CONFIG_440) sys_info_t sys_info; get_sys_info (&sys_info); @@ -907,7 +1083,8 @@ ulong get_bus_freq (ulong dummy) #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_440) || defined(CONFIG_405) + defined(CONFIG_405EX) || defined(CONFIG_405) || \ + defined(CONFIG_440) sys_info_t sys_info; get_sys_info (&sys_info); diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 9626b65..f5a135f 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -800,7 +800,7 @@ _start: /*----------------------------------------------------------------------- */ /* Enable two 128MB cachable regions. */ /*----------------------------------------------------------------------- */ - addis r1,r0,0x8000 + addis r1,r0,0xc000 addi r1,r1,0x0001 mticcr r1 /* instruction cache */ @@ -823,12 +823,23 @@ _start: /*****************************************************************************/ #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_405) + defined(CONFIG_405EX) || defined(CONFIG_405) /*----------------------------------------------------------------------- */ /* Clear and set up some registers. */ /*----------------------------------------------------------------------- */ addi r4,r0,0x0000 +#if !defined(CONFIG_405EX) mtspr sgr,r4 +#else + /* + * On 405EX, completely clearing the SGR leads to PPC hangup + * upon PCIe configuration access. The PCIe memory regions + * need to be guarded! + */ + lis r3,0x0000 + ori r3,r3,0x7FFC + mtspr sgr,r3 +#endif mtspr dcwr,r4 mtesr r4 /* clear Exception Syndrome Reg */ mttcr r4 /* clear Timer Control Reg */ @@ -851,7 +862,7 @@ _start: /*----------------------------------------------------------------------- */ /* Enable two 128MB cachable regions. */ /*----------------------------------------------------------------------- */ - lis r4,0x8000 + lis r4,0xc000 ori r4,r4,0x0001 mticcr r4 /* instruction cache */ isync @@ -860,12 +871,34 @@ _start: ori r4,r4,0x0000 mtdccr r4 /* data cache */ -#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) +#if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) || defined(CONFIG_405EX) /*----------------------------------------------------------------------- */ /* Tune the speed and size for flash CS0 */ /*----------------------------------------------------------------------- */ bl ext_bus_cntlr_init #endif +#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM)) + /* + * Boards like the Kilauea (405EX) don't have OCM and can't use + * DCache for init-ram. So setup stack here directly after the + * SDRAM is initialized. + */ + lis r1, CFG_INIT_RAM_ADDR@h + ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ + + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + /* + * Set up a dummy frame to store reset vector as return address. + * this causes stack underflow to reset board. + */ + stwu r1, -8(r1) /* Save back chain and move SP */ + lis r0, RESET_VECTOR@h /* Address of reset vector */ + ori r0, r0, RESET_VECTOR@l + stwu r1, -8(r1) /* Save back chain and move SP */ + stw r0, +12(r1) /* Save return addr (underflow vect) */ +#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */ #if defined(CONFIG_405EP) /*----------------------------------------------------------------------- */ @@ -983,7 +1016,7 @@ start_ram: ori r4,r4,0xa000 mtdcr ebccfgd,r4 - /* turn on data chache for this region */ + /* turn on data cache for this region */ lis r4,0x0080 mtdccr r4 @@ -1049,30 +1082,6 @@ start_ram: /*----------------------------------------------------------------------- */ bl sdram_init - /* - * Setup temporary stack pointer only for boards - * that do not use SDRAM SPD I2C stuff since it - * is already initialized to use DCACHE or OCM - * stacks. - */ -#if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM)) - lis r1, CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ - - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ - /* - * Set up a dummy frame to store reset vector as return address. - * this causes stack underflow to reset board. - */ - stwu r1, -8(r1) /* Save back chain and move SP */ - lis r0, RESET_VECTOR@h /* Address of reset vector */ - ori r0, r0, RESET_VECTOR@l - stwu r1, -8(r1) /* Save back chain and move SP */ - stw r0, +12(r1) /* Save return addr (underflow vect) */ -#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */ - #ifdef CONFIG_NAND_SPL bl nand_boot /* will not return */ #else @@ -1211,111 +1220,6 @@ mck_return: #endif /* CONFIG_440 */ -/* - * Cache functions. - * - * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM, - * although for some cache-ralated calls stubs have to be provided to satisfy - * symbols resolution. - * Icache-related functions are used in POST framework. - * - */ -#ifdef CONFIG_440 - .globl dcache_disable - .globl icache_disable - .globl icache_enable -dcache_disable: -icache_disable: -icache_enable: - blr - - .globl dcache_status - .globl icache_status -dcache_status: -icache_status: - mr r3, 0 - blr -#else -flush_dcache: - addis r9,r0,0x0002 /* set mask for EE and CE msr bits */ - ori r9,r9,0x8000 - mfmsr r12 /* save msr */ - andc r9,r12,r9 - mtmsr r9 /* disable EE and CE */ - addi r10,r0,0x0001 /* enable data cache for unused memory */ - mfdccr r9 /* region 0xF8000000-0xFFFFFFFF via */ - or r10,r10,r9 /* bit 31 in dccr */ - mtdccr r10 - - /* do loop for # of congruence classes. */ - lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */ - ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l - lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */ - ori r11,r11,(CFG_DCACHE_SIZE / 2)@l /* D cache set size - 2 way sets */ - mtctr r10 - addi r10,r0,(0xE000-0x10000) /* start at 0xFFFFE000 */ - add r11,r10,r11 /* add to get to other side of cache line */ -..flush_dcache_loop: - lwz r3,0(r10) /* least recently used side */ - lwz r3,0(r11) /* the other side */ - dccci r0,r11 /* invalidate both sides */ - addi r10,r10,CFG_CACHELINE_SIZE /* bump to next line */ - addi r11,r11,CFG_CACHELINE_SIZE /* bump to next line */ - bdnz ..flush_dcache_loop - sync /* allow memory access to complete */ - mtdccr r9 /* restore dccr */ - mtmsr r12 /* restore msr */ - blr - - .globl icache_enable -icache_enable: - mflr r8 - bl invalidate_icache - mtlr r8 - isync - addis r3,r0, 0x8000 /* set bit 0 */ - mticcr r3 - blr - - .globl icache_disable -icache_disable: - addis r3,r0, 0x0000 /* clear bit 0 */ - mticcr r3 - isync - blr - - .globl icache_status -icache_status: - mficcr r3 - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr - - .globl dcache_enable -dcache_enable: - mflr r8 - bl invalidate_dcache - mtlr r8 - isync - addis r3,r0, 0x8000 /* set bit 0 */ - mtdccr r3 - blr - - .globl dcache_disable -dcache_disable: - mflr r8 - bl flush_dcache - mtlr r8 - addis r3,r0, 0x0000 /* clear bit 0 */ - mtdccr r3 - blr - - .globl dcache_status -dcache_status: - mfdccr r3 - srwi r3, r3, 31 /* >>31 => select bit 0 */ - blr -#endif - .globl get_pvr get_pvr: mfspr r3, PVR @@ -1421,6 +1325,26 @@ ppcSync: */ .globl relocate_code relocate_code: +#ifdef CONFIG_4xx_DCACHE + /* + * We need to flush the Init Data before the dcache will be + * invalidated + */ + + /* save regs */ + mr r9,r3 + mr r10,r4 + mr r11,r5 + + mr r3,r4 + addi r4,r4,0x200 /* should be enough for init data */ + bl flush_dcache_range + + /* restore regs */ + mr r3,r9 + mr r4,r10 + mr r5,r11 +#endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) @@ -1448,7 +1372,7 @@ relocate_code: ori r4, r4, CFG_MONITOR_BASE@l lwz r5, GOT(__init_end) sub r5, r5, r4 - li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + li r6, L1_CACHE_BYTES /* Cache Line Size */ /* * Fix GOT pointer: @@ -1768,23 +1692,6 @@ in32: lwz 3,0x0000(3) blr -invalidate_icache: - iccci r0,r0 /* for 405, iccci invalidates the */ - blr /* entire I cache */ - -invalidate_dcache: - addi r6,0,0x0000 /* clear GPR 6 */ - /* Do loop for # of dcache congruence classes. */ - lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */ - ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l - /* NOTE: dccci invalidates both */ - mtctr r7 /* ways in the D cache */ -..dcloop: - dccci 0,r6 /* invalidate line */ - addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */ - bdnz ..dcloop - blr - /**************************************************************************/ /* PPC405EP specific stuff */ /**************************************************************************/ diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c index 098694c..ed493f1 100644 --- a/cpu/ppc4xx/tlb.c +++ b/cpu/ppc4xx/tlb.c @@ -26,6 +26,7 @@ #if defined(CONFIG_440) #include <ppc440.h> +#include <asm/cache.h> #include <asm/io.h> #include <asm/mmu.h> @@ -42,7 +43,6 @@ void remove_tlb(u32 vaddr, u32 size) u32 tlb_vaddr; u32 tlb_size = 0; - /* First, find the index of a TLB entry not being used */ for (i=0; i<PPC4XX_TLB_SIZE; i++) { tlb_word0_value = mftlb1(i); tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value); @@ -96,6 +96,92 @@ void remove_tlb(u32 vaddr, u32 size) asm("isync"); } +/* + * Change the I attribute (cache inhibited) of a TLB or multiple TLB's. + * This function is used to either turn cache on or off in a specific + * memory area. + */ +void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value) +{ + int i; + u32 tlb_word0_value; + u32 tlb_word2_value; + u32 tlb_vaddr; + u32 tlb_size = 0; + + for (i=0; i<PPC4XX_TLB_SIZE; i++) { + tlb_word0_value = mftlb1(i); + tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value); + if (((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_ENABLE) && + (tlb_vaddr >= vaddr)) { + /* + * TLB is enabled and start address is lower or equal + * than the area we are looking for. Now we only have + * to check the size/end address for a match. + */ + switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) { + case TLB_WORD0_SIZE_1KB: + tlb_size = 1 << 10; + break; + case TLB_WORD0_SIZE_4KB: + tlb_size = 4 << 10; + break; + case TLB_WORD0_SIZE_16KB: + tlb_size = 16 << 10; + break; + case TLB_WORD0_SIZE_64KB: + tlb_size = 64 << 10; + break; + case TLB_WORD0_SIZE_256KB: + tlb_size = 256 << 10; + break; + case TLB_WORD0_SIZE_1MB: + tlb_size = 1 << 20; + break; + case TLB_WORD0_SIZE_16MB: + tlb_size = 16 << 20; + break; + case TLB_WORD0_SIZE_256MB: + tlb_size = 256 << 20; + break; + } + + /* + * Now check the end-address if it's in the range + */ + if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) { + /* + * Found a TLB in the range. + * Change cache attribute in tlb2 word. + */ + tlb_word2_value = + TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE | + TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE | + TLB_WORD2_W_DISABLE | tlb_word2_i_value | + TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE | + TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE | + TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE | + TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE | + TLB_WORD2_SR_ENABLE; + + /* + * Now either flush or invalidate the dcache + */ + if (tlb_word2_i_value) + flush_dcache(); + else + invalidate_dcache(); + + mttlb3(i, tlb_word2_value); + asm("iccci 0,0"); + } + } + } + + /* Execute an ISYNC instruction so that the new TLB entry takes effect */ + asm("isync"); +} + static int add_tlb_entry(unsigned long phys_addr, unsigned long virt_addr, unsigned long tlb_word0_size_value, diff --git a/cpu/ppc4xx/usb.c b/cpu/ppc4xx/usb.c index 272ed8c..cb8d5c7 100644 --- a/cpu/ppc4xx/usb.c +++ b/cpu/ppc4xx/usb.c @@ -25,25 +25,41 @@ #if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT) +#ifdef CONFIG_4xx_DCACHE +#include <asm/mmu.h> +DECLARE_GLOBAL_DATA_PTR; +#endif + #include "usbdev.h" int usb_cpu_init(void) { +#ifdef CONFIG_4xx_DCACHE + /* disable cache */ + change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE); +#endif #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) usb_dev_init(); #endif - return 0; } int usb_cpu_stop(void) { +#ifdef CONFIG_4xx_DCACHE + /* enable cache */ + change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0); +#endif return 0; } int usb_cpu_init_fail(void) { +#ifdef CONFIG_4xx_DCACHE + /* enable cache */ + change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0); +#endif return 0; } diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h index bddf9e5..93e51b9 100644 --- a/cpu/ppc4xx/vecnum.h +++ b/cpu/ppc4xx/vecnum.h @@ -270,6 +270,110 @@ #define VECNUM_EIR3 30 /* External interrupt 3 */ #define VECNUM_EIR4 31 /* External interrupt 4 */ +#elif defined(CONFIG_405EX) + +/* UIC 0 */ +#define VECNUM_U0 00 +#define VECNUM_U1 01 +#define VECNUM_IIC0 02 +#define VECNUM_PKA 03 +#define VECNUM_TRNG 04 +#define VECNUM_EBM 05 +#define VECNUM_BGI 06 +#define VECNUM_IIC1 07 +#define VECNUM_SPI 08 +#define VECNUM_EIR0 09 +#define VECNUM_MTE 10 /* MAL Tx EOB */ +#define VECNUM_MRE 11 /* MAL Rx EOB */ +#define VECNUM_DMA0 12 +#define VECNUM_DMA1 13 +#define VECNUM_DMA2 14 +#define VECNUM_DMA3 15 +#define VECNUM_PCIE0AL 16 +#define VECNUM_PCIE0VPD 17 +#define VECNUM_RPCIE0HRST 18 +#define VECNUM_FPCIE0HRST 19 +#define VECNUM_PCIE0TCR 20 +#define VECNUM_PCIEMSI0 21 +#define VECNUM_PCIEMSI1 22 +#define VECNUM_SECURITY 23 +#define VECNUM_ETH0 24 +#define VECNUM_ETH1 25 +#define VECNUM_PCIEMSI2 26 +#define VECNUM_EIR4 27 +#define VECNUM_UIC2NC 28 +#define VECNUM_UIC2C 29 +#define VECNUM_UIC1NC 30 +#define VECNUM_UIC1C 31 + +/* UIC 1 */ +#define VECNUM_MS (32 + 00) /* MAL SERR */ +#define VECNUM_TXDE (32 + 01) /* MAL TXDE */ +#define VECNUM_RXDE (32 + 02) /* MAL RXDE */ +#define VECNUM_PCIE0BMVC0 (32 + 03) +#define VECNUM_PCIE0DCRERR (32 + 04) +#define VECNUM_EBC (32 + 05) +#define VECNUM_NDFC (32 + 06) +#define VECNUM_PCEI1DCRERR (32 + 07) +#define VECNUM_CT8 (32 + 08) +#define VECNUM_CT9 (32 + 09) +#define VECNUM_PCIE1AL (32 + 10) +#define VECNUM_PCIE1VPD (32 + 11) +#define VECNUM_RPCE1HRST (32 + 12) +#define VECNUM_FPCE1HRST (32 + 13) +#define VECNUM_PCIE1TCR (32 + 14) +#define VECNUM_PCIE1VC0 (32 + 15) +#define VECNUM_CT3 (32 + 16) +#define VECNUM_CT4 (32 + 17) +#define VECNUM_EIR7 (32 + 18) +#define VECNUM_EIR8 (32 + 19) +#define VECNUM_EIR9 (32 + 20) +#define VECNUM_CT5 (32 + 21) +#define VECNUM_CT6 (32 + 22) +#define VECNUM_CT7 (32 + 23) +#define VECNUM_SROM (32 + 24) /* SERIAL ROM */ +#define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */ +#define VECNUM_EIR2 (32 + 26) +#define VECNUM_EIR5 (32 + 27) +#define VECNUM_EIR6 (32 + 28) +#define VECNUM_EMAC0WAKE (32 + 29) +#define VECNUM_EIR1 (32 + 30) +#define VECNUM_EMAC1WAKE (32 + 31) + +/* UIC 2 */ +#define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */ +#define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */ +#define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */ +#define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */ +#define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */ +#define VECNUM_DDRMCUE (64 + 05) +#define VECNUM_DDRMCCE (64 + 06) +#define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */ +#define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */ +#define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */ +#define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */ +#define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */ +#define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */ +#define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */ +#define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */ +#define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */ +#define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */ +#define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */ +#define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */ +#define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */ +#define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */ +#define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */ +#define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */ +#define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */ +#define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */ +#define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */ +#define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */ +#define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */ +#define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */ +#define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */ +#define VECNUM_USBWAKE (64 + 30) /* USB wakup */ +#define VECNUM_USBOTG (64 + 31) /* USB OTG */ + #else /* !CONFIG_405EZ */ #define VECNUM_U0 0 /* UART0 */ diff --git a/drivers/hwmon/ds1775.c b/drivers/hwmon/ds1775.c index e44cee3..0fbb0b4 100644 --- a/drivers/hwmon/ds1775.c +++ b/drivers/hwmon/ds1775.c @@ -25,7 +25,7 @@ #include <i2c.h> #include <dtt.h> -#define DTT_I2C_DEV_CODE 0x49 /* Dallas Semi's DS1775 device code */ +#define DTT_I2C_DEV_CODE CFG_I2C_DTT_ADDR /* Dallas Semi's DS1775 device code */ int dtt_read(int sensor, int reg) { diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 4a22b0d..1d6016e 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -50,6 +50,7 @@ COBJS-y += pcf8563.o COBJS-y += s3c24x0_rtc.o COBJS-y += rs5c372.o COBJS-y += mcfrtc.o +COBJS-y += x1205.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/include/405_mal.h b/include/405_mal.h index 2a42184..7ea4eb1 100644 --- a/include/405_mal.h +++ b/include/405_mal.h @@ -92,7 +92,9 @@ #define MAL_ESR_PBEI 0x00000001 /* ^^ ^^ */ /* Mal IER */ -#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440SPE) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #define MAL_IER_PT 0x00000080 #define MAL_IER_PRE 0x00000040 #define MAL_IER_PWE 0x00000020 diff --git a/include/4xx_i2c.h b/include/4xx_i2c.h index 66b7997..7c79bd1 100644 --- a/include/4xx_i2c.h +++ b/include/4xx_i2c.h @@ -43,7 +43,7 @@ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700 + I2C_BUS_OFFS) -#elif defined(CONFIG_440) +#elif defined(CONFIG_440) || defined(CONFIG_405EX) /* all remaining 440 variants */ #define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400 + I2C_BUS_OFFS) #else diff --git a/include/405gp_pci.h b/include/asm-ppc/4xx_pci.h index 3c1adec..3c1adec 100644 --- a/include/405gp_pci.h +++ b/include/asm-ppc/4xx_pci.h diff --git a/cpu/ppc4xx/440spe_pcie.h b/include/asm-ppc/4xx_pcie.h index 38745eb..4c03b05 100644 --- a/cpu/ppc4xx/440spe_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -9,17 +9,38 @@ */ #include <ppc4xx.h> -#ifndef __440SPE_PCIE_H -#define __440SPE_PCIE_H - -#define mdelay(n) ({unsigned long __ms=(n); while (__ms--) udelay(1000);}) +#ifndef __4XX_PCIE_H +#define __4XX_PCIE_H #define DCRN_SDR0_CFGADDR 0x00e #define DCRN_SDR0_CFGDATA 0x00f +#if defined(CONFIG_440SPE) +#define CFG_PCIE_NR_PORTS 3 + +#define CFG_PCIE_ADDR_HIGH 0x0000000d + #define DCRN_PCIE0_BASE 0x100 #define DCRN_PCIE1_BASE 0x120 #define DCRN_PCIE2_BASE 0x140 + +#define PCIE0_SDR 0x300 +#define PCIE1_SDR 0x340 +#define PCIE2_SDR 0x370 +#endif + +#if defined(CONFIG_405EX) +#define CFG_PCIE_NR_PORTS 2 + +#define CFG_PCIE_ADDR_HIGH 0x00000000 + +#define DCRN_PCIE0_BASE 0x040 +#define DCRN_PCIE1_BASE 0x060 + +#define PCIE0_SDR 0x400 +#define PCIE1_SDR 0x440 +#endif + #define PCIE0 DCRN_PCIE0_BASE #define PCIE1 DCRN_PCIE1_BASE #define PCIE2 DCRN_PCIE2_BASE @@ -47,6 +68,28 @@ #define PESDR0_PLLLCT2 0x03a1 #define PESDR0_PLLLCT3 0x03a2 +/* common regs, at least for 405EX and 440SPe */ +#define SDRN_PESDR_UTLSET1(n) (sdr_base(n) + 0x00) +#define SDRN_PESDR_UTLSET2(n) (sdr_base(n) + 0x01) +#define SDRN_PESDR_DLPSET(n) (sdr_base(n) + 0x02) +#define SDRN_PESDR_LOOP(n) (sdr_base(n) + 0x03) +#define SDRN_PESDR_RCSSET(n) (sdr_base(n) + 0x04) +#define SDRN_PESDR_RCSSTS(n) (sdr_base(n) + 0x05) + +#if defined(CONFIG_440SPE) +#define SDRN_PESDR_HSSL0SET1(n) (sdr_base(n) + 0x06) +#define SDRN_PESDR_HSSL0SET2(n) (sdr_base(n) + 0x07) +#define SDRN_PESDR_HSSL0STS(n) (sdr_base(n) + 0x08) +#define SDRN_PESDR_HSSL1SET1(n) (sdr_base(n) + 0x09) +#define SDRN_PESDR_HSSL1SET2(n) (sdr_base(n) + 0x0a) +#define SDRN_PESDR_HSSL1STS(n) (sdr_base(n) + 0x0b) +#define SDRN_PESDR_HSSL2SET1(n) (sdr_base(n) + 0x0c) +#define SDRN_PESDR_HSSL2SET2(n) (sdr_base(n) + 0x0d) +#define SDRN_PESDR_HSSL2STS(n) (sdr_base(n) + 0x0e) +#define SDRN_PESDR_HSSL3SET1(n) (sdr_base(n) + 0x0f) +#define SDRN_PESDR_HSSL3SET2(n) (sdr_base(n) + 0x10) +#define SDRN_PESDR_HSSL3STS(n) (sdr_base(n) + 0x11) + #define PESDR0_UTLSET1 0x0300 #define PESDR0_UTLSET2 0x0301 #define PESDR0_DLPSET 0x0302 @@ -123,9 +166,44 @@ #define PESDR2_HSSCTLSET 0x0382 #define PESDR2_LANE_ABCD 0x0383 +#elif defined(CONFIG_405EX) + +#define SDRN_PESDR_PHYSET1(n) (sdr_base(n) + 0x06) +#define SDRN_PESDR_PHYSET2(n) (sdr_base(n) + 0x07) +#define SDRN_PESDR_BIST(n) (sdr_base(n) + 0x08) +#define SDRN_PESDR_LPB(n) (sdr_base(n) + 0x0b) +#define SDRN_PESDR_PHYSTA(n) (sdr_base(n) + 0x0c) + +#define PESDR0_UTLSET1 0x0400 +#define PESDR0_UTLSET2 0x0401 +#define PESDR0_DLPSET 0x0402 +#define PESDR0_LOOP 0x0403 +#define PESDR0_RCSSET 0x0404 +#define PESDR0_RCSSTS 0x0405 +#define PESDR0_PHYSET1 0x0406 +#define PESDR0_PHYSET2 0x0407 +#define PESDR0_BIST 0x0408 +#define PESDR0_LPB 0x040B +#define PESDR0_PHYSTA 0x040C + +#define PESDR1_UTLSET1 0x0440 +#define PESDR1_UTLSET2 0x0441 +#define PESDR1_DLPSET 0x0442 +#define PESDR1_LOOP 0x0443 +#define PESDR1_RCSSET 0x0444 +#define PESDR1_RCSSTS 0x0445 +#define PESDR1_PHYSET1 0x0446 +#define PESDR1_PHYSET2 0x0447 +#define PESDR1_BIST 0x0448 +#define PESDR1_LPB 0x044B +#define PESDR1_PHYSTA 0x044C + +#endif + /* * UTL register offsets */ +#define PEUTL_PBCTL 0x00 #define PEUTL_PBBSZ 0x20 #define PEUTL_OPDBSZ 0x68 #define PEUTL_IPHBSZ 0x70 @@ -133,6 +211,7 @@ #define PEUTL_OUTTR 0x90 #define PEUTL_INTR 0x98 #define PEUTL_PCTL 0xa0 +#define PEUTL_RCSTA 0xb0 #define PEUTL_RCIRQEN 0xb8 /* @@ -141,7 +220,8 @@ #define PECFG_BAR0LMPA 0x210 #define PECFG_BAR0HMPA 0x214 #define PECFG_BAR1MPA 0x218 -#define PECFG_BAR2MPA 0x220 +#define PECFG_BAR2LMPA 0x220 +#define PECFG_BAR2HMPA 0x224 #define PECFG_PIMEN 0x33c #define PECFG_PIM0LAL 0x340 @@ -164,11 +244,93 @@ #define GPL_DMER_MASK_DISA 0x02000000 -int ppc440spe_init_pcie(void); -int ppc440spe_init_pcie_rootport(int port); -void yucca_setup_pcie_fpga_rootpoint(int port); -void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port); -int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port); -int yucca_pcie_card_present(int port); +#define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL)) +#define U64_TO_U32_HIGH(val) ((u32)((val) >> 32)) + +/* + * Prototypes + */ +int ppc4xx_init_pcie(void); +int ppc4xx_init_pcie_rootport(int port); +int ppc4xx_init_pcie_endport(int port); +void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port); +int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port); int pcie_hose_scan(struct pci_controller *hose, int bus); -#endif /* __440SPE_PCIE_H */ + +/* + * Function to determine root port or endport from env variable. + */ +static inline int is_end_point(int port) +{ + char s[10], *tk; + char *pcie_mode = getenv("pcie_mode"); + + if (pcie_mode == NULL) + return 0; + + strcpy(s, pcie_mode); + tk = strtok(s, ":"); + + switch (port) { + case 0: + if (tk != NULL) { + if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) + return 1; + else + return 0; + } + else + return 0; + + case 1: + tk = strtok(NULL, ":"); + if (tk != NULL) { + if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) + return 1; + else + return 0; + } + else + return 0; + + case 2: + tk = strtok(NULL, ":"); + if (tk != NULL) + tk = strtok(NULL, ":"); + if (tk != NULL) { + if (!(strcmp(tk, "ep") && strcmp(tk, "EP"))) + return 1; + else + return 0; + } + else + return 0; + } + + return 0; +} + +static inline void mdelay(int n) +{ + u32 ms = n; + + while (ms--) + udelay(1000); +} + +static inline u32 sdr_base(int port) +{ + switch (port) { + default: /* to satisfy compiler */ + case 0: + return PCIE0_SDR; + case 1: + return PCIE1_SDR; +#if CFG_PCIE_NR_PORTS > 2 + case 2: + return PCIE2_SDR; +#endif + } +} + +#endif /* __4XX_PCIE_H */ diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 5befab4..e29bfc2 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -8,15 +8,24 @@ #include <asm/processor.h> /* bytes per L1 cache line */ -#if !defined(CONFIG_8xx) || defined(CONFIG_8260) +#if !(defined(CONFIG_8xx) || defined(CONFIG_IOP480)) #if defined(CONFIG_PPC64BRIDGE) -#define L1_CACHE_BYTES 128 +#define L1_CACHE_SHIFT 7 #else -#define L1_CACHE_BYTES 32 +#define L1_CACHE_SHIFT 5 #endif /* PPC64 */ #else -#define L1_CACHE_BYTES 16 -#endif /* !8xx || 8260 */ +#define L1_CACHE_SHIFT 4 +#endif /* !(8xx || IOP480) */ + +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +/* + * For compatibility reasons support the CFG_CACHELINE_SIZE too + */ +#ifndef CFG_CACHELINE_SIZE +#define CFG_CACHELINE_SIZE L1_CACHE_BYTES +#endif #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) #define L1_CACHE_PAGES 8 @@ -35,6 +44,8 @@ extern void flush_dcache_range(unsigned long start, unsigned long stop); extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void invalidate_dcache_range(unsigned long start, unsigned long stop); +extern void flush_dcache(void); +extern void invalidate_dcache(void); #ifdef CFG_INIT_RAM_LOCK extern void unlock_ram_in_cache(void); #endif /* CFG_INIT_RAM_LOCK */ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 4676e2c..05aee74 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -107,6 +107,9 @@ typedef struct global_data { unsigned int dp_alloc_base; unsigned int dp_alloc_top; #endif +#if defined(CONFIG_4xx) + u32 uart_clk; +#endif /* CONFIG_4xx */ #if defined(CFG_GT_6426x) unsigned int mirror_hack[16]; #endif diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h index c9b6a36..d0c3eba 100644 --- a/include/asm-ppc/gpio.h +++ b/include/asm-ppc/gpio.h @@ -21,6 +21,9 @@ * MA 02111-1307 USA */ +#ifndef __ASM_PPC_GPIO_H +#define __ASM_PPC_GPIO_H + /* 4xx PPC's have 2 GPIO controllers */ #if defined(CONFIG_405EZ) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -30,6 +33,36 @@ #define GPIO_GROUP_MAX 1 #endif +/* Offsets */ +#define GPIOx_OR 0x00 /* GPIO Output Register */ +#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ +#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ +#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ +#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ +#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ +#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ +#define GPIOx_IR 0x1C /* GPIO Input Register */ +#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ +#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ +#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ +#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ +#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ +#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ +#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ +#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ +#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ + +#define GPIO_OR(x) (x+GPIOx_OR) /* GPIO Output Register */ +#define GPIO_TCR(x) (x+GPIOx_TCR) /* GPIO Three-State Control Register */ +#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Select Register High or Low */ +#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ +#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ +#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ +#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ + +#define GPIO0 0 +#define GPIO1 1 + #define GPIO_MAX 32 #define GPIO_ALT1_SEL 0x40000000 #define GPIO_ALT2_SEL 0x80000000 @@ -56,3 +89,5 @@ void gpio_config(int pin, int in_out, int gpio_alt, int out_val); void gpio_write_bit(int pin, int val); int gpio_read_out_bit(int pin); void gpio_set_chip_configuration(void); + +#endif /* __ASM_PPC_GPIO_H */ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index b3cfa9b..edcb3b9 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -648,6 +648,7 @@ unsigned long mftlb3(unsigned long index); void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); void remove_tlb(u32 vaddr, u32 size); +void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_440 */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 0a160e2..f58b38a 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -91,6 +91,11 @@ /* Special Purpose Registers (SPRNs)*/ +/* PPC440 Architecture is BOOK-E */ +#ifdef CONFIG_440 +#define CONFIG_BOOKE +#endif + #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ #define SPRN_CTR 0x009 /* Count Register */ #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ @@ -765,6 +770,10 @@ #define PVR_405EP_RA 0x51210950 #define PVR_405GPR_RB 0x50910951 #define PVR_405EZ_RA 0x41511460 +#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A with Security */ +#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A without Security */ +#define PVR_405EX1_RA 0x12911477 /* 405EX rev A with Security */ +#define PVR_405EX2_RA 0x12911475 /* 405EX rev A without Security */ #define PVR_440GP_RB 0x40120440 #define PVR_440GP_RC 0x40120481 #define PVR_440EP_RA 0x42221850 diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index 464f6b5..bd9b6f7 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -84,6 +84,7 @@ typedef struct bd_info { defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || \ defined(CONFIG_405EZ) || \ + defined(CONFIG_405EX) || \ defined(CONFIG_440) unsigned char bi_s_version[4]; /* Version of this structure */ unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ diff --git a/include/bcd.h b/include/bcd.h new file mode 100644 index 0000000..c545308 --- /dev/null +++ b/include/bcd.h @@ -0,0 +1,20 @@ +/* Permission is hereby granted to copy, modify and redistribute this code + * in terms of the GNU Library General Public License, Version 2 or later, + * at your option. + */ + +/* macros to translate to/from binary and binary-coded decimal (frequently + * found in RTC chips). + */ + +#ifndef _BCD_H +#define _BCD_H + +#define BCD2BIN(val) (((val) & 0x0f) + ((val)>>4)*10) +#define BIN2BCD(val) ((((val)/10)<<4) + (val)%10) + +/* backwards compat */ +#define BCD_TO_BIN(val) ((val)=BCD2BIN(val)) +#define BIN_TO_BCD(val) ((val)=BIN2BCD(val)) + +#endif /* _BCD_H */ diff --git a/include/common.h b/include/common.h index 63ac8b0..edd0024 100644 --- a/include/common.h +++ b/include/common.h @@ -258,7 +258,7 @@ void pciinfo (int, int); int pci_pre_init (struct pci_controller * ); #endif -#if defined(CONFIG_PCI) && defined(CONFIG_440) +#if defined(CONFIG_PCI) && (defined(CONFIG_440) || defined(CONFIG_405EX)) # if defined(CFG_PCI_TARGET_INIT) void pci_target_init (struct pci_controller *); # endif @@ -266,7 +266,7 @@ void pciinfo (int, int); void pci_master_init (struct pci_controller *); # endif int is_pci_host (struct pci_controller *); -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_405EX) void pcie_setup_hoses(int busno); #endif #endif @@ -505,15 +505,13 @@ void get_sys_info ( sys_info_t * ); #if defined(CONFIG_4xx) || defined(CONFIG_IOP480) # if defined(CONFIG_440) - typedef PPC440_SYS_INFO sys_info_t; # if defined(CONFIG_440SPE) unsigned long determine_sysper(void); unsigned long determine_pci_clock_per(void); - int ppc440spe_revB(void); # endif -# else - typedef PPC405_SYS_INFO sys_info_t; # endif +typedef PPC4xx_SYS_INFO sys_info_t; +int ppc440spe_revB(void); void get_sys_info ( sys_info_t * ); #endif diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h index 4632991..5d28168 100644 --- a/include/configs/ADCIOP.h +++ b/include/configs/ADCIOP.h @@ -191,15 +191,6 @@ #define CFG_ETH_DEV_FN 0x0000 #define CFG_ETH_IOBASE 0x0fff0000 -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ -#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h index d25aa74..d490b33 100644 --- a/include/configs/AP1000.h +++ b/include/configs/AP1000.h @@ -193,14 +193,6 @@ #define CFG_ENV_ADDR \ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ #endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Init Memory Controller: diff --git a/include/configs/AR405.h b/include/configs/AR405.h index 0f301ec..50f09b0 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -213,16 +213,6 @@ #define CFG_ENV_ADDR_REDUND 0xFFFA0000 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 9adbba9..85c6a99 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -258,16 +258,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index ae32f6b..7029dbd 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -181,15 +181,6 @@ /* mask of address bits that overflow into the "EEPROM chip address" */ #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 21cd9c1..285cd5c 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -273,16 +273,6 @@ #define CFG_EEPROM_WREN 1 /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ #define CFG_PLD_BASE 0xf0000000 diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index a3717b9..58900c3 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -223,16 +223,6 @@ #define CFG_EEPROM_WREN 1 -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 1b948f6..bd43e1d 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -266,15 +266,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index fb71c5f..b248639 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -317,16 +317,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 4994319..1e9597d 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -288,16 +288,6 @@ #define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */ #define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 29f9292..a8029ea 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -319,16 +319,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h index 318ada1..eb47cd7 100644 --- a/include/configs/CPCI440.h +++ b/include/configs/CPCI440.h @@ -262,15 +262,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* Configuration Port location */ #define CONFIG_PORT_ADDR 0xF0000500 diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index c7b623a..78b754c 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -205,15 +205,6 @@ #define CFG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ /* total size of a CAT24WC08 is 1024 bytes */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index a965c12..2356858 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -192,12 +192,6 @@ #define CFG_MEMTEST_END (CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE) /* END ENVIRONNEMENT FLASH */ -/*----------------------------------------------------------------------- - * Cache Configuration. Only used to ..?? clear it, I guess.. - */ -#define CFG_DCACHE_SIZE 16384 -#define CFG_CACHELINE_SIZE 32 - /* * Init Memory Controller: * diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h index 627ea14..117a136 100644 --- a/include/configs/DASA_SIM.h +++ b/include/configs/DASA_SIM.h @@ -182,15 +182,6 @@ #define CFG_PCI9054_DEV_FN 0x0800 #define CFG_PCI9054_IOBASE 0x0eff0000 -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ -#define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 2eadbea..912fb2a 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -242,16 +242,6 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/DU405.h b/include/configs/DU405.h index 5c595f5..c8bf67f 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -232,15 +232,6 @@ #define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ /* total size of a CAT24WC08 is 1024 bytes */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index 5d48d2b..dc15b0c 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -323,14 +323,6 @@ #define CFG_ENV_ADDR \ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ #endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Init Memory Controller: diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h index a3f38bb..251227c 100644 --- a/include/configs/EXBITGEN.h +++ b/include/configs/EXBITGEN.h @@ -205,10 +205,6 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -/* Cache configuration */ -#define CFG_DCACHE_SIZE 8192 -#define CFG_CACHELINE_SIZE 32 - /* * Internal Definitions * diff --git a/include/configs/G2000.h b/include/configs/G2000.h index 9c713c6..c12ce48 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -331,16 +331,6 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 8967b3f..18e5b3c 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -363,16 +363,6 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index 1ff7108..a389d58 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -257,16 +257,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/JSE.h b/include/configs/JSE.h index ea3b0b4..5b40ef6 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -279,15 +279,6 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 3644e43..816e63b 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -281,14 +281,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ -#endif /* * Internal Definitions diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 8d7ec59..d61b49e 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -346,14 +346,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ -#endif /* * Internal Definitions diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 5b526a0..9ddf82b 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -258,15 +258,6 @@ */ /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * Logbuffer Configuration */ #undef CONFIG_LOGBUFFER /* supported but not enabled */ diff --git a/include/configs/ML2.h b/include/configs/ML2.h index f488275..66dae21 100644 --- a/include/configs/ML2.h +++ b/include/configs/ML2.h @@ -201,14 +201,6 @@ #define CFG_ENV_ADDR \ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ #endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Init Memory Controller: diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 5840ea2..94b5bc9 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -222,15 +222,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index 937df22..4e03088 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -220,15 +220,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index d6e7082..e70c0d3 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -251,15 +251,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index efa0157..b83520d 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -231,15 +231,6 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 652210c..6b16654 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -300,16 +300,6 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index b29f368..adbe8a9 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -270,16 +270,6 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ #define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 8a74c4f..c2aa2cc 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -454,16 +454,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 14848ab..3a413f5 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -306,16 +306,6 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 5512f4b..ec6f205 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -248,16 +248,6 @@ #define CFG_EEPROM_PAGE_WRITE_ENABLE /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index fc177fb..7017fff 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -290,15 +290,6 @@ */ #define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ -#endif - /* * Init Memory Controller: */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 20d693f..bfb3156 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -293,15 +293,6 @@ */ #define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ -#endif - /* * Init Memory Controller: */ diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 656784a..582d8cf 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -254,16 +254,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 611f5a6..38ea576 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -257,14 +257,6 @@ extern void out32(unsigned int, unsigned long); * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 440GX CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Internal Definitions diff --git a/include/configs/acadia.h b/include/configs/acadia.h index e3f6e2c..dc322dd 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -385,15 +385,6 @@ #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) diff --git a/include/configs/alpr.h b/include/configs/alpr.h index d88c3ad..aff9823 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -355,12 +355,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ /* * Internal Definitions diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 14c5638..d577448 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -414,15 +414,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 7736a1e..eca195a 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -321,14 +321,6 @@ #define CFG_ENV_ADDR \ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ #endif -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Init Memory Controller: diff --git a/include/configs/csb272.h b/include/configs/csb272.h index c43b497..a24478d 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -290,14 +290,6 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET /* - * Cache configuration - * - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 - -/* * Miscellaneous board specific definitions * */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index a7120aa..064650c 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -289,14 +289,6 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET /* - * Cache configuration - * - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 - -/* * Miscellaneous board specific definitions * */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 2c626a0..5faa9eb 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -293,14 +293,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Internal Definitions diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h index 577f459..b43b228 100644 --- a/include/configs/hcu4.h +++ b/include/configs/hcu4.h @@ -321,13 +321,6 @@ #define CONFIG_PORT_ADDR 0xF0000500 -/*----------------------------------------------------------------------- - * Cache Configuration - *----------------------------------------------------------------------*/ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405GPr CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ - /* * Internal Definitions * diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index 9085881..1214bc3 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -364,13 +364,6 @@ #define HCU_CPLD_VERSION_REGISTER ( CFG_CPLD + 0x0F00000 ) #define HCU_HW_VERSION_REGISTER ( CFG_CPLD + 0x1400000 ) -/*----------------------------------------------------------------------- - * Cache Configuration - *----------------------------------------------------------------------*/ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ - /* * Internal Definitions * diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 7908e5a..2eed941 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -62,7 +62,7 @@ #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ -#define CFG_PCIE_MEMSIZE 0x01000000 +#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 @@ -72,6 +72,9 @@ #define CFG_PCIE1_XCFGBASE 0xc3001000 #define CFG_PCIE2_XCFGBASE 0xc3002000 +/* base address of inbound PCIe window */ +#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL + /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE @@ -202,6 +205,7 @@ "upd=run load;run update\0" \ "kozio=bootm ffc60000\0" \ "pciconfighost=1\0" \ + "pcie_mode=RP:RP:RP\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -243,7 +247,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SDRAM - +#define CONFIG_CMD_SNTP #define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */ #define CONFIG_MII 1 /* MII PHY management */ @@ -427,14 +431,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Internal Definitions diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h new file mode 100644 index 0000000..e3f24a44 --- /dev/null +++ b/include/configs/kilauea.h @@ -0,0 +1,525 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * kilauea.h - configuration for AMCC Kilauea (405EX) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_KILAUEA 1 /* Board is Kilauea */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EX 1 /* Specifc 405EX support*/ +#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_EMAC_COUNT + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFC000000 +#define CFG_NAND_ADDR 0xF8000000 +#define CFG_FPGA_BASE 0xF0000000 +#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */ +#define CFG_MONITOR_BASE (TEXT_BASE) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +/* reserve some memory for POST and BOOT limit info */ +#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16) + +/* extra data in init-ram */ +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) +#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8) +#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12) +#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +/* define this if you want console on UART1 */ +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else +#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ +#endif + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/* + * IPL (Initial Program Loader, integrated inside CPU) + * Will load first 4k from NAND (SPL) into cache and execute it from there. + * + * SPL (Secondary Program Loader) + * Will load special U-Boot version (NUB) from NAND and execute it. This SPL + * has to fit into 4kByte. It sets up the CPU and configures the SDRAM + * controller and the NAND controller so that the special U-Boot image can be + * loaded from NAND to SDRAM. + * + * NUB (NAND U-Boot) + * This NAND U-Boot (NUB) is a special U-Boot version which can be started + * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. + * + * On 440EPx the SPL is copied to SDRAM before the NAND controller is + * set up. While still running from cache, I experienced problems accessing + * the NAND controller. sr - 2006-08-25 + */ +#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ +#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ +#define CFG_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */ +#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ +#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) + +/* + * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) + */ +#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ + +/* + * Now the NAND chip has to be defined (no autodetection used!) + */ +#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ +#define CFG_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */ + +#define CFG_NAND_ECCSIZE 256 +#define CFG_NAND_ECCBYTES 3 +#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE) +#define CFG_NAND_OOBSIZE 16 +#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) +#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7} + +#ifdef CFG_ENV_IS_IN_NAND +/* + * For NAND booting the environment is embedded in the U-Boot image. Please take + * look at the file board/amcc/sequoia/u-boot-nand.lds for details. + */ +#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE +#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) +#endif + +/*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM (256) /* 256MB */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ +#define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ + +/* Standard DTT sensor configuration */ +#define CONFIG_DTT_DS1775 1 +#define CONFIG_DTT_SENSORS { 0 } +#define CFG_I2C_DTT_ADDR 0x48 + +/* RTC configuration */ +#define CONFIG_RTC_DS1338 1 +#define CFG_I2C_RTC_ADDR 0x68 + +/*----------------------------------------------------------------------- + * Ethernet + *----------------------------------------------------------------------*/ +#define CONFIG_M88E1111_PHY 1 +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 1 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 2 + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "logversion=2\0" \ + "netdev=eth0\0" \ + "hostname=kilauea\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "net_nfs=tftp 200000 ${bootfile};" \ + "run nfsargs addip addtty;" \ + "bootm 200000\0" \ + "net_nfs_fdt=tftp 200000 ${bootfile};" \ + "tftp ${fdt_addr} ${fdt_file};" \ + "run nfsargs addip addtty;" \ + "bootm 200000 - ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=kilauea/uImage\0" \ + "fdt_file=kilauea/kilauea.dtb\0" \ + "fdt_addr=400000\0" \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc200000\0" \ + "initrd_high=30000000\0" \ + "load=tftp 200000 kilauea/u-boot.bin\0" \ + "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ + "cp.b ${fileaddr} fffa0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load update\0" \ + "nload=tftp 200000 kilauea/u-boot-nand.bin\0" \ + "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \ + "setenv filesize;saveenv\0" \ + "nupd=run nload nupdate\0" \ + "pciconfighost=1\0" \ + "pcie_mode=RP:RP\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_LOG +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP + +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CACHE | \ + CFG_POST_CPU | \ + CFG_POST_ETHER | \ + CFG_POST_I2C | \ + CFG_POST_MEMORY | \ + CFG_POST_UART) + +/* Define here the base-addresses of the UARTs to test in POST */ +#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE} + +#define CONFIG_LOGBUFFER +#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */ + +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE + +/*----------------------------------------------------------------------- + * PCIe stuff + *----------------------------------------------------------------------*/ +#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */ + +#define CFG_PCIE0_CFGBASE 0xa0000000 /* remote access */ +#define CFG_PCIE0_XCFGBASE 0xb0000000 /* local access */ +#define CFG_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */ + +#define CFG_PCIE1_CFGBASE 0xc0000000 /* remote access */ +#define CFG_PCIE1_XCFGBASE 0xd0000000 /* local access */ +#define CFG_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */ + +#define CFG_PCIE0_UTLBASE 0xef502000 +#define CFG_PCIE1_UTLBASE 0xef503000 + +/* base address of inbound PCIe window */ +#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) +/* booting from NAND, so NAND chips select has to be on CS 0 */ +#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ + +/* Memory Bank 1 (NOR-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x05806500 +#define CFG_EBC_PB1CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/ + +/* Memory Bank 0 (NAND-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x018003c0 +#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1e000) +#else +#define CFG_NAND_CS 1 /* NAND chip connected to CSx */ + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x05806500 +#define CFG_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/ + +/* Memory Bank 1 (NAND-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x018003c0 +#define CFG_EBC_PB1CR (CFG_NAND_ADDR | 0x1e000) +#endif + +/* Memory Bank 2 (FPGA) initialization */ +#define CFG_EBC_PB2AP 0x9400C800 +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */ + +#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */ + +/*----------------------------------------------------------------------- + * GPIO Setup + *----------------------------------------------------------------------*/ +#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +{ \ +/* GPIO Core 0 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO28 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \ +} \ +} + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/*----------------------------------------------------------------------- + * Some Kilauea stuff..., mainly fpga registers + */ +#define CFG_FPGA_REG_BASE CFG_FPGA_BASE +#define CFG_FPGA_FIFO_BASE (in32(CFG_FPGA_BASE) | (1 << 11)) + +/* interrupt */ +#define CFG_FPGA_SLIC0_R_DPRAM_INT 0x80000000 +#define CFG_FPGA_SLIC0_W_DPRAM_INT 0x40000000 +#define CFG_FPGA_SLIC1_R_DPRAM_INT 0x20000000 +#define CFG_FPGA_SLIC1_W_DPRAM_INT 0x10000000 +#define CFG_FPGA_PHY0_INT 0x08000000 +#define CFG_FPGA_PHY1_INT 0x04000000 +#define CFG_FPGA_SLIC0_INT 0x02000000 +#define CFG_FPGA_SLIC1_INT 0x01000000 + +/* DPRAM setting */ +/* 00: 32B; 01: 64B; 10: 128B; 11: 256B */ +#define CFG_FPGA_DPRAM_R_INT_LINE 0x00400000 /* 64 B */ +#define CFG_FPGA_DPRAM_W_INT_LINE 0x00100000 /* 64 B */ +#define CFG_FPGA_DPRAM_RW_TYPE 0x00080000 +#define CFG_FPGA_DPRAM_RST 0x00040000 +#define CFG_FPGA_UART0_FO 0x00020000 +#define CFG_FPGA_UART1_FO 0x00010000 + +/* loopback */ +#define CFG_FPGA_CHIPSIDE_LOOPBACK 0x00004000 +#define CFG_FPGA_LINESIDE_LOOPBACK 0x00008000 +#define CFG_FPGA_SLIC0_ENABLE 0x00002000 +#define CFG_FPGA_SLIC1_ENABLE 0x00001000 +#define CFG_FPGA_SLIC0_CS 0x00000800 +#define CFG_FPGA_SLIC1_CS 0x00000400 +#define CFG_FPGA_USER_LED0 0x00000200 +#define CFG_FPGA_USER_LED1 0x00000100 + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_CPU "PowerPC,405EX@0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/luan.h b/include/configs/luan.h index a09dd74..cba7295 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -293,15 +293,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 52deab4..9cb483d 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -414,7 +414,7 @@ /*----------------------------------------------------------------------- * PPC440 GPIO Configuration */ -#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ { \ /* GPIO Core 0 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ @@ -487,15 +487,6 @@ } \ } -/*----------------------------------------------------------------------- - * Cache Configuration - *----------------------------------------------------------------------*/ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/makalu.h b/include/configs/makalu.h new file mode 100644 index 0000000..2871a6c --- /dev/null +++ b/include/configs/makalu.h @@ -0,0 +1,399 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * makalu.h - configuration for AMCC Makalu (405EX) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_MAKALU 1 /* Board is Makalu */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EX 1 /* Specifc 405EX support*/ +#define CONFIG_SYS_CLK_FREQ 33330000 /* ext frequency to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFC000000 +#define CFG_FPGA_BASE 0xF0000000 +#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */ +#define CFG_MONITOR_BASE (TEXT_BASE) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */ +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +/* reserve some memory for POST and BOOT limit info */ +#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16) + +/* extra data in init-ram */ +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4) +#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8) +#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12) +#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* no ext. clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +/* define this if you want console on UART1 */ +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM 256 + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ +#define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ + +/* Standard DTT sensor configuration */ +#define CONFIG_DTT_DS1775 1 +#define CONFIG_DTT_SENSORS { 0 } +#define CFG_I2C_DTT_ADDR 0x48 + +/* RTC configuration */ +#define CONFIG_RTC_X1205 1 +#define CFG_I2C_RTC_ADDR 0x6f + +/*----------------------------------------------------------------------- + * Ethernet + *----------------------------------------------------------------------*/ +#define CONFIG_M88E1111_PHY 1 +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 1 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 0 + +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "logversion=2\0" \ + "netdev=eth0\0" \ + "hostname=makalu\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0" \ + "net_nfs=tftp 200000 ${bootfile};" \ + "run nfsargs addip addtty addmisc;" \ + "bootm 200000\0" \ + "net_nfs_fdt=tftp 200000 ${bootfile};" \ + "tftp ${fdt_addr} ${fdt_file};" \ + "run nfsargs addip addtty addmisc;" \ + "bootm 200000 - ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmisc;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=makalu/uImage\0" \ + "fdt_file=makalu/makalu.dtb\0" \ + "fdt_addr=400000\0" \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc200000\0" \ + "initrd_high=30000000\0" \ + "load=tftp 200000 makalu/u-boot.bin\0" \ + "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ + "cp.b ${fileaddr} fffa0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load update\0" \ + "pciconfighost=1\0" \ + "pcie_mode=RP:RP\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_LOG +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP + +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CACHE | \ + CFG_POST_CPU | \ + CFG_POST_ETHER | \ + CFG_POST_I2C | \ + CFG_POST_MEMORY | \ + CFG_POST_UART) + +/* Define here the base-addresses of the UARTs to test in POST */ +#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE} + +#define CONFIG_LOGBUFFER +#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */ + +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE + +/*----------------------------------------------------------------------- + * PCIe stuff + *----------------------------------------------------------------------*/ +#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */ + +#define CFG_PCIE0_CFGBASE 0xa0000000 /* remote access */ +#define CFG_PCIE0_XCFGBASE 0xb0000000 /* local access */ +#define CFG_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */ + +#define CFG_PCIE1_CFGBASE 0xc0000000 /* remote access */ +#define CFG_PCIE1_XCFGBASE 0xd0000000 /* local access */ +#define CFG_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */ + +#define CFG_PCIE0_UTLBASE 0xef502000 +#define CFG_PCIE1_UTLBASE 0xef503000 + +/* base address of inbound PCIe window */ +#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x08033700 +#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000) + +/* Memory Bank 2 (CPLD) initialization */ +#define CFG_EBC_PB2AP 0x9400C800 +#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */ + +#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */ + +/*----------------------------------------------------------------------- + * GPIO Setup + *----------------------------------------------------------------------*/ +#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +{ \ +/* GPIO Core 0 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20) USB2_DATA(4) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21) USB2_DATA(5) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22) USB2_DATA(6) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23) USB2_DATA(7) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1) IRQ(7) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2) IRQ(8) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3) IRQ(9) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16) USB2_DATA(0) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17) USB2_DATA(1) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18) USB2_DATA(2) */ \ +{GPIO0_BASE, GPIO_BI, GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19) USB2_DATA(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD UART1_CTS */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR UART1_RTS */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO20 UART0_DTR UART1_TX */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO21 UART0_RI UART1_RX */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ DMA_ACK2 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK DMA_REQ2 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ DMA_EOT2 IRQ(4) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK DMA_ACK3 IRQ(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5) DMA_EOT0 TS(3) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ DMA_EOT3 IRQ(5) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO29 DMA_EOT1 IRQ(2) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO30 DMA_REQ1 IRQ(1) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0}, /* GPIO31 DMA_ACK1 IRQ(0) */ \ +} \ +} + +#define CFG_GPIO_PCIE_RST 23 +#define CFG_GPIO_PCIE_CLKREQ 27 +#define CFG_GPIO_PCIE_WAKE 28 + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_CPU "PowerPC,405EX@0" + +#endif /* __CONFIG_H */ diff --git a/include/configs/ml300.h b/include/configs/ml300.h index 0183041..1945918 100644 --- a/include/configs/ml300.h +++ b/include/configs/ml300.h @@ -160,12 +160,6 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ - -/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index bc2fd33..fd4d3af 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -317,14 +317,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Internal Definitions diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 51f19a1..255e072 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -311,14 +311,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Internal Definitions diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 7653ba1..d66f4bd 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -365,7 +365,7 @@ /*----------------------------------------------------------------------- * PPC440 GPIO Configuration */ -#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ { \ /* GPIO Core 0 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ @@ -438,15 +438,6 @@ } \ } -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index dc906b1..60d401f 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -234,16 +234,6 @@ #define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ #define FLASH0_BA CFG_FLASH_BASE /* FLASH 0 Base Address */ diff --git a/include/configs/sc3.h b/include/configs/sc3.h index cb22536..0a03c0e 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -433,24 +433,6 @@ extern unsigned long offsetOfEnvironment; #define CONFIG_JFFS2_PART_SIZE 0x01000000 #define CONFIG_JFFS2_PART_OFFSET 0x00000000 -/*----------------------------------------------------------------------- - * Cache Configuration - * - * CFG_DCACHE_SIZE -> size of data cache: - * - 405GP 8k - * - 405GPr 16k - * How to handle the difference in chache size? - * CFG_CACHELINE_SIZE -> size of one cache line: 32 bytes - * (used in cpu/ppc4xx/start.S) -*/ -#define CFG_DCACHE_SIZE 16384 - -#define CFG_CACHELINE_SIZE 32 - -#if defined(CONFIG_CMD_KGDB) - #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: * diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 600f98c..2af675a 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -43,6 +43,14 @@ #define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \ 33333333 : 33000000) +#if 0 +/* + * 44x dcache supported is working now on sequoia, but we don't enable + * it yet since it needs further testing + */ +#define CONFIG_4xx_DCACHE /* enable dcache */ +#endif + #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ @@ -293,8 +301,15 @@ /* USB */ #ifdef CONFIG_440EPX -#define CONFIG_USB_OHCI +#define CONFIG_USB_OHCI_NEW #define CONFIG_USB_STORAGE +#define CFG_OHCI_BE_CONTROLLER + +#undef CFG_USB_OHCI_BOARD_INIT +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST +#define CFG_USB_OHCI_SLOT_NAME "ppc440" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 /* Comment this out to enable USB 1.1 device */ #define USB_2_0_DEVICE @@ -460,15 +475,6 @@ #define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS) #define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ -/*----------------------------------------------------------------------- - * Cache Configuration - *----------------------------------------------------------------------*/ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/taihu.h b/include/configs/taihu.h index d623e56..d012c60 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -80,6 +80,7 @@ "bootfile=/tftpboot/taihu/uImage\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \ "netdev=eth0\0" \ + "hostname=taihu\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -210,10 +211,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ +#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ /*----------------------------------------------------------------------- * I2C stuff @@ -244,6 +247,7 @@ unsigned char spi_read(void); /* standard dtt sensor configuration */ #define CONFIG_DTT_DS1775 1 #define CONFIG_DTT_SENSORS { 0 } +#define CFG_I2C_DTT_ADDR 0x49 /*----------------------------------------------------------------------- * PCI stuff @@ -327,7 +331,7 @@ unsigned char spi_read(void); /*----------------------------------------------------------------------- * PPC405 GPIO Configuration */ -#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 */ \ +#define CFG_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \ { \ /* GPIO Core 0 */ \ { GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \ @@ -365,13 +369,6 @@ unsigned char spi_read(void); } \ } -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */ -#define CFG_CACHELINE_SIZE 32 -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ - /* * Init Memory Controller: * @@ -421,43 +418,6 @@ unsigned char spi_read(void); #define CFG_EBC_PB4AP 0x158FF600 #define CFG_EBC_PB4CR 0x5021A000 -/*----------------------------------------------------------------------- - * Definitions for GPIO setup (PPC405EP specific) - * - * GPIO0[0] - External Bus Controller BLAST output - * GPIO0[1-9] - Instruction trace outputs - * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs - * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs - * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs - * GPIO0[24-27] - UART0 control signal inputs/outputs - * GPIO0[28-29] - UART1 data signal input/output - * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs - */ -#define CFG_GPIO0_OSRH 0x15555550 /* output select high/low */ -#define CFG_GPIO0_OSRL 0x00000110 -#define CFG_GPIO0_ISR1H 0x00000001 /* input select high/low */ -#define CFG_GPIO0_ISR1L 0x15545440 -#define CFG_GPIO0_TSRH 0x00000000 /* three-state select high/low */ -#define CFG_GPIO0_TSRL 0x00000000 -#define CFG_GPIO0_TCR 0xFFFE8117 /* three-state control */ -#define CFG_GPIO0_ODR 0x00000000 /* open drain */ - -#define GPIO0 0 /* GPIO controller 0 */ - -/* the GPIO macros in include/ppc405.h for High/Low registers are backwards */ - -#define GPIOx_OSL (GPIO0_OSRH-GPIO_BASE) -#define GPIOx_TSL (GPIO0_TSRH-GPIO_BASE) -#define GPIOx_IS1L (GPIO0_ISR1H-GPIO_BASE) -#define GPIOx_IS2L (GPIO0_ISR1H-GPIO_BASE) -#define GPIOx_IS3L (GPIO0_ISR1H-GPIO_BASE) - -#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO output select */ -#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO three-state select */ -#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO input select */ -#define GPIO_IS2(x) (x+GPIOx_IS1L) -#define GPIO_IS3(x) (x+GPIOx_IS1L) - #define CPLD_REG0_ADDR 0x50100000 #define CPLD_REG1_ADDR 0x50100001 /* diff --git a/include/configs/taishan.h b/include/configs/taishan.h index baa4fbd..ab3b0c1 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -319,15 +319,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- - * Cache Configuration - *----------------------------------------------------------------------*/ -#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/walnut.h b/include/configs/walnut.h index 180549e..19b29e7 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -290,16 +290,6 @@ #endif /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 35bce4a..a8eeff9 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -160,6 +160,14 @@ #define CFG_ENV_OFFSET 0x0 #endif /* CFG_ENV_IS_IN_EEPROM */ +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_AD7414 1 /* use AD7414 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo" @@ -273,6 +281,7 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DHCP #define CONFIG_CMD_DIAG +#define CONFIG_CMD_DTT #define CONFIG_CMD_ELF #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C @@ -361,15 +370,6 @@ #define CFG_BCSR5_PCI66EN 0x80 -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Internal Definitions * diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 74033b4..db1d35b 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -64,7 +64,7 @@ #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ -#define CFG_PCIE_MEMSIZE 0x01000000 +#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 @@ -74,6 +74,9 @@ #define CFG_PCIE1_XCFGBASE 0xc3001000 #define CFG_PCIE2_XCFGBASE 0xc3002000 +/* base address of inbound PCIe window */ +#define CFG_PCIE_INBOUND_BASE 0x0000000400000000ULL + /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE @@ -183,6 +186,7 @@ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ "pciconfighost=1\0" \ + "pcie_mode=RP:EP:EP\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -320,14 +324,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Internal Definitions diff --git a/include/configs/zeus.h b/include/configs/zeus.h index 605755a..810a528 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -237,13 +237,6 @@ #endif /*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405EP CPU */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ - -/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) */ /* use on chip memory (OCM) for temperary stack until sdram is tested */ diff --git a/include/ppc405.h b/include/ppc405.h index 0c7bf3e..b5ad38f 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -22,6 +22,12 @@ #ifndef __PPC405_H__ #define __PPC405_H__ +#ifndef CONFIG_IOP480 +#define CFG_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ +#else +#define CFG_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */ +#endif + /*--------------------------------------------------------------------- */ /* Special Purpose Registers */ /*--------------------------------------------------------------------- */ @@ -123,6 +129,40 @@ #define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */ #define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */ +#if defined(CONFIG_405EX) +#define uic0sr uicsr /* UIC status */ +#define uic0srs uicsrs /* UIC status set */ +#define uic0er uicer /* UIC enable */ +#define uic0cr uiccr /* UIC critical */ +#define uic0pr uicpr /* UIC polarity */ +#define uic0tr uictr /* UIC triggering */ +#define uic0msr uicmsr /* UIC masked status */ +#define uic0vr uicvr /* UIC vector */ +#define uic0vcr uicvcr /* UIC vector configuration*/ + +#define UIC_DCR_BASE1 0xd0 +#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */ +#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */ +#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */ +#define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */ +#define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */ +#define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */ +#define uic1msr (UIC_DCR_BASE1+0x6) /* UIC masked status */ +#define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */ +#define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/ + +#define UIC_DCR_BASE2 0xe0 +#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */ +#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */ +#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */ +#define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */ +#define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */ +#define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */ +#define uic2msr (UIC_DCR_BASE2+0x6) /* UIC masked status */ +#define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */ +#define uic2vcr (UIC_DCR_BASE2+0x8) /* UIC vector configuration*/ +#endif + /*-----------------------------------------------------------------------------+ | Universal interrupt controller interrupts +-----------------------------------------------------------------------------*/ @@ -166,6 +206,116 @@ #define UIC_EXT3 0x00000002 /* External interrupt 3 */ #define UIC_EXT4 0x00000001 /* External interrupt 4 */ +#elif defined(CONFIG_405EX) + +/* UIC 0 */ +#define UIC_U0 0x80000000 /* */ +#define UIC_U1 0x40000000 /* */ +#define UIC_IIC0 0x20000000 /* */ +#define UIC_PKA 0x10000000 /* */ +#define UIC_TRNG 0x08000000 /* */ +#define UIC_EBM 0x04000000 /* */ +#define UIC_BGI 0x02000000 /* */ +#define UIC_IIC1 0x01000000 /* */ +#define UIC_SPI 0x00800000 /* */ +#define UIC_EIRQ0 0x00400000 /**/ +#define UIC_MTE 0x00200000 /*MAL Tx EOB */ +#define UIC_MRE 0x00100000 /*MAL Rx EOB */ +#define UIC_DMA0 0x00080000 /* */ +#define UIC_DMA1 0x00040000 /* */ +#define UIC_DMA2 0x00020000 /* */ +#define UIC_DMA3 0x00010000 /* */ +#define UIC_PCIE0AL 0x00008000 /* */ +#define UIC_PCIE0VPD 0x00004000 /* */ +#define UIC_RPCIE0HRST 0x00002000 /* */ +#define UIC_FPCIE0HRST 0x00001000 /* */ +#define UIC_PCIE0TCR 0x00000800 /* */ +#define UIC_PCIEMSI0 0x00000400 /* */ +#define UIC_PCIEMSI1 0x00000200 /* */ +#define UIC_SECURITY 0x00000100 /* */ +#define UIC_ENET 0x00000080 /* */ +#define UIC_ENET1 0x00000040 /* */ +#define UIC_PCIEMSI2 0x00000020 /* */ +#define UIC_EIRQ4 0x00000010 /**/ +#define UIC_UIC2NC 0x00000008 /* */ +#define UIC_UIC2C 0x00000004 /* */ +#define UIC_UIC1NC 0x00000002 /* */ +#define UIC_UIC1C 0x00000001 /* */ + +#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */ +#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */ +/* UIC 1 */ +#define UIC_MS 0x80000000 /* MAL SERR */ +#define UIC_MTDE 0x40000000 /* MAL TXDE */ +#define UIC_MRDE 0x20000000 /* MAL RXDE */ +#define UIC_PCIE0BMVC0 0x10000000 /* */ +#define UIC_PCIE0DCRERR 0x08000000 /* */ +#define UIC_EBC 0x04000000 /* */ +#define UIC_NDFC 0x02000000 /* */ +#define UIC_PCEI1DCRERR 0x01000000 /* */ +#define UIC_GPTCMPT8 0x00800000 /* */ +#define UIC_GPTCMPT9 0x00400000 /* */ +#define UIC_PCIE1AL 0x00200000 /* */ +#define UIC_PCIE1VPD 0x00100000 /* */ +#define UIC_RPCE1HRST 0x00080000 /* */ +#define UIC_FPCE1HRST 0x00040000 /* */ +#define UIC_PCIE1TCR 0x00020000 /* */ +#define UIC_PCIE1VC0 0x00010000 /* */ +#define UIC_GPTCMPT3 0x00008000 /* */ +#define UIC_GPTCMPT4 0x00004000 /* */ +#define UIC_EIRQ7 0x00002000 /* */ +#define UIC_EIRQ8 0x00001000 /* */ +#define UIC_EIRQ9 0x00000800 /* */ +#define UIC_GPTCMP5 0x00000400 /* */ +#define UIC_GPTCMP6 0x00000200 /* */ +#define UIC_GPTCMP7 0x00000100 /* */ +#define UIC_SROM 0x00000080 /* SERIAL ROM*/ +#define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/ +#define UIC_EIRQ2 0x00000020 /* */ +#define UIC_EIRQ5 0x00000010 /* */ +#define UIC_EIRQ6 0x00000008 /* */ +#define UIC_EMAC0WAKE 0x00000004 /* */ +#define UIC_EIRQ1 0x00000002 /* */ +#define UIC_EMAC1WAKE 0x00000001 /* */ +#define UIC_MAL_SERR UIC_MS /* MAL SERR */ +#define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */ +#define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */ +/* UIC 2 */ +#define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/ +#define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/ +#define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/ +#define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/ +#define UIC_EIRQ3 0x08000000 /* External IRQ 3*/ +#define UIC_DDRMCUE 0x04000000 /* */ +#define UIC_DDRMCCE 0x02000000 /* */ +#define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/ +#define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/ +#define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/ +#define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/ +#define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/ +#define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/ +#define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/ +#define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/ +#define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/ +#define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/ +#define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/ +#define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/ +#define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/ +#define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/ +#define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/ +#define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/ +#define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/ +#define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/ +#define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/ +#define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/ +#define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/ +#define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/ +#define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/ +#define UIC_USBWAKE 0x00000002 /* USB wakup*/ +#define UIC_USBOTG 0x00000001 /* USB OTG*/ +#define UIC_ETH0 UIC_ENET +#define UIC_ETH1 UIC_ENET1 + #else /* !defined(CONFIG_405EZ) */ #define UIC_UART0 0x80000000 /* UART 0 */ @@ -200,9 +350,6 @@ /****************************************************************************** * SDRAM Controller ******************************************************************************/ -#define SDRAM_DCR_BASE 0x10 -#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ -#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ /* values for memcfga register - indirect addressing of these regs */ #ifndef CONFIG_405EP #define mem_besra 0x00 /* bus error syndrome reg a */ @@ -256,7 +403,11 @@ /****************************************************************************** * Power Management ******************************************************************************/ +#ifdef CONFIG_405EX +#define POWERMAN_DCR_BASE 0xb0 +#else #define POWERMAN_DCR_BASE 0xb8 +#endif #define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ #define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ #define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ @@ -264,9 +415,6 @@ /****************************************************************************** * Extrnal Bus Controller ******************************************************************************/ -#define EBC_DCR_BASE 0x12 -#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ -#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */ /* values for ebccfga register - indirect addressing of these regs */ #define pb0cr 0x00 /* periph bank 0 config reg */ #define pb1cr 0x01 /* periph bank 1 config reg */ @@ -561,16 +709,6 @@ #define VCO_MIN 500 #define VCO_MAX 1000 #elif defined(CONFIG_405EZ) -/****************************************************************************** - * SDR Registers - ******************************************************************************/ -#define SDR_DCR_BASE 0x0E -#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */ -#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */ - -#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) -#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) - #define sdrnand0 0x4000 #define sdrultra0 0x4040 #define sdrultra1 0x4050 @@ -604,10 +742,6 @@ /****************************************************************************** * Control ******************************************************************************/ -#define CNTRL_DCR_BASE 0x0C -#define cprcfga (CNTRL_DCR_BASE+0x0) /* CPR addr reg */ -#define cprcfgd (CNTRL_DCR_BASE+0x1) /* CPR data reg */ - /* CPR Registers */ #define cprclkupd 0x020 /* CPR_CLKUPD */ #define cprpllc 0x040 /* CPR_PLLC */ @@ -619,12 +753,6 @@ #define cprmisc0 0x181 /* CPR_MISC0 */ #define cprmisc1 0x182 /* CPR_MISC1 */ -/* - * Macro for accessing the indirect CPR register - */ -#define mtcpr(reg, data) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,data); } while (0) -#define mfcpr(reg, data) do { mtdcr(cprcfga,reg);data = mfdcr(cprcfgd); } while (0) - #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ @@ -645,252 +773,6 @@ #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ -#if 0 /* Deprecated */ -#define CNTRL_DCR_BASE 0x0f0 -#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ -#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ -#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ -#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ -#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ -#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ - -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ -#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ - -/* Bit definitions */ -#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ -#define PLLMR0_CPU_DIV_BYPASS 0x00000000 -#define PLLMR0_CPU_DIV_2 0x00100000 -#define PLLMR0_CPU_DIV_3 0x00200000 -#define PLLMR0_CPU_DIV_4 0x00300000 - -#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ -#define PLLMR0_CPU_PLB_DIV_1 0x00000000 -#define PLLMR0_CPU_PLB_DIV_2 0x00010000 -#define PLLMR0_CPU_PLB_DIV_3 0x00020000 -#define PLLMR0_CPU_PLB_DIV_4 0x00030000 - -#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ -#define PLLMR0_OPB_PLB_DIV_1 0x00000000 -#define PLLMR0_OPB_PLB_DIV_2 0x00001000 -#define PLLMR0_OPB_PLB_DIV_3 0x00002000 -#define PLLMR0_OPB_PLB_DIV_4 0x00003000 - -#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ -#define PLLMR0_EXB_PLB_DIV_2 0x00000000 -#define PLLMR0_EXB_PLB_DIV_3 0x00000100 -#define PLLMR0_EXB_PLB_DIV_4 0x00000200 -#define PLLMR0_EXB_PLB_DIV_5 0x00000300 - -#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ -#define PLLMR0_MAL_PLB_DIV_1 0x00000000 -#define PLLMR0_MAL_PLB_DIV_2 0x00000010 -#define PLLMR0_MAL_PLB_DIV_3 0x00000020 -#define PLLMR0_MAL_PLB_DIV_4 0x00000030 - -#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ -#define PLLMR0_PCI_PLB_DIV_1 0x00000000 -#define PLLMR0_PCI_PLB_DIV_2 0x00000001 -#define PLLMR0_PCI_PLB_DIV_3 0x00000002 -#define PLLMR0_PCI_PLB_DIV_4 0x00000003 - -#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ -#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ -#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ -#define PLLMR1_FBMUL_DIV_16 0x00000000 -#define PLLMR1_FBMUL_DIV_1 0x00100000 -#define PLLMR1_FBMUL_DIV_2 0x00200000 -#define PLLMR1_FBMUL_DIV_3 0x00300000 -#define PLLMR1_FBMUL_DIV_4 0x00400000 -#define PLLMR1_FBMUL_DIV_5 0x00500000 -#define PLLMR1_FBMUL_DIV_6 0x00600000 -#define PLLMR1_FBMUL_DIV_7 0x00700000 -#define PLLMR1_FBMUL_DIV_8 0x00800000 -#define PLLMR1_FBMUL_DIV_9 0x00900000 -#define PLLMR1_FBMUL_DIV_10 0x00A00000 -#define PLLMR1_FBMUL_DIV_11 0x00B00000 -#define PLLMR1_FBMUL_DIV_12 0x00C00000 -#define PLLMR1_FBMUL_DIV_13 0x00D00000 -#define PLLMR1_FBMUL_DIV_14 0x00E00000 -#define PLLMR1_FBMUL_DIV_15 0x00F00000 - -#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ -#define PLLMR1_FWDVA_DIV_8 0x00000000 -#define PLLMR1_FWDVA_DIV_7 0x00010000 -#define PLLMR1_FWDVA_DIV_6 0x00020000 -#define PLLMR1_FWDVA_DIV_5 0x00030000 -#define PLLMR1_FWDVA_DIV_4 0x00040000 -#define PLLMR1_FWDVA_DIV_3 0x00050000 -#define PLLMR1_FWDVA_DIV_2 0x00060000 -#define PLLMR1_FWDVA_DIV_1 0x00070000 -#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ -#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ - -/* Defines for CPC0_EPRCSR register */ -#define CPC0_EPRCSR_E0NFE 0x80000000 -#define CPC0_EPRCSR_E1NFE 0x40000000 -#define CPC0_EPRCSR_E1RPP 0x00000080 -#define CPC0_EPRCSR_E0RPP 0x00000040 -#define CPC0_EPRCSR_E1ERP 0x00000020 -#define CPC0_EPRCSR_E0ERP 0x00000010 -#define CPC0_EPRCSR_E1PCI 0x00000002 -#define CPC0_EPRCSR_E0PCI 0x00000001 - -/* Defines for CPC0_BOOR Register */ -#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ - -/* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 - /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 - /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 - /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 - /* PLL tune bits */ -#define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ - -/* Defines for CPC0_PLLMR0 Register fields */ - /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 - /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 - /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 - /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 - /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 - /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 - -/* - *------------------------------------------------------------------------------- - * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, - * assuming a 33.3MHz input clock to the 405EP. - *------------------------------------------------------------------------------- - */ -#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -/* - * PLL Voltage Controlled Oscillator (VCO) definitions - * Maximum and minimum values (in MHz) for correct PLL operation. - */ -#define VCO_MIN 500 -#define VCO_MAX 1000 -#endif /* #if 0 */ #else /* #ifdef CONFIG_405EP */ /****************************************************************************** * Control @@ -1214,6 +1096,25 @@ #define GPIO1_ISR3L (GPIO1_BASE+0x40) #define GPIO1_ISR3H (GPIO1_BASE+0x44) +#elif defined(CONFIG_405EX) +#define GPIO_BASE 0xEF600800 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) + #else /* !405EZ */ #define GPIO_BASE 0xEF600700 @@ -1234,39 +1135,458 @@ #endif /* CONFIG_405EZ */ -/* - * Macro for accessing the indirect EBC register - */ -#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data) -#define mfebc(reg, data) mtdcr(ebccfga,reg);data = mfdcr(ebccfgd) - -#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0) -#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0) - -#ifndef __ASSEMBLY__ - -typedef struct -{ - unsigned long pllFwdDiv; - unsigned long pllFwdDivB; - unsigned long pllFbkDiv; - unsigned long pllPlbDiv; - unsigned long pllPciDiv; - unsigned long pllExtBusDiv; - unsigned long pllOpbDiv; - unsigned long freqVCOMhz; /* in MHz */ - unsigned long freqProcessor; - unsigned long freqPLB; - unsigned long freqPCI; - unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ - unsigned long pciClkSync; /* PCI clock is synchronous */ - unsigned long freqVCOHz; -} PPC405_SYS_INFO; - -#endif /* _ASMLANGUAGE */ - -#define RESET_VECTOR 0xfffffffc -#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache - line aligned data. */ +#define GPIO0_BASE GPIO_BASE + +#if defined(CONFIG_405EX) +#define SDR0_SRST 0x0200 + +#define SDRAM_BESR0 0x00 +#define SDRAM_BEARL 0x02 +#define SDRAM_BEARU 0x03 +#define SDRAM_WMIRQ 0x06 /**/ +#define SDRAM_PLBOPT 0x08 /**/ +#define SDRAM_PUABA 0x09 /**/ +#define SDRAM_MCSTAT 0x1F /* memory controller status */ +#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ +#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */ +#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */ +#define SDRAM_MODT1 0x23 /* on die termination for bank 1 */ +#define SDRAM_MODT2 0x24 /* on die termination for bank 2 */ +#define SDRAM_MODT3 0x25 /* on die termination for bank 3 */ +#define SDRAM_CODT 0x26 /* on die termination for controller */ +#define SDRAM_VVPR 0x27 /* variable VRef programmming */ +#define SDRAM_OPARS 0x28 /* on chip driver control setup */ +#define SDRAM_OPART 0x29 /* on chip driver control trigger */ +#define SDRAM_RTR 0x30 /* refresh timer */ +#define SDRAM_PMIT 0x34 /* power management idle timer */ +#define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */ +#define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */ +#define SDRAM_MB2CF 0x48 /* memory bank 2 configuration */ +#define SDRAM_MB3CF 0x4C /* memory bank 3 configuration */ +#define SDRAM_INITPLR0 0x50 /* manual initialization control */ +#define SDRAM_INITPLR1 0x51 /* manual initialization control */ +#define SDRAM_INITPLR2 0x52 /* manual initialization control */ +#define SDRAM_INITPLR3 0x53 /* manual initialization control */ +#define SDRAM_INITPLR4 0x54 /* manual initialization control */ +#define SDRAM_INITPLR5 0x55 /* manual initialization control */ +#define SDRAM_INITPLR6 0x56 /* manual initialization control */ +#define SDRAM_INITPLR7 0x57 /* manual initialization control */ +#define SDRAM_INITPLR8 0x58 /* manual initialization control */ +#define SDRAM_INITPLR9 0x59 /* manual initialization control */ +#define SDRAM_INITPLR10 0x5a /* manual initialization control */ +#define SDRAM_INITPLR11 0x5b /* manual initialization control */ +#define SDRAM_INITPLR12 0x5c /* manual initialization control */ +#define SDRAM_INITPLR13 0x5d /* manual initialization control */ +#define SDRAM_INITPLR14 0x5e /* manual initialization control */ +#define SDRAM_INITPLR15 0x5f /* manual initialization control */ +#define SDRAM_RQDC 0x70 /* read DQS delay control */ +#define SDRAM_RFDC 0x74 /* read feedback delay control */ +#define SDRAM_RDCC 0x78 /* read data capture control */ +#define SDRAM_DLCR 0x7A /* delay line calibration */ +#define SDRAM_CLKTR 0x80 /* DDR clock timing */ +#define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */ +#define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */ +#define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */ +#define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ +#define SDRAM_MMODE 0x88 /* memory mode */ +#define SDRAM_MEMODE 0x89 /* memory extended mode */ +#define SDRAM_ECCCR 0x98 /* ECC error status */ +#define SDRAM_RID 0xF8 /* revision ID */ + +/*-----------------------------------------------------------------------------+ +| Memory Bank 0-7 configuration ++-----------------------------------------------------------------------------*/ +#define SDRAM_RXBAS_SDSZ_4 0x00000000 /* 4M */ +#define SDRAM_RXBAS_SDSZ_8 0x00001000 /* 8M */ +#define SDRAM_RXBAS_SDSZ_16 0x00002000 /* 16M */ +#define SDRAM_RXBAS_SDSZ_32 0x00003000 /* 32M */ +#define SDRAM_RXBAS_SDSZ_64 0x00004000 /* 64M */ +#define SDRAM_RXBAS_SDSZ_128 0x00005000 /* 128M */ +#define SDRAM_RXBAS_SDSZ_256 0x00006000 /* 256M */ +#define SDRAM_RXBAS_SDSZ_512 0x00007000 /* 512M */ +#define SDRAM_RXBAS_SDSZ_1024 0x00008000 /* 1024M */ +#define SDRAM_RXBAS_SDSZ_2048 0x00009000 /* 2048M */ +#define SDRAM_RXBAS_SDSZ_4096 0x0000a000 /* 4096M */ +#define SDRAM_RXBAS_SDSZ_8192 0x0000b000 /* 8192M */ + +/*-----------------------------------------------------------------------------+ +| Memory Controller Status ++-----------------------------------------------------------------------------*/ +#define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */ +#define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */ +#define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */ +#define SDRAM_MCSTAT_SRMS_MASK 0x80000000 /* Mem self refresh stat mask */ +#define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */ +#define SDRAM_MCSTAT_SRMS_SF 0x80000000 /* Mem in self refresh */ + +/*-----------------------------------------------------------------------------+ +| Memory Controller Options 1 ++-----------------------------------------------------------------------------*/ +#define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask */ +#define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */ +#define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */ +#define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */ +#define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/ +#define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3) +#define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */ +#define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */ +#define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */ +#define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */ +#define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */ +#define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */ +#define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */ +#define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */ +#define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */ +#define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */ +#define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */ +#define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */ +#define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */ +#define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */ +#define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */ +#define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */ +#define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */ +#define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */ +#define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */ +#define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */ +#define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */ +#define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */ +#define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */ +#define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */ +#define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */ +#define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */ +#define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */ +#define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */ +#define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */ + +/*-----------------------------------------------------------------------------+ +| Memory Controller Options 2 ++-----------------------------------------------------------------------------*/ +#define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */ +#define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */ +#define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */ +#define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */ +#define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */ +#define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */ +#define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */ +#define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */ +#define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */ +#define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */ +#define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */ +#define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */ +#define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */ +#define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/ +#define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */ +#define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */ + +/*-----------------------------------------------------------------------------+ +| SDRAM Refresh Timer Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RTR_RINT_MASK 0xFFF80000 +#define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16) +#define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8) + +/*-----------------------------------------------------------------------------+ +| SDRAM Read DQS Delay Control Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RQDC_RQDE_MASK 0x80000000 +#define SDRAM_RQDC_RQDE_DISABLE 0x00000000 +#define SDRAM_RQDC_RQDE_ENABLE 0x80000000 +#define SDRAM_RQDC_RQFD_MASK 0x000001FF +#define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) + +#define SDRAM_RQDC_RQFD_MAX 0xFF + +/*-----------------------------------------------------------------------------+ +| SDRAM Read Data Capture Control Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RDCC_RDSS_MASK 0xC0000000 +#define SDRAM_RDCC_RDSS_T1 0x00000000 +#define SDRAM_RDCC_RDSS_T2 0x40000000 +#define SDRAM_RDCC_RDSS_T3 0x80000000 +#define SDRAM_RDCC_RDSS_T4 0xC0000000 +#define SDRAM_RDCC_RSAE_MASK 0x00000001 +#define SDRAM_RDCC_RSAE_DISABLE 0x00000001 +#define SDRAM_RDCC_RSAE_ENABLE 0x00000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM Read Feedback Delay Control Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_RFDC_ARSE_MASK 0x80000000 +#define SDRAM_RFDC_ARSE_DISABLE 0x80000000 +#define SDRAM_RFDC_ARSE_ENABLE 0x00000000 +#define SDRAM_RFDC_RFOS_MASK 0x007F0000 +#define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define SDRAM_RFDC_RFFD_MASK 0x000003FF +#define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) + +#define SDRAM_RFDC_RFFD_MAX 0x4FF + +/*-----------------------------------------------------------------------------+ +| SDRAM Delay Line Calibration Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_DLCR_DCLM_MASK 0x80000000 +#define SDRAM_DLCR_DCLM_MANUEL 0x80000000 +#define SDRAM_DLCR_DCLM_AUTO 0x00000000 +#define SDRAM_DLCR_DLCR_MASK 0x08000000 +#define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000 +#define SDRAM_DLCR_DLCR_IDLE 0x00000000 +#define SDRAM_DLCR_DLCS_MASK 0x07000000 +#define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000 +#define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000 +#define SDRAM_DLCR_DLCS_COMPLETE 0x02000000 +#define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000 +#define SDRAM_DLCR_DLCS_ERROR 0x04000000 +#define SDRAM_DLCR_DLCV_MASK 0x000001FF +#define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0) +#define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF) + +/*-----------------------------------------------------------------------------+ +| SDRAM Controller On Die Termination Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_CODT_ODT_ON 0x80000000 +#define SDRAM_CODT_ODT_OFF 0x00000000 +#define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020 +#define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000 +#define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020 +#define SDRAM_CODT_DQS_MASK 0x00000010 +#define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000 +#define SDRAM_CODT_DQS_SINGLE_END 0x00000010 +#define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000 +#define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 +#define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 +#define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 +#define SDRAM_CODT_IO_HIZ 0x00000000 +#define SDRAM_CODT_IO_NMODE 0x00000001 + +/*-----------------------------------------------------------------------------+ +| SDRAM Mode Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_MMODE_WR_MASK 0x00000E00 +#define SDRAM_MMODE_WR_DDR1 0x00000000 +#define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400 +#define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600 +#define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800 +#define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00 +#define SDRAM_MMODE_DCL_MASK 0x00000070 +#define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020 +#define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060 +#define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030 +#define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020 +#define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030 +#define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040 +#define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050 +#define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060 +#define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070 + +/*-----------------------------------------------------------------------------+ +| SDRAM Extended Mode Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_MEMODE_DIC_MASK 0x00000002 +#define SDRAM_MEMODE_DIC_NORMAL 0x00000000 +#define SDRAM_MEMODE_DIC_WEAK 0x00000002 +#define SDRAM_MEMODE_DLL_MASK 0x00000001 +#define SDRAM_MEMODE_DLL_DISABLE 0x00000001 +#define SDRAM_MEMODE_DLL_ENABLE 0x00000000 +#define SDRAM_MEMODE_RTT_MASK 0x00000044 +#define SDRAM_MEMODE_RTT_DISABLED 0x00000000 +#define SDRAM_MEMODE_RTT_75OHM 0x00000004 +#define SDRAM_MEMODE_RTT_150OHM 0x00000040 +#define SDRAM_MEMODE_DQS_MASK 0x00000400 +#define SDRAM_MEMODE_DQS_DISABLE 0x00000400 +#define SDRAM_MEMODE_DQS_ENABLE 0x00000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM Clock Timing Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_CLKTR_CLKP_MASK 0xC0000000 +#define SDRAM_CLKTR_CLKP_0_DEG 0x00000000 +#define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM Write Timing Register ++-----------------------------------------------------------------------------*/ +#define SDRAM_WRDTR_WDTP_1_CYC 0x80000000 +#define SDRAM_WRDTR_LLWP_MASK 0x10000000 +#define SDRAM_WRDTR_LLWP_DIS 0x10000000 +#define SDRAM_WRDTR_LLWP_1_CYC 0x00000000 +#define SDRAM_WRDTR_WTR_MASK 0x0E000000 +#define SDRAM_WRDTR_WTR_0_DEG 0x06000000 +#define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000 +#define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000 + +/*-----------------------------------------------------------------------------+ +| SDRAM SDTR1 Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_SDTR1_LDOF_MASK 0x80000000 +#define SDRAM_SDTR1_LDOF_1_CLK 0x00000000 +#define SDRAM_SDTR1_LDOF_2_CLK 0x80000000 +#define SDRAM_SDTR1_RTW_MASK 0x00F00000 +#define SDRAM_SDTR1_RTW_2_CLK 0x00200000 +#define SDRAM_SDTR1_RTW_3_CLK 0x00300000 +#define SDRAM_SDTR1_WTWO_MASK 0x000F0000 +#define SDRAM_SDTR1_WTWO_0_CLK 0x00000000 +#define SDRAM_SDTR1_WTWO_1_CLK 0x00010000 +#define SDRAM_SDTR1_RTRO_MASK 0x0000F000 +#define SDRAM_SDTR1_RTRO_1_CLK 0x00000000 +#define SDRAM_SDTR1_RTRO_2_CLK 0x00002000 + +/*-----------------------------------------------------------------------------+ +| SDRAM SDTR2 Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_SDTR2_RCD_MASK 0xF0000000 +#define SDRAM_SDTR2_RCD_1_CLK 0x10000000 +#define SDRAM_SDTR2_RCD_2_CLK 0x20000000 +#define SDRAM_SDTR2_RCD_3_CLK 0x30000000 +#define SDRAM_SDTR2_RCD_4_CLK 0x40000000 +#define SDRAM_SDTR2_RCD_5_CLK 0x50000000 +#define SDRAM_SDTR2_WTR_MASK 0x0F000000 +#define SDRAM_SDTR2_WTR_1_CLK 0x01000000 +#define SDRAM_SDTR2_WTR_2_CLK 0x02000000 +#define SDRAM_SDTR2_WTR_3_CLK 0x03000000 +#define SDRAM_SDTR2_WTR_4_CLK 0x04000000 +#define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDRAM_SDTR2_XSNR_MASK 0x00FF0000 +#define SDRAM_SDTR2_XSNR_8_CLK 0x00080000 +#define SDRAM_SDTR2_XSNR_16_CLK 0x00100000 +#define SDRAM_SDTR2_XSNR_32_CLK 0x00200000 +#define SDRAM_SDTR2_XSNR_64_CLK 0x00400000 +#define SDRAM_SDTR2_WPC_MASK 0x0000F000 +#define SDRAM_SDTR2_WPC_2_CLK 0x00002000 +#define SDRAM_SDTR2_WPC_3_CLK 0x00003000 +#define SDRAM_SDTR2_WPC_4_CLK 0x00004000 +#define SDRAM_SDTR2_WPC_5_CLK 0x00005000 +#define SDRAM_SDTR2_WPC_6_CLK 0x00006000 +#define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12) +#define SDRAM_SDTR2_RPC_MASK 0x00000F00 +#define SDRAM_SDTR2_RPC_2_CLK 0x00000200 +#define SDRAM_SDTR2_RPC_3_CLK 0x00000300 +#define SDRAM_SDTR2_RPC_4_CLK 0x00000400 +#define SDRAM_SDTR2_RP_MASK 0x000000F0 +#define SDRAM_SDTR2_RP_3_CLK 0x00000030 +#define SDRAM_SDTR2_RP_4_CLK 0x00000040 +#define SDRAM_SDTR2_RP_5_CLK 0x00000050 +#define SDRAM_SDTR2_RP_6_CLK 0x00000060 +#define SDRAM_SDTR2_RP_7_CLK 0x00000070 +#define SDRAM_SDTR2_RRD_MASK 0x0000000F +#define SDRAM_SDTR2_RRD_2_CLK 0x00000002 +#define SDRAM_SDTR2_RRD_3_CLK 0x00000003 + +/*-----------------------------------------------------------------------------+ +| SDRAM SDTR3 Options ++-----------------------------------------------------------------------------*/ +#define SDRAM_SDTR3_RAS_MASK 0x1F000000 +#define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define SDRAM_SDTR3_RC_MASK 0x001F0000 +#define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define SDRAM_SDTR3_XCS_MASK 0x00001F00 +#define SDRAM_SDTR3_XCS 0x00000D00 +#define SDRAM_SDTR3_RFC_MASK 0x0000003F +#define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0) + +/*-----------------------------------------------------------------------------+ +| Memory Bank 0-1 configuration ++-----------------------------------------------------------------------------*/ +#define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */ +#define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */ +#define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */ +#define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */ +#define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */ +#define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */ +#define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */ +#define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */ +#define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */ +#define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */ +#define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */ +#define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ +#define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ +#define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ + +#define sdr_uart0 0x0120 /* UART0 Config */ +#define sdr_uart1 0x0121 /* UART1 Config */ +#define sdr_mfr 0x4300 /* SDR0_MFR reg */ + +/* Defines for CPC0_EPRCSR register */ +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 + +#define cpr0_clkupd 0x020 +#define cpr0_pllc 0x040 +#define cpr0_plld 0x060 +#define cpr0_cpud 0x080 +#define cpr0_plbd 0x0a0 +#define cpr0_opbd 0x0c0 +#define cpr0_perd 0x0e0 +#define cpr0_ahbd 0x100 +#define cpr0_icfg 0x140 + +#define SDR_PINSTP 0x0040 +#define sdr_sdcs 0x0060 + +#define SDR0_SDCS_SDD (0x80000000 >> 31) + +/* CUST0 Customer Configuration Register0 */ +#define SDR0_CUST0 0x4000 +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ + +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ + +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ + +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) + +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) + +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ +#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) +#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) + +#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ +#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ +#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ + +#define SDR0_PFC0 0x4100 +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_U1ME 0x02000000 +#define SDR0_PFC1_U0ME 0x00080000 +#define SDR0_PFC1_U0IM 0x00040000 +#define SDR0_PFC1_SIS 0x00020000 +#define SDR0_PFC1_DMAAEN 0x00010000 +#define SDR0_PFC1_DMADEN 0x00008000 +#define SDR0_PFC1_USBEN 0x00004000 +#define SDR0_PFC1_AHBSWAP 0x00000020 +#define SDR0_PFC1_USBBIGEN 0x00000010 +#define SDR0_PFC1_GPT_FREQ 0x0000000f +#endif #endif /* __PPC405_H__ */ diff --git a/include/ppc440.h b/include/ppc440.h index 38809f3..21e8836 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -22,6 +22,8 @@ #ifndef __PPC440_H__ #define __PPC440_H__ +#define CFG_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ + /*--------------------------------------------------------------------- */ /* Special Purpose Registers */ /*--------------------------------------------------------------------- */ @@ -123,10 +125,6 @@ /*----------------------------------------------------------------------------- | Clocking Controller +----------------------------------------------------------------------------*/ -#define CLOCKING_DCR_BASE 0x0c -#define clkcfga (CLOCKING_DCR_BASE+0x0) -#define clkcfgd (CLOCKING_DCR_BASE+0x1) - /* values for clkcfga register - indirect addressing of these regs */ #define clk_clkukpd 0x0020 #define clk_pllc 0x0040 @@ -140,9 +138,6 @@ #define clk_icfg 0x0140 /* 440gx sdr register definations */ -#define SDR_DCR_BASE 0x0e -#define sdrcfga (SDR_DCR_BASE+0x0) -#define sdrcfgd (SDR_DCR_BASE+0x1) #define sdr_sdstp0 0x0020 /* */ #define sdr_sdstp1 0x0021 /* */ #define SDR_PINSTP 0x0040 @@ -242,10 +237,6 @@ /*----------------------------------------------------------------------------- | SDRAM Controller +----------------------------------------------------------------------------*/ -#define SDRAM_DCR_BASE 0x10 -#define memcfga (SDRAM_DCR_BASE+0x0) /* Memory configuration address reg */ -#define memcfgd (SDRAM_DCR_BASE+0x1) /* Memory configuration data reg */ - /* values for memcfga register - indirect addressing of these regs */ #define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */ #define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */ @@ -331,9 +322,6 @@ #define sdr_sdstp6 0x4005 #define sdr_sdstp7 0x4007 -#define SDR0_CFGADDR 0x00E -#define SDR0_CFGDATA 0x00F - /****************************************************************************** * PCI express defines ******************************************************************************/ @@ -480,10 +468,6 @@ /*----------------------------------------------------------------------------+ | Memory controller defines +----------------------------------------------------------------------------*/ -#define SDRAMC_DCR_BASE 0x010 -#define SDRAMC_CFGADDR (SDRAMC_DCR_BASE+0x0) /* Memory configuration add */ -#define SDRAMC_CFGDATA (SDRAMC_DCR_BASE+0x1) /* Memory configuration data */ - /* A REVOIR versus specs 4 bank - SG*/ #define SDRAM_MCSTAT 0x14 /* memory controller status */ #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */ @@ -829,14 +813,13 @@ #define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */ #define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */ #define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */ + +#define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */ #endif /* CONFIG_440SPE */ /*----------------------------------------------------------------------------- | External Bus Controller +----------------------------------------------------------------------------*/ -#define EBC_DCR_BASE 0x12 -#define ebccfga (EBC_DCR_BASE+0x0) /* External bus controller addr reg */ -#define ebccfgd (EBC_DCR_BASE+0x1) /* External bus controller data reg */ /* values for ebccfga register - indirect addressing of these regs */ #define pb0cr 0x00 /* periph bank 0 config reg */ #define pb1cr 0x01 /* periph bank 1 config reg */ @@ -2207,9 +2190,6 @@ #define SDR0_CP440_NTO1_NTO1 0x00000002 #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) -#define SDR0_CFGADDR 0x00E /*already defined line 277 */ -#define SDR0_CFGDATA 0x00F - #define SDR0_SDSTP0 0x0020 #define SDR0_SDSTP0_ENG_MASK 0x80000000 @@ -3209,9 +3189,6 @@ /****************************************************************************** * GPIO macro register defines ******************************************************************************/ -#define GPIO0 0 -#define GPIO1 1 - #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700) @@ -3227,31 +3204,6 @@ #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00) #define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00) -/* Offsets */ -#define GPIOx_OR 0x00 /* GPIO Output Register */ -#define GPIOx_TCR 0x04 /* GPIO Three-State Control Register */ -#define GPIOx_OSL 0x08 /* GPIO Output Select Register (Bits 0-31) */ -#define GPIOx_OSH 0x0C /* GPIO Ouput Select Register (Bits 32-63) */ -#define GPIOx_TSL 0x10 /* GPIO Three-State Select Register (Bits 0-31) */ -#define GPIOx_TSH 0x14 /* GPIO Three-State Select Register (Bits 32-63) */ -#define GPIOx_ODR 0x18 /* GPIO Open drain Register */ -#define GPIOx_IR 0x1C /* GPIO Input Register */ -#define GPIOx_RR1 0x20 /* GPIO Receive Register 1 */ -#define GPIOx_RR2 0x24 /* GPIO Receive Register 2 */ -#define GPIOx_RR3 0x28 /* GPIO Receive Register 3 */ -#define GPIOx_IS1L 0x30 /* GPIO Input Select Register 1 (Bits 0-31) */ -#define GPIOx_IS1H 0x34 /* GPIO Input Select Register 1 (Bits 32-63) */ -#define GPIOx_IS2L 0x38 /* GPIO Input Select Register 2 (Bits 0-31) */ -#define GPIOx_IS2H 0x3C /* GPIO Input Select Register 2 (Bits 32-63) */ -#define GPIOx_IS3L 0x40 /* GPIO Input Select Register 3 (Bits 0-31) */ -#define GPIOx_IS3H 0x44 /* GPIO Input Select Register 3 (Bits 32-63) */ - -#define GPIO_OS(x) (x+GPIOx_OSL) /* GPIO Output Register High or Low */ -#define GPIO_TS(x) (x+GPIOx_TSL) /* GPIO Three-state Control Reg High or Low */ -#define GPIO_IS1(x) (x+GPIOx_IS1L) /* GPIO Input register1 High or Low */ -#define GPIO_IS2(x) (x+GPIOx_IS2L) /* GPIO Input register2 High or Low */ -#define GPIO_IS3(x) (x+GPIOx_IS3L) /* GPIO Input register3 High or Low */ - #define GPIO0_OR (GPIO0_BASE+0x0) #define GPIO0_TCR (GPIO0_BASE+0x4) #define GPIO0_OSRL (GPIO0_BASE+0x8) @@ -3289,71 +3241,8 @@ #define GPIO1_ISR3H (GPIO1_BASE+0x44) #endif -/* - * Macros for accessing the indirect EBC registers - */ -#define mtebc(reg, data) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,data); } while (0) -#define mfebc(reg, data) do { mtdcr(ebccfga,reg);data = mfdcr(ebccfgd); } while (0) - -/* - * Macros for accessing the indirect SDRAM controller registers - */ -#define mtsdram(reg, data) do { mtdcr(memcfga,reg);mtdcr(memcfgd,data); } while (0) -#define mfsdram(reg, data) do { mtdcr(memcfga,reg);data = mfdcr(memcfgd); } while (0) - -/* - * Macros for accessing the indirect clocking controller registers - */ -#define mtclk(reg, data) do { mtdcr(clkcfga,reg);mtdcr(clkcfgd,data); } while (0) -#define mfclk(reg, data) do { mtdcr(clkcfga,reg);data = mfdcr(clkcfgd); } while (0) - -/* - * Macros for accessing the sdr controller registers - */ -#define mtsdr(reg, data) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data); } while (0) -#define mfsdr(reg, data) do { mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd); } while (0) - -/* - * All 44x except 440GP have CPR registers (indirect DCR) - */ -#if !defined(CONFIG_440GP) -#define CPR0_CFGADDR 0x00C -#define CPR0_CFGDATA 0x00D - -#define mtcpr(reg, data) do { \ - mtdcr(CPR0_CFGADDR, reg); \ - mtdcr(CPR0_CFGDATA, data); \ - } while (0) - -#define mfcpr(reg, data) do { \ - mtdcr(CPR0_CFGADDR, reg); \ - data = mfdcr(CPR0_CFGDATA); \ - } while (0) -#endif - #ifndef __ASSEMBLY__ -typedef struct { - unsigned long pllFwdDivA; - unsigned long pllFwdDivB; - unsigned long pllFbkDiv; - unsigned long pllOpbDiv; - unsigned long pllPciDiv; - unsigned long pllExtBusDiv; - unsigned long freqVCOMhz; /* in MHz */ - unsigned long freqProcessor; - unsigned long freqTmrClk; - unsigned long freqPLB; - unsigned long freqOPB; - unsigned long freqEPB; - unsigned long freqPCI; -#ifdef CONFIG_440SPE - unsigned long freqDDR; -#endif - unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ - unsigned long pciClkSync; /* PCI clock is synchronous */ -} PPC440_SYS_INFO; - static inline u32 get_mcsr(void) { u32 val; @@ -3369,8 +3258,4 @@ static inline void set_mcsr(u32 val) #endif /* _ASMLANGUAGE */ -#define RESET_VECTOR 0xfffffffc -#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for */ - /* cache line aligned data. */ - #endif /* __PPC440_H__ */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h index ca241d2..76fe872 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -22,13 +22,80 @@ #ifndef __PPC4XX_H__ #define __PPC4XX_H__ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ -#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) - #if defined(CONFIG_440) #include <ppc440.h> #else #include <ppc405.h> #endif +/* + * Common stuff for 4xx (405 and 440) + */ + +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) + +#define RESET_VECTOR 0xfffffffc +#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache + line aligned data. */ + +#define CPR0_DCR_BASE 0x0C +#define cprcfga (CPR0_DCR_BASE+0x0) +#define cprcfgd (CPR0_DCR_BASE+0x1) + +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) +#define sdrcfgd (SDR_DCR_BASE+0x1) + +#define SDRAM_DCR_BASE 0x10 +#define memcfga (SDRAM_DCR_BASE+0x0) +#define memcfgd (SDRAM_DCR_BASE+0x1) + +#define EBC_DCR_BASE 0x12 +#define ebccfga (EBC_DCR_BASE+0x0) +#define ebccfgd (EBC_DCR_BASE+0x1) + +/* + * Macros for indirect DCR access + */ +#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) +#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) + +#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) +#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) + +#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) +#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) + +#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) +#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) + +#ifndef __ASSEMBLY__ + +typedef struct +{ + unsigned long freqDDR; + unsigned long freqEBC; + unsigned long freqOPB; + unsigned long freqPCI; + unsigned long freqPLB; + unsigned long freqTmrClk; + unsigned long freqUART; + unsigned long freqProcessor; + unsigned long freqVCOHz; + unsigned long freqVCOMhz; /* in MHz */ + unsigned long pciClkSync; /* PCI clock is synchronous */ + unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ + unsigned long pllExtBusDiv; + unsigned long pllFbkDiv; + unsigned long pllFwdDiv; + unsigned long pllFwdDivA; + unsigned long pllFwdDivB; + unsigned long pllOpbDiv; + unsigned long pllPciDiv; + unsigned long pllPlbDiv; +} PPC4xx_SYS_INFO; + +#endif /* __ASSEMBLY__ */ + #endif /* __PPC4XX_H__ */ diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index 3d8ca09..f285500 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -102,6 +102,8 @@ typedef struct emac_4xx_hw_st { uint32_t emac_ier; volatile mal_desc_t *tx; volatile mal_desc_t *rx; + u32 tx_phys; + u32 rx_phys; bd_t *bis; /* for eth_init upon mal error */ mal_desc_t *alloc_tx_buf; mal_desc_t *alloc_rx_buf; @@ -146,11 +148,12 @@ typedef struct emac_4xx_hw_st { #endif #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #define SDR0_PFC1_EM_1000 (0x00200000) #endif -/*ZMII Bridge Register addresses */ +/* ZMII Bridge Register addresses */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00) @@ -202,6 +205,8 @@ typedef struct emac_4xx_hw_st { /* RGMII Register Addresses */ #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1000) +#elif defined(CONFIG_405EX) +#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0xB00) #else #define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790) #endif @@ -223,7 +228,8 @@ typedef struct emac_4xx_hw_st { #define RGMII_SSR_SP_100MBPS (0x02) #define RGMII_SSR_SP_1000MBPS (0x04) -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_405EX) #define RGMII_SSR_V(__x) ((__x) * 8) #else #define RGMII_SSR_V(__x) ((__x -2) * 8) @@ -304,7 +310,7 @@ typedef struct emac_4xx_hw_st { #define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) #endif #else -#if defined(CONFIG_405EZ) +#if defined(CONFIG_405EZ) || defined(CONFIG_405EX) #define EMAC_BASE 0xEF600900 #else #define EMAC_BASE 0xEF600800 @@ -338,7 +344,8 @@ typedef struct emac_4xx_hw_st { /* on 440GX EMAC_MR1 has a different layout! */ #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_405EX) /* MODE Reg 1 */ #define EMAC_M1_FDE (0x80000000) #define EMAC_M1_ILE (0x40000000) diff --git a/include/serial.h b/include/serial.h index 30bfde3..e292f0c 100644 --- a/include/serial.h +++ b/include/serial.h @@ -22,8 +22,9 @@ extern struct serial_device serial_smc_device; extern struct serial_device serial_scc_device; extern struct serial_device * default_serial_console (void); -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ - || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_MPC5xxx) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ + defined(CONFIG_MPC5xxx) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CFG_NS16550_SERIAL) diff --git a/lib_ppc/cache.c b/lib_ppc/cache.c index a81ab5e..27e1a82 100644 --- a/lib_ppc/cache.c +++ b/lib_ppc/cache.c @@ -22,7 +22,7 @@ */ #include <common.h> - +#include <asm/cache.h> void flush_cache (ulong start_addr, ulong size) { diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile index 2d4d601..6e53bea 100644 --- a/nand_spl/board/amcc/acadia/Makefile +++ b/nand_spl/board/amcc/acadia/Makefile @@ -29,7 +29,7 @@ LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL -SOBJS = start.o resetvec.o +SOBJS = start.o resetvec.o cache.o COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) @@ -63,6 +63,10 @@ $(nandobj)System.map: $(nandobj)u-boot-spl # create symbolic links for common files # from cpu directory +$(obj)cache.S: + @rm -f $(obj)cache.S + ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S + $(obj)gpio.c: @rm -f $(obj)gpio.c ln -s $(SRCTREE)/cpu/ppc4xx/gpio.c $(obj)gpio.c diff --git a/nand_spl/board/amcc/bamboo/sdram.c b/nand_spl/board/amcc/bamboo/sdram.c index 4f09072..ac77d06 100644 --- a/nand_spl/board/amcc/bamboo/sdram.c +++ b/nand_spl/board/amcc/bamboo/sdram.c @@ -44,6 +44,12 @@ static void wait_init_complete(void) * not enough free space to implement the complete I2C SPD DDR autodetection * routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM * when booting from NAND flash. + * + * Note: + * As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed + * DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM + * modules are still plugged in. So it is recommended to remove the DIMM + * modules while using the NAND booting code with the fixed SDRAM setup! */ void early_sdram_init(void) { diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile new file mode 100644 index 0000000..98f2775 --- /dev/null +++ b/nand_spl/board/amcc/kilauea/Makefile @@ -0,0 +1,108 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o init.o resetvec.o cache.o +COBJS = memory.o nand_boot.o nand_ecc.o ndfc.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +# from cpu directory +$(obj)cache.S: + @rm -f $(obj)cache.S + ln -s $(SRCTREE)/cpu/ppc4xx/cache.S $(obj)cache.S + +$(obj)ndfc.c: + @rm -f $(obj)ndfc.c + ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S + +$(obj)start.S: + @rm -f $(obj)start.S + ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S + +# from board directory +$(obj)init.S: + @rm -f $(obj)init.S + ln -s $(SRCTREE)/board/amcc/kilauea/init.S $(obj)init.S + +$(obj)memory.c: + @rm -f $(obj)memory.c + ln -s $(SRCTREE)/board/amcc/kilauea/memory.c $(obj)memory.c + +# from nand_spl directory +$(obj)nand_boot.c: + @rm -f $(obj)nand_boot.c + ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c + +# from drivers/nand directory +$(obj)nand_ecc.c: + @rm -f $(obj)nand_ecc.c + ln -s $(SRCTREE)/drivers/nand/nand_ecc.c $(obj)nand_ecc.c + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/amcc/kilauea/config.mk b/nand_spl/board/amcc/kilauea/config.mk new file mode 100644 index 0000000..2249091 --- /dev/null +++ b/nand_spl/board/amcc/kilauea/config.mk @@ -0,0 +1,47 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# AMCC 405EX Reference Platform (Kilauea) board +# + +# +# TEXT_BASE for SPL: +# +# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff, +# in the last 4kBytes of memory space in cache. +# We will copy this SPL into instruction-cache in start.S. So we set +# TEXT_BASE to starting address in i-cache here. +# +TEXT_BASE = 0x00800000 + +# PAD_TO used to generate a 16kByte binary needed for the combined image +# -> PAD_TO = TEXT_BASE + 0x4000 +PAD_TO = 0x00804000 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/nand_spl/board/amcc/kilauea/u-boot.lds b/nand_spl/board/amcc/kilauea/u-boot.lds new file mode 100644 index 0000000..24df32d --- /dev/null +++ b/nand_spl/board/amcc/kilauea/u-boot.lds @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc:common) +SECTIONS +{ + .resetvec 0x00800FFC : + { + *(.resetvec) + } = 0xffff + + .text : + { + start.o (.text) + init.o (.text) + nand_boot.o (.text) + ndfc.o (.text) + + *(.text) + *(.fixup) + } + _etext = .; + + .data : + { + *(.rodata*) + *(.data*) + *(.sdata*) + __got2_start = .; + *(.got2) + __got2_end = .; + } + + _edata = .; + + __bss_start = .; + .bss : + { + *(.sbss) + *(.bss) + } + + _end = . ; +} diff --git a/post/cpu/ppc4xx/cache.c b/post/cpu/ppc4xx/cache.c index 109ca1f..30d5088 100644 --- a/post/cpu/ppc4xx/cache.c +++ b/post/cpu/ppc4xx/cache.c @@ -119,6 +119,10 @@ int cache_post_test (int flags) if (ints) enable_interrupts (); +#ifdef CONFIG_440 + remove_tlb((u32)virt, CACHE_POST_SIZE); +#endif + return res; } diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c index ab23ca5..09f9a5f 100644 --- a/post/cpu/ppc4xx/ether.c +++ b/post/cpu/ppc4xx/ether.c @@ -52,6 +52,28 @@ DECLARE_GLOBAL_DATA_PTR; +/* + * Get count of EMAC devices (doesn't have to be the max. possible number + * supported by the cpu) + * + * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the + * EMAC count is possible. As it is needed for the Kilauea/Haleakala + * 405EX/405EXr eval board, using the same binary. + */ +#if defined(CONFIG_BOARD_EMAC_COUNT) +#define LAST_EMAC_NUM board_emac_count() +#else /* CONFIG_BOARD_EMAC_COUNT */ +#if defined(CONFIG_HAS_ETH3) +#define LAST_EMAC_NUM 4 +#elif defined(CONFIG_HAS_ETH2) +#define LAST_EMAC_NUM 3 +#elif defined(CONFIG_HAS_ETH1) +#define LAST_EMAC_NUM 2 +#else +#define LAST_EMAC_NUM 1 +#endif +#endif /* CONFIG_BOARD_EMAC_COUNT */ + #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) #endif @@ -65,6 +87,8 @@ static volatile mal_desc_t rx __cacheline_aligned; static char *tx_buf; static char *rx_buf; +int board_emac_count(void); + static void ether_post_init (int devnum, int hw_addr) { int i; @@ -145,6 +169,8 @@ static void ether_post_init (int devnum, int hw_addr) rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY; rx.data_len = 0; rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf); + flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t)); + flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t)); switch (devnum) { case 1: @@ -266,11 +292,14 @@ static void ether_post_send (int devnum, int hw_addr, void *packet, int length) return; } udelay (1000); + invalidate_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t)); } tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST | EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP; tx.data_len = length; memcpy (tx.data_ptr, packet, length); + flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t)); + flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length); sync (); out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0); @@ -288,13 +317,17 @@ static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_lengt return 0; } udelay (1000); + invalidate_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t)); } length = rx.data_len - 4; - if (length <= max_length) + if (length <= max_length) { + invalidate_dcache_range((u32)rx.data_ptr, (u32)rx.data_ptr + length); memcpy(packet, rx.data_ptr, length); + } sync (); rx.ctrl |= MAL_RX_CTRL_EMPTY; + flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t)); sync (); return length; @@ -372,6 +405,7 @@ Done: int ether_post_test (int flags) { int res = 0; + int i; /* Allocate tx & rx packet buffers */ tx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE); @@ -383,13 +417,10 @@ int ether_post_test (int flags) goto out_free; } - /* EMAC0 */ - if (test_ctlr (0, 0)) - res = -1; - - /* EMAC1 */ - if (test_ctlr (1, 0x100)) - res = -1; + for (i = 0; i < LAST_EMAC_NUM; i++) { + if (test_ctlr (i, i*0x100)) + res = -1; + } out_free: free (tx_buf); diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c index 7c3ed40..f47b48e 100644 --- a/post/cpu/ppc4xx/uart.c +++ b/post/cpu/ppc4xx/uart.c @@ -101,6 +101,17 @@ #define UCR0_UDIV_POS 0 #define UCR1_UDIV_POS 8 #define UDIV_MAX 127 +#elif defined(CONFIG_405EX) +#define UART0_BASE 0xef600200 +#define UART1_BASE 0xef600300 +#define CR0_MASK 0x000000ff +#define CR0_EXTCLK_ENA 0x00800000 +#define CR0_UDIV_POS 0 +#define UDIV_SUBTRACT 0 +#define UART0_SDR sdr_uart0 +#define UART1_SDR sdr_uart1 +#define MFREG(a, d) mfsdr(a, d) +#define MTREG(a, d) mtsdr(a, d) #else /* CONFIG_405GP || CONFIG_405CR */ #define UART0_BASE 0xef600300 #define UART1_BASE 0xef600400 @@ -137,7 +148,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_440) +#if defined(CONFIG_440) || defined(CONFIG_405EX) #if !defined(CFG_EXT_SERIAL_CLOCK) static void serial_divs (int baudrate, unsigned long *pudiv, unsigned short *pbdiv) @@ -183,7 +194,7 @@ static void serial_divs (int baudrate, unsigned long *pudiv, static int uart_post_init (unsigned long dev_base) { - unsigned long reg; + unsigned long reg = 0; unsigned long udiv; unsigned short bdiv; volatile char val; diff --git a/post/lib_ppc/cpu.c b/post/lib_ppc/cpu.c index 1f2ded2..4ab6d2d 100644 --- a/post/lib_ppc/cpu.c +++ b/post/lib_ppc/cpu.c @@ -36,6 +36,7 @@ #include <watchdog.h> #include <post.h> +#include <asm/mmu.h> #if CONFIG_POST & CFG_POST_CPU @@ -59,6 +60,8 @@ extern int cpu_post_test_multi (void); extern int cpu_post_test_string (void); extern int cpu_post_test_complex (void); +DECLARE_GLOBAL_DATA_PTR; + ulong cpu_post_makecr (long v) { ulong cr = 0; @@ -81,6 +84,10 @@ int cpu_post_test (int flags) WATCHDOG_RESET(); if (ic) icache_disable (); +#ifdef CONFIG_4xx_DCACHE + /* disable cache */ + change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE); +#endif if (ret == 0) ret = cpu_post_test_cmp (); @@ -129,6 +136,10 @@ int cpu_post_test (int flags) if (ic) icache_enable (); +#ifdef CONFIG_4xx_DCACHE + /* enable cache */ + change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0); +#endif WATCHDOG_RESET(); diff --git a/rtc/x1205.c b/rtc/x1205.c new file mode 100644 index 0000000..319f051 --- /dev/null +++ b/rtc/x1205.c @@ -0,0 +1,178 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * based on a the Linux rtc-x1207.c driver which is: + * Copyright 2004 Karen Spearel + * Copyright 2005 Alessandro Zummo + * + * Information and datasheet: + * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Date & Time support for Xicor/Intersil X1205 RTC + */ + +/* #define DEBUG */ + +#include <common.h> +#include <command.h> +#include <rtc.h> +#include <i2c.h> +#include <bcd.h> + +#if defined(CONFIG_RTC_X1205) && defined(CONFIG_CMD_DATE) + +#define CCR_SEC 0 +#define CCR_MIN 1 +#define CCR_HOUR 2 +#define CCR_MDAY 3 +#define CCR_MONTH 4 +#define CCR_YEAR 5 +#define CCR_WDAY 6 +#define CCR_Y2K 7 + +#define X1205_REG_SR 0x3F /* status register */ +#define X1205_REG_Y2K 0x37 +#define X1205_REG_DW 0x36 +#define X1205_REG_YR 0x35 +#define X1205_REG_MO 0x34 +#define X1205_REG_DT 0x33 +#define X1205_REG_HR 0x32 +#define X1205_REG_MN 0x31 +#define X1205_REG_SC 0x30 +#define X1205_REG_DTR 0x13 +#define X1205_REG_ATR 0x12 +#define X1205_REG_INT 0x11 +#define X1205_REG_0 0x10 +#define X1205_REG_Y2K1 0x0F +#define X1205_REG_DWA1 0x0E +#define X1205_REG_YRA1 0x0D +#define X1205_REG_MOA1 0x0C +#define X1205_REG_DTA1 0x0B +#define X1205_REG_HRA1 0x0A +#define X1205_REG_MNA1 0x09 +#define X1205_REG_SCA1 0x08 +#define X1205_REG_Y2K0 0x07 +#define X1205_REG_DWA0 0x06 +#define X1205_REG_YRA0 0x05 +#define X1205_REG_MOA0 0x04 +#define X1205_REG_DTA0 0x03 +#define X1205_REG_HRA0 0x02 +#define X1205_REG_MNA0 0x01 +#define X1205_REG_SCA0 0x00 + +#define X1205_CCR_BASE 0x30 /* Base address of CCR */ +#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */ + +#define X1205_SR_RTCF 0x01 /* Clock failure */ +#define X1205_SR_WEL 0x02 /* Write Enable Latch */ +#define X1205_SR_RWEL 0x04 /* Register Write Enable */ + +#define X1205_DTR_DTR0 0x01 +#define X1205_DTR_DTR1 0x02 +#define X1205_DTR_DTR2 0x04 + +#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */ + +static void rtc_write(int reg, u8 val) +{ + i2c_write(CFG_I2C_RTC_ADDR, reg, 2, &val, 1); +} + +/* + * In the routines that deal directly with the x1205 hardware, we use + * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch + * Epoch is initialized as 2000. Time is set to UTC. + */ +void rtc_get(struct rtc_time *tm) +{ + u8 buf[8]; + + i2c_read(CFG_I2C_RTC_ADDR, X1205_CCR_BASE, 2, buf, 8); + + debug("%s: raw read data - sec=%02x, min=%02x, hr=%02x, " + "mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n", + __FUNCTION__, + buf[0], buf[1], buf[2], buf[3], + buf[4], buf[5], buf[6], buf[7]); + + tm->tm_sec = BCD2BIN(buf[CCR_SEC]); + tm->tm_min = BCD2BIN(buf[CCR_MIN]); + tm->tm_hour = BCD2BIN(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */ + tm->tm_mday = BCD2BIN(buf[CCR_MDAY]); + tm->tm_mon = BCD2BIN(buf[CCR_MONTH]); /* mon is 0-11 */ + tm->tm_year = BCD2BIN(buf[CCR_YEAR]) + + (BCD2BIN(buf[CCR_Y2K]) * 100); + tm->tm_wday = buf[CCR_WDAY]; + + debug("%s: tm is secs=%d, mins=%d, hours=%d, " + "mday=%d, mon=%d, year=%d, wday=%d\n", + __FUNCTION__, + tm->tm_sec, tm->tm_min, tm->tm_hour, + tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday); +} + +void rtc_set(struct rtc_time *tm) +{ + int i; + u8 buf[8]; + + debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, + tm->tm_hour, tm->tm_min, tm->tm_sec); + + buf[CCR_SEC] = BIN2BCD(tm->tm_sec); + buf[CCR_MIN] = BIN2BCD(tm->tm_min); + + /* set hour and 24hr bit */ + buf[CCR_HOUR] = BIN2BCD(tm->tm_hour) | X1205_HR_MIL; + + buf[CCR_MDAY] = BIN2BCD(tm->tm_mday); + + /* month, 1 - 12 */ + buf[CCR_MONTH] = BIN2BCD(tm->tm_mon); + + /* year, since the rtc epoch*/ + buf[CCR_YEAR] = BIN2BCD(tm->tm_year % 100); + buf[CCR_WDAY] = tm->tm_wday & 0x07; + buf[CCR_Y2K] = BIN2BCD(tm->tm_year / 100); + + /* this sequence is required to unlock the chip */ + rtc_write(X1205_REG_SR, X1205_SR_WEL); + rtc_write(X1205_REG_SR, X1205_SR_WEL | X1205_SR_RWEL); + + /* write register's data */ + for (i = 0; i < 8; i++) + rtc_write(X1205_CCR_BASE + i, buf[i]); + + rtc_write(X1205_REG_SR, 0); +} + +void rtc_reset(void) +{ + /* + * Nothing to do + */ +} + +#endif |