diff options
419 files changed, 5086 insertions, 3382 deletions
@@ -1382,9 +1382,6 @@ The following options need to be configured: Management command for E1000 devices. When used on devices with SPI support you can reprogram the EEPROM from U-Boot. - CONFIG_E1000_FALLBACK_MAC - default MAC for empty EEPROM after production. - CONFIG_EEPRO100 Support for Intel 82557/82559/82559ER chips. Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index e17e9f4..8588221 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -23,7 +23,6 @@ spi0 = &qspi; spi1 = &spi0; spi2 = &spi1; - mmc = &mmc; }; cpus { @@ -550,6 +549,7 @@ porta: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; + bank-name = "porta"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <29>; @@ -570,6 +570,7 @@ portb: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; + bank-name = "portb"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <29>; @@ -590,6 +591,7 @@ portc: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; + bank-name = "portc"; gpio-controller; #gpio-cells = <2>; snps,nr-gpios = <27>; @@ -621,7 +623,7 @@ arm,data-latency = <2 1 1>; }; - mmc: dwmmc0@ff704000 { + mmc0: dwmmc0@ff704000 { compatible = "altr,socfpga-dw-mshc"; reg = <0xff704000 0x1000>; interrupts = <0 139 4>; diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index f2b5963..7d1836e 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -33,6 +33,10 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + soc { + u-boot,dm-pre-reloc; + }; }; &gmac1 { @@ -67,6 +71,8 @@ &mmc0 { vmmc-supply = <®ulator_3_3v>; vqmmc-supply = <®ulator_3_3v>; + bus-width = <4>; + u-boot,dm-pre-reloc; }; &usb1 { diff --git a/arch/arm/dts/socfpga_cyclone5.dtsi b/arch/arm/dts/socfpga_cyclone5.dtsi index 234a901..de36209 100644 --- a/arch/arm/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/dts/socfpga_cyclone5.dtsi @@ -27,12 +27,6 @@ cap-sd-highspeed; }; - ethernet@ff702000 { - phy-mode = "rgmii"; - phy-addr = <0xffffffff>; /* probe for phy addr */ - status = "okay"; - }; - sysmgr@ffd08000 { cpu1-start-addr = <0xffd080c4>; }; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index 00b1830..6782691 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -23,6 +23,7 @@ &gmac1 { status = "okay"; + phy-mode = "rgmii"; }; &i2c0 { @@ -34,7 +35,7 @@ }; }; -&mmc { +&mmc0 { status = "okay"; }; diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 847da59..e72184b 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1105,6 +1105,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_UBISYS_P9D_EVP 3493 #define MACH_TYPE_ATDGP318 3494 #define MACH_TYPE_OMAP5_SEVM 3777 +#define MACH_TYPE_PICOSAM9G45 3838 #define MACH_TYPE_ARMADILLO_800EVA 3863 #define MACH_TYPE_KZM9G 4140 #define MACH_TYPE_COLIBRI_T30 4493 diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index d8d46dc..f9f148d 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -64,6 +64,11 @@ config TARGET_PM9G45 bool "Ronetix pm9g45 board" select CPU_ARM926EJS +config TARGET_PICOSAM9G45 + bool "Mini-box picosam9g45 board" + select CPU_ARM926EJS + select SUPPORT_SPL + config TARGET_AT91SAM9N12EK bool "Atmel AT91SAM9N12-EK board" select CPU_ARM926EJS @@ -155,6 +160,7 @@ source "board/egnite/ethernut5/Kconfig" source "board/esd/meesc/Kconfig" source "board/esd/otc570/Kconfig" source "board/eukrea/cpu9260/Kconfig" +source "board/mini-box/picosam9g45/Kconfig" source "board/ronetix/pm9261/Kconfig" source "board/ronetix/pm9263/Kconfig" source "board/ronetix/pm9g45/Kconfig" diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index ebb7dec..8a3fb94 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -158,6 +158,7 @@ typedef struct at91_pmc { #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ +#define AT91_PMC_DDR (1 << 2) /* DDR Clock */ #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h index 130a85a..c6c8dda 100644 --- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h +++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h @@ -23,8 +23,10 @@ struct atmel_mpddr { u32 md; }; -int ddr2_init(const unsigned int ram_address, - const struct atmel_mpddr *mpddr); + +int ddr2_init(const unsigned int base, + const unsigned int ram_address, + const struct atmel_mpddr *mpddr); /* Bit field in mode register */ #define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD 0x0 diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c index e2b6a49..47e6e5a 100644 --- a/arch/arm/mach-at91/mpddrc.c +++ b/arch/arm/mach-at91/mpddrc.c @@ -9,10 +9,10 @@ #include <asm/io.h> #include <asm/arch/atmel_mpddrc.h> -static inline void atmel_mpddr_op(int mode, u32 ram_address) +static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr, + int mode, + u32 ram_address) { - struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; - writel(mode, &mpddr->mr); writel(0, ram_address); } @@ -27,10 +27,13 @@ static int ddr2_decodtype_is_seq(u32 cr) return 1; } -int ddr2_init(const unsigned int ram_address, + +int ddr2_init(const unsigned int base, + const unsigned int ram_address, const struct atmel_mpddr *mpddr_value) { - struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + const struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base; + u32 ba_off, cr; /* Compute bank offset according to NC in configuration register */ @@ -52,30 +55,30 @@ int ddr2_init(const unsigned int ram_address, writel(mpddr_value->tpr2, &mpddr->tpr2); /* Issue a NOP command */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); /* A 200 us is provided to precede any signal toggle */ udelay(200); /* Issue a NOP command */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); /* Issue an all banks precharge command */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); /* Issue an extended mode register set(EMRS2) to choose operation */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, ram_address + (0x2 << ba_off)); /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, ram_address + (0x3 << ba_off)); /* * Issue an extended mode register set(EMRS1) to enable DLL and * program D.I.C (output driver impedance control) */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, ram_address + (0x1 << ba_off)); /* Enable DLL reset */ @@ -83,21 +86,21 @@ int ddr2_init(const unsigned int ram_address, writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr); /* A mode register set(MRS) cycle is issued to reset DLL */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); /* Issue an all banks precharge command */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); /* Two auto-refresh (CBR) cycles are provided */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); /* Disable DLL reset */ cr = readl(&mpddr->cr); writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr); /* A mode register set (MRS) cycle is issued to disable DLL reset */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); /* Set OCD calibration in default state */ cr = readl(&mpddr->cr); @@ -107,7 +110,7 @@ int ddr2_init(const unsigned int ram_address, * An extended mode register set (EMRS1) cycle is issued * to OCD default value */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, ram_address + (0x1 << ba_off)); /* OCD calibration mode exit */ @@ -118,11 +121,11 @@ int ddr2_init(const unsigned int ram_address, * An extended mode register set (EMRS1) cycle is issued * to enable OCD exit */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, ram_address + (0x1 << ba_off)); /* A nornal mode command is provided */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address); + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address); /* Perform a write access to any DDR2-SDRAM address */ writel(0, ram_address); diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index e46c348..690e362 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -1,28 +1,38 @@ if ARCH_SOCFPGA +config TARGET_SOCFPGA_ARRIA5 + bool + +config TARGET_SOCFPGA_CYCLONE5 + bool + choice prompt "Altera SOCFPGA board select" optional -config TARGET_SOCFPGA_ARRIA5 - bool "Altera SOCFPGA Arria V" +config TARGET_SOCFPGA_ARRIA5_SOCDK + bool "Altera SOCFPGA SoCDK (Arria V)" + select TARGET_SOCFPGA_ARRIA5 -config TARGET_SOCFPGA_CYCLONE5 - bool "Altera SOCFPGA Cyclone V" +config TARGET_SOCFPGA_CYCLONE5_SOCDK + bool "Altera SOCFPGA SoCDK (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 endchoice config SYS_BOARD - default "socfpga" + default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK config SYS_VENDOR - default "altera" + default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK config SYS_SOC default "socfpga" config SYS_CONFIG_NAME - default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5 - default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5 + default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK + default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK endif diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 8a745c9..316b326 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -10,3 +10,12 @@ obj-y += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \ fpga_manager.o scan_manager.o obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o + +# QTS-generated config file wrappers +obj-y += wrap_pll_config.o +obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ + wrap_sdram_config.o +CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) +CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR) +CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR) +CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR) diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 1341df4..aa71636 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -90,7 +90,7 @@ static void cm_write_with_phase(uint32_t value, void cm_basic_init(const struct cm_config * const cfg) { - uint32_t start, timeout; + unsigned long end; /* Start by being paranoid and gate all sw managed clocks */ @@ -159,12 +159,10 @@ void cm_basic_init(const struct cm_config * const cfg) writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); /* - * Time starts here - * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1) + * Time starts here. Must wait 7 us from + * BGPWRDN_SET(0) to VCO_ENABLE_SET(1). */ - start = get_timer(0); - /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */ - timeout = 7; + end = timer_get_us() + 7; /* main mpu */ writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); @@ -204,7 +202,7 @@ void cm_basic_init(const struct cm_config * const cfg) writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk); /* 7 us must have elapsed before we can enable the VCO */ - while (get_timer(start) < timeout) + while (timer_get_us() < end) ; /* Enable vco */ diff --git a/arch/arm/mach-socfpga/freeze_controller.c b/arch/arm/mach-socfpga/freeze_controller.c index 0be643c..2b16795 100644 --- a/arch/arm/mach-socfpga/freeze_controller.c +++ b/arch/arm/mach-socfpga/freeze_controller.c @@ -7,8 +7,8 @@ #include <common.h> #include <asm/io.h> +#include <asm/arch/clock_manager.h> #include <asm/arch/freeze_controller.h> -#include <asm/arch/timer.h> #include <asm/errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -112,6 +112,7 @@ void sys_mgr_frzctrl_thaw_req(void) u32 reg_cfg_mask; u32 reg_value; u32 channel_id; + unsigned long eosc1_freq; /* select software FSM */ writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW, &freeze_controller_base->src); @@ -162,12 +163,9 @@ void sys_mgr_frzctrl_thaw_req(void) setbits_le32(&freeze_controller_base->hioctrl, SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK); - /* - * Delay 1000 intosc. intosc is based on eosc1 - * Use worst case which is fatest eosc1=50MHz, delay required - * is 1/50MHz * 1000 = 20us - */ - udelay(20); + /* Delay 1000 intosc cycles. The intosc is based on eosc1. */ + eosc1_freq = cm_get_osc_clk_hz(1) / 1000; /* kHz */ + udelay(DIV_ROUND_UP(1000000, eosc1_freq)); /* * de-assert active low bhniotri signals, diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 46af30b..8712f8e 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -12,8 +12,7 @@ void sysmgr_pinmux_init(void); void sysmgr_config_warmrstcfgio(int enable); -void sysmgr_get_pinmux_table(const unsigned long **table, - unsigned int *table_len); +void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len); #endif struct socfpga_system_manager { diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh new file mode 100755 index 0000000..c1640bc --- /dev/null +++ b/arch/arm/mach-socfpga/qts-filter.sh @@ -0,0 +1,205 @@ +#!/bin/sh + +# +# Process iocsr_config_*.[ch] +# $1: SoC type +# $2: Input directory +# $3: Output directory +# +process_iocsr_config() { + soc="$1" + in_dir="$2" + out_dir="$3" + + ( + cat << EOF +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +EOF + + # Retrieve the scan chain lengths + grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \ + ${in_dir}/generated/iocsr_config_${soc}.h | tr -d "()" + + echo "" + + # Retrieve the scan chain config and zap the ad-hoc length encoding + sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}' \ + ${in_dir}/generated/iocsr_config_${soc}.c + + cat << EOF + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ +EOF + ) > "${out_dir}/iocsr_config.h" +} + +# +# Process pinmux_config_*.c (and ignore pinmux_config.h) +# $1: SoC type +# $2: Input directory +# $3: Output directory +# +process_pinmux_config() { + soc="$1" + in_dir="$2" + out_dir="$3" + + ( + cat << EOF +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +EOF + + # Retrieve the pinmux config and zap the ad-hoc length encoding + sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}' \ + ${in_dir}/generated/pinmux_config_${soc}.c + + cat << EOF + +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ +EOF + ) > "${out_dir}/pinmux_config.h" +} + +# +# Process pll_config.h +# $1: SoC type (not used) +# $2: Input directory +# $3: Output directory +# +process_pll_config() { + soc="$1" + in_dir="$2" + out_dir="$3" + + ( + cat << EOF +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +EOF + + # Retrieve the pll config and zap parenthesis + sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' \ + ${in_dir}/generated/pll_config.h + + cat << EOF + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ +EOF + ) > "${out_dir}/pll_config.h" +} + +# +# Filter out only the macros which are actually used by the code +# +grep_sdram_config() { + egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL)[[:space:]]" +} + +# +# Process sdram_config.h, sequencer_auto*h and sequencer_defines.h +# $1: SoC type (not used) +# $2: Input directory +# $3: Output directory +# +process_sdram_config() { + soc="$1" + in_dir="$2" + out_dir="$3" + + ( + cat << EOF +/* + * Altera SoCFPGA SDRAM configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +EOF + + echo "/* SDRAM configuration */" + # Retrieve the sdram config, zap broken lines and zap parenthesis + sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" ${in_dir}/generated/sdram/sdram_config.h | + sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' | + sort -u | grep_sdram_config + + echo "" + echo "/* Sequencer auto configuration */" + sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \ + ${in_dir}/hps_isw_handoff/*/sequencer_auto.h | sort -u | grep_sdram_config + + echo "" + echo "/* Sequencer defines configuration */" + sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \ + ${in_dir}/hps_isw_handoff/*/sequencer_defines.h | sort -u | grep_sdram_config + + echo "" + echo "/* Sequencer ac_rom_init configuration */" + sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\ + ${in_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c + + echo "" + echo "/* Sequencer inst_rom_init configuration */" + sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'\ + ${in_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c + + cat << EOF + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ +EOF + ) > "${out_dir}/sdram_config.h" +} + +usage() { + echo "$0 [soc_type] [input_dir] [output_dir]" + echo "Process QTS-generated headers into U-Boot compatible ones." + echo "" + echo " soc_type\t\tType of SoC, either 'cyclone5' or 'arria5'," + echo " input_dir\t\tDirectory with the QTS project." + echo " output_dir\t\tDirectory to store the U-Boot compatible headers." + echo "" +} + +soc="$1" +in_dir="$2" +out_dir="$3" + +if [ "$#" -ne 3 ] ; then + usage + exit 1 +fi + +if [ ! -d "${in_dir}" -o ! -d "${out_dir}" -o -z "${soc}" ] ; then + usage + exit 3 +fi + +process_iocsr_config "${soc}" "${in_dir}" "${out_dir}" +process_pinmux_config "${soc}" "${in_dir}" "${out_dir}" +process_pll_config "${soc}" "${in_dir}" "${out_dir}" +process_sdram_config "${soc}" "${in_dir}" "${out_dir}" diff --git a/arch/arm/mach-socfpga/system_manager.c b/arch/arm/mach-socfpga/system_manager.c index 744ec32..75a65f3 100644 --- a/arch/arm/mach-socfpga/system_manager.c +++ b/arch/arm/mach-socfpga/system_manager.c @@ -57,7 +57,7 @@ static void populate_sysmgr_fpgaintf_module(void) void sysmgr_pinmux_init(void) { uint32_t regs = (uint32_t)&sysmgr_regs->emacio[0]; - const unsigned long *sys_mgr_init_table; + const u8 *sys_mgr_init_table; unsigned int len; int i; diff --git a/board/altera/socfpga/wrap_iocsr_config.c b/arch/arm/mach-socfpga/wrap_iocsr_config.c index 49e9228..5e3f057 100644 --- a/board/altera/socfpga/wrap_iocsr_config.c +++ b/arch/arm/mach-socfpga/wrap_iocsr_config.c @@ -7,10 +7,9 @@ #include <common.h> #include <errno.h> #include <asm/arch/clock_manager.h> -/* - * Yes, dear reader, we're including a C file here, this is no mistake :-) - */ -#include "qts/iocsr_config.c" + +/* Board-specific header. */ +#include <qts/iocsr_config.h> int iocsr_get_config_table(const unsigned int chain_id, const unsigned long **table, diff --git a/arch/arm/mach-socfpga/wrap_pinmux_config.c b/arch/arm/mach-socfpga/wrap_pinmux_config.c new file mode 100644 index 0000000..a12f0b3 --- /dev/null +++ b/arch/arm/mach-socfpga/wrap_pinmux_config.c @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> + +/* Board-specific header. */ +#include <qts/pinmux_config.h> + +void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len) +{ + *table = sys_mgr_init_table; + *table_len = ARRAY_SIZE(sys_mgr_init_table); +} diff --git a/board/altera/socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c index 8dbff68..8a0a0e6 100644 --- a/board/altera/socfpga/wrap_pll_config.c +++ b/arch/arm/mach-socfpga/wrap_pll_config.c @@ -6,7 +6,7 @@ #include <common.h> #include <asm/arch/clock_manager.h> -#include "qts/pll_config.h" +#include <qts/pll_config.h> #define MAIN_VCO_BASE ( \ (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ diff --git a/board/altera/socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c index cd97cc5..31cc7de 100644 --- a/board/altera/socfpga/wrap_sdram_config.c +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c @@ -7,13 +7,9 @@ #include <common.h> #include <errno.h> #include <asm/arch/sdram.h> -/* QTS output file. */ -#include "qts/sdram_config.h" -#include "qts/sequencer_auto_ac_init.h" -#include "qts/sequencer_auto_inst_init.h" -#include "qts/sequencer_auto.h" -#include "qts/sequencer_defines.h" +/* Board-specific header. */ +#include <qts/sdram_config.h> static const struct socfpga_sdram_config sdram_config = { .ctrl_cfg = diff --git a/board/altera/arria5-socdk/MAINTAINERS b/board/altera/arria5-socdk/MAINTAINERS new file mode 100644 index 0000000..30f2477 --- /dev/null +++ b/board/altera/arria5-socdk/MAINTAINERS @@ -0,0 +1,7 @@ +SOCFPGA BOARD +M: Dinh Nguyen <dinguyen@altera.com> +M: Chin-Liang See <clsee@altera.com> +S: Maintained +F: board/altera/arria5-socdk/ +F: include/configs/socfpga_arria5.h +F: configs/socfpga_arria5_defconfig diff --git a/board/altera/socfpga/Makefile b/board/altera/arria5-socdk/Makefile index 5a15c71..86f9b78 100644 --- a/board/altera/socfpga/Makefile +++ b/board/altera/arria5-socdk/Makefile @@ -6,6 +6,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := socfpga.o wrap_pll_config.o -obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \ - wrap_sdram_config.o +obj-y := socfpga.o diff --git a/board/altera/arria5-socdk/qts/iocsr_config.h b/board/altera/arria5-socdk/qts/iocsr_config.h new file mode 100644 index 0000000..e2bb4bb --- /dev/null +++ b/board/altera/arria5-socdk/qts/iocsr_config.h @@ -0,0 +1,696 @@ +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000060, + 0x00018060, + 0x06018060, + 0x00004000, + 0x0C0300C0, + 0x0C030000, + 0x00000030, + 0x00000000, + 0x00000000, + 0x00002000, + 0x00000000, + 0x00000000, + 0x06000000, + 0x00006018, + 0x01806018, + 0x00001000, + 0x0000C030, + 0x04000000, + 0x03000000, + 0x0000300C, + 0x00000000, + 0x00000800, + 0x00006018, + 0x01806000, + 0x01800000, + 0x00000006, + 0x00001806, + 0x00000400, + 0x0000300C, + 0x00C03000, + 0x00C00000, + 0x00000003, + 0x00000C03, + 0x00000200, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x00100000, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x000300C0, + 0x10000000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x06018060, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x03000000, + 0x0000300C, + 0x0000300C, + 0x00000800, + 0x00006018, + 0x01806000, + 0x01800000, + 0x00000006, + 0x00002000, + 0x00000400, + 0x0000300C, + 0x01000000, + 0x00000000, + 0x00000004, + 0x00000C03, + 0x00000200, + 0x00001806, + 0x00800000, + 0x00000000, + 0x00000002, + 0x00000800, + 0x00000100, + 0x00001000, + 0x00400000, + 0xC0300000, + 0x00000000, + 0x00000400, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x00100000, + 0x40000000, + 0x00000000, + 0x00000100, + 0x00040000, + 0x00008000, + 0x18060180, + 0x20000000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000000, + 0x00010000, + 0x00002000, + 0x10038060, + 0x00000000, + 0x00000000, + 0x00000020, + 0x01806018, + 0x00001000, + 0x00010000, + 0x04000000, + 0x03000000, + 0x0000801C, + 0x00004000, + 0x00000800, + 0x01806018, + 0x02000000, + 0x00000000, + 0x00000008, + 0x00002000, + 0x00000400, + 0x00C0300C, + 0x00C03000, + 0x00C00003, + 0x00000C03, + 0x00300C03, + 0x00000200, + 0x00601806, + 0x80601800, + 0x80600001, + 0x80000601, + 0x00180601, + 0x00000100, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x2C820D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000050, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00A28, + 0xA20D0000, + 0x24906808, + 0x00A28340, + 0xD000001A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000050, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00040, + 0xA20D0002, + 0x24906808, + 0x00A28340, + 0xD005141A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC055F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x04510680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC055F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x8341D348, + 0x821A0124, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC055F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC055F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00481800, + 0x001A1A1A, + 0x085506A0, + 0x0000E1D4, + 0x045506A0, + 0x0000E1D4, + 0x085506A0, + 0x8000E1D4, + 0x00000200, + 0x00000004, + 0x04000000, + 0x00000009, + 0x00002410, + 0x00000040, + 0x41000000, + 0x00002082, + 0x00000350, + 0x000000DA, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x022A8350, + 0x000070EA, + 0x86000000, + 0x08000004, + 0x00000000, + 0x00482000, + 0x21800000, + 0x00101061, + 0x021541A8, + 0x00003875, + 0x011541A8, + 0x00003875, + 0x021541A8, + 0x20003875, + 0x00000080, + 0x00000001, + 0x41000000, + 0x00000002, + 0x00FF0904, + 0x00000000, + 0x90400000, + 0x00000820, + 0xC0000001, + 0xFFD602AF, + 0x86FFFFFF, + 0x0A0A78B4, + 0x000D020A, + 0x00006800, + 0x028A4320, + 0xEC2CB23D, + 0x8F5D1451, + 0xA47A88A2, + 0x0001A0E9, + 0x00410D00, + 0x40000068, + 0x3D000003, + 0x51EC2CB2, + 0xA28F5D14, + 0xE9A47A88, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000540, + 0x000003A8, + 0x08AA0D40, + 0x8001C3A8, + 0x0000007F, + 0x00000000, + 0x00004060, + 0xE1208000, + 0x0000001F, + 0x00004100, +}; + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/altera/arria5-socdk/qts/pinmux_config.h b/board/altera/arria5-socdk/qts/pinmux_config.h new file mode 100644 index 0000000..069d492 --- /dev/null +++ b/board/altera/arria5-socdk/qts/pinmux_config.h @@ -0,0 +1,219 @@ +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 3, /* EMACIO14 */ + 3, /* EMACIO15 */ + 3, /* EMACIO16 */ + 3, /* EMACIO17 */ + 3, /* EMACIO18 */ + 3, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 3, /* GENERALIO0 */ + 3, /* GENERALIO1 */ + 3, /* GENERALIO2 */ + 3, /* GENERALIO3 */ + 3, /* GENERALIO4 */ + 3, /* GENERALIO5 */ + 3, /* GENERALIO6 */ + 3, /* GENERALIO7 */ + 3, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 3, /* GENERALIO15 */ + 3, /* GENERALIO16 */ + 2, /* GENERALIO17 */ + 2, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 3, /* GENERALIO23 */ + 3, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 0, /* MIXED1IO0 */ + 0, /* MIXED1IO1 */ + 0, /* MIXED1IO2 */ + 0, /* MIXED1IO3 */ + 0, /* MIXED1IO4 */ + 0, /* MIXED1IO5 */ + 0, /* MIXED1IO6 */ + 0, /* MIXED1IO7 */ + 0, /* MIXED1IO8 */ + 0, /* MIXED1IO9 */ + 0, /* MIXED1IO10 */ + 0, /* MIXED1IO11 */ + 0, /* MIXED1IO12 */ + 0, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 3, /* MIXED2IO0 */ + 3, /* MIXED2IO1 */ + 3, /* MIXED2IO2 */ + 3, /* MIXED2IO3 */ + 3, /* MIXED2IO4 */ + 3, /* MIXED2IO5 */ + 3, /* MIXED2IO6 */ + 3, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/altera/arria5-socdk/qts/pll_config.h b/board/altera/arria5-socdk/qts/pll_config.h new file mode 100644 index 0000000..f6c5c95 --- /dev/null +++ b/board/altera/arria5-socdk/qts/pll_config.h @@ -0,0 +1,85 @@ +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 41 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 127 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1050000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 1066000000 +#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 +#define CONFIG_HPS_CLK_NAND_HZ 50000000 +#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 +#define CONFIG_HPS_CLK_QSPI_HZ 350000000 +#define CONFIG_HPS_CLK_SPIM_HZ 200000000 +#define CONFIG_HPS_CLK_CAN0_HZ 100000000 +#define CONFIG_HPS_CLK_CAN1_HZ 100000000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 0 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 2 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 + + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/altera/arria5-socdk/qts/sdram_config.h b/board/altera/arria5-socdk/qts/sdram_config.h new file mode 100644 index 0000000..e9fe60f --- /dev/null +++ b/board/altera/arria5-socdk/qts/sdram_config.h @@ -0,0 +1,340 @@ +/* + * Altera SoCFPGA SDRAM configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x48 +#define RW_MGR_GUARANTEED_READ 0x4B +#define RW_MGR_GUARANTEED_READ_CONT 0x53 +#define RW_MGR_GUARANTEED_WRITE 0x17 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7A +#define RW_MGR_IDLE_LOOP2 0x79 +#define RW_MGR_INIT_RESET_0_CKE_0 0x6E +#define RW_MGR_INIT_RESET_1_CKE_0 0x73 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x21 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x58 +#define RW_MGR_READ_B2B_WAIT1 0x60 +#define RW_MGR_READ_B2B_WAIT2 0x6A +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7C +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 8 +#define CALIB_VFIFO_OFFSET 6 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 234 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 15 +#define IO_DQS_EN_DELAY_OFFSET 16 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 6 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 5 +#define RW_MGR_MEM_DATA_WIDTH 40 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5 +#define TINIT_CNTR0_VAL 132 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 132 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] ={ + 0x20700000, + 0x20780000, + 0x10080831, + 0x10080930, + 0x10090004, + 0x100a0008, + 0x100b0000, + 0x10380400, + 0x10080849, + 0x100808c8, + 0x100a0004, + 0x10090010, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] ={ + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/altera/socfpga/socfpga.c b/board/altera/arria5-socdk/socfpga.c index a1dbc49..a1dbc49 100644 --- a/board/altera/socfpga/socfpga.c +++ b/board/altera/arria5-socdk/socfpga.c diff --git a/board/altera/socfpga/MAINTAINERS b/board/altera/cyclone5-socdk/MAINTAINERS index 0482581..f218ca4 100644 --- a/board/altera/socfpga/MAINTAINERS +++ b/board/altera/cyclone5-socdk/MAINTAINERS @@ -2,7 +2,7 @@ SOCFPGA BOARD M: Dinh Nguyen <dinguyen@altera.com> M: Chin-Liang See <clsee@altera.com> S: Maintained -F: board/altera/socfpga/ +F: board/altera/cyclone5-socdk/ F: include/configs/socfpga_cyclone5.h F: configs/socfpga_cyclone5_defconfig diff --git a/board/altera/cyclone5-socdk/Makefile b/board/altera/cyclone5-socdk/Makefile new file mode 100644 index 0000000..86f9b78 --- /dev/null +++ b/board/altera/cyclone5-socdk/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2010, Thomas Chou <thomas@wytron.com.tw> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := socfpga.o diff --git a/board/altera/cyclone5-socdk/qts/iocsr_config.h b/board/altera/cyclone5-socdk/qts/iocsr_config.h new file mode 100644 index 0000000..49a4fee --- /dev/null +++ b/board/altera/cyclone5-socdk/qts/iocsr_config.h @@ -0,0 +1,660 @@ +/* + * Altera SoCFPGA IOCSR configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00020080, + 0x08020000, + 0x08000000, + 0x00018020, + 0x00000000, + 0x00004000, + 0x00010040, + 0x04010000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x00020000, + 0x02008000, + 0x02000000, + 0x00000008, + 0x00002008, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x000C0300, + 0x10040000, + 0x100000C0, + 0x00000040, + 0x00010040, + 0x00008000, + 0x00080000, + 0x18060000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x00010040, + 0x10000000, + 0x04000000, + 0x00000010, + 0x00004010, + 0x00002000, + 0x06008020, + 0x02008000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x00004010, + 0x01004000, + 0x01000000, + 0x00003004, + 0x00001004, + 0x00000800, + 0x00000000, + 0x00000000, + 0x00800000, + 0x00000002, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00401000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00600802, + 0x00000000, + 0x80200000, + 0x80000600, + 0x00000200, + 0x00000100, + 0x00300401, + 0xC0100400, + 0x40100000, + 0x40000300, + 0x000C0100, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x80040100, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C010040, + 0x00008000, + 0x18020080, + 0x00000000, + 0x08000000, + 0x00040020, + 0x06018060, + 0x00004000, + 0x0C010040, + 0x04010000, + 0x00000030, + 0x00000000, + 0x03004010, + 0x00002000, + 0x06008020, + 0x02008000, + 0x02000018, + 0x00006008, + 0x01802008, + 0x00001000, + 0x03004010, + 0x01004000, + 0x0100000C, + 0x00003004, + 0x00C01004, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x2C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000070, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00A28, + 0xA20D0000, + 0x24906808, + 0x00A28340, + 0xD000001A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000070, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x906808A2, + 0xA2834024, + 0x05141A00, + 0x808A20D0, + 0x34024906, + 0x01A00040, + 0xA20D0002, + 0x24906808, + 0x00A28340, + 0xD005141A, + 0x06808A20, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x000001C1, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x04510680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x8341D348, + 0x821A0124, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A810, + 0xAA0D4000, + 0x01C3A808, + 0xAA0D4000, + 0x01C3A810, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D404, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA04, + 0x2A835000, + 0x0070EA02, + 0x2A835000, + 0x0070EA04, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x40120800, + 0x00000070, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC255F80, + 0xF1C71C71, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xBA28A3D8, + 0xF511451E, + 0x0341D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD859647A, + 0x1EBA28A3, + 0x48F51145, + 0x000341D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875011, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x001A1A1A, + 0x085506A0, + 0x0000E1D4, + 0x045506A0, + 0x0000E1D4, + 0x085506A0, + 0x8000E1D4, + 0x00000200, + 0x00000004, + 0x04000000, + 0x00000009, + 0x00002410, + 0x00000040, + 0x41000000, + 0x00002082, + 0x00000350, + 0x000000DA, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x022A8350, + 0x000070EA, + 0x86000000, + 0x08000004, + 0x00000000, + 0x00482000, + 0x21800000, + 0x00101061, + 0x021541A8, + 0x00003875, + 0x011541A8, + 0x00003875, + 0x021541A8, + 0x20003875, + 0x00000080, + 0x00000001, + 0x41000000, + 0x00000002, + 0x00FF0904, + 0x00000000, + 0x90400000, + 0x00000820, + 0xC0000001, + 0x38D612AF, + 0x86F8E38E, + 0x0A0A78B4, + 0x000D020A, + 0x00006800, + 0x028A4320, + 0xEC2CB23D, + 0x8F5D1451, + 0xA47A88A2, + 0x0001A0E9, + 0x00410D00, + 0x40000068, + 0x3D000003, + 0x51EC2CB2, + 0xA28F5D14, + 0xE9A47A88, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000540, + 0x000003A8, + 0x08AA0D40, + 0x8001C3A8, + 0x0000007F, + 0x00000000, + 0x00004060, + 0xE1208000, + 0x0000001F, + 0x00004100, +}; + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h new file mode 100644 index 0000000..33cf1fd --- /dev/null +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -0,0 +1,219 @@ +/* + * Altera SoCFPGA PinMux configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 3, /* EMACIO0 */ + 3, /* EMACIO1 */ + 3, /* EMACIO2 */ + 3, /* EMACIO3 */ + 3, /* EMACIO4 */ + 3, /* EMACIO5 */ + 3, /* EMACIO6 */ + 3, /* EMACIO7 */ + 3, /* EMACIO8 */ + 3, /* EMACIO9 */ + 3, /* EMACIO10 */ + 3, /* EMACIO11 */ + 3, /* EMACIO12 */ + 3, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 3, /* FLASHIO4 */ + 3, /* FLASHIO5 */ + 3, /* FLASHIO6 */ + 3, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 0, /* GENERALIO3 */ + 0, /* GENERALIO4 */ + 1, /* GENERALIO5 */ + 1, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 2, /* GENERALIO13 */ + 2, /* GENERALIO14 */ + 0, /* GENERALIO15 */ + 0, /* GENERALIO16 */ + 2, /* GENERALIO17 */ + 2, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 0, /* MIXED1IO0 */ + 1, /* MIXED1IO1 */ + 1, /* MIXED1IO2 */ + 1, /* MIXED1IO3 */ + 1, /* MIXED1IO4 */ + 0, /* MIXED1IO5 */ + 0, /* MIXED1IO6 */ + 0, /* MIXED1IO7 */ + 1, /* MIXED1IO8 */ + 1, /* MIXED1IO9 */ + 1, /* MIXED1IO10 */ + 1, /* MIXED1IO11 */ + 0, /* MIXED1IO12 */ + 0, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 1, /* MIXED1IO15 */ + 1, /* MIXED1IO16 */ + 1, /* MIXED1IO17 */ + 1, /* MIXED1IO18 */ + 0, /* MIXED1IO19 */ + 0, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h new file mode 100644 index 0000000..3d621ed --- /dev/null +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -0,0 +1,85 @@ +/* + * Altera SoCFPGA Clock and PLL configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CONFIG_HPS_DBCTRL_STAYOSC1 1 + +#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79 +#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1 +#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 +#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79 +#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CONFIG_HPS_CLK_OSC1_HZ 25000000 +#define CONFIG_HPS_CLK_OSC2_HZ 25000000 +#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 +#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 +#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 +#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 +#define CONFIG_HPS_CLK_NAND_HZ 50000000 +#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 +#define CONFIG_HPS_CLK_QSPI_HZ 400000000 +#define CONFIG_HPS_CLK_SPIM_HZ 200000000 +#define CONFIG_HPS_CLK_CAN0_HZ 100000000 +#define CONFIG_HPS_CLK_CAN1_HZ 100000000 +#define CONFIG_HPS_CLK_GPIODB_HZ 32000 +#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 +#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 + +#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 + + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h b/board/altera/cyclone5-socdk/qts/sdram_config.h new file mode 100644 index 0000000..37c1476 --- /dev/null +++ b/board/altera/cyclone5-socdk/qts/sdram_config.h @@ -0,0 +1,342 @@ +/* + * Altera SoCFPGA SDRAM configuration + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x48 +#define RW_MGR_GUARANTEED_READ 0x4B +#define RW_MGR_GUARANTEED_READ_CONT 0x53 +#define RW_MGR_GUARANTEED_WRITE 0x17 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7C +#define RW_MGR_IDLE_LOOP2 0x7B +#define RW_MGR_INIT_RESET_0_CKE_0 0x6E +#define RW_MGR_INIT_RESET_1_CKE_0 0x73 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x21 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x58 +#define RW_MGR_READ_B2B_WAIT1 0x60 +#define RW_MGR_READ_B2B_WAIT2 0x6A +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7E +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 7 +#define CALIB_VFIFO_OFFSET 5 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 6 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 5 +#define RW_MGR_MEM_DATA_WIDTH 40 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5 +#define TINIT_CNTR0_VAL 132 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 132 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] ={ + 0x20700000, + 0x20780000, + 0x10080431, + 0x10080530, + 0x10090004, + 0x100a0008, + 0x100b0000, + 0x10380400, + 0x10080449, + 0x100804c8, + 0x100a0004, + 0x10090010, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] ={ + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x0, + 0xa000, + 0x8000, + 0x80000, + 0x80, + 0x80, + 0x80, + 0x80, + 0xa080, + 0x8080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/board/altera/cyclone5-socdk/socfpga.c b/board/altera/cyclone5-socdk/socfpga.c new file mode 100644 index 0000000..a1dbc49 --- /dev/null +++ b/board/altera/cyclone5-socdk/socfpga.c @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2012 Altera Corporation <www.altera.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/reset_manager.h> +#include <asm/io.h> + +#include <usb.h> +#include <usb/s3c_udc.h> +#include <usb_mass_storage.h> + +#include <micrel.h> +#include <netdev.h> +#include <phy.h> + +DECLARE_GLOBAL_DATA_PTR; + +void s_init(void) {} + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + /* Address of boot parameters for ATAG (if ATAG is used) */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +/* + * PHY configuration + */ +#ifdef CONFIG_PHY_MICREL_KSZ9021 +int board_phy_config(struct phy_device *phydev) +{ + int ret; + /* + * These skew settings for the KSZ9021 ethernet phy is required for ethernet + * to work reliably on most flavors of cyclone5 boards. + */ + ret = ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, + 0x0); + if (ret) + return ret; + + ret = ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, + 0x0); + if (ret) + return ret; + + ret = ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, + 0xf0f0); + if (ret) + return ret; + + if (phydev->drv->config) + return phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_USB_GADGET +struct s3c_plat_otg_data socfpga_otg_data = { + .regs_otg = CONFIG_USB_DWC2_REG_ADDR, + .usb_gusbcfg = 0x1417, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + return s3c_udc_probe(&socfpga_otg_data); +} + +int g_dnl_board_usb_cable_connected(void) +{ + return 1; +} +#endif diff --git a/board/altera/socfpga/qts/iocsr_config.c b/board/altera/socfpga/qts/iocsr_config.c deleted file mode 100644 index 3b202b5..0000000 --- a/board/altera/socfpga/qts/iocsr_config.c +++ /dev/null @@ -1,1345 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2012-2014. All rights reserved - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* This file is generated by Preloader Generator */ - -#include "iocsr_config.h" - -#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 -const unsigned long iocsr_scan_chain0_table[(( - CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { - 0x00000000, - 0x00000000, - 0x0FF00000, - 0xC0000000, - 0x0000003F, - 0x00008000, - 0x00020080, - 0x08020000, - 0x08000000, - 0x00018020, - 0x00000000, - 0x00004000, - 0x00010040, - 0x04010000, - 0x04000000, - 0x00000010, - 0x00004010, - 0x00002000, - 0x00020000, - 0x02008000, - 0x02000000, - 0x00000008, - 0x00002008, - 0x00001000, -}; - -const unsigned long iocsr_scan_chain1_table[(( - CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { - 0x000C0300, - 0x10040000, - 0x100000C0, - 0x00000040, - 0x00010040, - 0x00008000, - 0x00080000, - 0x18060000, - 0x18000000, - 0x00000060, - 0x00018060, - 0x00004000, - 0x00010040, - 0x10000000, - 0x04000000, - 0x00000010, - 0x00004010, - 0x00002000, - 0x06008020, - 0x02008000, - 0x01FE0000, - 0xF8000000, - 0x00000007, - 0x00001000, - 0x00004010, - 0x01004000, - 0x01000000, - 0x00003004, - 0x00001004, - 0x00000800, - 0x00000000, - 0x00000000, - 0x00800000, - 0x00000002, - 0x00002000, - 0x00000400, - 0x00000000, - 0x00401000, - 0x00000003, - 0x00000000, - 0x00000000, - 0x00000200, - 0x00600802, - 0x00000000, - 0x80200000, - 0x80000600, - 0x00000200, - 0x00000100, - 0x00300401, - 0xC0100400, - 0x40100000, - 0x40000300, - 0x000C0100, - 0x00000080, -}; - -const unsigned long iocsr_scan_chain2_table[(( - CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { - 0x80040100, - 0x00000000, - 0x0FF00000, - 0x00000000, - 0x0C010040, - 0x00008000, - 0x18020080, - 0x00000000, - 0x08000000, - 0x00040020, - 0x06018060, - 0x00004000, - 0x0C010040, - 0x04010000, - 0x00000030, - 0x00000000, - 0x03004010, - 0x00002000, - 0x06008020, - 0x02008000, - 0x02000018, - 0x00006008, - 0x01802008, - 0x00001000, - 0x03004010, - 0x01004000, - 0x0100000C, - 0x00003004, - 0x00C01004, - 0x00000800, -}; - -const unsigned long iocsr_scan_chain3_table[(( - CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { - 0x2C420D80, - 0x082000FF, - 0x0A804001, - 0x07900000, - 0x08020000, - 0x00100000, - 0x0A800000, - 0x07900000, - 0x08020000, - 0x00100000, - 0xC8800000, - 0x00003001, - 0x00C00722, - 0x00000000, - 0x00000021, - 0x82000004, - 0x05400000, - 0x03C80000, - 0x04010000, - 0x00080000, - 0x05400000, - 0x03C80000, - 0x05400000, - 0x03C80000, - 0xE4400000, - 0x00001800, - 0x00600391, - 0x800E4400, - 0x00000001, - 0x40000002, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x72200000, - 0x80000C00, - 0x003001C8, - 0xC0072200, - 0x1C880000, - 0x20000300, - 0x00040000, - 0x50670000, - 0x00000070, - 0x24590000, - 0x00001000, - 0xA0000034, - 0x0D000001, - 0x906808A2, - 0xA2834024, - 0x05141A00, - 0x808A20D0, - 0x34024906, - 0x01A00A28, - 0xA20D0000, - 0x24906808, - 0x00A28340, - 0xD000001A, - 0x06808A20, - 0x10040000, - 0x00200000, - 0x10040000, - 0x00200000, - 0x15000000, - 0x0F200000, - 0x15000000, - 0x0F200000, - 0x01FE0000, - 0x00000000, - 0x01800E44, - 0x00391000, - 0x007F8006, - 0x00000000, - 0x0A800001, - 0x07900000, - 0x0A800000, - 0x07900000, - 0x0A800000, - 0x07900000, - 0x08020000, - 0x00100000, - 0xC8800000, - 0x00003001, - 0x00C00722, - 0x00000FF0, - 0x72200000, - 0x80000C00, - 0x05400000, - 0x02480000, - 0x04000000, - 0x00080000, - 0x05400000, - 0x03C80000, - 0x05400000, - 0x03C80000, - 0x6A1C0000, - 0x00001800, - 0x00600391, - 0x800E4400, - 0x1A870001, - 0x40000600, - 0x02A00040, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x72200000, - 0x80000C00, - 0x003001C8, - 0xC0072200, - 0x1C880000, - 0x20000300, - 0x00040000, - 0x50670000, - 0x00000070, - 0x24590000, - 0x00001000, - 0xA0000034, - 0x0D000001, - 0x906808A2, - 0xA2834024, - 0x05141A00, - 0x808A20D0, - 0x34024906, - 0x01A00040, - 0xA20D0002, - 0x24906808, - 0x00A28340, - 0xD005141A, - 0x06808A20, - 0x10040000, - 0x00200000, - 0x10040000, - 0x00200000, - 0x15000000, - 0x0F200000, - 0x15000000, - 0x0F200000, - 0x01FE0000, - 0x00000000, - 0x01800E44, - 0x00391000, - 0x007F8006, - 0x00000000, - 0x99300001, - 0x34343400, - 0xAA0D4000, - 0x01C3A810, - 0xAA0D4000, - 0x01C3A808, - 0xAA0D4000, - 0x01C3A810, - 0x00040100, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x000001C1, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x0002A000, - 0x0001E400, - 0x5506A000, - 0x00E1D404, - 0x00000000, - 0xC880090C, - 0x00003001, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA04, - 0x2A835000, - 0x0070EA02, - 0x2A835000, - 0x0070EA04, - 0x00010040, - 0x00000200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00002000, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC255F80, - 0xF1C71C71, - 0x14F3690D, - 0x1A041414, - 0x00D00000, - 0x14864000, - 0x59647A05, - 0xBA28A3D8, - 0xF511451E, - 0x0341D348, - 0x821A0000, - 0x0000D000, - 0x04510680, - 0xD859647A, - 0x1EBA28A3, - 0x48F51145, - 0x000341D3, - 0x00080200, - 0x00001000, - 0x00080200, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875011, - 0x10000000, - 0x00000000, - 0x0080C000, - 0x41000000, - 0x00003FC2, - 0x00820000, - 0xAA0D4000, - 0x01C3A810, - 0xAA0D4000, - 0x01C3A808, - 0xAA0D4000, - 0x01C3A810, - 0x00040100, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x00008000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x00020080, - 0x00000400, - 0x5506A000, - 0x00E1D404, - 0x00000000, - 0x0000090C, - 0x00000010, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA04, - 0x2A835000, - 0x0070EA02, - 0x2A835000, - 0x0070EA04, - 0x00015000, - 0x0000F200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00600391, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC255F80, - 0xF1C71C71, - 0x14F3690D, - 0x1A041414, - 0x00D00000, - 0x14864000, - 0x59647A05, - 0xBA28A3D8, - 0xF511451E, - 0x8341D348, - 0x821A0124, - 0x0000D000, - 0x00000680, - 0xD859647A, - 0x1EBA28A3, - 0x48F51145, - 0x000341D3, - 0x00080200, - 0x00001000, - 0x00080200, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875011, - 0x10000000, - 0x00000000, - 0x0080C000, - 0x41000000, - 0x04000002, - 0x00820000, - 0xAA0D4000, - 0x01C3A810, - 0xAA0D4000, - 0x01C3A808, - 0xAA0D4000, - 0x01C3A810, - 0x00040100, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x00008000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x0002A000, - 0x0001E400, - 0x5506A000, - 0x00E1D404, - 0x00000000, - 0xC880090C, - 0x00003001, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA04, - 0x2A835000, - 0x0070EA02, - 0x2A835000, - 0x0070EA04, - 0x00010040, - 0x00000200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00002000, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC255F80, - 0xF1C71C71, - 0x14F3690D, - 0x1A041414, - 0x00D00000, - 0x14864000, - 0x59647A05, - 0xBA28A3D8, - 0xF511451E, - 0x0341D348, - 0x821A0000, - 0x0000D000, - 0x00000680, - 0xD859647A, - 0x1EBA28A3, - 0x48F51145, - 0x000341D3, - 0x00080200, - 0x00001000, - 0x00080200, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875011, - 0x10000000, - 0x00000000, - 0x0080C000, - 0x41000000, - 0x04000002, - 0x00820000, - 0xAA0D4000, - 0x01C3A810, - 0xAA0D4000, - 0x01C3A808, - 0xAA0D4000, - 0x01C3A810, - 0x00040100, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x00008000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x00020080, - 0x00000400, - 0x5506A000, - 0x00E1D404, - 0x00000000, - 0x0000090C, - 0x00000010, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA04, - 0x2A835000, - 0x0070EA02, - 0x2A835000, - 0x0070EA04, - 0x00010040, - 0x00000200, - 0x00000000, - 0x00000482, - 0x40120800, - 0x00000070, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC255F80, - 0xF1C71C71, - 0x14F1690D, - 0x1A041414, - 0x00D00000, - 0x14864000, - 0x59647A05, - 0xBA28A3D8, - 0xF511451E, - 0x0341D348, - 0x821A0000, - 0x0000D000, - 0x00000680, - 0xD859647A, - 0x1EBA28A3, - 0x48F51145, - 0x000341D3, - 0x00080200, - 0x00001000, - 0x00080200, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875011, - 0x10000000, - 0x00000000, - 0x0080C000, - 0x41000000, - 0x04000002, - 0x00820000, - 0x00489800, - 0x001A1A1A, - 0x085506A0, - 0x0000E1D4, - 0x045506A0, - 0x0000E1D4, - 0x085506A0, - 0x8000E1D4, - 0x00000200, - 0x00000004, - 0x04000000, - 0x00000009, - 0x00002410, - 0x00000040, - 0x41000000, - 0x00002082, - 0x00000350, - 0x000000DA, - 0x00000100, - 0x40000002, - 0x00000100, - 0x00000002, - 0x022A8350, - 0x000070EA, - 0x86000000, - 0x08000004, - 0x00000000, - 0x00482000, - 0x21800000, - 0x00101061, - 0x021541A8, - 0x00003875, - 0x011541A8, - 0x00003875, - 0x021541A8, - 0x20003875, - 0x00000080, - 0x00000001, - 0x41000000, - 0x00000002, - 0x00FF0904, - 0x00000000, - 0x90400000, - 0x00000820, - 0xC0000001, - 0x38D612AF, - 0x86F8E38E, - 0x0A0A78B4, - 0x000D020A, - 0x00006800, - 0x028A4320, - 0xEC2CB23D, - 0x8F5D1451, - 0xA47A88A2, - 0x0001A0E9, - 0x00410D00, - 0x40000068, - 0x3D000003, - 0x51EC2CB2, - 0xA28F5D14, - 0xE9A47A88, - 0x000001A0, - 0x00000401, - 0x00000008, - 0x00000401, - 0x00000008, - 0x00000540, - 0x000003A8, - 0x08AA0D40, - 0x8001C3A8, - 0x0000007F, - 0x00000000, - 0x00004060, - 0xE1208000, - 0x0000001F, - 0x00004100, -}; -#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */ - -#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 -const unsigned long iocsr_scan_chain0_table[(( - CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00008000, - 0x00060180, - 0x18060000, - 0x18000060, - 0x00018060, - 0x06018060, - 0x00004000, - 0x0C0300C0, - 0x0C030000, - 0x00000030, - 0x00000000, - 0x00000000, - 0x00002000, - 0x00000000, - 0x00000000, - 0x06000000, - 0x00006018, - 0x01806018, - 0x00001000, - 0x0000C030, - 0x04000000, - 0x03000000, - 0x0000300C, - 0x00000000, - 0x00000800, - 0x00006018, - 0x01806000, - 0x01800000, - 0x00000006, - 0x00001806, - 0x00000400, - 0x0000300C, - 0x00C03000, - 0x00C00000, - 0x00000003, - 0x00000C03, - 0x00000200, -}; - -const unsigned long iocsr_scan_chain1_table[(( - CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)] = { - 0x00100000, - 0x300C0000, - 0x300000C0, - 0x000000C0, - 0x000300C0, - 0x00008000, - 0x00060180, - 0x18060000, - 0x18000000, - 0x00000060, - 0x00018060, - 0x00004000, - 0x000300C0, - 0x10000000, - 0x0C000000, - 0x00000030, - 0x0000C030, - 0x00002000, - 0x06018060, - 0x06018000, - 0x01FE0000, - 0xF8000000, - 0x00000007, - 0x00001000, - 0x0000C030, - 0x0300C000, - 0x03000000, - 0x0000300C, - 0x0000300C, - 0x00000800, - 0x00006018, - 0x01806000, - 0x01800000, - 0x00000006, - 0x00002000, - 0x00000400, - 0x0000300C, - 0x01000000, - 0x00000000, - 0x00000004, - 0x00000C03, - 0x00000200, - 0x00001806, - 0x00800000, - 0x00000000, - 0x00000002, - 0x00000800, - 0x00000100, - 0x00001000, - 0x00400000, - 0xC0300000, - 0x00000000, - 0x00000400, - 0x00000080, -}; - -const unsigned long iocsr_scan_chain2_table[(( - CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)] = { - 0x00100000, - 0x40000000, - 0x00000000, - 0x00000100, - 0x00040000, - 0x00008000, - 0x18060180, - 0x20000000, - 0x00000000, - 0x00000080, - 0x00020000, - 0x00004000, - 0x00040000, - 0x10000000, - 0x00000000, - 0x00000000, - 0x00010000, - 0x00002000, - 0x10038060, - 0x00000000, - 0x00000000, - 0x00000020, - 0x01806018, - 0x00001000, - 0x00010000, - 0x04000000, - 0x03000000, - 0x0000801C, - 0x00004000, - 0x00000800, - 0x01806018, - 0x02000000, - 0x00000000, - 0x00000008, - 0x00002000, - 0x00000400, - 0x00C0300C, - 0x00C03000, - 0x00C00003, - 0x00000C03, - 0x00300C03, - 0x00000200, - 0x00601806, - 0x80601800, - 0x80600001, - 0x80000601, - 0x00180601, - 0x00000100, -}; - -const unsigned long iocsr_scan_chain3_table[(( - CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)] = { - 0x2C820D80, - 0x082000FF, - 0x0A804001, - 0x07900000, - 0x08020000, - 0x00100000, - 0x0A800000, - 0x07900000, - 0x08020000, - 0x00100000, - 0xC8800000, - 0x00003001, - 0x00C00722, - 0x00000000, - 0x00000021, - 0x82000004, - 0x05400000, - 0x03C80000, - 0x04010000, - 0x00080000, - 0x05400000, - 0x03C80000, - 0x05400000, - 0x03C80000, - 0xE4400000, - 0x00001800, - 0x00600391, - 0x800E4400, - 0x00000001, - 0x40000002, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x72200000, - 0x80000C00, - 0x003001C8, - 0xC0072200, - 0x1C880000, - 0x20000300, - 0x00040000, - 0x50670000, - 0x00000050, - 0x24590000, - 0x00001000, - 0xA0000034, - 0x0D000001, - 0x906808A2, - 0xA2834024, - 0x05141A00, - 0x808A20D0, - 0x34024906, - 0x01A00A28, - 0xA20D0000, - 0x24906808, - 0x00A28340, - 0xD000001A, - 0x06808A20, - 0x10040000, - 0x00200000, - 0x10040000, - 0x00200000, - 0x15000000, - 0x0F200000, - 0x15000000, - 0x0F200000, - 0x01FE0000, - 0x00000000, - 0x01800E44, - 0x00391000, - 0x007F8006, - 0x00000000, - 0x0A800001, - 0x07900000, - 0x0A800000, - 0x07900000, - 0x0A800000, - 0x07900000, - 0x08020000, - 0x00100000, - 0xC8800000, - 0x00003001, - 0x00C00722, - 0x00000FF0, - 0x72200000, - 0x80000C00, - 0x05400000, - 0x02480000, - 0x04000000, - 0x00080000, - 0x05400000, - 0x03C80000, - 0x05400000, - 0x03C80000, - 0x6A1C0000, - 0x00001800, - 0x00600391, - 0x800E4400, - 0x1A870001, - 0x40000600, - 0x02A00040, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x02A00000, - 0x01E40000, - 0x72200000, - 0x80000C00, - 0x003001C8, - 0xC0072200, - 0x1C880000, - 0x20000300, - 0x00040000, - 0x50670000, - 0x00000050, - 0x24590000, - 0x00001000, - 0xA0000034, - 0x0D000001, - 0x906808A2, - 0xA2834024, - 0x05141A00, - 0x808A20D0, - 0x34024906, - 0x01A00040, - 0xA20D0002, - 0x24906808, - 0x00A28340, - 0xD005141A, - 0x06808A20, - 0x10040000, - 0x00200000, - 0x10040000, - 0x00200000, - 0x15000000, - 0x0F200000, - 0x15000000, - 0x0F200000, - 0x01FE0000, - 0x00000000, - 0x01800E44, - 0x00391000, - 0x007F8006, - 0x00000000, - 0x99300001, - 0x34343400, - 0xAA0D4000, - 0x01C3A810, - 0xAA0D4000, - 0x01C3A808, - 0xAA0D4000, - 0x01C3A810, - 0x00040100, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x01000000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x0002A000, - 0x0001E400, - 0x5506A000, - 0x00E1D404, - 0x00000000, - 0xC880090C, - 0x00003001, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA04, - 0x2A835000, - 0x0070EA02, - 0x2A835000, - 0x0070EA04, - 0x00010040, - 0x00000200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00002000, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC055F80, - 0xFFFFFFFF, - 0x14F3690D, - 0x1A041414, - 0x00D00000, - 0x14864000, - 0x59647A05, - 0xBA28A3D8, - 0xF511451E, - 0x0341D348, - 0x821A0000, - 0x0000D000, - 0x04510680, - 0xD859647A, - 0x1EBA28A3, - 0x48F51145, - 0x000341D3, - 0x00080200, - 0x00001000, - 0x00080200, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875011, - 0x10000000, - 0x00000000, - 0x0080C000, - 0x41000000, - 0x00003FC2, - 0x00820000, - 0xAA0D4000, - 0x01C3A810, - 0xAA0D4000, - 0x01C3A808, - 0xAA0D4000, - 0x01C3A810, - 0x00040100, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x00008000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x00020080, - 0x00000400, - 0x5506A000, - 0x00E1D404, - 0x00000000, - 0x0000090C, - 0x00000010, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA04, - 0x2A835000, - 0x0070EA02, - 0x2A835000, - 0x0070EA04, - 0x00015000, - 0x0000F200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00600391, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC055F80, - 0xFFFFFFFF, - 0x14F3690D, - 0x1A041414, - 0x00D00000, - 0x14864000, - 0x59647A05, - 0xBA28A3D8, - 0xF511451E, - 0x8341D348, - 0x821A0124, - 0x0000D000, - 0x00000680, - 0xD859647A, - 0x1EBA28A3, - 0x48F51145, - 0x000341D3, - 0x00080200, - 0x00001000, - 0x00080200, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875011, - 0x10000000, - 0x00000000, - 0x0080C000, - 0x41000000, - 0x04000002, - 0x00820000, - 0xAA0D4000, - 0x01C3A810, - 0xAA0D4000, - 0x01C3A808, - 0xAA0D4000, - 0x01C3A810, - 0x00040100, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x00008000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x0002A000, - 0x0001E400, - 0x5506A000, - 0x00E1D404, - 0x00000000, - 0xC880090C, - 0x00003001, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA04, - 0x2A835000, - 0x0070EA02, - 0x2A835000, - 0x0070EA04, - 0x00010040, - 0x00000200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00002000, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC055F80, - 0xFFFFFFFF, - 0x14F3690D, - 0x1A041414, - 0x00D00000, - 0x14864000, - 0x59647A05, - 0xBA28A3D8, - 0xF511451E, - 0x0341D348, - 0x821A0000, - 0x0000D000, - 0x00000680, - 0xD859647A, - 0x1EBA28A3, - 0x48F51145, - 0x000341D3, - 0x00080200, - 0x00001000, - 0x00080200, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875011, - 0x10000000, - 0x00000000, - 0x0080C000, - 0x41000000, - 0x04000002, - 0x00820000, - 0xAA0D4000, - 0x01C3A810, - 0xAA0D4000, - 0x01C3A808, - 0xAA0D4000, - 0x01C3A810, - 0x00040100, - 0x00000800, - 0x00000000, - 0x00001208, - 0x00482000, - 0x00008000, - 0x00000000, - 0x00410482, - 0x0006A000, - 0x0001B400, - 0x00020000, - 0x00000400, - 0x00020080, - 0x00000400, - 0x5506A000, - 0x00E1D404, - 0x00000000, - 0x0000090C, - 0x00000010, - 0x90400000, - 0x00000000, - 0x2020C243, - 0x2A835000, - 0x0070EA04, - 0x2A835000, - 0x0070EA02, - 0x2A835000, - 0x0070EA04, - 0x00010040, - 0x00000200, - 0x00000000, - 0x00000482, - 0x00120800, - 0x00400000, - 0x80000000, - 0x00104120, - 0x00000200, - 0xAC055F80, - 0xFFFFFFFF, - 0x14F1690D, - 0x1A041414, - 0x00D00000, - 0x14864000, - 0x59647A05, - 0xBA28A3D8, - 0xF511451E, - 0x0341D348, - 0x821A0000, - 0x0000D000, - 0x00000680, - 0xD859647A, - 0x1EBA28A3, - 0x48F51145, - 0x000341D3, - 0x00080200, - 0x00001000, - 0x00080200, - 0x00001000, - 0x000A8000, - 0x00075000, - 0x541A8000, - 0x03875011, - 0x10000000, - 0x00000000, - 0x0080C000, - 0x41000000, - 0x04000002, - 0x00820000, - 0x00481800, - 0x001A1A1A, - 0x085506A0, - 0x0000E1D4, - 0x045506A0, - 0x0000E1D4, - 0x085506A0, - 0x8000E1D4, - 0x00000200, - 0x00000004, - 0x04000000, - 0x00000009, - 0x00002410, - 0x00000040, - 0x41000000, - 0x00002082, - 0x00000350, - 0x000000DA, - 0x00000100, - 0x40000002, - 0x00000100, - 0x00000002, - 0x022A8350, - 0x000070EA, - 0x86000000, - 0x08000004, - 0x00000000, - 0x00482000, - 0x21800000, - 0x00101061, - 0x021541A8, - 0x00003875, - 0x011541A8, - 0x00003875, - 0x021541A8, - 0x20003875, - 0x00000080, - 0x00000001, - 0x41000000, - 0x00000002, - 0x00FF0904, - 0x00000000, - 0x90400000, - 0x00000820, - 0xC0000001, - 0xFFD602AF, - 0x86FFFFFF, - 0x0A0A78B4, - 0x000D020A, - 0x00006800, - 0x028A4320, - 0xEC2CB23D, - 0x8F5D1451, - 0xA47A88A2, - 0x0001A0E9, - 0x00410D00, - 0x40000068, - 0x3D000003, - 0x51EC2CB2, - 0xA28F5D14, - 0xE9A47A88, - 0x000001A0, - 0x00000401, - 0x00000008, - 0x00000401, - 0x00000008, - 0x00000540, - 0x000003A8, - 0x08AA0D40, - 0x8001C3A8, - 0x0000007F, - 0x00000000, - 0x00004060, - 0xE1208000, - 0x0000001F, - 0x00004100, -}; -#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */ diff --git a/board/altera/socfpga/qts/iocsr_config.h b/board/altera/socfpga/qts/iocsr_config.h deleted file mode 100644 index d1c9b0d..0000000 --- a/board/altera/socfpga/qts/iocsr_config.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2012-2014. All rights reserved - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* This file is generated by Preloader Generator */ - -#ifndef _PRELOADER_IOCSR_CONFIG_H_ -#define _PRELOADER_IOCSR_CONFIG_H_ - -#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (764) -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (955) -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) -#endif - -#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH (1337) -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH (1719) -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH (1528) -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH (16766) -#endif - -#endif /*_PRELOADER_IOCSR_CONFIG_H_*/ diff --git a/board/altera/socfpga/qts/pinmux_config.c b/board/altera/socfpga/qts/pinmux_config.c deleted file mode 100644 index 7e7a184..0000000 --- a/board/altera/socfpga/qts/pinmux_config.c +++ /dev/null @@ -1,429 +0,0 @@ -/* This file is generated by Preloader Generator */ - -#include "pinmux_config.h" - -#ifdef CONFIG_TARGET_SOCFPGA_CYCLONE5 -/* pin mux configuration data */ -unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = { - 3, /* EMACIO0 */ - 3, /* EMACIO1 */ - 3, /* EMACIO2 */ - 3, /* EMACIO3 */ - 3, /* EMACIO4 */ - 3, /* EMACIO5 */ - 3, /* EMACIO6 */ - 3, /* EMACIO7 */ - 3, /* EMACIO8 */ - 3, /* EMACIO9 */ - 3, /* EMACIO10 */ - 3, /* EMACIO11 */ - 3, /* EMACIO12 */ - 3, /* EMACIO13 */ - 0, /* EMACIO14 */ - 0, /* EMACIO15 */ - 0, /* EMACIO16 */ - 0, /* EMACIO17 */ - 0, /* EMACIO18 */ - 0, /* EMACIO19 */ - 3, /* FLASHIO0 */ - 0, /* FLASHIO1 */ - 3, /* FLASHIO2 */ - 3, /* FLASHIO3 */ - 3, /* FLASHIO4 */ - 3, /* FLASHIO5 */ - 3, /* FLASHIO6 */ - 3, /* FLASHIO7 */ - 0, /* FLASHIO8 */ - 3, /* FLASHIO9 */ - 3, /* FLASHIO10 */ - 3, /* FLASHIO11 */ - 0, /* GENERALIO0 */ - 1, /* GENERALIO1 */ - 1, /* GENERALIO2 */ - 0, /* GENERALIO3 */ - 0, /* GENERALIO4 */ - 1, /* GENERALIO5 */ - 1, /* GENERALIO6 */ - 1, /* GENERALIO7 */ - 1, /* GENERALIO8 */ - 0, /* GENERALIO9 */ - 0, /* GENERALIO10 */ - 0, /* GENERALIO11 */ - 0, /* GENERALIO12 */ - 2, /* GENERALIO13 */ - 2, /* GENERALIO14 */ - 0, /* GENERALIO15 */ - 0, /* GENERALIO16 */ - 2, /* GENERALIO17 */ - 2, /* GENERALIO18 */ - 0, /* GENERALIO19 */ - 0, /* GENERALIO20 */ - 0, /* GENERALIO21 */ - 0, /* GENERALIO22 */ - 0, /* GENERALIO23 */ - 0, /* GENERALIO24 */ - 0, /* GENERALIO25 */ - 0, /* GENERALIO26 */ - 0, /* GENERALIO27 */ - 0, /* GENERALIO28 */ - 0, /* GENERALIO29 */ - 0, /* GENERALIO30 */ - 0, /* GENERALIO31 */ - 0, /* MIXED1IO0 */ - 1, /* MIXED1IO1 */ - 1, /* MIXED1IO2 */ - 1, /* MIXED1IO3 */ - 1, /* MIXED1IO4 */ - 0, /* MIXED1IO5 */ - 0, /* MIXED1IO6 */ - 0, /* MIXED1IO7 */ - 1, /* MIXED1IO8 */ - 1, /* MIXED1IO9 */ - 1, /* MIXED1IO10 */ - 1, /* MIXED1IO11 */ - 0, /* MIXED1IO12 */ - 0, /* MIXED1IO13 */ - 0, /* MIXED1IO14 */ - 1, /* MIXED1IO15 */ - 1, /* MIXED1IO16 */ - 1, /* MIXED1IO17 */ - 1, /* MIXED1IO18 */ - 0, /* MIXED1IO19 */ - 0, /* MIXED1IO20 */ - 0, /* MIXED1IO21 */ - 0, /* MIXED2IO0 */ - 0, /* MIXED2IO1 */ - 0, /* MIXED2IO2 */ - 0, /* MIXED2IO3 */ - 0, /* MIXED2IO4 */ - 0, /* MIXED2IO5 */ - 0, /* MIXED2IO6 */ - 0, /* MIXED2IO7 */ - 0, /* GPLINMUX48 */ - 0, /* GPLINMUX49 */ - 0, /* GPLINMUX50 */ - 0, /* GPLINMUX51 */ - 0, /* GPLINMUX52 */ - 0, /* GPLINMUX53 */ - 0, /* GPLINMUX54 */ - 0, /* GPLINMUX55 */ - 0, /* GPLINMUX56 */ - 0, /* GPLINMUX57 */ - 0, /* GPLINMUX58 */ - 0, /* GPLINMUX59 */ - 0, /* GPLINMUX60 */ - 0, /* GPLINMUX61 */ - 0, /* GPLINMUX62 */ - 0, /* GPLINMUX63 */ - 0, /* GPLINMUX64 */ - 0, /* GPLINMUX65 */ - 0, /* GPLINMUX66 */ - 0, /* GPLINMUX67 */ - 0, /* GPLINMUX68 */ - 0, /* GPLINMUX69 */ - 0, /* GPLINMUX70 */ - 1, /* GPLMUX0 */ - 1, /* GPLMUX1 */ - 1, /* GPLMUX2 */ - 1, /* GPLMUX3 */ - 1, /* GPLMUX4 */ - 1, /* GPLMUX5 */ - 1, /* GPLMUX6 */ - 1, /* GPLMUX7 */ - 1, /* GPLMUX8 */ - 1, /* GPLMUX9 */ - 1, /* GPLMUX10 */ - 1, /* GPLMUX11 */ - 1, /* GPLMUX12 */ - 1, /* GPLMUX13 */ - 1, /* GPLMUX14 */ - 1, /* GPLMUX15 */ - 1, /* GPLMUX16 */ - 1, /* GPLMUX17 */ - 1, /* GPLMUX18 */ - 1, /* GPLMUX19 */ - 1, /* GPLMUX20 */ - 1, /* GPLMUX21 */ - 1, /* GPLMUX22 */ - 1, /* GPLMUX23 */ - 1, /* GPLMUX24 */ - 1, /* GPLMUX25 */ - 1, /* GPLMUX26 */ - 1, /* GPLMUX27 */ - 1, /* GPLMUX28 */ - 1, /* GPLMUX29 */ - 1, /* GPLMUX30 */ - 1, /* GPLMUX31 */ - 1, /* GPLMUX32 */ - 1, /* GPLMUX33 */ - 1, /* GPLMUX34 */ - 1, /* GPLMUX35 */ - 1, /* GPLMUX36 */ - 1, /* GPLMUX37 */ - 1, /* GPLMUX38 */ - 1, /* GPLMUX39 */ - 1, /* GPLMUX40 */ - 1, /* GPLMUX41 */ - 1, /* GPLMUX42 */ - 1, /* GPLMUX43 */ - 1, /* GPLMUX44 */ - 1, /* GPLMUX45 */ - 1, /* GPLMUX46 */ - 1, /* GPLMUX47 */ - 1, /* GPLMUX48 */ - 1, /* GPLMUX49 */ - 1, /* GPLMUX50 */ - 1, /* GPLMUX51 */ - 1, /* GPLMUX52 */ - 1, /* GPLMUX53 */ - 1, /* GPLMUX54 */ - 1, /* GPLMUX55 */ - 1, /* GPLMUX56 */ - 1, /* GPLMUX57 */ - 1, /* GPLMUX58 */ - 1, /* GPLMUX59 */ - 1, /* GPLMUX60 */ - 1, /* GPLMUX61 */ - 1, /* GPLMUX62 */ - 1, /* GPLMUX63 */ - 1, /* GPLMUX64 */ - 1, /* GPLMUX65 */ - 1, /* GPLMUX66 */ - 1, /* GPLMUX67 */ - 1, /* GPLMUX68 */ - 1, /* GPLMUX69 */ - 1, /* GPLMUX70 */ - 0, /* NANDUSEFPGA */ - 0, /* UART0USEFPGA */ - 0, /* RGMII1USEFPGA */ - 0, /* SPIS0USEFPGA */ - 0, /* CAN0USEFPGA */ - 0, /* I2C0USEFPGA */ - 0, /* SDMMCUSEFPGA */ - 0, /* QSPIUSEFPGA */ - 0, /* SPIS1USEFPGA */ - 0, /* RGMII0USEFPGA */ - 0, /* UART1USEFPGA */ - 0, /* CAN1USEFPGA */ - 0, /* USB1USEFPGA */ - 0, /* I2C3USEFPGA */ - 0, /* I2C2USEFPGA */ - 0, /* I2C1USEFPGA */ - 0, /* SPIM1USEFPGA */ - 0, /* USB0USEFPGA */ - 0 /* SPIM0USEFPGA */ -}; -#endif /* CONFIG_TARGET_SOCFPGA_CYCLONE5 */ - -#ifdef CONFIG_TARGET_SOCFPGA_ARRIA5 -/* pin mux configuration data */ -unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = { - 0, /* EMACIO0 */ - 2, /* EMACIO1 */ - 2, /* EMACIO2 */ - 2, /* EMACIO3 */ - 2, /* EMACIO4 */ - 2, /* EMACIO5 */ - 2, /* EMACIO6 */ - 2, /* EMACIO7 */ - 2, /* EMACIO8 */ - 0, /* EMACIO9 */ - 2, /* EMACIO10 */ - 2, /* EMACIO11 */ - 2, /* EMACIO12 */ - 2, /* EMACIO13 */ - 3, /* EMACIO14 */ - 3, /* EMACIO15 */ - 3, /* EMACIO16 */ - 3, /* EMACIO17 */ - 3, /* EMACIO18 */ - 3, /* EMACIO19 */ - 3, /* FLASHIO0 */ - 0, /* FLASHIO1 */ - 3, /* FLASHIO2 */ - 3, /* FLASHIO3 */ - 0, /* FLASHIO4 */ - 0, /* FLASHIO5 */ - 0, /* FLASHIO6 */ - 0, /* FLASHIO7 */ - 0, /* FLASHIO8 */ - 3, /* FLASHIO9 */ - 3, /* FLASHIO10 */ - 3, /* FLASHIO11 */ - 3, /* GENERALIO0 */ - 3, /* GENERALIO1 */ - 3, /* GENERALIO2 */ - 3, /* GENERALIO3 */ - 3, /* GENERALIO4 */ - 3, /* GENERALIO5 */ - 3, /* GENERALIO6 */ - 3, /* GENERALIO7 */ - 3, /* GENERALIO8 */ - 0, /* GENERALIO9 */ - 0, /* GENERALIO10 */ - 0, /* GENERALIO11 */ - 0, /* GENERALIO12 */ - 0, /* GENERALIO13 */ - 0, /* GENERALIO14 */ - 3, /* GENERALIO15 */ - 3, /* GENERALIO16 */ - 2, /* GENERALIO17 */ - 2, /* GENERALIO18 */ - 0, /* GENERALIO19 */ - 0, /* GENERALIO20 */ - 0, /* GENERALIO21 */ - 0, /* GENERALIO22 */ - 3, /* GENERALIO23 */ - 3, /* GENERALIO24 */ - 0, /* GENERALIO25 */ - 0, /* GENERALIO26 */ - 0, /* GENERALIO27 */ - 0, /* GENERALIO28 */ - 0, /* GENERALIO29 */ - 0, /* GENERALIO30 */ - 0, /* GENERALIO31 */ - 0, /* MIXED1IO0 */ - 0, /* MIXED1IO1 */ - 0, /* MIXED1IO2 */ - 0, /* MIXED1IO3 */ - 0, /* MIXED1IO4 */ - 0, /* MIXED1IO5 */ - 0, /* MIXED1IO6 */ - 0, /* MIXED1IO7 */ - 0, /* MIXED1IO8 */ - 0, /* MIXED1IO9 */ - 0, /* MIXED1IO10 */ - 0, /* MIXED1IO11 */ - 0, /* MIXED1IO12 */ - 0, /* MIXED1IO13 */ - 0, /* MIXED1IO14 */ - 3, /* MIXED1IO15 */ - 3, /* MIXED1IO16 */ - 3, /* MIXED1IO17 */ - 3, /* MIXED1IO18 */ - 3, /* MIXED1IO19 */ - 3, /* MIXED1IO20 */ - 0, /* MIXED1IO21 */ - 3, /* MIXED2IO0 */ - 3, /* MIXED2IO1 */ - 3, /* MIXED2IO2 */ - 3, /* MIXED2IO3 */ - 3, /* MIXED2IO4 */ - 3, /* MIXED2IO5 */ - 3, /* MIXED2IO6 */ - 3, /* MIXED2IO7 */ - 0, /* GPLINMUX48 */ - 0, /* GPLINMUX49 */ - 0, /* GPLINMUX50 */ - 0, /* GPLINMUX51 */ - 0, /* GPLINMUX52 */ - 0, /* GPLINMUX53 */ - 0, /* GPLINMUX54 */ - 0, /* GPLINMUX55 */ - 0, /* GPLINMUX56 */ - 0, /* GPLINMUX57 */ - 0, /* GPLINMUX58 */ - 0, /* GPLINMUX59 */ - 0, /* GPLINMUX60 */ - 0, /* GPLINMUX61 */ - 0, /* GPLINMUX62 */ - 0, /* GPLINMUX63 */ - 0, /* GPLINMUX64 */ - 0, /* GPLINMUX65 */ - 0, /* GPLINMUX66 */ - 0, /* GPLINMUX67 */ - 0, /* GPLINMUX68 */ - 0, /* GPLINMUX69 */ - 0, /* GPLINMUX70 */ - 1, /* GPLMUX0 */ - 1, /* GPLMUX1 */ - 1, /* GPLMUX2 */ - 1, /* GPLMUX3 */ - 1, /* GPLMUX4 */ - 1, /* GPLMUX5 */ - 1, /* GPLMUX6 */ - 1, /* GPLMUX7 */ - 1, /* GPLMUX8 */ - 1, /* GPLMUX9 */ - 1, /* GPLMUX10 */ - 1, /* GPLMUX11 */ - 1, /* GPLMUX12 */ - 1, /* GPLMUX13 */ - 1, /* GPLMUX14 */ - 1, /* GPLMUX15 */ - 1, /* GPLMUX16 */ - 1, /* GPLMUX17 */ - 1, /* GPLMUX18 */ - 1, /* GPLMUX19 */ - 1, /* GPLMUX20 */ - 1, /* GPLMUX21 */ - 1, /* GPLMUX22 */ - 1, /* GPLMUX23 */ - 1, /* GPLMUX24 */ - 1, /* GPLMUX25 */ - 1, /* GPLMUX26 */ - 1, /* GPLMUX27 */ - 1, /* GPLMUX28 */ - 1, /* GPLMUX29 */ - 1, /* GPLMUX30 */ - 1, /* GPLMUX31 */ - 1, /* GPLMUX32 */ - 1, /* GPLMUX33 */ - 1, /* GPLMUX34 */ - 1, /* GPLMUX35 */ - 1, /* GPLMUX36 */ - 1, /* GPLMUX37 */ - 1, /* GPLMUX38 */ - 1, /* GPLMUX39 */ - 1, /* GPLMUX40 */ - 1, /* GPLMUX41 */ - 1, /* GPLMUX42 */ - 1, /* GPLMUX43 */ - 1, /* GPLMUX44 */ - 1, /* GPLMUX45 */ - 1, /* GPLMUX46 */ - 1, /* GPLMUX47 */ - 1, /* GPLMUX48 */ - 1, /* GPLMUX49 */ - 1, /* GPLMUX50 */ - 1, /* GPLMUX51 */ - 1, /* GPLMUX52 */ - 1, /* GPLMUX53 */ - 1, /* GPLMUX54 */ - 1, /* GPLMUX55 */ - 1, /* GPLMUX56 */ - 1, /* GPLMUX57 */ - 1, /* GPLMUX58 */ - 1, /* GPLMUX59 */ - 1, /* GPLMUX60 */ - 1, /* GPLMUX61 */ - 1, /* GPLMUX62 */ - 1, /* GPLMUX63 */ - 1, /* GPLMUX64 */ - 1, /* GPLMUX65 */ - 1, /* GPLMUX66 */ - 1, /* GPLMUX67 */ - 1, /* GPLMUX68 */ - 1, /* GPLMUX69 */ - 1, /* GPLMUX70 */ - 0, /* NANDUSEFPGA */ - 0, /* UART0USEFPGA */ - 0, /* RGMII1USEFPGA */ - 0, /* SPIS0USEFPGA */ - 0, /* CAN0USEFPGA */ - 0, /* I2C0USEFPGA */ - 0, /* SDMMCUSEFPGA */ - 0, /* QSPIUSEFPGA */ - 0, /* SPIS1USEFPGA */ - 0, /* RGMII0USEFPGA */ - 0, /* UART1USEFPGA */ - 0, /* CAN1USEFPGA */ - 0, /* USB1USEFPGA */ - 0, /* I2C3USEFPGA */ - 0, /* I2C2USEFPGA */ - 0, /* I2C1USEFPGA */ - 0, /* SPIM1USEFPGA */ - 0, /* USB0USEFPGA */ - 0 /* SPIM0USEFPGA */ -}; -#endif /* CONFIG_TARGET_SOCFPGA_ARRIA5 */ diff --git a/board/altera/socfpga/qts/pinmux_config.h b/board/altera/socfpga/qts/pinmux_config.h deleted file mode 100644 index 21fabb0..0000000 --- a/board/altera/socfpga/qts/pinmux_config.h +++ /dev/null @@ -1,54 +0,0 @@ -/* This file is generated by Preloader Generator */ - -#ifndef _PRELOADER_PINMUX_CONFIG_H_ -#define _PRELOADER_PINMUX_CONFIG_H_ - -/* - * State of enabling for which IP connected out through the muxing. - * Value 1 mean the IP connection is muxed out - */ -#define CONFIG_HPS_EMAC0 (1) -#define CONFIG_HPS_EMAC1 (0) -#define CONFIG_HPS_USB0 (0) -#define CONFIG_HPS_USB1 (1) -#define CONFIG_HPS_NAND (0) -#define CONFIG_HPS_SDMMC (1) -#define CONFIG_HPS_QSPI (0) -#define CONFIG_HPS_UART0 (1) -#define CONFIG_HPS_UART1 (0) -#define CONFIG_HPS_TRACE (0) -#define CONFIG_HPS_I2C0 (1) -#define CONFIG_HPS_I2C1 (0) -#define CONFIG_HPS_I2C2 (0) -#define CONFIG_HPS_I2C3 (0) -#define CONFIG_HPS_SPIM0 (0) -#define CONFIG_HPS_SPIM1 (0) -#define CONFIG_HPS_SPIS0 (0) -#define CONFIG_HPS_SPIS1 (0) -#define CONFIG_HPS_CAN0 (1) -#define CONFIG_HPS_CAN1 (0) - -/* IP attribute value (which affected by pin muxing configuration) */ -#define CONFIG_HPS_SDMMC_BUSWIDTH (8) - -/* 1 if the pins are connected out */ -#define CONFIG_HPS_QSPI_CS0 (0) -#define CONFIG_HPS_QSPI_CS1 (0) -#define CONFIG_HPS_QSPI_CS2 (0) -#define CONFIG_HPS_QSPI_CS3 (0) - -/* UART */ -/* 1 means the pin is mux out or available */ -#define CONFIG_HPS_UART0_TX (1) -#define CONFIG_HPS_UART0_RX (1) -#define CONFIG_HPS_UART0_CTS (0) -#define CONFIG_HPS_UART0_RTS (0) -#define CONFIG_HPS_UART1_TX (0) -#define CONFIG_HPS_UART1_RX (0) -#define CONFIG_HPS_UART1_CTS (0) -#define CONFIG_HPS_UART1_RTS (0) - -/* Pin mux data */ -#define CONFIG_HPS_PINMUX_NUM (207) - -#endif /* _PRELOADER_PINMUX_CONFIG_H_ */ diff --git a/board/altera/socfpga/qts/pll_config.h b/board/altera/socfpga/qts/pll_config.h deleted file mode 100644 index 7cd25df..0000000 --- a/board/altera/socfpga/qts/pll_config.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2012-2014. All rights reserved - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* This file is generated by Preloader Generator */ - -#ifndef _PRELOADER_PLL_CONFIG_H_ -#define _PRELOADER_PLL_CONFIG_H_ - -/* PLL configuration data */ -/* Main PLL */ -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0) -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63) -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0) -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0) -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0) -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (511) -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (511) -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1) -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0) -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1) -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0) -/* - * To tell where is the clock source: - * 0 = MAINPLL - * 1 = PERIPHPLL - */ -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1) -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1) - -/* Peripheral PLL */ -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1) -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79) -/* - * To tell where is the VCOs source: - * 0 = EOSC1 - * 1 = EOSC2 - * 2 = F2S - */ -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0) -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3) -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (511) -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (511) -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (4) -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4) -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (511) -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0) -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (4) -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1) -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1) -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249) -/* - * To tell where is the clock source: - * 0 = F2S_PERIPH_REF_CLK - * 1 = MAIN_CLK - * 2 = PERIPH_CLK - */ -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (2) -#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2) -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1) - -/* SDRAM PLL */ -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2) -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79) - -/* - * To tell where is the VCOs source: - * 0 = EOSC1 - * 1 = EOSC2 - * 2 = F2S - */ -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0) -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1) -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0) -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0) -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0) -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1) -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4) -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5) -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0) - -/* Info for driver */ -#define CONFIG_HPS_CLK_OSC1_HZ (25000000) -#define CONFIG_HPS_CLK_OSC2_HZ (25000000) -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000) -#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000) -#define CONFIG_HPS_CLK_SDRVCO_HZ (666666666) -#define CONFIG_HPS_CLK_EMAC0_HZ (250000000) -#define CONFIG_HPS_CLK_EMAC1_HZ (250000000) -#define CONFIG_HPS_CLK_USBCLK_HZ (200000000) -#define CONFIG_HPS_CLK_NAND_HZ (50000000) -#define CONFIG_HPS_CLK_SDMMC_HZ (200000000) -#define CONFIG_HPS_CLK_QSPI_HZ (400000000) -#define CONFIG_HPS_CLK_SPIM_HZ (200000000) -#define CONFIG_HPS_CLK_CAN0_HZ (100000000) -#define CONFIG_HPS_CLK_CAN1_HZ (100000000) -#define CONFIG_HPS_CLK_GPIODB_HZ (32000) -#define CONFIG_HPS_CLK_L4_MP_HZ (100000000) -#define CONFIG_HPS_CLK_L4_SP_HZ (100000000) - -#endif /* _PRELOADER_PLL_CONFIG_H_ */ diff --git a/board/altera/socfpga/qts/sdram_config.h b/board/altera/socfpga/qts/sdram_config.h deleted file mode 100644 index f6d51ca..0000000 --- a/board/altera/socfpga/qts/sdram_config.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2012-2015 - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -/* This file is autogenerated from tools provided by Altera.*/ -#ifndef __SDRAM_CONFIG_H -#define __SDRAM_CONFIG_H - -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#ifdef CONFIG_SOCFPGA_ARRIA5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26 -#else -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 - -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 \ -0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 \ -0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 \ -0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 - -#endif /*#ifndef__SDRAM_CONFIG_H*/ diff --git a/board/altera/socfpga/qts/sequencer_auto.h b/board/altera/socfpga/qts/sequencer_auto.h deleted file mode 100644 index 0c5d83b..0000000 --- a/board/altera/socfpga/qts/sequencer_auto.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2012-2015 - * - * SPDX-License-Identifier: BSD-3-Clause - */ - - -#define RW_MGR_READ_B2B_WAIT2 0x6A -#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31 -#define RW_MGR_REFRESH_ALL 0x14 -#define RW_MGR_ZQCL 0x06 -#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22 -#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23 -#define RW_MGR_ACTIVATE_0_AND_1 0x0D -#define RW_MGR_MRS2_MIRR 0x0A -#define RW_MGR_INIT_RESET_0_CKE_0 0x6E -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45 -#define RW_MGR_ACTIVATE_1 0x0F -#define RW_MGR_MRS2 0x04 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34 -#define RW_MGR_MRS1 0x03 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define RW_MGR_IDLE_LOOP1 0x7A -#else -#define RW_MGR_IDLE_LOOP1 0x7C -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18 -#define RW_MGR_MRS3 0x05 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define RW_MGR_IDLE_LOOP2 0x79 -#else -#define RW_MGR_IDLE_LOOP2 0x7B -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E -#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24 -#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define RW_MGR_RDIMM_CMD 0x78 -#else -#define RW_MGR_RDIMM_CMD 0x7A -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36 -#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38 -#define RW_MGR_GUARANTEED_READ_CONT 0x53 -#define RW_MGR_MRS3_MIRR 0x0B -#define RW_MGR_IDLE 0x00 -#define RW_MGR_READ_B2B 0x58 -#define RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F -#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37 -#define RW_MGR_GUARANTEED_WRITE 0x17 -#define RW_MGR_PRECHARGE_ALL 0x12 -#define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define RW_MGR_SGLE_READ 0x7C -#else -#define RW_MGR_SGLE_READ 0x7E -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define RW_MGR_MRS0_USER_MIRR 0x0C -#define RW_MGR_RETURN 0x01 -#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35 -#define RW_MGR_MRS0_USER 0x07 -#define RW_MGR_GUARANTEED_READ 0x4B -#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 -#define RW_MGR_INIT_RESET_1_CKE_0 0x73 -#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 -#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20 -#define RW_MGR_MRS0_DLL_RESET 0x02 -#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E -#define RW_MGR_LFSR_WR_RD_BANK_0 0x21 -#define RW_MGR_CLEAR_DQS_ENABLE 0x48 -#define RW_MGR_MRS1_MIRR 0x09 -#define RW_MGR_READ_B2B_WAIT1 0x60 -#define RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680 -#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680 -#define RW_MGR_CONTENT_REFRESH_ALL 0x000980 -#define RW_MGR_CONTENT_ZQCL 0x008380 -#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700 -#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00 -#define RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800 -#define RW_MGR_CONTENT_MRS2_MIRR 0x008580 -#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000 -#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680 -#define RW_MGR_CONTENT_ACTIVATE_1 0x000880 -#define RW_MGR_CONTENT_MRS2 0x008280 -#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00 -#define RW_MGR_CONTENT_MRS1 0x008200 -#define RW_MGR_CONTENT_IDLE_LOOP1 0x00A680 -#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8 -#define RW_MGR_CONTENT_MRS3 0x008300 -#define RW_MGR_CONTENT_IDLE_LOOP2 0x008680 -#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88 -#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0 -#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88 -#define RW_MGR_CONTENT_RDIMM_CMD 0x009180 -#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700 -#define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8 -#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0 -#define RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168 -#define RW_MGR_CONTENT_MRS3_MIRR 0x008600 -#define RW_MGR_CONTENT_IDLE 0x080000 -#define RW_MGR_CONTENT_READ_B2B 0x040E88 -#define RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000 -#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00 -#define RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68 -#define RW_MGR_CONTENT_PRECHARGE_ALL 0x000900 -#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080 -#define RW_MGR_CONTENT_SGLE_READ 0x040F08 -#define RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400 -#define RW_MGR_CONTENT_RETURN 0x080680 -#define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80 -#define RW_MGR_CONTENT_MRS0_USER 0x008100 -#define RW_MGR_CONTENT_GUARANTEED_READ 0x001168 -#define RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480 -#define RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080 -#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680 -#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00 -#define RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180 -#define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680 -#define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80 -#define RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158 -#define RW_MGR_CONTENT_MRS1_MIRR 0x008500 -#define RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680 - diff --git a/board/altera/socfpga/qts/sequencer_auto_ac_init.h b/board/altera/socfpga/qts/sequencer_auto_ac_init.h deleted file mode 100644 index c46421b..0000000 --- a/board/altera/socfpga/qts/sequencer_auto_ac_init.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2012-2015 - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -const uint32_t ac_rom_init[] = { -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ - 0x20700000, - 0x20780000, - 0x10080831, - 0x10080930, - 0x10090004, - 0x100a0008, - 0x100b0000, - 0x10380400, - 0x10080849, - 0x100808c8, - 0x100a0004, - 0x10090010, - 0x100b0000, - 0x30780000, - 0x38780000, - 0x30780000, - 0x10680000, - 0x106b0000, - 0x10280400, - 0x10480000, - 0x1c980000, - 0x1c9b0000, - 0x1c980008, - 0x1c9b0008, - 0x38f80000, - 0x3cf80000, - 0x38780000, - 0x18180000, - 0x18980000, - 0x13580000, - 0x135b0000, - 0x13580008, - 0x135b0008, - 0x33780000, - 0x10580008, - 0x10780000 -#else - 0x20700000, - 0x20780000, - 0x10080431, - 0x10080530, - 0x10090004, - 0x100a0008, - 0x100b0000, - 0x10380400, - 0x10080449, - 0x100804c8, - 0x100a0004, - 0x10090010, - 0x100b0000, - 0x30780000, - 0x38780000, - 0x30780000, - 0x10680000, - 0x106b0000, - 0x10280400, - 0x10480000, - 0x1c980000, - 0x1c9b0000, - 0x1c980008, - 0x1c9b0008, - 0x38f80000, - 0x3cf80000, - 0x38780000, - 0x18180000, - 0x18980000, - 0x13580000, - 0x135b0000, - 0x13580008, - 0x135b0008, - 0x33780000, - 0x10580008, - 0x10780000 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -}; diff --git a/board/altera/socfpga/qts/sequencer_auto_inst_init.h b/board/altera/socfpga/qts/sequencer_auto_inst_init.h deleted file mode 100644 index ad0395b..0000000 --- a/board/altera/socfpga/qts/sequencer_auto_inst_init.h +++ /dev/null @@ -1,268 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2012-2015 - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -const u32 inst_rom_init[] = { - 0x80000, - 0x80680, - 0x8180, - 0x8200, - 0x8280, - 0x8300, - 0x8380, - 0x8100, - 0x8480, - 0x8500, - 0x8580, - 0x8600, - 0x8400, - 0x800, - 0x8680, - 0x880, - 0xa680, - 0x80680, - 0x900, - 0x80680, - 0x980, - 0x8680, - 0x80680, - 0xb68, - 0xcce8, - 0xae8, - 0x8ce8, - 0xb88, - 0xec88, - 0xa08, - 0xac88, - 0x80680, - 0xce00, - 0xcd80, - 0xe700, - 0xc00, - 0x20ce0, - 0x20ce0, - 0x20ce0, - 0x20ce0, - 0xd00, - 0x680, - 0x680, - 0x680, - 0x680, - 0x60e80, - 0x61080, - 0x61080, - 0x61080, - 0xa680, - 0x8680, - 0x80680, - 0xce00, - 0xcd80, - 0xe700, - 0xc00, - 0x30ce0, - 0x30ce0, - 0x30ce0, - 0x30ce0, - 0xd00, - 0x680, - 0x680, - 0x680, - 0x680, - 0x70e80, - 0x71080, - 0x71080, - 0x71080, - 0xa680, - 0x8680, - 0x80680, - 0x1158, - 0x6d8, - 0x80680, - 0x1168, - 0x7e8, - 0x7e8, - 0x87e8, - 0x40fe8, - 0x410e8, - 0x410e8, - 0x410e8, - 0x1168, - 0x7e8, - 0x7e8, - 0xa7e8, - 0x80680, - 0x40e88, - 0x41088, - 0x41088, - 0x41088, - 0x40f68, - 0x410e8, - 0x410e8, - 0x410e8, - 0xa680, - 0x40fe8, - 0x410e8, - 0x410e8, - 0x410e8, - 0x41008, - 0x41088, - 0x41088, - 0x41088, - 0x1100, - 0xc680, - 0x8680, - 0xe680, - 0x80680, - 0x0, - 0x8000, - 0xa000, - 0xc000, - 0x80000, - 0x80, - 0x8080, - 0xa080, - 0xc080, - 0x80080, - 0x9180, - 0x8680, - 0xa680, - 0x80680, - 0x40f08, - 0x80680 -}; -#else -const u32 inst_rom_init[] = { - 0x80000, - 0x80680, - 0x8180, - 0x8200, - 0x8280, - 0x8300, - 0x8380, - 0x8100, - 0x8480, - 0x8500, - 0x8580, - 0x8600, - 0x8400, - 0x800, - 0x8680, - 0x880, - 0xa680, - 0x80680, - 0x900, - 0x80680, - 0x980, - 0x8680, - 0x80680, - 0xb68, - 0xcce8, - 0xae8, - 0x8ce8, - 0xb88, - 0xec88, - 0xa08, - 0xac88, - 0x80680, - 0xce00, - 0xcd80, - 0xe700, - 0xc00, - 0x20ce0, - 0x20ce0, - 0x20ce0, - 0x20ce0, - 0xd00, - 0x680, - 0x680, - 0x680, - 0x680, - 0x60e80, - 0x61080, - 0x61080, - 0x61080, - 0xa680, - 0x8680, - 0x80680, - 0xce00, - 0xcd80, - 0xe700, - 0xc00, - 0x30ce0, - 0x30ce0, - 0x30ce0, - 0x30ce0, - 0xd00, - 0x680, - 0x680, - 0x680, - 0x680, - 0x70e80, - 0x71080, - 0x71080, - 0x71080, - 0xa680, - 0x8680, - 0x80680, - 0x1158, - 0x6d8, - 0x80680, - 0x1168, - 0x7e8, - 0x7e8, - 0x87e8, - 0x40fe8, - 0x410e8, - 0x410e8, - 0x410e8, - 0x1168, - 0x7e8, - 0x7e8, - 0xa7e8, - 0x80680, - 0x40e88, - 0x41088, - 0x41088, - 0x41088, - 0x40f68, - 0x410e8, - 0x410e8, - 0x410e8, - 0xa680, - 0x40fe8, - 0x410e8, - 0x410e8, - 0x410e8, - 0x41008, - 0x41088, - 0x41088, - 0x41088, - 0x1100, - 0xc680, - 0x8680, - 0xe680, - 0x80680, - 0x0, - 0x0, - 0xa000, - 0x8000, - 0x80000, - 0x80, - 0x80, - 0x80, - 0x80, - 0xa080, - 0x8080, - 0x80080, - 0x9180, - 0x8680, - 0xa680, - 0x80680, - 0x40f08, - 0x80680 -}; -#endif /* CONFIG_SOCFPGA_ARRIA5 */ diff --git a/board/altera/socfpga/qts/sequencer_defines.h b/board/altera/socfpga/qts/sequencer_defines.h deleted file mode 100644 index bfe5b27..0000000 --- a/board/altera/socfpga/qts/sequencer_defines.h +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright Altera Corporation (C) 2012-2015 - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _SEQUENCER_DEFINES_H_ -#define _SEQUENCER_DEFINES_H_ - -#define AC_ROM_MR1_MIRR 0000000000100 -#define AC_ROM_MR1_OCD_ENABLE -#define AC_ROM_MR2_MIRR 0000000010000 -#define AC_ROM_MR3_MIRR 0000000000000 -#define AC_ROM_MR0_CALIB -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define AC_ROM_MR0_DLL_RESET_MIRR 0100011001000 -#define AC_ROM_MR0_DLL_RESET 0100100110000 -#define AC_ROM_MR0_MIRR 0100001001001 -#define AC_ROM_MR0 0100000110001 -#else -#define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000 -#define AC_ROM_MR0_DLL_RESET 0010100110000 -#define AC_ROM_MR0_MIRR 0010001001001 -#define AC_ROM_MR0 0010000110001 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define AC_ROM_MR1 0000000000100 -#define AC_ROM_MR2 0000000001000 -#define AC_ROM_MR3 0000000000000 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define AFI_CLK_FREQ 534 -#else -#define AFI_CLK_FREQ 401 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define AFI_RATE_RATIO 1 -#define AVL_CLK_FREQ 67 -#define BFM_MODE 0 -#define BURST2 0 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define CALIB_LFIFO_OFFSET 8 -#define CALIB_VFIFO_OFFSET 6 -#else -#define CALIB_LFIFO_OFFSET 7 -#define CALIB_VFIFO_OFFSET 5 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0 -#define ENABLE_SUPER_QUICK_CALIBRATION 0 -#define GUARANTEED_READ_BRINGUP_TEST 0 -#define HARD_PHY 1 -#define HARD_VFIFO 1 -#define HPS_HW 1 -#define HR_DDIO_OUT_HAS_THREE_REGS 0 -#define IO_DELAY_PER_DCHAIN_TAP 25 -#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define IO_DELAY_PER_OPA_TAP 234 -#else -#define IO_DELAY_PER_OPA_TAP 312 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define IO_DLL_CHAIN_LENGTH 8 -#define IO_DM_OUT_RESERVE 0 -#define IO_DQDQS_OUT_PHASE_MAX 0 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define IO_DQS_EN_DELAY_MAX 15 -#define IO_DQS_EN_DELAY_OFFSET 16 -#else -#define IO_DQS_EN_DELAY_MAX 31 -#define IO_DQS_EN_DELAY_OFFSET 0 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define IO_DQS_EN_PHASE_MAX 7 -#define IO_DQS_IN_DELAY_MAX 31 -#define IO_DQS_IN_RESERVE 4 -#define IO_DQS_OUT_RESERVE 6 -#define IO_DQ_OUT_RESERVE 0 -#define IO_IO_IN_DELAY_MAX 31 -#define IO_IO_OUT1_DELAY_MAX 31 -#define IO_IO_OUT2_DELAY_MAX 0 -#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 -#define MARGIN_VARIATION_TEST 0 -#define MAX_LATENCY_COUNT_WIDTH 5 -#define MEM_ADDR_WIDTH 13 -#define READ_VALID_FIFO_SIZE 16 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c -#else -#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ -#define RW_MGR_MEM_ADDRESS_MIRRORING 0 -#define RW_MGR_MEM_ADDRESS_WIDTH 15 -#define RW_MGR_MEM_BANK_WIDTH 3 -#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1 -#define RW_MGR_MEM_CLK_EN_WIDTH 1 -#define RW_MGR_MEM_CONTROL_WIDTH 1 -#define RW_MGR_MEM_DATA_MASK_WIDTH 5 -#define RW_MGR_MEM_DATA_WIDTH 40 -#define RW_MGR_MEM_DQ_PER_READ_DQS 8 -#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 -#define RW_MGR_MEM_IF_READ_DQS_WIDTH 5 -#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 5 -#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 -#define RW_MGR_MEM_NUMBER_OF_RANKS 1 -#define RW_MGR_MEM_ODT_WIDTH 1 -#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 -#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 -#define RW_MGR_MR0_BL 1 -#define RW_MGR_MR0_CAS_LATENCY 3 -#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 5 -#define RW_MGR_WRITE_TO_DEBUG_READ 1.0 -#define SKEW_CALIBRATION 0 -#define TINIT_CNTR1_VAL 32 -#define TINIT_CNTR2_VAL 32 -#define TINIT_CNTR0_VAL 132 -#define TRESET_CNTR1_VAL 99 -#define TRESET_CNTR2_VAL 10 -#define TRESET_CNTR0_VAL 132 - -#endif /* _SEQUENCER_DEFINES_H_ */ diff --git a/board/altera/socfpga/wrap_pinmux_config.c b/board/altera/socfpga/wrap_pinmux_config.c deleted file mode 100644 index b33e2ca..0000000 --- a/board/altera/socfpga/wrap_pinmux_config.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2015 Marek Vasut <marex@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <errno.h> -/* - * Yes, dear reader, we're including a C file here, this is no mistake. - * But this time around, we do even more perverse hacking here to be - * compatible with QTS headers and obtain reasonably nice results too. - * - * First, we define _PRELOADER_PINMUX_CONFIG_H_, which will neutralise - * the pinmux_config.h inclusion in pinmux_config.c . Since we are - * probing everything from DT, we do NOT want those macros from the - * pinmux_config.h to ooze into our build system, anywhere, ever. So - * we nip it at the bud. - * - * Next, pinmux_config.c needs CONFIG_HPS_PINMUX_NUM and uses it to - * specify sized array explicitly. Instead, we want to use ARRAY_SIZE - * to figure out the size of the array, so define this macro as an - * empty one, so that the preprocessor optimizes things such that the - * arrays are not sized by default. - */ -#define _PRELOADER_PINMUX_CONFIG_H_ -#define CONFIG_HPS_PINMUX_NUM -#include "qts/pinmux_config.c" - -void sysmgr_get_pinmux_table(const unsigned long **table, - unsigned int *table_len) -{ - *table = sys_mgr_init_table; - *table_len = ARRAY_SIZE(sys_mgr_init_table); -} diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 4289179..2fea56f 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -131,23 +131,15 @@ static void ddr2_conf(struct atmel_mpddr *ddr2) void mem_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; struct atmel_mpddr ddr2; - unsigned long csa; ddr2_conf(&ddr2); /* enable DDR2 clock */ - writel(0x4, &pmc->scer); - - /* Chip select 1 is for DDR2/SDRAM */ - csa = readl(&mat->ebicsa); - csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; - csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V; - writel(csa, &mat->ebicsa); + writel(AT91_PMC_DDR, &pmc->scer); /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_CS6, &ddr2); + ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); } #endif diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 4f46a03..59bc535 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -316,7 +316,7 @@ void mem_init(void) ddr2_conf(&ddr2); /* enable DDR2 clock */ - writel(0x4, &pmc->scer); + writel(AT91_PMC_DDR, &pmc->scer); /* Chip select 1 is for DDR2/SDRAM */ csa = readl(&matrix->ebicsa); @@ -327,6 +327,6 @@ void mem_init(void) writel(csa, &matrix->ebicsa); /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_CS1, &ddr2); + ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); } #endif diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index 114ac5c..1738a2b 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -353,7 +353,7 @@ void mem_init(void) ddr2_conf(&ddr2); /* enable DDR2 clock */ - writel(0x4, &pmc->scer); + writel(AT91_PMC_DDR, &pmc->scer); /* Chip select 1 is for DDR2/SDRAM */ csa = readl(&matrix->ebicsa); @@ -364,6 +364,6 @@ void mem_init(void) writel(csa, &matrix->ebicsa); /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_CS1, &ddr2); + ddr2_init(ATMEL_BASE_DDRSDRC, ATMEL_BASE_CS1, &ddr2); } #endif diff --git a/board/atmel/sama5d3_xplained/sama5d3_xplained.c b/board/atmel/sama5d3_xplained/sama5d3_xplained.c index 92ed4e8..7a01149 100644 --- a/board/atmel/sama5d3_xplained/sama5d3_xplained.c +++ b/board/atmel/sama5d3_xplained/sama5d3_xplained.c @@ -191,10 +191,10 @@ void mem_init(void) /* enable MPDDR clock */ at91_periph_clk_enable(ATMEL_ID_MPDDRC); - writel(0x4, &pmc->scer); + writel(AT91_PMC_DDR, &pmc->scer); /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_DDRCS, &ddr2); + ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); } void at91_pmc_init(void) diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index cf6ed8b..7c95f33 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -15,6 +15,7 @@ #include <asm/arch/gpio.h> #include <asm/arch/clk.h> #include <lcd.h> +#include <linux/ctype.h> #include <atmel_hlcdc.h> #include <atmel_mci.h> #include <phy.h> @@ -369,6 +370,25 @@ void spi_cs_deactivate(struct spi_slave *slave) } #endif /* CONFIG_ATMEL_SPI */ +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + const int MAX_STR_LEN = 32; + char name[MAX_STR_LEN], *p; + int i; + + strncpy(name, get_cpu_name(), MAX_STR_LEN); + for (i = 0, p = name; (*p) && (i < MAX_STR_LEN); p++, i++) + *p = tolower(*p); + + strcat(name, "ek.dtb"); + setenv("dtb_name", name); +#endif + return 0; +} +#endif + /* SPL */ #ifdef CONFIG_SPL_BUILD void spl_board_init(void) @@ -430,10 +450,10 @@ void mem_init(void) /* enable MPDDR clock */ at91_periph_clk_enable(ATMEL_ID_MPDDRC); - writel(0x4, &pmc->scer); + writel(AT91_PMC_DDR, &pmc->scer); /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_DDRCS, &ddr2); + ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); } void at91_pmc_init(void) diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 7d447fe..db45331 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -390,10 +390,10 @@ void mem_init(void) /* enable MPDDR clock */ at91_periph_clk_enable(ATMEL_ID_MPDDRC); - writel(0x4, &pmc->scer); + writel(AT91_PMC_DDR, &pmc->scer); /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_DDRCS, &ddr2); + ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); } void at91_pmc_init(void) diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index e9bbb4b..357b223 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -386,10 +386,10 @@ void mem_init(void) /* enable MPDDR clock */ at91_periph_clk_enable(ATMEL_ID_MPDDRC); - writel(0x4, &pmc->scer); + writel(AT91_PMC_DDR, &pmc->scer); /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_DDRCS, &ddr2); + ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2); } void at91_pmc_init(void) diff --git a/board/mini-box/picosam9g45/Kconfig b/board/mini-box/picosam9g45/Kconfig new file mode 100644 index 0000000..98ec0c4 --- /dev/null +++ b/board/mini-box/picosam9g45/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PICOSAM9G45 + +config SYS_BOARD + default "picosam9g45" + +config SYS_VENDOR + default "mini-box" + +config SYS_CONFIG_NAME + default "picosam9g45" + +endif diff --git a/board/mini-box/picosam9g45/MAINTAINERS b/board/mini-box/picosam9g45/MAINTAINERS new file mode 100644 index 0000000..a8cf01d --- /dev/null +++ b/board/mini-box/picosam9g45/MAINTAINERS @@ -0,0 +1,6 @@ +PICOSAM9G45 BOARD +M: Erik van Luijk <evanluijk@interact.nl> +S: Maintained +F: board/mini-box/picosam9g45/ +F: include/configs/picosam9g45.h +F: configs/picosam9g45_defconfig diff --git a/board/mini-box/picosam9g45/Makefile b/board/mini-box/picosam9g45/Makefile new file mode 100644 index 0000000..bf6e8e3 --- /dev/null +++ b/board/mini-box/picosam9g45/Makefile @@ -0,0 +1,19 @@ +# +# Makefile for mini-box PICOSAM9G45 (AT91SAM9G45) based board +# (C) Copytight 2015 Inter Act B.V. +# +# Based on: +# U-Boot file: board/atmel/at91sam9m10g45ek/Makefile +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian@popies.net> +# Lead Tech Design <www.leadtechdesign.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += picosam9g45.o +obj-y += led.o diff --git a/board/mini-box/picosam9g45/led.c b/board/mini-box/picosam9g45/led.c new file mode 100644 index 0000000..dc1013a --- /dev/null +++ b/board/mini-box/picosam9g45/led.c @@ -0,0 +1,25 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91sam9g45.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> + +void coloured_LED_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable clock */ + writel(1 << ATMEL_ID_PIODE, &pmc->pcer); + + at91_set_gpio_output(CONFIG_GREEN_LED, 1); + + at91_set_gpio_value(CONFIG_GREEN_LED, 1); +} diff --git a/board/mini-box/picosam9g45/picosam9g45.c b/board/mini-box/picosam9g45/picosam9g45.c new file mode 100644 index 0000000..afbd6ce --- /dev/null +++ b/board/mini-box/picosam9g45/picosam9g45.c @@ -0,0 +1,354 @@ +/* + * Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board + * (C) Copyright 2015 Inter Act B.V. + * + * Based on: + * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clk.h> +#include <asm/arch/at91sam9g45_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clk.h> +#include <lcd.h> +#include <linux/mtd/nand.h> +#include <atmel_lcdc.h> +#include <atmel_mci.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include <net.h> +#endif +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#if defined(CONFIG_SPL_BUILD) +#include <spl.h> + +void at91_spl_board_init(void) +{ +#ifdef CONFIG_SYS_USE_MMC + at91_mci_hw_init(); +#endif +} + +#include <asm/arch/atmel_mpddrc.h> +static void ddr2_conf(struct atmel_mpddr *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_DQMS_SHARED | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3); + + ddr2->rtr = 0x24b; + + ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */ + 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */ + 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */ + 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */ + 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */ + 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/ + 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */ + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */ + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */ + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct atmel_mpddr ddr2; + unsigned long csa; + + ddr2_conf(&ddr2); + + /* enable DDR2 clock */ + writel(AT91_PMC_DDR, &pmc->scer); + + /* Chip select 1 is for DDR2/SDRAM */ + csa = readl(&mat->ebicsa); + csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; + csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V; + writel(csa, &mat->ebicsa); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); + ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2); +} +#endif + +#ifdef CONFIG_CMD_USB +static void picosam9g45_usb_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(1 << ATMEL_ID_PIODE, &pmc->pcer); + + at91_set_gpio_output(AT91_PIN_PD1, 0); + at91_set_gpio_output(AT91_PIN_PD3, 0); +} +#endif + +#ifdef CONFIG_MACB +static void picosam9g45_macb_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + + /* Enable clock */ + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + + /* + * Disable pull-up on: + * RXDV (PA15) => PHY normal mode (not Test mode) + * ERX0 (PA12) => PHY ADDR0 + * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA12) | + pin_to_mask(AT91_PIN_PA13), + &pioa->pudr); + + at91_phy_reset(); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA12) | + pin_to_mask(AT91_PIN_PA13), + &pioa->puer); + + /* And the pins. */ + at91_macb_hw_init(); +} +#endif + +#ifdef CONFIG_LCD + +vidinfo_t panel_info = { + .vl_col = 480, + .vl_row = 272, + .vl_clk = 9000000, + .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | + ATMEL_LCDC_INVFRAME_NORMAL, + .vl_bpix = 3, + .vl_tft = 1, + .vl_hsync_len = 45, + .vl_left_margin = 1, + .vl_right_margin = 1, + .vl_vsync_len = 1, + .vl_upper_margin = 40, + .vl_lower_margin = 1, + .mmio = ATMEL_BASE_LCDC, +}; + + +void lcd_enable(void) +{ + at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */ +} + +static void picosam9g45_lcd_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ + at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ + at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ + + at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ + at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ + at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ + at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ + at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ + at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ + at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ + at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ + at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ + at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ + at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ + at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ + at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ + + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); + + gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; +} + +#ifdef CONFIG_LCD_INFO +#include <nand.h> +#include <version.h> + +void lcd_show_board_info(void) +{ + ulong dram_size; + int i; + char temp[32]; + + lcd_printf("%s\n", U_BOOT_VERSION); + lcd_printf("(C) 2015 Inter Act B.V.\n"); + lcd_printf("support@interact.nl\n"); + lcd_printf("%s CPU at %s MHz\n", + ATMEL_CPU_NAME, + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + lcd_printf(" %ld MB SDRAM\n", dram_size >> 20); +} +#endif /* CONFIG_LCD_INFO */ +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bis) +{ + at91_mci_hw_init(); + + return atmel_mci_init((void *)ATMEL_BASE_MCI0); +} +#endif + +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + return 0; +} + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_USB + picosam9g45_usb_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91_spi0_hw_init(1 << 0); +#endif +#ifdef CONFIG_ATMEL_SPI + at91_spi0_hw_init(1 << 4); +#endif +#ifdef CONFIG_MACB + picosam9g45_macb_hw_init(); +#endif +#ifdef CONFIG_LCD + picosam9g45_lcd_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); +#endif + return rc; +} + +/* SPI chip select control */ +#ifdef CONFIG_ATMEL_SPI +#include <spi.h> + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs < 2; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + switch (slave->cs) { + case 1: + at91_set_gpio_output(AT91_PIN_PB18, 0); + break; + case 0: + default: + at91_set_gpio_output(AT91_PIN_PB3, 0); + break; + } +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + switch (slave->cs) { + case 1: + at91_set_gpio_output(AT91_PIN_PB18, 1); + break; + case 0: + default: + at91_set_gpio_output(AT91_PIN_PB3, 1); + break; + } +} +#endif /* CONFIG_ATMEL_SPI */ diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c index f3f6dae..3294203 100644 --- a/board/siemens/corvus/board.c +++ b/board/siemens/corvus/board.c @@ -144,23 +144,15 @@ static void ddr2_conf(struct atmel_mpddr *ddr2) void mem_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX; struct atmel_mpddr ddr2; - unsigned long csa; ddr2_conf(&ddr2); /* enable DDR2 clock */ - writel(0x4, &pmc->scer); - - /* Chip select 1 is for DDR2/SDRAM */ - csa = readl(&mat->ebicsa); - csa |= AT91_MATRIX_EBI_CS1A_SDRAMC; - csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V; - writel(csa, &mat->ebicsa); + writel(AT91_PMC_DDR, &pmc->scer); /* DDRAM2 Controller initialize */ - ddr2_init(ATMEL_BASE_CS6, &ddr2); + ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2); } #endif diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig index ff7abfa..7c41aa8 100644 --- a/configs/Ainol_AW1_defconfig +++ b/configs/Ainol_AW1_defconfig @@ -11,7 +11,6 @@ CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:40000,le:87,ri:112,up:38,lo CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-ainol-aw1" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -19,3 +18,4 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_USB_MUSB_HOST=y diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index 3aaf029..e3f44f6 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -11,7 +11,6 @@ CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:82,up:22,lo: CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-ampe-a76" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -19,3 +18,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_USB_MUSB_HOST=y diff --git a/configs/B4420QDS_NAND_defconfig b/configs/B4420QDS_NAND_defconfig index 0313e55..986eda6 100644 --- a/configs/B4420QDS_NAND_defconfig +++ b/configs/B4420QDS_NAND_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_B4860QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/B4420QDS_SPIFLASH_defconfig b/configs/B4420QDS_SPIFLASH_defconfig index 6352ef9..5c6a319 100644 --- a/configs/B4420QDS_SPIFLASH_defconfig +++ b/configs/B4420QDS_SPIFLASH_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/B4420QDS_defconfig b/configs/B4420QDS_defconfig index 3b449de..8568f7d 100644 --- a/configs/B4420QDS_defconfig +++ b/configs/B4420QDS_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4420" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/B4860QDS_NAND_defconfig b/configs/B4860QDS_NAND_defconfig index afa0600..a48ada4 100644 --- a/configs/B4860QDS_NAND_defconfig +++ b/configs/B4860QDS_NAND_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_B4860QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/B4860QDS_SECURE_BOOT_defconfig b/configs/B4860QDS_SECURE_BOOT_defconfig index a335ad3..60ff218 100644 --- a/configs/B4860QDS_SECURE_BOOT_defconfig +++ b/configs/B4860QDS_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/B4860QDS_SPIFLASH_defconfig b/configs/B4860QDS_SPIFLASH_defconfig index 18c3d94..7e8449e 100644 --- a/configs/B4860QDS_SPIFLASH_defconfig +++ b/configs/B4860QDS_SPIFLASH_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig index 01229cc..5e3fd50 100644 --- a/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/B4860QDS_SRIO_PCIE_BOOT_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF4000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/B4860QDS_defconfig b/configs/B4860QDS_defconfig index 8f300c0..d5c7545 100644 --- a/configs/B4860QDS_defconfig +++ b/configs/B4860QDS_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_B4860QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_B4860" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig index b0153c4..b123f9e 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig index 066e6f7..0da87b3 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK100_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_BSC9132QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_100" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig index 31bcec4..d8ad344 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND_SECBOOT,SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig index 64952a0..738c490 100644 --- a/configs/BSC9132QDS_NAND_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_NAND_DDRCLK133_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_BSC9132QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,NAND,SYS_CLK_100_DDR_133" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig index b5759fb..c468137 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK100_SECURE_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig index 9f30977..31a5223 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK100_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_100" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig index 7becdfe..726c8ff 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK133_SECURE_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig index 770c723..ff4e4b4 100644 --- a/configs/BSC9132QDS_NOR_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_NOR_DDRCLK133_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SYS_CLK_100_DDR_133" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig index 5b84924..61725cd 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_SECURE_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig index 365d13e..484857a 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK100_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig index d9e021a..c4a772a 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_SECURE_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig index 2f52320..fcada6d 100644 --- a/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_SDCARD_DDRCLK133_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig index bea9e23..9282e0e 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_SECURE_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig index 1f7557a..f6ad1e9 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig index 933ef77..f3c5702 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_SECURE_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig index 3cbe89b..7f3554d 100644 --- a/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig +++ b/configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_BSC9132QDS=y CONFIG_SYS_EXTRA_OPTIONS="BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/C29XPCIE_NAND_defconfig b/configs/C29XPCIE_NAND_defconfig index c6f0ae4..fd26cea 100644 --- a/configs/C29XPCIE_NAND_defconfig +++ b/configs/C29XPCIE_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig index 6c982dd..bcc2701 100644 --- a/configs/C29XPCIE_NOR_SECBOOT_defconfig +++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_C29XPCIE=y CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig index e95ff0a..2f151fa 100644 --- a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig +++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_C29XPCIE=y CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/C29XPCIE_SPIFLASH_defconfig b/configs/C29XPCIE_SPIFLASH_defconfig index 29889ea..8057f9c 100644 --- a/configs/C29XPCIE_SPIFLASH_defconfig +++ b/configs/C29XPCIE_SPIFLASH_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_C29XPCIE=y CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/C29XPCIE_defconfig b/configs/C29XPCIE_defconfig index 20bbe81..11610d5 100644 --- a/configs/C29XPCIE_defconfig +++ b/configs/C29XPCIE_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_C29XPCIE=y CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index f44aede..7f1c4eb 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -11,7 +11,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-chuwi-v7-cw0825" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -22,3 +21,4 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" CONFIG_VIDEO_LCD_SPI_CS="PA0" CONFIG_VIDEO_LCD_SPI_SCLK="PA1" CONFIG_VIDEO_LCD_SPI_MOSI="PA2" +CONFIG_USB_MUSB_HOST=y diff --git a/configs/Et_q8_v1_6_defconfig b/configs/Et_q8_v1_6_defconfig index ca8db19..65b8e1a 100644 --- a/configs/Et_q8_v1_6_defconfig +++ b/configs/Et_q8_v1_6_defconfig @@ -11,7 +11,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-et-q8-v1.6" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -21,3 +20,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" # CONFIG_CMD_FPGA is not set CONFIG_AXP221_DLDO1_VOLT=3300 CONFIG_AXP221_ALDO1_VOLT=3000 +CONFIG_USB_MUSB_HOST=y diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index 065a3f9..9ef06a7 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -12,7 +12,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH9" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-hyundai-a7hd" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -20,3 +19,4 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_USB_MUSB_HOST=y diff --git a/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig b/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig index 213de5a..40ccf8f 100644 --- a/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig +++ b/configs/Ippo_q8h_v1_2_a33_1024x600_defconfig @@ -12,7 +12,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ippo-q8h-v1.2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -22,3 +21,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" # CONFIG_CMD_FPGA is not set CONFIG_AXP221_DLDO1_VOLT=3300 CONFIG_AXP221_ALDO1_VOLT=3000 +CONFIG_USB_MUSB_HOST=y diff --git a/configs/Ippo_q8h_v1_2_defconfig b/configs/Ippo_q8h_v1_2_defconfig index ff5ec30..5b49c44 100644 --- a/configs/Ippo_q8h_v1_2_defconfig +++ b/configs/Ippo_q8h_v1_2_defconfig @@ -12,7 +12,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v1.2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -22,3 +21,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" # CONFIG_CMD_FPGA is not set CONFIG_AXP221_DLDO1_VOLT=3300 CONFIG_AXP221_ALDO1_VOLT=3000 +CONFIG_USB_MUSB_HOST=y diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig index b67206c..5316860 100644 --- a/configs/Ippo_q8h_v5_defconfig +++ b/configs/Ippo_q8h_v5_defconfig @@ -12,7 +12,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-a23-ippo-q8h-v5" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -22,3 +21,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" # CONFIG_CMD_FPGA is not set CONFIG_AXP221_DLDO1_VOLT=3300 CONFIG_AXP221_ALDO1_VOLT=3000 +CONFIG_USB_MUSB_HOST=y diff --git a/configs/MPC8536DS_36BIT_defconfig b/configs/MPC8536DS_36BIT_defconfig index 4b626a6..6604004 100644 --- a/configs/MPC8536DS_36BIT_defconfig +++ b/configs/MPC8536DS_36BIT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8536DS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/MPC8536DS_SDCARD_defconfig b/configs/MPC8536DS_SDCARD_defconfig index 3b02eb8..d1bad84 100644 --- a/configs/MPC8536DS_SDCARD_defconfig +++ b/configs/MPC8536DS_SDCARD_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8536DS=y CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/MPC8536DS_SPIFLASH_defconfig b/configs/MPC8536DS_SPIFLASH_defconfig index 0453cd2..ad0ae69 100644 --- a/configs/MPC8536DS_SPIFLASH_defconfig +++ b/configs/MPC8536DS_SPIFLASH_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_MPC8536DS=y CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/MPC8536DS_defconfig b/configs/MPC8536DS_defconfig index ceaa9e8..2e9ae63 100644 --- a/configs/MPC8536DS_defconfig +++ b/configs/MPC8536DS_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8536DS=y CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig index faeaa94..ab0c79b 100644 --- a/configs/MPC8544DS_defconfig +++ b/configs/MPC8544DS_defconfig @@ -1,3 +1,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8544DS=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index dfe1fca..11d67ef 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8548CDS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT" +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index ba52e94..6a9ce6a 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -1,3 +1,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8548CDS=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 69c44af..381947f 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8548CDS=y CONFIG_SYS_EXTRA_OPTIONS="LEGACY" +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/MPC8569MDS_ATM_defconfig b/configs/MPC8569MDS_ATM_defconfig index 326983d..719ca84 100644 --- a/configs/MPC8569MDS_ATM_defconfig +++ b/configs/MPC8569MDS_ATM_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8569MDS=y CONFIG_SYS_EXTRA_OPTIONS="ATM" +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/MPC8569MDS_defconfig b/configs/MPC8569MDS_defconfig index 81fb82a..bb1a4fb 100644 --- a/configs/MPC8569MDS_defconfig +++ b/configs/MPC8569MDS_defconfig @@ -1,3 +1,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8569MDS=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/MPC8572DS_36BIT_defconfig b/configs/MPC8572DS_36BIT_defconfig index 0ce85e4..5c76524 100644 --- a/configs/MPC8572DS_36BIT_defconfig +++ b/configs/MPC8572DS_36BIT_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8572DS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT" +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/MPC8572DS_defconfig b/configs/MPC8572DS_defconfig index dde9eb2..2f69b14 100644 --- a/configs/MPC8572DS_defconfig +++ b/configs/MPC8572DS_defconfig @@ -1,3 +1,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_MPC8572DS=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig index 7e83536..a60ce34 100644 --- a/configs/MSI_Primo73_defconfig +++ b/configs/MSI_Primo73_defconfig @@ -7,7 +7,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" -# CONFIG_USB_KEYBOARD is not set CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-primo73" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig index b089e97..3b8e043 100644 --- a/configs/MSI_Primo81_defconfig +++ b/configs/MSI_Primo81_defconfig @@ -10,8 +10,6 @@ CONFIG_VIDEO_LCD_MODE="x:768,y:1024,depth:18,pclk_khz:66000,le:56,ri:60,up:30,lo CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y -CONFIG_USB_MUSB_HOST=y -# CONFIG_USB_KEYBOARD is not set CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-primo81" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -25,3 +23,4 @@ CONFIG_VIDEO_LCD_SPI_CS="PH9" CONFIG_VIDEO_LCD_SPI_SCLK="PH10" CONFIG_VIDEO_LCD_SPI_MOSI="PH11" CONFIG_VIDEO_LCD_SPI_MISO="PH12" +CONFIG_USB_MUSB_HOST=y diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig index 8587bc8..53e023a 100644 --- a/configs/Merrii_A80_Optimus_defconfig +++ b/configs/Merrii_A80_Optimus_defconfig @@ -6,7 +6,6 @@ CONFIG_DRAM_ZQ=123 CONFIG_SYS_CLK_FREQ=1008000000 CONFIG_MMC0_CD_PIN="PH18" # CONFIG_VIDEO is not set -# CONFIG_USB_KEYBOARD is not set CONFIG_DEFAULT_DEVICE_TREE="sun9i-a80-optimus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_IMLS is not set diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index c88eb9b..31d6217 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y CONFIG_VIDEO_COMPOSITE=y +CONFIG_USB0_VBUS_PIN="PB9" CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mini-xplus" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -11,4 +12,3 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_FPGA is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y -CONFIG_USB0_VBUS_PIN="PB9" diff --git a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig index d27fd5e..407f0fb 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_SECBOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index e69f1c4..737921c 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig index 42f7625..a34436e 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_SECBOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index cb86d2a..c6cc9b5 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index be09aab..d32ca80 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig index 20136e3..56cc3c6 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_SECBOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 8f2bbc9..da56dfb 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,36BIT,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig index f760952..fec2697 100644 --- a/configs/P1010RDB-PA_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_NAND_SECBOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index d00b7d2..e45a541 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig index 0f9092b..64ed63a 100644 --- a/configs/P1010RDB-PA_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_NOR_SECBOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 643cc88..fe4c8b5 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 88044b1..3d41cb0 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig index 7ded62b..6afce00 100644 --- a/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_SECBOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index 7da4565..faab1ac 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PA,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig index 286f8da..a76affd 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_SECBOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index 385265d..64963b6 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig index 93e7f89..ea68ffb 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_SECBOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 9176139..0a5403d 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index fd1d4df..f7e9050 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig index a0d7bac..b92c3f3 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_SECBOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 9dc5af2..ae9309a 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,36BIT,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig index 3aa2ca0..9b9a8a2 100644 --- a/configs/P1010RDB-PB_NAND_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_NAND_SECBOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index db41c51..60b3417 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig index 80836a3..17b9941 100644 --- a/configs/P1010RDB-PB_NOR_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_NOR_SECBOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 4ec3893..f3b3b22 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index e938614..5d9607c 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig index 11f75b7..c88b433 100644 --- a/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_SECBOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1010RDB=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index b3a30e7..b390406 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1010RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1010RDB_PB,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig index 59aa9be..7714ac6 100644 --- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD,36BIT" +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig index b8d9c53..29a520b 100644 --- a/configs/P1020MBG-PC_36BIT_defconfig +++ b/configs/P1020MBG-PC_36BIT_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,36BIT" +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig index 0e64e82..c0a0745 100644 --- a/configs/P1020MBG-PC_SDCARD_defconfig +++ b/configs/P1020MBG-PC_SDCARD_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020MBG,SDCARD" +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig index 905b94c..bc408b7 100644 --- a/configs/P1020MBG-PC_defconfig +++ b/configs/P1020MBG-PC_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1020MBG" +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 84934a8..b7d1d2e 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index de86b76..6b55479 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 3ed759f..78db491 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index ca52331..df9dbc9 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,36BIT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 8391b4b..c54b31a 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 7411c67..3c08d4f 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index dc80723..708d5c4 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 089bfae..b7c624f 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PC" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 8f8660c..82492c0 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 959d6d3..e694d5b 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index df4bc85..3cf0b8a 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 2ebb668..6ddf70c 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1020RDB_PD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig index f94345c..b29fcc4 100644 --- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT,SDCARD" +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig index ac4bbd3..63b6471 100644 --- a/configs/P1020UTM-PC_36BIT_defconfig +++ b/configs/P1020UTM-PC_36BIT_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,36BIT" +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig index c4cd42e7..650ffe5 100644 --- a/configs/P1020UTM-PC_SDCARD_defconfig +++ b/configs/P1020UTM-PC_SDCARD_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1020UTM,SDCARD" +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig index aae966b..56ca99c 100644 --- a/configs/P1020UTM-PC_defconfig +++ b/configs/P1020UTM-PC_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1020UTM" +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig index 73f2f51..d246c7b 100644 --- a/configs/P1021RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1021RDB-PC_36BIT_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig index 5befdd9..1bf813f 100644 --- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig index 9838f09..d5c8bd2 100644 --- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig index 5fbc7ce..a9510dc 100644 --- a/configs/P1021RDB-PC_36BIT_defconfig +++ b/configs/P1021RDB-PC_36BIT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,36BIT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig index e238e05..a7de239 100644 --- a/configs/P1021RDB-PC_NAND_defconfig +++ b/configs/P1021RDB-PC_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig index a7a45ec..faf36fe 100644 --- a/configs/P1021RDB-PC_SDCARD_defconfig +++ b/configs/P1021RDB-PC_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig index 59ef5ea..cc9320f 100644 --- a/configs/P1021RDB-PC_SPIFLASH_defconfig +++ b/configs/P1021RDB-PC_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig index 543c28d..9ac36f7 100644 --- a/configs/P1021RDB-PC_defconfig +++ b/configs/P1021RDB-PC_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1021RDB" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1022DS_36BIT_NAND_defconfig b/configs/P1022DS_36BIT_NAND_defconfig index c0edafc..c093ccf 100644 --- a/configs/P1022DS_36BIT_NAND_defconfig +++ b/configs/P1022DS_36BIT_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="36BIT,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1022DS_36BIT_SDCARD_defconfig b/configs/P1022DS_36BIT_SDCARD_defconfig index d85530e..342870d 100644 --- a/configs/P1022DS_36BIT_SDCARD_defconfig +++ b/configs/P1022DS_36BIT_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1022DS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="36BIT,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1022DS_36BIT_SPIFLASH_defconfig b/configs/P1022DS_36BIT_SPIFLASH_defconfig index 1be12cc..40db7b5 100644 --- a/configs/P1022DS_36BIT_SPIFLASH_defconfig +++ b/configs/P1022DS_36BIT_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1022DS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="36BIT,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1022DS_36BIT_defconfig b/configs/P1022DS_36BIT_defconfig index 08d7a6e..d6f2ee4 100644 --- a/configs/P1022DS_36BIT_defconfig +++ b/configs/P1022DS_36BIT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1022DS=y CONFIG_SYS_EXTRA_OPTIONS="36BIT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1022DS_NAND_defconfig b/configs/P1022DS_NAND_defconfig index dbfb562..22e354c 100644 --- a/configs/P1022DS_NAND_defconfig +++ b/configs/P1022DS_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1022DS_SDCARD_defconfig b/configs/P1022DS_SDCARD_defconfig index 9cbcbd5..25ec334 100644 --- a/configs/P1022DS_SDCARD_defconfig +++ b/configs/P1022DS_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1022DS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1022DS_SPIFLASH_defconfig b/configs/P1022DS_SPIFLASH_defconfig index 98a859c..0227f35 100644 --- a/configs/P1022DS_SPIFLASH_defconfig +++ b/configs/P1022DS_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1022DS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1022DS_defconfig b/configs/P1022DS_defconfig index 69a25f7..427c64b 100644 --- a/configs/P1022DS_defconfig +++ b/configs/P1022DS_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1022DS=y CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1023RDB_defconfig b/configs/P1023RDB_defconfig index fc15e4b..ab8f6bb 100644 --- a/configs/P1023RDB_defconfig +++ b/configs/P1023RDB_defconfig @@ -1,3 +1,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1023RDB=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig index 207d3de..ab32765 100644 --- a/configs/P1024RDB_36BIT_defconfig +++ b/configs/P1024RDB_36BIT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,36BIT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig index f69257c..1b4f31c 100644 --- a/configs/P1024RDB_NAND_defconfig +++ b/configs/P1024RDB_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig index d847a0a..d647f8a 100644 --- a/configs/P1024RDB_SDCARD_defconfig +++ b/configs/P1024RDB_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig index c22bfe1..b5790e1 100644 --- a/configs/P1024RDB_SPIFLASH_defconfig +++ b/configs/P1024RDB_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1024RDB,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig index 21a84e3..5dd1cbc 100644 --- a/configs/P1024RDB_defconfig +++ b/configs/P1024RDB_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1024RDB" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig index 302d6e8..509f116 100644 --- a/configs/P1025RDB_36BIT_defconfig +++ b/configs/P1025RDB_36BIT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,36BIT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig index 616225e..6369e39 100644 --- a/configs/P1025RDB_NAND_defconfig +++ b/configs/P1025RDB_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig index 1ba3880..a3cc80a 100644 --- a/configs/P1025RDB_SDCARD_defconfig +++ b/configs/P1025RDB_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig index df648aa..b5d56f7 100644 --- a/configs/P1025RDB_SPIFLASH_defconfig +++ b/configs/P1025RDB_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P1025RDB,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig index a0d1a2c..05c347e 100644 --- a/configs/P1025RDB_defconfig +++ b/configs/P1025RDB_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P1025RDB" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 2c4bea3..e86ff8c 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 9d110db..d97c6bc 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index c41bbf9..8c15726 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 8ae1928..b93ce08 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,36BIT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 4492e09..3184f5e 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -5,3 +5,5 @@ CONFIG_SPL=y CONFIG_TPL=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 95f3d91..4328967 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index d6f0548..55cb86c 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index f871019..b5496fc 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P1_P2_RDB_PC=y CONFIG_SYS_EXTRA_OPTIONS="P2020RDB" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 028235a..a3e8f9c 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index ac1d678..dc022a1 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P2041RDB_SECURE_BOOT_defconfig b/configs/P2041RDB_SECURE_BOOT_defconfig index d0facae..3fccb2b 100644 --- a/configs/P2041RDB_SECURE_BOOT_defconfig +++ b/configs/P2041RDB_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 30953a7..f748ba3 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig index 74abe7d..4d62252 100644 --- a/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig +++ b/configs/P2041RDB_SRIO_PCIE_BOOT_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index b4b1489..9dba9a6 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P2041RDB=y CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P3041DS_NAND_SECURE_BOOT_defconfig b/configs/P3041DS_NAND_SECURE_BOOT_defconfig index 2f18bc1..6e4b88e 100644 --- a/configs/P3041DS_NAND_SECURE_BOOT_defconfig +++ b/configs/P3041DS_NAND_SECURE_BOOT_defconfig @@ -1,5 +1,7 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index a076390..d075e8f 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index c16dc96..5f1c198 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P3041DS_SECURE_BOOT_defconfig b/configs/P3041DS_SECURE_BOOT_defconfig index 7c76951..307f6d7 100644 --- a/configs/P3041DS_SECURE_BOOT_defconfig +++ b/configs/P3041DS_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index 26e45f6..6112639 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig index 71db82d..24a79ce 100644 --- a/configs/P3041DS_SRIO_PCIE_BOOT_defconfig +++ b/configs/P3041DS_SRIO_PCIE_BOOT_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index 0879537..0fed50f 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P3041DS=y CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 1e8bbf7..74a1452 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P4080DS_SECURE_BOOT_defconfig b/configs/P4080DS_SECURE_BOOT_defconfig index 33a9fd6..0dd1f32 100644 --- a/configs/P4080DS_SECURE_BOOT_defconfig +++ b/configs/P4080DS_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index e55be85..b7bfc38 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig index b3f6b69..766db5e 100644 --- a/configs/P4080DS_SRIO_PCIE_BOOT_defconfig +++ b/configs/P4080DS_SRIO_PCIE_BOOT_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index 5e5cea9..b0a6bdf 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P4080DS=y CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig index 98cdd35..c89ec85 100644 --- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig +++ b/configs/P5020DS_NAND_SECURE_BOOT_defconfig @@ -1,5 +1,7 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig index a071029..64ba6e9 100644 --- a/configs/P5020DS_NAND_defconfig +++ b/configs/P5020DS_NAND_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig index 5431491..796e9a1 100644 --- a/configs/P5020DS_SDCARD_defconfig +++ b/configs/P5020DS_SDCARD_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig index 26a418a..27ae488 100644 --- a/configs/P5020DS_SECURE_BOOT_defconfig +++ b/configs/P5020DS_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig index 65f0708..65cc600 100644 --- a/configs/P5020DS_SPIFLASH_defconfig +++ b/configs/P5020DS_SPIFLASH_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig index 66b7d6f..65e9d2f 100644 --- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig +++ b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig index a6d8839..bd06987 100644 --- a/configs/P5020DS_defconfig +++ b/configs/P5020DS_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5020DS=y CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P5040DS_NAND_SECURE_BOOT_defconfig b/configs/P5040DS_NAND_SECURE_BOOT_defconfig index a6cc7c4..3027031 100644 --- a/configs/P5040DS_NAND_SECURE_BOOT_defconfig +++ b/configs/P5040DS_NAND_SECURE_BOOT_defconfig @@ -1,5 +1,7 @@ -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SECURE_BOOT,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index 0d61782..b2f5cda 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index 498fe51..950df55 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P5040DS_SECURE_BOOT_defconfig b/configs/P5040DS_SECURE_BOOT_defconfig index 54d9b80..d0bc383 100644 --- a/configs/P5040DS_SECURE_BOOT_defconfig +++ b/configs/P5040DS_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 9a37c0e..0dbc3eb 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index 6df742e..5da5a3c 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P5040DS=y CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1023RDB_NAND_defconfig b/configs/T1023RDB_NAND_defconfig index 3ee42d6..836bde4 100644 --- a/configs/T1023RDB_NAND_defconfig +++ b/configs/T1023RDB_NAND_defconfig @@ -6,3 +6,5 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1023RDB_SDCARD_defconfig b/configs/T1023RDB_SDCARD_defconfig index ed67945..7bc7f54 100644 --- a/configs/T1023RDB_SDCARD_defconfig +++ b/configs/T1023RDB_SDCARD_defconfig @@ -6,3 +6,5 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig index 76e3e91..6a3ccca 100644 --- a/configs/T1023RDB_SECURE_BOOT_defconfig +++ b/configs/T1023RDB_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1023RDB_SPIFLASH_defconfig b/configs/T1023RDB_SPIFLASH_defconfig index e7f4525..83b14a8 100644 --- a/configs/T1023RDB_SPIFLASH_defconfig +++ b/configs/T1023RDB_SPIFLASH_defconfig @@ -6,3 +6,5 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1023RDB_defconfig b/configs/T1023RDB_defconfig index 8ff03a5..c4b72d4 100644 --- a/configs/T1023RDB_defconfig +++ b/configs/T1023RDB_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1024QDS_D4_SECURE_BOOT_defconfig b/configs/T1024QDS_D4_SECURE_BOOT_defconfig index 06a9619..f69c49d 100644 --- a/configs/T1024QDS_D4_SECURE_BOOT_defconfig +++ b/configs/T1024QDS_D4_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T102XQDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1024QDS_NAND_defconfig b/configs/T1024QDS_NAND_defconfig index c49facf..caedd39 100644 --- a/configs/T1024QDS_NAND_defconfig +++ b/configs/T1024QDS_NAND_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T102XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1024QDS_SDCARD_defconfig b/configs/T1024QDS_SDCARD_defconfig index 3a3beb1..844d9a5 100644 --- a/configs/T1024QDS_SDCARD_defconfig +++ b/configs/T1024QDS_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T102XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1024QDS_SECURE_BOOT_defconfig b/configs/T1024QDS_SECURE_BOOT_defconfig index b0890a4..9f80de0 100644 --- a/configs/T1024QDS_SECURE_BOOT_defconfig +++ b/configs/T1024QDS_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T102XQDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1024QDS_SPIFLASH_defconfig b/configs/T1024QDS_SPIFLASH_defconfig index df3ca94..dc5a460 100644 --- a/configs/T1024QDS_SPIFLASH_defconfig +++ b/configs/T1024QDS_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T102XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1024QDS_defconfig b/configs/T1024QDS_defconfig index 93588b7..74138c7 100644 --- a/configs/T1024QDS_defconfig +++ b/configs/T1024QDS_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T102XQDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 6f4f026..7ae0433 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T102XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 53c5c8c..3a664f8 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T102XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig index 65e9a5a..8f4378b 100644 --- a/configs/T1024RDB_SECURE_BOOT_defconfig +++ b/configs/T1024RDB_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 60aee0d..36f2208 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T102XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 2da2ea7..fba47c2 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T102XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1040D4RDB_NAND_defconfig b/configs/T1040D4RDB_NAND_defconfig index 3051f0c..0af8c8d 100644 --- a/configs/T1040D4RDB_NAND_defconfig +++ b/configs/T1040D4RDB_NAND_defconfig @@ -1,6 +1,8 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1040D4RDB_SDCARD_defconfig b/configs/T1040D4RDB_SDCARD_defconfig index 6c10c50..dc9ee34 100644 --- a/configs/T1040D4RDB_SDCARD_defconfig +++ b/configs/T1040D4RDB_SDCARD_defconfig @@ -1,6 +1,8 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig index f779126..6a891a6 100644 --- a/configs/T1040D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1040D4RDB_SECURE_BOOT_defconfig @@ -1,5 +1,7 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1040D4RDB_SPIFLASH_defconfig b/configs/T1040D4RDB_SPIFLASH_defconfig index 6614e34..4628576 100644 --- a/configs/T1040D4RDB_SPIFLASH_defconfig +++ b/configs/T1040D4RDB_SPIFLASH_defconfig @@ -1,6 +1,8 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1040D4RDB_defconfig b/configs/T1040D4RDB_defconfig index ce0cfa3..6adc196 100644 --- a/configs/T1040D4RDB_defconfig +++ b/configs/T1040D4RDB_defconfig @@ -1,5 +1,7 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040D4RDB,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1040QDS_D4_defconfig b/configs/T1040QDS_D4_defconfig index 31b3b10..8c4320b 100644 --- a/configs/T1040QDS_D4_defconfig +++ b/configs/T1040QDS_D4_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T1040QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1040QDS_SECURE_BOOT_defconfig b/configs/T1040QDS_SECURE_BOOT_defconfig index abb876f..607c280 100644 --- a/configs/T1040QDS_SECURE_BOOT_defconfig +++ b/configs/T1040QDS_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T1040QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1040QDS_defconfig b/configs/T1040QDS_defconfig index 3766524..1f200f9 100644 --- a/configs/T1040QDS_defconfig +++ b/configs/T1040QDS_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T1040QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1040RDB_NAND_defconfig b/configs/T1040RDB_NAND_defconfig index d4883b8..146448d 100644 --- a/configs/T1040RDB_NAND_defconfig +++ b/configs/T1040RDB_NAND_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1040RDB_SDCARD_defconfig b/configs/T1040RDB_SDCARD_defconfig index 46e7c72..f363067 100644 --- a/configs/T1040RDB_SDCARD_defconfig +++ b/configs/T1040RDB_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig index 8995e89..55d2a5e 100644 --- a/configs/T1040RDB_SECURE_BOOT_defconfig +++ b/configs/T1040RDB_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,SECURE_BOOT,T1040RDB" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1040RDB_SPIFLASH_defconfig b/configs/T1040RDB_SPIFLASH_defconfig index e0956b3..c6fd93a 100644 --- a/configs/T1040RDB_SPIFLASH_defconfig +++ b/configs/T1040RDB_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1040RDB_defconfig b/configs/T1040RDB_defconfig index 3ae358d..810d1d8 100644 --- a/configs/T1040RDB_defconfig +++ b/configs/T1040RDB_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1040,T1040RDB" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index fa4c250..c06e335 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -1,6 +1,8 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 12644d6..b86554a 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -1,6 +1,8 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig index e806591..8130f7c 100644 --- a/configs/T1042D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig @@ -1,5 +1,7 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 2504499..ca7243a 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -1,6 +1,8 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 3df7496..4e44c89 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -1,5 +1,7 @@ -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4" CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042D4RDB,T104XD4RDB,SYS_FSL_DDR4" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1042RDB_PI_NAND_defconfig b/configs/T1042RDB_PI_NAND_defconfig index 04af1b8..ff0052a 100644 --- a/configs/T1042RDB_PI_NAND_defconfig +++ b/configs/T1042RDB_PI_NAND_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1042RDB_PI_SDCARD_defconfig b/configs/T1042RDB_PI_SDCARD_defconfig index cf093fd..c19bd8b 100644 --- a/configs/T1042RDB_PI_SDCARD_defconfig +++ b/configs/T1042RDB_PI_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1042RDB_PI_SPIFLASH_defconfig b/configs/T1042RDB_PI_SPIFLASH_defconfig index aba0d18..fbce984 100644 --- a/configs/T1042RDB_PI_SPIFLASH_defconfig +++ b/configs/T1042RDB_PI_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T104XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1042RDB_PI_defconfig b/configs/T1042RDB_PI_defconfig index 7ad65ba..6353543 100644 --- a/configs/T1042RDB_PI_defconfig +++ b/configs/T1042RDB_PI_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB_PI" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig index 639fc94..39121ca 100644 --- a/configs/T1042RDB_SECURE_BOOT_defconfig +++ b/configs/T1042RDB_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,SECURE_BOOT,T1042RDB" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T1042RDB_defconfig b/configs/T1042RDB_defconfig index 670c87a..e5888e3 100644 --- a/configs/T1042RDB_defconfig +++ b/configs/T1042RDB_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T104XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T1042,T1042RDB" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index e6b1f46..3610370 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T208XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index d48eb87..37cb6b7 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T208XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 5f9a72b..0f27b07 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index c0251af..85a3689 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T208XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 018ee6f..8f276fa 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF4000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index eaa0792..c681528 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 512d60f..ab4a7be 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T208XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index d6fc340..5d0f43a 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T208XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2080RDB_SECURE_BOOT_defconfig b/configs/T2080RDB_SECURE_BOOT_defconfig index 28183f6..43a76bc 100644 --- a/configs/T2080RDB_SECURE_BOOT_defconfig +++ b/configs/T2080RDB_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T208XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 9733b36..1b230b1 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T208XRDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig index 56e5ce1..af1a232 100644 --- a/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080RDB_SRIO_PCIE_BOOT_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF4000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 2475ce3..cbd1220 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T208XRDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2080" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2081QDS_NAND_defconfig b/configs/T2081QDS_NAND_defconfig index 591b700..9ef946b 100644 --- a/configs/T2081QDS_NAND_defconfig +++ b/configs/T2081QDS_NAND_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T208XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2081QDS_SDCARD_defconfig b/configs/T2081QDS_SDCARD_defconfig index 45c7bca..8728f2d 100644 --- a/configs/T2081QDS_SDCARD_defconfig +++ b/configs/T2081QDS_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T208XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2081QDS_SPIFLASH_defconfig b/configs/T2081QDS_SPIFLASH_defconfig index 2784df6..95c37dc 100644 --- a/configs/T2081QDS_SPIFLASH_defconfig +++ b/configs/T2081QDS_SPIFLASH_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T208XQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig index 55fd6cc..1b0ac47 100644 --- a/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2081QDS_SRIO_PCIE_BOOT_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF4000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T2081QDS_defconfig b/configs/T2081QDS_defconfig index 5942524..8f3bcf6 100644 --- a/configs/T2081QDS_defconfig +++ b/configs/T2081QDS_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T208XQDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T2081" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T4160QDS_NAND_defconfig b/configs/T4160QDS_NAND_defconfig index 16cda07..3a35060 100644 --- a/configs/T4160QDS_NAND_defconfig +++ b/configs/T4160QDS_NAND_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T4240QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T4160QDS_SDCARD_defconfig b/configs/T4160QDS_SDCARD_defconfig index d23c887..ef7135e 100644 --- a/configs/T4160QDS_SDCARD_defconfig +++ b/configs/T4160QDS_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T4240QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T4160QDS_SECURE_BOOT_defconfig b/configs/T4160QDS_SECURE_BOOT_defconfig index 0fe99d2..d08f98c 100644 --- a/configs/T4160QDS_SECURE_BOOT_defconfig +++ b/configs/T4160QDS_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T4160QDS_defconfig b/configs/T4160QDS_defconfig index bab1712..e44af1e 100644 --- a/configs/T4160QDS_defconfig +++ b/configs/T4160QDS_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T4160RDB_defconfig b/configs/T4160RDB_defconfig index 9ca984c..1cc929f 100644 --- a/configs/T4160RDB_defconfig +++ b/configs/T4160RDB_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T4240RDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T4240QDS_NAND_defconfig b/configs/T4240QDS_NAND_defconfig index 130a614..31e1f53 100644 --- a/configs/T4240QDS_NAND_defconfig +++ b/configs/T4240QDS_NAND_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T4240QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T4240QDS_SDCARD_defconfig b/configs/T4240QDS_SDCARD_defconfig index 8eb5577..a464136 100644 --- a/configs/T4240QDS_SDCARD_defconfig +++ b/configs/T4240QDS_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T4240QDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T4240QDS_SECURE_BOOT_defconfig b/configs/T4240QDS_SECURE_BOOT_defconfig index d983e9a..094f305 100644 --- a/configs/T4240QDS_SECURE_BOOT_defconfig +++ b/configs/T4240QDS_SECURE_BOOT_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig index edd083a..60afd9e 100644 --- a/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T4240QDS_SRIO_PCIE_BOOT_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF4000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T4240QDS_defconfig b/configs/T4240QDS_defconfig index cd9df0f..7fe54bf 100644 --- a/configs/T4240QDS_defconfig +++ b/configs/T4240QDS_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T4240QDS=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 09f8f65..0d0d26c 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_T4240RDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index e1abd8a..01221b0 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_T4240RDB=y CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/TWR-P1025_defconfig b/configs/TWR-P1025_defconfig index c86900a..e6d34e8 100644 --- a/configs/TWR-P1025_defconfig +++ b/configs/TWR-P1025_defconfig @@ -2,3 +2,5 @@ CONFIG_PPC=y CONFIG_MPC85xx=y CONFIG_TARGET_P1_TWR=y CONFIG_SYS_EXTRA_OPTIONS="TWR_P1025" +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/TZX-Q8-713B7_defconfig b/configs/TZX-Q8-713B7_defconfig index 4ef80db..f5e3574 100644 --- a/configs/TZX-Q8-713B7_defconfig +++ b/configs/TZX-Q8-713B7_defconfig @@ -11,7 +11,6 @@ CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo: CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-tzx-q8-713b7" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -19,3 +18,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=2,AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_USB_MUSB_HOST=y diff --git a/configs/UCP1020_SPIFLASH_defconfig b/configs/UCP1020_SPIFLASH_defconfig index 9e41048..267dc0f 100644 --- a/configs/UCP1020_SPIFLASH_defconfig +++ b/configs/UCP1020_SPIFLASH_defconfig @@ -6,3 +6,5 @@ CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n" CONFIG_AUTOBOOT_STOP_STR="\x1b" CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig index cada7bb..6718865 100644 --- a/configs/UCP1020_defconfig +++ b/configs/UCP1020_defconfig @@ -6,3 +6,5 @@ CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc>\" to stop\n" CONFIG_AUTOBOOT_STOP_STR="\x1b" CONFIG_SPI_FLASH=y CONFIG_SYS_PROMPT="B$ " +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index 99a8c31..5417814 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -17,7 +17,6 @@ CONFIG_VIDEO_LCD_RESET="PG11" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_TL059WV5C0=y -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-utoo-p66" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -26,3 +25,4 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set # CONFIG_REQUIRE_SERIAL_CONSOLE is not set +CONFIG_USB_MUSB_HOST=y diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index 27f2e2b..e26816c 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -16,7 +16,6 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-yones-toptech-bd1078" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -24,3 +23,4 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_USB_MUSB_HOST=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 65efa9d..f84f57d 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -5,5 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index c0bc3c5..c0830db 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -9,6 +9,8 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis" # CONFIG_CMD_FPGA is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/arndale_defconfig b/configs/arndale_defconfig index 1f94ff0..3a1049f 100644 --- a/configs/arndale_defconfig +++ b/configs/arndale_defconfig @@ -6,6 +6,8 @@ CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_SOUND=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_COMPAT=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y @@ -13,6 +15,4 @@ CONFIG_SOUND_MAX98095=y CONFIG_SOUND_WM8994=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y CONFIG_SYS_PROMPT="ARNDALE # " diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index cdcd9de..104d53d 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_SUNXI=y CONFIG_MACH_SUN4I=y CONFIG_DRAM_CLK=384 CONFIG_DRAM_EMR1=4 +CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB2_VBUS_PIN="PH12" CONFIG_VIDEO_COMPOSITE=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-ba10-tvbox" @@ -14,4 +15,3 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_EMAC" # CONFIG_CMD_FPGA is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_MUSB_HOST=y -CONFIG_USB0_VBUS_PIN="PB9" diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index 7f92ead..13bd282 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -19,6 +19,8 @@ CONFIG_OF_CONTROL=y CONFIG_CPU=y CONFIG_DM_PCI=y CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y diff --git a/configs/caddy2_defconfig b/configs/caddy2_defconfig index 35efa7f..343432c 100644 --- a/configs/caddy2_defconfig +++ b/configs/caddy2_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC83xx=y CONFIG_TARGET_VME8349=y CONFIG_SYS_EXTRA_OPTIONS="CADDY2" # CONFIG_CMD_SETEXPR is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/cgtqmx6qeval_defconfig b/configs/cgtqmx6qeval_defconfig index af322bc..74f9527 100644 --- a/configs/cgtqmx6qeval_defconfig +++ b/configs/cgtqmx6qeval_defconfig @@ -1,10 +1,9 @@ CONFIG_ARM=y CONFIG_TARGET_CGTQMX6EVAL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q" -CONFIG_CMD_NET=y -CONFIG_DM=y -CONFIG_DM_THERMAL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SYS_PROMPT="CGT-QMX6-Quad U-Boot > " +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 66fc382..21c35e3 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -8,6 +8,9 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL" # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y # CONFIG_CMD_FPGA is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -21,12 +24,8 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_CMD_SF=y -CONFIG_CMD_I2C=y CONFIG_USB=y -CONFIG_CMD_USB=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_MX6=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig index 581df0a..df3a624 100644 --- a/configs/coreboot-x86_defconfig +++ b/configs/coreboot-x86_defconfig @@ -12,5 +12,7 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_DM_PCI=y CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_SYS_VSNPRINTF=y diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index aa1232d..4fc1827 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -19,6 +19,8 @@ CONFIG_OF_CONTROL=y CONFIG_CPU=y CONFIG_DM_PCI=y CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_DM_RTC=y diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index bf0ee84..4c1b573 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -10,8 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra114-dalmore" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y -CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y +CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index 0ff6706..e22f5f7 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -1,6 +1,6 @@ -CONFIG_SPL=y CONFIG_ARM=y CONFIG_TARGET_DB_88F6820_GP=y +CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set diff --git a/configs/e2220-1170_defconfig b/configs/e2220-1170_defconfig index 455e789..72e5ab3 100644 --- a/configs/e2220-1170_defconfig +++ b/configs/e2220-1170_defconfig @@ -10,8 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra210-e2220-1170" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y -CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y +CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/forfun_q88db_defconfig b/configs/forfun_q88db_defconfig index 610a062..30cead7 100644 --- a/configs/forfun_q88db_defconfig +++ b/configs/forfun_q88db_defconfig @@ -10,7 +10,6 @@ CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:40,up:31,lo: CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-forfun-q88db" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -18,3 +17,4 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_USB_MUSB_HOST=y diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig index 098284d..417a89c 100644 --- a/configs/ga10h_v1_1_defconfig +++ b/configs/ga10h_v1_1_defconfig @@ -14,7 +14,6 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun8i-a33-ga10h-v1.1" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -25,3 +24,4 @@ CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5" CONFIG_AXP221_DLDO1_VOLT=3300 CONFIG_AXP221_ALDO1_VOLT=3000 CONFIG_USB_EHCI_HCD=y +CONFIG_USB_MUSB_HOST=y diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig index d81f941..e294cac 100644 --- a/configs/gwventana_defconfig +++ b/configs/gwventana_defconfig @@ -7,5 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_DM=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y CONFIG_DM_SERIAL=y CONFIG_SYS_PROMPT="Ventana > " diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index 22d0caf..211cb86 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -11,7 +11,6 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3f" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -19,3 +18,4 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_USB_MUSB_HOST=y diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index c296c0c..35f08e5 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -11,7 +11,6 @@ CONFIG_VIDEO_LCD_MODE="x:1024,y:768,depth:24,pclk_khz:65000,le:159,ri:160,up:22, CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-inet-3w" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -19,3 +18,4 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_USB_MUSB_HOST=y diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index f958c31..bb8d080 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -10,7 +10,6 @@ CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" -CONFIG_USB_MUSB_HOST=y CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-inet-86vs" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL=y @@ -18,3 +17,4 @@ CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_FPGA is not set +CONFIG_USB_MUSB_HOST=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index 1dc2679..8930ebe 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -10,8 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-jetson-tk1" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y -CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y +CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/kmcoge4_defconfig b/configs/kmcoge4_defconfig index aa0e004..519b39d 100644 --- a/configs/kmcoge4_defconfig +++ b/configs/kmcoge4_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="KMCOGE4" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/kmlion1_defconfig b/configs/kmlion1_defconfig index 48fe188..f948b2b 100644 --- a/configs/kmlion1_defconfig +++ b/configs/kmlion1_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="KMLION1" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig index 8c6a5c4..940da92 100644 --- a/configs/ls1021aqds_ddr4_nor_defconfig +++ b/configs/ls1021aqds_ddr4_nor_defconfig @@ -2,3 +2,5 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" # CONFIG_CMD_SETEXPR is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig index efcef64..68bd117 100644 --- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig +++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig @@ -2,3 +2,5 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,LPUART" # CONFIG_CMD_SETEXPR is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index d3a12b1..613fc28 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -3,3 +3,5 @@ CONFIG_TARGET_LS1021AQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" # CONFIG_CMD_SETEXPR is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 045878f..97d08f1 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -2,3 +2,5 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" # CONFIG_CMD_SETEXPR is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index f28cfb3..af76fa0 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -1,3 +1,5 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y # CONFIG_CMD_SETEXPR is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig index 081e618..b2f6832 100644 --- a/configs/ls1021aqds_nor_lpuart_defconfig +++ b/configs/ls1021aqds_nor_lpuart_defconfig @@ -2,3 +2,5 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y CONFIG_SYS_EXTRA_OPTIONS="LPUART" # CONFIG_CMD_SETEXPR is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 6a1f711..7318eeb 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -1,10 +1,12 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021AQDS=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds" CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds" CONFIG_OF_CONTROL=y CONFIG_DM=y -CONFIG_DM_SPI=y CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_DM_SPI=y diff --git a/configs/ls1021aqds_sdcard_defconfig b/configs/ls1021aqds_sdcard_defconfig index e1b4854..0fb637e 100644 --- a/configs/ls1021aqds_sdcard_defconfig +++ b/configs/ls1021aqds_sdcard_defconfig @@ -3,3 +3,5 @@ CONFIG_TARGET_LS1021AQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" # CONFIG_CMD_SETEXPR is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index f51f2fd..0d2c9a0 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -2,3 +2,5 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT" # CONFIG_CMD_SETEXPR is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 939be78..0a4b3ea 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -1,3 +1,5 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y # CONFIG_CMD_SETEXPR is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index 8f34613..d7afca9 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -2,3 +2,5 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y CONFIG_SYS_EXTRA_OPTIONS="LPUART" # CONFIG_CMD_SETEXPR is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 420cfe7..4e5f100 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -1,10 +1,12 @@ CONFIG_ARM=y CONFIG_TARGET_LS1021ATWR=y +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr" CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr" CONFIG_OF_CONTROL=y CONFIG_DM=y -CONFIG_DM_SPI=y CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_DM_SPI=y diff --git a/configs/ls1021atwr_sdcard_defconfig b/configs/ls1021atwr_sdcard_defconfig index cfc7b524..f1709ed 100644 --- a/configs/ls1021atwr_sdcard_defconfig +++ b/configs/ls1021atwr_sdcard_defconfig @@ -3,3 +3,5 @@ CONFIG_TARGET_LS1021ATWR=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" # CONFIG_CMD_SETEXPR is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls2085aqds_defconfig b/configs/ls2085aqds_defconfig index 00b062b..fb5ab2f 100644 --- a/configs/ls2085aqds_defconfig +++ b/configs/ls2085aqds_defconfig @@ -7,5 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_DM_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2085aqds_nand_defconfig b/configs/ls2085aqds_nand_defconfig index b9dd651..10eda97 100644 --- a/configs/ls2085aqds_nand_defconfig +++ b/configs/ls2085aqds_nand_defconfig @@ -3,3 +3,5 @@ CONFIG_TARGET_LS2085AQDS=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" # CONFIG_CMD_SETEXPR is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/ls2085ardb_defconfig b/configs/ls2085ardb_defconfig index c7dae4b..e80b3c1 100644 --- a/configs/ls2085ardb_defconfig +++ b/configs/ls2085ardb_defconfig @@ -7,5 +7,7 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4" CONFIG_OF_CONTROL=y CONFIG_DM=y CONFIG_DM_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2085ardb_nand_defconfig b/configs/ls2085ardb_nand_defconfig index 8539307..96a0dfd 100644 --- a/configs/ls2085ardb_nand_defconfig +++ b/configs/ls2085ardb_nand_defconfig @@ -3,3 +3,5 @@ CONFIG_TARGET_LS2085ARDB=y CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND" # CONFIG_CMD_SETEXPR is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index b6eefaf..29159a1 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL" CONFIG_ARM=y CONFIG_TARGET_MX6UL_14X14_EVK=y CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6UL" diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 44bae73..274e955 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -10,12 +10,12 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-nyan-big" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y -CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_CROS_EC_KEYB=y +CONFIG_TEGRA114_SPI=y CONFIG_DISPLAY_PORT=y CONFIG_VIDEO_TEGRA124=y CONFIG_USB=y diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig index f0facf3..9c3b6d6 100644 --- a/configs/odroid-xu3_defconfig +++ b/configs/odroid-xu3_defconfig @@ -5,12 +5,11 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5422-odroidxu3" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_CMD_NET=y CONFIG_DM_I2C=y CONFIG_DM_I2C_COMPAT=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_VIDEO_BRIDGE=y CONFIG_SYS_PROMPT="ODROID-XU3 # " +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index cd7d21f..71a9a75 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -10,8 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y -CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y +CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 5fd2a54..877a905 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -10,8 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y -CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y +CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index a02e2ed..323a2d3 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -5,30 +5,30 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi" CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_SPI_FLASH=y CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_CROS_EC_KEYB=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_I2C_MUX=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_I2C_MUX=y +CONFIG_I2C_ARB_GPIO_CHALLENGE=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_TPS65090=y +CONFIG_DM_REGULATOR=y +CONFIG_REGULATOR_TPS65090=y +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y CONFIG_SOUND_MAX98095=y CONFIG_SOUND_WM8994=y -CONFIG_DM_I2C=y -CONFIG_DM_PMIC=y -CONFIG_DM_REGULATOR=y -CONFIG_PMIC_TPS65090=y -CONFIG_REGULATOR_TPS65090=y -CONFIG_DM_I2C_COMPAT=y -CONFIG_I2C_ARB_GPIO_CHALLENGE=y -CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y +CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_ERRNO_STR=y -CONFIG_VIDEO_BRIDGE=y -CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_SYS_PROMPT="Peach-Pi # " diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index e9fc6ae..6a08296 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -5,30 +5,30 @@ CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit" CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_SPI_FLASH=y CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SPI=y CONFIG_CROS_EC_KEYB=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_I2C_MUX=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_TUNNEL=y +CONFIG_I2C_MUX=y +CONFIG_I2C_ARB_GPIO_CHALLENGE=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_TPS65090=y +CONFIG_DM_REGULATOR=y +CONFIG_REGULATOR_TPS65090=y +CONFIG_VIDEO_BRIDGE=y +CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y CONFIG_SOUND_MAX98095=y CONFIG_SOUND_WM8994=y -CONFIG_DM_I2C=y -CONFIG_DM_PMIC=y -CONFIG_DM_REGULATOR=y -CONFIG_PMIC_TPS65090=y -CONFIG_REGULATOR_TPS65090=y -CONFIG_DM_I2C_COMPAT=y -CONFIG_I2C_ARB_GPIO_CHALLENGE=y -CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y +CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_ERRNO_STR=y -CONFIG_VIDEO_BRIDGE=y -CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_SYS_PROMPT="Peach-Pit # " diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig new file mode 100644 index 0000000..4128193 --- /dev/null +++ b/configs/picosam9g45_defconfig @@ -0,0 +1,12 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_TARGET_PICOSAM9G45=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC" +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +# CONFIG_CMD_SETEXPR is not set diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index 27daa62..b05c722 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -3,3 +3,5 @@ CONFIG_MPC85xx=y CONFIG_TARGET_QEMU_PPCE500=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_NETDEVICES=y +CONFIG_E1000=y diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index e579c36..0675646 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -15,6 +15,8 @@ CONFIG_CMD_BOOTSTAGE=y CONFIG_OF_CONTROL=y CONFIG_CPU=y CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_111=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 874a26b..85ff95d 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -13,16 +13,22 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_OF_HOSTFILE=y +CONFIG_CLK=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DEVRES=y CONFIG_DM_PCI=y CONFIG_PCI_SANDBOX=y -CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_SANDBOX=y +CONFIG_SPI_FLASH=y CONFIG_CMD_CROS_EC=y -CONFIG_CMD_DHRYSTONE=y CONFIG_CROS_EC=y CONFIG_CROS_EC_SANDBOX=y +CONFIG_RESET=y CONFIG_DM_ETH=y CONFIG_CROS_EC_KEYB=y +CONFIG_LED=y +CONFIG_LED_GPIO=y CONFIG_SANDBOX_SERIAL=y CONFIG_TPM_TIS_SANDBOX=y CONFIG_SYS_I2C_SANDBOX=y @@ -32,25 +38,19 @@ CONFIG_DM_PMIC=y CONFIG_DM_PMIC_SANDBOX=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_SANDBOX=y +CONFIG_RAM=y CONFIG_SOUND=y CONFIG_SOUND_SANDBOX=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EMUL=y CONFIG_USB_STORAGE=y +CONFIG_DM_MMC=y CONFIG_DM_RTC=y CONFIG_SYS_VSNPRINTF=y +CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y CONFIG_UNIT_TEST=y CONFIG_UT_TIME=y CONFIG_UT_DM=y CONFIG_UT_ENV=y -CONFIG_CLK=y -CONFIG_RESET=y -CONFIG_RAM=y -CONFIG_DM_MMC=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_SYSCON=y -CONFIG_REGMAP=y -CONFIG_DEVRES=y diff --git a/configs/smdk5250_defconfig b/configs/smdk5250_defconfig index f0c9e01..c9fd79f 100644 --- a/configs/smdk5250_defconfig +++ b/configs/smdk5250_defconfig @@ -6,7 +6,16 @@ CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_SOUND=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_SPI_FLASH=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_COMPAT=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_MAX77686=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_MAX77686=y +CONFIG_VIDEO_BRIDGE=y CONFIG_SOUND=y CONFIG_I2S=y CONFIG_I2S_SAMSUNG=y @@ -14,14 +23,5 @@ CONFIG_SOUND_MAX98095=y CONFIG_SOUND_WM8994=y CONFIG_USB=y CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_I2C_COMPAT=y -CONFIG_DM_PMIC=y -CONFIG_DM_REGULATOR=y -CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y CONFIG_ERRNO_STR=y -CONFIG_DM_PMIC_MAX77686=y -CONFIG_DM_REGULATOR_MAX77686=y -CONFIG_VIDEO_BRIDGE=y CONFIG_SYS_PROMPT="SMDK5250 # " diff --git a/configs/smdk5420_defconfig b/configs/smdk5420_defconfig index 253fbe5..e90c765 100644 --- a/configs/smdk5420_defconfig +++ b/configs/smdk5420_defconfig @@ -6,12 +6,11 @@ CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set CONFIG_SPI_FLASH=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_CMD_NET=y CONFIG_DM_I2C=y CONFIG_DM_I2C_COMPAT=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_VIDEO_BRIDGE=y CONFIG_SYS_PROMPT="SMDK5420 # " +CONFIG_USB=y +CONFIG_DM_USB=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index 4a90f0a..f5decd5 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -6,39 +6,39 @@ CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_SOUND=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_SPI_FLASH=y CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_KEYB=y -CONFIG_SOUND=y -CONFIG_I2S=y -CONFIG_I2S_SAMSUNG=y -CONFIG_SOUND_MAX98095=y -CONFIG_SOUND_WM8994=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_PMIC=y -CONFIG_DM_REGULATOR=y -CONFIG_PMIC_TPS65090=y -CONFIG_REGULATOR_TPS65090=y -CONFIG_DM_I2C_COMPAT=y -CONFIG_I2C_ARB_GPIO_CHALLENGE=y -CONFIG_I2C_MUX=y -CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y -CONFIG_ERRNO_STR=y -CONFIG_DM_PMIC_MAX77686=y -CONFIG_DM_REGULATOR_MAX77686=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_S5P=y -CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_BASE=0x12c30000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DM_I2C=y +CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_LDO=y +CONFIG_I2C_MUX=y +CONFIG_I2C_ARB_GPIO_CHALLENGE=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_MAX77686=y CONFIG_PMIC_S5M8767=y +CONFIG_PMIC_TPS65090=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_MAX77686=y CONFIG_REGULATOR_S5M8767=y +CONFIG_REGULATOR_TPS65090=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_VIDEO_BRIDGE_NXP_PTN3460=y CONFIG_SYS_PROMPT="snow # " +CONFIG_SOUND=y +CONFIG_I2S=y +CONFIG_I2S_SAMSUNG=y +CONFIG_SOUND_MAX98095=y +CONFIG_SOUND_WM8994=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_ERRNO_STR=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index f406db7..cb460e8 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -1,20 +1,18 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_TARGET_SOCFPGA_ARRIA5=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk" CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x00800000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y -CONFIG_SPI_FLASH=y CONFIG_SPL_DM=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_DM_SEQ_ALIAS=y -CONFIG_SPL_SIMPLE_BUS=y -CONFIG_DM_SPI=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPI_FLASH=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_GPIO=y +CONFIG_DWAPB_GPIO=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 75207bf..8a7f8cc 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -1,23 +1,18 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_TARGET_SOCFPGA_CYCLONE5=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x00800000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DM=y CONFIG_SPI_FLASH=y CONFIG_DM_ETH=y -CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y -CONFIG_SPL_DM=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_DM_SEQ_ALIAS=y -CONFIG_SPL_SIMPLE_BUS=y -CONFIG_DM_SPI=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DWAPB_GPIO=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index c38f1ab..d767579 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -1,23 +1,18 @@ CONFIG_ARM=y CONFIG_ARCH_SOCFPGA=y -CONFIG_TARGET_SOCFPGA_CYCLONE5=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_ADDR=0x00800000 # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DM=y CONFIG_SPI_FLASH=y CONFIG_DM_ETH=y -CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y -CONFIG_SPL_DM=y -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_DM_SEQ_ALIAS=y -CONFIG_SPL_SIMPLE_BUS=y -CONFIG_DM_SPI=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_SPL_STACK_R=y -CONFIG_SPL_STACK_R_ADDR=0x00800000 -CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DWAPB_GPIO=y diff --git a/configs/spring_defconfig b/configs/spring_defconfig index 2a9c6a9..f1d9a58 100644 --- a/configs/spring_defconfig +++ b/configs/spring_defconfig @@ -6,38 +6,38 @@ CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_SOUND=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y CONFIG_SPI_FLASH=y CONFIG_CMD_CROS_EC=y CONFIG_CROS_EC=y CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_KEYB=y -CONFIG_SOUND=y -CONFIG_I2S=y -CONFIG_I2S_SAMSUNG=y -CONFIG_SOUND_MAX98095=y -CONFIG_SOUND_WM8994=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_DM_I2C=y -CONFIG_DM_PMIC=y -CONFIG_DM_REGULATOR=y -CONFIG_PMIC_TPS65090=y -CONFIG_REGULATOR_TPS65090=y -CONFIG_DM_I2C_COMPAT=y -CONFIG_I2C_ARB_GPIO_CHALLENGE=y -CONFIG_I2C_MUX=y -CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y -CONFIG_ERRNO_STR=y -CONFIG_DM_PMIC_MAX77686=y -CONFIG_DM_REGULATOR_MAX77686=y CONFIG_DEBUG_UART=y CONFIG_DEBUG_UART_S5P=y -CONFIG_DEBUG_UART_CLOCK=100000000 CONFIG_DEBUG_UART_BASE=0x12c30000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DM_I2C=y +CONFIG_DM_I2C_COMPAT=y CONFIG_I2C_CROS_EC_LDO=y +CONFIG_I2C_MUX=y +CONFIG_I2C_ARB_GPIO_CHALLENGE=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_MAX77686=y CONFIG_PMIC_S5M8767=y +CONFIG_PMIC_TPS65090=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_MAX77686=y CONFIG_REGULATOR_S5M8767=y +CONFIG_REGULATOR_TPS65090=y CONFIG_VIDEO_BRIDGE=y CONFIG_VIDEO_BRIDGE_PARADE_PS862X=y CONFIG_SYS_PROMPT="spring # " +CONFIG_SOUND=y +CONFIG_I2S=y +CONFIG_I2S_SAMSUNG=y +CONFIG_SOUND_MAX98095=y +CONFIG_SOUND_WM8994=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_ERRNO_STR=y diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index f71206a..0eeb7f6 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -9,7 +9,7 @@ CONFIG_AUTOBOOT_STOP_STR=" " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set +CONFIG_OF_CONTROL=y CONFIG_NETDEVICES=y CONFIG_ETH_DESIGNWARE=y -CONFIG_OF_CONTROL=y CONFIG_SYS_PROMPT="STV0991> " diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig index 66ac0b1..c9a304d 100644 --- a/configs/tqma6s_wru4_mmc_defconfig +++ b/configs/tqma6s_wru4_mmc_defconfig @@ -3,11 +3,9 @@ CONFIG_ARCH_MX6=y CONFIG_TARGET_TQMA6=y CONFIG_TQMA6S=y CONFIG_WRU4=y -CONFIG_CMD_SETEXPR=y -CONFIG_CMD_NET=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Enter password in %d seconds to stop autoboot\n" CONFIG_AUTOBOOT_ENCRYPTION=y CONFIG_AUTOBOOT_STOP_STR_SHA256="36a9e7f1c95b82ffb99743e0c5c4ce95d83c9a430aac59f84ef3cbfab6145068" -CONFIG_PCA9551_LED=y CONFIG_SPI_FLASH=y +CONFIG_PCA9551_LED=y diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index 73a2558..ce2d493 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -10,8 +10,8 @@ CONFIG_DEFAULT_DEVICE_TREE="tegra124-venice2" # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set CONFIG_SPL_DM=y -CONFIG_TEGRA114_SPI=y CONFIG_SPI_FLASH=y +CONFIG_TEGRA114_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index 2bd0109..79c265f 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -1800,7 +1800,7 @@ static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp) u32 d, p, i; u32 dtaps_per_ptap; u32 work_bgn, work_end; - u32 found_passing_read, found_failing_read, initial_failing_dtap; + u32 found_passing_read, found_failing_read = 0, initial_failing_dtap; int ret; debug("%s:%d %u\n", __func__, __LINE__, grp); @@ -3247,7 +3247,7 @@ static void mem_skip_calibrate(void) * (1.25 * iocfg->dll_chain_length - 2) */ scc_mgr_set_dqdqs_output_phase(i, - 1.25 * iocfg->dll_chain_length - 2); + ((125 * iocfg->dll_chain_length) / 100) - 2); } writel(0xff, &sdr_scc_mgr->dqs_ena); writel(0xff, &sdr_scc_mgr->dqs_io_ena); diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 5934597..9a5d29d 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -14,6 +14,13 @@ config DM_GPIO particular GPIOs that they provide. The uclass interface is defined in include/asm-generic/gpio.h. +config DWAPB_GPIO + bool "DWAPB GPIO driver" + depends on DM && DM_GPIO + default n + help + Support for the Designware APB GPIO driver. + config LPC32XX_GPIO bool "LPC32XX GPIO driver" depends on DM diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 26f2574..ba18594 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -6,6 +6,7 @@ # ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o obj-$(CONFIG_AXP_GPIO) += axp_gpio.o endif obj-$(CONFIG_DM_GPIO) += gpio-uclass.o diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c new file mode 100644 index 0000000..72cec48 --- /dev/null +++ b/drivers/gpio/dwapb_gpio.c @@ -0,0 +1,167 @@ +/* + * (C) Copyright 2015 Marek Vasut <marex@denx.de> + * + * DesignWare APB GPIO driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <asm/arch/gpio.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/root.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define GPIO_SWPORTA_DR 0x00 +#define GPIO_SWPORTA_DDR 0x04 +#define GPIO_INTEN 0x30 +#define GPIO_INTMASK 0x34 +#define GPIO_INTTYPE_LEVEL 0x38 +#define GPIO_INT_POLARITY 0x3c +#define GPIO_INTSTATUS 0x40 +#define GPIO_PORTA_DEBOUNCE 0x48 +#define GPIO_PORTA_EOI 0x4c +#define GPIO_EXT_PORTA 0x50 + +struct gpio_dwapb_platdata { + const char *name; + int bank; + int pins; + fdt_addr_t base; +}; + +static int dwapb_gpio_direction_input(struct udevice *dev, unsigned pin) +{ + struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); + + clrbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin); + return 0; +} + +static int dwapb_gpio_direction_output(struct udevice *dev, unsigned pin, + int val) +{ + struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); + + setbits_le32(plat->base + GPIO_SWPORTA_DDR, 1 << pin); + + if (val) + setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + else + clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + + return 0; +} + +static int dwapb_gpio_get_value(struct udevice *dev, unsigned pin) +{ + struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); + return !!(readl(plat->base + GPIO_EXT_PORTA) & (1 << pin)); +} + + +static int dwapb_gpio_set_value(struct udevice *dev, unsigned pin, int val) +{ + struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); + + if (val) + setbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + else + clrbits_le32(plat->base + GPIO_SWPORTA_DR, 1 << pin); + + return 0; +} + +static const struct dm_gpio_ops gpio_dwapb_ops = { + .direction_input = dwapb_gpio_direction_input, + .direction_output = dwapb_gpio_direction_output, + .get_value = dwapb_gpio_get_value, + .set_value = dwapb_gpio_set_value, +}; + +static int gpio_dwapb_probe(struct udevice *dev) +{ + struct gpio_dev_priv *priv = dev_get_uclass_priv(dev); + struct gpio_dwapb_platdata *plat = dev->platdata; + + if (!plat) + return 0; + + priv->gpio_count = plat->pins; + priv->bank_name = plat->name; + + return 0; +} + +static int gpio_dwapb_bind(struct udevice *dev) +{ + struct gpio_dwapb_platdata *plat = dev_get_platdata(dev); + const void *blob = gd->fdt_blob; + struct udevice *subdev; + fdt_addr_t base; + int ret, node, bank = 0; + + /* If this is a child device, there is nothing to do here */ + if (plat) + return 0; + + base = fdtdec_get_addr(blob, dev->of_offset, "reg"); + if (base == FDT_ADDR_T_NONE) { + debug("Can't get the GPIO register base address\n"); + return -ENXIO; + } + + for (node = fdt_first_subnode(blob, dev->of_offset); + node > 0; + node = fdt_next_subnode(blob, node)) { + if (!fdtdec_get_bool(blob, node, "gpio-controller")) + continue; + + plat = NULL; + plat = calloc(1, sizeof(*plat)); + if (!plat) + return -ENOMEM; + + plat->base = base; + plat->bank = bank; + plat->pins = fdtdec_get_int(blob, node, "snps,nr-gpios", 0); + ret = fdt_get_string(blob, node, "bank-name", &plat->name); + if (ret) + goto err; + + ret = device_bind(dev, dev->driver, plat->name, + plat, -1, &subdev); + if (ret) + goto err; + + subdev->of_offset = node; + bank++; + } + + return 0; + +err: + free(plat); + return ret; +} + +static const struct udevice_id gpio_dwapb_ids[] = { + { .compatible = "snps,dw-apb-gpio" }, + { } +}; + +U_BOOT_DRIVER(gpio_dwapb) = { + .name = "gpio-dwapb", + .id = UCLASS_GPIO, + .of_match = gpio_dwapb_ids, + .ops = &gpio_dwapb_ops, + .bind = gpio_dwapb_bind, + .probe = gpio_dwapb_probe, +}; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index ce76a02..7367d9e 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -20,6 +20,38 @@ menuconfig NETDEVICES if NETDEVICES +config E1000 + bool "Intel PRO/1000 Gigabit Ethernet support" + help + This driver supports Intel(R) PRO/1000 gigabit ethernet family of + adapters. For more information on how to identify your adapter, go + to the Adapter & Driver ID Guide at: + + <http://support.intel.com/support/network/adapter/pro100/21397.htm> + +config E1000_SPI_GENERIC + bool "Allow access to the Intel 8257x SPI bus" + depends on E1000 + help + Allow generic access to the SPI bus on the Intel 8257x, for + example with the "sspi" command. + +config E1000_SPI + bool "Enable SPI bus utility code" + depends on E1000 + help + Utility code for direct access to the SPI bus on Intel 8257x. + This does not do anything useful unless you set at least one + of CONFIG_CMD_E1000 or CONFIG_E1000_SPI_GENERIC. + +config CMD_E1000 + bool "Enable the e1000 command" + depends on E1000 + help + This enables the 'e1000' management command for E1000 devices. When + used on devices with SPI support you can reprogram the EEPROM from + U-Boot. + config ETH_SANDBOX depends on DM_ETH && SANDBOX default y diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index d5d48b1..6f74d30 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -29,6 +29,10 @@ tested on both gig copper and gig fiber boards * Copyright 2011 Freescale Semiconductor, Inc. */ +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <pci.h> #include "e1000.h" #define TOUT_LOOP 100000 @@ -44,75 +48,84 @@ tested on both gig copper and gig fiber boards /* Intel i210 needs the DMA descriptor rings aligned to 128b */ #define E1000_BUFFER_ALIGN 128 +/* + * TODO(sjg@chromium.org): Even with driver model we share these buffers. + * Concurrent receiving on multiple active Ethernet devices will not work. + * Normally U-Boot does not support this anyway. To fix it in this driver, + * move these buffers and the tx/rx pointers to struct e1000_hw. + */ DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN); DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN); DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN); static int tx_tail; static int rx_tail, rx_last; +#ifdef CONFIG_DM_ETH +static int num_cards; /* Number of E1000 devices seen so far */ +#endif static struct pci_device_id e1000_supported[] = { - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF}, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) }, /* E1000 PCIe card */ - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER }, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES }, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS}, - {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX}, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) }, + { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) }, {} }; /* Function forward declarations */ -static int e1000_setup_link(struct eth_device *nic); -static int e1000_setup_fiber_link(struct eth_device *nic); -static int e1000_setup_copper_link(struct eth_device *nic); +static int e1000_setup_link(struct e1000_hw *hw); +static int e1000_setup_fiber_link(struct e1000_hw *hw); +static int e1000_setup_copper_link(struct e1000_hw *hw); static int e1000_phy_setup_autoneg(struct e1000_hw *hw); static void e1000_config_collision_dist(struct e1000_hw *hw); static int e1000_config_mac_to_phy(struct e1000_hw *hw); static int e1000_config_fc_after_link_up(struct e1000_hw *hw); -static int e1000_check_for_link(struct eth_device *nic); +static int e1000_check_for_link(struct e1000_hw *hw); static int e1000_wait_autoneg(struct e1000_hw *hw); static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, uint16_t * duplex); @@ -905,13 +918,13 @@ static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) /* Allocate a temporary buffer */ buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1)); if (!buf) { - E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n"); + E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n"); return -E1000_ERR_EEPROM; } /* Read the EEPROM */ if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) { - E1000_ERR(hw->nic, "Unable to read EEPROM!\n"); + E1000_ERR(hw, "Unable to read EEPROM!\n"); return -E1000_ERR_EEPROM; } @@ -927,9 +940,9 @@ static int e1000_validate_eeprom_checksum(struct e1000_hw *hw) return 0; /* Hrm, verification failed, print an error */ - E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n"); - E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n", - checksum_reg, checksum); + E1000_ERR(hw, "EEPROM checksum is incorrect!\n"); + E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n", + checksum_reg, checksum); return -E1000_ERR_EEPROM; } @@ -1176,9 +1189,8 @@ static bool e1000_is_second_port(struct e1000_hw *hw) * nic - Struct containing variables accessed by shared code *****************************************************************************/ static int -e1000_read_mac_addr(struct eth_device *nic) +e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6]) { - struct e1000_hw *hw = nic->priv; uint16_t offset; uint16_t eeprom_data; uint32_t reg_data = 0; @@ -1201,21 +1213,14 @@ e1000_read_mac_addr(struct eth_device *nic) DEBUGOUT("EEPROM Read Error\n"); return -E1000_ERR_EEPROM; } - nic->enetaddr[i] = eeprom_data & 0xff; - nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; + enetaddr[i] = eeprom_data & 0xff; + enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; } /* Invert the last bit if this is the second device */ if (e1000_is_second_port(hw)) - nic->enetaddr[5] ^= 1; + enetaddr[5] ^= 1; -#ifdef CONFIG_E1000_FALLBACK_MAC - if (!is_valid_ethaddr(nic->enetaddr)) { - unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC; - - memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE); - } -#endif return 0; } #endif @@ -1230,9 +1235,8 @@ e1000_read_mac_addr(struct eth_device *nic) * the receiver is in reset when the routine is called. *****************************************************************************/ static void -e1000_init_rx_addrs(struct eth_device *nic) +e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6]) { - struct e1000_hw *hw = nic->priv; uint32_t i; uint32_t addr_low; uint32_t addr_high; @@ -1241,11 +1245,11 @@ e1000_init_rx_addrs(struct eth_device *nic) /* Setup the receive address. */ DEBUGOUT("Programming MAC Address into RAR[0]\n"); - addr_low = (nic->enetaddr[0] | - (nic->enetaddr[1] << 8) | - (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24)); + addr_low = (enetaddr[0] | + (enetaddr[1] << 8) | + (enetaddr[2] << 16) | (enetaddr[3] << 24)); - addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV); + addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV); E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low); E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high); @@ -1652,9 +1656,8 @@ e1000_initialize_hardware_bits(struct e1000_hw *hw) * the transmit and receive units disabled and uninitialized. *****************************************************************************/ static int -e1000_init_hw(struct eth_device *nic) +e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6]) { - struct e1000_hw *hw = nic->priv; uint32_t ctrl; uint32_t i; int32_t ret_val; @@ -1707,7 +1710,7 @@ e1000_init_hw(struct eth_device *nic) /* Setup the receive address. This involves initializing all of the Receive * Address Registers (RARs 0 - 15). */ - e1000_init_rx_addrs(nic); + e1000_init_rx_addrs(hw, enetaddr); /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ if (hw->mac_type == e1000_82542_rev2_0) { @@ -1776,7 +1779,7 @@ e1000_init_hw(struct eth_device *nic) mdelay(15); /* Call a subroutine to configure the link and setup flow control. */ - ret_val = e1000_setup_link(nic); + ret_val = e1000_setup_link(hw); /* Set the transmit descriptor write-back policy */ if (hw->mac_type > e1000_82544) { @@ -1876,9 +1879,8 @@ e1000_init_hw(struct eth_device *nic) * transmitter and receiver are not enabled. *****************************************************************************/ static int -e1000_setup_link(struct eth_device *nic) +e1000_setup_link(struct e1000_hw *hw) { - struct e1000_hw *hw = nic->priv; int32_t ret_val; #ifndef CONFIG_E1000_NO_NVM uint32_t ctrl_ext; @@ -1966,7 +1968,7 @@ e1000_setup_link(struct eth_device *nic) /* Call the necessary subroutine to configure the link. */ ret_val = (hw->media_type == e1000_media_type_fiber) ? - e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic); + e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw); if (ret_val < 0) { return ret_val; } @@ -2023,9 +2025,8 @@ e1000_setup_link(struct eth_device *nic) * and receiver are not enabled. *****************************************************************************/ static int -e1000_setup_fiber_link(struct eth_device *nic) +e1000_setup_fiber_link(struct e1000_hw *hw) { - struct e1000_hw *hw = nic->priv; uint32_t ctrl; uint32_t status; uint32_t txcw = 0; @@ -2044,7 +2045,7 @@ e1000_setup_fiber_link(struct eth_device *nic) else signal = 0; - printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal, + printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal, ctrl); /* Take the link out of reset */ ctrl &= ~(E1000_CTRL_LRST); @@ -2132,7 +2133,7 @@ e1000_setup_fiber_link(struct eth_device *nic) */ DEBUGOUT("Never got a valid link from auto-neg!!!\n"); hw->autoneg_failed = 1; - ret_val = e1000_check_for_link(nic); + ret_val = e1000_check_for_link(hw); if (ret_val < 0) { DEBUGOUT("Error while checking for link\n"); return ret_val; @@ -3049,9 +3050,8 @@ e1000_copper_link_postconfig(struct e1000_hw *hw) * hw - Struct containing variables accessed by shared code ******************************************************************************/ static int -e1000_setup_copper_link(struct eth_device *nic) +e1000_setup_copper_link(struct e1000_hw *hw) { - struct e1000_hw *hw = nic->priv; int32_t ret_val; uint16_t i; uint16_t phy_data; @@ -3674,9 +3674,8 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw) * Called by any function that needs to check the link status of the adapter. *****************************************************************************/ static int -e1000_check_for_link(struct eth_device *nic) +e1000_check_for_link(struct e1000_hw *hw) { - struct e1000_hw *hw = nic->priv; uint32_t rxcw; uint32_t ctrl; uint32_t status; @@ -4873,9 +4872,8 @@ e1000_set_media_type(struct e1000_hw *hw) **/ static int -e1000_sw_init(struct eth_device *nic) +e1000_sw_init(struct e1000_hw *hw) { - struct e1000_hw *hw = (typeof(hw)) nic->priv; int result; /* PCI config space info */ @@ -4891,7 +4889,7 @@ e1000_sw_init(struct eth_device *nic) /* identify the MAC */ result = e1000_set_mac_type(hw); if (result) { - E1000_ERR(hw->nic, "Unknown MAC Type\n"); + E1000_ERR(hw, "Unknown MAC Type\n"); return result; } @@ -4980,8 +4978,8 @@ e1000_configure_tx(struct e1000_hw *hw) unsigned long tipg, tarc; uint32_t ipgr1, ipgr2; - E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base); - E1000_WRITE_REG(hw, TDBAH, 0); + E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base & 0xffffffff); + E1000_WRITE_REG(hw, TDBAH, (unsigned long)tx_base >> 32); E1000_WRITE_REG(hw, TDLEN, 128); @@ -5124,8 +5122,8 @@ e1000_configure_rx(struct e1000_hw *hw) E1000_WRITE_FLUSH(hw); } /* Setup the Base and Length of the Rx Descriptor Ring */ - E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base); - E1000_WRITE_REG(hw, RDBAH, 0); + E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base & 0xffffffff); + E1000_WRITE_REG(hw, RDBAH, (unsigned long)rx_base >> 32); E1000_WRITE_REG(hw, RDLEN, 128); @@ -5151,9 +5149,8 @@ e1000_configure_rx(struct e1000_hw *hw) POLL - Wait for a frame ***************************************************************************/ static int -e1000_poll(struct eth_device *nic) +_e1000_poll(struct e1000_hw *hw) { - struct e1000_hw *hw = nic->priv; struct e1000_rx_desc *rd; unsigned long inval_start, inval_end; uint32_t len; @@ -5174,18 +5171,12 @@ e1000_poll(struct eth_device *nic) invalidate_dcache_range((unsigned long)packet, (unsigned long)packet + roundup(len, ARCH_DMA_MINALIGN)); - net_process_received_packet((uchar *)packet, len); - fill_rx(hw); - return 1; + return len; } -/************************************************************************** -TRANSMIT - Transmit a frame -***************************************************************************/ -static int e1000_transmit(struct eth_device *nic, void *txpacket, int length) +static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length) { void *nv_packet = (void *)txpacket; - struct e1000_hw *hw = nic->priv; struct e1000_tx_desc *txp; int i = 0; unsigned long flush_start, flush_end; @@ -5222,27 +5213,9 @@ static int e1000_transmit(struct eth_device *nic, void *txpacket, int length) return 1; } -/*reset function*/ -static inline int -e1000_reset(struct eth_device *nic) -{ - struct e1000_hw *hw = nic->priv; - - e1000_reset_hw(hw); - if (hw->mac_type >= e1000_82544) { - E1000_WRITE_REG(hw, WUC, 0); - } - return e1000_init_hw(nic); -} - -/************************************************************************** -DISABLE - Turn off ethernet interface -***************************************************************************/ static void -e1000_disable(struct eth_device *nic) +_e1000_disable(struct e1000_hw *hw) { - struct e1000_hw *hw = nic->priv; - /* Turn off the ethernet interface */ E1000_WRITE_REG(hw, RCTL, 0); E1000_WRITE_REG(hw, TCTL, 0); @@ -5260,32 +5233,38 @@ e1000_disable(struct eth_device *nic) E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST); #endif mdelay(10); +} + +/*reset function*/ +static inline int +e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6]) +{ + e1000_reset_hw(hw); + if (hw->mac_type >= e1000_82544) + E1000_WRITE_REG(hw, WUC, 0); + return e1000_init_hw(hw, enetaddr); } -/************************************************************************** -INIT - set up ethernet interface(s) -***************************************************************************/ static int -e1000_init(struct eth_device *nic, bd_t * bis) +_e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6]) { - struct e1000_hw *hw = nic->priv; int ret_val = 0; - ret_val = e1000_reset(nic); + ret_val = e1000_reset(hw, enetaddr); if (ret_val < 0) { if ((ret_val == -E1000_ERR_NOLINK) || (ret_val == -E1000_ERR_TIMEOUT)) { - E1000_ERR(hw->nic, "Valid Link not detected\n"); + E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val); } else { - E1000_ERR(hw->nic, "Hardware Initialization Failed\n"); + E1000_ERR(hw, "Hardware Initialization Failed\n"); } - return 0; + return ret_val; } e1000_configure_tx(hw); e1000_setup_rctl(hw); e1000_configure_rx(hw); - return 1; + return 0; } /****************************************************************************** @@ -5319,8 +5298,143 @@ void e1000_get_bus_type(struct e1000_hw *hw) } } +#ifndef CONFIG_DM_ETH /* A list of all registered e1000 devices */ static LIST_HEAD(e1000_hw_list); +#endif + +static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno, + unsigned char enetaddr[6]) +{ + u32 val; + + /* Assign the passed-in values */ + hw->pdev = devno; + hw->cardnum = cardnum; + + /* Print a debug message with the IO base address */ + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); + E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0); + + /* Try to enable I/O accesses and bus-mastering */ + val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + pci_write_config_dword(devno, PCI_COMMAND, val); + + /* Make sure it worked */ + pci_read_config_dword(devno, PCI_COMMAND, &val); + if (!(val & PCI_COMMAND_MEMORY)) { + E1000_ERR(hw, "Can't enable I/O memory\n"); + return -ENOSPC; + } + if (!(val & PCI_COMMAND_MASTER)) { + E1000_ERR(hw, "Can't enable bus-mastering\n"); + return -EPERM; + } + + /* Are these variables needed? */ + hw->fc = e1000_fc_default; + hw->original_fc = e1000_fc_default; + hw->autoneg_failed = 0; + hw->autoneg = 1; + hw->get_link_status = true; +#ifndef CONFIG_E1000_NO_NVM + hw->eeprom_semaphore_present = true; +#endif + hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); + hw->mac_type = e1000_undefined; + + /* MAC and Phy settings */ + if (e1000_sw_init(hw) < 0) { + E1000_ERR(hw, "Software init failed\n"); + return -EIO; + } + if (e1000_check_phy_reset_block(hw)) + E1000_ERR(hw, "PHY Reset is blocked!\n"); + + /* Basic init was OK, reset the hardware and allow SPI access */ + e1000_reset_hw(hw); + +#ifndef CONFIG_E1000_NO_NVM + /* Validate the EEPROM and get chipset information */ +#if !defined(CONFIG_MVBC_1G) + if (e1000_init_eeprom_params(hw)) { + E1000_ERR(hw, "EEPROM is invalid!\n"); + return -EINVAL; + } + if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && + e1000_validate_eeprom_checksum(hw)) + return -ENXIO; +#endif + e1000_read_mac_addr(hw, enetaddr); +#endif + e1000_get_bus_type(hw); + +#ifndef CONFIG_E1000_NO_NVM + printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", + enetaddr[0], enetaddr[1], enetaddr[2], + enetaddr[3], enetaddr[4], enetaddr[5]); +#else + memset(enetaddr, 0, 6); + printf("e1000: no NVM\n"); +#endif + + return 0; +} + +/* Put the name of a device in a string */ +static void e1000_name(char *str, int cardnum) +{ + sprintf(str, "e1000#%u", cardnum); +} + +#ifndef CONFIG_DM_ETH +/************************************************************************** +TRANSMIT - Transmit a frame +***************************************************************************/ +static int e1000_transmit(struct eth_device *nic, void *txpacket, int length) +{ + struct e1000_hw *hw = nic->priv; + + return _e1000_transmit(hw, txpacket, length); +} + +/************************************************************************** +DISABLE - Turn off ethernet interface +***************************************************************************/ +static void +e1000_disable(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + + _e1000_disable(hw); +} + +/************************************************************************** +INIT - set up ethernet interface(s) +***************************************************************************/ +static int +e1000_init(struct eth_device *nic, bd_t *bis) +{ + struct e1000_hw *hw = nic->priv; + + return _e1000_init(hw, nic->enetaddr); +} + +static int +e1000_poll(struct eth_device *nic) +{ + struct e1000_hw *hw = nic->priv; + int len; + + len = _e1000_poll(hw); + if (len) { + net_process_received_packet((uchar *)packet, len); + fill_rx(hw); + } + + return len ? 1 : 0; +} /************************************************************************** PROBE - Look for an adapter, this routine's visible to the outside @@ -5331,13 +5445,12 @@ e1000_initialize(bd_t * bis) { unsigned int i; pci_dev_t devno; + int ret; DEBUGFUNC(); /* Find and probe all the matching PCI devices */ for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) { - u32 val; - /* * These will never get freed due to errors, this allows us to * perform SPI EEPROM programming from U-boot, for example. @@ -5354,83 +5467,18 @@ e1000_initialize(bd_t * bis) /* Make sure all of the fields are initially zeroed */ memset(nic, 0, sizeof(*nic)); memset(hw, 0, sizeof(*hw)); - - /* Assign the passed-in values */ - hw->cardnum = i; - hw->pdev = devno; - hw->nic = nic; nic->priv = hw; /* Generate a card name */ - sprintf(nic->name, "e1000#%u", hw->cardnum); + e1000_name(nic->name, i); + hw->name = nic->name; - /* Print a debug message with the IO base address */ - pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val); - E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0); - - /* Try to enable I/O accesses and bus-mastering */ - val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config_dword(devno, PCI_COMMAND, val); - - /* Make sure it worked */ - pci_read_config_dword(devno, PCI_COMMAND, &val); - if (!(val & PCI_COMMAND_MEMORY)) { - E1000_ERR(nic, "Can't enable I/O memory\n"); - continue; - } - if (!(val & PCI_COMMAND_MASTER)) { - E1000_ERR(nic, "Can't enable bus-mastering\n"); + ret = e1000_init_one(hw, i, devno, nic->enetaddr); + if (ret) continue; - } - - /* Are these variables needed? */ - hw->fc = e1000_fc_default; - hw->original_fc = e1000_fc_default; - hw->autoneg_failed = 0; - hw->autoneg = 1; - hw->get_link_status = true; -#ifndef CONFIG_E1000_NO_NVM - hw->eeprom_semaphore_present = true; -#endif - hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, - PCI_REGION_MEM); - hw->mac_type = e1000_undefined; - - /* MAC and Phy settings */ - if (e1000_sw_init(nic) < 0) { - E1000_ERR(nic, "Software init failed\n"); - continue; - } - if (e1000_check_phy_reset_block(hw)) - E1000_ERR(nic, "PHY Reset is blocked!\n"); - - /* Basic init was OK, reset the hardware and allow SPI access */ - e1000_reset_hw(hw); list_add_tail(&hw->list_node, &e1000_hw_list); -#ifndef CONFIG_E1000_NO_NVM - /* Validate the EEPROM and get chipset information */ -#if !defined(CONFIG_MVBC_1G) - if (e1000_init_eeprom_params(hw)) { - E1000_ERR(nic, "EEPROM is invalid!\n"); - continue; - } - if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) && - e1000_validate_eeprom_checksum(hw)) - continue; -#endif - e1000_read_mac_addr(nic); -#endif - e1000_get_bus_type(hw); - -#ifndef CONFIG_E1000_NO_NVM - printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ", - nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], - nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); -#else - memset(nic->enetaddr, 0, 6); - printf("e1000: no NVM\n"); -#endif + hw->nic = nic; /* Set up the function pointers and register the device */ nic->init = e1000_init; @@ -5453,12 +5501,22 @@ struct e1000_hw *e1000_find_card(unsigned int cardnum) return NULL; } +#endif /* !CONFIG_DM_ETH */ #ifdef CONFIG_CMD_E1000 static int do_e1000(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { + unsigned char *mac = NULL; +#ifdef CONFIG_DM_ETH + struct eth_pdata *plat; + struct udevice *dev; + char name[30]; + int ret; +#else struct e1000_hw *hw; +#endif + int cardnum; if (argc < 3) { cmd_usage(cmdtp); @@ -5466,14 +5524,25 @@ static int do_e1000(cmd_tbl_t *cmdtp, int flag, } /* Make sure we can find the requested e1000 card */ - hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10)); - if (!hw) { + cardnum = simple_strtoul(argv[1], NULL, 10); +#ifdef CONFIG_DM_ETH + e1000_name(name, cardnum); + ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev); + if (!ret) { + plat = dev_get_platdata(dev); + mac = plat->enetaddr; + } +#else + hw = e1000_find_card(cardnum); + if (hw) + mac = hw->nic->enetaddr; +#endif + if (!mac) { printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]); return 1; } if (!strcmp(argv[2], "print-mac-address")) { - unsigned char *mac = hw->nic->enetaddr; printf("%02x:%02x:%02x:%02x:%02x:%02x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); return 0; @@ -5502,3 +5571,109 @@ U_BOOT_CMD( " - Manage the Intel E1000 PCI device" ); #endif /* not CONFIG_CMD_E1000 */ + +#ifdef CONFIG_DM_ETH +static int e1000_eth_start(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_platdata(dev); + struct e1000_hw *hw = dev_get_priv(dev); + + return _e1000_init(hw, plat->enetaddr); +} + +static void e1000_eth_stop(struct udevice *dev) +{ + struct e1000_hw *hw = dev_get_priv(dev); + + _e1000_disable(hw); +} + +static int e1000_eth_send(struct udevice *dev, void *packet, int length) +{ + struct e1000_hw *hw = dev_get_priv(dev); + int ret; + + ret = _e1000_transmit(hw, packet, length); + + return ret ? 0 : -ETIMEDOUT; +} + +static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct e1000_hw *hw = dev_get_priv(dev); + int len; + + len = _e1000_poll(hw); + if (len) + *packetp = packet; + + return len ? len : -EAGAIN; +} + +static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct e1000_hw *hw = dev_get_priv(dev); + + fill_rx(hw); + + return 0; +} + +static int e1000_eth_probe(struct udevice *dev) +{ + struct eth_pdata *plat = dev_get_platdata(dev); + struct e1000_hw *hw = dev_get_priv(dev); + int ret; + + hw->name = dev->name; + ret = e1000_init_one(hw, trailing_strtol(dev->name), pci_get_bdf(dev), + plat->enetaddr); + if (ret < 0) { + printf(pr_fmt("failed to initialize card: %d\n"), ret); + return ret; + } + + return 0; +} + +static int e1000_eth_bind(struct udevice *dev) +{ + char name[20]; + + /* + * A simple way to number the devices. When device tree is used this + * is unnecessary, but when the device is just discovered on the PCI + * bus we need a name. We could instead have the uclass figure out + * which devices are different and number them. + */ + e1000_name(name, num_cards++); + + return device_set_name(dev, name); +} + +static const struct eth_ops e1000_eth_ops = { + .start = e1000_eth_start, + .send = e1000_eth_send, + .recv = e1000_eth_recv, + .stop = e1000_eth_stop, + .free_pkt = e1000_free_pkt, +}; + +static const struct udevice_id e1000_eth_ids[] = { + { .compatible = "intel,e1000" }, + { } +}; + +U_BOOT_DRIVER(eth_e1000) = { + .name = "eth_e1000", + .id = UCLASS_ETH, + .of_match = e1000_eth_ids, + .bind = e1000_eth_bind, + .probe = e1000_eth_probe, + .ops = &e1000_eth_ops, + .priv_auto_alloc_size = sizeof(struct e1000_hw), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported); +#endif diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index 23a81e6..c851922 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -19,11 +19,13 @@ #ifndef _E1000_HW_H_ #define _E1000_HW_H_ -#include <common.h> #include <linux/list.h> #include <malloc.h> #include <net.h> +/* Avoids a compile error since struct eth_device is not defined */ +#ifndef CONFIG_DM_ETH #include <netdev.h> +#endif #include <asm/io.h> #include <pci.h> @@ -1072,8 +1074,11 @@ typedef enum { /* Structure containing variables used by the shared code (e1000_hw.c) */ struct e1000_hw { + const char *name; struct list_head list_node; +#ifndef CONFIG_DM_ETH struct eth_device *nic; +#endif #ifdef CONFIG_E1000_SPI struct spi_slave spi; #endif diff --git a/drivers/net/e1000_spi.c b/drivers/net/e1000_spi.c index 93043a1..e7f6826 100644 --- a/drivers/net/e1000_spi.c +++ b/drivers/net/e1000_spi.c @@ -1,3 +1,4 @@ +#include <common.h> #include "e1000.h" #include <linux/compiler.h> diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 2bac68d..ad3f52a 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -718,7 +718,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index d222514..804493e 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -94,7 +94,6 @@ #define CONFIG_CMD_PCI -#define CONFIG_E1000 /* E1000 pci Ethernet card*/ /* * PCI Windows diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index bbdcc4c..6c39b1e 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -101,7 +101,6 @@ #define CONFIG_CMD_PCI -#define CONFIG_E1000 /* * PCI Windows diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 6a90531..1312438 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -61,7 +61,6 @@ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index ef268a8..d7aa501 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -32,7 +32,6 @@ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index a80221a..eef1b1e 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -423,7 +423,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#define CONFIG_E1000 /* Define e1000 pci Ethernet card */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 78019b9..ad80829 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -441,7 +441,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#define CONFIG_E1000 /* Define e1000 pci Ethernet card */ #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 71bd51b..f3334ad 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -505,7 +505,6 @@ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP #undef CONFIG_RTL8139 -#define CONFIG_E1000 /* Define e1000 pci Ethernet card */ #ifndef CONFIG_PCI_PNP #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 4e3c05a..8ac7000 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -186,7 +186,6 @@ #define CONFIG_CMD_PCI -#define CONFIG_E1000 /* E1000 pci Ethernet card*/ /* * PCI Windows diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 6ddf447..06b293f 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -554,7 +554,6 @@ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_E1000 /* Define e1000 pci Ethernet card */ #endif /* SATA */ diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index 8fff431..e61db18 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -250,7 +250,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #if defined(CONFIG_PCI) -#define CONFIG_E1000 /* Defind e1000 pci Ethernet card */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index cc8700b..5468495 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -562,7 +562,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 21a918a..2f78e05 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -668,7 +668,6 @@ unsigned long get_board_ddr_clk(void); #endif #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION #endif /* CONFIG_PCI */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 242c239..386d0e6 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -681,7 +681,6 @@ unsigned long get_board_ddr_clk(void); #endif #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION #endif /* CONFIG_PCI */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index af7d9f8..a0390a8 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -547,7 +547,6 @@ unsigned long get_board_ddr_clk(void); #endif #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 8c7c573..3927337 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -605,7 +605,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #endif #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index b0ee0de..19f07f8 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -619,7 +619,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ -#define CONFIG_E1000 #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 8c637c2..b0d8399 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -567,7 +567,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */ -#define CONFIG_E1000 #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 8ed6bf7..edc03c3 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -278,7 +278,6 @@ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index 76611b0..629be99 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -420,7 +420,6 @@ #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ #define CONFIG_CMD_PCI #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index 6c0ae22..fe1ef9d 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -55,7 +55,6 @@ #define CONFIG_CMD_PCI_ENUM /* PCI networking support */ -#define CONFIG_E1000 #define CONFIG_E1000_NO_NVM /* General networking support */ diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 2bded45..de5f12e 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -27,6 +27,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DISPLAY_CPUINFO +#define CONFIG_ENV_VARS_UBOOT_CONFIG #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT /* Device Tree support */ @@ -52,6 +53,20 @@ #define CONFIG_CMD_DHCP #ifdef CONFIG_SYS_USE_MMC +/* u-boot env in sd/mmc card */ +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_FAT_WRITE +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_SIZE 0x4000 + +#define CONFIG_BOOTCOMMAND "if test ! -n ${dtb_name}; then " \ + "setenv dtb_name at91-${board_name}.dtb; " \ + "fi; " \ + "fatload mmc 0:1 0x21000000 ${dtb_name}; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk " \ "root=/dev/mmcblk0p2 rw rootwait" @@ -62,6 +77,28 @@ "256K(env),256k(env_redundent),256k(spare)," \ "512k(dtb),6M(kernel)ro,-(rootfs) " \ "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs" + +#ifdef CONFIG_SYS_USE_NANDFLASH +/* u-boot env in nand flash */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0xc0000 +#define CONFIG_ENV_OFFSET_REDUND 0x100000 +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ + "nand read 0x22000000 0x200000 0x600000;" \ + "bootz 0x22000000 - 0x21000000" +#elif CONFIG_SYS_USE_SERIALFLASH +/* u-boot env in serial flash, by default is bus 0 and cs 0 */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x21000000 0x60000 0xc000; " \ + "sf read 0x22000000 0x6c000 0x394000; " \ + "bootz 0x22000000 - 0x21000000" +#endif + #endif #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 4d90209..2f6a3a5 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -251,5 +251,4 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302 -#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0 #endif diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index ea0a94b..acdd63e 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -259,8 +259,6 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302 -#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC - #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds #define CONFIG_SPL_MMC_SUPPORT diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 9f76786..fbb584d 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -261,8 +261,6 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302 -#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC - #ifdef CONFIG_SYS_USE_MMC #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds #define CONFIG_SPL_MMC_SUPPORT diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h index c590f56..d37a865 100644 --- a/include/configs/bayleybay.h +++ b/include/configs/bayleybay.h @@ -19,7 +19,6 @@ #define CONFIG_PCI_CONFIG_HOST_BRIDGE #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP -#define CONFIG_E1000 #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \ "stdout=serial,vga\0" \ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 9aaa0f5..2919220 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -575,7 +575,6 @@ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 2d2f3c1..c91e289 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -193,6 +193,4 @@ #define CONFIG_SYS_MCKR 0x1301 #define CONFIG_SYS_MCKR_CSS 0x1302 -#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0 - #endif diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 1ea320b..57a9512 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -34,7 +34,6 @@ #define CONFIG_PCI_CONFIG_HOST_BRIDGE #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP -#define CONFIG_E1000 #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \ "stdout=serial,vga\0" \ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 1c0d96e..8b9d922 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -168,7 +168,6 @@ /* Ethernet support */ #define CONFIG_FEC_MXC -#define CONFIG_E1000 #define CONFIG_MII #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_XCV_TYPE RGMII diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index a8cf3f7..7536cbd 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -375,7 +375,6 @@ int get_scl(void); #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 0871a71..dfaffa1 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -547,7 +547,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_PCI #define CONFIG_PCI_PNP -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index df7af3c..3299a9f 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -395,7 +395,6 @@ #ifdef CONFIG_PCI #define CONFIG_PCI_PNP -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI #endif diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h index 91d4c5b..f818570 100644 --- a/include/configs/ls2085aqds.h +++ b/include/configs/ls2085aqds.h @@ -313,7 +313,6 @@ unsigned long get_board_ddr_clk(void); #ifdef CONFIG_PCI #define CONFIG_PCI_PNP -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI #endif diff --git a/include/configs/ls2085ardb.h b/include/configs/ls2085ardb.h index 4f8eb13..aee1216 100644 --- a/include/configs/ls2085ardb.h +++ b/include/configs/ls2085ardb.h @@ -277,7 +277,6 @@ unsigned long get_board_sys_clk(void); #ifdef CONFIG_PCI #define CONFIG_PCI_PNP -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW #define CONFIG_CMD_PCI #endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index af3086d..af89e6b 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -767,7 +767,6 @@ #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ #define CONFIG_CMD_PCI #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 8231eb4..e9cc274 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -303,7 +303,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/ #define CONFIG_CMD_PCI #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h new file mode 100644 index 0000000..e3039c2 --- /dev/null +++ b/include/configs/picosam9g45.h @@ -0,0 +1,211 @@ +/* + * Configuration settings for the mini-box PICOSAM9G45 board. + * (C) Copyright 2015 Inter Act B.V. + * + * Based on: + * U-Boot file: include/configs/at91sam9m10g45ek.h + * (C) Copyright 2007-2008 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/hardware.h> + +#define CONFIG_SYS_TEXT_BASE 0x23f00000 + +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_PICOSAM + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_CMD_BOOTZ +#define CONFIG_OF_LIBFDT + +#define CONFIG_SYS_GENERIC_BOARD + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ +#define CONFIG_AT91_GPIO +#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS + +/* LCD */ +#define CONFIG_LCD +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO +#define CONFIG_LCD_INFO_BELOW_LOGO +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_ATMEL_LCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +/* board specific(not enough SRAM) */ +#define CONFIG_AT91SAM9G45_LCD_BASE 0x23E00000 + +/* LED */ +#define CONFIG_AT91_LED +#define CONFIG_GREEN_LED AT91_PIN_PD31 /* this is the user1 led */ + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Enable the watchdog */ +#define CONFIG_AT91SAM9_WATCHDOG +#define CONFIG_HW_WATCHDOG + +/* + * Command line configuration. + */ + +/* No NOR flash */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_USB + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 ATMEL_BASE_CS1 /* on DDRSDRC1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_2 ATMEL_BASE_CS6 /* on DDRSDRC0 */ +#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) + +/* MMC */ +#define CONFIG_CMD_MMC + +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#endif + +#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R +#define CONFIG_AT91_WANTS_COMMON_PHY + +/* USB */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ATMEL +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +#ifdef CONFIG_SYS_USE_MMC +/* bootstrap + u-boot + env + linux in mmc */ +#define FAT_ENV_INTERFACE "mmc" +/* + * We don't specify the part number, if device 0 has partition table, it means + * the first partition; it no partition table, then take whole device as a + * FAT file system. + */ +#define FAT_ENV_DEVICE_AND_PART "0" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_ENV_IS_IN_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_ENV_SIZE 0x4000 + +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mmcblk0p2 rw rootwait" +#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \ + "fatload mmc 0:1 0x22000000 zImage; " \ + "bootz 0x22000000 - 0x21000000" +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) + +/* Defines for SPL */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x300000 +#define CONFIG_SPL_MAX_SIZE 0x010000 +#define CONFIG_SPL_STACK 0x310000 + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT + +#define CONFIG_SYS_MONITOR_LEN 0x80000 + +#ifdef CONFIG_SYS_USE_MMC + +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 + +#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT + +#define CONFIG_SPL_ATMEL_SIZE +#define CONFIG_SYS_MASTER_CLOCK 132096000 +#define CONFIG_SYS_AT91_PLLA 0x20c73f03 +#define CONFIG_SYS_MCKR 0x1301 +#define CONFIG_SYS_MCKR_CSS 0x1302 + +#endif +#endif diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index be430ff..45f5e78 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -136,7 +136,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index c25e331..72df64e 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -30,7 +30,6 @@ #define CONFIG_PCI_CONFIG_HOST_BRIDGE #define CONFIG_PCI_PNP -#define CONFIG_E1000 #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga\0" \ "stdout=serial,vga\0" \ diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index c4141a0..73de62c 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -115,24 +115,9 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ #if CONFIG_SYS_USE_NANDFLASH -/* bootstrap + u-boot + env in nandflash */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0xc0000 -#define CONFIG_ENV_OFFSET_REDUND 0x100000 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ - "nand read 0x22000000 0x200000 0x600000;" \ - "bootz 0x22000000 - 0x21000000" +/* override the bootcmd, bootargs and other configuration for nandflash env */ #elif CONFIG_SYS_USE_MMC -/* bootstrap + u-boot + env in sd card */ -#define CONFIG_ENV_IS_IN_FAT -#define FAT_ENV_INTERFACE "mmc" -#define FAT_ENV_FILE "uboot.env" -#define FAT_ENV_DEVICE_AND_PART "0" -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d3_xplained.dtb; " \ - "fatload mmc 0:1 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" +/* override the bootcmd, bootargs and other configuration for sd/mmc env */ #else #define CONFIG_ENV_IS_NOWHERE #endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 9497bea..61b4bda 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -19,6 +19,9 @@ */ #include "at91-sama5_common.h" +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + /* serial console */ #define CONFIG_ATMEL_USART #define CONFIG_USART_BASE ATMEL_BASE_DBGU @@ -153,33 +156,11 @@ #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ #ifdef CONFIG_SYS_USE_SERIALFLASH -/* bootstrap + u-boot + env + linux in serial flash */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x5000 -#define CONFIG_ENV_SIZE 0x3000 -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_BOOTCOMMAND "sf probe 0; " \ - "sf read 0x22000000 0x42000 0x300000; " \ - "bootm 0x22000000" +/* override the bootcmd, bootargs and other configuration for spi flash env*/ #elif CONFIG_SYS_USE_NANDFLASH -/* bootstrap + u-boot + env in nandflash */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0xc0000 -#define CONFIG_ENV_OFFSET_REDUND 0x100000 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ - "nand read 0x22000000 0x200000 0x600000;" \ - "bootm 0x22000000 - 0x21000000" +/* override the bootcmd, bootargs and other configuration nandflash env */ #elif CONFIG_SYS_USE_MMC -/* bootstrap + u-boot + env in sd card */ -#define CONFIG_ENV_IS_IN_FAT -#define FAT_ENV_INTERFACE "mmc" -#define FAT_ENV_FILE "uboot.env" -#define FAT_ENV_DEVICE_AND_PART "0" -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \ - "fatload mmc 0:1 0x22000000 uImage; " \ - "bootm 0x22000000 - 0x21000000" +/* override the bootcmd, bootargs and other configuration for sd/mmc env */ #else #define CONFIG_ENV_IS_NOWHERE #endif @@ -228,7 +209,7 @@ #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 #endif diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index e06dfc9..139031d 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -117,46 +117,13 @@ #endif #ifdef CONFIG_SYS_USE_SERIALFLASH -/* bootstrap + u-boot + env + linux in serial flash */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS -#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_BOOTCOMMAND "sf probe 0; " \ - "sf read 0x21000000 0xa0000 0x60000; " \ - "sf read 0x22000000 0x100000 0x300000; " \ - "bootz 0x22000000 - 0x21000000" +/* override the bootcmd, bootargs and other configuration for spi flash env */ #elif CONFIG_SYS_USE_NANDFLASH -/* bootstrap + u-boot + env in nandflash */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0xc0000 -#define CONFIG_ENV_OFFSET_REDUND 0x100000 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ - "nand read 0x22000000 0x200000 0x600000;" \ - "bootz 0x22000000 - 0x21000000" +/* override the bootcmd, bootargs and other configuration for nandflash env */ #elif CONFIG_SYS_USE_MMC -/* bootstrap + u-boot + env in sd card */ -#define CONFIG_ENV_IS_IN_FAT -#define CONFIG_FAT_WRITE -#define FAT_ENV_INTERFACE "mmc" -/* - * We don't specify the part number, if device 0 has partition table, it means - * the first partition; it no partition table, then take whole device as a - * FAT file system. - */ -#define FAT_ENV_DEVICE_AND_PART "0" -#define FAT_ENV_FILE "uboot.env" -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d4_xplained.dtb; " \ - "fatload mmc 0:1 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" +/* override the bootcmd, bootargs and other configuration for sd/mmc env */ #endif - - /* SPL */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x200000 @@ -203,7 +170,7 @@ #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 #endif #endif diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index eadccc1..cde549a 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -115,42 +115,11 @@ #define CONFIG_SYS_CONSOLE_IS_IN_ENV #ifdef CONFIG_SYS_USE_SERIALFLASH -/* bootstrap + u-boot + env + linux in serial flash */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS -#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_BOOTCOMMAND "sf probe 0; " \ - "sf read 0x21000000 0xa0000 0x60000; " \ - "sf read 0x22000000 0x100000 0x300000; " \ - "bootz 0x22000000 - 0x21000000" +/* override the bootcmd, bootargs and other configuration for spi flash env*/ #elif CONFIG_SYS_USE_NANDFLASH -/* bootstrap + u-boot + env in nandflash */ -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0xc0000 -#define CONFIG_ENV_OFFSET_REDUND 0x100000 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ - "nand read 0x22000000 0x200000 0x600000;" \ - "bootz 0x22000000 - 0x21000000" +/* override the bootcmd, bootargs and other configuration for nandflash env*/ #elif CONFIG_SYS_USE_MMC -/* bootstrap + u-boot + env in sd card */ -#define CONFIG_ENV_IS_IN_FAT -#define CONFIG_FAT_WRITE -#define FAT_ENV_INTERFACE "mmc" -/* - * We don't specify the part number, if device 0 has partition table, it means - * the first partition; it no partition table, then take whole device as a - * FAT file system. - */ -#define FAT_ENV_DEVICE_AND_PART "0" -#define FAT_ENV_FILE "uboot.env" -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 sama5d4ek.dtb; " \ - "fatload mmc 0:1 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" +/* override the bootcmd, bootargs and other configuration for sd/mmc env */ #endif /* SPL */ @@ -199,7 +168,7 @@ #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 #endif #endif diff --git a/include/configs/socfpga_arria5.h b/include/configs/socfpga_arria5.h index e1cd9cc..3193684 100644 --- a/include/configs/socfpga_arria5.h +++ b/include/configs/socfpga_arria5.h @@ -23,6 +23,7 @@ #define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT #define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GPIO #define CONFIG_CMD_GREPENV #define CONFIG_CMD_MII #define CONFIG_CMD_MMC @@ -30,7 +31,6 @@ #define CONFIG_CMD_USB #define CONFIG_CMD_USB_MASS_STORAGE - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index 9b31741..9e733e5 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -23,6 +23,7 @@ #define CONFIG_CMD_EXT4_WRITE #define CONFIG_CMD_FAT #define CONFIG_CMD_FS_GENERIC +#define CONFIG_CMD_GPIO #define CONFIG_CMD_GREPENV #define CONFIG_CMD_MII #define CONFIG_CMD_MMC @@ -30,7 +31,6 @@ #define CONFIG_CMD_USB #define CONFIG_CMD_USB_MASS_STORAGE - /* Memory configurations */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 658f8b2..356220e 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -233,7 +233,6 @@ #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_E1000 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 3998274..bc4a998 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -298,7 +298,6 @@ * TSEC configuration */ #ifdef VME_CADDY2 -#define CONFIG_E1000 #else #define CONFIG_TSEC_ENET /* TSEC ethernet support */ #endif @@ -565,6 +565,7 @@ restart: /* include a debug print as well incase the debug messages are directed to stderr */ debug_cond(DEBUG_INT_STATE, "--- net_loop Abort!\n"); + ret = -EINTR; goto done; } @@ -19,10 +19,10 @@ /* Well known TFTP port # */ #define WELL_KNOWN_PORT 69 /* Millisecs to timeout for lost pkt */ -#define TIMEOUT 5000UL +#define TIMEOUT 100UL #ifndef CONFIG_NET_RETRY_COUNT /* # of timeouts before giving up */ -# define TIMEOUT_COUNT 10 +# define TIMEOUT_COUNT 1000 #else # define TIMEOUT_COUNT (CONFIG_NET_RETRY_COUNT * 2) #endif @@ -711,10 +711,10 @@ void tftp_start(enum proto_t protocol) if (ep != NULL) timeout_ms = simple_strtol(ep, NULL, 10); - if (timeout_ms < 1000) { - printf("TFTP timeout (%ld ms) too low, set min = 1000 ms\n", + if (timeout_ms < 10) { + printf("TFTP timeout (%ld ms) too low, set min = 10 ms\n", timeout_ms); - timeout_ms = 1000; + timeout_ms = 10; } debug("TFTP blocksize = %i, timeout = %ld ms\n", |