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-rw-r--r--arch/powerpc/cpu/ppc4xx/cpu_init.c27
-rw-r--r--arch/powerpc/cpu/ppc4xx/start.S5
-rw-r--r--include/configs/APC405.h1
-rw-r--r--include/ppc440.h1
4 files changed, 25 insertions, 9 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index c04eede..b31bd0b 100644
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -142,22 +142,28 @@ void reconfigure_pll(u32 new_cpu_freq)
* modify it.
*/
if (temp == 1) {
- mfcpr(CPR0_PLLD, reg);
- /* Get current value of fbdv. */
- temp = (reg & PLLD_FBDV_MASK) >> 24;
- fbdv = temp ? temp : 32;
- /* Get current value of lfbdv. */
- temp = (reg & PLLD_LFBDV_MASK);
- lfbdv = temp ? temp : 64;
/*
* Load register that contains current boot strapping option.
*/
mfcpr(CPR0_ICFG, reg);
- /* Shift strapping option into low 3 bits.*/
- reg = (reg >> 28);
+ /*
+ * Strapping option bits (ICS) are already in correct position,
+ * only masking needed.
+ */
+ reg &= CPR0_ICFG_ICS_MASK;
if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) ||
(reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) {
+ mfcpr(CPR0_PLLD, reg);
+
+ /* Get current value of fbdv. */
+ temp = (reg & PLLD_FBDV_MASK) >> 24;
+ fbdv = temp ? temp : 32;
+
+ /* Get current value of lfbdv. */
+ temp = (reg & PLLD_LFBDV_MASK);
+ lfbdv = temp ? temp : 64;
+
/*
* Get current value of FWDVA. Assign current FWDVA to
* new FWDVB.
@@ -165,12 +171,14 @@ void reconfigure_pll(u32 new_cpu_freq)
mfcpr(CPR0_PLLD, reg);
target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16;
fwdvb = target_fwdvb ? target_fwdvb : 8;
+
/*
* Get current value of FWDVB. Assign current FWDVB to
* new FWDVA.
*/
target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8;
fwdva = target_fwdva ? target_fwdva : 16;
+
/*
* Update CPR0_PLLD with switched FWDVA and FWDVB.
*/
@@ -181,6 +189,7 @@ void reconfigure_pll(u32 new_cpu_freq)
((fbdv == 32 ? 0 : fbdv) << 24) |
(lfbdv == 64 ? 0 : lfbdv);
mtcpr(CPR0_PLLD, reg);
+
/* Acknowledge that a reset is required. */
reset_needed = 1;
}
diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S
index 5296dad..4bad32f 100644
--- a/arch/powerpc/cpu/ppc4xx/start.S
+++ b/arch/powerpc/cpu/ppc4xx/start.S
@@ -1459,6 +1459,11 @@ relocate_code:
mtspr SPRN_DTV3,r6
msync
isync
+
+ /* Invalidate data cache, now no longer our stack */
+ dccci 0,0
+ sync
+ isync
#endif /* CONFIG_SYS_INIT_RAM_DCACHE */
/*
diff --git a/include/configs/APC405.h b/include/configs/APC405.h
index 20849bc..a7724ad 100644
--- a/include/configs/APC405.h
+++ b/include/configs/APC405.h
@@ -104,6 +104,7 @@
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
+#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1
diff --git a/include/ppc440.h b/include/ppc440.h
index c807dda..6727753 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1711,6 +1711,7 @@
#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define CPR0_ICFG_RLI_MASK 0x80000000
+#define CPR0_ICFG_ICS_MASK 0x00000007
#define CPR0_SPCID_SPCIDV0_MASK 0x03000000
#define CPR0_SPCID_SPCIDV0_DIV1 0x01000000
#define CPR0_SPCID_SPCIDV0_DIV2 0x02000000