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-rw-r--r--drivers/qe/uec.c50
1 files changed, 50 insertions, 0 deletions
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index d2c430b..ba89247 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -29,6 +29,7 @@
#include "uccf.h"
#include "uec.h"
#include "uec_phy.h"
+#include "miiphy.h"
#if defined(CONFIG_QE)
@@ -125,6 +126,13 @@ static uec_info_t eth4_uec_info = {
};
#endif
+#define MAXCONTROLLERS (4)
+
+static struct eth_device *devlist[MAXCONTROLLERS];
+
+u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
+void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
+
static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
{
uec_t *uec_regs;
@@ -629,6 +637,39 @@ static void phy_change(struct eth_device *dev)
adjust_link(dev);
}
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
+ && !defined(BITBANGMII)
+
+/*
+ * Read a MII PHY register.
+ *
+ * Returns:
+ * 0 on success
+ */
+static int uec_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
+{
+ *value = uec_read_phy_reg(devlist[0], addr, reg);
+
+ return 0;
+}
+
+/*
+ * Write a MII PHY register.
+ *
+ * Returns:
+ * 0 on success
+ */
+static int uec_miiphy_write(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
+{
+ uec_write_phy_reg(devlist[0], addr, reg, value);
+
+ return 0;
+}
+
+#endif
+
static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
{
uec_t *uec_regs;
@@ -1334,6 +1375,8 @@ int uec_initialize(int index)
return -EINVAL;
}
+ devlist[index] = dev;
+
uec->uec_info = uec_info;
sprintf(dev->name, "FSL UEC%d", index);
@@ -1356,6 +1399,13 @@ int uec_initialize(int index)
return err;
}
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
+ && !defined(BITBANGMII)
+ miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write);
+#endif
+
return 1;
}
+
+
#endif /* CONFIG_QE */