diff options
103 files changed, 3013 insertions, 1119 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 4b91b0f..abc9211 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -806,6 +806,10 @@ Prafulla Wadaskar <prafulla@marvell.com> rd6281a ARM926EJS (Kirkwood SoC) sheevaplug ARM926EJS (Kirkwood SoC) +Matthias Weisser <weisserm@arcor.de> + + jadecpu ARM926EJS (MB86R01 SoC) + Richard Woodruff <r-woodruff2@ti.com> omap2420h4 ARM1136EJS @@ -579,6 +579,7 @@ LIST_ARM9=" \ edminiv2 \ guruplug \ imx27lite \ + jadecpu \ lpd7a400 \ magnesium \ mv88f6281gtw_ge \ @@ -253,6 +253,13 @@ ifeq ($(SOC),omap4) LIBS += $(CPUDIR)/omap-common/libomap-common.a endif +ifeq ($(SOC),s5pc1xx) +LIBS += $(CPUDIR)/s5p-common/libs5p-common.a +endif +ifeq ($(SOC),s5pc2xx) +LIBS += $(CPUDIR)/s5p-common/libs5p-common.a +endif + LIBS := $(addprefix $(obj),$(LIBS)) .PHONY : $(LIBS) $(TIMESTAMP_FILE) $(VERSION_FILE) diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c index c63e864..82c978b 100644 --- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c +++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c @@ -81,7 +81,7 @@ unsigned int kw_winctrl_calcsize(unsigned int sizeval) unsigned int j = 0; u32 val = sizeval >> 1; - for (i = 0; val > 0x10000; i++) { + for (i = 0; val >= 0x10000; i++) { j |= (1 << i); val = val >> 1; } diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile new file mode 100644 index 0000000..ce3e5a5 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = clock.o reset.o timer.o +SOBJS = + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c new file mode 100644 index 0000000..70c8c8b --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +/* + * Get the peripheral bus frequency depending on pll pin settings + */ +ulong get_bus_freq(ulong dummy) +{ + struct mb86r0x_crg * crg = (struct mb86r0x_crg *) + MB86R0x_CRG_BASE; + uint32_t pllmode; + + pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE; + + if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20) + return 40000000; + + return 41164767; +} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c new file mode 100644 index 0000000..e7f0f67 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +/* + * Reset the cpu by setting software reset request bit + */ +void reset_cpu(ulong ignored) +{ + struct mb86r0x_crg * crg = (struct mb86r0x_crg *) + MB86R0x_CRG_BASE; + + writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr); + while (1) + /* NOP */; + /* Never reached */ +} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c new file mode 100644 index 0000000..9175b71 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c @@ -0,0 +1,142 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop <stelian.pop@leadtechdesign.com> + * Lead Tech Design <www.leadtechdesign.com> + * + * (C) Copyright 2010 + * Matthias Weisser, Graf-Syteco <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <div64.h> +#include <common.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> + +#define TIMER_LOAD_VAL 0xffffffff +#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256) + +static unsigned long long timestamp; +static ulong lastdec; + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, TIMER_FREQ); + + return tick; +} + +static inline unsigned long long usec_to_tick(unsigned long long usec) +{ + usec *= TIMER_FREQ; + do_div(usec, 1000000); + + return usec; +} + +/* nothing really to do with interrupts, just starts up a counter. */ +int timer_init(void) +{ + struct mb86r0x_timer * timer = (struct mb86r0x_timer *) + MB86R0x_TIMER_BASE; + ulong ctrl = readl(&timer->control); + + writel(TIMER_LOAD_VAL, &timer->load); + + ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S | + MB86R0x_TIMER_SIZE_32; + + writel(ctrl, &timer->control); + + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ +unsigned long long get_ticks(void) +{ + struct mb86r0x_timer * timer = (struct mb86r0x_timer *) + MB86R0x_TIMER_BASE; + ulong now = readl(&timer->value); + + if (now <= lastdec) { + /* normal mode (non roll) */ + /* move stamp forward with absolut diff ticks */ + timestamp += lastdec - now; + } else { + /* we have rollover of incrementer */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + return timestamp; +} + +void reset_timer_masked(void) +{ + struct mb86r0x_timer * timer = (struct mb86r0x_timer *) + MB86R0x_TIMER_BASE; + + /* capture current value time */ + lastdec = readl(&timer->value); + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked(void) +{ + return tick_to_time(get_ticks()); +} + +void __udelay(unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; + + tmo = usec_to_tick(usec); + tmp = get_ticks(); /* get current timestamp */ + + while ((get_ticks() - tmp) < tmo) /* loop till event */ + /*NOP*/; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = TIMER_FREQ; + return tbclk; +} diff --git a/arch/arm/cpu/arm926ejs/orion5x/cpu.c b/arch/arm/cpu/arm926ejs/orion5x/cpu.c index 3740e33..260f88b 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/cpu.c +++ b/arch/arm/cpu/arm926ejs/orion5x/cpu.c @@ -61,7 +61,7 @@ unsigned int orion5x_winctrl_calcsize(unsigned int sizeval) unsigned int j = 0; u32 val = sizeval >> 1; - for (i = 0; val > 0x10000; i++) { + for (i = 0; val >= 0x10000; i++) { j |= (1 << i); val = val >> 1; } diff --git a/arch/arm/cpu/armv7/s5p-common/Makefile b/arch/arm/cpu/armv7/s5p-common/Makefile new file mode 100644 index 0000000..37371f6 --- /dev/null +++ b/arch/arm/cpu/armv7/s5p-common/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2009 Samsung Electronics +# Minkyu Kang <mk7.kang@samsung.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)libs5p-common.a + +COBJS-y += cpu_info.o +COBJS-y += timer.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/s5pc1xx/cpu_info.c b/arch/arm/cpu/armv7/s5p-common/cpu_info.c index f16c0ff..2f6c708 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/cpu_info.c +++ b/arch/arm/cpu/armv7/s5p-common/cpu_info.c @@ -25,15 +25,14 @@ #include <asm/arch/clk.h> /* Default is s5pc100 */ -unsigned int s5pc1xx_cpu_id = 0xC100; +unsigned int s5p_cpu_id = 0xC100; #ifdef CONFIG_ARCH_CPU_INIT int arch_cpu_init(void) { - s5pc1xx_cpu_id = readl(S5PC1XX_PRO_ID); - s5pc1xx_cpu_id = 0xC000 | ((s5pc1xx_cpu_id & 0x00FFF000) >> 12); + s5p_set_cpu_id(); - s5pc1xx_clock_init(); + s5p_clock_init(); return 0; } @@ -41,7 +40,7 @@ int arch_cpu_init(void) u32 get_device_type(void) { - return s5pc1xx_cpu_id; + return s5p_cpu_id; } #ifdef CONFIG_DISPLAY_CPUINFO @@ -50,7 +49,7 @@ int print_cpuinfo(void) char buf[32]; printf("CPU:\tS5P%X@%sMHz\n", - s5pc1xx_cpu_id, strmhz(buf, get_arm_clk())); + s5p_cpu_id, strmhz(buf, get_arm_clk())); return 0; } diff --git a/arch/arm/cpu/armv7/s5pc1xx/timer.c b/arch/arm/cpu/armv7/s5p-common/timer.c index c5df5c5..0490650 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/timer.c +++ b/arch/arm/cpu/armv7/s5p-common/timer.c @@ -44,23 +44,20 @@ static unsigned long long timestamp; /* Monotonic incrementing timer */ static unsigned long lastdec; /* Last decremneter snapshot */ /* macro to read the 16 bit timer */ -static inline struct s5pc1xx_timer *s5pc1xx_get_base_timer(void) +static inline struct s5p_timer *s5p_get_base_timer(void) { - if (cpu_is_s5pc110()) - return (struct s5pc1xx_timer *)S5PC110_TIMER_BASE; - else - return (struct s5pc1xx_timer *)S5PC100_TIMER_BASE; + return (struct s5p_timer *)samsung_get_base_timer(); } int timer_init(void) { - struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer(); + struct s5p_timer *const timer = s5p_get_base_timer(); u32 val; /* * @ PWM Timer 4 * Timer Freq(HZ) = - * PCLK / { (prescaler_value + 1) * (divider_value) } + * PWM_CLK / { (prescaler_value + 1) * (divider_value) } */ /* set prescaler : 16 */ @@ -71,7 +68,7 @@ int timer_init(void) if (count_value == 0) { /* reset initial value */ /* count_value = 2085937.5(HZ) (per 1 sec)*/ - count_value = get_pclk() / ((PRESCALER_1 + 1) * + count_value = get_pwm_clk() / ((PRESCALER_1 + 1) * (MUX_DIV_2 + 1)); /* count_value / 100 = 20859.375(HZ) (per 10 msec) */ @@ -83,13 +80,13 @@ int timer_init(void) lastdec = count_value; val = (readl(&timer->tcon) & ~(0x07 << TCON_TIMER4_SHIFT)) | - S5PC1XX_TCON4_AUTO_RELOAD; + TCON4_AUTO_RELOAD; /* auto reload & manual update */ - writel(val | S5PC1XX_TCON4_UPDATE, &timer->tcon); + writel(val | TCON4_UPDATE, &timer->tcon); /* start PWM timer 4 */ - writel(val | S5PC1XX_TCON4_START, &timer->tcon); + writel(val | TCON4_START, &timer->tcon); timestamp = 0; @@ -154,7 +151,7 @@ void __udelay(unsigned long usec) void reset_timer_masked(void) { - struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer(); + struct s5p_timer *const timer = s5p_get_base_timer(); /* reset time */ lastdec = readl(&timer->tcnto4); @@ -163,7 +160,7 @@ void reset_timer_masked(void) unsigned long get_timer_masked(void) { - struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer(); + struct s5p_timer *const timer = s5p_get_base_timer(); unsigned long now = readl(&timer->tcnto4); if (lastdec >= now) diff --git a/arch/arm/cpu/armv7/s5pc1xx/Makefile b/arch/arm/cpu/armv7/s5pc1xx/Makefile index 3785593..263945f 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/Makefile +++ b/arch/arm/cpu/armv7/s5pc1xx/Makefile @@ -32,9 +32,7 @@ SOBJS = cache.o SOBJS += reset.o COBJS += clock.o -COBJS += cpu_info.o COBJS += sromc.o -COBJS += timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/s5pc1xx/clock.c b/arch/arm/cpu/armv7/s5pc1xx/clock.c index 19619f9..98a27e5 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/clock.c +++ b/arch/arm/cpu/armv7/s5pc1xx/clock.c @@ -38,14 +38,16 @@ #define CONFIG_SYS_CLK_FREQ_C110 24000000 #endif -unsigned long (*get_pclk)(void); +unsigned long (*get_uart_clk)(int dev_index); +unsigned long (*get_pwm_clk)(void); unsigned long (*get_arm_clk)(void); unsigned long (*get_pll_clk)(int); /* s5pc110: return pll clock frequency */ static unsigned long s5pc100_get_pll_clk(int pllreg) { - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, mask, fout; unsigned int freq; @@ -95,7 +97,8 @@ static unsigned long s5pc100_get_pll_clk(int pllreg) /* s5pc100: return pll clock frequency */ static unsigned long s5pc110_get_pll_clk(int pllreg) { - struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc110_clock *clk = + (struct s5pc110_clock *)samsung_get_base_clock(); unsigned long r, m, p, s, mask, fout; unsigned int freq; @@ -151,7 +154,8 @@ static unsigned long s5pc110_get_pll_clk(int pllreg) /* s5pc110: return ARM clock frequency */ static unsigned long s5pc110_get_arm_clk(void) { - struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc110_clock *clk = + (struct s5pc110_clock *)samsung_get_base_clock(); unsigned long div; unsigned long dout_apll, armclk; unsigned int apll_ratio; @@ -170,7 +174,8 @@ static unsigned long s5pc110_get_arm_clk(void) /* s5pc100: return ARM clock frequency */ static unsigned long s5pc100_get_arm_clk(void) { - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); unsigned long div; unsigned long dout_apll, armclk; unsigned int apll_ratio, arm_ratio; @@ -191,7 +196,8 @@ static unsigned long s5pc100_get_arm_clk(void) /* s5pc100: return HCLKD0 frequency */ static unsigned long get_hclk(void) { - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); unsigned long hclkd0; uint div, d0_bus_ratio; @@ -207,7 +213,8 @@ static unsigned long get_hclk(void) /* s5pc100: return PCLKD1 frequency */ static unsigned long get_pclkd1(void) { - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); unsigned long d1_bus, pclkd1; uint div, d1_bus_ratio, pclkd1_ratio; @@ -227,7 +234,8 @@ static unsigned long get_pclkd1(void) /* s5pc110: return HCLKs frequency */ static unsigned long get_hclk_sys(int dom) { - struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc110_clock *clk = + (struct s5pc110_clock *)samsung_get_base_clock(); unsigned long hclk; unsigned int div; unsigned int offset; @@ -255,7 +263,8 @@ static unsigned long get_hclk_sys(int dom) /* s5pc110: return PCLKs frequency */ static unsigned long get_pclk_sys(int dom) { - struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc110_clock *clk = + (struct s5pc110_clock *)samsung_get_base_clock(); unsigned long pclk; unsigned int div; unsigned int offset; @@ -289,15 +298,33 @@ static unsigned long s5pc100_get_pclk(void) return get_pclkd1(); } -void s5pc1xx_clock_init(void) +/* s5pc1xx: return uart clock frequency */ +static unsigned long s5pc1xx_get_uart_clk(int dev_index) +{ + if (cpu_is_s5pc110()) + return s5pc110_get_pclk(); + else + return s5pc100_get_pclk(); +} + +/* s5pc1xx: return pwm clock frequency */ +static unsigned long s5pc1xx_get_pwm_clk(void) +{ + if (cpu_is_s5pc110()) + return s5pc110_get_pclk(); + else + return s5pc100_get_pclk(); +} + +void s5p_clock_init(void) { if (cpu_is_s5pc110()) { get_pll_clk = s5pc110_get_pll_clk; get_arm_clk = s5pc110_get_arm_clk; - get_pclk = s5pc110_get_pclk; } else { get_pll_clk = s5pc100_get_pll_clk; get_arm_clk = s5pc100_get_arm_clk; - get_pclk = s5pc100_get_pclk; } + get_uart_clk = s5pc1xx_get_uart_clk; + get_pwm_clk = s5pc1xx_get_pwm_clk; } diff --git a/arch/arm/cpu/armv7/s5pc1xx/reset.S b/arch/arm/cpu/armv7/s5pc1xx/reset.S index 7f6ff9c..70fa146 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/reset.S +++ b/arch/arm/cpu/armv7/s5pc1xx/reset.S @@ -28,7 +28,7 @@ .globl reset_cpu reset_cpu: - ldr r1, =S5PC1XX_PRO_ID + ldr r1, =S5PC100_PRO_ID ldr r2, [r1] ldr r4, =0x00010000 and r4, r2, r4 diff --git a/arch/arm/cpu/armv7/s5pc1xx/sromc.c b/arch/arm/cpu/armv7/s5pc1xx/sromc.c index 380be81..044d122 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/sromc.c +++ b/arch/arm/cpu/armv7/s5pc1xx/sromc.c @@ -35,12 +35,8 @@ void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf) { u32 tmp; - struct s5pc1xx_smc *srom; - - if (cpu_is_s5pc100()) - srom = (struct s5pc1xx_smc *)S5PC100_SROMC_BASE; - else - srom = (struct s5pc1xx_smc *)S5PC110_SROMC_BASE; + struct s5pc1xx_smc *srom = + (struct s5pc1xx_smc *)samsung_get_base_sromc(); /* Configure SMC_BW register to handle proper SROMC bank */ tmp = srom->bw; diff --git a/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h b/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h new file mode 100644 index 0000000..0bc5279 --- /dev/null +++ b/arch/arm/include/asm/arch-mb86r0x/asm-offsets.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef ASM_OFFSETS_H +#define ASM_OFFSETS_H + +/* + * Offset definitions for DDR controller + */ +#define DDR2_DRIC 0x00 +#define DDR2_DRIC1 0x02 +#define DDR2_DRIC2 0x04 +#define DDR2_DRCA 0x06 +#define DDR2_DRCM 0x08 +#define DDR2_DRCST1 0x0a +#define DDR2_DRCST2 0x0c +#define DDR2_DRCR 0x0e +#define DDR2_DRCF 0x20 +#define DDR2_DRASR 0x30 +#define DDR2_DRIMS 0x50 +#define DDR2_DROS 0x60 +#define DDR2_DRIBSODT1 0x64 +#define DDR2_DROABA 0x70 +#define DDR2_DROBS 0x84 + +/* + * Offset definitions Chip Control Module + */ +#define CCNT_CDCRC 0xec + +/* + * Offset definitions clock reset generator + */ +#define CRG_CRPR 0x00 +#define CRG_CRHA 0x18 +#define CRG_CRPA 0x1c +#define CRG_CRPB 0x20 +#define CRG_CRHB 0x24 +#define CRG_CRAM 0x28 + +/* + * Offset definitions External bus interface + */ +#define MEMC_MCFMODE0 0x00 +#define MEMC_MCFMODE2 0x08 +#define MEMC_MCFMODE4 0x10 +#define MEMC_MCFTIM0 0x20 +#define MEMC_MCFTIM2 0x28 +#define MEMC_MCFTIM4 0x30 +#define MEMC_MCFAREA0 0x40 +#define MEMC_MCFAREA2 0x48 +#define MEMC_MCFAREA4 0x50 + +#endif /* ASM_OFFSETS_H */ diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h new file mode 100644 index 0000000..d1e57c0 --- /dev/null +++ b/arch/arm/include/asm/arch-mb86r0x/hardware.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007 + * + * Author : Carsten Schneider, mycable GmbH + * <cs@mycable.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include <asm/sizes.h> +#include <asm/arch/mb86r0x.h> + +#endif diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h new file mode 100644 index 0000000..36a28b7 --- /dev/null +++ b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h @@ -0,0 +1,573 @@ +/* + * (C) Copyright 2007 + * + * mb86r0x definitions + * + * Author : Carsten Schneider, mycable GmbH + * <cs@mycable.de> + * + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MB86R0X_H +#define MB86R0X_H + +#ifndef __ASSEMBLY__ + +/* GPIO registers */ +struct mb86r0x_gpio { + uint32_t gpdr0; + uint32_t gpdr1; + uint32_t gpdr2; + uint32_t res; + uint32_t gpddr0; + uint32_t gpddr1; + uint32_t gpddr2; +}; + +/* PWM registers */ +struct mb86r0x_pwm { + uint32_t bcr; + uint32_t tpr; + uint32_t pr; + uint32_t dr; + uint32_t cr; + uint32_t sr; + uint32_t ccr; + uint32_t ir; +}; + +/* The mb86r0x chip control (CCNT) register set. */ +struct mb86r0x_ccnt { + uint32_t ccid; + uint32_t csrst; + uint32_t pad0[2]; + uint32_t cist; + uint32_t cistm; + uint32_t cgpio_ist; + uint32_t cgpio_istm; + uint32_t cgpio_ip; + uint32_t cgpio_im; + uint32_t caxi_bw; + uint32_t caxi_ps; + uint32_t cmux_md; + uint32_t cex_pin_st; + uint32_t cmlb; + uint32_t pad1[1]; + uint32_t cusb; + uint32_t pad2[41]; + uint32_t cbsc; + uint32_t cdcrc; + uint32_t cmsr0; + uint32_t cmsr1; + uint32_t pad3[2]; +}; + +/* The mb86r0x clock reset generator */ +struct mb86r0x_crg { + uint32_t crpr; + uint32_t pad0; + uint32_t crwr; + uint32_t crsr; + uint32_t crda; + uint32_t crdb; + uint32_t crha; + uint32_t crpa; + uint32_t crpb; + uint32_t crhb; + uint32_t cram; +}; + +/* The mb86r0x timer */ +struct mb86r0x_timer { + uint32_t load; + uint32_t value; + uint32_t control; + uint32_t intclr; + uint32_t ris; + uint32_t mis; + uint32_t bgload; +}; + +/* mb86r0x gdc display controller */ +struct mb86r0x_gdc_dsp { + /* Display settings */ + uint32_t dcm0; + uint16_t pad00; + uint16_t htp; + uint16_t hdp; + uint16_t hdb; + uint16_t hsp; + uint8_t hsw; + uint8_t vsw; + uint16_t pad01; + uint16_t vtr; + uint16_t vsp; + uint16_t vdp; + uint16_t wx; + uint16_t wy; + uint16_t ww; + uint16_t wh; + + /* Layer 0 */ + uint32_t l0m; + uint32_t l0oa; + uint32_t l0da; + uint16_t l0dx; + uint16_t l0dy; + + /* Layer 1 */ + uint32_t l1m; + uint32_t cbda0; + uint32_t cbda1; + uint32_t pad02; + + /* Layer 2 */ + uint32_t l2m; + uint32_t l2oa0; + uint32_t l2da0; + uint32_t l2oa1; + uint32_t l2da1; + uint16_t l2dx; + uint16_t l2dy; + + /* Layer 3 */ + uint32_t l3m; + uint32_t l3oa0; + uint32_t l3da0; + uint32_t l3oa1; + uint32_t l3da1; + uint16_t l3dx; + uint16_t l3dy; + + /* Layer 4 */ + uint32_t l4m; + uint32_t l4oa0; + uint32_t l4da0; + uint32_t l4oa1; + uint32_t l4da1; + uint16_t l4dx; + uint16_t l4dy; + + /* Layer 5 */ + uint32_t l5m; + uint32_t l5oa0; + uint32_t l5da0; + uint32_t l5oa1; + uint32_t l5da1; + uint16_t l5dx; + uint16_t l5dy; + + /* Cursor */ + uint16_t cutc; + uint8_t cpm; + uint8_t csize; + uint32_t cuoa0; + uint16_t cux0; + uint16_t cuy0; + uint32_t cuoa1; + uint16_t cux1; + uint16_t cuy1; + + /* Layer blending */ + uint32_t l0bld; + uint32_t pad03; + uint32_t l0tc; + uint16_t l3tc; + uint16_t l2tc; + uint32_t pad04[15]; + + /* Display settings */ + uint32_t dcm1; + uint32_t dcm2; + uint32_t dcm3; + uint32_t pad05; + + /* Layer 0 extended */ + uint32_t l0em; + uint16_t l0wx; + uint16_t l0wy; + uint16_t l0ww; + uint16_t l0wh; + uint32_t pad06; + + /* Layer 1 extended */ + uint32_t l1em; + uint16_t l1wx; + uint16_t l1wy; + uint16_t l1ww; + uint16_t l1wh; + uint32_t pad07; + + /* Layer 2 extended */ + uint32_t l2em; + uint16_t l2wx; + uint16_t l2wy; + uint16_t l2ww; + uint16_t l2wh; + uint32_t pad08; + + /* Layer 3 extended */ + uint32_t l3em; + uint16_t l3wx; + uint16_t l3wy; + uint16_t l3ww; + uint16_t l3wh; + uint32_t pad09; + + /* Layer 4 extended */ + uint32_t l4em; + uint16_t l4wx; + uint16_t l4wy; + uint16_t l4ww; + uint16_t l4wh; + uint32_t pad10; + + /* Layer 5 extended */ + uint32_t l5em; + uint16_t l5wx; + uint16_t l5wy; + uint16_t l5ww; + uint16_t l5wh; + uint32_t pad11; + + /* Multi screen control */ + uint32_t msc; + uint32_t pad12[3]; + uint32_t dls; + uint32_t dbgc; + + /* Layer blending */ + uint32_t l1bld; + uint32_t l2bld; + uint32_t l3bld; + uint32_t l4bld; + uint32_t l5bld; + uint32_t pad13; + + /* Extended transparency control */ + uint32_t l0etc; + uint32_t l1etc; + uint32_t l2etc; + uint32_t l3etc; + uint32_t l4etc; + uint32_t l5etc; + uint32_t pad14[10]; + + /* YUV coefficients */ + uint32_t l1ycr0; + uint32_t l1ycr1; + uint32_t l1ycg0; + uint32_t l1ycg1; + uint32_t l1ycb0; + uint32_t l1ycb1; + uint32_t pad15[130]; + + /* Layer palletes */ + uint32_t l0pal[256]; + uint32_t l1pal[256]; + uint32_t pad16[256]; + uint32_t l2pal[256]; + uint32_t l3pal[256]; + uint32_t pad17[256]; + + /* PWM settings */ + uint32_t vpwmm; + uint16_t vpwms; + uint16_t vpwme; + uint32_t vpwmc; + uint32_t pad18[253]; +}; + +/* mb86r0x gdc capture controller */ +struct mb86r0x_gdc_cap { + uint32_t vcm; + uint32_t csc; + uint32_t vcs; + uint32_t pad01; + + uint32_t cbm; + uint32_t cboa; + uint32_t cbla; + uint16_t cihstr; + uint16_t civstr; + uint16_t cihend; + uint16_t civend; + uint32_t pad02; + + uint32_t chp; + uint32_t cvp; + uint32_t pad03[4]; + + uint32_t clpf; + uint32_t pad04; + uint32_t cmss; + uint32_t cmds; + uint32_t pad05[12]; + + uint32_t rgbhc; + uint32_t rgbhen; + uint32_t rgbven; + uint32_t pad06; + uint32_t rgbs; + uint32_t pad07[11]; + + uint32_t rgbcmy; + uint32_t rgbcmcb; + uint32_t rgbcmcr; + uint32_t rgbcmb; + uint32_t pad08[12 + 1984]; +}; + +/* mb86r0x gdc draw */ +struct mb86r0x_gdc_draw { + uint32_t ys; + uint32_t xs; + uint32_t dxdy; + uint32_t xus; + uint32_t dxudy; + uint32_t xls; + uint32_t dxldy; + uint32_t usn; + uint32_t lsn; + uint32_t pad01[7]; + uint32_t rs; + uint32_t drdx; + uint32_t drdy; + uint32_t gs; + uint32_t dgdx; + uint32_t dgdy; + uint32_t bs; + uint32_t dbdx; + uint32_t dbdy; + uint32_t pad02[7]; + uint32_t zs; + uint32_t dzdx; + uint32_t dzdy; + uint32_t pad03[13]; + uint32_t ss; + uint32_t dsdx; + uint32_t dsdy; + uint32_t ts; + uint32_t dtdx; + uint32_t dtdy; + uint32_t qs; + uint32_t dqdx; + uint32_t dqdy; + uint32_t pad04[23]; + uint32_t lpn; + uint32_t lxs; + uint32_t lxde; + uint32_t lys; + uint32_t lyde; + uint32_t lzs; + uint32_t lzde; + uint32_t pad05[13]; + uint32_t pxdc; + uint32_t pydc; + uint32_t pzdc; + uint32_t pad06[25]; + uint32_t rxs; + uint32_t rys; + uint32_t rsizex; + uint32_t rsizey; + uint32_t pad07[12]; + uint32_t saddr; + uint32_t sstride; + uint32_t srx; + uint32_t sry; + uint32_t daddr; + uint32_t dstride; + uint32_t drx; + uint32_t dry; + uint32_t brsizex; + uint32_t brsizey; + uint32_t tcolor; + uint32_t pad08[93]; + uint32_t blpo; + uint32_t pad09[7]; + uint32_t ctr; + uint32_t ifsr; + uint32_t ifcnt; + uint32_t sst; + uint32_t ds; + uint32_t pst; + uint32_t est; + uint32_t pad10; + uint32_t mdr0; + uint32_t mdr1; + uint32_t mdr2; + uint32_t mdr3; + uint32_t mdr4; + uint32_t pad14[2]; + uint32_t mdr7; + uint32_t fbr; + uint32_t xres; + uint32_t zbr; + uint32_t tbr; + uint32_t pfbr; + uint32_t cxmin; + uint32_t cxmax; + uint32_t cymin; + uint32_t cymax; + uint32_t txs; + uint32_t tis; + uint32_t toa; + uint32_t sho; + uint32_t abr; + uint32_t pad15[2]; + uint32_t fc; + uint32_t bc; + uint32_t alf; + uint32_t blp; + uint32_t pad16; + uint32_t tbc; + uint32_t pad11[42]; + uint32_t lx0dc; + uint32_t ly0dc; + uint32_t lx1dc; + uint32_t ly1dc; + uint32_t pad12[12]; + uint32_t x0dc; + uint32_t y0dc; + uint32_t x1dc; + uint32_t y1dc; + uint32_t x2dc; + uint32_t y2dc; + uint32_t pad13[666]; +}; + +/* mb86r0x gdc geometry engine */ +struct mb86r0x_gdc_geom { + uint32_t gctr; + uint32_t pad00[15]; + uint32_t gmdr0; + uint32_t gmdr1; + uint32_t gmdr2; + uint32_t pad01[237]; + uint32_t dfifog; + uint32_t pad02[767]; +}; + +/* mb86r0x gdc */ +struct mb86r0x_gdc { + uint32_t pad00[2]; + uint32_t lts; + uint32_t pad01; + uint32_t lsta; + uint32_t pad02[3]; + uint32_t ist; + uint32_t imask; + uint32_t pad03[6]; + uint32_t lsa; + uint32_t lco; + uint32_t lreq; + + uint32_t pad04[16*1024 - 19]; + struct mb86r0x_gdc_dsp dsp0; + struct mb86r0x_gdc_dsp dsp1; + uint32_t pad05[4*1024 - 2]; + uint32_t vccc; + uint32_t vcsr; + struct mb86r0x_gdc_cap cap0; + struct mb86r0x_gdc_cap cap1; + uint32_t pad06[4*1024]; + uint32_t texture_base[16*1024]; + struct mb86r0x_gdc_draw draw; + uint32_t pad07[7*1024]; + struct mb86r0x_gdc_geom geom; + uint32_t pad08[7*1024]; +}; + +#endif /* __ASSEMBLY__ */ + +/* + * Physical Address Defines + */ +#define MB86R0x_DDR2_BASE 0xf3000000 +#define MB86R0x_GDC_BASE 0xf1fc0000 +#define MB86R0x_CCNT_BASE 0xfff42000 +#define MB86R0x_CAN0_BASE 0xfff54000 +#define MB86R0x_CAN1_BASE 0xfff55000 +#define MB86R0x_I2C0_BASE 0xfff56000 +#define MB86R0x_I2C1_BASE 0xfff57000 +#define MB86R0x_EHCI_BASE 0xfff80000 +#define MB86R0x_OHCI_BASE 0xfff81000 +#define MB86R0x_IRC1_BASE 0xfffb0000 +#define MB86R0x_MEMC_BASE 0xfffc0000 +#define MB86R0x_TIMER_BASE 0xfffe0000 +#define MB86R0x_UART0_BASE 0xfffe1000 +#define MB86R0x_UART1_BASE 0xfffe2000 +#define MB86R0x_IRCE_BASE 0xfffe4000 +#define MB86R0x_CRG_BASE 0xfffe7000 +#define MB86R0x_IRC0_BASE 0xfffe8000 +#define MB86R0x_GPIO_BASE 0xfffe9000 +#define MB86R0x_PWM0_BASE 0xfff41000 +#define MB86R0x_PWM1_BASE 0xfff41100 + +#define MB86R0x_CRSR_SWRSTREQ (1 << 1) + +/* + * Timer register bits + */ +#define MB86R0x_TIMER_ENABLE (1 << 7) +#define MB86R0x_TIMER_MODE_MSK (1 << 6) +#define MB86R0x_TIMER_MODE_FR (0 << 6) +#define MB86R0x_TIMER_MODE_PD (1 << 6) + +#define MB86R0x_TIMER_INT_EN (1 << 5) +#define MB86R0x_TIMER_PRS_MSK (3 << 2) +#define MB86R0x_TIMER_PRS_4S (1 << 2) +#define MB86R0x_TIMER_PRS_8S (1 << 3) +#define MB86R0x_TIMER_SIZE_32 (1 << 1) +#define MB86R0x_TIMER_ONE_SHT (1 << 0) + +/* + * Clock reset generator bits + */ +#define MB86R0x_CRG_CRPR_PLLRDY (1 << 8) +#define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0) +#define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0) +/* + * DDR2 controller bits + */ +#define MB86R0x_DDR2_DRCI_DRINI (1 << 15) +#define MB86R0x_DDR2_DRCI_CKEN (1 << 14) +#define MB86R0x_DDR2_DRCI_DRCMD (1 << 0) +#define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \ + MB86R0x_DDR2_DRCI_CKEN | \ + MB86R0x_DDR2_DRCI_DRCMD) +#define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \ + MB86R0x_DDR2_DRCI_CKEN) +#define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN +#endif /* MB86R0X_H */ diff --git a/arch/arm/include/asm/arch-omap24xx/i2c.h b/arch/arm/include/asm/arch-omap24xx/i2c.h index 19046aa..6f64519 100644 --- a/arch/arm/include/asm/arch-omap24xx/i2c.h +++ b/arch/arm/include/asm/arch-omap24xx/i2c.h @@ -36,7 +36,9 @@ struct i2c { unsigned short stat; /* 0x08 */ unsigned short res3; unsigned short iv; /* 0x0C */ - unsigned short res4[3]; + unsigned short res4; + unsigned short syss; /* 0x10 */ + unsigned short res4p1; unsigned short buf; /* 0x14 */ unsigned short res5; unsigned short cnt; /* 0x18 */ @@ -63,110 +65,4 @@ struct i2c { #define I2C_BUS_MAX 2 -/* I2C masks */ - -/* I2C Interrupt Enable Register (I2C_IE): */ -#define I2C_IE_GC_IE (1 << 5) -#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ -#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ -#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ -#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ - -/* I2C Status Register (I2C_STAT): */ - -#define I2C_STAT_SBD (1 << 15) /* Single byte data */ -#define I2C_STAT_BB (1 << 12) /* Bus busy */ -#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define I2C_STAT_GC (1 << 5) -#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ -#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ - - -/* I2C Interrupt Code Register (I2C_INTCODE): */ - -#define I2C_INTCODE_MASK 7 -#define I2C_INTCODE_NONE 0 -#define I2C_INTCODE_AL 1 /* Arbitration lost */ -#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ -#define I2C_INTCODE_ARDY 3 /* Register access ready */ -#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ -#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ - -/* I2C Buffer Configuration Register (I2C_BUF): */ - -#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ -#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ - -/* I2C Configuration Register (I2C_CON): */ - -#define I2C_CON_EN (1 << 15) /* I2C module enable */ -#define I2C_CON_BE (1 << 14) /* Big endian mode */ -#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ -#define I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode (master mode only) */ -#define I2C_CON_XA (1 << 8) /* Expand address */ -#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ -#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ - -/* I2C System Test Register (I2C_SYSTEST): */ - -#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode (on breakpoint) */ -#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ -#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ -#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ -#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ -#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ -#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ - -/* These values were copied from omap3, include/asm-arm/arch-omap3/i2c.h. */ -#define OMAP_I2C_STANDARD 100000 -#define OMAP_I2C_FAST_MODE 400000 -#define OMAP_I2C_HIGH_SPEED 3400000 - -#define SYSTEM_CLOCK_12 12000000 -#define SYSTEM_CLOCK_13 13000000 -#define SYSTEM_CLOCK_192 19200000 -#define SYSTEM_CLOCK_96 96000000 - -#ifndef I2C_IP_CLK -#define I2C_IP_CLK SYSTEM_CLOCK_96 -#endif - -#ifndef I2C_INTERNAL_SAMPLING_CLK -#define I2C_INTERNAL_SAMPLING_CLK 19200000 -#endif - -/* These are the trim values for standard and fast speed */ -#ifndef I2C_FASTSPEED_SCLL_TRIM -#define I2C_FASTSPEED_SCLL_TRIM 6 -#endif -#ifndef I2C_FASTSPEED_SCLH_TRIM -#define I2C_FASTSPEED_SCLH_TRIM 6 -#endif - -/* These are the trim values for high speed */ -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM -#define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM -#define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM -#define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM I2C_FASTSPEED_SCLL_TRIM -#endif -#ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM -#define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM I2C_FASTSPEED_SCLH_TRIM -#endif - -#define I2C_PSC_MAX 0x0f -#define I2C_PSC_MIN 0x00 - - #endif diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h b/arch/arm/include/asm/arch-orion5x/cpu.h index 80717f8..6ce02a9 100644 --- a/arch/arm/include/asm/arch-orion5x/cpu.h +++ b/arch/arm/include/asm/arch-orion5x/cpu.h @@ -76,7 +76,7 @@ enum orion5x_cpu_attrib { /* * Device Address MAP BAR values -/* + * * All addresses and sizes not defined by board code * will be given default values here. */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/clk.h b/arch/arm/include/asm/arch-s5pc1xx/clk.h index 3e59abe..3488eb7 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/clk.h +++ b/arch/arm/include/asm/arch-s5pc1xx/clk.h @@ -29,10 +29,11 @@ #define HPLL 3 #define VPLL 4 -void s5pc1xx_clock_init(void); +void s5p_clock_init(void); extern unsigned long (*get_pll_clk)(int pllreg); extern unsigned long (*get_arm_clk)(void); -extern unsigned long (*get_pclk)(void); +extern unsigned long (*get_pwm_clk)(void); +extern unsigned long (*get_uart_clk)(int dev_index); #endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/cpu.h b/arch/arm/include/asm/arch-s5pc1xx/cpu.h index b3af8cc..e74959f 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/cpu.h +++ b/arch/arm/include/asm/arch-s5pc1xx/cpu.h @@ -25,9 +25,9 @@ #define S5PC1XX_ADDR_BASE 0xE0000000 -#define S5PC1XX_CLOCK_BASE 0xE0100000 - /* S5PC100 */ +#define S5PC100_PRO_ID 0xE0000000 +#define S5PC100_CLOCK_BASE 0xE0100000 #define S5PC100_GPIO_BASE 0xE0300000 #define S5PC100_VIC0_BASE 0xE4000000 #define S5PC100_VIC1_BASE 0xE4100000 @@ -41,6 +41,8 @@ #define S5PC100_MMC_BASE 0xED800000 /* S5PC110 */ +#define S5PC110_PRO_ID 0xE0000000 +#define S5PC110_CLOCK_BASE 0xE0100000 #define S5PC110_GPIO_BASE 0xE0200000 #define S5PC110_PWMTIMER_BASE 0xE2500000 #define S5PC110_WATCHDOG_BASE 0xE2700000 @@ -54,21 +56,44 @@ #define S5PC110_VIC2_BASE 0xF2200000 #define S5PC110_VIC3_BASE 0xF2300000 -/* Chip ID */ -#define S5PC1XX_PRO_ID 0xE0000000 - #ifndef __ASSEMBLY__ +#include <asm/io.h> /* CPU detection macros */ -extern unsigned int s5pc1xx_cpu_id; +extern unsigned int s5p_cpu_id; + +static inline void s5p_set_cpu_id(void) +{ + s5p_cpu_id = readl(S5PC100_PRO_ID); + s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12); +} #define IS_SAMSUNG_TYPE(type, id) \ static inline int cpu_is_##type(void) \ { \ - return s5pc1xx_cpu_id == id ? 1 : 0; \ + return s5p_cpu_id == id ? 1 : 0; \ } IS_SAMSUNG_TYPE(s5pc100, 0xc100) IS_SAMSUNG_TYPE(s5pc110, 0xc110) + +#define SAMSUNG_BASE(device, base) \ +static inline unsigned int samsung_get_base_##device(void) \ +{ \ + if (cpu_is_s5pc100()) \ + return S5PC100_##base; \ + else if (cpu_is_s5pc110()) \ + return S5PC110_##base; \ + else \ + return 0; \ +} + +SAMSUNG_BASE(clock, CLOCK_BASE) +SAMSUNG_BASE(gpio, GPIO_BASE) +SAMSUNG_BASE(pro_id, PRO_ID) +SAMSUNG_BASE(mmc, MMC_BASE) +SAMSUNG_BASE(sromc, SROMC_BASE) +SAMSUNG_BASE(timer, PWMTIMER_BASE) +SAMSUNG_BASE(uart, UART_BASE) #endif #endif /* _S5PC1XX_CPU_H */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index 9a7faed..2df33a6 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -33,96 +33,96 @@ struct s5p_gpio_bank { }; struct s5pc100_gpio { - struct s5p_gpio_bank gpio_a0; - struct s5p_gpio_bank gpio_a1; - struct s5p_gpio_bank gpio_b; - struct s5p_gpio_bank gpio_c; - struct s5p_gpio_bank gpio_d; - struct s5p_gpio_bank gpio_e0; - struct s5p_gpio_bank gpio_e1; - struct s5p_gpio_bank gpio_f0; - struct s5p_gpio_bank gpio_f1; - struct s5p_gpio_bank gpio_f2; - struct s5p_gpio_bank gpio_f3; - struct s5p_gpio_bank gpio_g0; - struct s5p_gpio_bank gpio_g1; - struct s5p_gpio_bank gpio_g2; - struct s5p_gpio_bank gpio_g3; - struct s5p_gpio_bank gpio_i; - struct s5p_gpio_bank gpio_j0; - struct s5p_gpio_bank gpio_j1; - struct s5p_gpio_bank gpio_j2; - struct s5p_gpio_bank gpio_j3; - struct s5p_gpio_bank gpio_j4; - struct s5p_gpio_bank gpio_k0; - struct s5p_gpio_bank gpio_k1; - struct s5p_gpio_bank gpio_k2; - struct s5p_gpio_bank gpio_k3; - struct s5p_gpio_bank gpio_l0; - struct s5p_gpio_bank gpio_l1; - struct s5p_gpio_bank gpio_l2; - struct s5p_gpio_bank gpio_l3; - struct s5p_gpio_bank gpio_l4; - struct s5p_gpio_bank gpio_h0; - struct s5p_gpio_bank gpio_h1; - struct s5p_gpio_bank gpio_h2; - struct s5p_gpio_bank gpio_h3; + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank b; + struct s5p_gpio_bank c; + struct s5p_gpio_bank d; + struct s5p_gpio_bank e0; + struct s5p_gpio_bank e1; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank f2; + struct s5p_gpio_bank f3; + struct s5p_gpio_bank g0; + struct s5p_gpio_bank g1; + struct s5p_gpio_bank g2; + struct s5p_gpio_bank g3; + struct s5p_gpio_bank i; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; + struct s5p_gpio_bank j2; + struct s5p_gpio_bank j3; + struct s5p_gpio_bank j4; + struct s5p_gpio_bank k0; + struct s5p_gpio_bank k1; + struct s5p_gpio_bank k2; + struct s5p_gpio_bank k3; + struct s5p_gpio_bank l0; + struct s5p_gpio_bank l1; + struct s5p_gpio_bank l2; + struct s5p_gpio_bank l3; + struct s5p_gpio_bank l4; + struct s5p_gpio_bank h0; + struct s5p_gpio_bank h1; + struct s5p_gpio_bank h2; + struct s5p_gpio_bank h3; }; struct s5pc110_gpio { - struct s5p_gpio_bank gpio_a0; - struct s5p_gpio_bank gpio_a1; - struct s5p_gpio_bank gpio_b; - struct s5p_gpio_bank gpio_c0; - struct s5p_gpio_bank gpio_c1; - struct s5p_gpio_bank gpio_d0; - struct s5p_gpio_bank gpio_d1; - struct s5p_gpio_bank gpio_e0; - struct s5p_gpio_bank gpio_e1; - struct s5p_gpio_bank gpio_f0; - struct s5p_gpio_bank gpio_f1; - struct s5p_gpio_bank gpio_f2; - struct s5p_gpio_bank gpio_f3; - struct s5p_gpio_bank gpio_g0; - struct s5p_gpio_bank gpio_g1; - struct s5p_gpio_bank gpio_g2; - struct s5p_gpio_bank gpio_g3; - struct s5p_gpio_bank gpio_i; - struct s5p_gpio_bank gpio_j0; - struct s5p_gpio_bank gpio_j1; - struct s5p_gpio_bank gpio_j2; - struct s5p_gpio_bank gpio_j3; - struct s5p_gpio_bank gpio_j4; - struct s5p_gpio_bank gpio_mp0_1; - struct s5p_gpio_bank gpio_mp0_2; - struct s5p_gpio_bank gpio_mp0_3; - struct s5p_gpio_bank gpio_mp0_4; - struct s5p_gpio_bank gpio_mp0_5; - struct s5p_gpio_bank gpio_mp0_6; - struct s5p_gpio_bank gpio_mp0_7; - struct s5p_gpio_bank gpio_mp1_0; - struct s5p_gpio_bank gpio_mp1_1; - struct s5p_gpio_bank gpio_mp1_2; - struct s5p_gpio_bank gpio_mp1_3; - struct s5p_gpio_bank gpio_mp1_4; - struct s5p_gpio_bank gpio_mp1_5; - struct s5p_gpio_bank gpio_mp1_6; - struct s5p_gpio_bank gpio_mp1_7; - struct s5p_gpio_bank gpio_mp1_8; - struct s5p_gpio_bank gpio_mp2_0; - struct s5p_gpio_bank gpio_mp2_1; - struct s5p_gpio_bank gpio_mp2_2; - struct s5p_gpio_bank gpio_mp2_3; - struct s5p_gpio_bank gpio_mp2_4; - struct s5p_gpio_bank gpio_mp2_5; - struct s5p_gpio_bank gpio_mp2_6; - struct s5p_gpio_bank gpio_mp2_7; - struct s5p_gpio_bank gpio_mp2_8; + struct s5p_gpio_bank a0; + struct s5p_gpio_bank a1; + struct s5p_gpio_bank b; + struct s5p_gpio_bank c0; + struct s5p_gpio_bank c1; + struct s5p_gpio_bank d0; + struct s5p_gpio_bank d1; + struct s5p_gpio_bank e0; + struct s5p_gpio_bank e1; + struct s5p_gpio_bank f0; + struct s5p_gpio_bank f1; + struct s5p_gpio_bank f2; + struct s5p_gpio_bank f3; + struct s5p_gpio_bank g0; + struct s5p_gpio_bank g1; + struct s5p_gpio_bank g2; + struct s5p_gpio_bank g3; + struct s5p_gpio_bank i; + struct s5p_gpio_bank j0; + struct s5p_gpio_bank j1; + struct s5p_gpio_bank j2; + struct s5p_gpio_bank j3; + struct s5p_gpio_bank j4; + struct s5p_gpio_bank mp0_1; + struct s5p_gpio_bank mp0_2; + struct s5p_gpio_bank mp0_3; + struct s5p_gpio_bank mp0_4; + struct s5p_gpio_bank mp0_5; + struct s5p_gpio_bank mp0_6; + struct s5p_gpio_bank mp0_7; + struct s5p_gpio_bank mp1_0; + struct s5p_gpio_bank mp1_1; + struct s5p_gpio_bank mp1_2; + struct s5p_gpio_bank mp1_3; + struct s5p_gpio_bank mp1_4; + struct s5p_gpio_bank mp1_5; + struct s5p_gpio_bank mp1_6; + struct s5p_gpio_bank mp1_7; + struct s5p_gpio_bank mp1_8; + struct s5p_gpio_bank mp2_0; + struct s5p_gpio_bank mp2_1; + struct s5p_gpio_bank mp2_2; + struct s5p_gpio_bank mp2_3; + struct s5p_gpio_bank mp2_4; + struct s5p_gpio_bank mp2_5; + struct s5p_gpio_bank mp2_6; + struct s5p_gpio_bank mp2_7; + struct s5p_gpio_bank mp2_8; struct s5p_gpio_bank res1[48]; - struct s5p_gpio_bank gpio_h0; - struct s5p_gpio_bank gpio_h1; - struct s5p_gpio_bank gpio_h2; - struct s5p_gpio_bank gpio_h3; + struct s5p_gpio_bank h0; + struct s5p_gpio_bank h1; + struct s5p_gpio_bank h2; + struct s5p_gpio_bank h3; }; /* functions */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h index ac560c2..68c59d1 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h +++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h @@ -56,7 +56,7 @@ struct s5p_mmc { unsigned int control4; unsigned char res4[0x6e]; unsigned short hcver; - unsigned char res5[0xFFF00]; + unsigned char res5[0xFFF02]; }; struct mmc_host { diff --git a/arch/arm/include/asm/arch-s5pc1xx/pwm.h b/arch/arm/include/asm/arch-s5pc1xx/pwm.h index e02a8d8..0369968 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/pwm.h +++ b/arch/arm/include/asm/arch-s5pc1xx/pwm.h @@ -22,19 +22,15 @@ #ifndef __ASM_ARM_ARCH_PWM_H_ #define __ASM_ARM_ARCH_PWM_H_ -/* PWM timer addressing */ -#define S5PC100_TIMER_BASE S5PC100_PWMTIMER_BASE -#define S5PC110_TIMER_BASE S5PC110_PWMTIMER_BASE - /* Interval mode(Auto Reload) of PWM Timer 4 */ -#define S5PC1XX_TCON4_AUTO_RELOAD (1 << 22) +#define TCON4_AUTO_RELOAD (1 << 22) /* Update TCNTB4 */ -#define S5PC1XX_TCON4_UPDATE (1 << 21) +#define TCON4_UPDATE (1 << 21) /* start bit of PWM Timer 4 */ -#define S5PC1XX_TCON4_START (1 << 20) +#define TCON4_START (1 << 20) #ifndef __ASSEMBLY__ -struct s5pc1xx_timer { +struct s5p_timer { unsigned int tcfg0; unsigned int tcfg1; unsigned int tcon; diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 6379534..d9c6544 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -40,11 +40,10 @@ int checkcpu (void) return (0); } - -int do_reset (void) +int do_reset(void) { - void (*rst)(void) = (void(*)(void))CONFIG_SYS_RESET_ADDR; - disable_interrupts (); - rst(); - return(0); + disable_interrupts(); + /* indirect call to go beyond 256MB limitation of toolchain */ + nios2_callr(CONFIG_SYS_RESET_ADDR); + return 0; } diff --git a/arch/nios2/include/asm/system.h b/arch/nios2/include/asm/system.h index bb03ca5..086d92b 100644 --- a/arch/nios2/include/asm/system.h +++ b/arch/nios2/include/asm/system.h @@ -56,4 +56,9 @@ ((flags & NIOS2_STATUS_PIE_MSK) == 0x0); \ }) +/* indirect call to go beyond 256MB limitation of toolchain */ +#define nios2_callr(addr) __asm__ __volatile__ ( \ + "callr %0" \ + : : "r" (addr)) + #endif /* __ASM_NIOS2_SYSTEM_H */ diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index e25a113..40a4d15 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -42,7 +42,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima if (boot_get_fdt(flag, argc, argv, images, &of_flat_tree, &of_size)) return 1; #endif - if (!of_flat_tree) + if (!of_flat_tree && argc > 3) of_flat_tree = (char *)simple_strtoul(argv[3], NULL, 16); if (of_flat_tree) initrd_end = (ulong)of_flat_tree; diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index f15d43c..3f80700 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -74,7 +74,7 @@ int checkcpu (void) puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2c3be6d..27236a0 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -179,7 +179,7 @@ static void corenet_tb_init(void) volatile ccsr_rcpm_t *rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); volatile ccsr_pic_t *pic = - (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); u32 whoami = in_be32(&pic->whoami); /* Enable the timebase register for this core */ diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 8e7b827..4540364 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -54,18 +54,19 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); if (reg) { + u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; + val = cpu_to_fdt32(val); if (*reg == id) { - fdt_setprop_string(blob, off, "status", "okay"); + fdt_setprop_string(blob, off, "status", + "okay"); } else { - u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr; - val = cpu_to_fdt32(val); fdt_setprop_string(blob, off, "status", "disabled"); - fdt_setprop_string(blob, off, "enable-method", - "spin-table"); - fdt_setprop(blob, off, "cpu-release-addr", - &val, sizeof(val)); } + fdt_setprop_string(blob, off, "enable-method", + "spin-table"); + fdt_setprop(blob, off, "cpu-release-addr", + &val, sizeof(val)); } else { printf ("cpu NULL\n"); } diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c index ac8c01a..a62b031 100644 --- a/arch/powerpc/cpu/mpc85xx/interrupts.c +++ b/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -35,7 +35,7 @@ int interrupt_init_cpu(unsigned int *decrementer_count) { - ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR; + ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; out_be32(&pic->gcr, MPC85xx_PICGCR_RST); while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST) diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index e05257c..603baef 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -38,7 +38,7 @@ u32 get_my_id() int cpu_reset(int nr) { - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); out_be32(&pic->pir, 1 << nr); /* the dummy read works around an errata on early 85xx MP PICs */ (void)in_be32(&pic->pir); @@ -207,7 +207,7 @@ static void plat_mp_up(unsigned long bootpg) gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); - pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1; @@ -272,7 +272,7 @@ static void plat_mp_up(unsigned long bootpg) volatile u32 bpcr; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); u32 devdisr; int timeout = 10; diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index 3861146..a6cfaa5 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -81,10 +81,10 @@ struct liodn_id_table fman2_liodn_tbl[] = { #endif struct liodn_id_table sec_liodn_tbl[] = { - SET_SEC_JQ_LIODN_ENTRY(0, 146, 154), - SET_SEC_JQ_LIODN_ENTRY(1, 147, 155), - SET_SEC_JQ_LIODN_ENTRY(2, 178, 186), - SET_SEC_JQ_LIODN_ENTRY(3, 179, 187), + SET_SEC_JR_LIODN_ENTRY(0, 146, 154), + SET_SEC_JR_LIODN_ENTRY(1, 147, 155), + SET_SEC_JR_LIODN_ENTRY(2, 178, 186), + SET_SEC_JR_LIODN_ENTRY(3, 179, 187), SET_SEC_RTIC_LIODN_ENTRY(a, 144), SET_SEC_RTIC_LIODN_ENTRY(b, 145), SET_SEC_RTIC_LIODN_ENTRY(c, 176), diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index 7e96664..7800717 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -288,7 +288,7 @@ UnknownException(struct pt_regs *regs) void ExtIntException(struct pt_regs *regs) { - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); uint vect; diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 97a94f4..5b30fbd 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -110,13 +110,15 @@ struct cpu_type *identify_cpu(u32 ver) } int cpu_numcores() { - ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC85xx_PIC_ADDR; + ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; struct cpu_type *cpu = gd->cpu; /* better to query feature reporting register than just assume 1 */ +#define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00 +#define MPC8xxx_PICFRR_NCPU_SHIFT 8 if (cpu == &cpu_type_unknown) - return ((in_be32(&pic->frr) & MPC85xx_PICFRR_NCPU_MASK) >> - MPC85xx_PICFRR_NCPU_SHIFT) + 1; + return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >> + MPC8xxx_PICFRR_NCPU_SHIFT) + 1; return cpu->num_cores; } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index dccb7aa..e82082e 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -613,6 +613,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, #if defined(CONFIG_FSL_DDR3) md_en = popts->mirrored_dimm; #endif + rcw_en = popts->registered_dimm_en; qd_en = popts->quad_rank_present ? 1 : 0; ddr->ddr_sdram_cfg_2 = (0 | ((frc_sr & 0x1) << 31) diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index c04eede..b31bd0b 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -142,22 +142,28 @@ void reconfigure_pll(u32 new_cpu_freq) * modify it. */ if (temp == 1) { - mfcpr(CPR0_PLLD, reg); - /* Get current value of fbdv. */ - temp = (reg & PLLD_FBDV_MASK) >> 24; - fbdv = temp ? temp : 32; - /* Get current value of lfbdv. */ - temp = (reg & PLLD_LFBDV_MASK); - lfbdv = temp ? temp : 64; /* * Load register that contains current boot strapping option. */ mfcpr(CPR0_ICFG, reg); - /* Shift strapping option into low 3 bits.*/ - reg = (reg >> 28); + /* + * Strapping option bits (ICS) are already in correct position, + * only masking needed. + */ + reg &= CPR0_ICFG_ICS_MASK; if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) || (reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) { + mfcpr(CPR0_PLLD, reg); + + /* Get current value of fbdv. */ + temp = (reg & PLLD_FBDV_MASK) >> 24; + fbdv = temp ? temp : 32; + + /* Get current value of lfbdv. */ + temp = (reg & PLLD_LFBDV_MASK); + lfbdv = temp ? temp : 64; + /* * Get current value of FWDVA. Assign current FWDVA to * new FWDVB. @@ -165,12 +171,14 @@ void reconfigure_pll(u32 new_cpu_freq) mfcpr(CPR0_PLLD, reg); target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16; fwdvb = target_fwdvb ? target_fwdvb : 8; + /* * Get current value of FWDVB. Assign current FWDVB to * new FWDVA. */ target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8; fwdva = target_fwdva ? target_fwdva : 16; + /* * Update CPR0_PLLD with switched FWDVA and FWDVB. */ @@ -181,6 +189,7 @@ void reconfigure_pll(u32 new_cpu_freq) ((fbdv == 32 ? 0 : fbdv) << 24) | (lfbdv == 64 ? 0 : lfbdv); mtcpr(CPR0_PLLD, reg); + /* Acknowledge that a reset is required. */ reset_needed = 1; } diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 5296dad..4bad32f 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -1459,6 +1459,11 @@ relocate_code: mtspr SPRN_DTV3,r6 msync isync + + /* Invalidate data cache, now no longer our stack */ + dccci 0,0 + sync + isync #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ /* diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index acdc99a..4c17fe2 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -115,11 +115,11 @@ extern void fdt_fixup_liodn(void *blob); FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ -#define SET_SEC_JQ_LIODN_ENTRY(jqNum, liodnA, liodnB) \ - SET_LIODN_ENTRY_2("fsl,sec4.0-job-queue", liodnA, liodnB,\ - offsetof(ccsr_sec_t, jqliodnr[jqNum].ls) + \ +#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \ + SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\ + offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jqNum) + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum) /* This is a bit evil since we treat rtic param as both a string & hex value */ #define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index c1382c8..3dd2b7f 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -760,8 +760,6 @@ typedef struct ccsr_pic { u32 eoi; /* End Of IRQ */ u8 res9[3916]; u32 frr; /* Feature Reporting */ -#define MPC85xx_PICFRR_NCPU_MASK 0x00001f00 -#define MPC85xx_PICFRR_NCPU_SHIFT 8 u8 res10[28]; u32 gcr; /* Global Configuration */ #define MPC85xx_PICGCR_RST 0x80000000 @@ -2065,7 +2063,7 @@ typedef struct ccsr_sec { struct { u32 ms; /* Job Ring LIODN Register, MS */ u32 ls; /* Job Ring LIODN Register, LS */ - } jqliodnr[4]; + } jrliodnr[4]; u8 res2[0x30]; struct { u32 ms; /* RTIC LIODN Register, MS */ @@ -2110,8 +2108,8 @@ typedef struct ccsr_sec { #define SEC_CTPR_MS_AXI_LIODN 0x08000000 #define SEC_CTPR_MS_QI 0x02000000 #define SEC_RVID_MA 0x0f000000 -#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000 -#define SEC_CHANUM_MS_JQNUM_SHIFT 28 +#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 +#define SEC_CHANUM_MS_JRNUM_SHIFT 28 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 #define SEC_CHANUM_MS_DECONUM_SHIFT 24 #endif @@ -2301,7 +2299,7 @@ typedef struct ccsr_pme { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) -#define CONFIG_SYS_MPC85xx_PIC_ADDR \ +#define CONFIG_SYS_MPC8xxx_PIC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) #define CONFIG_SYS_MPC85xx_CPM_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h index 4bebb68..4e60cbb 100644 --- a/arch/powerpc/include/asm/immap_86xx.h +++ b/arch/powerpc/include/asm/immap_86xx.h @@ -1250,12 +1250,15 @@ typedef struct immap { extern immap_t *immr; -#define CONFIG_SYS_MPC86xx_DDR_OFFSET (0x2000) +#define CONFIG_SYS_MPC86xx_DDR_OFFSET 0x2000 #define CONFIG_SYS_MPC86xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET) -#define CONFIG_SYS_MPC86xx_DDR2_OFFSET (0x6000) +#define CONFIG_SYS_MPC86xx_DDR2_OFFSET 0x6000 #define CONFIG_SYS_MPC86xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET) -#define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000) +#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET) +#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000 +#define CONFIG_SYS_MPC8xxx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET) + #define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000 #ifdef CONFIG_MPC8610 diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds index 9a6cd1b..3c4fbe3 100644 --- a/board/dbau1x00/u-boot.lds +++ b/board/dbau1x00/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/espt/lowlevel_init.S b/board/espt/lowlevel_init.S index 7f0686c..1a11eee 100644 --- a/board/espt/lowlevel_init.S +++ b/board/espt/lowlevel_init.S @@ -206,26 +206,31 @@ PKDR_A: .long 0xFFEF0034 /* GPIO Set data */ PADR_D: .long 0x00000000 -PACR_D: .long 0x00001400 +PACR_D: .word 0x1400 +.align 2 PBDR_D: .long 0x00000000 -PBCR_D: .long 0x0000555A +PBCR_D: .word 0x555A +.align 2 PCDR_D: .long 0x00000000 -PCCR_D: .long 0x00005555 +PCCR_D: .word 0x5555 +.align 2 PDDR_D: .long 0x00000000 -PDCR_D: .long 0x00000155 -PECR_D: .long 0x00000000 -PFCR_D: .long 0x00000000 -PGCR_D: .long 0x00000000 -PHCR_D: .long 0x00000000 -PICR_D: .long 0x00000800 +PDCR_D: .word 0x0155 +PECR_D: .word 0x0000 +PFCR_D: .word 0x0000 +PGCR_D: .word 0x0000 +PHCR_D: .word 0x0000 +PICR_D: .word 0x0800 PJDR_D: .long 0x00000006 -PJCR_D: .long 0x00005A57 +PJCR_D: .word 0x5A57 +.align 2 PKDR_D: .long 0x00000000 -PKCR_D: .long 0x0000FFF9 -PLCR_D: .long 0x0000C330 -PMCR_D: .long 0x0000FFFF -PNCR_D: .long 0x00000242 -POCR_D: .long 0x00000000 +PKCR_D: .word 0xFFF9 +.align 2 +PLCR_D: .word 0xC330 +PMCR_D: .word 0xFFFF +PNCR_D: .word 0x0242 +POCR_D: .word 0x0000 /* Pin Select */ PSEL0_A: .long 0xFFEF0070 @@ -233,11 +238,12 @@ PSEL1_A: .long 0xFFEF0072 PSEL2_A: .long 0xFFEF0074 PSEL3_A: .long 0xFFEF0076 PSEL4_A: .long 0xFFEF0078 -PSEL0_D: .long 0x0001 -PSEL1_D: .long 0x2400 -PSEL2_D: .long 0x0000 -PSEL3_D: .long 0x2421 -PSEL4_D: .long 0x0000 +PSEL0_D: .word 0x0001 +PSEL1_D: .word 0x2400 +PSEL2_D: .word 0x0000 +PSEL3_D: .word 0x2421 +PSEL4_D: .word 0x0000 +.align 2 MMSEL_A: .long 0xFE600020 BCR_A: .long 0xFF801000 diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 3cdefb3..48d95d6 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -23,6 +23,7 @@ #include <common.h> #include <command.h> #include <netdev.h> +#include <linux/compiler.h> #include <asm/mmu.h> #include <asm/processor.h> #include <asm/cache.h> @@ -120,28 +121,6 @@ int board_early_init_r(void) set_liodns(); setup_portals(); -#ifdef CONFIG_SRIO1 - if (is_serdes_configured(SRIO1)) { - set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_1); - } else { - printf (" SRIO1: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ -#endif - -#ifdef CONFIG_SRIO2 - if (is_serdes_configured(SRIO2)) { - set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, - LAW_TRGT_IF_RIO_2); - } else { - printf (" SRIO2: disabled\n"); - } -#else - setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ -#endif - return 0; } @@ -164,10 +143,34 @@ static const char *serdes_clock_to_string(u32 clock) int misc_init_r(void) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + __maybe_unused ccsr_gur_t *gur; u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw3; + gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_SRIO1 + if (is_serdes_configured(SRIO1)) { + set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, + LAW_TRGT_IF_RIO_1); + } else { + printf (" SRIO1: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ +#endif + +#ifdef CONFIG_SRIO2 + if (is_serdes_configured(SRIO2)) { + set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, + LAW_TRGT_IF_RIO_2); + } else { + printf (" SRIO2: disabled\n"); + } +#else + setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ +#endif + /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 82b2b4f..18adf2f 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -66,11 +66,19 @@ typedef struct { * seem reliable, but errors will appear when memory intensive * program is run. */ /* XXX: Single rank at 800 MHz is OK. */ -const board_specific_parameters_t board_specific_parameters[][20] = { +const board_specific_parameters_t board_specific_parameters[][30] = { { /* memory controller 0 */ /* lo| hi| num| clk| cpo|wrdata|2T */ /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 4, 6, 7, 3, 0}, + {334, 400, 4, 6, 9, 3, 0}, + {401, 549, 4, 6, 11, 3, 0}, + {550, 680, 4, 1, 10, 5, 0}, + {681, 850, 4, 1, 12, 5, 0}, + {851, 1050, 4, 1, 12, 5, 0}, + {1051, 1250, 4, 1, 15, 4, 0}, + {1251, 1350, 4, 1, 15, 4, 0}, { 0, 333, 2, 6, 7, 3, 0}, {334, 400, 2, 6, 9, 3, 0}, {401, 549, 2, 6, 11, 3, 0}, @@ -90,6 +98,14 @@ const board_specific_parameters_t board_specific_parameters[][20] = { /* memory controller 1 */ /* lo| hi| num| clk| cpo|wrdata|2T */ /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 4, 6, 7, 3, 0}, + {334, 400, 4, 6, 9, 3, 0}, + {401, 549, 4, 6, 11, 3, 0}, + {550, 680, 4, 1, 10, 5, 0}, + {681, 850, 4, 1, 12, 5, 0}, + {851, 1050, 4, 1, 12, 5, 0}, + {1051, 1250, 4, 1, 15, 4, 0}, + {1251, 1350, 4, 1, 15, 4, 0}, { 0, 333, 2, 6, 7, 3, 0}, {334, 400, 2, 6, 9, 3, 0}, {401, 549, 2, 6, 11, 3, 0}, diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index 30d640f..9a1b075 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -68,7 +68,7 @@ const board_specific_parameters_t board_specific_parameters[][20] = { {550, 680, 1, 4, 0x1f, 3, 0}, {681, 850, 1, 4, 0x1f, 4, 0} #else - { 0, 850, 2, 4, 0x1f, 4, 0}, + { 0, 850, 2, 6, 0x1f, 4, 0}, { 0, 850, 1, 4, 0x1f, 4, 0} #endif }, @@ -120,7 +120,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, /* Write leveling override */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xa; - popts->wrlvl_start = 0x7; + popts->wrlvl_start = 0x8; /* Rtt and Rtt_WR override */ popts->rtt_override = 1; popts->rtt_override_value = DDR3_RTT_120_OHM; diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds index e6eee9b..aeb0fcc 100644 --- a/board/gth2/u-boot.lds +++ b/board/gth2/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds index 9a6cd1b..3c4fbe3 100644 --- a/board/incaip/u-boot.lds +++ b/board/incaip/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/mpr2/lowlevel_init.S b/board/mpr2/lowlevel_init.S index 5f02bd4..0f7a892 100644 --- a/board/mpr2/lowlevel_init.S +++ b/board/mpr2/lowlevel_init.S @@ -82,10 +82,10 @@ lowlevel_init: /* * PLL Settings */ -FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */ -WTCNT_D: .long 0x5A00 /* start counting at zero */ -WTCSR_D: .long 0xA507 /* divide by 4096 */ - +FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */ +WTCNT_D: .word 0x5A00 /* start counting at zero */ +WTCSR_D: .word 0xA507 /* divide by 4096 */ +.align 2 /* * Spansion S29GL256N11 @ 48 MHz */ diff --git a/board/ms7720se/lowlevel_init.S b/board/ms7720se/lowlevel_init.S index 7593811..3df25b6 100644 --- a/board/ms7720se/lowlevel_init.S +++ b/board/ms7720se/lowlevel_init.S @@ -114,10 +114,10 @@ FRQCR_A: .long 0xA415FF80 /* FRQCR Address */ WTCNT_A: .long 0xA415FF84 WTCSR_A: .long 0xA415FF86 UCLKCR_A: .long 0xA40A0008 -FRQCR_D: .long 0x1103 /* I:B:P=8:4:2 */ -WTCNT_D: .long 0x5A00 -WTCSR_D: .long 0xA506 -UCLKCR_D: .long 0xA5C0 +FRQCR_D: .word 0x1103 /* I:B:P=8:4:2 */ +WTCNT_D: .word 0x5A00 +WTCSR_D: .word 0xA506 +UCLKCR_D: .word 0xA5C0 #define BSC_BASE 0xA4FD0000 CMNCR_A: .long BSC_BASE @@ -164,7 +164,8 @@ SDCR_D1: .long 0x00000011 RTCSR_D: .long 0xA55A0010 RTCNT_D: .long 0xA55A001F RTCOR_D: .long 0xA55A001F -SDMR3_D: .long 0x0000 +SDMR3_D: .word 0x0000 +.align 2 SDCR_D2: .long 0x00000811 #define PFC_BASE 0xA4050100 @@ -178,15 +179,16 @@ PTCR_A: .long PFC_BASE + 0x1E PVCR_A: .long PFC_BASE + 0x22 PSELA_A: .long PFC_BASE + 0x24 -PCCR_D: .long 0x0000 -PDCR_D: .long 0x0000 -PECR_D: .long 0x0000 -PGCR_D: .long 0x0000 -PHCR_D: .long 0x0000 -PPCR_D: .long 0x00AA -PTCR_D: .long 0x0280 -PVCR_D: .long 0x0000 -PSELA_D: .long 0x0000 +PCCR_D: .word 0x0000 +PDCR_D: .word 0x0000 +PECR_D: .word 0x0000 +PGCR_D: .word 0x0000 +PHCR_D: .word 0x0000 +PPCR_D: .word 0x00AA +PTCR_D: .word 0x0280 +PVCR_D: .word 0x0000 +PSELA_D: .word 0x0000 +.align 2 CCR_A: .long 0xFFFFFFEC !CCR_D: .long 0x0000000D diff --git a/board/ms7750se/lowlevel_init.S b/board/ms7750se/lowlevel_init.S index 5e09a39..3041e64 100644 --- a/board/ms7750se/lowlevel_init.S +++ b/board/ms7750se/lowlevel_init.S @@ -120,13 +120,14 @@ CCR_D_DISABLE: .long 0x0808 FRQCR_A: .long FRQCR FRQCR_D: #ifdef CONFIG_CPU_TYPE_R - .long 0x00000e1a /* 12:3:3 */ + .word 0x0e1a /* 12:3:3 */ #else /* CONFIG_CPU_TYPE_R */ #ifdef CONFIG_GOOD_SESH4 - .long 0x00000e13 /* 6:2:1 */ + .word 0x00e13 /* 6:2:1 */ #else - .long 0x00000e23 /* 6:1:1 */ + .word 0x00e23 /* 6:1:1 */ #endif +.align 2 #endif /* CONFIG_CPU_TYPE_R */ BCR1_A: .long BCR1 @@ -140,15 +141,19 @@ WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */ WCR3_A: .long WCR3 WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */ RTCSR_A: .long RTCSR -RTCSR_D: .long 0xA518 /* RTCSR Write Code A5h Data 18h */ +RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */ +.align 2 RTCNT_A: .long RTCNT -RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ +RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ +.align 2 RTCOR_A: .long RTCOR -RTCOR_D: .long RTCOR_D_VALUE /* Set refresh time (about 15us) */ +RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */ +.align 2 SDMR3_A: .long SDMR3_ADDRESS SDMR3_D: .long 0x00 MCR_A: .long MCR MCR_D1: .long MCR_D1_VALUE MCR_D2: .long MCR_D2_VALUE RFCR_A: .long RFCR -RFCR_D: .long 0xA400 /* RFCR Write Code A4h Data 00h */ +RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */ +.align 2 diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds index 9a6cd1b..358cc54 100644 --- a/board/pb1x00/u-boot.lds +++ b/board/pb1x00/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds index 1881e65..542601a 100644 --- a/board/purple/u-boot.lds +++ b/board/purple/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds index ad058ca..bd16786 100644 --- a/board/qemu-mips/u-boot.lds +++ b/board/qemu-mips/u-boot.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) ENTRY(_start) SECTIONS diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S index 0daf25a..04cfef1 100644 --- a/board/renesas/ap325rxa/lowlevel_init.S +++ b/board/renesas/ap325rxa/lowlevel_init.S @@ -119,15 +119,16 @@ lowlevel_init: DRVCRA_A: .long DRVCRA DRVCRB_A: .long DRVCRB -DRVCRA_D: .long 0x4555 -DRVCRB_D: .long 0x0005 +DRVCRA_D: .word 0x4555 +DRVCRB_D: .word 0x0005 RWTCSR_A: .long RWTCSR RWTCNT_A: .long RWTCNT FRQCR_A: .long FRQCR -RWTCSR_D1: .long 0xa507 -RWTCSR_D2: .long 0xa504 -RWTCNT_D: .long 0x5a00 +RWTCSR_D1: .word 0xa507 +RWTCSR_D2: .word 0xa504 +RWTCNT_D: .word 0x5a00 +.align 2 FRQCR_D: .long 0x0b04474a SBSC_SDCR_A: .long SBSC_SDCR diff --git a/board/renesas/r2dplus/lowlevel_init.S b/board/renesas/r2dplus/lowlevel_init.S index 76d3cfc..f3392f0 100644 --- a/board/renesas/r2dplus/lowlevel_init.S +++ b/board/renesas/r2dplus/lowlevel_init.S @@ -94,11 +94,14 @@ WCR3_D: .long 0x07777707 LED_A: .long 0x04000036 /* LED Address */ LED_D: .long 0xFF /* LED Data */ RTCNT_A: .long RTCNT /* RTCNT Address */ -RTCNT_D: .long 0xA500 /* RTCNT Write Code A5h Data 00h */ +RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */ +.align 2 RTCOR_A: .long RTCOR /* RTCOR Address */ -RTCOR_D: .long 0xA534 /* RTCOR Write Code */ +RTCOR_D: .word 0xA534 /* RTCOR Write Code */ +.align 2 RTCSR_A: .long RTCSR /* RTCSR Address */ -RTCSR_D: .long 0xA510 /* RTCSR Write Code */ +RTCSR_D: .word 0xA510 /* RTCSR Write Code */ +.align 2 SDMR3_A: .long 0xFF9400CC /* SDMR3 Address */ SDMR3_D0: .long 0x55 SDMR3_D1: .long 0x00 diff --git a/board/renesas/rsk7203/lowlevel_init.S b/board/renesas/rsk7203/lowlevel_init.S index 7b9ecd8..30ef5ab 100644 --- a/board/renesas/rsk7203/lowlevel_init.S +++ b/board/renesas/rsk7203/lowlevel_init.S @@ -73,7 +73,7 @@ init_bsc_cs0: write32 CMNCR_A, CMNCR_D - write32 SC0BCR_A, SC0BCR_D + write32 CS0BCR_A, CS0BCR_D write32 CS0WCR_A, CS0WCR_D @@ -122,63 +122,82 @@ repeat0: CCR1_A: .long CCR1 CCR1_D: .long 0x0000090B PCCRL4_A: .long 0xFFFE3910 -PCCRL4_D0: .long 0x00000000 +PCCRL4_D0: .word 0x0000 +.align 2 PECRL4_A: .long 0xFFFE3A10 -PECRL4_D0: .long 0x00000000 +PECRL4_D0: .word 0x0000 +.align 2 PECRL3_A: .long 0xFFFE3A12 -PECRL3_D: .long 0x00000000 +PECRL3_D: .word 0x0000 +.align 2 PEIORL_A: .long 0xFFFE3A06 -PEIORL_D0: .long 0x00001C00 -PEIORL_D1: .long 0x00001C02 +PEIORL_D0: .word 0x1C00 +PEIORL_D1: .word 0x1C02 PCIORL_A: .long 0xFFFE3906 -PCIORL_D: .long 0x00004000 +PCIORL_D: .word 0x4000 +.align 2 PFCRH2_A: .long 0xFFFE3A8C -PFCRH2_D: .long 0x00000000 +PFCRH2_D: .word 0x0000 +.align 2 PFCRH3_A: .long 0xFFFE3A8A -PFCRH3_D: .long 0x00000000 +PFCRH3_D: .word 0x0000 +.align 2 PFCRH1_A: .long 0xFFFE3A8E -PFCRH1_D: .long 0x00000000 +PFCRH1_D: .word 0x0000 +.align 2 PFIORH_A: .long 0xFFFE3A84 -PFIORH_D: .long 0x00000729 +PFIORH_D: .word 0x0729 +.align 2 PECRL1_A: .long 0xFFFE3A16 -PECRL1_D0: .long 0x00000033 +PECRL1_D0: .word 0x0033 +.align 2 WTCSR_A: .long 0xFFFE0000 -WTCSR_D0: .long 0x0000A518 -WTCSR_D1: .long 0x0000A51D +WTCSR_D0: .word 0xA518 +WTCSR_D1: .word 0xA51D WTCNT_A: .long 0xFFFE0002 -WTCNT_D: .long 0x00005A84 +WTCNT_D: .word 0x5A84 +.align 2 FRQCR_A: .long 0xFFFE0010 -FRQCR_D: .long 0x00000104 +FRQCR_D: .word 0x0104 +.align 2 -PCCRL4_D1: .long 0x00000010 -PECRL1_D1: .long 0x00000133 +PCCRL4_D1: .word 0x0010 +PECRL1_D1: .word 0x0133 CMNCR_A: .long 0xFFFC0000 CMNCR_D: .long 0x00001810 -SC0BCR_A: .long 0xFFFC0004 -SC0BCR_D: .long 0x10000400 +CS0BCR_A: .long 0xFFFC0004 +CS0BCR_D: .long 0x10000400 CS0WCR_A: .long 0xFFFC0028 CS0WCR_D: .long 0x00000B41 -PECRL4_D1: .long 0x00000100 +PECRL4_D1: .word 0x0100 +.align 2 CS1WCR_A: .long 0xFFFC002C CS1WCR_D: .long 0x00000B01 -PCCRL4_D2: .long 0x00000011 +PCCRL4_D2: .word 0x0011 +.align 2 PCCRL3_A: .long 0xFFFE3912 -PCCRL3_D: .long 0x00000011 +PCCRL3_D: .word 0x0011 +.align 2 PCCRL2_A: .long 0xFFFE3914 -PCCRL2_D: .long 0x00001111 +PCCRL2_D: .word 0x1111 +.align 2 PCCRL1_A: .long 0xFFFE3916 -PCCRL1_D: .long 0x00001010 +PCCRL1_D: .word 0x1010 PDCRL4_A: .long 0xFFFE3990 -PDCRL4_D: .long 0x00000011 +PDCRL4_D: .word 0x0011 +.align 2 PDCRL3_A: .long 0xFFFE3992 -PDCRL3_D: .long 0x00000011 +PDCRL3_D: .word 0x00011 +.align 2 PDCRL2_A: .long 0xFFFE3994 -PDCRL2_D: .long 0x00001111 +PDCRL2_D: .word 0x1111 +.align 2 PDCRL1_A: .long 0xFFFE3996 -PDCRL1_D: .long 0x00001000 +PDCRL1_D: .word 0x1000 +.align 2 CS3BCR_A: .long 0xFFFC0010 CS3BCR_D: .long 0x00004400 CS3WCR_A: .long 0xFFFC0034 @@ -190,13 +209,5 @@ RTCOR_D: .long 0xA55A0041 RTCSR_A: .long 0xFFFC0050 RTCSR_D: .long 0xa55a0010 -STBCR3_A: .long 0xFFFE0408 -STBCR3_D: .long 0x00000000 -STBCR4_A: .long 0xFFFE040C -STBCR4_D: .long 0x00000008 -STBCR5_A: .long 0xFFFE0410 -STBCR5_D: .long 0x00000000 -STBCR6_A: .long 0xFFFE0414 -STBCR6_D: .long 0x00000002 SDRAM_MODE: .long 0xFFFC5040 REPEAT_D: .long 0x00009C40 diff --git a/board/renesas/sh7763rdp/lowlevel_init.S b/board/renesas/sh7763rdp/lowlevel_init.S index 3747bf6..5b18200 100644 --- a/board/renesas/sh7763rdp/lowlevel_init.S +++ b/board/renesas/sh7763rdp/lowlevel_init.S @@ -266,8 +266,8 @@ SDR4_D: .long 0x00000300 SDMR00308_D: .long 0x00000000 SDMR00B08_D: .long 0x00000000 SDMR02000_D: .long 0x00000000 -PSEL0_D: .long 0x00000001 -PSEL1_D: .long 0x00000244 +PSEL0_D: .word 0x00000001 +PSEL1_D: .word 0x00000244 SR_MASK_D: .long 0xEFFFFF0F WDTST_D: .long 0x5A000FFF WDTCSR_D: .long 0xA5000000 diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S index 40d9b08..86f6783 100644 --- a/board/renesas/sh7785lcr/lowlevel_init.S +++ b/board/renesas/sh7785lcr/lowlevel_init.S @@ -68,22 +68,22 @@ lowlevel_init: wait_timer WAIT_200US /*------- GPIO -------*/ - write16 PACR_A, PACR_D - write16 PBCR_A, PBCR_D - write16 PCCR_A, PCCR_D - write16 PDCR_A, PDCR_D - write16 PECR_A, PECR_D - write16 PFCR_A, PFCR_D - write16 PGCR_A, PGCR_D + write16 PACR_A, PXCR_D + write16 PBCR_A, PXCR_D + write16 PCCR_A, PXCR_D + write16 PDCR_A, PXCR_D + write16 PECR_A, PXCR_D + write16 PFCR_A, PXCR_D + write16 PGCR_A, PXCR_D write16 PHCR_A, PHCR_D write16 PJCR_A, PJCR_D write16 PKCR_A, PKCR_D - write16 PLCR_A, PLCR_D + write16 PLCR_A, PXCR_D write16 PMCR_A, PMCR_D write16 PNCR_A, PNCR_D - write16 PPCR_A, PPCR_D - write16 PQCR_A, PQCR_D - write16 PRCR_A, PRCR_D + write16 PPCR_A, PXCR_D + write16 PQCR_A, PXCR_D + write16 PRCR_A, PXCR_D write8 PEPUPR_A, PEPUPR_D write8 PHPUPR_A, PHPUPR_D @@ -179,22 +179,14 @@ lbsc_end: .align 4 /*------- GPIO -------*/ -PACR_D: .long 0x0000 -PBCR_D: .long 0x0000 -PCCR_D: .long 0x0000 -PDCR_D: .long 0x0000 -PECR_D: .long 0x0000 -PFCR_D: .long 0x0000 -PGCR_D: .long 0x0000 -PHCR_D: .long 0x00c0 -PJCR_D: .long 0xc3fc -PKCR_D: .long 0x03ff -PLCR_D: .long 0x0000 -PMCR_D: .long 0xffff -PNCR_D: .long 0xf0c3 -PPCR_D: .long 0x0000 -PQCR_D: .long 0x0000 -PRCR_D: .long 0x0000 +/* P{A,B C,D,E,F,G,L,P,Q,R}CR_D */ +PXCR_D: .word 0x0000 + +PHCR_D: .word 0x00c0 +PJCR_D: .word 0xc3fc +PKCR_D: .word 0x03ff +PMCR_D: .word 0xffff +PNCR_D: .word 0xf0c3 PEPUPR_D: .long 0xff PHPUPR_D: .long 0x00 @@ -203,10 +195,10 @@ PKPUPR_D: .long 0x00 PLPUPR_D: .long 0x00 PMPUPR_D: .long 0xfc PNPUPR_D: .long 0x00 -PPUPR1_D: .long 0xffbf -PPUPR2_D: .long 0xff00 -P1MSELR_D: .long 0x3780 -P2MSELR_D: .long 0x0000 +PPUPR1_D: .word 0xffbf +PPUPR2_D: .word 0xff00 +P1MSELR_D: .word 0x3780 +P2MSELR_D: .word 0x0000 #define GPIO_BASE 0xffe70000 PACR_A: .long GPIO_BASE + 0x00 diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index 060d5d1..4336729 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -67,7 +67,7 @@ int board_mmc_init(bd_t *bis) int i; /* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */ - gpio_direction_output(&s5pc110_gpio->gpio_j2, 7, 1); + gpio_direction_output(&s5pc110_gpio->j2, 7, 1); /* * MMC0 GPIO @@ -80,11 +80,11 @@ int board_mmc_init(bd_t *bis) if (i == 2) continue; /* GPG0[0:6] special function 2 */ - gpio_cfg_pin(&s5pc110_gpio->gpio_g0, i, 0x2); + gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2); /* GPG0[0:6] pull disable */ - gpio_set_pull(&s5pc110_gpio->gpio_g0, i, GPIO_PULL_NONE); + gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE); /* GPG0[0:6] drv 4x */ - gpio_set_drv(&s5pc110_gpio->gpio_g0, i, GPIO_DRV_4X); + gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X); } return s5p_mmc_init(0); diff --git a/board/samsung/goni/lowlevel_init.S b/board/samsung/goni/lowlevel_init.S index 4b72992..62737ab 100644 --- a/board/samsung/goni/lowlevel_init.S +++ b/board/samsung/goni/lowlevel_init.S @@ -51,7 +51,7 @@ lowlevel_init: ldr r7, =S5PC100_GPIO_BASE ldr r8, =S5PC100_GPIO_BASE /* Read CPU ID */ - ldr r2, =S5PC1XX_PRO_ID + ldr r2, =S5PC110_PRO_ID ldr r0, [r2] mov r1, #0x00010000 and r0, r0, r1 @@ -377,7 +377,7 @@ lockloop: * void system_clock_init(void) */ system_clock_init: - ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000 /* Check S5PC100 */ cmp r7, r8 @@ -437,7 +437,7 @@ system_clock_init: ldr r1, =0x3ff03ff str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE - ldr r0, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000 /* Set Clock divider */ ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5 diff --git a/board/samsung/smdkc100/lowlevel_init.S b/board/samsung/smdkc100/lowlevel_init.S index 32572c5..30d0d06 100644 --- a/board/samsung/smdkc100/lowlevel_init.S +++ b/board/samsung/smdkc100/lowlevel_init.S @@ -131,7 +131,7 @@ wakeup_reset: * void system_clock_init(void) */ system_clock_init: - ldr r8, =S5PC1XX_CLOCK_BASE @ 0xE0100000 + ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000 /* Set Clock divider */ ldr r1, =0x00011110 diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c index c25869e..501855e 100644 --- a/board/samsung/smdkc100/onenand.c +++ b/board/samsung/smdkc100/onenand.c @@ -35,7 +35,8 @@ void onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; - struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE; + struct s5pc100_clock *clk = + (struct s5pc100_clock *)samsung_get_base_clock(); struct samsung_onenand *onenand; int value; diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index fb466c6..31e8d9e 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -38,10 +38,10 @@ static void smc9115_pre_init(void) u32 smc_bw_conf, smc_bc_conf; struct s5pc100_gpio *const gpio = - (struct s5pc100_gpio *)S5PC100_GPIO_BASE; + (struct s5pc100_gpio *)samsung_get_base_gpio(); /* gpio configuration GPK0CON */ - gpio_cfg_pin(&gpio->gpio_k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile new file mode 100644 index 0000000..87d2234 --- /dev/null +++ b/board/syteco/jadecpu/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop <stelian.pop@leadtechdesign.com> +# Lead Tech Design <www.leadtechdesign.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += jadecpu.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/syteco/jadecpu/config.mk b/board/syteco/jadecpu/config.mk new file mode 100644 index 0000000..c661f0b --- /dev/null +++ b/board/syteco/jadecpu/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x46000000 diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c new file mode 100644 index 0000000..04d2f9d --- /dev/null +++ b/board/syteco/jadecpu/jadecpu.c @@ -0,0 +1,170 @@ +/* + * (c) 2010 Graf-Syteco, Matthias Weisser + * <weisserm@arcor.de> + * + * (C) Copyright 2007, mycable GmbH + * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/mb86r0x.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *) + MB86R0x_CCNT_BASE; + + /* We select mode 0 for group 2 and mode 1 for group 4 */ + writel(0x00000010, &ccnt->cmux_md); + + gd->flags = 0; + gd->bd->bi_arch_number = MACH_TYPE_JADECPU; + gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000; + + icache_enable(); + + return 0; +} + +static void setup_display_power(uint32_t pwr_bit, char *pwm_opts, + unsigned long pwm_base) +{ + struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) + MB86R0x_GPIO_BASE; + struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base; + const char *e; + + writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2); + + e = getenv(pwm_opts); + if (e != NULL) { + const char *s; + uint32_t freq, init; + + freq = 0; + init = 0; + + s = strchr(e, 'f'); + if (s != NULL) + freq = simple_strtol(s + 2, NULL, 0); + + s = strchr(e, 'i'); + if (s != NULL) + init = simple_strtol(s + 2, NULL, 0); + + if (freq > 0) { + writel(CONFIG_MB86R0x_IOCLK / 1000 / freq, + &pwm->bcr); + writel(1002, &pwm->tpr); + writel(1, &pwm->pr); + writel(init * 10 + 1, &pwm->dr); + writel(1, &pwm->cr); + writel(1, &pwm->sr); + } + } +} + +int board_late_init(void) +{ + struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) + MB86R0x_GPIO_BASE; + uint32_t in_word; + +#ifdef CONFIG_VIDEO_MB86R0xGDC + /* Check if we have valid display settings and turn on power if so */ + /* Display 0 */ + if (getenv("gs_dsp_0_param") || getenv("videomode")) + setup_display_power((1 << 3), "gs_dsp_0_pwm", + MB86R0x_PWM0_BASE); + + /* The corresponding GPIO is always an output */ + writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2); + + /* Display 1 */ + if (getenv("gs_dsp_1_param") || getenv("videomode1")) + setup_display_power((1 << 4), "gs_dsp_1_pwm", + MB86R0x_PWM1_BASE); + + /* The corresponding GPIO is always an output */ + writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2); +#endif /* CONFIG_VIDEO_MB86R0xGDC */ + + /* 5V enable */ + writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1); + writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1); + + /* We have special boot options if told by GPIOs */ + in_word = readl(&gpio->gpdr1); + + if ((in_word & 0xC0) == 0xC0) { + setenv("stdin", "serial"); + setenv("stdout", "serial"); + setenv("stderr", "serial"); + setenv("preboot", "run gs_slow_boot"); + } else if ((in_word & 0xC0) != 0) { + setenv("stdout", "vga"); + setenv("gs_bootcmd", "mw.l 0x40000000 0 1024; usb start;" + "fatls usb 0; fatload usb 0 0x40000000 mcq5resq.bin;" + "bootelf 0x40000000; bootelf 0x10080000"); + setenv("preboot", "run gs_slow_boot"); + } else { + setenv("stdin", "serial"); + setenv("stdout", "serial"); + setenv("stderr", "serial"); + if (getenv("gs_devel")) { + setenv("preboot", "run gs_slow_boot"); + } else { + setenv("gs_bootcmd", "bootelf 0x10080000"); + setenv("preboot", "run gs_fast_boot"); + } + } + + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +/* + * DRAM configuration + */ +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC911X + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); +#endif + return rc; +} diff --git a/board/syteco/jadecpu/lowlevel_init.S b/board/syteco/jadecpu/lowlevel_init.S new file mode 100644 index 0000000..5ad4dce --- /dev/null +++ b/board/syteco/jadecpu/lowlevel_init.S @@ -0,0 +1,265 @@ +/* + * Board specific setup info + * + * (C) Copyright 2007, mycable GmbH + * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de> + * + * (C) Copyright 2003, ARM Ltd. + * Philippe Robin, <philippe.robin@arm.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/macro.h> +#include <asm/arch/mb86r0x.h> +#include <asm/arch/asm-offsets.h> + +/* Set up the platform, once the cpu has been initialized */ +.globl lowlevel_init +lowlevel_init: +/* + * Initialize Clock Reset Generator (CRG) + */ + + ldr r0, =MB86R0x_CRG_BASE + + /* Not change the initial value that is set by external pin.*/ +WAIT_PLL: + ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */ + tst r2, #MB86R0x_CRG_CRPR_PLLRDY + beq WAIT_PLL + + /* Set clock gate control */ + ldr r1, =CONFIG_SYS_CRG_CRHA_INIT + str r1, [r0, #CRG_CRHA] + ldr r1, =CONFIG_SYS_CRG_CRPA_INIT + str r1, [r0, #CRG_CRPA] + ldr r1, =CONFIG_SYS_CRG_CRPB_INIT + str r1, [r0, #CRG_CRPB] + ldr r1, =CONFIG_SYS_CRG_CRHB_INIT + str r1, [r0, #CRG_CRHB] + ldr r1, =CONFIG_SYS_CRG_CRAM_INIT + str r1, [r0, #CRG_CRAM] + +/* + * Initialize External Bus Interface + */ + ldr r0, =MB86R0x_MEMC_BASE + + ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT + str r1, [r0, #MEMC_MCFMODE0] + ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT + str r1, [r0, #MEMC_MCFMODE2] + ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT + str r1, [r0, #MEMC_MCFMODE4] + + ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT + str r1, [r0, #MEMC_MCFTIM0] + ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT + str r1, [r0, #MEMC_MCFTIM2] + ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT + str r1, [r0, #MEMC_MCFTIM4] + + ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT + str r1, [r0, #MEMC_MCFAREA0] + ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT + str r1, [r0, #MEMC_MCFAREA2] + ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT + str r1, [r0, #MEMC_MCFAREA4] + +/* + * Initialize DDR2 Controller + */ + + /* Wait for PLL LOCK up time or more */ + wait_timer 20 + + /* + * (2) Initialize DDRIF + */ + ldr r0, =MB86R0x_DDR2_BASE + ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT + strh r1, [r0, #DDR2_DRIMS] + + /* + * (3) Wait for 20MCKPs(120nsec) or more + */ + wait_timer 20 + + /* + * (4) IRESET/IUSRRST release + */ + ldr r0, =MB86R0x_CCNT_BASE + ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1 + str r1, [r0, #CCNT_CDCRC] + + /* + * (5) Wait for 20MCKPs(120nsec) or more + */ + wait_timer 20 + + /* + * (6) IDLLRST release + */ + ldr r0, =MB86R0x_CCNT_BASE + ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2 + str r1, [r0, #CCNT_CDCRC] + + /* + * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec) + */ + wait_timer 33536 + + /* + * (9) MCKE ON + */ + ldr r0, =MB86R0x_DDR2_BASE + ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT + strh r1, [r0, #DDR2_DRCA] + ldr r1, =MB86R0x_DDR2_DRCI_INIT + strh r1, [r0, #DDR2_DRIC] + + /* + * (10) Initialize SDRAM + */ + + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 67 /* 400ns wait */ + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 200 + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 18 /* 105ns wait */ + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + wait_timer 200 /* MRS to OCD: 200clock */ + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10 + strh r1, [r0, #DDR2_DRIC1] + ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10 + strh r1, [r0, #DDR2_DRIC2] + ldr r1, =MB86R0x_DDR2_DRCI_CMD + strh r1, [r0, #DDR2_DRIC] + + ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT + strh r1, [r0, #DDR2_DRCM] + + ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT + strh r1, [r0, #DDR2_DRCST1] + + ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT + strh r1, [r0, #DDR2_DRCST2] + + ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT + strh r1, [r0, #DDR2_DRCR] + + ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT + strh r1, [r0, #DDR2_DRCF] + + ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT + strh r1, [r0, #DDR2_DRASR] + + /* + * (11) ODT setting + */ + ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT + strh r1, [r0, #DDR2_DROBS] + ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT + strh r1, [r0, #DDR2_DROABA] + ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT + strh r1, [r0, #DDR2_DRIBSODT1] + + /* + * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode + */ + ldr r1, =CONFIG_SYS_DDR2_DROS_INIT + strh r1, [r0, #DDR2_DROS] + ldr r1, =MB86R0x_DDR2_DRCI_NORMAL + strh r1, [r0, #DDR2_DRIC] + + mov pc, lr diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index 8ba1b19..2272ff0 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -101,7 +101,7 @@ static long fixed_sdram(void) phys_size_t initdram(int board_type) { volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; - volatile fsl_lbus_t *lbc = &im->lbus; + volatile fsl_lbc_t *lbc = &im->im_lbc; u32 msize; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) @@ -43,6 +43,7 @@ meesc arm arm926ejs - esd at91 otc570 arm arm926ejs - esd at91 pm9261 arm arm926ejs - ronetix at91 pm9263 arm arm926ejs - ronetix at91 +jadecpu arm arm926ejs jadecpu syteco mb86r0x suen3 arm arm926ejs km_arm keymile kirkwood rd6281a arm arm926ejs - Marvell kirkwood mx51evk arm armv7 mx51evk freescale mx51 diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index fbe73f1..d43867f 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -348,6 +348,25 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } +#elif defined(CONFIG_SH) + +int do_bdinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + bd_t *bd = gd->bd; + print_num ("mem start ", (ulong)bd->bi_memstart); + print_lnum ("mem size ", (u64)bd->bi_memsize); + print_num ("flash start ", (ulong)bd->bi_flashstart); + print_num ("flash size ", (ulong)bd->bi_flashsize); + print_num ("flash offset ", (ulong)bd->bi_flashoffset); + +#if defined(CONFIG_CMD_NET) + print_eth(0); + printf ("ip_addr = %pI4\n", &bd->bi_ip_addr); +#endif + printf ("baudrate = %ld bps\n", (ulong)bd->bi_baudrate); + return 0; +} + #else #error "a case for this architecture does not exist!" #endif diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 371e022..1283c82 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -152,7 +152,7 @@ int i2c_set_bus_speed(unsigned int) /* * get_alen: small parser helper function to get address length - * returns the address length,or 0 on error + * returns the address length */ static uint get_alen(char *arg) { @@ -163,9 +163,6 @@ static uint get_alen(char *arg) for (j = 0; j < 8; j++) { if (arg[j] == '.') { alen = arg[j+1] - '0'; - if (alen > 3) { - return 0; - } break; } else if (arg[j] == '\0') break; @@ -198,7 +195,7 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv */ devaddr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) + if (alen > 3) return cmd_usage(cmdtp); /* @@ -255,7 +252,7 @@ static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] */ addr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) + if (alen > 3) return cmd_usage(cmdtp); /* @@ -337,7 +334,7 @@ static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] */ addr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) + if (alen > 3) return cmd_usage(cmdtp); /* @@ -399,7 +396,7 @@ static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] */ addr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) + if (alen > 3) return cmd_usage(cmdtp); /* @@ -477,7 +474,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char * const arg */ addr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) + if (alen > 3) return cmd_usage(cmdtp); } @@ -621,7 +618,7 @@ static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] */ addr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) + if (alen > 3) return cmd_usage(cmdtp); /* diff --git a/common/fdt_support.c b/common/fdt_support.c index 33336be..aef4fe2 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -874,35 +874,6 @@ static inline u64 of_read_number(const __be32 *cell, int size) return r; } -static int of_n_cells(const void *blob, int nodeoffset, const char *name) -{ - int np; - const int *ip; - - do { - np = fdt_parent_offset(blob, nodeoffset); - - if (np >= 0) - nodeoffset = np; - ip = (int *)fdt_getprop(blob, nodeoffset, name, NULL); - if (ip) - return be32_to_cpup(ip); - } while (np >= 0); - - /* No #<NAME>-cells property for the root node */ - return 1; -} - -int of_n_addr_cells(const void *blob, int nodeoffset) -{ - return of_n_cells(blob, nodeoffset, "#address-cells"); -} - -int of_n_size_cells(const void *blob, int nodeoffset) -{ - return of_n_cells(blob, nodeoffset, "#size-cells"); -} - #define PRu64 "%llx" /* Max address size we deal with */ @@ -928,7 +899,7 @@ static void of_dump_addr(const char *s, const u32 *addr, int na) { } struct of_bus { const char *name; const char *addresses; - void (*count_cells)(void *blob, int offset, + void (*count_cells)(void *blob, int parentoffset, int *addrc, int *sizec); u64 (*map)(u32 *addr, const u32 *range, int na, int ns, int pna); @@ -936,13 +907,26 @@ struct of_bus { }; /* Default translator (generic bus) */ -static void of_bus_default_count_cells(void *blob, int offset, +static void of_bus_default_count_cells(void *blob, int parentoffset, int *addrc, int *sizec) { - if (addrc) - *addrc = of_n_addr_cells(blob, offset); - if (sizec) - *sizec = of_n_size_cells(blob, offset); + const u32 *prop; + + if (addrc) { + prop = fdt_getprop(blob, parentoffset, "#address-cells", NULL); + if (prop) + *addrc = be32_to_cpup(prop); + else + *addrc = 2; + } + + if (sizec) { + prop = fdt_getprop(blob, parentoffset, "#size-cells", NULL); + if (prop) + *sizec = be32_to_cpup(prop); + else + *sizec = 1; + } } static u64 of_bus_default_map(u32 *addr, const u32 *range, @@ -1068,7 +1052,7 @@ u64 __of_translate_address(void *blob, int node_offset, const u32 *in_addr, bus = &of_busses[0]; /* Cound address cells & copy address locally */ - bus->count_cells(blob, node_offset, &na, &ns); + bus->count_cells(blob, parent, &na, &ns); if (!OF_CHECK_COUNTS(na, ns)) { printf("%s: Bad cell count for %s\n", __FUNCTION__, fdt_get_name(blob, node_offset, NULL)); @@ -1095,7 +1079,7 @@ u64 __of_translate_address(void *blob, int node_offset, const u32 *in_addr, /* Get new parent bus and counts */ pbus = &of_busses[0]; - pbus->count_cells(blob, node_offset, &pna, &pns); + pbus->count_cells(blob, parent, &pna, &pns); if (!OF_CHECK_COUNTS(pna, pns)) { printf("%s: Bad cell count for %s\n", __FUNCTION__, fdt_get_name(blob, node_offset, NULL)); diff --git a/common/serial.c b/common/serial.c index fceabfa..1345c08 100644 --- a/common/serial.c +++ b/common/serial.c @@ -40,9 +40,9 @@ struct serial_device *__default_serial_console (void) return &serial_scc_device; #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \ - || defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) \ - || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \ - || defined(CONFIG_SYS_SC520) + || defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) \ + || defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) \ + || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) #if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL) #if (CONFIG_CONS_INDEX==1) return &eserial1_device; @@ -78,7 +78,7 @@ struct serial_device *__default_serial_console (void) #else #error "CONFIG_SERIAL? missing." #endif -#elif defined(CONFIG_S5PC1XX) +#elif defined(CONFIG_S5P) #if defined(CONFIG_SERIAL0) return &s5p_serial0_device; #elif defined(CONFIG_SERIAL1) @@ -162,7 +162,7 @@ void serial_initialize (void) serial_register(&s3c24xx_serial1_device); serial_register(&s3c24xx_serial2_device); #endif -#if defined(CONFIG_S5PC1XX) +#if defined(CONFIG_S5P) serial_register(&s5p_serial0_device); serial_register(&s5p_serial1_device); serial_register(&s5p_serial2_device); diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c index df33e7a..09c18c1 100644 --- a/drivers/dma/fsl_dma.c +++ b/drivers/dma/fsl_dma.c @@ -114,8 +114,12 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) { while (count) { xfer_size = MIN(FSL_DMA_MAX_SIZE, count); - out_dma32(&dma->dar, (uint) dest); - out_dma32(&dma->sar, (uint) src); + out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF)); + out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF)); + out_dma32(&dma->satr, + in_dma32(&dma->satr) | (u32)((u64)src >> 32)); + out_dma32(&dma->datr, + in_dma32(&dma->datr) | (u32)((u64)dest >> 32)); out_dma32(&dma->bcr, xfer_size); dma_sync(); diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 528ca2e..07d395d 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -29,7 +29,7 @@ COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o -COBJS-$(CONFIG_S5PC1XX) += s5p_gpio.o +COBJS-$(CONFIG_S5P) += s5p_gpio.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index d2c2515..8921ff9 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -28,7 +28,7 @@ LIB := $(obj)libi2c.a COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o -COBJS-$(CONFIG_I2C_KIRKWOOD) += kirkwood_i2c.o +COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o diff --git a/drivers/i2c/kirkwood_i2c.c b/drivers/i2c/kirkwood_i2c.c deleted file mode 100644 index a4409be..0000000 --- a/drivers/i2c/kirkwood_i2c.c +++ /dev/null @@ -1,496 +0,0 @@ -/* - * Driver for the i2c controller on the Marvell line of host bridges - * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, Orion SoC family), - * and Kirkwood family. - * - * Based on: - * Author: Mark A. Greer <mgreer@mvista.com> - * 2005 (c) MontaVista, Software, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * ported from Linux to u-boot - * (C) Copyright 2009 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ -#include <common.h> -#include <i2c.h> -#include <asm/arch/kirkwood.h> -#include <asm/errno.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = 0; -#if defined(CONFIG_I2C_MUX) -static unsigned int i2c_bus_num_mux __attribute__ ((section ("data"))) = 0; -#endif - -/* Register defines */ -#define KW_I2C_REG_SLAVE_ADDR 0x00 -#define KW_I2C_REG_DATA 0x04 -#define KW_I2C_REG_CONTROL 0x08 -#define KW_I2C_REG_STATUS 0x0c -#define KW_I2C_REG_BAUD 0x0c -#define KW_I2C_REG_EXT_SLAVE_ADDR 0x10 -#define KW_I2C_REG_SOFT_RESET 0x1c - -#define KW_I2C_REG_CONTROL_ACK 0x00000004 -#define KW_I2C_REG_CONTROL_IFLG 0x00000008 -#define KW_I2C_REG_CONTROL_STOP 0x00000010 -#define KW_I2C_REG_CONTROL_START 0x00000020 -#define KW_I2C_REG_CONTROL_TWSIEN 0x00000040 -#define KW_I2C_REG_CONTROL_INTEN 0x00000080 - -/* Ctlr status values */ -#define KW_I2C_STATUS_BUS_ERR 0x00 -#define KW_I2C_STATUS_MAST_START 0x08 -#define KW_I2C_STATUS_MAST_REPEAT_START 0x10 -#define KW_I2C_STATUS_MAST_WR_ADDR_ACK 0x18 -#define KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20 -#define KW_I2C_STATUS_MAST_WR_ACK 0x28 -#define KW_I2C_STATUS_MAST_WR_NO_ACK 0x30 -#define KW_I2C_STATUS_MAST_LOST_ARB 0x38 -#define KW_I2C_STATUS_MAST_RD_ADDR_ACK 0x40 -#define KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48 -#define KW_I2C_STATUS_MAST_RD_DATA_ACK 0x50 -#define KW_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58 -#define KW_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0 -#define KW_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8 -#define KW_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0 -#define KW_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 -#define KW_I2C_STATUS_NO_STATUS 0xf8 - -/* Driver states */ -enum { - KW_I2C_STATE_INVALID, - KW_I2C_STATE_IDLE, - KW_I2C_STATE_WAITING_FOR_START_COND, - KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK, - KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK, - KW_I2C_STATE_WAITING_FOR_SLAVE_ACK, - KW_I2C_STATE_WAITING_FOR_SLAVE_DATA, -}; - -/* Driver actions */ -enum { - KW_I2C_ACTION_INVALID, - KW_I2C_ACTION_CONTINUE, - KW_I2C_ACTION_SEND_START, - KW_I2C_ACTION_SEND_ADDR_1, - KW_I2C_ACTION_SEND_ADDR_2, - KW_I2C_ACTION_SEND_DATA, - KW_I2C_ACTION_RCV_DATA, - KW_I2C_ACTION_RCV_DATA_STOP, - KW_I2C_ACTION_SEND_STOP, -}; - -/* defines to get compatible with Linux driver */ -#define IRQ_NONE 0x0 -#define IRQ_HANDLED 0x01 - -#define I2C_M_TEN 0x01 -#define I2C_M_RD 0x02 -#define I2C_M_REV_DIR_ADDR 0x04; - -struct i2c_msg { - u32 addr; - u32 flags; - u8 *buf; - u32 len; -}; - -struct kirkwood_i2c_data { - int irq; - u32 state; - u32 action; - u32 aborting; - u32 cntl_bits; - void *reg_base; - u32 reg_base_p; - u32 reg_size; - u32 addr1; - u32 addr2; - u32 bytes_left; - u32 byte_posn; - u32 block; - int rc; - u32 freq_m; - u32 freq_n; - struct i2c_msg *msg; -}; - -static struct kirkwood_i2c_data __drv_data __attribute__ ((section (".data"))); -static struct kirkwood_i2c_data *drv_data = &__drv_data; -static struct i2c_msg __i2c_msg __attribute__ ((section (".data"))); -static struct i2c_msg *kirkwood_i2c_msg = &__i2c_msg; - -/* - ***************************************************************************** - * - * Finite State Machine & Interrupt Routines - * - ***************************************************************************** - */ - -static inline int abs(int n) -{ - if(n >= 0) - return n; - else - return n * -1; -} - -static void kirkwood_calculate_speed(int speed) -{ - int calcspeed; - int diff; - int best_diff = CONFIG_SYS_TCLK; - int best_speed = 0; - int m, n; - int tmp[8] = {2, 4, 8, 16, 32, 64, 128, 256}; - - for (n = 0; n < 8; n++) { - for (m = 0; m < 16; m++) { - calcspeed = CONFIG_SYS_TCLK / (10 * (m + 1) * tmp[n]); - diff = abs((speed - calcspeed)); - if ( diff < best_diff) { - best_diff = diff; - best_speed = calcspeed; - drv_data->freq_m = m; - drv_data->freq_n = n; - } - } - } -} - -/* Reset hardware and initialize FSM */ -static void -kirkwood_i2c_hw_init(int speed, int slaveadd) -{ - drv_data->state = KW_I2C_STATE_IDLE; - - kirkwood_calculate_speed(speed); - writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SOFT_RESET); - writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)), - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_BAUD); - writel(slaveadd, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_SLAVE_ADDR); - writel(0, CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_EXT_SLAVE_ADDR); - writel(KW_I2C_REG_CONTROL_TWSIEN | KW_I2C_REG_CONTROL_STOP, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); -} - -static void -kirkwood_i2c_fsm(u32 status) -{ - /* - * If state is idle, then this is likely the remnants of an old - * operation that driver has given up on or the user has killed. - * If so, issue the stop condition and go to idle. - */ - if (drv_data->state == KW_I2C_STATE_IDLE) { - drv_data->action = KW_I2C_ACTION_SEND_STOP; - return; - } - - /* The status from the ctlr [mostly] tells us what to do next */ - switch (status) { - /* Start condition interrupt */ - case KW_I2C_STATUS_MAST_START: /* 0x08 */ - case KW_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */ - drv_data->action = KW_I2C_ACTION_SEND_ADDR_1; - drv_data->state = KW_I2C_STATE_WAITING_FOR_ADDR_1_ACK; - break; - - /* Performing a write */ - case KW_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */ - if (drv_data->msg->flags & I2C_M_TEN) { - drv_data->action = KW_I2C_ACTION_SEND_ADDR_2; - drv_data->state = - KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK; - break; - } - /* FALLTHRU */ - case KW_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */ - case KW_I2C_STATUS_MAST_WR_ACK: /* 0x28 */ - if ((drv_data->bytes_left == 0) - || (drv_data->aborting - && (drv_data->byte_posn != 0))) { - drv_data->action = KW_I2C_ACTION_SEND_STOP; - drv_data->state = KW_I2C_STATE_IDLE; - } else { - drv_data->action = KW_I2C_ACTION_SEND_DATA; - drv_data->state = - KW_I2C_STATE_WAITING_FOR_SLAVE_ACK; - drv_data->bytes_left--; - } - break; - - /* Performing a read */ - case KW_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */ - if (drv_data->msg->flags & I2C_M_TEN) { - drv_data->action = KW_I2C_ACTION_SEND_ADDR_2; - drv_data->state = - KW_I2C_STATE_WAITING_FOR_ADDR_2_ACK; - break; - } - /* FALLTHRU */ - case KW_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */ - if (drv_data->bytes_left == 0) { - drv_data->action = KW_I2C_ACTION_SEND_STOP; - drv_data->state = KW_I2C_STATE_IDLE; - break; - } - /* FALLTHRU */ - case KW_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */ - if (status != KW_I2C_STATUS_MAST_RD_DATA_ACK) - drv_data->action = KW_I2C_ACTION_CONTINUE; - else { - drv_data->action = KW_I2C_ACTION_RCV_DATA; - drv_data->bytes_left--; - } - drv_data->state = KW_I2C_STATE_WAITING_FOR_SLAVE_DATA; - - if ((drv_data->bytes_left == 1) || drv_data->aborting) - drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_ACK; - break; - - case KW_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */ - drv_data->action = KW_I2C_ACTION_RCV_DATA_STOP; - drv_data->state = KW_I2C_STATE_IDLE; - break; - - case KW_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */ - case KW_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */ - case KW_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */ - /* Doesn't seem to be a device at other end */ - drv_data->action = KW_I2C_ACTION_SEND_STOP; - drv_data->state = KW_I2C_STATE_IDLE; - drv_data->rc = -ENODEV; - break; - - default: - printf("kirkwood_i2c_fsm: Ctlr Error -- state: 0x%x, " - "status: 0x%x, addr: 0x%x, flags: 0x%x\n", - drv_data->state, status, drv_data->msg->addr, - drv_data->msg->flags); - drv_data->action = KW_I2C_ACTION_SEND_STOP; - kirkwood_i2c_hw_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - drv_data->rc = -EIO; - } -} - -static void -kirkwood_i2c_do_action(void) -{ - switch(drv_data->action) { - case KW_I2C_ACTION_CONTINUE: - writel(drv_data->cntl_bits, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_SEND_START: - writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_START, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_SEND_ADDR_1: - writel(drv_data->addr1, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); - writel(drv_data->cntl_bits, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_SEND_ADDR_2: - writel(drv_data->addr2, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); - writel(drv_data->cntl_bits, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_SEND_DATA: - writel(drv_data->msg->buf[drv_data->byte_posn++], - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); - writel(drv_data->cntl_bits, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_RCV_DATA: - drv_data->msg->buf[drv_data->byte_posn++] = - readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); - writel(drv_data->cntl_bits, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - break; - - case KW_I2C_ACTION_RCV_DATA_STOP: - drv_data->msg->buf[drv_data->byte_posn++] = - readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_DATA); - drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN; - writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - drv_data->block = 0; - break; - - case KW_I2C_ACTION_INVALID: - default: - printf("kirkwood_i2c_do_action: Invalid action: %d\n", - drv_data->action); - drv_data->rc = -EIO; - /* FALLTHRU */ - case KW_I2C_ACTION_SEND_STOP: - drv_data->cntl_bits &= ~KW_I2C_REG_CONTROL_INTEN; - writel(drv_data->cntl_bits | KW_I2C_REG_CONTROL_STOP, - CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - drv_data->block = 0; - break; - } -} - -static int -kirkwood_i2c_intr(void) -{ - u32 status; - u32 ctrl; - int rc = IRQ_NONE; - - ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - while ((ctrl & KW_I2C_REG_CONTROL_IFLG) && - (drv_data->rc == 0)) { - status = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_STATUS); - kirkwood_i2c_fsm(status); - kirkwood_i2c_do_action(); - rc = IRQ_HANDLED; - ctrl = readl(CONFIG_I2C_KW_REG_BASE + KW_I2C_REG_CONTROL); - udelay(1000); - } - return rc; -} - -static void -kirkwood_i2c_doio(struct i2c_msg *msg) -{ - int ret; - - while ((drv_data->rc == 0) && (drv_data->state != KW_I2C_STATE_IDLE)) { - /* poll Status register */ - ret = kirkwood_i2c_intr(); - if (ret == IRQ_NONE) - udelay(10); - } -} - -static void -kirkwood_i2c_prepare_for_io(struct i2c_msg *msg) -{ - u32 dir = 0; - - drv_data->msg = msg; - drv_data->byte_posn = 0; - drv_data->bytes_left = msg->len; - drv_data->aborting = 0; - drv_data->rc = 0; - /* in u-boot we use no IRQs */ - drv_data->cntl_bits = KW_I2C_REG_CONTROL_ACK | KW_I2C_REG_CONTROL_TWSIEN; - - if (msg->flags & I2C_M_RD) - dir = 1; - if (msg->flags & I2C_M_TEN) { - drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir; - drv_data->addr2 = (u32)msg->addr & 0xff; - } else { - drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir; - drv_data->addr2 = 0; - } - /* OK, no start it (from kirkwood_i2c_execute_msg())*/ - drv_data->action = KW_I2C_ACTION_SEND_START; - drv_data->state = KW_I2C_STATE_WAITING_FOR_START_COND; - drv_data->block = 1; - kirkwood_i2c_do_action(); -} - -void -i2c_init(int speed, int slaveadd) -{ - kirkwood_i2c_hw_init(speed, slaveadd); -} - -int -i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) -{ - kirkwood_i2c_msg->buf = data; - kirkwood_i2c_msg->len = length; - kirkwood_i2c_msg->addr = dev; - kirkwood_i2c_msg->flags = I2C_M_RD; - - kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg); - kirkwood_i2c_doio(kirkwood_i2c_msg); - return drv_data->rc; -} - -int -i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) -{ - kirkwood_i2c_msg->buf = data; - kirkwood_i2c_msg->len = length; - kirkwood_i2c_msg->addr = dev; - kirkwood_i2c_msg->flags = 0; - - kirkwood_i2c_prepare_for_io(kirkwood_i2c_msg); - kirkwood_i2c_doio(kirkwood_i2c_msg); - return drv_data->rc; -} - -int -i2c_probe(uchar chip) -{ - return i2c_read(chip, 0, 0, NULL, 0); -} - -int i2c_set_bus_num(unsigned int bus) -{ -#if defined(CONFIG_I2C_MUX) - if (bus < CONFIG_SYS_MAX_I2C_BUS) { - i2c_bus_num = bus; - } else { - int ret; - - ret = i2x_mux_select_mux(bus); - if (ret) - return ret; - i2c_bus_num = 0; - } - i2c_bus_num_mux = bus; -#else - if (bus > 0) { - return -1; - } - - i2c_bus_num = bus; -#endif - return 0; -} - -unsigned int i2c_get_bus_num(void) -{ -#if defined(CONFIG_I2C_MUX) - return i2c_bus_num_mux; -#else - return i2c_bus_num; -#endif -} diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c new file mode 100644 index 0000000..16a536f --- /dev/null +++ b/drivers/i2c/mvtwsi.c @@ -0,0 +1,428 @@ +/* + * Driver for the TWSI (i2c) controller found on the Marvell + * orion5x and kirkwood SoC families. + * + * Author: Albert Aribaud <albert.aribaud@free.fr> + * Copyright (c) 2010 Albert Aribaud. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <i2c.h> +#include <asm/errno.h> +#include <asm/io.h> + +/* + * include a file that will provide CONFIG_I2C_MVTWSI_BASE + * and possibly other settings + */ + +#if defined(CONFIG_ORION5X) +#include <asm/arch/orion5x.h> +#elif defined(CONFIG_KIRKWOOD) +#include <asm/arch/kirkwood.h> +#else +#error Driver mvtwsi not supported by SoC or board +#endif + +/* + * TWSI register structure + */ + +struct mvtwsi_registers { + u32 slave_address; + u32 data; + u32 control; + union { + u32 status; /* when reading */ + u32 baudrate; /* when writing */ + }; + u32 xtnd_slave_addr; + u32 reserved[2]; + u32 soft_reset; +}; + +/* + * Control register fields + */ + +#define MVTWSI_CONTROL_ACK 0x00000004 +#define MVTWSI_CONTROL_IFLG 0x00000008 +#define MVTWSI_CONTROL_STOP 0x00000010 +#define MVTWSI_CONTROL_START 0x00000020 +#define MVTWSI_CONTROL_TWSIEN 0x00000040 +#define MVTWSI_CONTROL_INTEN 0x00000080 + +/* + * Status register values -- only those expected in normal master + * operation on non-10-bit-address devices; whatever status we don't + * expect in nominal conditions (bus errors, arbitration losses, + * missing ACKs...) we just pass back to the caller as an error + * code. + */ + +#define MVTWSI_STATUS_START 0x08 +#define MVTWSI_STATUS_REPEATED_START 0x10 +#define MVTWSI_STATUS_ADDR_W_ACK 0x18 +#define MVTWSI_STATUS_DATA_W_ACK 0x28 +#define MVTWSI_STATUS_ADDR_R_ACK 0x40 +#define MVTWSI_STATUS_ADDR_R_NAK 0x48 +#define MVTWSI_STATUS_DATA_R_ACK 0x50 +#define MVTWSI_STATUS_DATA_R_NAK 0x58 +#define MVTWSI_STATUS_IDLE 0xF8 + +/* + * The single instance of the controller we'll be dealing with + */ + +static struct mvtwsi_registers *twsi = + (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE; + +/* + * Returned statuses are 0 for success and nonzero otherwise. + * Currently, cmd_i2c and cmd_eeprom do not interpret an error status. + * Thus to ease debugging, the return status contains some debug info: + * - bits 31..24 are error class: 1 is timeout, 2 is 'status mismatch'. + * - bits 23..16 are the last value of the control register. + * - bits 15..8 are the last value of the status register. + * - bits 7..0 are the expected value of the status register. + */ + +#define MVTWSI_ERROR_WRONG_STATUS 0x01 +#define MVTWSI_ERROR_TIMEOUT 0x02 + +#define MVTWSI_ERROR(ec, lc, ls, es) (((ec << 24) & 0xFF000000) | \ + ((lc << 16) & 0x00FF0000) | ((ls<<8) & 0x0000FF00) | (es & 0xFF)) + +/* + * Wait for IFLG to raise, or return 'timeout'; then if status is as expected, + * return 0 (ok) or return 'wrong status'. + */ +static int twsi_wait(int expected_status) +{ + int control, status; + int timeout = 1000; + + do { + control = readl(&twsi->control); + if (control & MVTWSI_CONTROL_IFLG) { + status = readl(&twsi->status); + if (status == expected_status) + return 0; + else + return MVTWSI_ERROR( + MVTWSI_ERROR_WRONG_STATUS, + control, status, expected_status); + } + udelay(10); /* one clock cycle at 100 kHz */ + } while (timeout--); + status = readl(&twsi->status); + return MVTWSI_ERROR( + MVTWSI_ERROR_TIMEOUT, control, status, expected_status); +} + +/* + * These flags are ORed to any write to the control register + * They allow global setting of TWSIEN and ACK. + * By default none are set. + * twsi_start() sets TWSIEN (in case the controller was disabled) + * twsi_recv() sets ACK or resets it depending on expected status. + */ +static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN; + +/* + * Assert the START condition, either in a single I2C transaction + * or inside back-to-back ones (repeated starts). + */ +static int twsi_start(int expected_status) +{ + /* globally set TWSIEN in case it was not */ + twsi_control_flags |= MVTWSI_CONTROL_TWSIEN; + /* assert START */ + writel(twsi_control_flags | MVTWSI_CONTROL_START, &twsi->control); + /* wait for controller to process START */ + return twsi_wait(expected_status); +} + +/* + * Send a byte (i2c address or data). + */ +static int twsi_send(u8 byte, int expected_status) +{ + /* put byte in data register for sending */ + writel(byte, &twsi->data); + /* clear any pending interrupt -- that'll cause sending */ + writel(twsi_control_flags, &twsi->control); + /* wait for controller to receive byte and check ACK */ + return twsi_wait(expected_status); +} + +/* + * Receive a byte. + * Global mvtwsi_control_flags variable says if we should ack or nak. + */ +static int twsi_recv(u8 *byte) +{ + int expected_status, status; + + /* compute expected status based on ACK bit in global control flags */ + if (twsi_control_flags & MVTWSI_CONTROL_ACK) + expected_status = MVTWSI_STATUS_DATA_R_ACK; + else + expected_status = MVTWSI_STATUS_DATA_R_NAK; + /* acknowledge *previous state* and launch receive */ + writel(twsi_control_flags, &twsi->control); + /* wait for controller to receive byte and assert ACK or NAK */ + status = twsi_wait(expected_status); + /* if we did receive expected byte then store it */ + if (status == 0) + *byte = readl(&twsi->data); + /* return status */ + return status; +} + +/* + * Assert the STOP condition. + * This is also used to force the bus back in idle (SDA=SCL=1). + */ +static int twsi_stop(int status) +{ + int control, stop_status; + int timeout = 1000; + + /* assert STOP */ + control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP; + writel(control, &twsi->control); + /* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */ + do { + stop_status = readl(&twsi->status); + if (stop_status == MVTWSI_STATUS_IDLE) + break; + udelay(10); /* one clock cycle at 100 kHz */ + } while (timeout--); + control = readl(&twsi->control); + if (stop_status != MVTWSI_STATUS_IDLE) + if (status == 0) + status = MVTWSI_ERROR( + MVTWSI_ERROR_TIMEOUT, + control, status, MVTWSI_STATUS_IDLE); + return status; +} + +/* + * Ugly formula to convert m and n values to a frequency comes from + * TWSI specifications + */ + +#define TWSI_FREQUENCY(m, n) \ + ((u8) (CONFIG_SYS_TCLK / (10 * (m + 1) * 2 * (1 << n)))) + +/* + * These are required to be reprogrammed before enabling the controller + * because a reset loses them. + * Default values come from the spec, but a twsi_reset will change them. + * twsi_slave_address left uninitialized lest checkpatch.pl complains. + */ + +/* Baudrate generator: m (bits 7..4) =4, n (bits 3..0) =4 */ +static u8 twsi_baud_rate = 0x44; /* baudrate at controller reset */ +/* Default frequency corresponding to default m=4, n=4 */ +static u8 twsi_actual_speed = TWSI_FREQUENCY(4, 4); +/* Default slave address is 0 (so is an uninitialized static) */ +static u8 twsi_slave_address; + +/* + * Reset controller. + * Called at end of i2c_init unsuccessful i2c transactions. + * Controller reset also resets the baud rate and slave address, so + * re-establish them. + */ +static void twsi_reset(void) +{ + /* ensure controller will be enabled by any twsi*() function */ + twsi_control_flags = MVTWSI_CONTROL_TWSIEN; + /* reset controller */ + writel(0, &twsi->soft_reset); + /* wait 2 ms -- this is what the Marvell LSP does */ + udelay(20000); + /* set baud rate */ + writel(twsi_baud_rate, &twsi->baudrate); + /* set slave address even though we don't use it */ + writel(twsi_slave_address, &twsi->slave_address); + writel(0, &twsi->xtnd_slave_addr); + /* assert STOP but don't care for the result */ + (void) twsi_stop(0); +} + +/* + * I2C init called by cmd_i2c when doing 'i2c reset'. + * Sets baud to the highest possible value not exceeding requested one. + */ +void i2c_init(int requested_speed, int slaveadd) +{ + int tmp_speed, highest_speed, n, m; + int baud = 0x44; /* baudrate at controller reset */ + + /* use actual speed to collect progressively higher values */ + highest_speed = 0; + /* compute m, n setting for highest speed not above requested speed */ + for (n = 0; n < 8; n++) { + for (m = 0; m < 16; m++) { + tmp_speed = TWSI_FREQUENCY(m, n); + if ((tmp_speed <= requested_speed) + && (tmp_speed > highest_speed)) { + highest_speed = tmp_speed; + baud = (m << 3) | n; + } + } + } + /* save baud rate and slave for later calls to twsi_reset */ + twsi_baud_rate = baud; + twsi_actual_speed = highest_speed; + twsi_slave_address = slaveadd; + /* reset controller */ + twsi_reset(); +} + +/* + * Begin I2C transaction with expected start status, at given address. + * Common to i2c_probe, i2c_read and i2c_write. + * Expected address status will derive from direction bit (bit 0) in addr. + */ +static int i2c_begin(int expected_start_status, u8 addr) +{ + int status, expected_addr_status; + + /* compute expected address status from direction bit in addr */ + if (addr & 1) /* reading */ + expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK; + else /* writing */ + expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK; + /* assert START */ + status = twsi_start(expected_start_status); + /* send out the address if the start went well */ + if (status == 0) + status = twsi_send(addr, expected_addr_status); + /* return ok or status of first failure to caller */ + return status; +} + +/* + * I2C probe called by cmd_i2c when doing 'i2c probe'. + * Begin read, nak data byte, end. + */ +int i2c_probe(uchar chip) +{ + u8 dummy_byte; + int status; + + /* begin i2c read */ + status = i2c_begin(MVTWSI_STATUS_START, (chip << 1) | 1); + /* dummy read was accepted: receive byte but NAK it. */ + if (status == 0) + status = twsi_recv(&dummy_byte); + /* Stop transaction */ + twsi_stop(0); + /* return 0 or status of first failure */ + return status; +} + +/* + * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c + * Begin write, send address byte(s), begin read, receive data bytes, end. + * + * NOTE: some EEPROMS want a stop right before the second start, while + * some will choke if it is there. Deciding which we should do is eeprom + * stuff, not i2c, but at the moment the APIs won't let us put it in + * cmd_eeprom, so we have to choose here, and for the moment that'll be + * a repeated start without a preceding stop. + */ +int i2c_read(u8 dev, uint addr, int alen, u8 *data, int length) +{ + int status; + + /* begin i2c write to send the address bytes */ + status = i2c_begin(MVTWSI_STATUS_START, (dev << 1)); + /* send addr bytes */ + while ((status == 0) && alen--) + status = twsi_send(addr >> (8*alen), + MVTWSI_STATUS_DATA_W_ACK); + /* begin i2c read to receive eeprom data bytes */ + if (status == 0) + status = i2c_begin( + MVTWSI_STATUS_REPEATED_START, (dev << 1) | 1); + /* prepare ACK if at least one byte must be received */ + if (length > 0) + twsi_control_flags |= MVTWSI_CONTROL_ACK; + /* now receive actual bytes */ + while ((status == 0) && length--) { + /* reset NAK if we if no more to read now */ + if (length == 0) + twsi_control_flags &= ~MVTWSI_CONTROL_ACK; + /* read current byte */ + status = twsi_recv(data++); + } + /* Stop transaction */ + status = twsi_stop(status); + /* return 0 or status of first failure */ + return status; +} + +/* + * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c + * Begin write, send address byte(s), send data bytes, end. + */ +int i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) +{ + int status; + + /* begin i2c write to send the eeprom adress bytes then data bytes */ + status = i2c_begin(MVTWSI_STATUS_START, (dev << 1)); + /* send addr bytes */ + while ((status == 0) && alen--) + status = twsi_send(addr >> (8*alen), + MVTWSI_STATUS_DATA_W_ACK); + /* send data bytes */ + while ((status == 0) && (length-- > 0)) + status = twsi_send(*(data++), MVTWSI_STATUS_DATA_W_ACK); + /* Stop transaction */ + status = twsi_stop(status); + /* return 0 or status of first failure */ + return status; +} + +/* + * Bus set routine: we only support bus 0. + */ +int i2c_set_bus_num(unsigned int bus) +{ + if (bus > 0) { + return -1; + } + return 0; +} + +/* + * Bus get routine: hard-return bus 0. + */ +unsigned int i2c_get_bus_num(void) +{ + return 0; +} diff --git a/drivers/i2c/omap24xx_i2c.h b/drivers/i2c/omap24xx_i2c.h index 650e33a..1f38c23 100644 --- a/drivers/i2c/omap24xx_i2c.h +++ b/drivers/i2c/omap24xx_i2c.h @@ -20,8 +20,8 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -#ifndef _OMAP24XX_I2C_H_ -#define _OMAP24XX_I2C_H_ +#ifndef _OMAP2PLUS_I2C_H_ +#define _OMAP2PLUS_I2C_H_ /* I2C masks */ diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c index 9506cca..15d41e5 100644 --- a/drivers/mmc/omap3_mmc.c +++ b/drivers/mmc/omap3_mmc.c @@ -33,7 +33,7 @@ #include "omap3_mmc.h" -const unsigned short mmc_transspeed_val[15][4] = { +static const unsigned short mmc_transspeed_val[15][4] = { {CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)}, {CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)}, {CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)}, @@ -51,7 +51,7 @@ const unsigned short mmc_transspeed_val[15][4] = { {CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)} }; -mmc_card_data cur_card_data; +static mmc_card_data cur_card_data; static block_dev_desc_t mmc_blk_dev; static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE; @@ -80,7 +80,7 @@ block_dev_desc_t *mmc_get_dev(int dev) return (block_dev_desc_t *) &mmc_blk_dev; } -unsigned char mmc_board_init(void) +static unsigned char mmc_board_init(void) { #if defined(CONFIG_TWL4030_POWER) twl4030_power_mmc_init(); @@ -114,7 +114,7 @@ unsigned char mmc_board_init(void) return 1; } -void mmc_init_stream(void) +static void mmc_init_stream(void) { writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); @@ -129,7 +129,7 @@ void mmc_init_stream(void) writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); } -unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) +static unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) { unsigned int val; @@ -158,7 +158,7 @@ unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) return 1; } -unsigned char mmc_init_setup(void) +static unsigned char mmc_init_setup(void) { unsigned int reg_val; @@ -192,7 +192,7 @@ unsigned char mmc_init_setup(void) return 1; } -unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, +static unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, unsigned int *response) { unsigned int mmc_stat; @@ -228,7 +228,7 @@ unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, return 1; } -unsigned char mmc_read_data(unsigned int *output_buf) +static unsigned char mmc_read_data(unsigned int *output_buf) { unsigned int mmc_stat; unsigned int read_count = 0; @@ -269,7 +269,7 @@ unsigned char mmc_read_data(unsigned int *output_buf) return 1; } -unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) +static unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) { unsigned char err; unsigned int argument = 0; @@ -380,7 +380,7 @@ unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) return 1; } -unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data, +static unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data, mmc_csd_reg_t *cur_csd) { mmc_extended_csd_reg_t ext_csd; @@ -434,45 +434,48 @@ unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data, return 1; } -unsigned char omap_mmc_read_sect(unsigned int start_sec, unsigned int num_bytes, - mmc_card_data *mmc_c, - unsigned long *output_buf) +static unsigned long mmc_bread(int dev_num, unsigned long blknr, + lbaint_t blkcnt, void *dst) { unsigned char err; unsigned int argument; unsigned int resp[4]; - unsigned int num_sec_val = - (num_bytes + (MMCSD_SECTOR_SIZE - 1)) / MMCSD_SECTOR_SIZE; + unsigned int *output_buf = dst; unsigned int sec_inc_val; + lbaint_t i; - if (num_sec_val == 0) - return 1; + if (blkcnt == 0) + return 0; - if (mmc_c->mode == SECTOR_MODE) { - argument = start_sec; + if (cur_card_data.mode == SECTOR_MODE) { + argument = blknr; sec_inc_val = 1; } else { - argument = start_sec * MMCSD_SECTOR_SIZE; + argument = blknr * MMCSD_SECTOR_SIZE; sec_inc_val = MMCSD_SECTOR_SIZE; } - while (num_sec_val) { + for (i = 0; i < blkcnt; i++) { err = mmc_send_cmd(MMC_CMD17, argument, resp); - if (err != 1) - return err; + if (err != 1) { + printf("mmc: CMD17 failed, status = %08x\n", err); + break; + } - err = mmc_read_data((unsigned int *) output_buf); - if (err != 1) - return err; + err = mmc_read_data(output_buf); + if (err != 1) { + printf("mmc: read failed, status = %08x\n", err); + break; + } output_buf += (MMCSD_SECTOR_SIZE / 4); argument += sec_inc_val; - num_sec_val--; } - return 1; + + return i; } -unsigned char configure_mmc(mmc_card_data *mmc_card_cur) +static unsigned char configure_mmc(mmc_card_data *mmc_card_cur) { unsigned char ret_val; unsigned int argument; @@ -541,13 +544,6 @@ unsigned char configure_mmc(mmc_card_data *mmc_card_cur) return 1; } -unsigned long mmc_bread(int dev_num, unsigned long blknr, lbaint_t blkcnt, - void *dst) -{ - omap_mmc_read_sect(blknr, (blkcnt * MMCSD_SECTOR_SIZE), &cur_card_data, - (unsigned long *) dst); - return 1; -} int mmc_legacy_init(int dev) { diff --git a/drivers/mmc/omap3_mmc.h b/drivers/mmc/omap3_mmc.h index cbb3dc3..e4d263c 100644 --- a/drivers/mmc/omap3_mmc.h +++ b/drivers/mmc/omap3_mmc.h @@ -230,13 +230,4 @@ typedef union { mmc_csd_reg_t Card_CSD; } mmc_resp_t; -extern mmc_card_data mmc_dev; - -unsigned char mmc_lowlevel_init(void); -unsigned char mmc_send_command(unsigned int cmd, unsigned int arg, - unsigned int *response); -unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd); -unsigned char mmc_set_opendrain(unsigned char state); -unsigned char mmc_read_data(unsigned int *output_buf); - #endif /* MMC_H */ diff --git a/drivers/mmc/s5p_mmc.c b/drivers/mmc/s5p_mmc.c index 669b1d0..1fd425c 100644 --- a/drivers/mmc/s5p_mmc.c +++ b/drivers/mmc/s5p_mmc.c @@ -23,12 +23,6 @@ #include <asm/io.h> #include <asm/arch/mmc.h> -#ifdef DEBUG_S5P_HSMMC -#define dbg(x...) printf(x) -#else -#define dbg(x...) do { } while (0) -#endif - /* support 4 mmc hosts */ struct mmc mmc_dev[4]; struct mmc_host mmc_host[4]; @@ -36,18 +30,14 @@ struct mmc_host mmc_host[4]; static inline struct s5p_mmc *s5p_get_base_mmc(int dev_index) { unsigned long offset = dev_index * sizeof(struct s5p_mmc); - - if (cpu_is_s5pc100()) - return (struct s5p_mmc *)(S5PC100_MMC_BASE + offset); - else - return (struct s5p_mmc *)(S5PC110_MMC_BASE + offset); + return (struct s5p_mmc *)(samsung_get_base_mmc() + offset); } static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data) { unsigned char ctrl; - dbg("data->dest: %08x\n", (u32)data->dest); + debug("data->dest: %08x\n", (u32)data->dest); writel((u32)data->dest, &host->reg->sysad); /* * DMASEL[4:3] @@ -128,7 +118,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (data) mmc_prepare_data(host, data); - dbg("cmd->arg: %08x\n", cmd->cmdarg); + debug("cmd->arg: %08x\n", cmd->cmdarg); writel(cmd->cmdarg, &host->reg->argument); if (data) @@ -165,7 +155,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (data) flags |= (1 << 5); - dbg("cmd: %d\n", cmd->cmdidx); + debug("cmd: %d\n", cmd->cmdidx); writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg); @@ -186,11 +176,11 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (mask & (1 << 16)) { /* Timeout Error */ - dbg("timeout: %08x cmd %d\n", mask, cmd->cmdidx); + debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); return TIMEOUT; } else if (mask & (1 << 15)) { /* Error Interrupt */ - dbg("error: %08x cmd %d\n", mask, cmd->cmdidx); + debug("error: %08x cmd %d\n", mask, cmd->cmdidx); return -1; } @@ -206,7 +196,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, cmd->response[i] |= readb(offset - 1); } - dbg("cmd->resp[%d]: %08x\n", + debug("cmd->resp[%d]: %08x\n", i, cmd->response[i]); } } else if (cmd->resp_type & MMC_RSP_BUSY) { @@ -223,10 +213,10 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, } cmd->response[0] = readl(&host->reg->rspreg0); - dbg("cmd->resp[0]: %08x\n", cmd->response[0]); + debug("cmd->resp[0]: %08x\n", cmd->response[0]); } else { cmd->response[0] = readl(&host->reg->rspreg0); - dbg("cmd->resp[0]: %08x\n", cmd->response[0]); + debug("cmd->resp[0]: %08x\n", cmd->response[0]); } } @@ -242,11 +232,11 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, return -1; } else if (mask & (1 << 3)) { /* DMA Interrupt */ - dbg("DMA end\n"); + debug("DMA end\n"); break; } else if (mask & (1 << 1)) { /* Transfer Complete */ - dbg("r/w is done\n"); + debug("r/w is done\n"); break; } } @@ -288,7 +278,7 @@ static void mmc_change_clock(struct mmc_host *host, uint clock) div = 2; else div = 1; - dbg("div: %d\n", div); + debug("div: %d\n", div); div >>= 1; /* @@ -325,7 +315,7 @@ static void mmc_set_ios(struct mmc *mmc) unsigned char ctrl; unsigned long val; - dbg("set_ios: bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); + debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock); /* * SELCLKPADDS[17:16] diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c index f2be687..20b4912 100644 --- a/drivers/mtd/onenand/samsung.c +++ b/drivers/mtd/onenand/samsung.c @@ -67,7 +67,7 @@ do { \ #define MAP_01 (0x1 << 24) #define MAP_10 (0x2 << 24) #define MAP_11 (0x3 << 24) -#elif defined(CONFIG_S5PC1XX) +#elif defined(CONFIG_S5P) #define MAP_00 (0x0 << 26) #define MAP_01 (0x1 << 26) #define MAP_10 (0x2 << 26) @@ -121,7 +121,7 @@ static unsigned int s3c_mem_addr(int fba, int fpa, int fsa) { return (fba << 12) | (fpa << 6) | (fsa << 4); } -#elif defined(CONFIG_S5PC1XX) +#elif defined(CONFIG_S5P) static unsigned int s3c_mem_addr(int fba, int fpa, int fsa) { return (fba << 13) | (fpa << 7) | (fsa << 5); @@ -614,7 +614,7 @@ void s3c_onenand_init(struct mtd_info *mtd) #if defined(CONFIG_S3C64XX) onenand->base = (void *)0x70100000; onenand->ahb_addr = (void *)0x20000000; -#elif defined(CONFIG_S5PC1XX) +#elif defined(CONFIG_S5P) onenand->base = (void *)0xE7100000; onenand->ahb_addr = (void *)0xB0000000; #endif diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index c731bfb..6d45a8e 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -36,7 +36,7 @@ COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o COBJS-$(CONFIG_SYS_NS16550) += ns16550.o COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o COBJS-$(CONFIG_S3C64XX) += s3c64xx.o -COBJS-$(CONFIG_S5PC1XX) += serial_s5p.o +COBJS-$(CONFIG_S5P) += serial_s5p.o COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial.o COBJS-$(CONFIG_CLPS7111_SERIAL) += serial_clps7111.o COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index e0d4e80..7709664 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -30,11 +30,7 @@ static inline struct s5p_uart *s5p_get_base_uart(int dev_index) { u32 offset = dev_index * sizeof(struct s5p_uart); - - if (cpu_is_s5pc100()) - return (struct s5p_uart *)(S5PC100_UART_BASE + offset); - else - return (struct s5p_uart *)(S5PC110_UART_BASE + offset); + return (struct s5p_uart *)(samsung_get_base_uart() + offset); } /* @@ -67,11 +63,11 @@ void serial_setbrg_dev(const int dev_index) { DECLARE_GLOBAL_DATA_PTR; struct s5p_uart *const uart = s5p_get_base_uart(dev_index); - u32 pclk = get_pclk(); + u32 uclk = get_uart_clk(dev_index); u32 baudrate = gd->baudrate; u32 val; - val = pclk / baudrate; + val = uclk / baudrate; writel(val / 16 - 1, &uart->ubrdiv); writew(udivslot[val % 16], &uart->udivslot); diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 7d84fc7..4be82e7 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -32,6 +32,7 @@ COBJS-$(CONFIG_S6E63D6) += s6e63d6.o COBJS-$(CONFIG_VIDEO_AMBA) += amba.o COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o +COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o COBJS-$(CONFIG_SED156X) += sed156x.o diff --git a/drivers/video/mb86r0xgdc.c b/drivers/video/mb86r0xgdc.c new file mode 100644 index 0000000..3bdc1db --- /dev/null +++ b/drivers/video/mb86r0xgdc.c @@ -0,0 +1,186 @@ +/* + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * mb86r0xgdc.c - Graphic interface for Fujitsu MB86R0x integrated graphic + * controller. + */ + +#include <common.h> + +#include <malloc.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <video_fb.h> +#include "videomodes.h" + +/* + * 4MB (at the end of system RAM) + */ +#define VIDEO_MEM_SIZE 0x400000 + +#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */ + +/* + * Graphic Device + */ +static GraphicDevice mb86r0x; + +static void dsp_init(struct mb86r0x_gdc_dsp *dsp, char *modestr, + u32 *videomem) +{ + struct ctfb_res_modes var_mode; + u32 dcm1, dcm2, dcm3; + u16 htp, hdp, hdb, hsp, vtr, vsp, vdp; + u8 hsw, vsw; + u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1; + u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh; + unsigned long div; + int bpp; + u32 i; + + bpp = video_get_params(&var_mode, modestr); + + if (bpp == 0) { + var_mode.xres = 640; + var_mode.yres = 480; + var_mode.pixclock = 39721; /* 25MHz */ + var_mode.left_margin = 48; + var_mode.right_margin = 16; + var_mode.upper_margin = 33; + var_mode.lower_margin = 10; + var_mode.hsync_len = 96; + var_mode.vsync_len = 2; + var_mode.sync = 0; + var_mode.vmode = 0; + bpp = 15; + } + + /* Fill memory with white */ + for (i = 0; i < var_mode.xres * var_mode.yres / 2; i++) + *videomem++ = 0xFFFFFFFF; + + mb86r0x.winSizeX = var_mode.xres; + mb86r0x.winSizeY = var_mode.yres; + + /* LCD base clock is ~ 660MHZ. We do calculations in kHz */ + div = 660000 / (1000000000L / var_mode.pixclock); + if (div > 64) + div = 64; + if (0 == div) + div = 1; + + dcm1 = (div - 1) << 8; + dcm2 = 0x00000000; + if (var_mode.sync & FB_SYNC_CLK_INV) + dcm3 = 0x00000100; + else + dcm3 = 0x00000000; + + htp = var_mode.left_margin + var_mode.xres + + var_mode.hsync_len + var_mode.right_margin; + hdp = var_mode.xres; + hdb = var_mode.xres; + hsp = var_mode.xres + var_mode.right_margin; + hsw = var_mode.hsync_len; + + vsw = var_mode.vsync_len; + vtr = var_mode.upper_margin + var_mode.yres + + var_mode.vsync_len + var_mode.lower_margin; + vsp = var_mode.yres + var_mode.lower_margin; + vdp = var_mode.yres; + + l2m = ((var_mode.yres - 1) << (0)) | + (((var_mode.xres * 2) / 64) << (16)) | + ((1) << (31)); + + l2em = (1 << 0) | (1 << 1); + + l2oa0 = mb86r0x.frameAdrs; + l2da0 = mb86r0x.frameAdrs; + l2oa1 = mb86r0x.frameAdrs; + l2da1 = mb86r0x.frameAdrs; + l2dx = 0; + l2dy = 0; + l2wx = 0; + l2wy = 0; + l2ww = var_mode.xres; + l2wh = var_mode.yres - 1; + + writel(dcm1, &dsp->dcm1); + writel(dcm2, &dsp->dcm2); + writel(dcm3, &dsp->dcm3); + + writew(htp, &dsp->htp); + writew(hdp, &dsp->hdp); + writew(hdb, &dsp->hdb); + writew(hsp, &dsp->hsp); + writeb(hsw, &dsp->hsw); + + writeb(vsw, &dsp->vsw); + writew(vtr, &dsp->vtr); + writew(vsp, &dsp->vsp); + writew(vdp, &dsp->vdp); + + writel(l2m, &dsp->l2m); + writel(l2em, &dsp->l2em); + writel(l2oa0, &dsp->l2oa0); + writel(l2da0, &dsp->l2da0); + writel(l2oa1, &dsp->l2oa1); + writel(l2da1, &dsp->l2da1); + writew(l2dx, &dsp->l2dx); + writew(l2dy, &dsp->l2dy); + writew(l2wx, &dsp->l2wx); + writew(l2wy, &dsp->l2wy); + writew(l2ww, &dsp->l2ww); + writew(l2wh, &dsp->l2wh); + + writel(dcm1 | (1 << 18) | (1 << 31), &dsp->dcm1); +} + +void *video_hw_init(void) +{ + struct mb86r0x_gdc *gdc = (struct mb86r0x_gdc *) MB86R0x_GDC_BASE; + GraphicDevice *pGD = &mb86r0x; + char *s; + u32 *vid; + + memset(pGD, 0, sizeof(GraphicDevice)); + + pGD->gdfIndex = GDF_15BIT_555RGB; + pGD->gdfBytesPP = 2; + pGD->memSize = VIDEO_MEM_SIZE; + pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE; + + vid = (u32 *)pGD->frameAdrs; + + s = getenv("videomode"); + if (s != NULL) + dsp_init(&gdc->dsp0, s, vid); + + s = getenv("videomode1"); + if (s != NULL) + dsp_init(&gdc->dsp1, s, vid); + + return pGD; +} diff --git a/examples/standalone/mips.lds b/examples/standalone/mips.lds index 717b201..63a1c92 100644 --- a/examples/standalone/mips.lds +++ b/examples/standalone/mips.lds @@ -24,7 +24,7 @@ /* OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") */ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") OUTPUT_ARCH(mips) SECTIONS { diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 20849bc..a7724ad 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -104,6 +104,7 @@ #define CONFIG_NET_MULTI 1 #undef CONFIG_HAS_ETH1 +#define CONFIG_PPC4xx_EMAC #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index dd609da..3dcee85 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -124,7 +124,7 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD #define CONFIG_FSL_DDR3 diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 57dd165..ccfc660 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -132,6 +132,7 @@ */ #include <config_cmd_default.h> #define CONFIG_CMD_IDE +#define CONFIG_CMD_I2C /* * Network @@ -182,6 +183,16 @@ #endif /* CMD_IDE */ /* + * I2C related stuff + */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_I2C_MVTWSI +#define CONFIG_I2C_MVTWSI_BASE ORION5X_TWSI_BASE +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* * Environment variables configurations */ #define CONFIG_ENV_IS_IN_FLASH 1 diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h new file mode 100644 index 0000000..29c534c --- /dev/null +++ b/include/configs/jadecpu.h @@ -0,0 +1,291 @@ +/* + * (C) Copyright 2010 + * Matthias Weisser <weisserm@arcor.de> + * + * Configuation settings for the jadecpu board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MB86R0x +#define CONFIG_MB86R0x_IOCLK get_bus_freq(0) +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "gs_fast_boot=setenv bootdelay 5\0" \ + "gs_slow_boot=setenv bootdelay 10\0" \ + "bootcmd=mw.l 0x40000000 0 1024; usb start;" \ + "fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \ + "bootelf 0x40000000\0" \ + "" + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define BOARD_LATE_INIT 1 + +/* + * Compressions + */ +#define CONFIG_LZO + +/* + * Hardware drivers + */ + +/* + * Serial + */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_COM1 0xfffe1000 /* UART 0 */ +#define CONFIG_SYS_NS16550_COM2 0xfff50000 /* UART 2 */ +#define CONFIG_SYS_NS16550_COM3 0xfff51000 /* UART 3 */ +#define CONFIG_SYS_NS16550_COM4 0xfff43000 /* UART 4 */ + +#define CONFIG_CONS_INDEX 4 + +/* + * Ethernet + */ +#define CONFIG_NET_MULTI +#define CONFIG_SMC911X +#define CONFIG_SMC911X_BASE 0x02000000 +#define CONFIG_SMC911X_16_BIT + +/* + * Video + */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_MB86R0xGDC +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CFB_CONSOLE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024) +#define VIDEO_FB_16BPP_WORD_SWAP +#define VIDEO_KBD_INIT_FCT 0 +#define VIDEO_TSTC_FCT serial_tstc +#define VIDEO_GETC_FCT serial_getc + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_XIMG + +#define CONFIG_CMD_BMP 1 +#define CONFIG_CMD_CAN 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_ELF 1 +#define CONFIG_CMD_FAT 1 +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_USB 1 + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* USB */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0xFFF81000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mb86r0x" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */ +#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE (128 * 1024) + +/* + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */ + +#define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "jade> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define CONFIG_PREBOOT "" + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "delaygs" +#define CONFIG_AUTOBOOT_STOP_STR "stopgs" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +/* + * Clock reset generator init + */ +#define CONFIG_SYS_CRG_CRHA_INIT 0xffff +#define CONFIG_SYS_CRG_CRPA_INIT 0xffff +#define CONFIG_SYS_CRG_CRPB_INIT 0xfffe +#define CONFIG_SYS_CRG_CRHB_INIT 0xffff +#define CONFIG_SYS_CRG_CRAM_INIT 0xffef + +/* + * Memory controller settings + */ +#define CONFIG_SYS_MEMC_MCFMODE0_INIT 0x00000001 /* 16bit */ +#define CONFIG_SYS_MEMC_MCFMODE2_INIT 0x00000001 /* 16bit */ +#define CONFIG_SYS_MEMC_MCFMODE4_INIT 0x00000021 /* 16bit, Page*/ +#define CONFIG_SYS_MEMC_MCFTIM0_INIT 0x16191008 +#define CONFIG_SYS_MEMC_MCFTIM2_INIT 0x03061008 +#define CONFIG_SYS_MEMC_MCFTIM4_INIT 0x03061804 +#define CONFIG_SYS_MEMC_MCFAREA0_INIT 0x000000c0 /* 0x0c000000 1MB */ +#define CONFIG_SYS_MEMC_MCFAREA2_INIT 0x00000020 /* 0x02000000 1MB */ +#define CONFIG_SYS_MEMC_MCFAREA4_INIT 0x001f0000 /* 0x10000000 32 MB */ + +/* + * DDR2 controller init settings + */ +#define CONFIG_SYS_DDR2_DRIMS_INIT 0x5555 +#define CONFIG_SYS_CCNT_CDCRC_INIT_1 0x00000002 +#define CONFIG_SYS_CCNT_CDCRC_INIT_2 0x00000003 +#define CONFIG_SYS_DDR2_DRIC1_INIT 0x003f +#define CONFIG_SYS_DDR2_DRIC2_INIT 0x0000 +#define CONFIG_SYS_DDR2_DRCA_INIT 0xc124 /* 512Mbit DDR2SDRAM x 2 */ +#define CONFIG_SYS_DDR2_DRCM_INIT 0x0032 +#define CONFIG_SYS_DDR2_DRCST1_INIT 0x3418 +#define CONFIG_SYS_DDR2_DRCST2_INIT 0x6e32 +#define CONFIG_SYS_DDR2_DRCR_INIT 0x0141 +#define CONFIG_SYS_DDR2_DRCF_INIT 0x0002 +#define CONFIG_SYS_DDR2_DRASR_INIT 0x0001 +#define CONFIG_SYS_DDR2_DROBS_INIT 0x0001 +#define CONFIG_SYS_DDR2_DROABA_INIT 0x0103 +#define CONFIG_SYS_DDR2_DRIBSODT1_INIT 0x003F +#define CONFIG_SYS_DDR2_DROS_INIT 0x0001 + +/* + * DRAM init sequence + */ + +/* PALL Command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_1 0x0017 +#define CONFIG_SYS_DDR2_INIT_DRIC2_1 0x0400 + +/* EMR(2) command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_2 0x0006 +#define CONFIG_SYS_DDR2_INIT_DRIC2_2 0x0000 + +/* EMR(3) command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_3 0x0007 +#define CONFIG_SYS_DDR2_INIT_DRIC2_3 0x0000 + +/* EMR(1) command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_4 0x0005 +#define CONFIG_SYS_DDR2_INIT_DRIC2_4 0x0000 + +/* MRS command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_5 0x0004 +#define CONFIG_SYS_DDR2_INIT_DRIC2_5 0x0532 + +/* PALL command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_6 0x0017 +#define CONFIG_SYS_DDR2_INIT_DRIC2_6 0x0400 + +/* REF command 1 */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_7 0x000f +#define CONFIG_SYS_DDR2_INIT_DRIC2_7 0x0000 + +/* MRS command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_8 0x0004 +#define CONFIG_SYS_DDR2_INIT_DRIC2_8 0x0432 + +/* EMR(1) command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_9 0x0005 +#define CONFIG_SYS_DDR2_INIT_DRIC2_9 0x0380 + +/* EMR(1) command */ +#define CONFIG_SYS_DDR2_INIT_DRIC1_10 0x0005 +#define CONFIG_SYS_DDR2_INIT_DRIC2_10 0x0002 + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index 6519c90..1617e69 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -142,16 +142,8 @@ /* * I2C related stuff */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SOFT_I2C /* I2C bit-banged */ -#if defined(CONFIG_HARD_I2C) -#define CONFIG_I2C_KIRKWOOD -#define CONFIG_I2C_KW_REG_BASE KW_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - #define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */ #if defined(CONFIG_SOFT_I2C) #ifndef __ASSEMBLY__ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index c8ea8fd..dc01ceb 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -30,7 +30,7 @@ /* High Level Configuration Options */ #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5PC1XX 1 /* which is in a S5PC1XX Family */ +#define CONFIG_S5P 1 /* which is in a S5P Family */ #define CONFIG_S5PC110 1 /* which is in a S5PC110 */ #define CONFIG_MACH_GONI 1 /* working with Goni */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 76a47c4..595d174 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -34,7 +34,7 @@ */ #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ #define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5PC1XX 1 /* which is in a S5PC1XX Family */ +#define CONFIG_S5P 1 /* which is in a S5P Family */ #define CONFIG_S5PC100 1 /* which is in a S5PC100 */ #define CONFIG_SMDKC100 1 /* working with SMDKC100 */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 1589913..56d24f9 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -39,6 +39,7 @@ #define CONFIG_VE8313 1 #define CONFIG_PCI 1 +#define CONFIG_FSL_ELBC 1 #define CONFIG_BOARD_EARLY_INIT_F 1 diff --git a/include/ppc440.h b/include/ppc440.h index c807dda..6727753 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1711,6 +1711,7 @@ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define CPR0_ICFG_RLI_MASK 0x80000000 +#define CPR0_ICFG_ICS_MASK 0x00000007 #define CPR0_SPCID_SPCIDV0_MASK 0x03000000 #define CPR0_SPCID_SPCIDV0_DIV1 0x01000000 #define CPR0_SPCID_SPCIDV0_DIV2 0x02000000 diff --git a/include/serial.h b/include/serial.h index 6513d8e..15ab73c 100644 --- a/include/serial.h +++ b/include/serial.h @@ -25,9 +25,9 @@ extern struct serial_device * default_serial_console (void); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ - defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) || \ - defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \ - defined(CONFIG_SYS_SC520) + defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \ + defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ + defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CONFIG_SYS_NS16550_SERIAL) @@ -52,7 +52,7 @@ extern struct serial_device s3c24xx_serial1_device; extern struct serial_device s3c24xx_serial2_device; #endif -#if defined(CONFIG_S5PC1XX) +#if defined(CONFIG_S5P) extern struct serial_device s5p_serial0_device; extern struct serial_device s5p_serial1_device; extern struct serial_device s5p_serial2_device; diff --git a/tools/Makefile b/tools/Makefile index 749d994..b2e73b2 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -118,6 +118,9 @@ endif ifeq ($(VENDOR),ronetix) LOGO_BMP= logos/ronetix.bmp endif +ifeq ($(VENDOR),syteco) +LOGO_BMP= logos/syteco.bmp +endif # now $(obj) is defined HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c)) diff --git a/tools/logos/syteco.bmp b/tools/logos/syteco.bmp Binary files differnew file mode 100644 index 0000000..9a994fe --- /dev/null +++ b/tools/logos/syteco.bmp |
