diff options
770 files changed, 9332 insertions, 2448 deletions
@@ -741,8 +741,7 @@ DO_STATIC_RELA = endif # Always append ALL so that arch config.mk's can add custom ones -ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map u-boot.cfg \ - binary_size_check no_new_adhoc_configs_check +ALL-y += u-boot.srec u-boot.bin u-boot.sym System.map binary_size_check ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin ifeq ($(CONFIG_SPL_FSL_PBL),y) @@ -821,6 +820,11 @@ ifeq ($(CONFIG_DM_I2C_COMPAT)$(CONFIG_SANDBOX),y) @echo "before sending patches to the mailing list." @echo "====================================================" endif + @# Check that this build does not use CONFIG options that we do not + @# know about unless they are in Kconfig. All the existing CONFIG + @# options are whitelisted, so new ones should not be added. + $(srctree)/scripts/check-config.sh u-boot.cfg \ + $(srctree)/scripts/config_whitelist.txt ${srctree} 1>&2 PHONY += dtbs dtbs: dts/dt.dtb @@ -845,6 +849,12 @@ endif %.imx: %.bin $(Q)$(MAKE) $(build)=arch/arm/imx-common $@ +%.vyb: %.imx + $(Q)$(MAKE) $(build)=arch/arm/cpu/armv7/vf610 $@ + +quiet_cmd_copy = COPY $@ + cmd_copy = cp $< $@ + u-boot.dtb: dts/dt.dtb $(call cmd,copy) @@ -937,27 +947,6 @@ u-boot.sha1: u-boot.bin u-boot.dis: u-boot $(OBJDUMP) -d $< > $@ -# If .u-boot.cfg.d is still present, then either: -# a) The previous build used a Makefile that used if_changed rather than -# if_changed_dep when building u-boot.cfg, and hence any later builds will -# be unaware of the dependencies for u-boot.cfg. In this case, we must -# delete u-boot.cfg to force it and .u-boot.cfg.cmd to be rebuilt the -# correct way. -# b) The previous build failed or was interrupted while building u-boot.cfg, -# so deleting u-boot.cfg isn't going to cause any additional work. -ifneq ($(wildcard $(obj)/.u-boot.cfg.d),) - unused := $(shell rm -f $(obj)/u-boot.cfg) -endif -u-boot.cfg: include/config.h FORCE - $(call if_changed_dep,cpp_cfg) - -# Check that this build does not use CONFIG options that we don't know about -# unless they are in Kconfig. All the existing CONFIG options are whitelisted, -# so new ones should not be added. -no_new_adhoc_configs_check: u-boot.cfg FORCE - $(srctree)/scripts/check-config.sh $< \ - $(srctree)/scripts/config_whitelist.txt ${srctree} 1>&2 - ifdef CONFIG_TPL SPL_PAYLOAD := tpl/u-boot-with-tpl.bin else @@ -325,27 +325,6 @@ The following options need to be configured: - CPU Daughterboard Type: (if CONFIG_ATSTK1000 is defined) Define exactly one, e.g. CONFIG_ATSTK1002 -- CPU Module Type: (if CONFIG_COGENT is defined) - Define exactly one of - CONFIG_CMA286_60_OLD ---- FIXME --- not tested yet: - CONFIG_CMA286_60, CONFIG_CMA286_21, CONFIG_CMA286_60P, - CONFIG_CMA287_23, CONFIG_CMA287_50 - -- Motherboard Type: (if CONFIG_COGENT is defined) - Define exactly one of - CONFIG_CMA101, CONFIG_CMA102 - -- Motherboard I/O Modules: (if CONFIG_COGENT is defined) - Define one or more of - CONFIG_CMA302 - -- Motherboard Options: (if CONFIG_CMA101 or CONFIG_CMA102 are defined) - Define one or more of - CONFIG_LCD_HEARTBEAT - update a character position on - the LCD display every second with - a "rotator" |\-/|\-/ - - Marvell Family Member CONFIG_SYS_MVFS - define it if you want to enable multiple fs option at one time @@ -578,20 +557,6 @@ The following options need to be configured: CONFIG_SYS_FSL_SEC_LE Defines the SEC controller register space as Little Endian -- Intel Monahans options: - CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO - - Defines the Monahans run mode to oscillator - ratio. Valid values are 8, 16, 24, 31. The core - frequency is this value multiplied by 13 MHz. - - CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO - - Defines the Monahans turbo mode to oscillator - ratio. Valid values are 1 (default if undefined) and - 2. The core frequency as calculated above is multiplied - by this value. - - MIPS CPU options: CONFIG_SYS_INIT_SP_OFFSET @@ -730,11 +695,6 @@ The following options need to be configured: This causes ft_system_setup() to be called before booting the kernel. - CONFIG_OF_BOOT_CPU - - This define fills in the correct boot CPU in the boot - param header, the default value is zero if undefined. - CONFIG_OF_IDE_FIXUP U-Boot can detect if an IDE device is present or not. @@ -1337,10 +1297,6 @@ The following options need to be configured: CONFIG_LAN91C96 Support for SMSC's LAN91C96 chips. - CONFIG_LAN91C96_BASE - Define this to hold the physical address - of the LAN91C96's I/O space - CONFIG_LAN91C96_USE_32_BIT Define this to enable 32 bit addressing @@ -1405,7 +1361,7 @@ The following options need to be configured: - PWM Support: CONFIG_PWM_IMX - Support for PWM modul on the imx6. + Support for PWM module on the imx6. - TPM Support: CONFIG_TPM @@ -1525,10 +1481,6 @@ The following options need to be configured: Derive USB clock from external clock "blah" - CONFIG_SYS_USB_EXTC_CLK 0x02 - CONFIG_SYS_USB_BRG_CLK 0xBLAH - Derive USB clock from brgclk - - CONFIG_SYS_USB_BRG_CLK 0x04 - If you have a USB-IF assigned VendorID then you may wish to define your own vendor specific values either in BoardName.h or directly in usbd_vendor_info.h. If you don't define @@ -1691,23 +1643,13 @@ The following options need to be configured: If not defined the default value "mbr" is used. - Journaling Flash filesystem support: - CONFIG_JFFS2_NAND, CONFIG_JFFS2_NAND_OFF, CONFIG_JFFS2_NAND_SIZE, - CONFIG_JFFS2_NAND_DEV + CONFIG_JFFS2_NAND Define these for a default partition on a NAND device CONFIG_SYS_JFFS2_FIRST_SECTOR, CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS Define these for a default partition on a NOR device - CONFIG_SYS_JFFS_CUSTOM_PART - Define this to create an own partition. You have to provide a - function struct part_info* jffs2_part_info(int part_num) - - If you define only one JFFS2 partition you may also want to - #define CONFIG_SYS_JFFS_SINGLE_PART 1 - to disable the command chpart. This is the default when you - have not defined a custom partition - - FAT(File Allocation Table) filesystem write function support: CONFIG_FAT_WRITE @@ -2338,8 +2280,6 @@ CBFS (Coreboot Filesystem) support - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3 - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4 - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4 - - CONFIG_SYS_I2C_SH_BASE5 for setting the register channel 5 - - CONFIG_SYS_I2C_SH_SPEED5 for for the speed channel 5 - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses - drivers/i2c/omap24xx_i2c.c @@ -2393,10 +2333,7 @@ CBFS (Coreboot Filesystem) support additional defines: CONFIG_SYS_NUM_I2C_BUSES - Hold the number of i2c buses you want to use. If you - don't use/have i2c muxes on your i2c bus, this - is equal to CONFIG_SYS_NUM_I2C_ADAPTERS, and you can - omit this define. + Hold the number of i2c buses you want to use. CONFIG_SYS_I2C_DIRECT_BUS define this, if you don't use i2c muxes on your hardware. @@ -2610,7 +2547,7 @@ CBFS (Coreboot Filesystem) support will skip addresses 0x50 and 0x68 on a board with one I2C bus #define CONFIG_I2C_MULTI_BUS - #define CONFIG_SYS_I2C_MULTI_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} + #define CONFIG_SYS_I2C_NOPROBES {{0,0x50},{0,0x68},{1,0x54}} will skip addresses 0x50 and 0x68 on bus 0 and address 0x54 on bus 1 @@ -3767,10 +3704,6 @@ Configuration Settings: - CONFIG_SYS_SDRAM_BASE: Physical start address of SDRAM. _Must_ be 0 here. -- CONFIG_SYS_MBIO_BASE: - Physical start address of Motherboard I/O (if using a - Cogent motherboard) - - CONFIG_SYS_FLASH_BASE: Physical start address of Flash memory. @@ -4202,7 +4135,7 @@ to save the current settings. This setting describes a second storage area of CONFIG_ENV_SIZE size used to hold a redundant copy of the environment data, so that there is a valid backup copy in case there is a power failure - during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be + during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be aligned to an erase sector boundary. - CONFIG_ENV_SPI_BUS (optional): @@ -4253,7 +4186,7 @@ but it can not erase, write this NOR flash by SRIO or PCIE interface. This setting describes a second storage area of CONFIG_ENV_SIZE size used to hold a redundant copy of the environment data, so that there is a valid backup copy in case there is a power failure - during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be + during a "saveenv" operation. CONFIG_ENV_OFFSET_REDUND must be aligned to an erase block boundary. - CONFIG_ENV_RANGE (optional): @@ -4554,7 +4487,7 @@ Low Level (hardware related) configuration options: CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial data is located at the end of the available space (sometimes written as (CONFIG_SYS_INIT_RAM_SIZE - - CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just + GENERATED_GBL_DATA_SIZE), and the initial stack is just below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) downward. @@ -4613,11 +4546,6 @@ Low Level (hardware related) configuration options: enable SPI microcode relocation patch (MPC8xx); define relocation offset in DPRAM [SCC4] -- CONFIG_SYS_USE_OSCCLK: - Use OSCM clock mode on MBX8xx board. Be careful, - wrong setting might damage your board. Read - doc/README.MBX before setting this variable! - - CONFIG_SYS_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only) Offset of the bootmode word in DPRAM used by post (Power On Self Tests). This definition overrides @@ -4861,10 +4789,6 @@ within that device. Specifies that QE/FMAN firmware is located on the primary SD/MMC device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device. -- CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH - Specifies that QE/FMAN firmware is located on the primary SPI - device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device. - - CONFIG_SYS_QE_FMAN_FW_IN_REMOTE Specifies that QE/FMAN firmware is located in the remote (master) memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which @@ -4883,22 +4807,6 @@ within that device. - CONFIG_FSL_MC_ENET Enable the MC driver for Layerscape SoCs. -- CONFIG_SYS_LS_MC_FW_ADDR - The address in the storage device where the firmware is located. The - meaning of this address depends on which CONFIG_SYS_LS_MC_FW_IN_xxx macro - is also specified. - -- CONFIG_SYS_LS_MC_FW_LENGTH - The maximum possible size of the firmware. The firmware binary format - has a field that specifies the actual size of the firmware, but it - might not be possible to read any part of the firmware unless some - local storage is allocated to hold the entire firmware first. - -- CONFIG_SYS_LS_MC_FW_IN_NOR - Specifies that MC firmware is located in NOR flash, mapped as - normal addressable memory via the LBC. CONFIG_SYS_LS_MC_FW_ADDR is the - virtual address in NOR flash. - Freescale Layerscape Debug Server Support: ------------------------------------------- The Freescale Layerscape Debug Server Support supports the loading of diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5f185e1..ada2217 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -595,6 +595,10 @@ config TARGET_PCM052 bool "Support pcm-052" select CPU_V7 +config TARGET_BK4R1 + bool "Support BK4r1" + select CPU_V7 + config ARCH_ZYNQ bool "Xilinx Zynq Platform" select CPU_V7 diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 8f85862..542b897 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -144,4 +144,7 @@ else ALL-y += u-boot.imx endif endif +ifneq ($(CONFIG_VF610),) +ALL-y += u-boot.vyb +endif endif diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index f42eee1..f0f72fa 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -95,6 +95,9 @@ int print_cpuinfo(void) case TI81XX: cpu_s = "TI81XX"; break; + case AM437X: + cpu_s = "AM437X"; + break; default: cpu_s = "Unknown CPU type"; break; @@ -110,7 +113,7 @@ int print_cpuinfo(void) else sec_s = "?"; - printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s); + printf("CPU : %s-%s rev %s\n", cpu_s, sec_s, rev_s); return 0; } diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index 1872c57..658934d 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -19,7 +19,11 @@ ENTRY(lowlevel_init) /* * Setup a temporary stack. Global data is not available yet. */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) + ldr sp, =CONFIG_SPL_STACK +#else ldr sp, =CONFIG_SYS_INIT_SP_ADDR +#endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ #ifdef CONFIG_SPL_DM mov r9, #0 diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 4214ab5..d851b26 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -31,6 +31,10 @@ config MX6UL select ROM_UNIFIED_SECTIONS bool +config MX6ULL + bool + select MX6UL + choice prompt "MX6 board select" optional @@ -133,6 +137,12 @@ config TARGET_MX6UL_14X14_EVK select DM_THERMAL select SUPPORT_SPL +config TARGET_MX6ULL_14X14_EVK + bool "Support mx6ull_14x14_evk" + select MX6ULL + select DM + select DM_THERMAL + config TARGET_NITROGEN6X bool "nitrogen6x" @@ -222,6 +232,7 @@ source "board/freescale/mx6slevk/Kconfig" source "board/freescale/mx6sxsabresd/Kconfig" source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig" +source "board/freescale/mx6ullevk/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 9beb6f0..ae3143c 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -97,7 +97,10 @@ void enable_enet_clk(unsigned char enable) { u32 mask, *addr; - if (is_mx6ul()) { + if (is_mx6ull()) { + mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK; + addr = &imx_ccm->CCGR0; + } else if (is_mx6ul()) { mask = MXC_CCM_CCGR3_ENET_MASK; addr = &imx_ccm->CCGR3; } else { @@ -117,7 +120,7 @@ void enable_uart_clk(unsigned char enable) { u32 mask; - if (is_mx6ul()) + if (is_mx6ul() || is_mx6ull()) mask = MXC_CCM_CCGR5_UART_MASK; else mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK; @@ -168,7 +171,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) reg &= ~mask; __raw_writel(reg, &imx_ccm->CCGR2); } else { - if (is_mx6sx() || is_mx6ul()) { + if (is_mx6sx() || is_mx6ul() || is_mx6ull()) { mask = MXC_CCM_CCGR6_I2C4_MASK; addr = &imx_ccm->CCGR6; } else { @@ -279,7 +282,7 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num) switch (pll) { case PLL_BUS: - if (!is_mx6ul()) { + if (!is_mx6ul() && !is_mx6ull()) { if (pfd_num == 3) { /* No PFD3 on PLL2 */ return 0; @@ -380,7 +383,7 @@ static u32 get_ipg_per_clk(void) reg = __raw_readl(&imx_ccm->cscmr1); if (is_mx6sl() || is_mx6sx() || - is_mx6dqp() || is_mx6ul()) { + is_mx6dqp() || is_mx6ul() || is_mx6ull()) { if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK) return MXC_HCLK; /* OSC 24Mhz */ } @@ -396,7 +399,8 @@ static u32 get_uart_clk(void) u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ reg = __raw_readl(&imx_ccm->cscdr1); - if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) { + if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() || + is_mx6ull()) { if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) freq = MXC_HCLK; } @@ -415,7 +419,8 @@ static u32 get_cspi_clk(void) cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; - if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) { + if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() || + is_mx6ull()) { if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK) return MXC_HCLK / (cspi_podf + 1); } @@ -477,7 +482,7 @@ static u32 get_mmdc_ch0_clk(void) u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div; - if (is_mx6sx() || is_mx6ul() || is_mx6sl()) { + if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) { podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET; if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) { @@ -615,7 +620,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq) debug("mxs_set_lcdclk, freq = %dKHz\n", freq); - if (!is_mx6sx() && !is_mx6ul()) { + if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull()) { debug("This chip not support lcd!\n"); return; } @@ -749,7 +754,7 @@ int enable_lcdif_clock(u32 base_addr) MXC_CCM_CCGR3_DISP_AXI_MASK) : (MXC_CCM_CCGR3_LCDIF1_PIX_MASK | MXC_CCM_CCGR3_DISP_AXI_MASK); - } else if (is_mx6ul()) { + } else if (is_mx6ul() || is_mx6ull()) { if (base_addr != LCDIF1_BASE_ADDR) { puts("Wrong LCD interface!\n"); return -EINVAL; @@ -847,7 +852,7 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); } else if (fec_id == 1) { /* Only i.MX6SX/UL support ENET2 */ - if (!(is_mx6sx() || is_mx6ul())) + if (!(is_mx6sx() || is_mx6ul() || is_mx6ull())) return -EINVAL; reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT; reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); @@ -1069,17 +1074,27 @@ void hab_caam_clock_enable(unsigned char enable) { u32 reg; - /* CG4 ~ CG6, CAAM clocks */ - reg = __raw_readl(&imx_ccm->CCGR0); - if (enable) - reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | - MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | - MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); - else - reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | - MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | - MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); - __raw_writel(reg, &imx_ccm->CCGR0); + if (is_mx6ull()) { + /* CG5, DCP clock */ + reg = __raw_readl(&imx_ccm->CCGR0); + if (enable) + reg |= MXC_CCM_CCGR0_DCP_CLK_MASK; + else + reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK; + __raw_writel(reg, &imx_ccm->CCGR0); + } else { + /* CG4 ~ CG6, CAAM clocks */ + reg = __raw_readl(&imx_ccm->CCGR0); + if (enable) + reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | + MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | + MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); + else + reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK | + MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | + MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK); + __raw_writel(reg, &imx_ccm->CCGR0); + } /* EMI slow clk */ reg = __raw_readl(&imx_ccm->CCGR6); diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 5b2a051..7b53bfd 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -126,7 +126,7 @@ u32 get_cpu_speed_grade_hz(void) val >>= OCOTP_CFG3_SPEED_SHIFT; val &= 0x3; - if (is_mx6ul()) { + if (is_mx6ul() || is_mx6ull()) { if (val == OCOTP_CFG3_SPEED_528MHZ) return 528000000; else if (val == OCOTP_CFG3_SPEED_696MHZ) @@ -293,7 +293,7 @@ static void clear_mmdc_ch_mask(void) reg = readl(&mxc_ccm->ccdr); /* Clear MMDC channel mask */ - if (is_mx6sx() || is_mx6ul() || is_mx6sl()) + if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); else reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); @@ -314,6 +314,12 @@ static void init_bandgap(void) * be set. */ writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); + /* + * On i.MX6ULL, the LDO 1.2V bandgap voltage is 30mV higher. so set + * VBGADJ bits to 2b'110 to adjust it. + */ + if (is_mx6ull()) + writel(BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ, &anatop->ana_misc0_set); } @@ -343,7 +349,7 @@ int arch_cpu_init(void) */ init_bandgap(); - if (!IS_ENABLED(CONFIG_MX6UL)) { + if (!is_mx6ul() && !is_mx6ull()) { /* * When low freq boot is enabled, ROM will not set AHB * freq, so we need to ensure AHB freq is 132MHz in such @@ -356,14 +362,41 @@ int arch_cpu_init(void) set_ahb_rate(132000000); } - if (IS_ENABLED(CONFIG_MX6UL) && is_soc_rev(CHIP_REV_1_0) == 0) { + if (is_mx6ul()) { + if (is_soc_rev(CHIP_REV_1_0) == 0) { + /* + * According to the design team's requirement on + * i.MX6UL,the PMIC_STBY_REQ PAD should be configured + * as open drain 100K (0x0000b8a0). + * Only exists on TO1.0 + */ + writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c); + } else { + /* + * From TO1.1, SNVS adds internal pull up control + * for POR_B, the register filed is GPBIT[1:0], + * after system boot up, it can be set to 2b'01 + * to disable internal pull up.It can save about + * 30uA power in SNVS mode. + */ + writel((readl(MX6UL_SNVS_LP_BASE_ADDR + 0x10) & + (~0x1400)) | 0x400, + MX6UL_SNVS_LP_BASE_ADDR + 0x10); + } + } + + if (is_mx6ull()) { /* - * According to the design team's requirement on i.MX6UL, - * the PMIC_STBY_REQ PAD should be configured as open - * drain 100K (0x0000b8a0). - * Only exists on TO1.0 + * GPBIT[1:0] is suggested to set to 2'b11: + * 2'b00 : always PUP100K + * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL + * 2'b10 : always disable PUP100K + * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL + * register offset is different from i.MX6UL, since + * i.MX6UL is fixed by ECO. */ - writel(0x0000b8a0, IOMUXC_BASE_ADDR + 0x29c); + writel(readl(MX6UL_SNVS_LP_BASE_ADDR) | + 0x3, MX6UL_SNVS_LP_BASE_ADDR); } /* Set perclk to source from OSC 24MHz */ @@ -459,7 +492,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) struct fuse_bank4_regs *fuse = (struct fuse_bank4_regs *)bank->fuse_regs; - if ((is_mx6sx() || is_mx6ul()) && dev_id == 1) { + if ((is_mx6sx() || is_mx6ul() || is_mx6ull()) && dev_id == 1) { u32 value = readl(&fuse->mac_addr2); mac[0] = value >> 24 ; mac[1] = value >> 16 ; @@ -494,7 +527,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) const struct boot_mode soc_boot_modes[] = { {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)}, /* reserved value should start rom usb */ - {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)}, + {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)}, @@ -523,7 +556,7 @@ void s_init(void) u32 mask528; u32 reg, periph1, periph2; - if (is_mx6sx() || is_mx6ul()) + if (is_mx6sx() || is_mx6ul() || is_mx6ull()) return; /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 66a3b3d..8ce12c8 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -24,6 +24,30 @@ ENTRY(save_boot_params) str r0, [r1] b save_boot_params_ret ENDPROC(save_boot_params) + +#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE) +ENTRY(switch_to_hypervisor) + +/* + * Switch to hypervisor mode + */ + adr r0, save_sp + str sp, [r0] + adr r1, restore_from_hyp + ldr r0, =0x102 + b omap_smc1 +restore_from_hyp: + adr r0, save_sp + ldr sp, [r0] + MRC p15, 4, R0, c1, c0, 0 + ldr r1, =0X1004 @Set cache enable bits for hypervisor mode + orr r0, r0, r1 + MCR p15, 4, R0, c1, c0, 0 + b switch_to_hypervisor_ret +save_sp: + .word 0x0 +ENDPROC(switch_to_hypervisor) +#endif #endif ENTRY(omap_smc1) diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c index 579bebf..b37163a 100644 --- a/arch/arm/cpu/armv7/omap-common/omap-cache.c +++ b/arch/arm/cpu/armv7/omap-common/omap-cache.c @@ -17,7 +17,28 @@ DECLARE_GLOBAL_DATA_PTR; -#define ARMV7_DCACHE_WRITEBACK 0xe +/* + * Without LPAE short descriptors are used + * Set C - Cache Bit3 + * Set B - Buffer Bit2 + * The last 2 bits set to 0b10 + * Do Not set XN bit4 + * So value is 0xe + * + * With LPAE cache configuration happens via MAIR0 register + * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF. + * 0xFF maps to Cache writeback with Read and Write Allocate set + * The bits[1:0] should have the value 0b01 for the first level + * descriptor. + * So the value is 0xd + */ + +#ifdef CONFIG_ARMV7_LPAE +#define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC +#else +#define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK +#endif + #define ARMV7_DOMAIN_CLIENT 1 #define ARMV7_DOMAIN_MASK (0x3 << 0) @@ -32,13 +53,13 @@ void dram_bank_mmu_setup(int bank) bd_t *bd = gd->bd; int i; - u32 start = bd->bi_dram[bank].start >> 20; - u32 size = bd->bi_dram[bank].size >> 20; + u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; + u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; u32 end = start + size; debug("%s: bank: %d\n", __func__, bank); for (i = start; i < end; i++) - set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); + set_section_dcache(i, ARMV7_DCACHE_POLICY); } void arm_init_domains(void) diff --git a/arch/arm/cpu/armv7/omap4/Kconfig b/arch/arm/cpu/armv7/omap4/Kconfig index c3dc95f..2091dd7 100644 --- a/arch/arm/cpu/armv7/omap4/Kconfig +++ b/arch/arm/cpu/armv7/omap4/Kconfig @@ -33,6 +33,9 @@ config SPL_POWER_SUPPORT config SPL_SERIAL_SUPPORT default y +config SPL_DISPLAY_PRINT + default y + choice prompt "OMAP4 board select" optional diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index a947ba4..22259dc 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -33,6 +33,9 @@ config SPL_POWER_SUPPORT config SPL_SERIAL_SUPPORT default y +config SPL_DISPLAY_PRINT + default y + choice prompt "OMAP5 board select" optional diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 691e5d3..7eee54b 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -17,6 +17,7 @@ #include <config.h> #include <asm/system.h> #include <linux/linkage.h> +#include <asm/armv7.h> /************************************************************************* * @@ -30,11 +31,24 @@ .globl reset .globl save_boot_params_ret +#ifdef CONFIG_ARMV7_LPAE + .global switch_to_hypervisor_ret +#endif reset: /* Allow the board to save important registers */ b save_boot_params save_boot_params_ret: +#ifdef CONFIG_ARMV7_LPAE +/* + * check for Hypervisor support + */ + mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 + and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits + cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT) + beq switch_to_hypervisor +switch_to_hypervisor_ret: +#endif /* * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode, * except if in HYP mode already @@ -103,6 +117,13 @@ ENTRY(save_boot_params) ENDPROC(save_boot_params) .weak save_boot_params +#ifdef CONFIG_ARMV7_LPAE +ENTRY(switch_to_hypervisor) + b switch_to_hypervisor_ret +ENDPROC(switch_to_hypervisor) + .weak switch_to_hypervisor +#endif + /************************************************************************* * * cpu_init_cp15 diff --git a/arch/arm/cpu/armv7/vf610/Makefile b/arch/arm/cpu/armv7/vf610/Makefile index 68cb756..2945377 100644 --- a/arch/arm/cpu/armv7/vf610/Makefile +++ b/arch/arm/cpu/armv7/vf610/Makefile @@ -6,3 +6,8 @@ obj-y += generic.o obj-y += timer.o + +MKIMAGEFLAGS_u-boot.vyb = -T vybridimage + +u-boot.vyb: u-boot.imx + $(call if_changed,mkimage) diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index 08b9ef4..50eb0c6 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -322,7 +322,7 @@ int arch_misc_init(void) { char soc[6]; - strcat(soc, "vf"); + strcpy(soc, "vf"); strcat(soc, soc_type); setenv("soc", soc); diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c index e21e199..2ddd67e 100644 --- a/arch/arm/cpu/armv8/sec_firmware.c +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -19,12 +19,22 @@ extern void c_runtime_cpu_setup(void); #define SEC_FIRMWARE_LOADED 0x1 #define SEC_FIRMWARE_RUNNING 0x2 #define SEC_FIRMWARE_ADDR_MASK (~0x3) - /* - * Secure firmware load addr - * Flags used: 0x1 secure firmware has been loaded to secure memory - * 0x2 secure firmware is running - */ - phys_addr_t sec_firmware_addr; +/* + * Secure firmware load addr + * Flags used: 0x1 secure firmware has been loaded to secure memory + * 0x2 secure firmware is running + */ +phys_addr_t sec_firmware_addr; + +#ifndef SEC_FIRMWARE_FIT_IMAGE +#define SEC_FIRMWARE_FIT_IMAGE "firmware" +#endif +#ifndef SEC_FIRMEWARE_FIT_CNF_NAME +#define SEC_FIRMEWARE_FIT_CNF_NAME "config@1" +#endif +#ifndef SEC_FIRMWARE_TARGET_EL +#define SEC_FIRMWARE_TARGET_EL 2 +#endif static int sec_firmware_get_data(const void *sec_firmware_img, const void **data, size_t *size) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 032c5ae..8458f6b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -133,7 +133,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_sr1500.dtb \ socfpga_cyclone5_vining_fpga.dtb -dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb +dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ + dra72-evm-revc.dtb dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ am572x-idk.dtb dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb @@ -278,7 +279,12 @@ dtb-$(CONFIG_MACH_SUN9I) += \ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ vf610-colibri.dtb \ vf610-twr.dtb \ - pcm052.dtb + pcm052.dtb \ + bk4r1.dtb + +dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb + +dtb-$(CONFIG_MX7) += imx7-colibri.dtb dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2l-evm.dtb \ diff --git a/arch/arm/dts/bk4r1.dts b/arch/arm/dts/bk4r1.dts new file mode 100644 index 0000000..197e5ab --- /dev/null +++ b/arch/arm/dts/bk4r1.dts @@ -0,0 +1,48 @@ +/* + * Copyright 2016 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ + +/dts-v1/; +#include "vf.dtsi" + +/ { + model = "Phytec phyCORE-Vybrid"; + compatible = "phytec,pcm052", "fsl,vf610"; + + chosen { + stdout-path = &uart1; + }; + + aliases { + spi0 = &qspi0; + }; + +}; + +&uart1 { + status = "okay"; +}; + +&qspi0 { + bus-num = <0>; + num-cs = <2>; + status = "okay"; + + qflash0: spi_flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <108000000>; + reg = <0>; + }; + + qflash1: spi_flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <66000000>; + reg = <1>; + }; +}; diff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi new file mode 100644 index 0000000..b0993e5 --- /dev/null +++ b/arch/arm/dts/dra72-evm-common.dtsi @@ -0,0 +1,513 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra72x.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; + + chosen { + stdout-path = &uart1; + tick-timer = &timer2; + }; + + aliases { + display0 = &hdmi0; + }; + + evm_3v3: fixedregulator-evm_3v3 { + compatible = "regulator-fixed"; + regulator-name = "evm_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; + }; + + extcon_usb2: extcon_usb2 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder { + compatible = "ti,tpd12s015"; + + gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ + <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + +&dra7_pmx_core { + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + dcan1_pins_default: dcan1_pins_default { + pinctrl-single,pins = < + 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ + 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ + >; + }; + + dcan1_pins_sleep: dcan1_pins_sleep { + pinctrl-single,pins = < + 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ + 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ + >; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps65917: tps65917@58 { + compatible = "ti,tps65917"; + reg = <0x58>; + + interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ + interrupt-controller; + #interrupt-cells = <2>; + + ti,system-power-controller; + + tps65917_pmic { + compatible = "ti,tps65917-pmic"; + + tps65917_regulators: regulators { + smps1_reg: smps1 { + /* VDD_MPU */ + regulator-name = "smps1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps2_reg: smps2 { + /* VDD_CORE */ + regulator-name = "smps2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1060000>; + regulator-boot-on; + regulator-always-on; + }; + + smps3_reg: smps3 { + /* VDD_GPU IVA DSPEVE */ + regulator-name = "smps3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + smps4_reg: smps4 { + /* VDDS1V8 */ + regulator-name = "smps4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps5_reg: smps5 { + /* VDD_DDR */ + regulator-name = "smps5"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + /* LDO1_OUT --> SDIO */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-bypass; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHY */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + /* VDDA_1V8_PLL */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldo4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + }; + }; + + tps65917_power_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps65917>; + interrupts = <1 IRQ_TYPE_NONE>; + wakeup-source; + ti,palmas-long-press-seconds = <6>; + }; + }; + + pcf_gpio_21: gpio@21 { + compatible = "ti,pcf8575"; + u-boot,i2c-offset-len = <0>; + reg = <0x21>; + lines-initial-states = <0x1408>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + pcf_hdmi: pcf8575@26 { + compatible = "nxp,pcf8575"; + u-boot,i2c-offset-len = <0>; + reg = <0x26>; + gpio-controller; + #gpio-cells = <2>; + /* + * initial state is used here to keep the mdio interface + * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and + * VIN2_S0 driven high otherwise Ethernet stops working + * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 + */ + lines-initial-states = <0x0f2b>; + + p1 { + /* vin6_sel_s0: high: VIN6, low: audio */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "vin6_sel_s0"; + }; + }; +}; + +&uart1 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3e0>; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + /* + * For the existing IOdelay configuration via U-Boot we don't + * support NAND on dra72-evm. Keep it disabled. Enabling it + * requires a different configuration by U-Boot. + */ + status = "disabled"; + ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ + nand@0,0 { + /* To use NAND, DIP switch SW5 must be set like so: + * SW5.1 (NAND_SELn) = ON (LOW) + * SW5.9 (GPMC_WPN) = OFF (HIGH) + */ + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ /* device IO registers */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <80>; + gpmc,cs-wr-off-ns = <80>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <60>; + gpmc,adv-wr-off-ns = <60>; + gpmc,we-on-ns = <10>; + gpmc,we-off-ns = <50>; + gpmc,oe-on-ns = <4>; + gpmc,oe-off-ns = <40>; + gpmc,access-ns = <40>; + gpmc,wr-access-ns = <80>; + gpmc,rd-cycle-ns = <80>; + gpmc,wr-cycle-ns = <80>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x000020000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00020000 0x00020000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00040000 0x00020000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x00060000 0x00020000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00080000 0x00040000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x000c0000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x001c0000 0x00020000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x001e0000 0x00020000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00200000 0x00800000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x0f600000>; + }; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldo4_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldo4_reg>; +}; + +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&usb1 { + dr_mode = "otg"; +}; + +&usb2 { + dr_mode = "host"; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + vmmc_aux-supply = <&ldo1_reg>; + bus-width = <4>; + /* + * SDCD signal is not being used here - using the fact that GPIO mode + * is a viable alternative + */ + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; + max-frequency = <192000000>; +}; + +&mmc2 { + /* SW5-3 in ON position */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; + + vmmc-supply = <&evm_3v3>; + bus-width = <8>; + ti,non-removable; + max-frequency = <192000000>; +}; + +&mac { + status = "okay"; +}; + +&dcan1 { + status = "ok"; +}; + +&qspi { + status = "okay"; + + spi-max-frequency = <76800000>; + m25p80@0 { + compatible = "s25fl256s1", "spi-flash"; + spi-max-frequency = <64000000>; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first four physical blocks + * for a valid file to boot and the flash here is + * 64KiB block size. + */ + partition@0 { + label = "QSPI.SPL"; + reg = <0x00000000 0x000010000>; + }; + partition@1 { + label = "QSPI.SPL.backup1"; + reg = <0x00010000 0x00010000>; + }; + partition@2 { + label = "QSPI.SPL.backup2"; + reg = <0x00020000 0x00010000>; + }; + partition@3 { + label = "QSPI.SPL.backup3"; + reg = <0x00030000 0x00010000>; + }; + partition@4 { + label = "QSPI.u-boot"; + reg = <0x00040000 0x00100000>; + }; + partition@5 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00140000 0x00080000>; + }; + partition@6 { + label = "QSPI.u-boot-env"; + reg = <0x001c0000 0x00010000>; + }; + partition@7 { + label = "QSPI.u-boot-env.backup1"; + reg = <0x001d0000 0x0010000>; + }; + partition@8 { + label = "QSPI.kernel"; + reg = <0x001e0000 0x0800000>; + }; + partition@9 { + label = "QSPI.file-system"; + reg = <0x009e0000 0x01620000>; + }; + }; +}; + +&dss { + status = "ok"; + + vdda_video-supply = <&ldo5_reg>; +}; + +&hdmi { + status = "ok"; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; diff --git a/arch/arm/dts/dra72-evm-revc.dts b/arch/arm/dts/dra72-evm-revc.dts new file mode 100644 index 0000000..0f8a7ef --- /dev/null +++ b/arch/arm/dts/dra72-evm-revc.dts @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "dra72-evm-common.dtsi" +#include <dt-bindings/net/ti-dp83867.h> + +/ { + model = "TI DRA722 Rev C EVM"; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ + }; +}; + +&tps65917_regulators { + ldo2_reg: ldo2 { + /* LDO2_OUT --> VDDA_1V8_PHY2 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hdmi { + vdda_video-supply = <&ldo2_reg>; +}; + +&mac { + mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, + <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ + <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ + dual_emac; +}; + +&cpsw_emac0 { + phy-handle = <&dp83867_0>; + phy-mode = "rgmii-id"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy-handle = <&dp83867_1>; + phy-mode = "rgmii-id"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + dp83867_0: ethernet-phy@2 { + reg = <2>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + ti,min-output-imepdance; + }; + + dp83867_1: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + ti,min-output-imepdance; + }; +}; diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts index e7c5db2..f81f918 100644 --- a/arch/arm/dts/dra72-evm.dts +++ b/arch/arm/dts/dra72-evm.dts @@ -5,674 +5,24 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -/dts-v1/; - -#include "dra72x.dtsi" -#include <dt-bindings/gpio/gpio.h> +#include <dra72-evm-common.dtsi> / { model = "TI DRA722"; compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; - chosen { - stdout-path = &uart1; - tick-timer = &timer2; - }; - memory { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1024 MB */ }; - - aliases { - display0 = &hdmi0; - }; - - evm_3v3: fixedregulator-evm_3v3 { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - evm_3v3_sd: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3_sd"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb1: extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb2: extcon_usb2 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; - - gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ - <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; -}; - -&dra7_pmx_core { - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - 0x2b4 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ - 0x2b8 (PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ - >; - }; - - nand_default: nand_default { - pinctrl-single,pins = < - 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ - 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ - 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ - 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ - 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ - 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ - 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ - 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ - 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ - 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ - 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ - 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ - 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ - 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ - 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ - 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ - 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ - 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ - 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ - 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ - 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ - 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - usb2_pins: pinmux_usb2_pins { - pinctrl-single,pins = < - 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ - >; - }; - - tps65917_pins_default: tps65917_pins_default { - pinctrl-single,pins = < - 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ - >; - }; - - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ - 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - dcan1_pins_default: dcan1_pins_default { - pinctrl-single,pins = < - 0x3d0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ - 0x418 (PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ - >; - }; - - dcan1_pins_sleep: dcan1_pins_sleep { - pinctrl-single,pins = < - 0x3d0 (MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ - 0x418 (MUX_MODE15 | PULL_UP) /* wakeup0.off */ - >; - }; - - qspi1_pins: pinmux_qspi1_pins { - pinctrl-single,pins = < - 0x74 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ - 0x78 (PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ - 0x7c (PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ - 0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ - 0x84 (PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ - 0x88 (PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ - 0xb8 (PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ - >; - }; - - hdmi_pins: pinmux_hdmi_pins { - pinctrl-single,pins = < - 0x408 (PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ - 0x40c (PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - 0x3b8 (PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ - >; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - - tps65917: tps65917@58 { - compatible = "ti,tps65917"; - reg = <0x58>; - - pinctrl-names = "default"; - pinctrl-0 = <&tps65917_pins_default>; - - interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ - interrupt-controller; - #interrupt-cells = <2>; - - ti,system-power-controller; - - tps65917_pmic { - compatible = "ti,tps65917-pmic"; - - regulators { - smps1_reg: smps1 { - /* VDD_MPU */ - regulator-name = "smps1"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps2_reg: smps2 { - /* VDD_CORE */ - regulator-name = "smps2"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1060000>; - regulator-boot-on; - regulator-always-on; - }; - - smps3_reg: smps3 { - /* VDD_GPU IVA DSPEVE */ - regulator-name = "smps3"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - - smps4_reg: smps4 { - /* VDDS1V8 */ - regulator-name = "smps4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps5_reg: smps5 { - /* VDD_DDR */ - regulator-name = "smps5"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - /* LDO1_OUT --> SDIO */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - ldo2_reg: ldo2 { - /* LDO2_OUT --> TP1017 (UNUSED) */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHY */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PLL */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldo4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; - - tps65917_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps65917>; - interrupts = <1 IRQ_TYPE_NONE>; - wakeup-source; - ti,palmas-long-press-seconds = <6>; - }; - }; - - pcf_gpio_21: gpio@21 { - compatible = "ti,pcf8575"; - reg = <0x21>; - lines-initial-states = <0x1408>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - u-boot,i2c-offset-len = <0>; - }; }; -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - clock-frequency = <400000>; - - pcf_hdmi: pcf8575@26 { - compatible = "nxp,pcf8575"; - reg = <0x26>; - gpio-controller; - #gpio-cells = <2>; - /* - * initial state is used here to keep the mdio interface - * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and - * VIN2_S0 driven high otherwise Ethernet stops working - * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 - */ - lines-initial-states = <0x0f2b>; - u-boot,i2c-offset-len = <0>; - }; -}; - -&uart1 { - status = "okay"; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_default>; - ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ - nand@0,0 { - /* To use NAND, DIP switch SW5 must be set like so: - * SW5.1 (NAND_SELn) = ON (LOW) - * SW5.9 (GPMC_WPN) = OFF (HIGH) - */ - reg = <0 0 4>; /* device IO registers */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <80>; - gpmc,cs-wr-off-ns = <80>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <60>; - gpmc,adv-wr-off-ns = <60>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <50>; - gpmc,oe-on-ns = <4>; - gpmc,oe-off-ns = <40>; - gpmc,access-ns = <40>; - gpmc,wr-access-ns = <80>; - gpmc,rd-cycle-ns = <80>; - gpmc,wr-cycle-ns = <80>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wait-monitoring-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00020000 0x00020000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00040000 0x00020000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x00060000 0x00020000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00080000 0x00040000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x000c0000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x001c0000 0x00020000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x001e0000 0x00020000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00200000 0x00800000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x0f600000>; - }; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldo4_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldo4_reg>; -}; - -&omap_dwc3_1 { - extcon = <&extcon_usb1>; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb1 { - dr_mode = "peripheral"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; -}; - -&usb2 { - dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pins>; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; - - vmmc_aux-supply = <&ldo1_reg>; - vmmc-supply = <&evm_3v3_sd>; - bus-width = <4>; - /* - * SDCD signal is not being used here - using the fact that GPIO mode - * is a viable alternative - */ - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; -}; - -&mmc2 { - /* SW5-3 in ON position */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_default>; - - vmmc-supply = <&evm_3v3>; - bus-width = <8>; - ti,non-removable; -}; - -&dra7_pmx_core { - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 2 */ - 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ - 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ - 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ - 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ - 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ - 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ - 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ - 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ - 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ - 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ - 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ - 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ - >; - - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 2 */ - 0x198 (MUX_MODE15) - 0x19c (MUX_MODE15) - 0x1a0 (MUX_MODE15) - 0x1a4 (MUX_MODE15) - 0x1a8 (MUX_MODE15) - 0x1ac (MUX_MODE15) - 0x1b0 (MUX_MODE15) - 0x1b4 (MUX_MODE15) - 0x1b8 (MUX_MODE15) - 0x1bc (MUX_MODE15) - 0x1c0 (MUX_MODE15) - 0x1c4 (MUX_MODE15) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ - 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - 0x23c (MUX_MODE15) - 0x240 (MUX_MODE15) - >; - }; -}; - -&mac { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>; -}; &cpsw_emac0 { phy_id = <&davinci_mdio>, <3>; phy-mode = "rgmii"; }; -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; -}; - -&dcan1 { - status = "ok"; - pinctrl-names = "default", "sleep", "active"; - pinctrl-0 = <&dcan1_pins_sleep>; - pinctrl-1 = <&dcan1_pins_sleep>; - pinctrl-2 = <&dcan1_pins_default>; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi1_pins>; - - spi-max-frequency = <76800000>; - m25p80@0 { - compatible = "s25fl256s1","spi-flash"; - spi-max-frequency = <64000000>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first four physical blocks - * for a valid file to boot and the flash here is - * 64KiB block size. - */ - partition@0 { - label = "QSPI.SPL"; - reg = <0x00000000 0x000010000>; - }; - partition@1 { - label = "QSPI.SPL.backup1"; - reg = <0x00010000 0x00010000>; - }; - partition@2 { - label = "QSPI.SPL.backup2"; - reg = <0x00020000 0x00010000>; - }; - partition@3 { - label = "QSPI.SPL.backup3"; - reg = <0x00030000 0x00010000>; - }; - partition@4 { - label = "QSPI.u-boot"; - reg = <0x00040000 0x00100000>; - }; - partition@5 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00140000 0x00080000>; - }; - partition@6 { - label = "QSPI.u-boot-env"; - reg = <0x001c0000 0x00010000>; - }; - partition@7 { - label = "QSPI.u-boot-env.backup1"; - reg = <0x001d0000 0x0010000>; - }; - partition@8 { - label = "QSPI.kernel"; - reg = <0x001e0000 0x0800000>; - }; - partition@9 { - label = "QSPI.file-system"; - reg = <0x009e0000 0x01620000>; - }; - }; -}; - &dss { status = "ok"; @@ -680,15 +30,9 @@ }; &hdmi { - status = "ok"; vdda-supply = <&ldo3_reg>; +}; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; +&mac { + mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/dts/imx6ul-pinfunc.h b/arch/arm/dts/imx6ul-pinfunc.h new file mode 100644 index 0000000..0034eeb --- /dev/null +++ b/arch/arm/dts/imx6ul-pinfunc.h @@ -0,0 +1,938 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DTS_IMX6UL_PINFUNC_H +#define __DTS_IMX6UL_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0 +#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0 + +#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003c 0x02c8 0x0000 5 0 +#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02cc 0x0000 5 0 + +#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02d0 0x0000 0 0 +#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02d0 0x05a0 1 0 +#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02d0 0x0000 2 0 +#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0 +#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0 +#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0 +#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0000 6 0 +#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0 +#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0 +#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x0000 2 0 +#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0 +#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0 +#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0 +#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0000 6 0 +#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0 +#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0 +#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0 +#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004c 0x02d8 0x05fc 2 0 +#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004c 0x02d8 0x0000 3 0 +#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004c 0x02d8 0x0000 4 0 +#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004c 0x02d8 0x0000 5 0 +#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004c 0x02d8 0x0000 6 0 +#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004c 0x02d8 0x0000 8 0 +#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02dc 0x0000 0 0 +#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02dc 0x0000 1 0 +#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02dc 0x05f8 2 0 +#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02dc 0x0000 4 0 +#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02dc 0x0000 5 0 +#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02dc 0x0000 6 0 +#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02dc 0x0000 8 0 +#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02e0 0x0000 0 0 +#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02e0 0x0000 1 0 +#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x05f4 2 0 +#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0 +#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0 +#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0 +#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0 +#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0 +#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0 +#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0 +#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0 +#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1 +#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0 +#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005c 0x02e8 0x04b8 2 0 +#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005c 0x02e8 0x0574 3 0 +#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005c 0x02e8 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005c 0x02e8 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005c 0x02e8 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005c 0x02e8 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005c 0x02e8 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02ec 0x05b0 0 1 +#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02ec 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02ec 0x0664 2 0 +#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02ec 0x057c 3 0 +#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02ec 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02ec 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02ec 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02ec 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02ec 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02f0 0x05a4 0 0 +#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02f0 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02f0 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0 +#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0 +#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0 +#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1 +#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0 +#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0 +#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK 0x0068 0x02f4 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1 +#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1 +#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x006c 0x02f8 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x006c 0x02f8 0x0644 8 2 +#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x0070 0x02fc 0x057c 0 1 +#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x0070 0x02fc 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x0070 0x02fc 0x04bc 2 0 +#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 0x0070 0x02fc 0x0530 3 0 +#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x0070 0x02fc 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x0070 0x02fc 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02fc 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0070 0x02fc 0x0644 8 3 +#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x0070 0x02fc 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x0074 0x0300 0x0578 0 0 +#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x0074 0x0300 0x0580 1 0 +#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 0x0074 0x0300 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 0x0074 0x0300 0x0000 3 0 +#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 0x0074 0x0300 0x069c 4 0 +#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0074 0x0300 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 0x0074 0x0300 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 0x0074 0x0300 0x0000 7 0 +#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 0x0074 0x0300 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 0x0074 0x0300 0x0620 8 0 +#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0078 0x0304 0x0000 0 0 +#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0078 0x0304 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE 0x0078 0x0304 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 0x0078 0x0304 0x0528 3 0 +#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 0x0078 0x0304 0x0674 4 1 +#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0078 0x0304 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO07__CCM_STOP 0x0078 0x0304 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x0078 0x0304 0x0620 8 1 +#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 0x0078 0x0304 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x007c 0x0308 0x0000 0 0 +#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x007c 0x0308 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x007c 0x0308 0x0000 2 0 +#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 0x007c 0x0308 0x052c 3 1 +#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x007c 0x0308 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x007c 0x0308 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x007c 0x0308 0x04c0 6 1 +#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x007c 0x0308 0x0640 8 1 +#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 0x007c 0x0308 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x0080 0x030c 0x0000 0 0 +#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x0080 0x030c 0x0000 1 0 +#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x0080 0x030c 0x0618 2 0 +#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 0x0080 0x030c 0x0524 3 1 +#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 0x0080 0x030c 0x0000 4 0 +#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0080 0x030c 0x0000 5 0 +#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 0x0080 0x030c 0x0000 6 0 +#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0080 0x030c 0x0000 8 0 +#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 0x0080 0x030c 0x0640 8 2 +#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0084 0x0310 0x0000 0 0 +#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x0084 0x0310 0x0624 0 2 +#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 0x0084 0x0310 0x0000 1 0 +#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x0084 0x0310 0x05b4 2 0 +#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 0x0084 0x0310 0x04c4 3 1 +#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 0x0084 0x0310 0x0000 4 0 +#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 0x0084 0x0310 0x0000 5 0 +#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 0x0084 0x0310 0x0000 8 0 +#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0088 0x0314 0x0624 0 3 +#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0088 0x0314 0x0000 0 0 +#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x0088 0x0314 0x0000 1 0 +#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x0088 0x0314 0x05b8 2 0 +#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 0x0088 0x0314 0x04c8 3 1 +#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 0x0088 0x0314 0x0594 4 0 +#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 0x0088 0x0314 0x0000 5 0 +#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 0x0088 0x0314 0x0618 8 1 +#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x008c 0x0318 0x0000 0 0 +#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x008c 0x0318 0x0620 0 2 +#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x008c 0x0318 0x0000 1 0 +#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 0x008c 0x0318 0x066c 2 1 +#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 0x008c 0x0318 0x04d8 3 0 +#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN 0x008c 0x0318 0x0000 4 0 +#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x008c 0x0318 0x0000 5 0 +#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 0x008c 0x0318 0x069c 8 1 +#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0090 0x031c 0x0620 0 3 +#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x0090 0x031c 0x0000 0 0 +#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x0090 0x031c 0x0000 1 0 +#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x0090 0x031c 0x0668 2 1 +#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 0x0090 0x031c 0x04cc 3 1 +#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT 0x0090 0x031c 0x0000 4 0 +#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0090 0x031c 0x0000 5 0 +#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 0x0090 0x031c 0x0674 8 2 +#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0094 0x0320 0x0000 0 0 +#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0094 0x0320 0x062c 0 0 +#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x0094 0x0320 0x0000 1 0 +#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x0094 0x0320 0x05bc 2 0 +#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04dc 3 0 +#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1 +#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0 +#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0000 8 0 +#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1 +#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0 +#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0 +#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x0098 0x0324 0x05c0 2 0 +#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 0x0098 0x0324 0x04e0 3 0 +#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 0x0098 0x0324 0x0590 4 0 +#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x0098 0x0324 0x0000 5 0 +#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 0x0098 0x0324 0x0000 7 0 +#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x0098 0x0324 0x0554 8 0 +#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x009c 0x0328 0x0000 0 0 +#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x009c 0x0328 0x0628 0 0 +#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x009c 0x0328 0x0000 1 0 +#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x009c 0x0328 0x0000 2 0 +#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 0x009c 0x0328 0x04e4 3 0 +#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 0x009c 0x0328 0x0000 4 0 +#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x009c 0x0328 0x0000 5 0 +#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 0x009c 0x0328 0x0000 7 0 +#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x009c 0x0328 0x055c 8 0 +#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x00a0 0x032c 0x0628 0 1 +#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x00a0 0x032c 0x0000 0 0 +#define MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x00a0 0x032c 0x0000 1 0 +#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x00a0 0x032c 0x0588 2 0 +#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 0x00a0 0x032c 0x04e8 3 0 +#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 0x00a0 0x032c 0x0000 4 0 +#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00a0 0x032c 0x0000 5 0 +#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 0x00a0 0x032c 0x0000 7 0 +#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x00a0 0x032c 0x0558 8 0 +#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00a4 0x0330 0x0000 0 0 +#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0 +#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0 +#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0 +#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x0000 3 0 +#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0 +#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2 +#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0 +#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 0x00a4 0x0330 0x0000 7 0 +#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x00a4 0x0330 0x04b8 8 1 +#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00a8 0x0334 0x0634 0 1 +#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0 +#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0 +#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0 +#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x0000 3 0 +#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3 +#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0 +#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0 +#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 0x00a8 0x0334 0x0000 8 0 +#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00ac 0x0338 0x0000 0 0 +#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0 +#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0 +#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0 +#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x0000 3 0 +#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0 +#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0 +#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0 +#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00b0 0x033c 0x0630 0 1 +#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0 +#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0 +#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0 +#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x0000 3 0 +#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0 +#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0 +#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0 +#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00b4 0x0340 0x0000 0 0 +#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0 +#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0 +#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1 +#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x0000 3 0 +#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0 +#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0 +#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0544 8 1 +#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00b8 0x0344 0x063c 0 1 +#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0 +#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0 +#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2 +#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x0000 3 0 +#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0 +#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0 +#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0000 8 0 +#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0 +#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x054c 8 0 +#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0 +#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4 +#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0 +#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2 +#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x0000 3 0 +#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0 +#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5 +#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0 +#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0 +#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2 +#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0000 3 0 +#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0 +#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0 +#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0548 8 1 +#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00c4 0x0350 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0 +#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0 +#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0 +#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1 +#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1 +#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0 +#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3 +#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0 +#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4 +#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1 +#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2 +#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1 +#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3 +#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0 +#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0 +#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0 +#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0 +#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0 +#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0 +#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x0000 3 0 +#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2 +#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0 +#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0 +#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 0x00dc 0x0368 0x0594 8 1 +#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00e0 0x036c 0x0000 0 0 +#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1 +#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0 +#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0 +#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0000 3 0 +#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0 +#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0 +#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0 +#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 0x00e0 0x036c 0x0590 8 1 +#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x00e4 0x0370 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x00e4 0x0370 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 0x00e4 0x0370 0x064c 1 1 +#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD 0x00e4 0x0370 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x00e4 0x0370 0x05b4 3 1 +#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00e4 0x0370 0x0578 4 1 +#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x00e4 0x0370 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x00e4 0x0370 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 0x00e4 0x0370 0x0000 8 0 +#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2 +#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK 0x00e8 0x0374 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1 +#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0 +#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x00e8 0x0374 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 0x00e8 0x0374 0x0664 8 1 +#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x00ec 0x0378 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00ec 0x0378 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 0x00ec 0x0378 0x0654 1 0 +#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B 0x00ec 0x0378 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x00ec 0x0378 0x05bc 3 1 +#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 0x00ec 0x0378 0x0000 4 0 +#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x00ec 0x0378 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x00ec 0x0378 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M 0x00ec 0x0378 0x0000 8 0 +#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x00f0 0x037c 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00f0 0x037c 0x0654 1 1 +#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 0x00f0 0x037c 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN 0x00f0 0x037c 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x00f0 0x037c 0x05c0 3 1 +#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0 +#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0 +#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD 0x00f4 0x0380 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x00f4 0x0380 0x0564 3 0 +#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 0x00f4 0x0380 0x0000 4 0 +#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x00f4 0x0380 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x00f4 0x0380 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 0x00f4 0x0380 0x0000 8 0 +#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1 +#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK 0x00f8 0x0384 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0 +#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0 +#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x00f8 0x0384 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 0x00f8 0x0384 0x0660 8 1 +#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00fc 0x0388 0x0000 0 0 +#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x00fc 0x0388 0x0000 1 0 +#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 0x00fc 0x0388 0x0658 1 0 +#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B 0x00fc 0x0388 0x0000 2 0 +#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x00fc 0x0388 0x0568 3 0 +#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00fc 0x0388 0x057c 4 2 +#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00fc 0x0388 0x0000 5 0 +#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x00fc 0x0388 0x0000 6 0 +#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 0x00fc 0x0388 0x04bc 8 1 +#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0100 0x038c 0x0000 0 0 +#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1 +#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0 +#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0 +#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0000 3 0 +#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0 +#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0 +#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0 +#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x0100 0x038c 0x0000 8 0 +#define MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x0104 0x0390 0x0000 0 0 +#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0 +#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0 +#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2 +#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0000 3 0 +#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0 +#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0 +#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0 +#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x0108 0x0394 0x0000 0 0 +#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 0x0108 0x0394 0x0000 1 0 +#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x0108 0x0394 0x063c 2 3 +#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0x0108 0x0394 0x0000 2 0 +#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 0x0108 0x0394 0x060c 3 0 +#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 0x0108 0x0394 0x0000 4 0 +#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x0108 0x0394 0x0000 5 0 +#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 0x0108 0x0394 0x0000 8 0 +#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x010c 0x0398 0x05dc 0 0 +#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 0x010c 0x0398 0x0000 1 0 +#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x010c 0x0398 0x0000 2 0 +#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 0x010c 0x0398 0x0638 2 2 +#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 0x010c 0x0398 0x0608 3 0 +#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB 0x010c 0x0398 0x0000 4 0 +#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x010c 0x0398 0x0000 5 0 +#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 0x010c 0x0398 0x0000 8 0 +#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x0110 0x039c 0x0000 0 0 +#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1 +#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3 +#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0 +#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0000 3 0 +#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0 +#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0 +#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0 +#define MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x0114 0x03a0 0x0000 0 0 +#define MX6UL_PAD_LCD_RESET__LCDIF_CS 0x0114 0x03a0 0x0000 1 0 +#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 0x0114 0x03a0 0x0000 2 0 +#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 0x0114 0x03a0 0x0000 3 0 +#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x0114 0x03a0 0x0000 4 0 +#define MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0114 0x03a0 0x0000 5 0 +#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2 +#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2 +#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 0x011c 0x03a8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x05ec 8 0 +#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2 +#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 0x0120 0x03ac 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x05e8 8 0 +#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2 +#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2 +#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 0x0128 0x03b4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 0x0128 0x03b4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3 +#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 0x012c 0x03b8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 0x012c 0x03b8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2 +#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 0x0130 0x03bc 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 0x0130 0x03bc 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3 +#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0 +#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 0x0134 0x03c0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2 +#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0584 8 2 +#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0588 8 2 +#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1 +#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1 +#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0 +#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x068c 8 0 +#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 0x0154 0x03e0 0x0690 8 0 +#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2 +#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 0x0158 0x03e4 0x0694 8 0 +#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3 +#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 0x015c 0x03e8 0x0698 8 0 +#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x0160 0x03ec 0x0678 8 1 +#define MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x0164 0x03f0 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x0164 0x03f0 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 0x0164 0x03f0 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x0164 0x03f0 0x0670 8 1 +#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x0168 0x03f4 0x067c 8 1 +#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x0168 0x03f4 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2 +#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0 +#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3 +#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0000 2 0 +#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x016c 0x03f8 0x0680 8 1 +#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0 +#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x0170 0x03fc 0x0684 8 0 +#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0 +#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0 +#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0 +#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0000 3 0 +#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0 +#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0 +#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0 +#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x0174 0x0400 0x0688 8 1 +#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0 +#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2 +#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0 +#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x0000 3 0 +#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0 +#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0 +#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0 +#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0 +#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2 +#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0 +#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x0000 3 0 +#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0 +#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0 +#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2 +#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2 +#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1 +#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2 +#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0190 0x041c 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x0190 0x041c 0x068c 1 1 +#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x0190 0x041c 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x0190 0x041c 0x0564 3 1 +#define MX6UL_PAD_NAND_DATA04__EIM_AD12 0x0190 0x041c 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x0190 0x041c 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x0190 0x041c 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 0x0190 0x041c 0x062c 8 2 +#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0194 0x0420 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x0194 0x0420 0x0690 1 1 +#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x0194 0x0420 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x0194 0x0420 0x056c 3 1 +#define MX6UL_PAD_NAND_DATA05__EIM_AD13 0x0194 0x0420 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x0194 0x0420 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x0194 0x0420 0x062c 8 3 +#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 0x0194 0x0420 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0198 0x0424 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x0198 0x0424 0x0694 1 1 +#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 0x0198 0x0424 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x0198 0x0424 0x0568 3 1 +#define MX6UL_PAD_NAND_DATA06__EIM_AD14 0x0198 0x0424 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x0198 0x0424 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x0198 0x0424 0x0000 8 0 +#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 0x0198 0x0424 0x0628 8 4 +#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0 +#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1 +#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0 +#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0000 3 0 +#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0 +#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0 +#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5 +#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 0x019c 0x0428 0x0000 8 0 +#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x01a0 0x042c 0x0000 0 0 +#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x01a0 0x042c 0x0000 1 0 +#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 0x01a0 0x042c 0x0000 2 0 +#define MX6UL_PAD_NAND_ALE__PWM3_OUT 0x01a0 0x042c 0x0000 3 0 +#define MX6UL_PAD_NAND_ALE__EIM_ADDR17 0x01a0 0x042c 0x0000 4 0 +#define MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x01a0 0x042c 0x0000 5 0 +#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 0x01a0 0x042c 0x0000 8 0 +#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x01a4 0x0430 0x0000 0 0 +#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x01a4 0x0430 0x0000 1 0 +#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x01a4 0x0430 0x0000 2 0 +#define MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x01a4 0x0430 0x0000 3 0 +#define MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x01a4 0x0430 0x0000 4 0 +#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x01a4 0x0430 0x0000 5 0 +#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 0x01a4 0x0430 0x0000 8 0 +#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0 +#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0 +#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0 +#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0000 3 0 +#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0 +#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0 +#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0 +#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 0x01a8 0x0434 0x0634 8 2 +#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x01ac 0x0438 0x0000 0 0 +#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x01ac 0x0438 0x0000 1 0 +#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x01ac 0x0438 0x0000 2 0 +#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x01ac 0x0438 0x0554 3 1 +#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 0x01ac 0x0438 0x0000 4 0 +#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x01ac 0x0438 0x0000 5 0 +#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x01ac 0x0438 0x0634 8 3 +#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 0x01ac 0x0438 0x0000 8 0 +#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x01b0 0x043c 0x0000 0 0 +#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x01b0 0x043c 0x0000 1 0 +#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x01b0 0x043c 0x0000 2 0 +#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x01b0 0x043c 0x055c 3 1 +#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0x01b0 0x043c 0x0000 4 0 +#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x01b0 0x043c 0x0000 5 0 +#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x01b0 0x043c 0x0000 8 0 +#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 0x01b0 0x043c 0x0630 8 2 +#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x01b4 0x0440 0x0000 0 0 +#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x01b4 0x0440 0x0000 1 0 +#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x01b4 0x0440 0x0000 2 0 +#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x01b4 0x0440 0x0558 3 1 +#define MX6UL_PAD_NAND_CLE__EIM_ADDR16 0x01b4 0x0440 0x0000 4 0 +#define MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x01b4 0x0440 0x0000 5 0 +#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x01b4 0x0440 0x0630 8 3 +#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 0x01b4 0x0440 0x0000 8 0 +#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x01b8 0x0444 0x0000 0 0 +#define MX6UL_PAD_NAND_DQS__CSI_FIELD 0x01b8 0x0444 0x0530 1 1 +#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x01b8 0x0444 0x0000 2 0 +#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0 +#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0 +#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0 +#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0000 6 0 +#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x061c 8 1 +#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0 +#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0 +#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 0x01bc 0x0448 0x0000 2 0 +#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0 +#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0 +#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0 +#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0000 6 0 +#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0 +#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0 +#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0 +#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x0000 2 0 +#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3 +#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0 +#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0 +#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x01c0 0x044c 0x0664 8 2 +#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x01c4 0x0450 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 0x01c4 0x0450 0x0000 1 0 +#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01c4 0x0450 0x05fc 2 1 +#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 0x01c4 0x0450 0x0000 3 0 +#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 0x01c4 0x0450 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x01c4 0x0450 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x01c4 0x0450 0x04b8 8 2 +#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x01c8 0x0454 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA1__GPT2_CLK 0x01c8 0x0454 0x05a0 1 1 +#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01c8 0x0454 0x05f8 2 1 +#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 0x01c8 0x0454 0x0584 3 3 +#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 0x01c8 0x0454 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x01c8 0x0454 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 0x01c8 0x0454 0x0000 8 0 +#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x01cc 0x0458 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 0x01cc 0x0458 0x0598 1 1 +#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01cc 0x0458 0x05f4 2 1 +#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 0x01cc 0x0458 0x0000 3 0 +#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 0x01cc 0x0458 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x01cc 0x0458 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 0x01cc 0x0458 0x0000 6 0 +#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 0x01cc 0x0458 0x0660 8 2 +#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x01d0 0x045c 0x0000 0 0 +#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 0x01d0 0x045c 0x059c 1 1 +#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01d0 0x045c 0x0000 2 0 +#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 0x01d0 0x045c 0x0588 3 3 +#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 0x01d0 0x045c 0x0000 4 0 +#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x01d0 0x045c 0x0000 5 0 +#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 0x01d0 0x045c 0x0000 6 0 +#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 0x01d0 0x045c 0x04bc 8 2 +#define MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x01d4 0x0460 0x0000 0 0 +#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 0x01d4 0x0460 0x0674 1 0 +#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 0x01d4 0x0460 0x0000 2 0 +#define MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x01d4 0x0460 0x05a8 3 0 +#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x01d4 0x0460 0x0000 4 0 +#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x01d4 0x0460 0x0000 5 0 +#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 0x01d4 0x0460 0x0000 6 0 +#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x01d4 0x0460 0x0000 8 0 +#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x01d4 0x0460 0x064c 8 0 +#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x01d8 0x0464 0x0528 0 1 +#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 0x01d8 0x0464 0x069c 1 2 +#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 0x01d8 0x0464 0x0000 2 0 +#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x01d8 0x0464 0x05a4 3 2 +#define MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x01d8 0x0464 0x0000 4 0 +#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x01d8 0x0464 0x0000 5 0 +#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 0x01d8 0x0464 0x0000 6 0 +#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x01d8 0x0464 0x064c 8 3 +#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x01d8 0x0464 0x0000 8 0 +#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x01dc 0x0468 0x052c 0 0 +#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x01dc 0x0468 0x0670 1 0 +#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 0x01dc 0x0468 0x0000 2 0 +#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x01dc 0x0468 0x05b0 3 0 +#define MX6UL_PAD_CSI_VSYNC__EIM_RW 0x01dc 0x0468 0x0000 4 0 +#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x01dc 0x0468 0x0000 5 0 +#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x01dc 0x0468 0x0000 6 0 +#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x01dc 0x0468 0x0648 8 0 +#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x01dc 0x0468 0x0000 8 0 +#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x01e0 0x046c 0x0524 0 0 +#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x01e0 0x046c 0x0678 1 0 +#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 0x01e0 0x046c 0x0000 2 0 +#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x01e0 0x046c 0x05ac 3 0 +#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x01e0 0x046c 0x0000 4 0 +#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x01e0 0x046c 0x0000 5 0 +#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x01e0 0x046c 0x0000 6 0 +#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x01e0 0x046c 0x0000 8 0 +#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x01e0 0x046c 0x0648 8 1 +#define MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x01e4 0x0470 0x04c4 0 0 +#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x01e4 0x0470 0x067c 1 0 +#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 0x01e4 0x0470 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x01e4 0x0470 0x0544 3 0 +#define MX6UL_PAD_CSI_DATA00__EIM_AD00 0x01e4 0x0470 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x01e4 0x0470 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 0x01e4 0x0470 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x01e4 0x0470 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 0x01e4 0x0470 0x0644 8 0 +#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0 +#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0 +#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0000 3 0 +#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1 +#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1 +#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x01ec 0x0478 0x0684 1 2 +#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 0x01ec 0x0478 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x01ec 0x0478 0x054c 3 1 +#define MX6UL_PAD_CSI_DATA02__EIM_AD02 0x01ec 0x0478 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x01ec 0x0478 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x01ec 0x0478 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01ec 0x0478 0x0640 8 5 +#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 0x01ec 0x0478 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01f0 0x047c 0x04cc 0 0 +#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01f0 0x047c 0x0688 1 0 +#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01f0 0x047c 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01f0 0x047c 0x0548 3 0 +#define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01f0 0x047c 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01f0 0x047c 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01f0 0x047c 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01f0 0x047c 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01f0 0x047c 0x0640 8 0 +#define MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x01f4 0x0480 0x04dc 0 1 +#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 0x01f4 0x0480 0x068c 1 2 +#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x01f4 0x0480 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x01f4 0x0480 0x0534 3 1 +#define MX6UL_PAD_CSI_DATA04__EIM_AD04 0x01f4 0x0480 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x01f4 0x0480 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x01f4 0x0480 0x05ec 6 1 +#define MX6UL_PAD_CSI_DATA04__USDHC1_WP 0x01f4 0x0480 0x066c 8 2 +#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1 +#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2 +#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0000 3 0 +#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1 +#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 0x01f8 0x0484 0x0668 8 2 +#define MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x01fc 0x0488 0x04e4 0 1 +#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 0x01fc 0x0488 0x0694 1 2 +#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0x01fc 0x0488 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1 +#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0 +#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1 +#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2 +#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0x0200 0x048c 0x0000 2 0 +#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0200 0x048c 0x0538 3 1 +#define MX6UL_PAD_CSI_DATA07__EIM_AD07 0x0200 0x048c 0x0000 4 0 +#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0200 0x048c 0x0000 5 0 +#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x0200 0x048c 0x0000 6 0 +#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x0200 0x048c 0x0000 8 0 + +#endif /* __DTS_IMX6UL_PINFUNC_H */ diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts b/arch/arm/dts/imx6ull-14x14-evk.dts new file mode 100644 index 0000000..375bd4e --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-evk.dts @@ -0,0 +1,527 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "imx6ull.dtsi" + +/ { + model = "Freescale i.MX6 ULL 14x14 EVK Board"; + compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + }; + + spi4 { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + oe-gpios = <&gpio5 8 0>; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&cpu0 { + arm-supply = <®_arm>; + soc-supply = <®_soc>; + dc-supply = <®_gpio_dvfs>; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&iomuxc_snvs { + pinctrl-names = "default_snvs"; + pinctrl-0 = <&pinctrl_hog_2>; + imx6ul-evk { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_lcdif_reset: lcdifresetgrp { + fsl,pins = < + /* used for lcd reset */ + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + + pinctrl_sai2_hp_det_b: sai2_hp_det_grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + }; +}; + + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl + &pinctrl_lcdif_reset>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbphy1 { + tx-d-cal = <0x5>; +}; + +&usbphy2 { + tx-d-cal = <0x5>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; diff --git a/arch/arm/dts/imx6ull-pinfunc-snvs.h b/arch/arm/dts/imx6ull-pinfunc-snvs.h new file mode 100644 index 0000000..da3f412 --- /dev/null +++ b/arch/arm/dts/imx6ull-pinfunc-snvs.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H +#define __DTS_IMX6ULL_PINFUNC_SNVS_H +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0 +#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0 +#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0 + +#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */ + diff --git a/arch/arm/dts/imx6ull-pinfunc.h b/arch/arm/dts/imx6ull-pinfunc.h new file mode 100644 index 0000000..fca0036 --- /dev/null +++ b/arch/arm/dts/imx6ull-pinfunc.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __DTS_IMX6ULL_PINFUNC_H +#define __DTS_IMX6ULL_PINFUNC_H + +#include "imx6ul-pinfunc.h" +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ +#define MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0 +#define MX6UL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0 +#define MX6UL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0 + +#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0 +#define MX6UL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0 + +#endif /* __DTS_IMX6ULL_PINFUNC_H */ diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi new file mode 100644 index 0000000..65950e8 --- /dev/null +++ b/arch/arm/dts/imx6ull.dtsi @@ -0,0 +1,1161 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <dt-bindings/clock/imx6ul-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "imx6ull-pinfunc.h" +#include "imx6ull-pinfunc-snvs.h" +#include "skeleton.dtsi" + +/ { + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + ethernet0 = &fec1; + ethernet1 = &fec2; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + serial7 = &uart8; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; + usbphy0 = &usbphy1; + usbphy1 = &usbphy2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clock-latency = <61036>; /* two CLK32 periods */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 99000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 99000 1175000 + >; + clocks = <&clks IMX6UL_CLK_ARM>, + <&clks IMX6UL_CLK_PLL2_BUS>, + <&clks IMX6UL_CLK_PLL2_PFD2>, + <&clks IMX6UL_CA7_SECONDARY_SEL>, + <&clks IMX6UL_CLK_STEP>, + <&clks IMX6UL_CLK_PLL1_SW>, + <&clks IMX6UL_CLK_PLL1_SYS>, + <&clks IMX6UL_PLL1_BYPASS>, + <&clks IMX6UL_CLK_PLL1>, + <&clks IMX6UL_PLL1_BYPASS_SRC>, + <&clks IMX6UL_CLK_OSC>; + clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", "secondary_sel", "step", + "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src", "osc"; + }; + }; + + intc: interrupt-controller@00a01000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a02000 0x100>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ckil"; + }; + + osc: clock@1 { + compatible = "fixed-clock"; + reg = <1>; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "osc"; + }; + + ipp_di0: clock@2 { + compatible = "fixed-clock"; + reg = <2>; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di0"; + }; + + ipp_di1: clock@3 { + compatible = "fixed-clock"; + reg = <3>; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "ipp_di1"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gpc>; + ranges; + + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>, + <&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>, + <&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>, + <&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>, + <&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>, + <&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>, + <&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>, + <&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>, <&clks IMX6UL_PLL1_BYPASS_SRC>, + <&clks IMX6UL_PLL1_BYPASS>, <&clks IMX6UL_CLK_PLL1_SYS>, <&clks IMX6UL_CLK_PLL1_SW>, + <&clks IMX6UL_CLK_PLL1>; + clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg", + "periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", + "ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel", + "step", "mmdc", "pll1_bypass_src", "pll1_bypass", "pll1_sys", "pll1_sw", "pll1"; + fsl,max_ddr_freq = <400000000>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ocrams: sram@00900000 { + compatible = "fsl,lpm-sram"; + reg = <0x00900000 0x4000>; + }; + + ocrams_ddr: sram@00904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00904000 0x1000>; + }; + + ocram: sram@00905000 { + compatible = "mmio-sram"; + reg = <0x00905000 0x1B000>; + }; + + dma_apbh: dma-apbh@01804000 { + compatible = "fsl,imx6ul-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x01804000 0x2000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX6UL_CLK_APBHDMA>; + }; + + gpmi: gpmi-nand@01806000{ + compatible = "fsl,imx6ull-gpmi-nand", "fsl, imx6ul-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x01806000 0x2000>, <0x01808000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bch"; + clocks = <&clks IMX6UL_CLK_GPMI_IO>, + <&clks IMX6UL_CLK_GPMI_APB>, + <&clks IMX6UL_CLK_GPMI_BCH>, + <&clks IMX6UL_CLK_GPMI_BCH_APB>, + <&clks IMX6UL_CLK_PER_BCH>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", + "gpmi_bch_apb", "per1_bch"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + aips1: aips-bus@02000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba-bus@02000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif: spdif@02004000 { + compatible = "fsl,imx6ul-spdif", "fsl,imx35-spdif"; + reg = <0x02004000 0x4000>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&sdma 41 18 0>, + <&sdma 42 18 0>; + dma-names = "rx", "tx"; + clocks = <&clks IMX6UL_CLK_SPDIF_GCLK>, + <&clks IMX6UL_CLK_OSC>, + <&clks IMX6UL_CLK_SPDIF>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_IPG>, + <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_SPBA>; + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "dma"; + status = "disabled"; + }; + + ecspi1: ecspi@02008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ECSPI1>, + <&clks IMX6UL_CLK_ECSPI1>; + clock-names = "ipg", "per"; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi2: ecspi@0200c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ECSPI2>, + <&clks IMX6UL_CLK_ECSPI2>; + clock-names = "ipg", "per"; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi3: ecspi@02010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ECSPI3>, + <&clks IMX6UL_CLK_ECSPI3>; + clock-names = "ipg", "per"; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ecspi4: ecspi@02014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ECSPI4>, + <&clks IMX6UL_CLK_ECSPI4>; + clock-names = "ipg", "per"; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart7: serial@02018000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02018000 0x4000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART7_IPG>, + <&clks IMX6UL_CLK_UART7_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 43 4 0>, <&sdma 44 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart1: serial@02020000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART1_IPG>, + <&clks IMX6UL_CLK_UART1_SERIAL>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + esai: esai@02024000 { + compatible = "fsl,imx6ull-esai"; + reg = <0x02024000 0x4000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ESAI_IPG>, + <&clks IMX6UL_CLK_ESAI_MEM>, + <&clks IMX6UL_CLK_ESAI_EXTAL>, + <&clks IMX6UL_CLK_ESAI_IPG>, + <&clks IMX6UL_CLK_SPBA>; + clock-names = "core", "mem", "extal", + "fsys", "dma"; + dmas = <&sdma 0 21 0>, <&sdma 47 21 0>; + dma-names = "rx", "tx"; + dma-source = <&gpr 0 14 0 15>; + status = "disabled"; + }; + + sai1: sai@02028000 { + compatible = "fsl,imx6ul-sai", + "fsl,imx6sx-sai"; + reg = <0x02028000 0x4000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_SAI1_IPG>, + <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_SAI1>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 35 24 0>, <&sdma 36 24 0>; + status = "disabled"; + }; + + sai2: sai@0202c000 { + compatible = "fsl,imx6ul-sai", + "fsl,imx6sx-sai"; + reg = <0x0202c000 0x4000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_SAI2_IPG>, + <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_SAI2>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 37 24 0>, <&sdma 38 24 0>; + status = "disabled"; + }; + + sai3: sai@02030000 { + compatible = "fsl,imx6ul-sai", + "fsl,imx6sx-sai"; + reg = <0x02030000 0x4000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_SAI3_IPG>, + <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_SAI3>, + <&clks 0>, <&clks 0>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 39 24 0>, <&sdma 40 24 0>; + status = "disabled"; + }; + + asrc: asrc@02034000 { + compatible = "fsl,imx53-asrc"; + reg = <0x02034000 0x4000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ASRC_IPG>, + <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>, + <&clks IMX6UL_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "dma"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; + status = "okay"; + }; + }; + + tsc: tsc@02040000 { + compatible = "fsl,imx6ul-tsc"; + reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_IPG>, + <&clks IMX6UL_CLK_ADC2>; + clock-names = "tsc", "adc"; + status = "disabled"; + }; + + pwm1: pwm@02080000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_PWM1>, + <&clks IMX6UL_CLK_PWM1>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm2: pwm@02084000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm3: pwm@02088000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_PWM3>, + <&clks IMX6UL_CLK_PWM3>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm4: pwm@0208c000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + flexcan1: can@02090000 { + compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; + reg = <0x02090000 0x4000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_CAN1_IPG>, + <&clks IMX6UL_CLK_CAN1_SERIAL>; + clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 1 0x10 17>; + status = "disabled"; + }; + + flexcan2: can@02094000 { + compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; + reg = <0x02094000 0x4000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_CAN2_IPG>, + <&clks IMX6UL_CLK_CAN2_SERIAL>; + clock-names = "ipg", "per"; + stop-mode = <&gpr 0x10 2 0x10 18>; + status = "disabled"; + }; + + gpt1: gpt@02098000 { + compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt"; + reg = <0x02098000 0x4000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_GPT1_BUS>, + <&clks IMX6UL_CLK_GPT1_SERIAL>; + clock-names = "ipg", "per"; + }; + + gpio1: gpio@0209c000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@020a0000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@020a4000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@020a8000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@020ac000 { + compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + snvslp: snvs@020b0000 { + compatible = "fsl,imx6ul-snvs"; + reg = <0x020b0000 0x4000>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + }; + + fec2: ethernet@020b4000 { + compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; + reg = <0x020b4000 0x4000>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ENET>, + <&clks IMX6UL_CLK_ENET_AHB>, + <&clks IMX6UL_CLK_ENET_PTP>, + <&clks IMX6UL_CLK_ENET2_REF_125M>, + <&clks IMX6UL_CLK_ENET2_REF_125M>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + stop-mode = <&gpr 0x10 4>; + fsl,num-tx-queues=<1>; + fsl,num-rx-queues=<1>; + fsl,magic-packet; + fsl,wakeup_irq = <0>; + status = "disabled"; + }; + + kpp: kpp@020b8000 { + compatible = "fsl,imx6ul-kpp", "fsl,imx21-kpp"; + reg = <0x020b8000 0x4000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>; + status = "disabled"; + }; + + wdog1: wdog@020bc000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_WDOG1>; + }; + + wdog2: wdog@020c0000 { + compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_WDOG2>; + status = "disabled"; + }; + + clks: ccm@020c4000 { + compatible = "fsl,imx6ul-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + #clock-cells = <1>; + clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; + clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; + }; + + anatop: anatop@020c8000 { + compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", + "syscon", "simple-bus"; + reg = <0x020c8000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + + reg_3p0: regulator-3p0@120 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; + }; + + reg_arm: regulator-vddcore@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "cpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_soc: regulator-vddsoc@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <28>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + }; + + usbphy1: usbphy@020c9000 { + compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + usbphy2: usbphy@020ca000 { + compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USBPHY2>; + phy-3p0-supply = <®_3p0>; + fsl,anatop = <&anatop>; + }; + + tempmon: tempmon { + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + }; + + snvs: snvs@020cc000 { + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; + reg = <0x020cc000 0x4000>; + + snvs_rtc: snvs-rtc-lp { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + regmap = <&snvs>; + offset = <0x34>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + }; + + snvs_poweroff: snvs-poweroff { + compatible = "syscon-poweroff"; + regmap = <&snvs>; + offset = <0x38>; + mask = <0x61>; + }; + + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + linux,keycode = <KEY_POWER>; + wakeup; + }; + }; + + epit1: epit@020d0000 { + reg = <0x020d0000 0x4000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + }; + + epit2: epit@020d4000 { + reg = <0x020d4000 0x4000>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + }; + + src: src@020d8000 { + compatible = "fsl,imx6ul-src", "fsl,imx51-src"; + reg = <0x020d8000 0x4000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + + gpc: gpc@020dc000 { + compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0xfc00000 0x7d00 0x0 0x1400640>; + }; + + iomuxc: iomuxc@020e0000 { + compatible = "fsl,imx6ul-iomuxc"; + reg = <0x020e0000 0x4000>; + }; + + gpr: iomuxc-gpr@020e4000 { + compatible = "fsl,imx6ul-iomuxc-gpr", "syscon"; + reg = <0x020e4000 0x4000>; + }; + + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; + }; + + gpt2: gpt@020e8000 { + compatible = "fsl,imx6ul-gpt", "fsl,imx31-gpt"; + reg = <0x020e8000 0x4000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + }; + + sdma: sdma@020ec000 { + compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_SDMA>, + <&clks IMX6UL_CLK_SDMA>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + iram = <&ocram>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + }; + + pwm5: pwm@020f0000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f0000 0x4000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm6: pwm@020f4000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f4000 0x4000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm7: pwm@020f8000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020f8000 0x4000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + + pwm8: pwm@020fc000 { + compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; + reg = <0x020fc000 0x4000>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + }; + }; + + aips2: aips-bus@02100000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + usbotg1: usb@02184000 { + compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + fsl,anatop = <&anatop>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbotg2: usb@02184200 { + compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USBOH3>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + status = "disabled"; + }; + + usbmisc: usbmisc@02184800 { + #index-cells = <1>; + compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + }; + + fec1: ethernet@02188000 { + compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; + reg = <0x02188000 0x4000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ENET>, + <&clks IMX6UL_CLK_ENET_AHB>, + <&clks IMX6UL_CLK_ENET_PTP>, + <&clks IMX6UL_CLK_ENET_REF>, + <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "ipg", "ahb", "ptp", + "enet_clk_ref", "enet_out"; + stop-mode = <&gpr 0x10 3>; + fsl,num-tx-queues=<1>; + fsl,num-rx-queues=<1>; + fsl,magic-packet; + fsl,wakeup_irq = <0>; + status = "disabled"; + }; + + usdhc1: usdhc@02190000 { + compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USDHC1>, + <&clks IMX6UL_CLK_USDHC1>, + <&clks IMX6UL_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: usdhc@02194000 { + compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_USDHC2>, + <&clks IMX6UL_CLK_USDHC2>, + <&clks IMX6UL_CLK_USDHC2>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + adc1: adc@02198000 { + compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; + reg = <0x02198000 0x4000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_ADC1>; + num-channels = <2>; + clock-names = "adc"; + status = "disabled"; + }; + + i2c1: i2c@021a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_I2C1>; + status = "disabled"; + }; + + i2c2: i2c@021a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_I2C2>; + status = "disabled"; + }; + + i2c3: i2c@021a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_I2C3>; + status = "disabled"; + }; + + romcp@021ac000 { + compatible = "fsl,imx6ul-romcp", "syscon"; + reg = <0x021ac000 0x4000>; + }; + + mmdc: mmdc@021b0000 { + compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + }; + + weim: weim@021b8000 { + compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim"; + reg = <0x021b8000 0x4000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>; + }; + + ocotp: ocotp-ctrl@021bc000 { + compatible = "fsl,imx6ull-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6UL_CLK_OCOTP>; + }; + + csu: csu@021c0000 { + compatible = "fsl,imx6ul-csu"; + reg = <0x021c0000 0x4000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + csi: csi@021c4000 { + compatible = "fsl,imx6ul-csi", "fsl,imx6s-csi"; + reg = <0x021c4000 0x4000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, + <&clks IMX6UL_CLK_CSI>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + lcdif: lcdif@021c8000 { + compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; + reg = <0x021c8000 0x4000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, + <&clks IMX6UL_CLK_LCDIF_APB>, + <&clks IMX6UL_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; + }; + + pxp: pxp@021cc000 { + compatible = "fsl,imx6ull-pxp-dma", "fsl,imx7d-pxp-dma"; + reg = <0x021cc000 0x4000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_PXP>; + clock-names = "pxp_ipg", "pxp_axi"; + status = "disabled"; + }; + + qspi: qspi@021e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ull-qspi", "fsl,imx6ul-qspi"; + reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_QSPI>, + <&clks IMX6UL_CLK_QSPI>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + uart2: serial@021e8000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021e8000 0x4000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART2_IPG>, + <&clks IMX6UL_CLK_UART2_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart3: serial@021ec000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021ec000 0x4000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART3_IPG>, + <&clks IMX6UL_CLK_UART3_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart4: serial@021f0000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f0000 0x4000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART4_IPG>, + <&clks IMX6UL_CLK_UART4_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uart5: serial@021f4000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f4000 0x4000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART5_IPG>, + <&clks IMX6UL_CLK_UART5_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c4: i2c@021f8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; + reg = <0x021f8000 0x4000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_I2C4>; + status = "disabled"; + }; + + uart6: serial@021fc000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021fc000 0x4000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART6_IPG>, + <&clks IMX6UL_CLK_UART6_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + }; + + aips3: aips-bus@02200000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02200000 0x100000>; + ranges; + + dcp: dcp@02280000 { + reg = <0x02280000 0x4000>; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + /*clocks = <&clks IMX6UL_CLK_DCP>;*/ + clock-names = "dcp"; + status = "disabled"; + }; + + rngb: rngb@02284000 { + reg = <0x02284000 0x4000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + }; + + uart8: serial@02288000 { + compatible = "fsl,imx6ul-uart", + "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02288000 0x4000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6UL_CLK_UART8_IPG>, + <&clks IMX6UL_CLK_UART8_SERIAL>; + clock-names = "ipg", "per"; + dmas = <&sdma 45 4 0>, <&sdma 46 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + epdc: epdc@0228c000 { + compatible = "fsl,imx7d-epdc"; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x0228c000 0x4000>; + clocks = <&clks IMX6UL_CLK_EPDC_ACLK>, + <&clks IMX6UL_CLK_EPDC_PIX>; + clock-names = "epdc_axi", "epdc_pix"; + /* Need to fix epdc-ram */ + /* epdc-ram = <&gpr 0x4 30>; */ + status = "disabled"; + }; + + iomuxc_snvs: iomuxc-snvs@02290000 { + compatible = "fsl,imx6ull-iomuxc-snvs"; + reg = <0x02290000 0x10000>; + }; + + snvs_gpr: snvs-gpr@0x02294000 { + compatible = "fsl, imx6ull-snvs-gpr"; + reg = <0x02294000 0x10000>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx7-colibri.dts b/arch/arm/dts/imx7-colibri.dts new file mode 100644 index 0000000..cbef5d5 --- /dev/null +++ b/arch/arm/dts/imx7-colibri.dts @@ -0,0 +1,97 @@ +/* + * Copyright 2016 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include "imx7.dtsi" + +/ { + model = "Toradex Colibri iMX7S/D"; + compatible = "toradex,imx7-colibri", "fsl,imx7"; + + chosen { + stdout-path = &uart1; + }; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + status = "okay"; + + rn5t567@33 { + compatible = "ricoh,rn5t567"; + reg = <0x33>; + }; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; + uart-has-rtscts; + fsl,dte-mode; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c4: i2c4-grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f + MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpio-grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f + MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 + MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 + MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 + >; + }; + + pinctrl_uart1_ctrl1: uart1-ctrl1-grp { + fsl,pins = < + MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */ + MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */ + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f + MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x4000007f + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x4000007f + >; + }; +}; diff --git a/arch/arm/dts/imx7.dtsi b/arch/arm/dts/imx7.dtsi new file mode 100644 index 0000000..755cc46 --- /dev/null +++ b/arch/arm/dts/imx7.dtsi @@ -0,0 +1,194 @@ +/* + * Copyright 2016 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ or X11 + */ +#include "imx7d-pinfunc.h" +#include "skeleton.dtsi" + +/ { + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + i2c3 = &i2c4; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + serial6 = &uart7; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + aips1: aips-bus@30000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30000000 0x400000>; + ranges; + + gpio1: gpio@30200000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30200000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio2: gpio@30210000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30210000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio3: gpio@30220000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30220000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio4: gpio@30230000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30230000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio5: gpio@30240000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30240000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio6: gpio@30250000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30250000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio7: gpio@30260000 { + compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; + reg = <0x30260000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + }; + + iomuxc_lpsr: iomuxc-lpsr@302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; + }; + + iomuxc: iomuxc@30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + }; + }; + + aips3: aips-bus@30800000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30800000 0x400000>; + ranges; + + uart1: serial@30860000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + status = "disabled"; + }; + + uart2: serial@30890000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + status = "disabled"; + }; + + uart3: serial@30880000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + status = "disabled"; + }; + + i2c1: i2c@30a20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a20000 0x10000>; + status = "disabled"; + }; + + i2c2: i2c@30a30000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a30000 0x10000>; + status = "disabled"; + }; + + i2c3: i2c@30a40000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a40000 0x10000>; + status = "disabled"; + }; + + i2c4: i2c@30a50000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; + reg = <0x30a50000 0x10000>; + status = "disabled"; + }; + + uart4: serial@30a60000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a60000 0x10000>; + status = "disabled"; + }; + + uart5: serial@30a70000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a70000 0x10000>; + status = "disabled"; + }; + + uart6: serial@30a80000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a80000 0x10000>; + status = "disabled"; + }; + + uart7: serial@30a90000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30a90000 0x10000>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx7d-pinfunc.h b/arch/arm/dts/imx7d-pinfunc.h new file mode 100644 index 0000000..32d2464 --- /dev/null +++ b/arch/arm/dts/imx7d-pinfunc.h @@ -0,0 +1,1151 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DTS_IMX7D_PINFUNC_H +#define __DTS_IMX7D_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <mux_reg conf_reg input_reg mux_mode input_val> + */ + +#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0 0x0000 0x0030 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO00__PWM4_OUT 0x0000 0x0030 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY 0x0000 0x0030 0x0000 0x2 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x0000 0x0030 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB 0x0000 0x0030 0x0000 0x4 0x0 +#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x0004 0x0034 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO01__PWM1_OUT 0x0004 0x0034 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3 0x0004 0x0034 0x0000 0x2 0x0 +#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK 0x0004 0x0034 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x0004 0x0034 0x0000 0x4 0x0 +#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT 0x0004 0x0034 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x0008 0x0038 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO02__PWM2_OUT 0x0008 0x0038 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1 0x0008 0x0038 0x0564 0x2 0x3 +#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK 0x0008 0x0038 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1 0x0008 0x0038 0x0000 0x5 0x0 +#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT 0x0008 0x0038 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID 0x0008 0x0038 0x0734 0x7 0x3 +#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x000C 0x003C 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO03__PWM3_OUT 0x000C 0x003C 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2 0x000C 0x003C 0x0570 0x2 0x3 +#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK 0x000C 0x003C 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2 0x000C 0x003C 0x0000 0x5 0x0 +#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT 0x000C 0x003C 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID 0x000C 0x003C 0x0730 0x7 0x3 +#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x0010 0x0040 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC 0x0010 0x0040 0x072C 0x1 0x1 +#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4 0x0010 0x0040 0x0594 0x2 0x1 +#define MX7D_PAD_GPIO1_IO04__UART5_CTS_B 0x0010 0x0040 0x0710 0x3 0x4 +#define MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x0010 0x0040 0x05D4 0x4 0x2 +#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT 0x0010 0x0040 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x0014 0x0044 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR 0x0014 0x0044 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5 0x0014 0x0044 0x0598 0x2 0x1 +#define MX7D_PAD_GPIO1_IO05__UART5_RTS_B 0x0014 0x0044 0x0710 0x3 0x5 +#define MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x0014 0x0044 0x05D8 0x4 0x2 +#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT 0x0014 0x0044 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6 0x0018 0x0048 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC 0x0018 0x0048 0x0728 0x1 0x1 +#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6 0x0018 0x0048 0x059C 0x2 0x1 +#define MX7D_PAD_GPIO1_IO06__UART5_RX_DATA 0x0018 0x0048 0x0714 0x3 0x4 +#define MX7D_PAD_GPIO1_IO06__I2C2_SCL 0x0018 0x0048 0x05DC 0x4 0x2 +#define MX7D_PAD_GPIO1_IO06__CCM_WAIT 0x0018 0x0048 0x0000 0x5 0x0 +#define MX7D_PAD_GPIO1_IO06__KPP_ROW4 0x0018 0x0048 0x0624 0x6 0x1 +#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x001C 0x004C 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR 0x001C 0x004C 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7 0x001C 0x004C 0x05A0 0x2 0x1 +#define MX7D_PAD_GPIO1_IO07__UART5_TX_DATA 0x001C 0x004C 0x0714 0x3 0x5 +#define MX7D_PAD_GPIO1_IO07__I2C2_SDA 0x001C 0x004C 0x05E0 0x4 0x2 +#define MX7D_PAD_GPIO1_IO07__CCM_STOP 0x001C 0x004C 0x0000 0x5 0x0 +#define MX7D_PAD_GPIO1_IO07__KPP_COL4 0x001C 0x004C 0x0604 0x6 0x1 +#define MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x0014 0x026C 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x0014 0x026C 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0014 0x026C 0x0000 0x2 0x0 +#define MX7D_PAD_GPIO1_IO08__UART3_DCE_RX 0x0014 0x026C 0x0704 0x3 0x0 +#define MX7D_PAD_GPIO1_IO08__UART3_DTE_TX 0x0014 0x026C 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO08__I2C3_SCL 0x0014 0x026C 0x05E4 0x4 0x0 +#define MX7D_PAD_GPIO1_IO08__KPP_COL5 0x0014 0x026C 0x0608 0x6 0x0 +#define MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x0014 0x026C 0x0000 0x7 0x0 +#define MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x0018 0x0270 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO09__SD1_LCTL 0x0018 0x0270 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO09__CCM_ENET_REF_CLK3 0x0018 0x0270 0x0000 0x2 0x0 +#define MX7D_PAD_GPIO1_IO09__UART3_DCE_TX 0x0018 0x0270 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO09__UART3_DTE_RX 0x0018 0x0270 0x0704 0x3 0x1 +#define MX7D_PAD_GPIO1_IO09__I2C3_SDA 0x0018 0x0270 0x05E8 0x4 0x0 +#define MX7D_PAD_GPIO1_IO09__CCM_PMIC_READY 0x0018 0x0270 0x04F4 0x5 0x0 +#define MX7D_PAD_GPIO1_IO09__KPP_ROW5 0x0018 0x0270 0x0628 0x6 0x0 +#define MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x0018 0x0270 0x0000 0x7 0x0 +#define MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x001C 0x0274 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO10__SD2_LCTL 0x001C 0x0274 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x001C 0x0274 0x0568 0x2 0x0 +#define MX7D_PAD_GPIO1_IO10__UART3_DCE_RTS 0x001C 0x0274 0x0700 0x3 0x0 +#define MX7D_PAD_GPIO1_IO10__UART3_DTE_CTS 0x001C 0x0274 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO10__I2C4_SCL 0x001C 0x0274 0x05EC 0x4 0x0 +#define MX7D_PAD_GPIO1_IO10__FLEXTIMER1_PHA 0x001C 0x0274 0x05A4 0x5 0x0 +#define MX7D_PAD_GPIO1_IO10__KPP_COL6 0x001C 0x0274 0x060C 0x6 0x0 +#define MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x001C 0x0274 0x0000 0x7 0x0 +#define MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x0020 0x0278 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO11__SD3_LCTL 0x0020 0x0278 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x0020 0x0278 0x0000 0x2 0x0 +#define MX7D_PAD_GPIO1_IO11__UART3_DCE_CTS 0x0020 0x0278 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO11__UART3_DTE_RTS 0x0020 0x0278 0x0700 0x3 0x1 +#define MX7D_PAD_GPIO1_IO11__I2C4_SDA 0x0020 0x0278 0x05F0 0x4 0x0 +#define MX7D_PAD_GPIO1_IO11__FLEXTIMER1_PHB 0x0020 0x0278 0x05A8 0x5 0x0 +#define MX7D_PAD_GPIO1_IO11__KPP_ROW6 0x0020 0x0278 0x062C 0x6 0x0 +#define MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x0020 0x0278 0x0000 0x7 0x0 +#define MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0024 0x027C 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x0024 0x027C 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 0x0024 0x027C 0x0564 0x2 0x0 +#define MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x0024 0x027C 0x04DC 0x3 0x0 +#define MX7D_PAD_GPIO1_IO12__CM4_NMI 0x0024 0x027C 0x0000 0x4 0x0 +#define MX7D_PAD_GPIO1_IO12__CCM_EXT_CLK1 0x0024 0x027C 0x04E4 0x5 0x0 +#define MX7D_PAD_GPIO1_IO12__SNVS_VIO_5 0x0024 0x027C 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO12__USB_OTG1_ID 0x0024 0x027C 0x0734 0x7 0x0 +#define MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x0028 0x0280 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x0028 0x0280 0x0000 0x1 0x0 +#define MX7D_PAD_GPIO1_IO13__CCM_ENET_REF_CLK2 0x0028 0x0280 0x0570 0x2 0x0 +#define MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x0028 0x0280 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO13__CCM_PMIC_READY 0x0028 0x0280 0x04F4 0x4 0x1 +#define MX7D_PAD_GPIO1_IO13__CCM_EXT_CLK2 0x0028 0x0280 0x04E8 0x5 0x0 +#define MX7D_PAD_GPIO1_IO13__SNVS_VIO_5_CTL 0x0028 0x0280 0x0000 0x6 0x0 +#define MX7D_PAD_GPIO1_IO13__USB_OTG2_ID 0x0028 0x0280 0x0730 0x7 0x0 +#define MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x002C 0x0284 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO14__SD3_CD_B 0x002C 0x0284 0x0738 0x1 0x0 +#define MX7D_PAD_GPIO1_IO14__ENET2_MDIO 0x002C 0x0284 0x0574 0x2 0x0 +#define MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x002C 0x0284 0x04E0 0x3 0x0 +#define MX7D_PAD_GPIO1_IO14__WDOG3_WDOG_B 0x002C 0x0284 0x0000 0x4 0x0 +#define MX7D_PAD_GPIO1_IO14__CCM_EXT_CLK3 0x002C 0x0284 0x04EC 0x5 0x0 +#define MX7D_PAD_GPIO1_IO14__SDMA_EXT_EVENT0 0x002C 0x0284 0x06D8 0x6 0x0 +#define MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x0030 0x0288 0x0000 0x0 0x0 +#define MX7D_PAD_GPIO1_IO15__SD3_WP 0x0030 0x0288 0x073C 0x1 0x0 +#define MX7D_PAD_GPIO1_IO15__ENET2_MDC 0x0030 0x0288 0x0000 0x2 0x0 +#define MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x0030 0x0288 0x0000 0x3 0x0 +#define MX7D_PAD_GPIO1_IO15__WDOG4_WDOG_B 0x0030 0x0288 0x0000 0x4 0x0 +#define MX7D_PAD_GPIO1_IO15__CCM_EXT_CLK4 0x0030 0x0288 0x04F0 0x5 0x0 +#define MX7D_PAD_GPIO1_IO15__SDMA_EXT_EVENT1 0x0030 0x0288 0x06DC 0x6 0x0 +#define MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x0034 0x02A4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA00__SIM1_PORT2_TRXD 0x0034 0x02A4 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x0034 0x02A4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA00__KPP_ROW3 0x0034 0x02A4 0x0620 0x3 0x0 +#define MX7D_PAD_EPDC_DATA00__EIM_AD0 0x0034 0x02A4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x0034 0x02A4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA00__LCD_DATA0 0x0034 0x02A4 0x0638 0x6 0x0 +#define MX7D_PAD_EPDC_DATA00__LCD_CLK 0x0034 0x02A4 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x0038 0x02A8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA01__SIM1_PORT2_CLK 0x0038 0x02A8 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x0038 0x02A8 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA01__KPP_COL3 0x0038 0x02A8 0x0600 0x3 0x0 +#define MX7D_PAD_EPDC_DATA01__EIM_AD1 0x0038 0x02A8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x0038 0x02A8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA01__LCD_DATA1 0x0038 0x02A8 0x063C 0x6 0x0 +#define MX7D_PAD_EPDC_DATA01__LCD_ENABLE 0x0038 0x02A8 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x003C 0x02AC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA02__SIM1_PORT2_RST_B 0x003C 0x02AC 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x003C 0x02AC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA02__KPP_ROW2 0x003C 0x02AC 0x061C 0x3 0x0 +#define MX7D_PAD_EPDC_DATA02__EIM_AD2 0x003C 0x02AC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x003C 0x02AC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA02__LCD_DATA2 0x003C 0x02AC 0x0640 0x6 0x0 +#define MX7D_PAD_EPDC_DATA02__LCD_VSYNC 0x003C 0x02AC 0x0698 0x7 0x0 +#define MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x0040 0x02B0 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA03__SIM1_PORT2_SVEN 0x0040 0x02B0 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x0040 0x02B0 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA03__KPP_COL2 0x0040 0x02B0 0x05FC 0x3 0x0 +#define MX7D_PAD_EPDC_DATA03__EIM_AD3 0x0040 0x02B0 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x0040 0x02B0 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA03__LCD_DATA3 0x0040 0x02B0 0x0644 0x6 0x0 +#define MX7D_PAD_EPDC_DATA03__LCD_HSYNC 0x0040 0x02B0 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x0044 0x02B4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA04__SIM1_PORT2_PD 0x0044 0x02B4 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x0044 0x02B4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA04__KPP_ROW1 0x0044 0x02B4 0x0618 0x3 0x0 +#define MX7D_PAD_EPDC_DATA04__EIM_AD4 0x0044 0x02B4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x0044 0x02B4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA04__LCD_DATA4 0x0044 0x02B4 0x0648 0x6 0x0 +#define MX7D_PAD_EPDC_DATA04__JTAG_FAIL 0x0044 0x02B4 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x0048 0x02B8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA05__SIM2_PORT2_TRXD 0x0048 0x02B8 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x0048 0x02B8 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA05__KPP_COL1 0x0048 0x02B8 0x05F8 0x3 0x0 +#define MX7D_PAD_EPDC_DATA05__EIM_AD5 0x0048 0x02B8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x0048 0x02B8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA05__LCD_DATA5 0x0048 0x02B8 0x064C 0x6 0x0 +#define MX7D_PAD_EPDC_DATA05__JTAG_ACTIVE 0x0048 0x02B8 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x004C 0x02BC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA06__SIM2_PORT2_CLK 0x004C 0x02BC 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x004C 0x02BC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA06__KPP_ROW0 0x004C 0x02BC 0x0614 0x3 0x0 +#define MX7D_PAD_EPDC_DATA06__EIM_AD6 0x004C 0x02BC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x004C 0x02BC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA06__LCD_DATA6 0x004C 0x02BC 0x0650 0x6 0x0 +#define MX7D_PAD_EPDC_DATA06__JTAG_DE_B 0x004C 0x02BC 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x0050 0x02C0 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA07__SIM2_PORT2_RST_B 0x0050 0x02C0 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x0050 0x02C0 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA07__KPP_COL0 0x0050 0x02C0 0x05F4 0x3 0x0 +#define MX7D_PAD_EPDC_DATA07__EIM_AD7 0x0050 0x02C0 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x0050 0x02C0 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA07__LCD_DATA7 0x0050 0x02C0 0x0654 0x6 0x0 +#define MX7D_PAD_EPDC_DATA07__JTAG_DONE 0x0050 0x02C0 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x0054 0x02C4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x0054 0x02C4 0x06E4 0x1 0x0 +#define MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x0054 0x02C4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x0054 0x02C4 0x071C 0x3 0x0 +#define MX7D_PAD_EPDC_DATA08__UART6_DTE_TX 0x0054 0x02C4 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA08__EIM_OE 0x0054 0x02C4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x0054 0x02C4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA08__LCD_DATA8 0x0054 0x02C4 0x0658 0x6 0x0 +#define MX7D_PAD_EPDC_DATA08__LCD_BUSY 0x0054 0x02C4 0x0634 0x7 0x0 +#define MX7D_PAD_EPDC_DATA08__EPDC_SDCLK 0x0054 0x02C4 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x0058 0x02C8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x0058 0x02C8 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x0058 0x02C8 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x0058 0x02C8 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA09__UART6_DTE_RX 0x0058 0x02C8 0x071C 0x3 0x1 +#define MX7D_PAD_EPDC_DATA09__EIM_RW 0x0058 0x02C8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x0058 0x02C8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA09__LCD_DATA9 0x0058 0x02C8 0x065C 0x6 0x0 +#define MX7D_PAD_EPDC_DATA09__LCD_DATA0 0x0058 0x02C8 0x0638 0x7 0x1 +#define MX7D_PAD_EPDC_DATA09__EPDC_SDLE 0x0058 0x02C8 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x005C 0x02CC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x005C 0x02CC 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x005C 0x02CC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x005C 0x02CC 0x0718 0x3 0x0 +#define MX7D_PAD_EPDC_DATA10__UART6_DTE_CTS 0x005C 0x02CC 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA10__EIM_CS0_B 0x005C 0x02CC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x005C 0x02CC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA10__LCD_DATA10 0x005C 0x02CC 0x0660 0x6 0x0 +#define MX7D_PAD_EPDC_DATA10__LCD_DATA9 0x005C 0x02CC 0x065C 0x7 0x1 +#define MX7D_PAD_EPDC_DATA10__EPDC_SDOE 0x005C 0x02CC 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x0060 0x02D0 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x0060 0x02D0 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x0060 0x02D0 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x0060 0x02D0 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA11__UART6_DTE_RTS 0x0060 0x02D0 0x0718 0x3 0x1 +#define MX7D_PAD_EPDC_DATA11__EIM_BCLK 0x0060 0x02D0 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x0060 0x02D0 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA11__LCD_DATA11 0x0060 0x02D0 0x0664 0x6 0x0 +#define MX7D_PAD_EPDC_DATA11__LCD_DATA1 0x0060 0x02D0 0x063C 0x7 0x1 +#define MX7D_PAD_EPDC_DATA11__EPDC_SDCE0 0x0060 0x02D0 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x0064 0x02D4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x0064 0x02D4 0x06E0 0x1 0x0 +#define MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x0064 0x02D4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x0064 0x02D4 0x0724 0x3 0x0 +#define MX7D_PAD_EPDC_DATA12__UART7_DTE_TX 0x0064 0x02D4 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA12__EIM_LBA_B 0x0064 0x02D4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x0064 0x02D4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA12__LCD_DATA12 0x0064 0x02D4 0x0668 0x6 0x0 +#define MX7D_PAD_EPDC_DATA12__LCD_DATA21 0x0064 0x02D4 0x068C 0x7 0x0 +#define MX7D_PAD_EPDC_DATA12__EPDC_GDCLK 0x0064 0x02D4 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x0068 0x02D8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA13__SIM2_PORT1_TRXD 0x0068 0x02D8 0x06EC 0x1 0x0 +#define MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x0068 0x02D8 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x0068 0x02D8 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA13__UART7_DTE_RX 0x0068 0x02D8 0x0724 0x3 0x1 +#define MX7D_PAD_EPDC_DATA13__EIM_WAIT 0x0068 0x02D8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x0068 0x02D8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA13__LCD_DATA13 0x0068 0x02D8 0x066C 0x6 0x0 +#define MX7D_PAD_EPDC_DATA13__LCD_CS 0x0068 0x02D8 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA13__EPDC_GDOE 0x0068 0x02D8 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x006C 0x02DC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA14__SIM2_PORT1_CLK 0x006C 0x02DC 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x006C 0x02DC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x006C 0x02DC 0x0720 0x3 0x0 +#define MX7D_PAD_EPDC_DATA14__UART7_DTE_CTS 0x006C 0x02DC 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA14__EIM_EB_B0 0x006C 0x02DC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x006C 0x02DC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA14__LCD_DATA14 0x006C 0x02DC 0x0670 0x6 0x0 +#define MX7D_PAD_EPDC_DATA14__LCD_DATA22 0x006C 0x02DC 0x0690 0x7 0x0 +#define MX7D_PAD_EPDC_DATA14__EPDC_GDSP 0x006C 0x02DC 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x0070 0x02E0 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_DATA15__SIM2_PORT1_RST_B 0x0070 0x02E0 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x0070 0x02E0 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x0070 0x02E0 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_DATA15__UART7_DTE_RTS 0x0070 0x02E0 0x0720 0x3 0x1 +#define MX7D_PAD_EPDC_DATA15__EIM_CS1_B 0x0070 0x02E0 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x0070 0x02E0 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_DATA15__LCD_DATA15 0x0070 0x02E0 0x0674 0x6 0x0 +#define MX7D_PAD_EPDC_DATA15__LCD_WR_RWN 0x0070 0x02E0 0x0000 0x7 0x0 +#define MX7D_PAD_EPDC_DATA15__EPDC_PWR_COM 0x0070 0x02E0 0x0000 0x8 0x0 +#define MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x0074 0x02E4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDCLK__SIM2_PORT2_SVEN 0x0074 0x02E4 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x0074 0x02E4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDCLK__KPP_ROW4 0x0074 0x02E4 0x0624 0x3 0x0 +#define MX7D_PAD_EPDC_SDCLK__EIM_AD10 0x0074 0x02E4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x0074 0x02E4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDCLK__LCD_CLK 0x0074 0x02E4 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_SDCLK__LCD_DATA20 0x0074 0x02E4 0x0688 0x7 0x0 +#define MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x0078 0x02E8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDLE__SIM2_PORT2_PD 0x0078 0x02E8 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x0078 0x02E8 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDLE__KPP_COL4 0x0078 0x02E8 0x0604 0x3 0x0 +#define MX7D_PAD_EPDC_SDLE__EIM_AD11 0x0078 0x02E8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDLE__GPIO2_IO17 0x0078 0x02E8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDLE__LCD_DATA16 0x0078 0x02E8 0x0678 0x6 0x0 +#define MX7D_PAD_EPDC_SDLE__LCD_DATA8 0x0078 0x02E8 0x0658 0x7 0x1 +#define MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x007C 0x02EC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDOE__FLEXTIMER1_CH0 0x007C 0x02EC 0x0584 0x1 0x0 +#define MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x007C 0x02EC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDOE__KPP_COL5 0x007C 0x02EC 0x0608 0x3 0x1 +#define MX7D_PAD_EPDC_SDOE__EIM_AD12 0x007C 0x02EC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDOE__GPIO2_IO18 0x007C 0x02EC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDOE__LCD_DATA17 0x007C 0x02EC 0x067C 0x6 0x0 +#define MX7D_PAD_EPDC_SDOE__LCD_DATA23 0x007C 0x02EC 0x0694 0x7 0x0 +#define MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x0080 0x02F0 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDSHR__FLEXTIMER1_CH1 0x0080 0x02F0 0x0588 0x1 0x0 +#define MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x0080 0x02F0 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDSHR__KPP_ROW5 0x0080 0x02F0 0x0628 0x3 0x1 +#define MX7D_PAD_EPDC_SDSHR__EIM_AD13 0x0080 0x02F0 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDSHR__GPIO2_IO19 0x0080 0x02F0 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDSHR__LCD_DATA18 0x0080 0x02F0 0x0680 0x6 0x0 +#define MX7D_PAD_EPDC_SDSHR__LCD_DATA10 0x0080 0x02F0 0x0660 0x7 0x1 +#define MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x0084 0x02F4 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDCE0__FLEXTIMER1_CH2 0x0084 0x02F4 0x058C 0x1 0x0 +#define MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x0084 0x02F4 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDCE0__EIM_AD14 0x0084 0x02F4 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDCE0__GPIO2_IO20 0x0084 0x02F4 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDCE0__LCD_DATA19 0x0084 0x02F4 0x0684 0x6 0x0 +#define MX7D_PAD_EPDC_SDCE0__LCD_DATA5 0x0084 0x02F4 0x064C 0x7 0x1 +#define MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x0088 0x02F8 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDCE1__FLEXTIMER1_CH3 0x0088 0x02F8 0x0590 0x1 0x0 +#define MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x0088 0x02F8 0x0578 0x2 0x0 +#define MX7D_PAD_EPDC_SDCE1__ENET2_RX_ER 0x0088 0x02F8 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_SDCE1__EIM_AD15 0x0088 0x02F8 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDCE1__GPIO2_IO21 0x0088 0x02F8 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDCE1__LCD_DATA20 0x0088 0x02F8 0x0688 0x6 0x1 +#define MX7D_PAD_EPDC_SDCE1__LCD_DATA4 0x0088 0x02F8 0x0648 0x7 0x1 +#define MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x008C 0x02FC 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDCE2__SIM2_PORT1_SVEN 0x008C 0x02FC 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x008C 0x02FC 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDCE2__KPP_COL6 0x008C 0x02FC 0x060C 0x3 0x1 +#define MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 0x008C 0x02FC 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x008C 0x02FC 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDCE2__LCD_DATA21 0x008C 0x02FC 0x068C 0x6 0x1 +#define MX7D_PAD_EPDC_SDCE2__LCD_DATA3 0x008C 0x02FC 0x0644 0x7 0x1 +#define MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x0090 0x0300 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_SDCE3__SIM2_PORT1_PD 0x0090 0x0300 0x06E8 0x1 0x0 +#define MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x0090 0x0300 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_SDCE3__KPP_ROW6 0x0090 0x0300 0x062C 0x3 0x1 +#define MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 0x0090 0x0300 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x0090 0x0300 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_SDCE3__LCD_DATA22 0x0090 0x0300 0x0690 0x6 0x1 +#define MX7D_PAD_EPDC_SDCE3__LCD_DATA2 0x0090 0x0300 0x0640 0x7 0x1 +#define MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x0094 0x0304 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_GDCLK__FLEXTIMER2_CH0 0x0094 0x0304 0x05AC 0x1 0x0 +#define MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x0094 0x0304 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_GDCLK__KPP_COL7 0x0094 0x0304 0x0610 0x3 0x0 +#define MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 0x0094 0x0304 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_GDCLK__GPIO2_IO24 0x0094 0x0304 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_GDCLK__LCD_DATA23 0x0094 0x0304 0x0694 0x6 0x1 +#define MX7D_PAD_EPDC_GDCLK__LCD_DATA16 0x0094 0x0304 0x0678 0x7 0x1 +#define MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x0098 0x0308 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_GDOE__FLEXTIMER2_CH1 0x0098 0x0308 0x05B0 0x1 0x0 +#define MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x0098 0x0308 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_GDOE__KPP_ROW7 0x0098 0x0308 0x0630 0x3 0x0 +#define MX7D_PAD_EPDC_GDOE__EIM_ADDR19 0x0098 0x0308 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_GDOE__GPIO2_IO25 0x0098 0x0308 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_GDOE__LCD_WR_RWN 0x0098 0x0308 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_GDOE__LCD_DATA18 0x0098 0x0308 0x0680 0x7 0x1 +#define MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x009C 0x030C 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_GDRL__FLEXTIMER2_CH2 0x009C 0x030C 0x05B4 0x1 0x0 +#define MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x009C 0x030C 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_GDRL__EIM_ADDR20 0x009C 0x030C 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x009C 0x030C 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_GDRL__LCD_RD_E 0x009C 0x030C 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_GDRL__LCD_DATA19 0x009C 0x030C 0x0684 0x7 0x1 +#define MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x00A0 0x0310 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_GDSP__FLEXTIMER2_CH3 0x00A0 0x0310 0x05B8 0x1 0x0 +#define MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x00A0 0x0310 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_GDSP__ENET2_TX_ER 0x00A0 0x0310 0x0000 0x3 0x0 +#define MX7D_PAD_EPDC_GDSP__EIM_ADDR21 0x00A0 0x0310 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x00A0 0x0310 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_GDSP__LCD_BUSY 0x00A0 0x0310 0x0634 0x6 0x1 +#define MX7D_PAD_EPDC_GDSP__LCD_DATA17 0x00A0 0x0310 0x067C 0x7 0x1 +#define MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x00A4 0x0314 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_BDR0__ENET2_TX_CLK 0x00A4 0x0314 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_BDR0__CCM_ENET_REF_CLK2 0x00A4 0x0314 0x0570 0x3 0x1 +#define MX7D_PAD_EPDC_BDR0__EIM_ADDR22 0x00A4 0x0314 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x00A4 0x0314 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_BDR0__LCD_CS 0x00A4 0x0314 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_BDR0__LCD_DATA7 0x00A4 0x0314 0x0654 0x7 0x1 +#define MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x00A8 0x0318 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_BDR1__EPDC_SDCLKN 0x00A8 0x0318 0x0000 0x1 0x0 +#define MX7D_PAD_EPDC_BDR1__ENET2_RX_CLK 0x00A8 0x0318 0x0578 0x2 0x1 +#define MX7D_PAD_EPDC_BDR1__EIM_AD8 0x00A8 0x0318 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x00A8 0x0318 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_BDR1__LCD_ENABLE 0x00A8 0x0318 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_BDR1__LCD_DATA6 0x00A8 0x0318 0x0650 0x7 0x1 +#define MX7D_PAD_EPDC_PWR_COM__EPDC_PWR_COM 0x00AC 0x031C 0x0000 0x0 0x0 +#define MX7D_PAD_EPDC_PWR_COM__FLEXTIMER2_PHA 0x00AC 0x031C 0x05CC 0x1 0x0 +#define MX7D_PAD_EPDC_PWR_COM__ENET2_CRS 0x00AC 0x031C 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_PWR_COM__EIM_AD9 0x00AC 0x031C 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x00AC 0x031C 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC 0x00AC 0x031C 0x0000 0x6 0x0 +#define MX7D_PAD_EPDC_PWR_COM__LCD_DATA11 0x00AC 0x031C 0x0664 0x7 0x1 +#define MX7D_PAD_EPDC_PWR_STAT__EPDC_PWR_STAT 0x00B0 0x0320 0x0580 0x0 0x0 +#define MX7D_PAD_EPDC_PWR_STAT__FLEXTIMER2_PHB 0x00B0 0x0320 0x05D0 0x1 0x0 +#define MX7D_PAD_EPDC_PWR_STAT__ENET2_COL 0x00B0 0x0320 0x0000 0x2 0x0 +#define MX7D_PAD_EPDC_PWR_STAT__EIM_EB_B1 0x00B0 0x0320 0x0000 0x4 0x0 +#define MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x00B0 0x0320 0x0000 0x5 0x0 +#define MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC 0x00B0 0x0320 0x0698 0x6 0x1 +#define MX7D_PAD_EPDC_PWR_STAT__LCD_DATA12 0x00B0 0x0320 0x0668 0x7 0x1 +#define MX7D_PAD_LCD_CLK__LCD_CLK 0x00B4 0x0324 0x0000 0x0 0x0 +#define MX7D_PAD_LCD_CLK__ECSPI4_MISO 0x00B4 0x0324 0x0558 0x1 0x0 +#define MX7D_PAD_LCD_CLK__ENET1_1588_EVENT2_IN 0x00B4 0x0324 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_CLK__CSI_DATA16 0x00B4 0x0324 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_CLK__UART2_DCE_RX 0x00B4 0x0324 0x06FC 0x4 0x0 +#define MX7D_PAD_LCD_CLK__UART2_DTE_TX 0x00B4 0x0324 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_CLK__GPIO3_IO0 0x00B4 0x0324 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x00B8 0x0328 0x0000 0x0 0x0 +#define MX7D_PAD_LCD_ENABLE__ECSPI4_MOSI 0x00B8 0x0328 0x055C 0x1 0x0 +#define MX7D_PAD_LCD_ENABLE__ENET1_1588_EVENT3_IN 0x00B8 0x0328 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_ENABLE__CSI_DATA17 0x00B8 0x0328 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_ENABLE__UART2_DCE_TX 0x00B8 0x0328 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_ENABLE__UART2_DTE_RX 0x00B8 0x0328 0x06FC 0x4 0x1 +#define MX7D_PAD_LCD_ENABLE__GPIO3_IO1 0x00B8 0x0328 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x00BC 0x032C 0x0000 0x0 0x0 +#define MX7D_PAD_LCD_HSYNC__ECSPI4_SCLK 0x00BC 0x032C 0x0554 0x1 0x0 +#define MX7D_PAD_LCD_HSYNC__ENET2_1588_EVENT2_IN 0x00BC 0x032C 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_HSYNC__CSI_DATA18 0x00BC 0x032C 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_HSYNC__UART2_DCE_RTS 0x00BC 0x032C 0x06F8 0x4 0x0 +#define MX7D_PAD_LCD_HSYNC__UART2_DTE_CTS 0x00BC 0x032C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_HSYNC__GPIO3_IO2 0x00BC 0x032C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x00C0 0x0330 0x0698 0x0 0x2 +#define MX7D_PAD_LCD_VSYNC__ECSPI4_SS0 0x00C0 0x0330 0x0560 0x1 0x0 +#define MX7D_PAD_LCD_VSYNC__ENET2_1588_EVENT3_IN 0x00C0 0x0330 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_VSYNC__CSI_DATA19 0x00C0 0x0330 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_VSYNC__UART2_DCE_CTS 0x00C0 0x0330 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_VSYNC__UART2_DTE_RTS 0x00C0 0x0330 0x06F8 0x4 0x1 +#define MX7D_PAD_LCD_VSYNC__GPIO3_IO3 0x00C0 0x0330 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_RESET__LCD_RESET 0x00C4 0x0334 0x0000 0x0 0x0 +#define MX7D_PAD_LCD_RESET__GPT1_COMPARE1 0x00C4 0x0334 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_RESET__ARM_PLATFORM_EVENTI 0x00C4 0x0334 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_RESET__CSI_FIELD 0x00C4 0x0334 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_RESET__EIM_DTACK_B 0x00C4 0x0334 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_RESET__GPIO3_IO4 0x00C4 0x0334 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA00__LCD_DATA0 0x00C8 0x0338 0x0638 0x0 0x2 +#define MX7D_PAD_LCD_DATA00__GPT1_COMPARE2 0x00C8 0x0338 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_DATA00__CSI_DATA20 0x00C8 0x0338 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA00__EIM_DATA0 0x00C8 0x0338 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA00__GPIO3_IO5 0x00C8 0x0338 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA00__SRC_BOOT_CFG0 0x00C8 0x0338 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA01__LCD_DATA1 0x00CC 0x033C 0x063C 0x0 0x2 +#define MX7D_PAD_LCD_DATA01__GPT1_COMPARE3 0x00CC 0x033C 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_DATA01__CSI_DATA21 0x00CC 0x033C 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA01__EIM_DATA1 0x00CC 0x033C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA01__GPIO3_IO6 0x00CC 0x033C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA01__SRC_BOOT_CFG1 0x00CC 0x033C 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA02__LCD_DATA2 0x00D0 0x0340 0x0640 0x0 0x2 +#define MX7D_PAD_LCD_DATA02__GPT1_CLK 0x00D0 0x0340 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_DATA02__CSI_DATA22 0x00D0 0x0340 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA02__EIM_DATA2 0x00D0 0x0340 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA02__GPIO3_IO7 0x00D0 0x0340 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA02__SRC_BOOT_CFG2 0x00D0 0x0340 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA03__LCD_DATA3 0x00D4 0x0344 0x0644 0x0 0x2 +#define MX7D_PAD_LCD_DATA03__GPT1_CAPTURE1 0x00D4 0x0344 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_DATA03__CSI_DATA23 0x00D4 0x0344 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA03__EIM_DATA3 0x00D4 0x0344 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA03__GPIO3_IO8 0x00D4 0x0344 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA03__SRC_BOOT_CFG3 0x00D4 0x0344 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA04__LCD_DATA4 0x00D8 0x0348 0x0648 0x0 0x2 +#define MX7D_PAD_LCD_DATA04__GPT1_CAPTURE2 0x00D8 0x0348 0x0000 0x1 0x0 +#define MX7D_PAD_LCD_DATA04__CSI_VSYNC 0x00D8 0x0348 0x0520 0x3 0x0 +#define MX7D_PAD_LCD_DATA04__EIM_DATA4 0x00D8 0x0348 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA04__GPIO3_IO9 0x00D8 0x0348 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA04__SRC_BOOT_CFG4 0x00D8 0x0348 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA05__LCD_DATA5 0x00DC 0x034C 0x064C 0x0 0x2 +#define MX7D_PAD_LCD_DATA05__CSI_HSYNC 0x00DC 0x034C 0x0518 0x3 0x0 +#define MX7D_PAD_LCD_DATA05__EIM_DATA5 0x00DC 0x034C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA05__GPIO3_IO10 0x00DC 0x034C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA05__SRC_BOOT_CFG5 0x00DC 0x034C 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA06__LCD_DATA6 0x00E0 0x0350 0x0650 0x0 0x2 +#define MX7D_PAD_LCD_DATA06__CSI_PIXCLK 0x00E0 0x0350 0x051C 0x3 0x0 +#define MX7D_PAD_LCD_DATA06__EIM_DATA6 0x00E0 0x0350 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA06__GPIO3_IO11 0x00E0 0x0350 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA06__SRC_BOOT_CFG6 0x00E0 0x0350 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA07__LCD_DATA7 0x00E4 0x0354 0x0654 0x0 0x2 +#define MX7D_PAD_LCD_DATA07__CSI_MCLK 0x00E4 0x0354 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA07__EIM_DATA7 0x00E4 0x0354 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA07__GPIO3_IO12 0x00E4 0x0354 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA07__SRC_BOOT_CFG7 0x00E4 0x0354 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA08__LCD_DATA8 0x00E8 0x0358 0x0658 0x0 0x2 +#define MX7D_PAD_LCD_DATA08__CSI_DATA9 0x00E8 0x0358 0x0514 0x3 0x0 +#define MX7D_PAD_LCD_DATA08__EIM_DATA8 0x00E8 0x0358 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA08__GPIO3_IO13 0x00E8 0x0358 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA08__SRC_BOOT_CFG8 0x00E8 0x0358 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA09__LCD_DATA9 0x00EC 0x035C 0x065C 0x0 0x2 +#define MX7D_PAD_LCD_DATA09__CSI_DATA8 0x00EC 0x035C 0x0510 0x3 0x0 +#define MX7D_PAD_LCD_DATA09__EIM_DATA9 0x00EC 0x035C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA09__GPIO3_IO14 0x00EC 0x035C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA09__SRC_BOOT_CFG9 0x00EC 0x035C 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA10__LCD_DATA10 0x00F0 0x0360 0x0660 0x0 0x2 +#define MX7D_PAD_LCD_DATA10__CSI_DATA7 0x00F0 0x0360 0x050C 0x3 0x0 +#define MX7D_PAD_LCD_DATA10__EIM_DATA10 0x00F0 0x0360 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA10__GPIO3_IO15 0x00F0 0x0360 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA10__SRC_BOOT_CFG10 0x00F0 0x0360 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA11__LCD_DATA11 0x00F4 0x0364 0x0664 0x0 0x2 +#define MX7D_PAD_LCD_DATA11__CSI_DATA6 0x00F4 0x0364 0x0508 0x3 0x0 +#define MX7D_PAD_LCD_DATA11__EIM_DATA11 0x00F4 0x0364 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA11__GPIO3_IO16 0x00F4 0x0364 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA11__SRC_BOOT_CFG11 0x00F4 0x0364 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA12__LCD_DATA12 0x00F8 0x0368 0x0668 0x0 0x2 +#define MX7D_PAD_LCD_DATA12__CSI_DATA5 0x00F8 0x0368 0x0504 0x3 0x0 +#define MX7D_PAD_LCD_DATA12__EIM_DATA12 0x00F8 0x0368 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA12__GPIO3_IO17 0x00F8 0x0368 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA12__SRC_BOOT_CFG12 0x00F8 0x0368 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA13__LCD_DATA13 0x00FC 0x036C 0x066C 0x0 0x1 +#define MX7D_PAD_LCD_DATA13__CSI_DATA4 0x00FC 0x036C 0x0500 0x3 0x0 +#define MX7D_PAD_LCD_DATA13__EIM_DATA13 0x00FC 0x036C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA13__GPIO3_IO18 0x00FC 0x036C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA13__SRC_BOOT_CFG13 0x00FC 0x036C 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA14__LCD_DATA14 0x0100 0x0370 0x0670 0x0 0x1 +#define MX7D_PAD_LCD_DATA14__CSI_DATA3 0x0100 0x0370 0x04FC 0x3 0x0 +#define MX7D_PAD_LCD_DATA14__EIM_DATA14 0x0100 0x0370 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA14__GPIO3_IO19 0x0100 0x0370 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA14__SRC_BOOT_CFG14 0x0100 0x0370 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA15__LCD_DATA15 0x0104 0x0374 0x0674 0x0 0x1 +#define MX7D_PAD_LCD_DATA15__CSI_DATA2 0x0104 0x0374 0x04F8 0x3 0x0 +#define MX7D_PAD_LCD_DATA15__EIM_DATA15 0x0104 0x0374 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA15__GPIO3_IO20 0x0104 0x0374 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA15__SRC_BOOT_CFG15 0x0104 0x0374 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA16__LCD_DATA16 0x0108 0x0378 0x0678 0x0 0x2 +#define MX7D_PAD_LCD_DATA16__FLEXTIMER1_CH4 0x0108 0x0378 0x0594 0x1 0x0 +#define MX7D_PAD_LCD_DATA16__CSI_DATA1 0x0108 0x0378 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA16__EIM_CRE 0x0108 0x0378 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA16__GPIO3_IO21 0x0108 0x0378 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA16__SRC_BOOT_CFG16 0x0108 0x0378 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA17__LCD_DATA17 0x010C 0x037C 0x067C 0x0 0x2 +#define MX7D_PAD_LCD_DATA17__FLEXTIMER1_CH5 0x010C 0x037C 0x0598 0x1 0x0 +#define MX7D_PAD_LCD_DATA17__CSI_DATA0 0x010C 0x037C 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA17__EIM_ACLK_FREERUN 0x010C 0x037C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA17__GPIO3_IO22 0x010C 0x037C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA17__SRC_BOOT_CFG17 0x010C 0x037C 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA18__LCD_DATA18 0x0110 0x0380 0x0680 0x0 0x2 +#define MX7D_PAD_LCD_DATA18__FLEXTIMER1_CH6 0x0110 0x0380 0x059C 0x1 0x0 +#define MX7D_PAD_LCD_DATA18__ARM_PLATFORM_EVENTO 0x0110 0x0380 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_DATA18__CSI_DATA15 0x0110 0x0380 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA18__EIM_CS2_B 0x0110 0x0380 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA18__GPIO3_IO23 0x0110 0x0380 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA18__SRC_BOOT_CFG18 0x0110 0x0380 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA19__EIM_CS3_B 0x0114 0x0384 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x0114 0x0384 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA19__SRC_BOOT_CFG19 0x0114 0x0384 0x0000 0x6 0x0 +#define MX7D_PAD_LCD_DATA19__LCD_DATA19 0x0114 0x0384 0x0684 0x0 0x2 +#define MX7D_PAD_LCD_DATA19__FLEXTIMER1_CH7 0x0114 0x0384 0x05A0 0x1 0x0 +#define MX7D_PAD_LCD_DATA19__CSI_DATA14 0x0114 0x0384 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA20__EIM_ADDR23 0x0118 0x0388 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x0118 0x0388 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA20__I2C3_SCL 0x0118 0x0388 0x05E4 0x6 0x1 +#define MX7D_PAD_LCD_DATA20__LCD_DATA20 0x0118 0x0388 0x0688 0x0 0x2 +#define MX7D_PAD_LCD_DATA20__FLEXTIMER2_CH4 0x0118 0x0388 0x05BC 0x1 0x0 +#define MX7D_PAD_LCD_DATA20__ENET1_1588_EVENT2_OUT 0x0118 0x0388 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_DATA20__CSI_DATA13 0x0118 0x0388 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA21__LCD_DATA21 0x011C 0x038C 0x068C 0x0 0x2 +#define MX7D_PAD_LCD_DATA21__FLEXTIMER2_CH5 0x011C 0x038C 0x05C0 0x1 0x0 +#define MX7D_PAD_LCD_DATA21__ENET1_1588_EVENT3_OUT 0x011C 0x038C 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_DATA21__CSI_DATA12 0x011C 0x038C 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA21__EIM_ADDR24 0x011C 0x038C 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x011C 0x038C 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA21__I2C3_SDA 0x011C 0x038C 0x05E8 0x6 0x1 +#define MX7D_PAD_LCD_DATA22__LCD_DATA22 0x0120 0x0390 0x0690 0x0 0x2 +#define MX7D_PAD_LCD_DATA22__FLEXTIMER2_CH6 0x0120 0x0390 0x05C4 0x1 0x0 +#define MX7D_PAD_LCD_DATA22__ENET2_1588_EVENT2_OUT 0x0120 0x0390 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_DATA22__CSI_DATA11 0x0120 0x0390 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA22__EIM_ADDR25 0x0120 0x0390 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x0120 0x0390 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA22__I2C4_SCL 0x0120 0x0390 0x05EC 0x6 0x1 +#define MX7D_PAD_LCD_DATA23__LCD_DATA23 0x0124 0x0394 0x0694 0x0 0x2 +#define MX7D_PAD_LCD_DATA23__FLEXTIMER2_CH7 0x0124 0x0394 0x05C8 0x1 0x0 +#define MX7D_PAD_LCD_DATA23__ENET2_1588_EVENT3_OUT 0x0124 0x0394 0x0000 0x2 0x0 +#define MX7D_PAD_LCD_DATA23__CSI_DATA10 0x0124 0x0394 0x0000 0x3 0x0 +#define MX7D_PAD_LCD_DATA23__EIM_ADDR26 0x0124 0x0394 0x0000 0x4 0x0 +#define MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x0124 0x0394 0x0000 0x5 0x0 +#define MX7D_PAD_LCD_DATA23__I2C4_SDA 0x0124 0x0394 0x05F0 0x6 0x1 +#define MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0128 0x0398 0x06F4 0x0 0x0 +#define MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0128 0x0398 0x0000 0x0 0x0 +#define MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x0128 0x0398 0x05D4 0x1 0x0 +#define MX7D_PAD_UART1_RX_DATA__CCM_PMIC_READY 0x0128 0x0398 0x0000 0x2 0x0 +#define MX7D_PAD_UART1_RX_DATA__ECSPI1_SS1 0x0128 0x0398 0x0000 0x3 0x0 +#define MX7D_PAD_UART1_RX_DATA__ENET2_1588_EVENT0_IN 0x0128 0x0398 0x0000 0x4 0x0 +#define MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x0128 0x0398 0x0000 0x5 0x0 +#define MX7D_PAD_UART1_RX_DATA__ENET1_MDIO 0x0128 0x0398 0x0000 0x6 0x0 +#define MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x012C 0x039C 0x0000 0x0 0x0 +#define MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x012C 0x039C 0x06F4 0x0 0x1 +#define MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x012C 0x039C 0x05D8 0x1 0x0 +#define MX7D_PAD_UART1_TX_DATA__SAI3_MCLK 0x012C 0x039C 0x0000 0x2 0x0 +#define MX7D_PAD_UART1_TX_DATA__ECSPI1_SS2 0x012C 0x039C 0x0000 0x3 0x0 +#define MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x012C 0x039C 0x0000 0x4 0x0 +#define MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x012C 0x039C 0x0000 0x5 0x0 +#define MX7D_PAD_UART1_TX_DATA__ENET1_MDC 0x012C 0x039C 0x0000 0x6 0x0 +#define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2 +#define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0 +#define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0 +#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x0000 0x2 0x0 +#define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0 +#define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0 +#define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 +#define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO 0x0130 0x03A0 0x0000 0x6 0x0 +#define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0134 0x03A4 0x0000 0x0 0x0 +#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0134 0x03A4 0x06FC 0x0 0x3 +#define MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x0134 0x03A4 0x05E0 0x1 0x0 +#define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0 0x0134 0x03A4 0x06C8 0x2 0x0 +#define MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY 0x0134 0x03A4 0x0000 0x3 0x0 +#define MX7D_PAD_UART2_TX_DATA__ENET2_1588_EVENT1_OUT 0x0134 0x03A4 0x0000 0x4 0x0 +#define MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x0134 0x03A4 0x0000 0x5 0x0 +#define MX7D_PAD_UART2_TX_DATA__ENET2_MDC 0x0134 0x03A4 0x0000 0x6 0x0 +#define MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0138 0x03A8 0x0704 0x0 0x2 +#define MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x0138 0x03A8 0x0000 0x0 0x0 +#define MX7D_PAD_UART3_RX_DATA__USB_OTG1_OC 0x0138 0x03A8 0x072C 0x1 0x0 +#define MX7D_PAD_UART3_RX_DATA__SAI3_RX_SYNC 0x0138 0x03A8 0x06CC 0x2 0x0 +#define MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO 0x0138 0x03A8 0x0528 0x3 0x0 +#define MX7D_PAD_UART3_RX_DATA__ENET1_1588_EVENT0_IN 0x0138 0x03A8 0x0000 0x4 0x0 +#define MX7D_PAD_UART3_RX_DATA__GPIO4_IO4 0x0138 0x03A8 0x0000 0x5 0x0 +#define MX7D_PAD_UART3_RX_DATA__SD1_LCTL 0x0138 0x03A8 0x0000 0x6 0x0 +#define MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x013C 0x03AC 0x0000 0x0 0x0 +#define MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x013C 0x03AC 0x0704 0x0 0x3 +#define MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR 0x013C 0x03AC 0x0000 0x1 0x0 +#define MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x013C 0x03AC 0x06D0 0x2 0x0 +#define MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI 0x013C 0x03AC 0x052C 0x3 0x0 +#define MX7D_PAD_UART3_TX_DATA__ENET1_1588_EVENT0_OUT 0x013C 0x03AC 0x0000 0x4 0x0 +#define MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x013C 0x03AC 0x0000 0x5 0x0 +#define MX7D_PAD_UART3_TX_DATA__SD2_LCTL 0x013C 0x03AC 0x0000 0x6 0x0 +#define MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x0140 0x03B0 0x0700 0x0 0x2 +#define MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x0140 0x03B0 0x0000 0x0 0x0 +#define MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x0140 0x03B0 0x0728 0x1 0x0 +#define MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x0140 0x03B0 0x0000 0x2 0x0 +#define MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK 0x0140 0x03B0 0x0000 0x3 0x0 +#define MX7D_PAD_UART3_RTS_B__ENET1_1588_EVENT1_IN 0x0140 0x03B0 0x0000 0x4 0x0 +#define MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x0140 0x03B0 0x0000 0x5 0x0 +#define MX7D_PAD_UART3_RTS_B__SD3_LCTL 0x0140 0x03B0 0x0000 0x6 0x0 +#define MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x0144 0x03B4 0x0000 0x0 0x0 +#define MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x0144 0x03B4 0x0700 0x0 0x3 +#define MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR 0x0144 0x03B4 0x0000 0x1 0x0 +#define MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x0144 0x03B4 0x06D4 0x2 0x0 +#define MX7D_PAD_UART3_CTS_B__ECSPI1_SS0 0x0144 0x03B4 0x0530 0x3 0x0 +#define MX7D_PAD_UART3_CTS_B__ENET1_1588_EVENT1_OUT 0x0144 0x03B4 0x0000 0x4 0x0 +#define MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x0144 0x03B4 0x0000 0x5 0x0 +#define MX7D_PAD_UART3_CTS_B__SD1_VSELECT 0x0144 0x03B4 0x0000 0x6 0x0 +#define MX7D_PAD_I2C1_SCL__I2C1_SCL 0x0148 0x03B8 0x05D4 0x0 0x1 +#define MX7D_PAD_I2C1_SCL__UART4_DCE_CTS 0x0148 0x03B8 0x0000 0x1 0x0 +#define MX7D_PAD_I2C1_SCL__UART4_DTE_RTS 0x0148 0x03B8 0x0708 0x1 0x0 +#define MX7D_PAD_I2C1_SCL__FLEXCAN1_RX 0x0148 0x03B8 0x04DC 0x2 0x1 +#define MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x0148 0x03B8 0x0548 0x3 0x0 +#define MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x0148 0x03B8 0x0000 0x5 0x0 +#define MX7D_PAD_I2C1_SCL__SD2_VSELECT 0x0148 0x03B8 0x0000 0x6 0x0 +#define MX7D_PAD_I2C1_SDA__I2C1_SDA 0x014C 0x03BC 0x05D8 0x0 0x1 +#define MX7D_PAD_I2C1_SDA__UART4_DCE_RTS 0x014C 0x03BC 0x0708 0x1 0x1 +#define MX7D_PAD_I2C1_SDA__UART4_DTE_CTS 0x014C 0x03BC 0x0000 0x1 0x0 +#define MX7D_PAD_I2C1_SDA__FLEXCAN1_TX 0x014C 0x03BC 0x0000 0x2 0x0 +#define MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x014C 0x03BC 0x054C 0x3 0x0 +#define MX7D_PAD_I2C1_SDA__CCM_ENET_REF_CLK1 0x014C 0x03BC 0x0564 0x4 0x1 +#define MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x014C 0x03BC 0x0000 0x5 0x0 +#define MX7D_PAD_I2C1_SDA__SD3_VSELECT 0x014C 0x03BC 0x0000 0x6 0x0 +#define MX7D_PAD_I2C2_SCL__I2C2_SCL 0x0150 0x03C0 0x05DC 0x0 0x1 +#define MX7D_PAD_I2C2_SCL__UART4_DCE_RX 0x0150 0x03C0 0x070C 0x1 0x0 +#define MX7D_PAD_I2C2_SCL__UART4_DTE_TX 0x0150 0x03C0 0x0000 0x1 0x0 +#define MX7D_PAD_I2C2_SCL__WDOG3_WDOG_B 0x0150 0x03C0 0x0000 0x2 0x0 +#define MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x0150 0x03C0 0x0544 0x3 0x0 +#define MX7D_PAD_I2C2_SCL__CCM_ENET_REF_CLK2 0x0150 0x03C0 0x0570 0x4 0x2 +#define MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x0150 0x03C0 0x0000 0x5 0x0 +#define MX7D_PAD_I2C2_SCL__SD3_CD_B 0x0150 0x03C0 0x0738 0x6 0x1 +#define MX7D_PAD_I2C2_SDA__I2C2_SDA 0x0154 0x03C4 0x05E0 0x0 0x1 +#define MX7D_PAD_I2C2_SDA__UART4_DCE_TX 0x0154 0x03C4 0x0000 0x1 0x0 +#define MX7D_PAD_I2C2_SDA__UART4_DTE_RX 0x0154 0x03C4 0x070C 0x1 0x1 +#define MX7D_PAD_I2C2_SDA__WDOG3_WDOG_RST_B_DEB 0x0154 0x03C4 0x0000 0x2 0x0 +#define MX7D_PAD_I2C2_SDA__ECSPI3_SS0 0x0154 0x03C4 0x0550 0x3 0x0 +#define MX7D_PAD_I2C2_SDA__CCM_ENET_REF_CLK3 0x0154 0x03C4 0x0000 0x4 0x0 +#define MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x0154 0x03C4 0x0000 0x5 0x0 +#define MX7D_PAD_I2C2_SDA__SD3_WP 0x0154 0x03C4 0x073C 0x6 0x1 +#define MX7D_PAD_I2C3_SCL__I2C3_SCL 0x0158 0x03C8 0x05E4 0x0 0x2 +#define MX7D_PAD_I2C3_SCL__UART5_DCE_CTS 0x0158 0x03C8 0x0000 0x1 0x0 +#define MX7D_PAD_I2C3_SCL__UART5_DTE_RTS 0x0158 0x03C8 0x0710 0x1 0x0 +#define MX7D_PAD_I2C3_SCL__FLEXCAN2_RX 0x0158 0x03C8 0x04E0 0x2 0x1 +#define MX7D_PAD_I2C3_SCL__CSI_VSYNC 0x0158 0x03C8 0x0520 0x3 0x1 +#define MX7D_PAD_I2C3_SCL__SDMA_EXT_EVENT0 0x0158 0x03C8 0x06D8 0x4 0x1 +#define MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x0158 0x03C8 0x0000 0x5 0x0 +#define MX7D_PAD_I2C3_SCL__EPDC_BDR0 0x0158 0x03C8 0x0000 0x6 0x0 +#define MX7D_PAD_I2C3_SDA__I2C3_SDA 0x015C 0x03CC 0x05E8 0x0 0x2 +#define MX7D_PAD_I2C3_SDA__UART5_DCE_RTS 0x015C 0x03CC 0x0710 0x1 0x1 +#define MX7D_PAD_I2C3_SDA__UART5_DTE_CTS 0x015C 0x03CC 0x0000 0x1 0x0 +#define MX7D_PAD_I2C3_SDA__FLEXCAN2_TX 0x015C 0x03CC 0x0000 0x2 0x0 +#define MX7D_PAD_I2C3_SDA__CSI_HSYNC 0x015C 0x03CC 0x0518 0x3 0x1 +#define MX7D_PAD_I2C3_SDA__SDMA_EXT_EVENT1 0x015C 0x03CC 0x06DC 0x4 0x1 +#define MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x015C 0x03CC 0x0000 0x5 0x0 +#define MX7D_PAD_I2C3_SDA__EPDC_BDR1 0x015C 0x03CC 0x0000 0x6 0x0 +#define MX7D_PAD_I2C4_SCL__I2C4_SCL 0x0160 0x03D0 0x05EC 0x0 0x2 +#define MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x0160 0x03D0 0x0714 0x1 0x0 +#define MX7D_PAD_I2C4_SCL__UART5_DTE_TX 0x0160 0x03D0 0x0000 0x1 0x0 +#define MX7D_PAD_I2C4_SCL__WDOG4_WDOG_B 0x0160 0x03D0 0x0000 0x2 0x0 +#define MX7D_PAD_I2C4_SCL__CSI_PIXCLK 0x0160 0x03D0 0x051C 0x3 0x1 +#define MX7D_PAD_I2C4_SCL__USB_OTG1_ID 0x0160 0x03D0 0x0734 0x4 0x1 +#define MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x0160 0x03D0 0x0000 0x5 0x0 +#define MX7D_PAD_I2C4_SCL__EPDC_VCOM0 0x0160 0x03D0 0x0000 0x6 0x0 +#define MX7D_PAD_I2C4_SDA__I2C4_SDA 0x0164 0x03D4 0x05F0 0x0 0x2 +#define MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x0164 0x03D4 0x0000 0x1 0x0 +#define MX7D_PAD_I2C4_SDA__UART5_DTE_RX 0x0164 0x03D4 0x0714 0x1 0x1 +#define MX7D_PAD_I2C4_SDA__WDOG4_WDOG_RST_B_DEB 0x0164 0x03D4 0x0000 0x2 0x0 +#define MX7D_PAD_I2C4_SDA__CSI_MCLK 0x0164 0x03D4 0x0000 0x3 0x0 +#define MX7D_PAD_I2C4_SDA__USB_OTG2_ID 0x0164 0x03D4 0x0730 0x4 0x1 +#define MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x0164 0x03D4 0x0000 0x5 0x0 +#define MX7D_PAD_I2C4_SDA__EPDC_VCOM1 0x0164 0x03D4 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x0168 0x03D8 0x0524 0x0 0x1 +#define MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x0168 0x03D8 0x071C 0x1 0x2 +#define MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x0168 0x03D8 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x0168 0x03D8 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI1_SCLK__CSI_DATA2 0x0168 0x03D8 0x04F8 0x3 0x1 +#define MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x0168 0x03D8 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI1_SCLK__EPDC_PWR_COM 0x0168 0x03D8 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x016C 0x03DC 0x052C 0x0 0x1 +#define MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x016C 0x03DC 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x016C 0x03DC 0x071C 0x1 0x3 +#define MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x016C 0x03DC 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI1_MOSI__CSI_DATA3 0x016C 0x03DC 0x04FC 0x3 0x1 +#define MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x016C 0x03DC 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI1_MOSI__EPDC_PWR_STAT 0x016C 0x03DC 0x0580 0x6 0x1 +#define MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x0170 0x03E0 0x0528 0x0 0x1 +#define MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x0170 0x03E0 0x0718 0x1 0x2 +#define MX7D_PAD_ECSPI1_MISO__UART6_DTE_CTS 0x0170 0x03E0 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x0170 0x03E0 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI1_MISO__CSI_DATA4 0x0170 0x03E0 0x0500 0x3 0x1 +#define MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x0170 0x03E0 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI1_MISO__EPDC_PWR_IRQ 0x0170 0x03E0 0x057C 0x6 0x0 +#define MX7D_PAD_ECSPI1_SS0__ECSPI1_SS0 0x0174 0x03E4 0x0530 0x0 0x1 +#define MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x0174 0x03E4 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI1_SS0__UART6_DTE_RTS 0x0174 0x03E4 0x0718 0x1 0x3 +#define MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x0174 0x03E4 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI1_SS0__CSI_DATA5 0x0174 0x03E4 0x0504 0x3 0x1 +#define MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x0174 0x03E4 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI1_SS0__EPDC_PWR_CTRL3 0x0174 0x03E4 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x0178 0x03E8 0x0534 0x0 0x0 +#define MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x0178 0x03E8 0x0724 0x1 0x2 +#define MX7D_PAD_ECSPI2_SCLK__UART7_DTE_TX 0x0178 0x03E8 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 0x0178 0x03E8 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI2_SCLK__CSI_DATA6 0x0178 0x03E8 0x0508 0x3 0x1 +#define MX7D_PAD_ECSPI2_SCLK__LCD_DATA13 0x0178 0x03E8 0x066C 0x4 0x2 +#define MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x0178 0x03E8 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI2_SCLK__EPDC_PWR_CTRL0 0x0178 0x03E8 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x017C 0x03EC 0x053C 0x0 0x0 +#define MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x017C 0x03EC 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI2_MOSI__UART7_DTE_RX 0x017C 0x03EC 0x0724 0x1 0x3 +#define MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 0x017C 0x03EC 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI2_MOSI__CSI_DATA7 0x017C 0x03EC 0x050C 0x3 0x1 +#define MX7D_PAD_ECSPI2_MOSI__LCD_DATA14 0x017C 0x03EC 0x0670 0x4 0x2 +#define MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x017C 0x03EC 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI2_MOSI__EPDC_PWR_CTRL1 0x017C 0x03EC 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x0180 0x03F0 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI2_MISO__EPDC_PWR_CTRL2 0x0180 0x03F0 0x0000 0x6 0x0 +#define MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x0180 0x03F0 0x0538 0x0 0x0 +#define MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x0180 0x03F0 0x0720 0x1 0x2 +#define MX7D_PAD_ECSPI2_MISO__UART7_DTE_CTS 0x0180 0x03F0 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI2_MISO__SD1_DATA6 0x0180 0x03F0 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI2_MISO__CSI_DATA8 0x0180 0x03F0 0x0510 0x3 0x1 +#define MX7D_PAD_ECSPI2_MISO__LCD_DATA15 0x0180 0x03F0 0x0674 0x4 0x2 +#define MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x0184 0x03F4 0x0540 0x0 0x0 +#define MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x0184 0x03F4 0x0000 0x1 0x0 +#define MX7D_PAD_ECSPI2_SS0__UART7_DTE_RTS 0x0184 0x03F4 0x0720 0x1 0x3 +#define MX7D_PAD_ECSPI2_SS0__SD1_DATA7 0x0184 0x03F4 0x0000 0x2 0x0 +#define MX7D_PAD_ECSPI2_SS0__CSI_DATA9 0x0184 0x03F4 0x0514 0x3 0x1 +#define MX7D_PAD_ECSPI2_SS0__LCD_RESET 0x0184 0x03F4 0x0000 0x4 0x0 +#define MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x0184 0x03F4 0x0000 0x5 0x0 +#define MX7D_PAD_ECSPI2_SS0__EPDC_PWR_WAKE 0x0184 0x03F4 0x0000 0x6 0x0 +#define MX7D_PAD_SD1_CD_B__SD1_CD_B 0x0188 0x03F8 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_CD_B__UART6_DCE_RX 0x0188 0x03F8 0x071C 0x2 0x4 +#define MX7D_PAD_SD1_CD_B__UART6_DTE_TX 0x0188 0x03F8 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_CD_B__ECSPI4_MISO 0x0188 0x03F8 0x0558 0x3 0x1 +#define MX7D_PAD_SD1_CD_B__FLEXTIMER1_CH0 0x0188 0x03F8 0x0584 0x4 0x1 +#define MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x0188 0x03F8 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_CD_B__CCM_CLKO1 0x0188 0x03F8 0x0000 0x6 0x0 +#define MX7D_PAD_SD1_WP__SD1_WP 0x018C 0x03FC 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_WP__UART6_DCE_TX 0x018C 0x03FC 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_WP__UART6_DTE_RX 0x018C 0x03FC 0x071C 0x2 0x5 +#define MX7D_PAD_SD1_WP__ECSPI4_MOSI 0x018C 0x03FC 0x055C 0x3 0x1 +#define MX7D_PAD_SD1_WP__FLEXTIMER1_CH1 0x018C 0x03FC 0x0588 0x4 0x1 +#define MX7D_PAD_SD1_WP__GPIO5_IO1 0x018C 0x03FC 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_WP__CCM_CLKO2 0x018C 0x03FC 0x0000 0x6 0x0 +#define MX7D_PAD_SD1_RESET_B__SD1_RESET_B 0x0190 0x0400 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_RESET_B__SAI3_MCLK 0x0190 0x0400 0x0000 0x1 0x0 +#define MX7D_PAD_SD1_RESET_B__UART6_DCE_RTS 0x0190 0x0400 0x0718 0x2 0x4 +#define MX7D_PAD_SD1_RESET_B__UART6_DTE_CTS 0x0190 0x0400 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK 0x0190 0x0400 0x0554 0x3 0x1 +#define MX7D_PAD_SD1_RESET_B__FLEXTIMER1_CH2 0x0190 0x0400 0x058C 0x4 0x1 +#define MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x0190 0x0400 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_CLK__SD1_CLK 0x0194 0x0404 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_CLK__SAI3_RX_SYNC 0x0194 0x0404 0x06CC 0x1 0x1 +#define MX7D_PAD_SD1_CLK__UART6_DCE_CTS 0x0194 0x0404 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_CLK__UART6_DTE_RTS 0x0194 0x0404 0x0718 0x2 0x5 +#define MX7D_PAD_SD1_CLK__ECSPI4_SS0 0x0194 0x0404 0x0560 0x3 0x1 +#define MX7D_PAD_SD1_CLK__FLEXTIMER1_CH3 0x0194 0x0404 0x0590 0x4 0x1 +#define MX7D_PAD_SD1_CLK__GPIO5_IO3 0x0194 0x0404 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_CMD__SD1_CMD 0x0198 0x0408 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_CMD__SAI3_RX_BCLK 0x0198 0x0408 0x06C4 0x1 0x1 +#define MX7D_PAD_SD1_CMD__ECSPI4_SS1 0x0198 0x0408 0x0000 0x3 0x0 +#define MX7D_PAD_SD1_CMD__FLEXTIMER2_CH0 0x0198 0x0408 0x05AC 0x4 0x1 +#define MX7D_PAD_SD1_CMD__GPIO5_IO4 0x0198 0x0408 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_DATA0__SD1_DATA0 0x019C 0x040C 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_DATA0__SAI3_RX_DATA0 0x019C 0x040C 0x06C8 0x1 0x1 +#define MX7D_PAD_SD1_DATA0__UART7_DCE_RX 0x019C 0x040C 0x0724 0x2 0x4 +#define MX7D_PAD_SD1_DATA0__UART7_DTE_TX 0x019C 0x040C 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_DATA0__ECSPI4_SS2 0x019C 0x040C 0x0000 0x3 0x0 +#define MX7D_PAD_SD1_DATA0__FLEXTIMER2_CH1 0x019C 0x040C 0x05B0 0x4 0x1 +#define MX7D_PAD_SD1_DATA0__GPIO5_IO5 0x019C 0x040C 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_DATA0__CCM_EXT_CLK1 0x019C 0x040C 0x04E4 0x6 0x1 +#define MX7D_PAD_SD1_DATA1__SD1_DATA1 0x01A0 0x0410 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_DATA1__SAI3_TX_BCLK 0x01A0 0x0410 0x06D0 0x1 0x1 +#define MX7D_PAD_SD1_DATA1__UART7_DCE_TX 0x01A0 0x0410 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_DATA1__UART7_DTE_RX 0x01A0 0x0410 0x0724 0x2 0x5 +#define MX7D_PAD_SD1_DATA1__ECSPI4_SS3 0x01A0 0x0410 0x0000 0x3 0x0 +#define MX7D_PAD_SD1_DATA1__FLEXTIMER2_CH2 0x01A0 0x0410 0x05B4 0x4 0x1 +#define MX7D_PAD_SD1_DATA1__GPIO5_IO6 0x01A0 0x0410 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_DATA1__CCM_EXT_CLK2 0x01A0 0x0410 0x04E8 0x6 0x1 +#define MX7D_PAD_SD1_DATA2__SD1_DATA2 0x01A4 0x0414 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_DATA2__SAI3_TX_SYNC 0x01A4 0x0414 0x06D4 0x1 0x1 +#define MX7D_PAD_SD1_DATA2__UART7_DCE_CTS 0x01A4 0x0414 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_DATA2__UART7_DTE_RTS 0x01A4 0x0414 0x0720 0x2 0x4 +#define MX7D_PAD_SD1_DATA2__ECSPI4_RDY 0x01A4 0x0414 0x0000 0x3 0x0 +#define MX7D_PAD_SD1_DATA2__FLEXTIMER2_CH3 0x01A4 0x0414 0x05B8 0x4 0x1 +#define MX7D_PAD_SD1_DATA2__GPIO5_IO7 0x01A4 0x0414 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_DATA2__CCM_EXT_CLK3 0x01A4 0x0414 0x04EC 0x6 0x1 +#define MX7D_PAD_SD1_DATA3__SD1_DATA3 0x01A8 0x0418 0x0000 0x0 0x0 +#define MX7D_PAD_SD1_DATA3__SAI3_TX_DATA0 0x01A8 0x0418 0x0000 0x1 0x0 +#define MX7D_PAD_SD1_DATA3__UART7_DCE_RTS 0x01A8 0x0418 0x0720 0x2 0x5 +#define MX7D_PAD_SD1_DATA3__UART7_DTE_CTS 0x01A8 0x0418 0x0000 0x2 0x0 +#define MX7D_PAD_SD1_DATA3__ECSPI3_SS1 0x01A8 0x0418 0x0000 0x3 0x0 +#define MX7D_PAD_SD1_DATA3__FLEXTIMER1_PHA 0x01A8 0x0418 0x05A4 0x4 0x1 +#define MX7D_PAD_SD1_DATA3__GPIO5_IO8 0x01A8 0x0418 0x0000 0x5 0x0 +#define MX7D_PAD_SD1_DATA3__CCM_EXT_CLK4 0x01A8 0x0418 0x04F0 0x6 0x1 +#define MX7D_PAD_SD2_CD_B__SD2_CD_B 0x01AC 0x041C 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x01AC 0x041C 0x0568 0x1 0x2 +#define MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x01AC 0x041C 0x0574 0x2 0x2 +#define MX7D_PAD_SD2_CD_B__ECSPI3_SS2 0x01AC 0x041C 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_CD_B__FLEXTIMER1_PHB 0x01AC 0x041C 0x05A8 0x4 0x1 +#define MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x01AC 0x041C 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_CD_B__SDMA_EXT_EVENT0 0x01AC 0x041C 0x06D8 0x6 0x2 +#define MX7D_PAD_SD2_WP__SD2_WP 0x01B0 0x0420 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_WP__ENET1_MDC 0x01B0 0x0420 0x0000 0x1 0x0 +#define MX7D_PAD_SD2_WP__ENET2_MDC 0x01B0 0x0420 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_WP__ECSPI3_SS3 0x01B0 0x0420 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_WP__USB_OTG1_ID 0x01B0 0x0420 0x0734 0x4 0x2 +#define MX7D_PAD_SD2_WP__GPIO5_IO10 0x01B0 0x0420 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_WP__SDMA_EXT_EVENT1 0x01B0 0x0420 0x06DC 0x6 0x2 +#define MX7D_PAD_SD2_RESET_B__SD2_RESET_B 0x01B4 0x0424 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_RESET_B__SAI2_MCLK 0x01B4 0x0424 0x0000 0x1 0x0 +#define MX7D_PAD_SD2_RESET_B__SD2_RESET 0x01B4 0x0424 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_RESET_B__ECSPI3_RDY 0x01B4 0x0424 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_RESET_B__USB_OTG2_ID 0x01B4 0x0424 0x0730 0x4 0x2 +#define MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x01B4 0x0424 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_CLK__SD2_CLK 0x01B8 0x0428 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_CLK__SAI2_RX_SYNC 0x01B8 0x0428 0x06B8 0x1 0x0 +#define MX7D_PAD_SD2_CLK__MQS_RIGHT 0x01B8 0x0428 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_CLK__GPT4_CLK 0x01B8 0x0428 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_CLK__GPIO5_IO12 0x01B8 0x0428 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_CMD__SD2_CMD 0x01BC 0x042C 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_CMD__SAI2_RX_BCLK 0x01BC 0x042C 0x06B0 0x1 0x0 +#define MX7D_PAD_SD2_CMD__MQS_LEFT 0x01BC 0x042C 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_CMD__GPT4_CAPTURE1 0x01BC 0x042C 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_CMD__SIM2_PORT1_TRXD 0x01BC 0x042C 0x06EC 0x4 0x1 +#define MX7D_PAD_SD2_CMD__GPIO5_IO13 0x01BC 0x042C 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_DATA0__SD2_DATA0 0x01C0 0x0430 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_DATA0__SAI2_RX_DATA0 0x01C0 0x0430 0x06B4 0x1 0x0 +#define MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x01C0 0x0430 0x070C 0x2 0x2 +#define MX7D_PAD_SD2_DATA0__UART4_DTE_TX 0x01C0 0x0430 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_DATA0__GPT4_CAPTURE2 0x01C0 0x0430 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_DATA0__SIM2_PORT1_CLK 0x01C0 0x0430 0x0000 0x4 0x0 +#define MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x01C0 0x0430 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_DATA1__SD2_DATA1 0x01C4 0x0434 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_DATA1__SAI2_TX_BCLK 0x01C4 0x0434 0x06BC 0x1 0x0 +#define MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x01C4 0x0434 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_DATA1__UART4_DTE_RX 0x01C4 0x0434 0x070C 0x2 0x3 +#define MX7D_PAD_SD2_DATA1__GPT4_COMPARE1 0x01C4 0x0434 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_DATA1__SIM2_PORT1_RST_B 0x01C4 0x0434 0x0000 0x4 0x0 +#define MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x01C4 0x0434 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_DATA2__SD2_DATA2 0x01C8 0x0438 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_DATA2__SAI2_TX_SYNC 0x01C8 0x0438 0x06C0 0x1 0x0 +#define MX7D_PAD_SD2_DATA2__UART4_DCE_CTS 0x01C8 0x0438 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_DATA2__UART4_DTE_RTS 0x01C8 0x0438 0x0708 0x2 0x2 +#define MX7D_PAD_SD2_DATA2__GPT4_COMPARE2 0x01C8 0x0438 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_DATA2__SIM2_PORT1_SVEN 0x01C8 0x0438 0x0000 0x4 0x0 +#define MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x01C8 0x0438 0x0000 0x5 0x0 +#define MX7D_PAD_SD2_DATA3__SD2_DATA3 0x01CC 0x043C 0x0000 0x0 0x0 +#define MX7D_PAD_SD2_DATA3__SAI2_TX_DATA0 0x01CC 0x043C 0x0000 0x1 0x0 +#define MX7D_PAD_SD2_DATA3__UART4_DCE_RTS 0x01CC 0x043C 0x0708 0x2 0x3 +#define MX7D_PAD_SD2_DATA3__UART4_DTE_CTS 0x01CC 0x043C 0x0000 0x2 0x0 +#define MX7D_PAD_SD2_DATA3__GPT4_COMPARE3 0x01CC 0x043C 0x0000 0x3 0x0 +#define MX7D_PAD_SD2_DATA3__SIM2_PORT1_PD 0x01CC 0x043C 0x06E8 0x4 0x1 +#define MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x01CC 0x043C 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_CLK__SD3_CLK 0x01D0 0x0440 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_CLK__NAND_CLE 0x01D0 0x0440 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_CLK__ECSPI4_MISO 0x01D0 0x0440 0x0558 0x2 0x2 +#define MX7D_PAD_SD3_CLK__SAI3_RX_SYNC 0x01D0 0x0440 0x06CC 0x3 0x2 +#define MX7D_PAD_SD3_CLK__GPT3_CLK 0x01D0 0x0440 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_CLK__GPIO6_IO0 0x01D0 0x0440 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_CMD__SD3_CMD 0x01D4 0x0444 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_CMD__NAND_ALE 0x01D4 0x0444 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_CMD__ECSPI4_MOSI 0x01D4 0x0444 0x055C 0x2 0x2 +#define MX7D_PAD_SD3_CMD__SAI3_RX_BCLK 0x01D4 0x0444 0x06C4 0x3 0x2 +#define MX7D_PAD_SD3_CMD__GPT3_CAPTURE1 0x01D4 0x0444 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_CMD__GPIO6_IO1 0x01D4 0x0444 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA0__SD3_DATA0 0x01D8 0x0448 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA0__NAND_DATA00 0x01D8 0x0448 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA0__ECSPI4_SS0 0x01D8 0x0448 0x0560 0x2 0x2 +#define MX7D_PAD_SD3_DATA0__SAI3_RX_DATA0 0x01D8 0x0448 0x06C8 0x3 0x2 +#define MX7D_PAD_SD3_DATA0__GPT3_CAPTURE2 0x01D8 0x0448 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA0__GPIO6_IO2 0x01D8 0x0448 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA1__SD3_DATA1 0x01DC 0x044C 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA1__NAND_DATA01 0x01DC 0x044C 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA1__ECSPI4_SCLK 0x01DC 0x044C 0x0554 0x2 0x2 +#define MX7D_PAD_SD3_DATA1__SAI3_TX_BCLK 0x01DC 0x044C 0x06D0 0x3 0x2 +#define MX7D_PAD_SD3_DATA1__GPT3_COMPARE1 0x01DC 0x044C 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA1__GPIO6_IO3 0x01DC 0x044C 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA2__SD3_DATA2 0x01E0 0x0450 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA2__NAND_DATA02 0x01E0 0x0450 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA2__I2C3_SDA 0x01E0 0x0450 0x05E8 0x2 0x3 +#define MX7D_PAD_SD3_DATA2__SAI3_TX_SYNC 0x01E0 0x0450 0x06D4 0x3 0x2 +#define MX7D_PAD_SD3_DATA2__GPT3_COMPARE2 0x01E0 0x0450 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA2__GPIO6_IO4 0x01E0 0x0450 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA3__SD3_DATA3 0x01E4 0x0454 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA3__NAND_DATA03 0x01E4 0x0454 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA3__I2C3_SCL 0x01E4 0x0454 0x05E4 0x2 0x3 +#define MX7D_PAD_SD3_DATA3__SAI3_TX_DATA0 0x01E4 0x0454 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_DATA3__GPT3_COMPARE3 0x01E4 0x0454 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA3__GPIO6_IO5 0x01E4 0x0454 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA4__SD3_DATA4 0x01E8 0x0458 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA4__NAND_DATA04 0x01E8 0x0458 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA4__UART3_DCE_RX 0x01E8 0x0458 0x0704 0x3 0x4 +#define MX7D_PAD_SD3_DATA4__UART3_DTE_TX 0x01E8 0x0458 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_DATA4__FLEXCAN2_RX 0x01E8 0x0458 0x04E0 0x4 0x2 +#define MX7D_PAD_SD3_DATA4__GPIO6_IO6 0x01E8 0x0458 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA5__SD3_DATA5 0x01EC 0x045C 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA5__NAND_DATA05 0x01EC 0x045C 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA5__UART3_DCE_TX 0x01EC 0x045C 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_DATA5__UART3_DTE_RX 0x01EC 0x045C 0x0704 0x3 0x5 +#define MX7D_PAD_SD3_DATA5__FLEXCAN1_TX 0x01EC 0x045C 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA5__GPIO6_IO7 0x01EC 0x045C 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA6__SD3_DATA6 0x01F0 0x0460 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA6__NAND_DATA06 0x01F0 0x0460 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA6__SD3_WP 0x01F0 0x0460 0x073C 0x2 0x2 +#define MX7D_PAD_SD3_DATA6__UART3_DCE_RTS 0x01F0 0x0460 0x0700 0x3 0x4 +#define MX7D_PAD_SD3_DATA6__UART3_DTE_CTS 0x01F0 0x0460 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_DATA6__FLEXCAN2_TX 0x01F0 0x0460 0x0000 0x4 0x0 +#define MX7D_PAD_SD3_DATA6__GPIO6_IO8 0x01F0 0x0460 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_DATA7__SD3_DATA7 0x01F4 0x0464 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_DATA7__NAND_DATA07 0x01F4 0x0464 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_DATA7__SD3_CD_B 0x01F4 0x0464 0x0738 0x2 0x2 +#define MX7D_PAD_SD3_DATA7__UART3_DCE_CTS 0x01F4 0x0464 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_DATA7__UART3_DTE_RTS 0x01F4 0x0464 0x0700 0x3 0x5 +#define MX7D_PAD_SD3_DATA7__FLEXCAN1_RX 0x01F4 0x0464 0x04DC 0x4 0x2 +#define MX7D_PAD_SD3_DATA7__GPIO6_IO9 0x01F4 0x0464 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_STROBE__SD3_STROBE 0x01F8 0x0468 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_STROBE__NAND_RE_B 0x01F8 0x0468 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x01F8 0x0468 0x0000 0x5 0x0 +#define MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x01FC 0x046C 0x0000 0x0 0x0 +#define MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x01FC 0x046C 0x0000 0x1 0x0 +#define MX7D_PAD_SD3_RESET_B__SD3_RESET 0x01FC 0x046C 0x0000 0x2 0x0 +#define MX7D_PAD_SD3_RESET_B__SAI3_MCLK 0x01FC 0x046C 0x0000 0x3 0x0 +#define MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x01FC 0x046C 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x0200 0x0470 0x06A0 0x0 0x0 +#define MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x0200 0x0470 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x0200 0x0470 0x0714 0x2 0x2 +#define MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x0200 0x0470 0x0000 0x2 0x0 +#define MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x0200 0x0470 0x04DC 0x3 0x3 +#define MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x0200 0x0470 0x06E4 0x4 0x1 +#define MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x0200 0x0470 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_RX_DATA__SRC_ANY_PU_RESET 0x0200 0x0470 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x0204 0x0474 0x06A8 0x0 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x0204 0x0474 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x0204 0x0474 0x0000 0x2 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x0204 0x0474 0x0714 0x2 0x3 +#define MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x0204 0x0474 0x0000 0x3 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x0204 0x0474 0x0000 0x4 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x0204 0x0474 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_TX_BCLK__SRC_EARLY_RESET 0x0204 0x0474 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x0208 0x0478 0x06AC 0x0 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__NAND_DQS 0x0208 0x0478 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x0208 0x0478 0x0000 0x2 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__UART5_DTE_RTS 0x0208 0x0478 0x0710 0x2 0x2 +#define MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x0208 0x0478 0x04E0 0x3 0x3 +#define MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x0208 0x0478 0x0000 0x4 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 0x0208 0x0478 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_TX_SYNC__SRC_INT_BOOT 0x0208 0x0478 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x020C 0x047C 0x0000 0x0 0x0 +#define MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x020C 0x047C 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x020C 0x047C 0x0710 0x2 0x3 +#define MX7D_PAD_SAI1_TX_DATA__UART5_DTE_CTS 0x020C 0x047C 0x0000 0x2 0x0 +#define MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x020C 0x047C 0x0000 0x3 0x0 +#define MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x020C 0x047C 0x0000 0x4 0x0 +#define MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x020C 0x047C 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_TX_DATA__SRC_SYSTEM_RESET 0x020C 0x047C 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x0210 0x0480 0x06A4 0x0 0x0 +#define MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B 0x0210 0x0480 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_RX_SYNC__SAI2_RX_SYNC 0x0210 0x0480 0x06B8 0x2 0x1 +#define MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x0210 0x0480 0x05EC 0x3 0x3 +#define MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x0210 0x0480 0x06E0 0x4 0x1 +#define MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x0210 0x0480 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0210 0x0480 0x0000 0x6 0x0 +#define MX7D_PAD_SAI1_RX_SYNC__SRC_CA7_RESET_B0 0x0210 0x0480 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_RX_BCLK__SAI1_RX_BCLK 0x0214 0x0484 0x069C 0x0 0x0 +#define MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B 0x0214 0x0484 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_RX_BCLK__SAI2_RX_BCLK 0x0214 0x0484 0x06B0 0x2 0x1 +#define MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x0214 0x0484 0x05F0 0x3 0x3 +#define MX7D_PAD_SAI1_RX_BCLK__FLEXTIMER2_PHA 0x0214 0x0484 0x05CC 0x4 0x1 +#define MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x0214 0x0484 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0214 0x0484 0x0000 0x6 0x0 +#define MX7D_PAD_SAI1_RX_BCLK__SRC_CA7_RESET_B1 0x0214 0x0484 0x0000 0x7 0x0 +#define MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x0218 0x0488 0x0000 0x0 0x0 +#define MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x0218 0x0488 0x0000 0x1 0x0 +#define MX7D_PAD_SAI1_MCLK__SAI2_MCLK 0x0218 0x0488 0x0000 0x2 0x0 +#define MX7D_PAD_SAI1_MCLK__CCM_PMIC_READY 0x0218 0x0488 0x04F4 0x3 0x3 +#define MX7D_PAD_SAI1_MCLK__FLEXTIMER2_PHB 0x0218 0x0488 0x05D0 0x4 0x1 +#define MX7D_PAD_SAI1_MCLK__GPIO6_IO18 0x0218 0x0488 0x0000 0x5 0x0 +#define MX7D_PAD_SAI1_MCLK__SRC_TESTER_ACK 0x0218 0x0488 0x0000 0x7 0x0 +#define MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x021C 0x048C 0x06C0 0x0 0x1 +#define MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x021C 0x048C 0x0548 0x1 0x1 +#define MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x021C 0x048C 0x070C 0x2 0x4 +#define MX7D_PAD_SAI2_TX_SYNC__UART4_DTE_TX 0x021C 0x048C 0x0000 0x2 0x0 +#define MX7D_PAD_SAI2_TX_SYNC__UART1_DCE_CTS 0x021C 0x048C 0x0000 0x3 0x0 +#define MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x021C 0x048C 0x06F0 0x3 0x0 +#define MX7D_PAD_SAI2_TX_SYNC__FLEXTIMER2_CH4 0x021C 0x048C 0x05BC 0x4 0x1 +#define MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x021C 0x048C 0x0000 0x5 0x0 +#define MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x0220 0x0490 0x06BC 0x0 0x1 +#define MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x0220 0x0490 0x054C 0x1 0x1 +#define MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x0220 0x0490 0x0000 0x2 0x0 +#define MX7D_PAD_SAI2_TX_BCLK__UART4_DTE_RX 0x0220 0x0490 0x070C 0x2 0x5 +#define MX7D_PAD_SAI2_TX_BCLK__UART1_DCE_RTS 0x0220 0x0490 0x06F0 0x3 0x1 +#define MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x0220 0x0490 0x0000 0x3 0x0 +#define MX7D_PAD_SAI2_TX_BCLK__FLEXTIMER2_CH5 0x0220 0x0490 0x05C0 0x4 0x1 +#define MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20 0x0220 0x0490 0x0000 0x5 0x0 +#define MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x0224 0x0494 0x06B4 0x0 0x1 +#define MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x0224 0x0494 0x0544 0x1 0x1 +#define MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x0224 0x0494 0x0000 0x2 0x0 +#define MX7D_PAD_SAI2_RX_DATA__UART4_DTE_RTS 0x0224 0x0494 0x0708 0x2 0x4 +#define MX7D_PAD_SAI2_RX_DATA__UART2_DCE_CTS 0x0224 0x0494 0x0000 0x3 0x0 +#define MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x0224 0x0494 0x06F8 0x3 0x2 +#define MX7D_PAD_SAI2_RX_DATA__FLEXTIMER2_CH6 0x0224 0x0494 0x05C4 0x4 0x1 +#define MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x0224 0x0494 0x0000 0x5 0x0 +#define MX7D_PAD_SAI2_RX_DATA__KPP_COL7 0x0224 0x0494 0x0610 0x6 0x1 +#define MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x0228 0x0498 0x0000 0x0 0x0 +#define MX7D_PAD_SAI2_TX_DATA__ECSPI3_SS0 0x0228 0x0498 0x0550 0x1 0x1 +#define MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x0228 0x0498 0x0708 0x2 0x5 +#define MX7D_PAD_SAI2_TX_DATA__UART4_DTE_CTS 0x0228 0x0498 0x0000 0x2 0x0 +#define MX7D_PAD_SAI2_TX_DATA__UART2_DCE_RTS 0x0228 0x0498 0x06F8 0x3 0x3 +#define MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x0228 0x0498 0x0000 0x3 0x0 +#define MX7D_PAD_SAI2_TX_DATA__FLEXTIMER2_CH7 0x0228 0x0498 0x05C8 0x4 0x1 +#define MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 0x0228 0x0498 0x0000 0x5 0x0 +#define MX7D_PAD_SAI2_TX_DATA__KPP_ROW7 0x0228 0x0498 0x0630 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x022C 0x049C 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RD0__PWM1_OUT 0x022C 0x049C 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x022C 0x049C 0x05E4 0x2 0x4 +#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DCE_CTS 0x022C 0x049C 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_RD0__UART1_DTE_RTS 0x022C 0x049C 0x06F0 0x3 0x2 +#define MX7D_PAD_ENET1_RGMII_RD0__EPDC_VCOM0 0x022C 0x049C 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x022C 0x049C 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RD0__KPP_ROW3 0x022C 0x049C 0x0620 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x0230 0x04A0 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RD1__PWM2_OUT 0x0230 0x04A0 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x0230 0x04A0 0x05E8 0x2 0x4 +#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DCE_RTS 0x0230 0x04A0 0x06F0 0x3 0x3 +#define MX7D_PAD_ENET1_RGMII_RD1__UART1_DTE_CTS 0x0230 0x04A0 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_RD1__EPDC_VCOM1 0x0230 0x04A0 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0230 0x04A0 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RD1__KPP_COL3 0x0230 0x04A0 0x0600 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x0234 0x04A4 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x0234 0x04A4 0x04DC 0x1 0x4 +#define MX7D_PAD_ENET1_RGMII_RD2__ECSPI2_SCLK 0x0234 0x04A4 0x0534 0x2 0x1 +#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DCE_RX 0x0234 0x04A4 0x06F4 0x3 0x2 +#define MX7D_PAD_ENET1_RGMII_RD2__UART1_DTE_TX 0x0234 0x04A4 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_RD2__EPDC_SDCE4 0x0234 0x04A4 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x0234 0x04A4 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RD2__KPP_ROW2 0x0234 0x04A4 0x061C 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x0238 0x04A8 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x0238 0x04A8 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_RD3__ECSPI2_MOSI 0x0238 0x04A8 0x053C 0x2 0x1 +#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DCE_TX 0x0238 0x04A8 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_RD3__UART1_DTE_RX 0x0238 0x04A8 0x06F4 0x3 0x3 +#define MX7D_PAD_ENET1_RGMII_RD3__EPDC_SDCE5 0x0238 0x04A8 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x0238 0x04A8 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RD3__KPP_COL2 0x0238 0x04A8 0x05FC 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x023C 0x04AC 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__ECSPI2_SS1 0x023C 0x04AC 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__EPDC_SDCE6 0x023C 0x04AC 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x023C 0x04AC 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RX_CTL__KPP_ROW1 0x023C 0x04AC 0x0618 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x0240 0x04B0 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER 0x0240 0x04B0 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_RXC__ECSPI2_SS2 0x0240 0x04B0 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_RXC__EPDC_SDCE7 0x0240 0x04B0 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0240 0x04B0 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_RXC__KPP_COL1 0x0240 0x04B0 0x0000 0x6 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x0244 0x04B4 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__PWM3_OUT 0x0244 0x04B4 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__ECSPI2_SS3 0x0244 0x04B4 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__EPDC_SDCE8 0x0244 0x04B4 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0244 0x04B4 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_TD0__KPP_ROW0 0x0244 0x04B4 0x0614 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x0248 0x04B8 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TD1__PWM4_OUT 0x0248 0x04B8 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_TD1__ECSPI2_RDY 0x0248 0x04B8 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TD1__EPDC_SDCE9 0x0248 0x04B8 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0248 0x04B8 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_TD1__KPP_COL0 0x0248 0x04B8 0x05F4 0x6 0x1 +#define MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x024C 0x04BC 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TD2__FLEXCAN2_RX 0x024C 0x04BC 0x04E0 0x1 0x4 +#define MX7D_PAD_ENET1_RGMII_TD2__ECSPI2_MISO 0x024C 0x04BC 0x0538 0x2 0x1 +#define MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x024C 0x04BC 0x05EC 0x3 0x4 +#define MX7D_PAD_ENET1_RGMII_TD2__EPDC_SDOED 0x024C 0x04BC 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x024C 0x04BC 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x0250 0x04C0 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TD3__FLEXCAN2_TX 0x0250 0x04C0 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_TD3__ECSPI2_SS0 0x0250 0x04C0 0x0540 0x2 0x1 +#define MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x0250 0x04C0 0x05F0 0x3 0x4 +#define MX7D_PAD_ENET1_RGMII_TD3__EPDC_SDOEZ 0x0250 0x04C0 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x0250 0x04C0 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS 0x0250 0x04C0 0x0000 0x7 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x0254 0x04C4 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 0x0254 0x04C4 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 0x0254 0x04C4 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0254 0x04C4 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x0258 0x04C8 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER 0x0258 0x04C8 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 0x0258 0x04C8 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 0x0258 0x04C8 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x0258 0x04C8 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x025C 0x04CC 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 0x025C 0x04CC 0x0564 0x1 0x2 +#define MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x025C 0x04CC 0x06A0 0x2 0x1 +#define MX7D_PAD_ENET1_TX_CLK__GPT2_COMPARE3 0x025C 0x04CC 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_TX_CLK__EPDC_PWR_IRQ 0x025C 0x04CC 0x057C 0x4 0x1 +#define MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x025C 0x04CC 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_TX_CLK__CCM_EXT_CLK1 0x025C 0x04CC 0x04E4 0x6 0x2 +#define MX7D_PAD_ENET1_TX_CLK__CSU_ALARM_AUT0 0x025C 0x04CC 0x0000 0x7 0x0 +#define MX7D_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x0260 0x04D0 0x056C 0x0 0x0 +#define MX7D_PAD_ENET1_RX_CLK__WDOG2_WDOG_B 0x0260 0x04D0 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x0260 0x04D0 0x06A8 0x2 0x1 +#define MX7D_PAD_ENET1_RX_CLK__GPT2_CLK 0x0260 0x04D0 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_RX_CLK__EPDC_PWR_WAKE 0x0260 0x04D0 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x0260 0x04D0 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_RX_CLK__CCM_EXT_CLK2 0x0260 0x04D0 0x04E8 0x6 0x2 +#define MX7D_PAD_ENET1_RX_CLK__CSU_ALARM_AUT1 0x0260 0x04D0 0x0000 0x7 0x0 +#define MX7D_PAD_ENET1_CRS__ENET1_CRS 0x0264 0x04D4 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_CRS__WDOG2_WDOG_RST_B_DEB 0x0264 0x04D4 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x0264 0x04D4 0x06AC 0x2 0x1 +#define MX7D_PAD_ENET1_CRS__GPT2_CAPTURE1 0x0264 0x04D4 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_CRS__EPDC_PWR_CTRL0 0x0264 0x04D4 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x0264 0x04D4 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_CRS__CCM_EXT_CLK3 0x0264 0x04D4 0x04EC 0x6 0x2 +#define MX7D_PAD_ENET1_CRS__CSU_ALARM_AUT2 0x0264 0x04D4 0x0000 0x7 0x0 +#define MX7D_PAD_ENET1_COL__ENET1_COL 0x0268 0x04D8 0x0000 0x0 0x0 +#define MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY 0x0268 0x04D8 0x0000 0x1 0x0 +#define MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x0268 0x04D8 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_COL__GPT2_CAPTURE2 0x0268 0x04D8 0x0000 0x3 0x0 +#define MX7D_PAD_ENET1_COL__EPDC_PWR_CTRL1 0x0268 0x04D8 0x0000 0x4 0x0 +#define MX7D_PAD_ENET1_COL__GPIO7_IO15 0x0268 0x04D8 0x0000 0x5 0x0 +#define MX7D_PAD_ENET1_COL__CCM_EXT_CLK4 0x0268 0x04D8 0x04F0 0x6 0x2 +#define MX7D_PAD_ENET1_COL__CSU_INT_DEB 0x0268 0x04D8 0x0000 0x7 0x0 + +#endif /* __DTS_IMX7D_PINFUNC_H */ diff --git a/arch/arm/dts/vf.dtsi b/arch/arm/dts/vf.dtsi index d7d21a3..000aff2 100644 --- a/arch/arm/dts/vf.dtsi +++ b/arch/arm/dts/vf.dtsi @@ -83,7 +83,9 @@ #address-cells = <1>; #size-cells = <0>; compatible = "fsl,vf610-qspi"; - reg = <0x40044000 0x1000>; + reg = <0x40044000 0x1000>, + <0x20000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; status = "disabled"; }; diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index a33aa16..632faca 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -159,6 +159,8 @@ const char *get_imx_type(u32 imxtype) return "6SX"; /* SoloX version of the mx6 */ case MXC_CPU_MX6UL: return "6UL"; /* Ultra-Lite version of the mx6 */ + case MXC_CPU_MX6ULL: + return "6ULL"; /* ULL version of the mx6 */ case MXC_CPU_MX51: return "51"; case MXC_CPU_MX53: diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c index 3d2ce3a..e5dbd93 100644 --- a/arch/arm/imx-common/init.c +++ b/arch/arm/imx-common/init.c @@ -44,7 +44,7 @@ void init_aips(void) writel(0x00000000, &aips2->opacr3); writel(0x00000000, &aips2->opacr4); - if (is_mx6sx() || is_mx7()) { + if (is_mx6ull() || is_mx6sx() || is_mx7()) { /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 66137d1..392f4bc 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -42,6 +42,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) #ifdef CONFIG_IOMUX_LPSR u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT; +#ifdef CONFIG_MX7 if (lpsr == IOMUX_CONFIG_LPSR) { base = (void *)IOMUXC_LPSR_BASE_ADDR; mux_mode &= ~IOMUX_CONFIG_LPSR; @@ -49,9 +50,17 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) if (sel_input_ofs) sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS; } +#else + if (is_mx6ull()) { + if (lpsr == IOMUX_CONFIG_LPSR) { + base = (void *)IOMUXC_SNVS_BASE_ADDR; + mux_mode &= ~IOMUX_CONFIG_LPSR; + } + } +#endif #endif - if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs) + if (is_soc_type(MXC_SOC_MX7) || is_cpu_type(MXC_CPU_MX6ULL) || mux_ctrl_ofs) __raw_writel(mux_mode, base + mux_ctrl_ofs); if (sel_input_ofs) @@ -83,7 +92,7 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, #if defined(CONFIG_MX6QDL) stride = 2; - if (!is_mx6dq()) + if (!is_mx6dq() && !is_mx6dqp()) p += 1; #else stride = 1; diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index a01590c..fb1b693 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -44,7 +44,8 @@ static inline int gpt_has_clk_source_osc(void) { #if defined(CONFIG_MX6) if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) || - is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul()) + is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() || + is_mx6ull()) return 1; return 0; @@ -83,8 +84,8 @@ int timer_init(void) if (gpt_has_clk_source_osc()) { i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN; - /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */ - if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) { + /* For DL/S, SX, UL, ULL set 24Mhz OSC Enable bit and prescaler */ + if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull()) { i |= GPTCR_24MEN; /* Produce 3Mhz clock */ diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 62bca8c..dbed776 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -43,7 +43,8 @@ #define HS_DEVICE 0x2 #define GP_DEVICE 0x3 -/* cpu-id for AM33XX and TI81XX family */ +/* cpu-id for AM43XX AM33XX and TI81XX family */ +#define AM437X 0xB98C #define AM335X 0xB944 #define TI81XX 0xB81E #define DEVICE_ID (CTRL_BASE + 0x0600) @@ -579,6 +580,8 @@ struct pwmss_regs { }; #define ECAP_CLK_EN BIT(0) #define ECAP_CLK_STOP_REQ BIT(1) +#define EPWM_CLK_EN BIT(8) +#define EPWM_CLK_STOP_REQ BIT(9) struct pwmss_ecap_regs { unsigned int tsctr; @@ -592,6 +595,40 @@ struct pwmss_ecap_regs { unsigned short ecctl2; }; +struct pwmss_epwm_regs { + unsigned short tbctl; + unsigned short tbsts; + unsigned short tbphshr; + unsigned short tbphs; + unsigned short tbcnt; + unsigned short tbprd; + unsigned short res1; + unsigned short cmpctl; + unsigned short cmpahr; + unsigned short cmpa; + unsigned short cmpb; + unsigned short aqctla; + unsigned short aqctlb; + unsigned short aqsfrc; + unsigned short aqcsfrc; + unsigned short dbctl; + unsigned short dbred; + unsigned short dbfed; + unsigned short tzsel; + unsigned short tzctl; + unsigned short tzflg; + unsigned short tzclr; + unsigned short tzfrc; + unsigned short etsel; + unsigned short etps; + unsigned short etflg; + unsigned short etclr; + unsigned short etfrc; + unsigned short pcctl; + unsigned int res2[66]; + unsigned short hrcnfg; +}; + /* Capture Control register 2 */ #define ECTRL2_SYNCOSEL_MASK (0x03 << 6) #define ECTRL2_MDSL_ECAP BIT(9) diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h index d1aed58..fa9b84f 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am33xx.h @@ -67,5 +67,6 @@ /* PWMSS */ #define PWMSS0_BASE 0x48300000 #define AM33XX_ECAP0_BASE 0x48300100 +#define AM33XX_EPWM_BASE 0x48300200 #endif /* __AM33XX_HARDWARE_AM33XX_H */ diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 7c63c13..667115b0 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -17,7 +17,8 @@ #define MXC_CPU_MX6SX 0x62 #define MXC_CPU_MX6Q 0x63 #define MXC_CPU_MX6UL 0x64 -#define MXC_CPU_MX6SOLO 0x65 /* dummy ID */ +#define MXC_CPU_MX6ULL 0x65 +#define MXC_CPU_MX6SOLO 0x66 /* dummy */ #define MXC_CPU_MX6D 0x67 #define MXC_CPU_MX6DP 0x68 #define MXC_CPU_MX6QP 0x69 diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 22212c2..f74737a 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -379,6 +379,16 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) /* Define the bits in register CS1CDR */ +/* MX6UL, !MX6ULL */ +#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET 22 +#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS1CDR_SAI3_CLK_PODF_OFFSET 16 +#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS1CDR_SAI1_CLK_PRED_OFFSET 6 +#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_MASK 0x3F +#define MXC_CCM_CS1CDR_SAI1_CLK_PODF_OFFSET 0 + #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22) @@ -460,7 +470,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 /* Define the bits in register CHSCCDR */ -#ifdef CONFIG_MX6SX +/* i.MX6SX */ #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15) #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12) @@ -473,7 +483,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7) #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0 -#else + #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) @@ -486,7 +496,14 @@ struct mxc_ccm_reg { #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 -#endif + +/* i.MX6ULL */ +#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x7 << 15) +#define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET 15 +#define MXC_CCM_CHSCCDR_EPDC_PODF_MASK (0x7 << 12) +#define MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET 12 +#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK (0x7 << 9) +#define MXC_CCM_CHSCCDR_EPDC_CLK_SEL_OFFSET 9 #define CHSCCDR_CLK_SEL_LDB_DI0 3 #define CHSCCDR_PODF_DIVIDE_BY_3 2 @@ -626,6 +643,12 @@ struct mxc_ccm_reg { /* Define the bits in registers CCGRx */ #define MXC_CCM_CCGR_CG_MASK 3 +/* i.MX 6ULL */ +#define MXC_CCM_CCGR0_DCP_CLK_OFFSET 10 +#define MXC_CCM_CCGR0_DCP_CLK_MASK (3 << MXC_CCM_CCGR0_DCP_CLK_OFFSET) +#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET 12 +#define MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR0_ENET_CLK_ENABLE_OFFSET) + #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET) #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2 @@ -702,13 +725,12 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET) #endif -#ifndef CONFIG_MX6SX #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) -#else +/* i.MX6SX/UL */ #define MXC_CCM_CCGR2_CSI_OFFSET 2 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET) -#endif + #ifndef CONFIG_MX6SX #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) @@ -744,9 +766,18 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) +/* i.MX6ULL */ +#define MXC_CCM_CCGR2_ESAI_CLK_OFFSET 0 +#define MXC_CCM_CCGR2_ESAI_CLK_MASK (3 << MXC_CCM_CCGR2_ESAI_CLK_OFFSET) +#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET 4 +#define MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_MASK (3 << MXC_CCM_CCGR2_IOMUXC_SNVS_CLK_OFFSET) + /* Exist on i.MX6SX */ #define MXC_CCM_CCGR3_M4_OFFSET 2 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET) +/* i.MX6ULL */ +#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET 4 +#define MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_EPDC_CLK_ENABLE_OFFSET) #define MXC_CCM_CCGR3_ENET_OFFSET 4 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET) #define MXC_CCM_CCGR3_QSPI_OFFSET 14 @@ -808,7 +839,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR3_OCRAM_OFFSET 28 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) -/* GPIO4 on i.MX6UL */ +/* GPIO4 on i.MX6UL/ULL */ #define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30 #define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET) @@ -817,6 +848,10 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) #endif +/* i.MX6ULL */ +#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET 30 +#define MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_MASK (3 << MXC_CCM_CCGR3_IOMUXC_SNVS_GPR_CLK_OFFSET) + #define MXC_CCM_CCGR4_PCIE_OFFSET 0 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) /* QSPI2 on i.MX6SX */ @@ -883,6 +918,13 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) #define MXC_CCM_CCGR6_USDHC2_OFFSET 4 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) +#define MXC_CCM_CCGR6_SIM1_CLK_OFFSET 6 +#define MXC_CCM_CCGR6_SIM1_CLK_MASK (3 << MXC_CCM_CCGR6_SIM1_CLK_OFFSET) +#define MXC_CCM_CCGR6_SIM2_CLK_OFFSET 8 +#define MXC_CCM_CCGR6_SIM2_CLK_MASK (3 << MXC_CCM_CCGR6_SIM2_CLK_OFFSET) +/* i.MX6ULL */ +#define MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET 8 +#define MXC_CCM_CCGR6_IPMUX4_CLK_MASK (3 << MXC_CCM_CCGR6_IPMUX4_CLK_OFFSET) /* GPMI/BCH on i.MX6UL */ #define MXC_CCM_CCGR6_BCH_OFFSET 6 #define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET) @@ -895,6 +937,9 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) +/* i.MX6ULL */ +#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET 18 +#define MXC_CCM_CCGR6_AIPS_TZ3_CLK_MASK (3 << MXC_CCM_CCGR6_AIPS_TZ3_CLK_OFFSET) /* The following *CCGR6* exist only i.MX6SX */ #define MXC_CCM_CCGR6_PWM8_OFFSET 16 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET) @@ -1226,6 +1271,7 @@ struct mxc_ccm_reg { (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60 #define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23) #define BP_PMU_MISC2_AUDIO_DIV_MSB 23 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 53bf054..8bb36eb 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -182,6 +182,7 @@ #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) +#define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) @@ -265,6 +266,7 @@ #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) +#define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #ifdef CONFIG_MX6SX #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) #else @@ -318,6 +320,14 @@ #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) +#elif defined(CONFIG_MX6ULL) +#define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) +#define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) +#define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) +#define UART8_IPS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) +#define EPDC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) +#define IOMUXC_SNVS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) +#define SNVS_GPR_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) #endif /* Only for i.MX6SX */ #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) @@ -336,10 +346,12 @@ #include <asm/types.h> /* only for i.MX6SX/UL */ -#define WDOG3_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL) ? \ +#define WDOG3_BASE_ADDR ((is_mx6ul() ? \ MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)) -#define LCDIF1_BASE_ADDR ((is_cpu_type(MXC_CPU_MX6UL)) ? \ - MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR) +#define LCDIF1_BASE_ADDR ((is_mx6ul()) ? \ + MX6UL_LCDIF1_BASE_ADDR : \ + ((is_mx6ull()) ? \ + MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR)) extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h index 4b6bb18..b9cd670 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h @@ -37,6 +37,8 @@ enum { #include "mx6sl_pins.h" #elif defined(CONFIG_MX6SX) #include "mx6sx_pins.h" +#elif defined(CONFIG_MX6ULL) +#include "mx6ull_pins.h" #elif defined(CONFIG_MX6UL) #include "mx6ul_pins.h" #else diff --git a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h new file mode 100644 index 0000000..682430e --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h @@ -0,0 +1,1065 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_IMX6ULL_PINS_H__ +#define __ASM_ARCH_IMX6ULL_PINS_H__ + +#include <asm/imx-common/iomux-v3.h> + +enum { + MX6_PAD_BOOT_MODE0__GPIO5_IO10 = IOMUX_PAD(0x0044, 0x0000, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_BOOT_MODE1__GPIO5_IO11 = IOMUX_PAD(0x0048, 0x0004, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + + /* + * The TAMPER Pin can be used for GPIO, which depends on + * TAMPER_PIN_DISABLE[1:0] settings. + */ + MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 = IOMUX_PAD(0x004C, 0x0008, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER1__GPIO5_IO01 = IOMUX_PAD(0x0050, 0x000C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 = IOMUX_PAD(0x0054, 0x0010, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER3__GPIO5_IO03 = IOMUX_PAD(0x0058, 0x0014, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 = IOMUX_PAD(0x005C, 0x0018, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER5__GPIO5_IO05 = IOMUX_PAD(0x0060, 0x001C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER6__GPIO5_IO06 = IOMUX_PAD(0x0064, 0x0020, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 = IOMUX_PAD(0x0068, 0x0024, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 = IOMUX_PAD(0x006C, 0x0028, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 = IOMUX_PAD(0x0070, 0x002C, IOMUX_CONFIG_LPSR | 5, 0x0000, 0, 0), + + MX6_PAD_JTAG_MOD__SJC_MOD = IOMUX_PAD(0x02D0, 0x0044, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__GPT2_CLK = IOMUX_PAD(0x02D0, 0x0044, 1, 0x05A0, 0, 0), + MX6_PAD_JTAG_MOD__SPDIF_OUT = IOMUX_PAD(0x02D0, 0x0044, 2, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__ENET1_REF_CLK_25M = IOMUX_PAD(0x02D0, 0x0044, 3, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__CCM_PMIC_RDY = IOMUX_PAD(0x02D0, 0x0044, 4, 0x04C0, 0, 0), + MX6_PAD_JTAG_MOD__GPIO1_IO10 = IOMUX_PAD(0x02D0, 0x0044, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_MOD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02D0, 0x0044, 6, 0x0610, 0, 0), + + MX6_PAD_JTAG_TMS__SJC_TMS = IOMUX_PAD(0x02D4, 0x0048, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__GPT2_CAPTURE1 = IOMUX_PAD(0x02D4, 0x0048, 1, 0x0598, 0, 0), + MX6_PAD_JTAG_TMS__SAI2_MCLK = IOMUX_PAD(0x02D4, 0x0048, 2, 0x05F0, 0, 0), + MX6_PAD_JTAG_TMS__CCM_CLKO1 = IOMUX_PAD(0x02D4, 0x0048, 3, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__CCM_WAIT = IOMUX_PAD(0x02D4, 0x0048, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__GPIO1_IO11 = IOMUX_PAD(0x02D4, 0x0048, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TMS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x02D4, 0x0048, 6, 0x0614, 0, 0), + MX6_PAD_JTAG_TMS__EPIT1_OUT = IOMUX_PAD(0x02D4, 0x0048, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TDO__SJC_TDO = IOMUX_PAD(0x02D8, 0x004C, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__GPT2_CAPTURE2 = IOMUX_PAD(0x02D8, 0x004C, 1, 0x059C, 0, 0), + MX6_PAD_JTAG_TDO__SAI2_TX_SYNC = IOMUX_PAD(0x02D8, 0x004C, 2, 0x05FC, 0, 0), + MX6_PAD_JTAG_TDO__CCM_CLKO2 = IOMUX_PAD(0x02D8, 0x004C, 3, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__CCM_STOP = IOMUX_PAD(0x02D8, 0x004C, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__GPIO1_IO12 = IOMUX_PAD(0x02D8, 0x004C, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__MQS_RIGHT = IOMUX_PAD(0x02D8, 0x004C, 6, 0x0000, 0, 0), + MX6_PAD_JTAG_TDO__EPIT2_OUT = IOMUX_PAD(0x02D8, 0x004C, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TDI__SJC_TDI = IOMUX_PAD(0x02DC, 0x0050, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__GPT2_COMPARE1 = IOMUX_PAD(0x02DC, 0x0050, 1, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__SAI2_TX_BCLK = IOMUX_PAD(0x02DC, 0x0050, 2, 0x05F8, 0, 0), + MX6_PAD_JTAG_TDI__PWM6_OUT = IOMUX_PAD(0x02DC, 0x0050, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__GPIO1_IO13 = IOMUX_PAD(0x02DC, 0x0050, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__MQS_LEFT = IOMUX_PAD(0x02DC, 0x0050, 6, 0x0000, 0, 0), + MX6_PAD_JTAG_TDI__SIM1_POWER_FAIL = IOMUX_PAD(0x02DC, 0x0050, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TCK__SJC_TCK = IOMUX_PAD(0x02E0, 0x0054, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__GPT2_COMPARE2 = IOMUX_PAD(0x02E0, 0x0054, 1, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__SAI2_RX_DATA = IOMUX_PAD(0x02E0, 0x0054, 2, 0x05F4, 0, 0), + MX6_PAD_JTAG_TCK__PWM7_OUT = IOMUX_PAD(0x02E0, 0x0054, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__GPIO1_IO14 = IOMUX_PAD(0x02E0, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__SIM2_POWER_FAIL = IOMUX_PAD(0x02E0, 0x0054, 8, 0x0000, 0, 0), + + MX6_PAD_JTAG_TRST_B__SJC_TRSTB = IOMUX_PAD(0x02E4, 0x0058, 0, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__GPT2_COMPARE3 = IOMUX_PAD(0x02E4, 0x0058, 1, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__SAI2_TX_DATA = IOMUX_PAD(0x02E4, 0x0058, 2, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__PWM8_OUT = IOMUX_PAD(0x02E4, 0x0058, 4, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__GPIO1_IO15 = IOMUX_PAD(0x02E4, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02E4, 0x0058, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO00__I2C2_SCL = IOMUX_PAD(0x02E8, 0x005C, IOMUX_CONFIG_SION | 0, 0x05AC, 1, 0), + MX6_PAD_GPIO1_IO00__GPT1_CAPTURE1 = IOMUX_PAD(0x02E8, 0x005C, 1, 0x058C, 0, 0), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID = IOMUX_PAD(0x02E8, 0x005C, 2, 0x04B8, 0, 0), + MX6_PAD_GPIO1_IO00__ENET1_REF_CLK1 = IOMUX_PAD(0x02E8, 0x005C, 3, 0x0574, 0, 0), + MX6_PAD_GPIO1_IO00__MQS_RIGHT = IOMUX_PAD(0x02E8, 0x005C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__GPIO1_IO00 = IOMUX_PAD(0x02E8, 0x005C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02E8, 0x005C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__SRC_SYSTEM_RESET = IOMUX_PAD(0x02E8, 0x005C, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO00__WDOG3_WDOG_B = IOMUX_PAD(0x02E8, 0x005C, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO01__I2C2_SDA = IOMUX_PAD(0x02EC, 0x0060, IOMUX_CONFIG_SION | 0, 0x05B0, 1, 0), + MX6_PAD_GPIO1_IO01__GPT1_COMPARE1 = IOMUX_PAD(0x02EC, 0x0060, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__USB_OTG1_OC = IOMUX_PAD(0x02EC, 0x0060, 2, 0x0664, 0, 0), + MX6_PAD_GPIO1_IO01__ENET2_REF_CLK2 = IOMUX_PAD(0x02EC, 0x0060, 3, 0x057C, 0, 0), + MX6_PAD_GPIO1_IO01__MQS_LEFT = IOMUX_PAD(0x02EC, 0x0060, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__GPIO1_IO01 = IOMUX_PAD(0x02EC, 0x0060, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02EC, 0x0060, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__SRC_EARLY_RESET = IOMUX_PAD(0x02EC, 0x0060, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO01__WDOG1_WDOG_B = IOMUX_PAD(0x02EC, 0x0060, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO02__I2C1_SCL = IOMUX_PAD(0x02F0, 0x0064, IOMUX_CONFIG_SION | 0, 0x05A4, 0, 0), + MX6_PAD_GPIO1_IO02__GPT1_COMPARE2 = IOMUX_PAD(0x02F0, 0x0064, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR = IOMUX_PAD(0x02F0, 0x0064, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__ENET1_REF_CLK_25M = IOMUX_PAD(0x02F0, 0x0064, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__USDHC1_WP = IOMUX_PAD(0x02F0, 0x0064, 4, 0x066C, 0, 0), + MX6_PAD_GPIO1_IO02__GPIO1_IO02 = IOMUX_PAD(0x02F0, 0x0064, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 = IOMUX_PAD(0x02F0, 0x0064, 6, 0x0610, 1, 0), + MX6_PAD_GPIO1_IO02__SRC_ANY_PU_RESET = IOMUX_PAD(0x02F0, 0x0064, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__UART1_DCE_TX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO02__UART1_DTE_RX = IOMUX_PAD(0x02F0, 0x0064, 8, 0x0624, 0, 0), + + MX6_PAD_GPIO1_IO03__I2C1_SDA = IOMUX_PAD(0x02F4, 0x0068, IOMUX_CONFIG_SION | 0, 0x05A8, 1, 0), + MX6_PAD_GPIO1_IO03__GPT1_COMPARE3 = IOMUX_PAD(0x02F4, 0x0068, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__USB_OTG2_OC = IOMUX_PAD(0x02F4, 0x0068, 2, 0x0660, 0, 0), + MX6_PAD_GPIO1_IO03__USDHC1_CD_B = IOMUX_PAD(0x02F4, 0x0068, 4, 0x0668, 0, 0), + MX6_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x02F4, 0x0068, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK = IOMUX_PAD(0x02F4, 0x0068, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__SRC_TESTER_ACK = IOMUX_PAD(0x02F4, 0x0068, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO03__UART1_DCE_RX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0624, 1, 0), + MX6_PAD_GPIO1_IO03__UART1_DTE_TX = IOMUX_PAD(0x02F4, 0x0068, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO04__ENET1_REF_CLK1 = IOMUX_PAD(0x02F8, 0x006C, 0, 0x0574, 1, 0), + MX6_PAD_GPIO1_IO04__PWM3_OUT = IOMUX_PAD(0x02F8, 0x006C, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR = IOMUX_PAD(0x02F8, 0x006C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__USDHC1_RESET_B = IOMUX_PAD(0x02F8, 0x006C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x02F8, 0x006C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x02F8, 0x006C, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__UART5_DCE_TX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__UART5_DTE_RX = IOMUX_PAD(0x02F8, 0x006C, 8, 0x0644, 2, 0), + + MX6_PAD_GPIO1_IO05__ENET2_REF_CLK2 = IOMUX_PAD(0x02FC, 0x0070, 0, 0x057C, 1, 0), + MX6_PAD_GPIO1_IO05__PWM4_OUT = IOMUX_PAD(0x02FC, 0x0070, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID = IOMUX_PAD(0x02FC, 0x0070, 2, 0x04BC, 0, 0), + MX6_PAD_GPIO1_IO05__CSI_FIELD = IOMUX_PAD(0x02FC, 0x0070, 3, 0x0530, 0, 0), + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT = IOMUX_PAD(0x02FC, 0x0070, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__GPIO1_IO05 = IOMUX_PAD(0x02FC, 0x0070, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT = IOMUX_PAD(0x02FC, 0x0070, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO05__UART5_DCE_RX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0644, 3, 0), + MX6_PAD_GPIO1_IO05__UART5_DTE_TX = IOMUX_PAD(0x02FC, 0x0070, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO06__ENET1_MDIO = IOMUX_PAD(0x0300, 0x0074, 0, 0x0578, 0, 0), + MX6_PAD_GPIO1_IO06__ENET2_MDIO = IOMUX_PAD(0x0300, 0x0074, 1, 0x0580, 0, 0), + MX6_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE = IOMUX_PAD(0x0300, 0x0074, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CSI_MCLK = IOMUX_PAD(0x0300, 0x0074, 3, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__USDHC2_WP = IOMUX_PAD(0x0300, 0x0074, 4, 0x069C, 0, 0), + MX6_PAD_GPIO1_IO06__GPIO1_IO06 = IOMUX_PAD(0x0300, 0x0074, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CCM_WAIT = IOMUX_PAD(0x0300, 0x0074, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__CCM_REF_EN_B = IOMUX_PAD(0x0300, 0x0074, 7, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__UART1_DCE_CTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO06__UART1_DTE_RTS = IOMUX_PAD(0x0300, 0x0074, 8, 0x0620, 0, 0), + + MX6_PAD_GPIO1_IO07__ENET1_MDC = IOMUX_PAD(0x0304, 0x0078, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__ENET2_MDC = IOMUX_PAD(0x0304, 0x0078, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__USB_OTG_HOST_MODE = IOMUX_PAD(0x0304, 0x0078, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__CSI_PIXCLK = IOMUX_PAD(0x0304, 0x0078, 3, 0x0528, 0, 0), + MX6_PAD_GPIO1_IO07__USDHC2_CD_B = IOMUX_PAD(0x0304, 0x0078, 4, 0x0674, 1, 0), + MX6_PAD_GPIO1_IO07__GPIO1_IO07 = IOMUX_PAD(0x0304, 0x0078, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__CCM_STOP = IOMUX_PAD(0x0304, 0x0078, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO07__UART1_DCE_RTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0620, 1, 0), + MX6_PAD_GPIO1_IO07__UART1_DTE_CTS = IOMUX_PAD(0x0304, 0x0078, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x0308, 0x007C, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__WDOG1_WDOG_B = IOMUX_PAD(0x0308, 0x007C, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__SPDIF_OUT = IOMUX_PAD(0x0308, 0x007C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__CSI_VSYNC = IOMUX_PAD(0x0308, 0x007C, 3, 0x052C, 1, 0), + MX6_PAD_GPIO1_IO08__USDHC2_VSELECT = IOMUX_PAD(0x0308, 0x007C, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__GPIO1_IO08 = IOMUX_PAD(0x0308, 0x007C, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO08__CCM_PMIC_RDY = IOMUX_PAD(0x0308, 0x007C, 6, 0x04C0, 1, 0), + MX6_PAD_GPIO1_IO08__UART5_DCE_RTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0640, 1, 0), + MX6_PAD_GPIO1_IO08__UART5_DTE_CTS = IOMUX_PAD(0x0308, 0x007C, 8, 0x0000, 0, 0), + + MX6_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x030C, 0x0080, 0, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__WDOG1_WDOG_ANY = IOMUX_PAD(0x030C, 0x0080, 1, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__SPDIF_IN = IOMUX_PAD(0x030C, 0x0080, 2, 0x0618, 0, 0), + MX6_PAD_GPIO1_IO09__CSI_HSYNC = IOMUX_PAD(0x030C, 0x0080, 3, 0x0524, 1, 0), + MX6_PAD_GPIO1_IO09__USDHC2_RESET_B = IOMUX_PAD(0x030C, 0x0080, 4, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__GPIO1_IO09 = IOMUX_PAD(0x030C, 0x0080, 5, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__USDHC1_RESET_B = IOMUX_PAD(0x030C, 0x0080, 6, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__UART5_DCE_CTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO09__UART5_DTE_RTS = IOMUX_PAD(0x030C, 0x0080, 8, 0x0640, 2, 0), + + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0000, 0, 0), + + MX6_PAD_UART1_TX_DATA__UART1_DTE_RX = IOMUX_PAD(0x0310, 0x0084, 0, 0x0624, 2, 0), + MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 = IOMUX_PAD(0x0310, 0x0084, 1, 0x0000, 0, 0), + MX6_PAD_UART1_TX_DATA__I2C3_SCL = IOMUX_PAD(0x0310, 0x0084, IOMUX_CONFIG_SION | 2, 0x05B4, 0, 0), + MX6_PAD_UART1_TX_DATA__CSI_DATA02 = IOMUX_PAD(0x0310, 0x0084, 3, 0x04C4, 1, 0), + MX6_PAD_UART1_TX_DATA__GPT1_COMPARE1 = IOMUX_PAD(0x0310, 0x0084, 4, 0x0000, 0, 0), + MX6_PAD_UART1_TX_DATA__GPIO1_IO16 = IOMUX_PAD(0x0310, 0x0084, 5, 0x0000, 0, 0), + MX6_PAD_UART1_TX_DATA__SPDIF_OUT = IOMUX_PAD(0x0310, 0x0084, 8, 0x0000, 0, 0), + + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0624, 3, 0), + + MX6_PAD_UART1_RX_DATA__UART1_DTE_TX = IOMUX_PAD(0x0314, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 = IOMUX_PAD(0x0314, 0x0088, 1, 0x0000, 0, 0), + MX6_PAD_UART1_RX_DATA__I2C3_SDA = IOMUX_PAD(0x0314, 0x0088, IOMUX_CONFIG_SION | 2, 0x05B8, 0, 0), + MX6_PAD_UART1_RX_DATA__CSI_DATA03 = IOMUX_PAD(0x0314, 0x0088, 3, 0x04C8, 1, 0), + MX6_PAD_UART1_RX_DATA__GPT1_CLK = IOMUX_PAD(0x0314, 0x0088, 4, 0x0594, 0, 0), + MX6_PAD_UART1_RX_DATA__GPIO1_IO17 = IOMUX_PAD(0x0314, 0x0088, 5, 0x0000, 0, 0), + MX6_PAD_UART1_RX_DATA__SPDIF_IN = IOMUX_PAD(0x0314, 0x0088, 8, 0x0618, 1, 0), + + MX6_PAD_UART1_CTS_B__UART1_DCE_CTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0000, 0, 0), + + MX6_PAD_UART1_CTS_B__UART1_DTE_RTS = IOMUX_PAD(0x0318, 0x008C, 0, 0x0620, 2, 0), + MX6_PAD_UART1_CTS_B__ENET1_RX_CLK = IOMUX_PAD(0x0318, 0x008C, 1, 0x0000, 0, 0), + MX6_PAD_UART1_CTS_B__USDHC1_WP = IOMUX_PAD(0x0318, 0x008C, 2, 0x066C, 1, 0), + MX6_PAD_UART1_CTS_B__CSI_DATA04 = IOMUX_PAD(0x0318, 0x008C, 3, 0x04D8, 0, 0), + MX6_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN = IOMUX_PAD(0x0318, 0x008C, 4, 0x0000, 0, 0), + MX6_PAD_UART1_CTS_B__GPIO1_IO18 = IOMUX_PAD(0x0318, 0x008C, 5, 0x0000, 0, 0), + MX6_PAD_UART1_CTS_B__USDHC2_WP = IOMUX_PAD(0x0318, 0x008C, 8, 0x069C, 1, 0), + + MX6_PAD_UART1_RTS_B__UART1_DCE_RTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0620, 3, 0), + + MX6_PAD_UART1_RTS_B__UART1_DTE_CTS = IOMUX_PAD(0x031C, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__ENET1_TX_ER = IOMUX_PAD(0x031C, 0x0090, 1, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__USDHC1_CD_B = IOMUX_PAD(0x031C, 0x0090, 2, 0x0668, 1, 0), + MX6_PAD_UART1_RTS_B__CSI_DATA05 = IOMUX_PAD(0x031C, 0x0090, 3, 0x04CC, 1, 0), + MX6_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT = IOMUX_PAD(0x031C, 0x0090, 4, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__GPIO1_IO19 = IOMUX_PAD(0x031C, 0x0090, 5, 0x0000, 0, 0), + MX6_PAD_UART1_RTS_B__USDHC2_CD_B = IOMUX_PAD(0x031C, 0x0090, 8, 0x0674, 2, 0), + + MX6_PAD_UART2_TX_DATA__UART2_DCE_TX = IOMUX_PAD(0x0320, 0x0094, 0, 0x0000, 0, 0), + + MX6_PAD_UART2_TX_DATA__UART2_DTE_RX = IOMUX_PAD(0x0320, 0x0094, 0, 0x062C, 0, 0), + MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 = IOMUX_PAD(0x0320, 0x0094, 1, 0x0000, 0, 0), + MX6_PAD_UART2_TX_DATA__I2C4_SCL = IOMUX_PAD(0x0320, 0x0094, IOMUX_CONFIG_SION | 2, 0x05BC, 0, 0), + MX6_PAD_UART2_TX_DATA__CSI_DATA06 = IOMUX_PAD(0x0320, 0x0094, 3, 0x04DC, 0, 0), + MX6_PAD_UART2_TX_DATA__GPT1_CAPTURE1 = IOMUX_PAD(0x0320, 0x0094, 4, 0x058C, 1, 0), + MX6_PAD_UART2_TX_DATA__GPIO1_IO20 = IOMUX_PAD(0x0320, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_UART2_TX_DATA__ECSPI3_SS0 = IOMUX_PAD(0x0320, 0x0094, 8, 0x0560, 0, 0), + + MX6_PAD_UART2_RX_DATA__UART2_DCE_RX = IOMUX_PAD(0x0324, 0x0098, 0, 0x062C, 1, 0), + + MX6_PAD_UART2_RX_DATA__UART2_DTE_TX = IOMUX_PAD(0x0324, 0x0098, 0, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 = IOMUX_PAD(0x0324, 0x0098, 1, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__I2C4_SDA = IOMUX_PAD(0x0324, 0x0098, IOMUX_CONFIG_SION | 2, 0x05C0, 0, 0), + MX6_PAD_UART2_RX_DATA__CSI_DATA07 = IOMUX_PAD(0x0324, 0x0098, 3, 0x04E0, 0, 0), + MX6_PAD_UART2_RX_DATA__GPT1_CAPTURE2 = IOMUX_PAD(0x0324, 0x0098, 4, 0x0590, 0, 0), + MX6_PAD_UART2_RX_DATA__GPIO1_IO21 = IOMUX_PAD(0x0324, 0x0098, 5, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__SJC_DONE = IOMUX_PAD(0x0324, 0x0098, 7, 0x0000, 0, 0), + MX6_PAD_UART2_RX_DATA__ECSPI3_SCLK = IOMUX_PAD(0x0324, 0x0098, 8, 0x0554, 0, 0), + + MX6_PAD_UART2_CTS_B__UART2_DCE_CTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0000, 0, 0), + + MX6_PAD_UART2_CTS_B__UART2_DTE_RTS = IOMUX_PAD(0x0328, 0x009C, 0, 0x0628, 0, 0), + MX6_PAD_UART2_CTS_B__ENET1_CRS = IOMUX_PAD(0x0328, 0x009C, 1, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__FLEXCAN2_TX = IOMUX_PAD(0x0328, 0x009C, 2, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__CSI_DATA08 = IOMUX_PAD(0x0328, 0x009C, 3, 0x04E4, 0, 0), + MX6_PAD_UART2_CTS_B__GPT1_COMPARE2 = IOMUX_PAD(0x0328, 0x009C, 4, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__GPIO1_IO22 = IOMUX_PAD(0x0328, 0x009C, 5, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__SJC_DE_B = IOMUX_PAD(0x0328, 0x009C, 7, 0x0000, 0, 0), + MX6_PAD_UART2_CTS_B__ECSPI3_MOSI = IOMUX_PAD(0x0328, 0x009C, 8, 0x055C, 0, 0), + + MX6_PAD_UART2_RTS_B__UART2_DCE_RTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0628, 1, 0), + + MX6_PAD_UART2_RTS_B__UART2_DTE_CTS = IOMUX_PAD(0x032C, 0x00A0, 0, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__ENET1_COL = IOMUX_PAD(0x032C, 0x00A0, 1, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__FLEXCAN2_RX = IOMUX_PAD(0x032C, 0x00A0, 2, 0x0588, 0, 0), + MX6_PAD_UART2_RTS_B__CSI_DATA09 = IOMUX_PAD(0x032C, 0x00A0, 3, 0x04E8, 0, 0), + MX6_PAD_UART2_RTS_B__GPT1_COMPARE3 = IOMUX_PAD(0x032C, 0x00A0, 4, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__GPIO1_IO23 = IOMUX_PAD(0x032C, 0x00A0, 5, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__SJC_FAIL = IOMUX_PAD(0x032C, 0x00A0, 7, 0x0000, 0, 0), + MX6_PAD_UART2_RTS_B__ECSPI3_MISO = IOMUX_PAD(0x032C, 0x00A0, 8, 0x0558, 0, 0), + + MX6_PAD_UART3_TX_DATA__UART3_DCE_TX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0000, 0, 0), + + MX6_PAD_UART3_TX_DATA__UART3_DTE_RX = IOMUX_PAD(0x0330, 0x00A4, 0, 0x0634, 0, 0), + MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 = IOMUX_PAD(0x0330, 0x00A4, 1, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__SIM1_PORT0_PD = IOMUX_PAD(0x0330, 0x00A4, 2, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__CSI_DATA01 = IOMUX_PAD(0x0330, 0x00A4, 3, 0x04D4, 0, 0), + MX6_PAD_UART3_TX_DATA__UART2_DCE_CTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__UART2_DTE_RTS = IOMUX_PAD(0x0330, 0x00A4, 4, 0x0628, 2, 0), + MX6_PAD_UART3_TX_DATA__GPIO1_IO24 = IOMUX_PAD(0x0330, 0x00A4, 5, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__SJC_JTAG_ACT = IOMUX_PAD(0x0330, 0x00A4, 7, 0x0000, 0, 0), + MX6_PAD_UART3_TX_DATA__ANATOP_OTG1_ID = IOMUX_PAD(0x0330, 0x00A4, 8, 0x04B8, 1, 0), + + MX6_PAD_UART3_RX_DATA__UART3_DCE_RX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0634, 1, 0), + + MX6_PAD_UART3_RX_DATA__UART3_DTE_TX = IOMUX_PAD(0x0334, 0x00A8, 0, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 = IOMUX_PAD(0x0334, 0x00A8, 1, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__SIM2_PORT0_PD = IOMUX_PAD(0x0334, 0x00A8, 2, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__CSI_DATA00 = IOMUX_PAD(0x0334, 0x00A8, 3, 0x04D0, 0, 0), + MX6_PAD_UART3_RX_DATA__UART2_DCE_RTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0628, 3, 0), + MX6_PAD_UART3_RX_DATA__UART2_DTE_CTS = IOMUX_PAD(0x0334, 0x00A8, 4, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__GPIO1_IO25 = IOMUX_PAD(0x0334, 0x00A8, 5, 0x0000, 0, 0), + MX6_PAD_UART3_RX_DATA__EPIT1_OUT = IOMUX_PAD(0x0334, 0x00A8, 8, 0x0000, 0, 0), + + MX6_PAD_UART3_CTS_B__UART3_DCE_CTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0000, 0, 0), + + MX6_PAD_UART3_CTS_B__UART3_DTE_RTS = IOMUX_PAD(0x0338, 0x00AC, 0, 0x0630, 0, 0), + MX6_PAD_UART3_CTS_B__ENET2_RX_CLK = IOMUX_PAD(0x0338, 0x00AC, IOMUX_CONFIG_SION | 1, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__FLEXCAN1_TX = IOMUX_PAD(0x0338, 0x00AC, 2, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__CSI_DATA10 = IOMUX_PAD(0x0338, 0x00AC, 3, 0x04EC, 0, 0), + MX6_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0338, 0x00AC, 4, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__GPIO1_IO26 = IOMUX_PAD(0x0338, 0x00AC, 5, 0x0000, 0, 0), + MX6_PAD_UART3_CTS_B__EPIT2_OUT = IOMUX_PAD(0x0338, 0x00AC, 8, 0x0000, 0, 0), + + MX6_PAD_UART3_RTS_B__UART3_DCE_RTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0630, 1, 0), + + MX6_PAD_UART3_RTS_B__UART3_DTE_CTS = IOMUX_PAD(0x033C, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__ENET2_TX_ER = IOMUX_PAD(0x033C, 0x00B0, 1, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__FLEXCAN1_RX = IOMUX_PAD(0x033C, 0x00B0, 2, 0x0584, 0, 0), + MX6_PAD_UART3_RTS_B__CSI_DATA11 = IOMUX_PAD(0x033C, 0x00B0, 3, 0x04F0, 0, 0), + MX6_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x033C, 0x00B0, 4, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__GPIO1_IO27 = IOMUX_PAD(0x033C, 0x00B0, 5, 0x0000, 0, 0), + MX6_PAD_UART3_RTS_B__WDOG1_WDOG_B = IOMUX_PAD(0x033C, 0x00B0, 8, 0x0000, 0, 0), + + MX6_PAD_UART4_TX_DATA__UART4_DCE_TX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x0000, 0, 0), + + MX6_PAD_UART4_TX_DATA__UART4_DTE_RX = IOMUX_PAD(0x0340, 0x00B4, 0, 0x063C, 0, 0), + MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 = IOMUX_PAD(0x0340, 0x00B4, 1, 0x0000, 0, 0), + MX6_PAD_UART4_TX_DATA__I2C1_SCL = IOMUX_PAD(0x0340, 0x00B4, IOMUX_CONFIG_SION | 2, 0x05A4, 1, 0), + MX6_PAD_UART4_TX_DATA__CSI_DATA12 = IOMUX_PAD(0x0340, 0x00B4, 3, 0x04F4, 0, 0), + MX6_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 = IOMUX_PAD(0x0340, 0x00B4, 4, 0x0000, 0, 0), + MX6_PAD_UART4_TX_DATA__GPIO1_IO28 = IOMUX_PAD(0x0340, 0x00B4, 5, 0x0000, 0, 0), + MX6_PAD_UART4_TX_DATA__ECSPI2_SCLK = IOMUX_PAD(0x0340, 0x00B4, 8, 0x0544, 1, 0), + + MX6_PAD_UART4_RX_DATA__UART4_DCE_RX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x063C, 1, 0), + + MX6_PAD_UART4_RX_DATA__UART4_DTE_TX = IOMUX_PAD(0x0344, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 = IOMUX_PAD(0x0344, 0x00B8, 1, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__I2C1_SDA = IOMUX_PAD(0x0344, 0x00B8, IOMUX_CONFIG_SION | 2, 0x05A8, 2, 0), + MX6_PAD_UART4_RX_DATA__CSI_DATA13 = IOMUX_PAD(0x0344, 0x00B8, 3, 0x04F8, 0, 0), + MX6_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 = IOMUX_PAD(0x0344, 0x00B8, 4, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__GPIO1_IO29 = IOMUX_PAD(0x0344, 0x00B8, 5, 0x0000, 0, 0), + MX6_PAD_UART4_RX_DATA__ECSPI2_SS0 = IOMUX_PAD(0x0344, 0x00B8, 8, 0x0550, 1, 0), + MX6_PAD_UART5_TX_DATA__GPIO1_IO30 = IOMUX_PAD(0x0348, 0x00BC, 5, 0x0000, 0, 0), + MX6_PAD_UART5_TX_DATA__ECSPI2_MOSI = IOMUX_PAD(0x0348, 0x00BC, 8, 0x054C, 0, 0), + + MX6_PAD_UART5_TX_DATA__UART5_DCE_TX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0000, 0, 0), + + MX6_PAD_UART5_TX_DATA__UART5_DTE_RX = IOMUX_PAD(0x0348, 0x00BC, 0, 0x0644, 4, 0), + MX6_PAD_UART5_TX_DATA__ENET2_CRS = IOMUX_PAD(0x0348, 0x00BC, 1, 0x0000, 0, 0), + MX6_PAD_UART5_TX_DATA__I2C2_SCL = IOMUX_PAD(0x0348, 0x00BC, IOMUX_CONFIG_SION | 2, 0x05AC, 2, 0), + MX6_PAD_UART5_TX_DATA__CSI_DATA14 = IOMUX_PAD(0x0348, 0x00BC, 3, 0x04FC, 0, 0), + MX6_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 = IOMUX_PAD(0x0348, 0x00BC, 4, 0x0000, 0, 0), + + MX6_PAD_UART5_RX_DATA__UART5_DCE_RX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0644, 5, 0), + + MX6_PAD_UART5_RX_DATA__UART5_DTE_TX = IOMUX_PAD(0x034C, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__ENET2_COL = IOMUX_PAD(0x034C, 0x00C0, 1, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__I2C2_SDA = IOMUX_PAD(0x034C, 0x00C0, IOMUX_CONFIG_SION | 2, 0x05B0, 2, 0), + MX6_PAD_UART5_RX_DATA__CSI_DATA15 = IOMUX_PAD(0x034C, 0x00C0, 3, 0x0500, 0, 0), + MX6_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB = IOMUX_PAD(0x034C, 0x00C0, 4, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__GPIO1_IO31 = IOMUX_PAD(0x034C, 0x00C0, 5, 0x0000, 0, 0), + MX6_PAD_UART5_RX_DATA__ECSPI2_MISO = IOMUX_PAD(0x034C, 0x00C0, 8, 0x0548, 1, 0), + + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 = IOMUX_PAD(0x0350, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__UART4_DCE_RTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0638, 0, 0), + MX6_PAD_ENET1_RX_DATA0__UART4_DTE_CTS = IOMUX_PAD(0x0350, 0x00C4, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__PWM1_OUT = IOMUX_PAD(0x0350, 0x00C4, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__CSI_DATA16 = IOMUX_PAD(0x0350, 0x00C4, 3, 0x0504, 0, 0), + MX6_PAD_ENET1_RX_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0350, 0x00C4, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 = IOMUX_PAD(0x0350, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA0__KPP_ROW00 = IOMUX_PAD(0x0350, 0x00C4, 6, 0x05D0, 0, 0), + MX6_PAD_ENET1_RX_DATA0__USDHC1_LCTL = IOMUX_PAD(0x0350, 0x00C4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 = IOMUX_PAD(0x0354, 0x00C8, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__UART4_DCE_CTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__UART4_DTE_RTS = IOMUX_PAD(0x0354, 0x00C8, 1, 0x0638, 1, 0), + MX6_PAD_ENET1_RX_DATA1__PWM2_OUT = IOMUX_PAD(0x0354, 0x00C8, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__CSI_DATA17 = IOMUX_PAD(0x0354, 0x00C8, 3, 0x0508, 0, 0), + MX6_PAD_ENET1_RX_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0354, 0x00C8, 4, 0x0584, 1, 0), + MX6_PAD_ENET1_RX_DATA1__GPIO2_IO01 = IOMUX_PAD(0x0354, 0x00C8, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_DATA1__KPP_COL00 = IOMUX_PAD(0x0354, 0x00C8, 6, 0x05C4, 0, 0), + MX6_PAD_ENET1_RX_DATA1__USDHC2_LCTL = IOMUX_PAD(0x0354, 0x00C8, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0), + MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__CSI_DATA18 = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0), + MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__GPIO2_IO02 = IOMUX_PAD(0x0358, 0x00CC, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__KPP_ROW01 = IOMUX_PAD(0x0358, 0x00CC, 6, 0x05D4, 0, 0), + MX6_PAD_ENET1_RX_EN__USDHC1_VSELECT = IOMUX_PAD(0x0358, 0x00CC, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0), + MX6_PAD_ENET1_TX_DATA0__CSI_DATA19 = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0), + MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0), + MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA0__KPP_COL01 = IOMUX_PAD(0x035C, 0x00D0, 6, 0x05C8, 0, 0), + MX6_PAD_ENET1_TX_DATA0__USDHC2_VSELECT = IOMUX_PAD(0x035C, 0x00D0, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 = IOMUX_PAD(0x0360, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__UART6_DCE_CTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__UART6_DTE_RTS = IOMUX_PAD(0x0360, 0x00D4, 1, 0x0648, 2, 0), + MX6_PAD_ENET1_TX_DATA1__PWM5_OUT = IOMUX_PAD(0x0360, 0x00D4, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__CSI_DATA20 = IOMUX_PAD(0x0360, 0x00D4, 3, 0x0514, 0, 0), + MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO = IOMUX_PAD(0x0360, 0x00D4, 4, 0x0580, 1, 0), + MX6_PAD_ENET1_TX_DATA1__GPIO2_IO04 = IOMUX_PAD(0x0360, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_DATA1__KPP_ROW02 = IOMUX_PAD(0x0360, 0x00D4, 6, 0x05D8, 0, 0), + MX6_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0360, 0x00D4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN = IOMUX_PAD(0x0364, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__UART6_DCE_RTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0648, 3, 0), + MX6_PAD_ENET1_TX_EN__UART6_DTE_CTS = IOMUX_PAD(0x0364, 0x00D8, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__PWM6_OUT = IOMUX_PAD(0x0364, 0x00D8, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__CSI_DATA21 = IOMUX_PAD(0x0364, 0x00D8, 3, 0x0518, 0, 0), + MX6_PAD_ENET1_TX_EN__ENET2_MDC = IOMUX_PAD(0x0364, 0x00D8, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__GPIO2_IO05 = IOMUX_PAD(0x0364, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_EN__KPP_COL02 = IOMUX_PAD(0x0364, 0x00D8, 6, 0x05CC, 0, 0), + MX6_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB = IOMUX_PAD(0x0364, 0x00D8, 8, 0x0000, 0, 0), + + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK = IOMUX_PAD(0x0368, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__UART7_DCE_CTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__UART7_DTE_RTS = IOMUX_PAD(0x0368, 0x00DC, 1, 0x0650, 0, 0), + MX6_PAD_ENET1_TX_CLK__PWM7_OUT = IOMUX_PAD(0x0368, 0x00DC, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__CSI_DATA22 = IOMUX_PAD(0x0368, 0x00DC, 3, 0x051C, 0, 0), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 = IOMUX_PAD(0x0368, 0x00DC, IOMUX_CONFIG_SION | 4, 0x0574, 2, 0), + MX6_PAD_ENET1_TX_CLK__GPIO2_IO06 = IOMUX_PAD(0x0368, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__KPP_ROW03 = IOMUX_PAD(0x0368, 0x00DC, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_TX_CLK__GPT1_CLK = IOMUX_PAD(0x0368, 0x00DC, 8, 0x0594, 1, 0), + + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER = IOMUX_PAD(0x036C, 0x00E0, 0, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__UART7_DCE_RTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0650, 1, 0), + MX6_PAD_ENET1_RX_ER__UART7_DTE_CTS = IOMUX_PAD(0x036C, 0x00E0, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__PWM8_OUT = IOMUX_PAD(0x036C, 0x00E0, 2, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__CSI_DATA23 = IOMUX_PAD(0x036C, 0x00E0, 3, 0x0520, 0, 0), + MX6_PAD_ENET1_RX_ER__EIM_CRE = IOMUX_PAD(0x036C, 0x00E0, 4, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__GPIO2_IO07 = IOMUX_PAD(0x036C, 0x00E0, 5, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__KPP_COL03 = IOMUX_PAD(0x036C, 0x00E0, 6, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_ER__GPT1_CAPTURE2 = IOMUX_PAD(0x036C, 0x00E0, 8, 0x0590, 1, 0), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 = IOMUX_PAD(0x0370, 0x00E4, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__UART6_DCE_TX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__UART6_DTE_RX = IOMUX_PAD(0x0370, 0x00E4, 1, 0x064C, 1, 0), + MX6_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD = IOMUX_PAD(0x0370, 0x00E4, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__I2C3_SCL = IOMUX_PAD(0x0370, 0x00E4, IOMUX_CONFIG_SION | 3, 0x05B4, 1, 0), + MX6_PAD_ENET2_RX_DATA0__ENET1_MDIO = IOMUX_PAD(0x0370, 0x00E4, 4, 0x0578, 1, 0), + MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08 = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__KPP_ROW04 = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0), + MX6_PAD_ENET2_RX_DATA1__UART6_DTE_TX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__SIM1_PORT0_CLK = IOMUX_PAD(0x0374, 0x00E8, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__I2C3_SDA = IOMUX_PAD(0x0374, 0x00E8, IOMUX_CONFIG_SION | 3, 0x05B8, 1, 0), + MX6_PAD_ENET2_RX_DATA1__ENET1_MDC = IOMUX_PAD(0x0374, 0x00E8, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09 = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__KPP_COL04 = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0), + + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__UART7_DCE_TX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__UART7_DTE_RX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0654, 0, 0), + MX6_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B = IOMUX_PAD(0x0378, 0x00EC, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__I2C4_SCL = IOMUX_PAD(0x0378, 0x00EC, IOMUX_CONFIG_SION | 3, 0x05BC, 1, 0), + MX6_PAD_ENET2_RX_EN__EIM_ADDR26 = IOMUX_PAD(0x0378, 0x00EC, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__GPIO2_IO10 = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__KPP_ROW05 = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0), + MX6_PAD_ENET2_TX_DATA0__UART7_DTE_TX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN = IOMUX_PAD(0x037C, 0x00F0, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__I2C4_SDA = IOMUX_PAD(0x037C, 0x00F0, IOMUX_CONFIG_SION | 3, 0x05C0, 1, 0), + MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02 = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11 = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__KPP_COL05 = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__UART8_DTE_RX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x065C, 0, 0), + MX6_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD = IOMUX_PAD(0x0380, 0x00F4, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__ECSPI4_SCLK = IOMUX_PAD(0x0380, 0x00F4, 3, 0x0564, 0, 0), + MX6_PAD_ENET2_TX_DATA1__EIM_EB_B03 = IOMUX_PAD(0x0380, 0x00F4, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12 = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__KPP_ROW06 = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0), + + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__UART8_DCE_RX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0), + MX6_PAD_ENET2_TX_EN__UART8_DTE_TX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__SIM2_PORT0_CLK = IOMUX_PAD(0x0384, 0x00F8, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__ECSPI4_MOSI = IOMUX_PAD(0x0384, 0x00F8, 3, 0x056C, 0, 0), + MX6_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN = IOMUX_PAD(0x0384, 0x00F8, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__GPIO2_IO13 = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__KPP_COL06 = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_EN__USB_OTG2_OC = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0), + + MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__UART8_DTE_RTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0658, 0, 0), + MX6_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B = IOMUX_PAD(0x0388, 0x00FC, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__ECSPI4_MISO = IOMUX_PAD(0x0388, 0x00FC, 3, 0x0568, 0, 0), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 4, 0x057C, 2, 0), + MX6_PAD_ENET2_TX_CLK__GPIO2_IO14 = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__KPP_ROW07 = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0), + + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0), + MX6_PAD_ENET2_RX_ER__UART8_DTE_CTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN = IOMUX_PAD(0x038C, 0x0100, 2, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__ECSPI4_SS0 = IOMUX_PAD(0x038C, 0x0100, 3, 0x0570, 0, 0), + MX6_PAD_ENET2_RX_ER__EIM_ADDR25 = IOMUX_PAD(0x038C, 0x0100, 4, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__GPIO2_IO15 = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__KPP_COL07 = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_CLK__LCDIF_CLK = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__UART4_DCE_TX = IOMUX_PAD(0x0390, 0x0104, 2, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__UART4_DTE_RX = IOMUX_PAD(0x0390, 0x0104, 2, 0x063C, 2, 0), + MX6_PAD_LCD_CLK__SAI3_MCLK = IOMUX_PAD(0x0390, 0x0104, 3, 0x0600, 0, 0), + MX6_PAD_LCD_CLK__EIM_CS2_B = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__GPIO3_IO00 = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__LCDIF_RD_E = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__UART4_DCE_RX = IOMUX_PAD(0x0394, 0x0108, 2, 0x063C, 3, 0), + MX6_PAD_LCD_ENABLE__UART4_DTE_TX = IOMUX_PAD(0x0394, 0x0108, 2, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__SAI3_TX_SYNC = IOMUX_PAD(0x0394, 0x0108, 3, 0x060C, 0, 0), + MX6_PAD_LCD_ENABLE__EIM_CS3_B = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__GPIO3_IO01 = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0), + MX6_PAD_LCD_HSYNC__LCDIF_RS = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART4_DCE_CTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__UART4_DTE_RTS = IOMUX_PAD(0x0398, 0x010C, 2, 0x0638, 2, 0), + MX6_PAD_LCD_HSYNC__SAI3_TX_BCLK = IOMUX_PAD(0x0398, 0x010C, 3, 0x0608, 0, 0), + MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__GPIO3_IO02 = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__ECSPI2_SS1 = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__LCDIF_BUSY = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0), + MX6_PAD_LCD_VSYNC__UART4_DCE_RTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0638, 3, 0), + MX6_PAD_LCD_VSYNC__UART4_DTE_CTS = IOMUX_PAD(0x039C, 0x0110, 2, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__SAI3_RX_DATA = IOMUX_PAD(0x039C, 0x0110, 3, 0x0604, 0, 0), + MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__GPIO3_IO03 = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__ECSPI2_SS2 = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_RESET__LCDIF_RESET = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__LCDIF_CS = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__CA7_MX6ULL_EVENTI = IOMUX_PAD(0x03A0, 0x0114, 2, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__SAI3_TX_DATA = IOMUX_PAD(0x03A0, 0x0114, 3, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__GPIO3_IO04 = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__ECSPI2_SS3 = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA00__LCDIF_DATA00 = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x03A4, 0x0118, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__I2C3_SDA = IOMUX_PAD(0x03A4, 0x0118, IOMUX_CONFIG_SION | 4, 0x05B8, 2, 0), + MX6_PAD_LCD_DATA00__GPIO3_IO05 = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__SRC_BT_CFG00 = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__SAI1_MCLK = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0), + + MX6_PAD_LCD_DATA01__LCDIF_DATA01 = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x03A8, 0x011C, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__I2C3_SCL = IOMUX_PAD(0x03A8, 0x011C, IOMUX_CONFIG_SION | 4, 0x05B4, 2, 0), + MX6_PAD_LCD_DATA01__GPIO3_IO06 = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__SRC_BT_CFG01 = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__SAI1_TX_SYNC = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0), + + MX6_PAD_LCD_DATA02__LCDIF_DATA02 = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x03AC, 0x0120, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__I2C4_SDA = IOMUX_PAD(0x03AC, 0x0120, IOMUX_CONFIG_SION | 4, 0x05C0, 2, 0), + MX6_PAD_LCD_DATA02__GPIO3_IO07 = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__SRC_BT_CFG02 = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__SAI1_TX_BCLK = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0), + + MX6_PAD_LCD_DATA03__LCDIF_DATA03 = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x03B0, 0x0124, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__I2C4_SCL = IOMUX_PAD(0x03B0, 0x0124, IOMUX_CONFIG_SION | 4, 0x05BC, 2, 0), + MX6_PAD_LCD_DATA03__GPIO3_IO08 = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__SRC_BT_CFG03 = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__SAI1_RX_DATA = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0), + + MX6_PAD_LCD_DATA04__LCDIF_DATA04 = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__UART8_DCE_CTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__UART8_DTE_RTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0658, 2, 0), + MX6_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x03B4, 0x0128, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SPDIF_SR_CLK = IOMUX_PAD(0x03B4, 0x0128, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__GPIO3_IO09 = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SRC_BT_CFG04 = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__SAI1_TX_DATA = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA05__LCDIF_DATA05 = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__UART8_DCE_RTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0), + MX6_PAD_LCD_DATA05__UART8_DTE_CTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x03B8, 0x012C, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__SPDIF_OUT = IOMUX_PAD(0x03B8, 0x012C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__SRC_BT_CFG05 = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__ECSPI1_SS1 = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA06__LCDIF_DATA06 = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__UART7_DCE_CTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__UART7_DTE_RTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0650, 2, 0), + MX6_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x03BC, 0x0130, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__SPDIF_LOCK = IOMUX_PAD(0x03BC, 0x0130, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__SRC_BT_CFG06 = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__ECSPI1_SS2 = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA07__LCDIF_DATA07 = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__UART7_DCE_RTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0), + MX6_PAD_LCD_DATA07__UART7_DTE_CTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x03C0, 0x0134, 3, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__SPDIF_EXT_CLK = IOMUX_PAD(0x03C0, 0x0134, 4, 0x061C, 0, 0), + MX6_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__SRC_BT_CFG07 = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__ECSPI1_SS3 = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA08__LCDIF_DATA08 = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__SPDIF_IN = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0), + MX6_PAD_LCD_DATA08__CSI_DATA16 = IOMUX_PAD(0x03C4, 0x0138, 3, 0x0504, 1, 0), + MX6_PAD_LCD_DATA08__EIM_DATA00 = IOMUX_PAD(0x03C4, 0x0138, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x03C4, 0x0138, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__SRC_BT_CFG08 = IOMUX_PAD(0x03C4, 0x0138, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA08__FLEXCAN1_TX = IOMUX_PAD(0x03C4, 0x0138, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA09__LCDIF_DATA09 = IOMUX_PAD(0x03C8, 0x013C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__SAI3_MCLK = IOMUX_PAD(0x03C8, 0x013C, 1, 0x0600, 1, 0), + MX6_PAD_LCD_DATA09__CSI_DATA17 = IOMUX_PAD(0x03C8, 0x013C, 3, 0x0508, 1, 0), + MX6_PAD_LCD_DATA09__EIM_DATA01 = IOMUX_PAD(0x03C8, 0x013C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x03C8, 0x013C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__SRC_BT_CFG09 = IOMUX_PAD(0x03C8, 0x013C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA09__FLEXCAN1_RX = IOMUX_PAD(0x03C8, 0x013C, 8, 0x0584, 2, 0), + + MX6_PAD_LCD_DATA10__LCDIF_DATA10 = IOMUX_PAD(0x03CC, 0x0140, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__SAI3_RX_SYNC = IOMUX_PAD(0x03CC, 0x0140, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__CSI_DATA18 = IOMUX_PAD(0x03CC, 0x0140, 3, 0x050C, 1, 0), + MX6_PAD_LCD_DATA10__EIM_DATA02 = IOMUX_PAD(0x03CC, 0x0140, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x03CC, 0x0140, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__SRC_BT_CFG10 = IOMUX_PAD(0x03CC, 0x0140, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__FLEXCAN2_TX = IOMUX_PAD(0x03CC, 0x0140, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA11__LCDIF_DATA11 = IOMUX_PAD(0x03D0, 0x0144, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__SAI3_RX_BCLK = IOMUX_PAD(0x03D0, 0x0144, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__CSI_DATA19 = IOMUX_PAD(0x03D0, 0x0144, 3, 0x0510, 1, 0), + MX6_PAD_LCD_DATA11__EIM_DATA03 = IOMUX_PAD(0x03D0, 0x0144, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x03D0, 0x0144, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__SRC_BT_CFG11 = IOMUX_PAD(0x03D0, 0x0144, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__FLEXCAN2_RX = IOMUX_PAD(0x03D0, 0x0144, 8, 0x0588, 2, 0), + + MX6_PAD_LCD_DATA12__LCDIF_DATA12 = IOMUX_PAD(0x03D4, 0x0148, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__SAI3_TX_SYNC = IOMUX_PAD(0x03D4, 0x0148, 1, 0x060C, 1, 0), + MX6_PAD_LCD_DATA12__CSI_DATA20 = IOMUX_PAD(0x03D4, 0x0148, 3, 0x0514, 1, 0), + MX6_PAD_LCD_DATA12__EIM_DATA04 = IOMUX_PAD(0x03D4, 0x0148, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x03D4, 0x0148, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__SRC_BT_CFG12 = IOMUX_PAD(0x03D4, 0x0148, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA12__ECSPI1_RDY = IOMUX_PAD(0x03D4, 0x0148, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA13__LCDIF_DATA13 = IOMUX_PAD(0x03D8, 0x014C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__SAI3_TX_BCLK = IOMUX_PAD(0x03D8, 0x014C, 1, 0x0608, 1, 0), + MX6_PAD_LCD_DATA13__CSI_DATA21 = IOMUX_PAD(0x03D8, 0x014C, 3, 0x0518, 1, 0), + MX6_PAD_LCD_DATA13__EIM_DATA05 = IOMUX_PAD(0x03D8, 0x014C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x03D8, 0x014C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__SRC_BT_CFG13 = IOMUX_PAD(0x03D8, 0x014C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA13__USDHC2_RESET_B = IOMUX_PAD(0x03D8, 0x014C, 8, 0x0000, 0, 0), + + MX6_PAD_LCD_DATA14__LCDIF_DATA14 = IOMUX_PAD(0x03DC, 0x0150, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__SAI3_RX_DATA = IOMUX_PAD(0x03DC, 0x0150, 1, 0x0604, 1, 0), + MX6_PAD_LCD_DATA14__CSI_DATA22 = IOMUX_PAD(0x03DC, 0x0150, 3, 0x051C, 1, 0), + MX6_PAD_LCD_DATA14__EIM_DATA06 = IOMUX_PAD(0x03DC, 0x0150, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__SRC_BT_CFG14 = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA14__USDHC2_DATA4 = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0), + + MX6_PAD_LCD_DATA15__LCDIF_DATA15 = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__SAI3_TX_DATA = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__CSI_DATA23 = IOMUX_PAD(0x03E0, 0x0154, 3, 0x0520, 1, 0), + MX6_PAD_LCD_DATA15__EIM_DATA07 = IOMUX_PAD(0x03E0, 0x0154, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__SRC_BT_CFG15 = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__USDHC2_DATA5 = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0), + + MX6_PAD_LCD_DATA16__LCDIF_DATA16 = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__UART7_DCE_TX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__UART7_DTE_RX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0654, 2, 0), + MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x03E4, 0x0158, 3, 0x04D4, 1, 0), + MX6_PAD_LCD_DATA16__EIM_DATA08 = IOMUX_PAD(0x03E4, 0x0158, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__SRC_BT_CFG24 = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA16__USDHC2_DATA6 = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0), + + MX6_PAD_LCD_DATA17__LCDIF_DATA17 = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0), + MX6_PAD_LCD_DATA17__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x03E8, 0x015C, 3, 0x04D0, 1, 0), + MX6_PAD_LCD_DATA17__EIM_DATA09 = IOMUX_PAD(0x03E8, 0x015C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__SRC_BT_CFG25 = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__USDHC2_DATA7 = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0), + + MX6_PAD_LCD_DATA18__LCDIF_DATA18 = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__PWM5_OUT = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__CA7_MX6ULL_EVENTO = IOMUX_PAD(0x03EC, 0x0160, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__CSI_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 3, 0x04EC, 1, 0), + MX6_PAD_LCD_DATA18__EIM_DATA10 = IOMUX_PAD(0x03EC, 0x0160, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__GPIO3_IO23 = IOMUX_PAD(0x03EC, 0x0160, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__SRC_BT_CFG26 = IOMUX_PAD(0x03EC, 0x0160, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA18__USDHC2_CMD = IOMUX_PAD(0x03EC, 0x0160, 8, 0x0678, 1, 0), + MX6_PAD_LCD_DATA19__EIM_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__GPIO3_IO24 = IOMUX_PAD(0x03F0, 0x0164, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__SRC_BT_CFG27 = IOMUX_PAD(0x03F0, 0x0164, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__USDHC2_CLK = IOMUX_PAD(0x03F0, 0x0164, 8, 0x0670, 1, 0), + + MX6_PAD_LCD_DATA19__LCDIF_DATA19 = IOMUX_PAD(0x03F0, 0x0164, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__PWM6_OUT = IOMUX_PAD(0x03F0, 0x0164, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__WDOG1_WDOG_ANY = IOMUX_PAD(0x03F0, 0x0164, 2, 0x0000, 0, 0), + MX6_PAD_LCD_DATA19__CSI_DATA11 = IOMUX_PAD(0x03F0, 0x0164, 3, 0x04F0, 1, 0), + MX6_PAD_LCD_DATA20__EIM_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__GPIO3_IO25 = IOMUX_PAD(0x03F4, 0x0168, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__SRC_BT_CFG28 = IOMUX_PAD(0x03F4, 0x0168, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__USDHC2_DATA0 = IOMUX_PAD(0x03F4, 0x0168, 8, 0x067C, 1, 0), + + MX6_PAD_LCD_DATA20__LCDIF_DATA20 = IOMUX_PAD(0x03F4, 0x0168, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__UART8_DCE_TX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA20__UART8_DTE_RX = IOMUX_PAD(0x03F4, 0x0168, 1, 0x065C, 2, 0), + MX6_PAD_LCD_DATA20__ECSPI1_SCLK = IOMUX_PAD(0x03F4, 0x0168, 2, 0x0534, 0, 0), + MX6_PAD_LCD_DATA20__CSI_DATA12 = IOMUX_PAD(0x03F4, 0x0168, 3, 0x04F4, 1, 0), + + MX6_PAD_LCD_DATA21__LCDIF_DATA21 = IOMUX_PAD(0x03F8, 0x016C, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__UART8_DCE_RX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x065C, 3, 0), + MX6_PAD_LCD_DATA21__UART8_DTE_TX = IOMUX_PAD(0x03F8, 0x016C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__ECSPI1_SS0 = IOMUX_PAD(0x03F8, 0x016C, 2, 0x0540, 0, 0), + MX6_PAD_LCD_DATA21__CSI_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 3, 0x04F8, 1, 0), + MX6_PAD_LCD_DATA21__EIM_DATA13 = IOMUX_PAD(0x03F8, 0x016C, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__SRC_BT_CFG29 = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA21__USDHC2_DATA1 = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0), + + MX6_PAD_LCD_DATA22__LCDIF_DATA22 = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__MQS_RIGHT = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__ECSPI1_MOSI = IOMUX_PAD(0x03FC, 0x0170, 2, 0x053C, 0, 0), + MX6_PAD_LCD_DATA22__CSI_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 3, 0x04FC, 1, 0), + MX6_PAD_LCD_DATA22__EIM_DATA14 = IOMUX_PAD(0x03FC, 0x0170, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__GPIO3_IO27 = IOMUX_PAD(0x03FC, 0x0170, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__SRC_BT_CFG30 = IOMUX_PAD(0x03FC, 0x0170, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA22__USDHC2_DATA2 = IOMUX_PAD(0x03FC, 0x0170, 8, 0x0684, 0, 0), + + MX6_PAD_LCD_DATA23__LCDIF_DATA23 = IOMUX_PAD(0x0400, 0x0174, 0, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__MQS_LEFT = IOMUX_PAD(0x0400, 0x0174, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__ECSPI1_MISO = IOMUX_PAD(0x0400, 0x0174, 2, 0x0538, 0, 0), + MX6_PAD_LCD_DATA23__CSI_DATA15 = IOMUX_PAD(0x0400, 0x0174, 3, 0x0500, 1, 0), + MX6_PAD_LCD_DATA23__EIM_DATA15 = IOMUX_PAD(0x0400, 0x0174, 4, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__GPIO3_IO28 = IOMUX_PAD(0x0400, 0x0174, 5, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__SRC_BT_CFG31 = IOMUX_PAD(0x0400, 0x0174, 6, 0x0000, 0, 0), + MX6_PAD_LCD_DATA23__USDHC2_DATA3 = IOMUX_PAD(0x0400, 0x0174, 8, 0x0688, 1, 0), + + MX6_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x0404, 0x0178, 0, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__USDHC2_CLK = IOMUX_PAD(0x0404, 0x0178, 1, 0x0670, 2, 0), + MX6_PAD_NAND_RE_B__QSPI_B_SCLK = IOMUX_PAD(0x0404, 0x0178, 2, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__KPP_ROW00 = IOMUX_PAD(0x0404, 0x0178, 3, 0x05D0, 1, 0), + MX6_PAD_NAND_RE_B__EIM_EB_B00 = IOMUX_PAD(0x0404, 0x0178, 4, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__GPIO4_IO00 = IOMUX_PAD(0x0404, 0x0178, 5, 0x0000, 0, 0), + MX6_PAD_NAND_RE_B__ECSPI3_SS2 = IOMUX_PAD(0x0404, 0x0178, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x0408, 0x017C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__USDHC2_CMD = IOMUX_PAD(0x0408, 0x017C, 1, 0x0678, 2, 0), + MX6_PAD_NAND_WE_B__QSPI_B_SS0_B = IOMUX_PAD(0x0408, 0x017C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__KPP_COL00 = IOMUX_PAD(0x0408, 0x017C, 3, 0x05C4, 1, 0), + MX6_PAD_NAND_WE_B__EIM_EB_B01 = IOMUX_PAD(0x0408, 0x017C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__GPIO4_IO01 = IOMUX_PAD(0x0408, 0x017C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_WE_B__ECSPI3_SS3 = IOMUX_PAD(0x0408, 0x017C, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x040C, 0x0180, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x040C, 0x0180, 1, 0x067C, 2, 0), + MX6_PAD_NAND_DATA00__QSPI_B_SS1_B = IOMUX_PAD(0x040C, 0x0180, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__KPP_ROW01 = IOMUX_PAD(0x040C, 0x0180, 3, 0x05D4, 1, 0), + MX6_PAD_NAND_DATA00__EIM_AD08 = IOMUX_PAD(0x040C, 0x0180, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__GPIO4_IO02 = IOMUX_PAD(0x040C, 0x0180, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA00__ECSPI4_RDY = IOMUX_PAD(0x040C, 0x0180, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x0410, 0x0184, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0410, 0x0184, 1, 0x0680, 2, 0), + MX6_PAD_NAND_DATA01__QSPI_B_DQS = IOMUX_PAD(0x0410, 0x0184, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__KPP_COL01 = IOMUX_PAD(0x0410, 0x0184, 3, 0x05C8, 1, 0), + MX6_PAD_NAND_DATA01__EIM_AD09 = IOMUX_PAD(0x0410, 0x0184, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__GPIO4_IO03 = IOMUX_PAD(0x0410, 0x0184, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA01__ECSPI4_SS1 = IOMUX_PAD(0x0410, 0x0184, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x0414, 0x0188, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0414, 0x0188, 1, 0x0684, 1, 0), + MX6_PAD_NAND_DATA02__QSPI_B_DATA00 = IOMUX_PAD(0x0414, 0x0188, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__KPP_ROW02 = IOMUX_PAD(0x0414, 0x0188, 3, 0x05D8, 1, 0), + MX6_PAD_NAND_DATA02__EIM_AD10 = IOMUX_PAD(0x0414, 0x0188, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__GPIO4_IO04 = IOMUX_PAD(0x0414, 0x0188, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA02__ECSPI4_SS2 = IOMUX_PAD(0x0414, 0x0188, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0418, 0x018C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x0418, 0x018C, 1, 0x0688, 2, 0), + MX6_PAD_NAND_DATA03__QSPI_B_DATA01 = IOMUX_PAD(0x0418, 0x018C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__KPP_COL02 = IOMUX_PAD(0x0418, 0x018C, 3, 0x05CC, 1, 0), + MX6_PAD_NAND_DATA03__EIM_AD11 = IOMUX_PAD(0x0418, 0x018C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__GPIO4_IO05 = IOMUX_PAD(0x0418, 0x018C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA03__ECSPI4_SS3 = IOMUX_PAD(0x0418, 0x018C, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x041C, 0x0190, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x041C, 0x0190, 1, 0x068C, 1, 0), + MX6_PAD_NAND_DATA04__QSPI_B_DATA02 = IOMUX_PAD(0x041C, 0x0190, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__ECSPI4_SCLK = IOMUX_PAD(0x041C, 0x0190, 3, 0x0564, 1, 0), + MX6_PAD_NAND_DATA04__EIM_AD12 = IOMUX_PAD(0x041C, 0x0190, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__GPIO4_IO06 = IOMUX_PAD(0x041C, 0x0190, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__UART2_DCE_TX = IOMUX_PAD(0x041C, 0x0190, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA04__UART2_DTE_RX = IOMUX_PAD(0x041C, 0x0190, 8, 0x062C, 2, 0), + + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x0420, 0x0194, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0420, 0x0194, 1, 0x0690, 1, 0), + MX6_PAD_NAND_DATA05__QSPI_B_DATA03 = IOMUX_PAD(0x0420, 0x0194, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__ECSPI4_MOSI = IOMUX_PAD(0x0420, 0x0194, 3, 0x056C, 1, 0), + MX6_PAD_NAND_DATA05__EIM_AD13 = IOMUX_PAD(0x0420, 0x0194, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__GPIO4_IO07 = IOMUX_PAD(0x0420, 0x0194, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA05__UART2_DCE_RX = IOMUX_PAD(0x0420, 0x0194, 8, 0x062C, 3, 0), + MX6_PAD_NAND_DATA05__UART2_DTE_TX = IOMUX_PAD(0x0420, 0x0194, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x0424, 0x0198, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0424, 0x0198, 1, 0x0694, 1, 0), + MX6_PAD_NAND_DATA06__SAI2_RX_BCLK = IOMUX_PAD(0x0424, 0x0198, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__ECSPI4_MISO = IOMUX_PAD(0x0424, 0x0198, 3, 0x0568, 1, 0), + MX6_PAD_NAND_DATA06__EIM_AD14 = IOMUX_PAD(0x0424, 0x0198, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__GPIO4_IO08 = IOMUX_PAD(0x0424, 0x0198, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__UART2_DCE_CTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0000, 0, 0), + MX6_PAD_NAND_DATA06__UART2_DTE_RTS = IOMUX_PAD(0x0424, 0x0198, 8, 0x0628, 4, 0), + + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0428, 0x019C, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x0428, 0x019C, 1, 0x0698, 1, 0), + MX6_PAD_NAND_DATA07__QSPI_A_SS1_B = IOMUX_PAD(0x0428, 0x019C, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__ECSPI4_SS0 = IOMUX_PAD(0x0428, 0x019C, 3, 0x0570, 1, 0), + MX6_PAD_NAND_DATA07__EIM_AD15 = IOMUX_PAD(0x0428, 0x019C, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__GPIO4_IO09 = IOMUX_PAD(0x0428, 0x019C, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DATA07__UART2_DCE_RTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0628, 5, 0), + MX6_PAD_NAND_DATA07__UART2_DTE_CTS = IOMUX_PAD(0x0428, 0x019C, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x042C, 0x01A0, 0, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__USDHC2_RESET_B = IOMUX_PAD(0x042C, 0x01A0, 1, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__QSPI_A_DQS = IOMUX_PAD(0x042C, 0x01A0, 2, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__PWM3_OUT = IOMUX_PAD(0x042C, 0x01A0, 3, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__EIM_ADDR17 = IOMUX_PAD(0x042C, 0x01A0, 4, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__GPIO4_IO10 = IOMUX_PAD(0x042C, 0x01A0, 5, 0x0000, 0, 0), + MX6_PAD_NAND_ALE__ECSPI3_SS1 = IOMUX_PAD(0x042C, 0x01A0, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x0430, 0x01A4, 0, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__USDHC1_RESET_B = IOMUX_PAD(0x0430, 0x01A4, 1, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__QSPI_A_SCLK = IOMUX_PAD(0x0430, 0x01A4, 2, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__PWM4_OUT = IOMUX_PAD(0x0430, 0x01A4, 3, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__EIM_BCLK = IOMUX_PAD(0x0430, 0x01A4, 4, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__GPIO4_IO11 = IOMUX_PAD(0x0430, 0x01A4, 5, 0x0000, 0, 0), + MX6_PAD_NAND_WP_B__ECSPI3_RDY = IOMUX_PAD(0x0430, 0x01A4, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x0434, 0x01A8, 0, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__USDHC1_DATA4 = IOMUX_PAD(0x0434, 0x01A8, 1, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 = IOMUX_PAD(0x0434, 0x01A8, 2, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__ECSPI3_SS0 = IOMUX_PAD(0x0434, 0x01A8, 3, 0x0560, 1, 0), + MX6_PAD_NAND_READY_B__EIM_CS1_B = IOMUX_PAD(0x0434, 0x01A8, 4, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__GPIO4_IO12 = IOMUX_PAD(0x0434, 0x01A8, 5, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__UART3_DCE_TX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0000, 0, 0), + MX6_PAD_NAND_READY_B__UART3_DTE_RX = IOMUX_PAD(0x0434, 0x01A8, 8, 0x0634, 2, 0), + + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0438, 0x01AC, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 = IOMUX_PAD(0x0438, 0x01AC, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 = IOMUX_PAD(0x0438, 0x01AC, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__ECSPI3_SCLK = IOMUX_PAD(0x0438, 0x01AC, 3, 0x0554, 1, 0), + MX6_PAD_NAND_CE0_B__EIM_DTACK_B = IOMUX_PAD(0x0438, 0x01AC, 4, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__GPIO4_IO13 = IOMUX_PAD(0x0438, 0x01AC, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CE0_B__UART3_DCE_RX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0634, 3, 0), + MX6_PAD_NAND_CE0_B__UART3_DTE_TX = IOMUX_PAD(0x0438, 0x01AC, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x043C, 0x01B0, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 = IOMUX_PAD(0x043C, 0x01B0, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 = IOMUX_PAD(0x043C, 0x01B0, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__ECSPI3_MOSI = IOMUX_PAD(0x043C, 0x01B0, 3, 0x055C, 1, 0), + MX6_PAD_NAND_CE1_B__EIM_ADDR18 = IOMUX_PAD(0x043C, 0x01B0, 4, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__GPIO4_IO14 = IOMUX_PAD(0x043C, 0x01B0, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__UART3_DCE_CTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0000, 0, 0), + MX6_PAD_NAND_CE1_B__UART3_DTE_RTS = IOMUX_PAD(0x043C, 0x01B0, 8, 0x0630, 2, 0), + + MX6_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0440, 0x01B4, 0, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__USDHC1_DATA7 = IOMUX_PAD(0x0440, 0x01B4, 1, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 = IOMUX_PAD(0x0440, 0x01B4, 2, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__ECSPI3_MISO = IOMUX_PAD(0x0440, 0x01B4, 3, 0x0558, 1, 0), + MX6_PAD_NAND_CLE__EIM_ADDR16 = IOMUX_PAD(0x0440, 0x01B4, 4, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__GPIO4_IO15 = IOMUX_PAD(0x0440, 0x01B4, 5, 0x0000, 0, 0), + MX6_PAD_NAND_CLE__UART3_DCE_RTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0630, 3, 0), + MX6_PAD_NAND_CLE__UART3_DTE_CTS = IOMUX_PAD(0x0440, 0x01B4, 8, 0x0000, 0, 0), + + MX6_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0444, 0x01B8, 0, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__CSI_FIELD = IOMUX_PAD(0x0444, 0x01B8, 1, 0x0530, 1, 0), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B = IOMUX_PAD(0x0444, 0x01B8, 2, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__PWM5_OUT = IOMUX_PAD(0x0444, 0x01B8, 3, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__EIM_WAIT = IOMUX_PAD(0x0444, 0x01B8, 4, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__GPIO4_IO16 = IOMUX_PAD(0x0444, 0x01B8, 5, 0x0000, 0, 0), + MX6_PAD_NAND_DQS__SDMA_EXT_EVENT01 = IOMUX_PAD(0x0444, 0x01B8, 6, 0x0614, 1, 0), + MX6_PAD_NAND_DQS__SPDIF_EXT_CLK = IOMUX_PAD(0x0444, 0x01B8, 8, 0x061C, 1, 0), + + MX6_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x0448, 0x01BC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPT2_COMPARE1 = IOMUX_PAD(0x0448, 0x01BC, 1, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SAI2_RX_SYNC = IOMUX_PAD(0x0448, 0x01BC, 2, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SPDIF_OUT = IOMUX_PAD(0x0448, 0x01BC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__EIM_ADDR19 = IOMUX_PAD(0x0448, 0x01BC, 4, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__GPIO2_IO16 = IOMUX_PAD(0x0448, 0x01BC, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CMD__SDMA_EXT_EVENT00 = IOMUX_PAD(0x0448, 0x01BC, 6, 0x0610, 2, 0), + MX6_PAD_SD1_CMD__USB_OTG1_PWR = IOMUX_PAD(0x0448, 0x01BC, 8, 0x0000, 0, 0), + + MX6_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x044C, 0x01C0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPT2_COMPARE2 = IOMUX_PAD(0x044C, 0x01C0, 1, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__SAI2_MCLK = IOMUX_PAD(0x044C, 0x01C0, 2, 0x05F0, 1, 0), + MX6_PAD_SD1_CLK__SPDIF_IN = IOMUX_PAD(0x044C, 0x01C0, 3, 0x0618, 3, 0), + MX6_PAD_SD1_CLK__EIM_ADDR20 = IOMUX_PAD(0x044C, 0x01C0, 4, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__GPIO2_IO17 = IOMUX_PAD(0x044C, 0x01C0, 5, 0x0000, 0, 0), + MX6_PAD_SD1_CLK__USB_OTG1_OC = IOMUX_PAD(0x044C, 0x01C0, 8, 0x0664, 2, 0), + + MX6_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x0450, 0x01C4, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__GPT2_COMPARE3 = IOMUX_PAD(0x0450, 0x01C4, 1, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__SAI2_TX_SYNC = IOMUX_PAD(0x0450, 0x01C4, 2, 0x05FC, 1, 0), + MX6_PAD_SD1_DATA0__FLEXCAN1_TX = IOMUX_PAD(0x0450, 0x01C4, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__EIM_ADDR21 = IOMUX_PAD(0x0450, 0x01C4, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__GPIO2_IO18 = IOMUX_PAD(0x0450, 0x01C4, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA0__ANATOP_OTG1_ID = IOMUX_PAD(0x0450, 0x01C4, 8, 0x04B8, 2, 0), + + MX6_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x0454, 0x01C8, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__GPT2_CLK = IOMUX_PAD(0x0454, 0x01C8, 1, 0x05A0, 1, 0), + MX6_PAD_SD1_DATA1__SAI2_TX_BCLK = IOMUX_PAD(0x0454, 0x01C8, 2, 0x05F8, 1, 0), + MX6_PAD_SD1_DATA1__FLEXCAN1_RX = IOMUX_PAD(0x0454, 0x01C8, 3, 0x0584, 3, 0), + MX6_PAD_SD1_DATA1__EIM_ADDR22 = IOMUX_PAD(0x0454, 0x01C8, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__GPIO2_IO19 = IOMUX_PAD(0x0454, 0x01C8, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0454, 0x01C8, 8, 0x0000, 0, 0), + + MX6_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x0458, 0x01CC, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__GPT2_CAPTURE1 = IOMUX_PAD(0x0458, 0x01CC, 1, 0x0598, 1, 0), + MX6_PAD_SD1_DATA2__SAI2_RX_DATA = IOMUX_PAD(0x0458, 0x01CC, 2, 0x05F4, 1, 0), + MX6_PAD_SD1_DATA2__FLEXCAN2_TX = IOMUX_PAD(0x0458, 0x01CC, 3, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__EIM_ADDR23 = IOMUX_PAD(0x0458, 0x01CC, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__GPIO2_IO20 = IOMUX_PAD(0x0458, 0x01CC, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__CCM_CLKO1 = IOMUX_PAD(0x0458, 0x01CC, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA2__USB_OTG2_OC = IOMUX_PAD(0x0458, 0x01CC, 8, 0x0660, 2, 0), + + MX6_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x045C, 0x01D0, 0, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__GPT2_CAPTURE2 = IOMUX_PAD(0x045C, 0x01D0, 1, 0x059C, 1, 0), + MX6_PAD_SD1_DATA3__SAI2_TX_DATA = IOMUX_PAD(0x045C, 0x01D0, 2, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__FLEXCAN2_RX = IOMUX_PAD(0x045C, 0x01D0, 3, 0x0588, 3, 0), + MX6_PAD_SD1_DATA3__EIM_ADDR24 = IOMUX_PAD(0x045C, 0x01D0, 4, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__GPIO2_IO21 = IOMUX_PAD(0x045C, 0x01D0, 5, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__CCM_CLKO2 = IOMUX_PAD(0x045C, 0x01D0, 6, 0x0000, 0, 0), + MX6_PAD_SD1_DATA3__ANATOP_OTG2_ID = IOMUX_PAD(0x045C, 0x01D0, 8, 0x04BC, 2, 0), + + MX6_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x0460, 0x01D4, 0, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__USDHC2_CD_B = IOMUX_PAD(0x0460, 0x01D4, 1, 0x0674, 0, 0), + MX6_PAD_CSI_MCLK__RAWNAND_CE2_B = IOMUX_PAD(0x0460, 0x01D4, 2, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__I2C1_SDA = IOMUX_PAD(0x0460, 0x01D4, IOMUX_CONFIG_SION | 3, 0x05A8, 0, 0), + MX6_PAD_CSI_MCLK__EIM_CS0_B = IOMUX_PAD(0x0460, 0x01D4, 4, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__GPIO4_IO17 = IOMUX_PAD(0x0460, 0x01D4, 5, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL = IOMUX_PAD(0x0460, 0x01D4, 6, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__UART6_DCE_TX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x0000, 0, 0), + MX6_PAD_CSI_MCLK__UART6_DTE_RX = IOMUX_PAD(0x0460, 0x01D4, 8, 0x064C, 0, 0), + + MX6_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x0464, 0x01D8, 0, 0x0528, 1, 0), + MX6_PAD_CSI_PIXCLK__USDHC2_WP = IOMUX_PAD(0x0464, 0x01D8, 1, 0x069C, 2, 0), + MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B = IOMUX_PAD(0x0464, 0x01D8, 2, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__I2C1_SCL = IOMUX_PAD(0x0464, 0x01D8, IOMUX_CONFIG_SION | 3, 0x05A4, 2, 0), + MX6_PAD_CSI_PIXCLK__EIM_OE = IOMUX_PAD(0x0464, 0x01D8, 4, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__GPIO4_IO18 = IOMUX_PAD(0x0464, 0x01D8, 5, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 = IOMUX_PAD(0x0464, 0x01D8, 6, 0x0000, 0, 0), + MX6_PAD_CSI_PIXCLK__UART6_DCE_RX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x064C, 3, 0), + MX6_PAD_CSI_PIXCLK__UART6_DTE_TX = IOMUX_PAD(0x0464, 0x01D8, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x0468, 0x01DC, 0, 0x052C, 0, 0), + MX6_PAD_CSI_VSYNC__USDHC2_CLK = IOMUX_PAD(0x0468, 0x01DC, 1, 0x0670, 0, 0), + MX6_PAD_CSI_VSYNC__SIM1_PORT1_CLK = IOMUX_PAD(0x0468, 0x01DC, 2, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__I2C2_SDA = IOMUX_PAD(0x0468, 0x01DC, IOMUX_CONFIG_SION | 3, 0x05B0, 0, 0), + MX6_PAD_CSI_VSYNC__EIM_RW = IOMUX_PAD(0x0468, 0x01DC, 4, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__GPIO4_IO19 = IOMUX_PAD(0x0468, 0x01DC, 5, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__PWM7_OUT = IOMUX_PAD(0x0468, 0x01DC, 6, 0x0000, 0, 0), + MX6_PAD_CSI_VSYNC__UART6_DCE_RTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0648, 0, 0), + MX6_PAD_CSI_VSYNC__UART6_DTE_CTS = IOMUX_PAD(0x0468, 0x01DC, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x046C, 0x01E0, 0, 0x0524, 0, 0), + MX6_PAD_CSI_HSYNC__USDHC2_CMD = IOMUX_PAD(0x046C, 0x01E0, 1, 0x0678, 0, 0), + MX6_PAD_CSI_HSYNC__SIM1_PORT1_PD = IOMUX_PAD(0x046C, 0x01E0, 2, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__I2C2_SCL = IOMUX_PAD(0x046C, 0x01E0, IOMUX_CONFIG_SION | 3, 0x05AC, 0, 0), + MX6_PAD_CSI_HSYNC__EIM_LBA_B = IOMUX_PAD(0x046C, 0x01E0, 4, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__GPIO4_IO20 = IOMUX_PAD(0x046C, 0x01E0, 5, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__PWM8_OUT = IOMUX_PAD(0x046C, 0x01E0, 6, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__UART6_DCE_CTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0000, 0, 0), + MX6_PAD_CSI_HSYNC__UART6_DTE_RTS = IOMUX_PAD(0x046C, 0x01E0, 8, 0x0648, 1, 0), + + MX6_PAD_CSI_DATA00__CSI_DATA02 = IOMUX_PAD(0x0470, 0x01E4, 0, 0x04C4, 0, 0), + MX6_PAD_CSI_DATA00__USDHC2_DATA0 = IOMUX_PAD(0x0470, 0x01E4, 1, 0x067C, 0, 0), + MX6_PAD_CSI_DATA00__SIM1_PORT1_RST_B = IOMUX_PAD(0x0470, 0x01E4, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__ECSPI2_SCLK = IOMUX_PAD(0x0470, 0x01E4, 3, 0x0544, 0, 0), + MX6_PAD_CSI_DATA00__EIM_AD00 = IOMUX_PAD(0x0470, 0x01E4, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__GPIO4_IO21 = IOMUX_PAD(0x0470, 0x01E4, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__SRC_INT_BOOT = IOMUX_PAD(0x0470, 0x01E4, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__UART5_DCE_TX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA00__UART5_DTE_RX = IOMUX_PAD(0x0470, 0x01E4, 8, 0x0644, 0, 0), + + MX6_PAD_CSI_DATA01__CSI_DATA03 = IOMUX_PAD(0x0474, 0x01E8, 0, 0x04C8, 0, 0), + MX6_PAD_CSI_DATA01__USDHC2_DATA1 = IOMUX_PAD(0x0474, 0x01E8, 1, 0x0680, 0, 0), + MX6_PAD_CSI_DATA01__SIM1_PORT1_SVEN = IOMUX_PAD(0x0474, 0x01E8, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__ECSPI2_SS0 = IOMUX_PAD(0x0474, 0x01E8, 3, 0x0550, 0, 0), + MX6_PAD_CSI_DATA01__EIM_AD01 = IOMUX_PAD(0x0474, 0x01E8, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__GPIO4_IO22 = IOMUX_PAD(0x0474, 0x01E8, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA01__SAI1_MCLK = IOMUX_PAD(0x0474, 0x01E8, 6, 0x05E0, 0, 0), + MX6_PAD_CSI_DATA01__UART5_DCE_RX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0644, 1, 0), + MX6_PAD_CSI_DATA01__UART5_DTE_TX = IOMUX_PAD(0x0474, 0x01E8, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA02__CSI_DATA04 = IOMUX_PAD(0x0478, 0x01EC, 0, 0x04D8, 1, 0), + MX6_PAD_CSI_DATA02__USDHC2_DATA2 = IOMUX_PAD(0x0478, 0x01EC, 1, 0x0684, 2, 0), + MX6_PAD_CSI_DATA02__SIM1_PORT1_TRXD = IOMUX_PAD(0x0478, 0x01EC, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__ECSPI2_MOSI = IOMUX_PAD(0x0478, 0x01EC, 3, 0x054C, 1, 0), + MX6_PAD_CSI_DATA02__EIM_AD02 = IOMUX_PAD(0x0478, 0x01EC, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__GPIO4_IO23 = IOMUX_PAD(0x0478, 0x01EC, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__SAI1_RX_SYNC = IOMUX_PAD(0x0478, 0x01EC, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA02__UART5_DCE_RTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0640, 5, 0), + MX6_PAD_CSI_DATA02__UART5_DTE_CTS = IOMUX_PAD(0x0478, 0x01EC, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA03__CSI_DATA05 = IOMUX_PAD(0x047C, 0x01F0, 0, 0x04CC, 0, 0), + MX6_PAD_CSI_DATA03__USDHC2_DATA3 = IOMUX_PAD(0x047C, 0x01F0, 1, 0x0688, 0, 0), + MX6_PAD_CSI_DATA03__SIM2_PORT1_PD = IOMUX_PAD(0x047C, 0x01F0, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__ECSPI2_MISO = IOMUX_PAD(0x047C, 0x01F0, 3, 0x0548, 0, 0), + MX6_PAD_CSI_DATA03__EIM_AD03 = IOMUX_PAD(0x047C, 0x01F0, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__GPIO4_IO24 = IOMUX_PAD(0x047C, 0x01F0, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__SAI1_RX_BCLK = IOMUX_PAD(0x047C, 0x01F0, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__UART5_DCE_CTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0000, 0, 0), + MX6_PAD_CSI_DATA03__UART5_DTE_RTS = IOMUX_PAD(0x047C, 0x01F0, 8, 0x0640, 0, 0), + + MX6_PAD_CSI_DATA04__CSI_DATA06 = IOMUX_PAD(0x0480, 0x01F4, 0, 0x04DC, 1, 0), + MX6_PAD_CSI_DATA04__USDHC2_DATA4 = IOMUX_PAD(0x0480, 0x01F4, 1, 0x068C, 2, 0), + MX6_PAD_CSI_DATA04__SIM2_PORT1_CLK = IOMUX_PAD(0x0480, 0x01F4, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__ECSPI1_SCLK = IOMUX_PAD(0x0480, 0x01F4, 3, 0x0534, 1, 0), + MX6_PAD_CSI_DATA04__EIM_AD04 = IOMUX_PAD(0x0480, 0x01F4, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__GPIO4_IO25 = IOMUX_PAD(0x0480, 0x01F4, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA04__SAI1_TX_SYNC = IOMUX_PAD(0x0480, 0x01F4, 6, 0x05EC, 1, 0), + MX6_PAD_CSI_DATA04__USDHC1_WP = IOMUX_PAD(0x0480, 0x01F4, 8, 0x066C, 2, 0), + + MX6_PAD_CSI_DATA05__CSI_DATA07 = IOMUX_PAD(0x0484, 0x01F8, 0, 0x04E0, 1, 0), + MX6_PAD_CSI_DATA05__USDHC2_DATA5 = IOMUX_PAD(0x0484, 0x01F8, 1, 0x0690, 2, 0), + MX6_PAD_CSI_DATA05__SIM2_PORT1_RST_B = IOMUX_PAD(0x0484, 0x01F8, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__ECSPI1_SS0 = IOMUX_PAD(0x0484, 0x01F8, 3, 0x0540, 1, 0), + MX6_PAD_CSI_DATA05__EIM_AD05 = IOMUX_PAD(0x0484, 0x01F8, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__GPIO4_IO26 = IOMUX_PAD(0x0484, 0x01F8, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA05__SAI1_TX_BCLK = IOMUX_PAD(0x0484, 0x01F8, 6, 0x05E8, 1, 0), + MX6_PAD_CSI_DATA05__USDHC1_CD_B = IOMUX_PAD(0x0484, 0x01F8, 8, 0x0668, 2, 0), + + MX6_PAD_CSI_DATA06__CSI_DATA08 = IOMUX_PAD(0x0488, 0x01FC, 0, 0x04E4, 1, 0), + MX6_PAD_CSI_DATA06__USDHC2_DATA6 = IOMUX_PAD(0x0488, 0x01FC, 1, 0x0694, 2, 0), + MX6_PAD_CSI_DATA06__SIM2_PORT1_SVEN = IOMUX_PAD(0x0488, 0x01FC, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__ECSPI1_MOSI = IOMUX_PAD(0x0488, 0x01FC, 3, 0x053C, 1, 0), + MX6_PAD_CSI_DATA06__EIM_AD06 = IOMUX_PAD(0x0488, 0x01FC, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__GPIO4_IO27 = IOMUX_PAD(0x0488, 0x01FC, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA06__SAI1_RX_DATA = IOMUX_PAD(0x0488, 0x01FC, 6, 0x05E4, 1, 0), + MX6_PAD_CSI_DATA06__USDHC1_RESET_B = IOMUX_PAD(0x0488, 0x01FC, 8, 0x0000, 0, 0), + + MX6_PAD_CSI_DATA07__CSI_DATA09 = IOMUX_PAD(0x048C, 0x0200, 0, 0x04E8, 1, 0), + MX6_PAD_CSI_DATA07__USDHC2_DATA7 = IOMUX_PAD(0x048C, 0x0200, 1, 0x0698, 2, 0), + MX6_PAD_CSI_DATA07__SIM2_PORT1_TRXD = IOMUX_PAD(0x048C, 0x0200, 2, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__ECSPI1_MISO = IOMUX_PAD(0x048C, 0x0200, 3, 0x0538, 1, 0), + MX6_PAD_CSI_DATA07__EIM_AD07 = IOMUX_PAD(0x048C, 0x0200, 4, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__GPIO4_IO28 = IOMUX_PAD(0x048C, 0x0200, 5, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__SAI1_TX_DATA = IOMUX_PAD(0x048C, 0x0200, 6, 0x0000, 0, 0), + MX6_PAD_CSI_DATA07__USDHC1_VSELECT = IOMUX_PAD(0x048C, 0x0200, 8, 0x0000, 0, 0), +}; +#endif /* __ASM_ARCH_IMX6ULL_PINS_H__ */ diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h index 9b79506..171f4d9 100644 --- a/arch/arm/include/asm/atomic.h +++ b/arch/arm/include/asm/atomic.h @@ -21,6 +21,11 @@ #endif typedef struct { volatile int counter; } atomic_t; +#if BITS_PER_LONG == 32 +typedef struct { volatile long long counter; } atomic64_t; +#else /* BIT_PER_LONG == 32 */ +typedef struct { volatile long counter; } atomic64_t; +#endif #define ATOMIC_INIT(i) { (i) } @@ -28,7 +33,9 @@ typedef struct { volatile int counter; } atomic_t; #include <asm/proc-armv/system.h> #define atomic_read(v) ((v)->counter) -#define atomic_set(v,i) (((v)->counter) = (i)) +#define atomic_set(v, i) (((v)->counter) = (i)) +#define atomic64_read(v) atomic_read(v) +#define atomic64_set(v, i) atomic_set(v, i) static inline void atomic_add(int i, volatile atomic_t *v) { @@ -101,6 +108,65 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr) local_irq_restore(flags); } +#if BITS_PER_LONG == 32 + +static inline void atomic64_add(long long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic64_sub(long long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} + +#else /* BIT_PER_LONG == 32 */ + +static inline void atomic64_add(long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic64_sub(long i, volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} +#endif + +static inline void atomic64_inc(volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter += 1; + local_irq_restore(flags); +} + +static inline void atomic64_dec(volatile atomic64_t *v) +{ + unsigned long flags = 0; + + local_irq_save(flags); + v->counter -= 1; + local_irq_restore(flags); +} + /* Atomic operations are already serializing on ARM */ #define smp_mb__before_atomic_dec() barrier() #define smp_mb__after_atomic_dec() barrier() diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index 2e49968..b3af696 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -39,10 +39,9 @@ * MUX_CTRL_OFS: 0..11 (12) * PAD_CTRL_OFS: 12..23 (12) * SEL_INPUT_OFS: 24..35 (12) - * MUX_MODE + SION: 36..40 (5) - * PAD_CTRL + NO_PAD_CTRL: 41..58 (18) - * SEL_INP: 59..62 (4) - * reserved: 63 (1) + * MUX_MODE + SION + LPSR: 36..41 (6) + * PAD_CTRL + NO_PAD_CTRL: 42..59 (18) + * SEL_INP: 60..63 (4) */ typedef u64 iomux_v3_cfg_t; @@ -57,10 +56,10 @@ typedef u64 iomux_v3_cfg_t; MUX_SEL_INPUT_OFS_SHIFT) #define MUX_MODE_SHIFT 36 -#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) -#define MUX_PAD_CTRL_SHIFT 41 +#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x3f << MUX_MODE_SHIFT) +#define MUX_PAD_CTRL_SHIFT 42 #define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) -#define MUX_SEL_INPUT_SHIFT 59 +#define MUX_SEL_INPUT_SHIFT 60 #define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) #define MUX_MODE_SION ((iomux_v3_cfg_t)IOMUX_CONFIG_SION << \ @@ -85,12 +84,12 @@ typedef u64 iomux_v3_cfg_t; #define NO_PAD_CTRL (1 << 17) +#define IOMUX_CONFIG_LPSR 0x20 +#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ + MUX_MODE_SHIFT) #ifdef CONFIG_MX7 #define IOMUX_LPSR_SEL_INPUT_OFS 0x70000 -#define IOMUX_CONFIG_LPSR 0x8 -#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ - MUX_MODE_SHIFT) #define PAD_CTL_DSE_1P8V_140OHM (0x0<<0) #define PAD_CTL_DSE_1P8V_35OHM (0x1<<0) diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h index 32f95b3..6ace8bb 100644 --- a/arch/arm/include/asm/imx-common/sys_proto.h +++ b/arch/arm/include/asm/imx-common/sys_proto.h @@ -33,6 +33,7 @@ #define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX)) #define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL)) #define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL)) +#define is_mx6ull() (is_cpu_type(MXC_CPU_MX6ULL)) u32 get_nr_cpus(void); u32 get_cpu_rev(void); diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 1864ab9..6b46078 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h @@ -45,7 +45,7 @@ static inline void *phys_to_virt(unsigned long x) /* * Virtual <-> DMA view memory address translations * Again, these are *only* valid on the kernel direct mapped RAM - * memory. Use of these is *depreciated*. + * memory. Use of these is *deprecated*. */ #define virt_to_bus(x) (__virt_to_bus((unsigned long)(x))) #define bus_to_virt(x) ((void *)(__bus_to_virt((unsigned long)(x)))) @@ -127,7 +127,7 @@ static inline void *phys_to_virt(unsigned long x) #endif /* - * We should really eliminate virt_to_bus() here - it's depreciated. + * We should really eliminate virt_to_bus() here - it's deprecated. */ #define page_to_bus(page) (virt_to_bus(page_address(page))) diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h index f7b97ef..df9934b 100644 --- a/arch/arm/include/asm/setjmp.h +++ b/arch/arm/include/asm/setjmp.h @@ -11,29 +11,26 @@ struct jmp_buf_data { ulong target; ulong regs[5]; + int ret; }; typedef struct jmp_buf_data jmp_buf[1]; static inline int setjmp(jmp_buf jmp) { - long r = 0; + jmp->ret = 0; #ifdef CONFIG_ARM64 asm volatile( "adr x1, jmp_target\n" - "str x1, %1\n" - "stp x26, x27, %2\n" - "stp x28, x29, %3\n" + "str x1, %0\n" + "stp x26, x27, %1\n" + "stp x28, x29, %2\n" "mov x1, sp\n" - "str x1, %4\n" - "b 2f\n" + "str x1, %3\n" "jmp_target: " - "mov %0, #1\n" - "2:\n" - : "+r" (r), "=m" (jmp->target), - "=m" (jmp->regs[0]), "=m" (jmp->regs[2]), - "=m" (jmp->regs[4]) + : "=m" (jmp->target), "=m" (jmp->regs[0]), + "=m" (jmp->regs[2]), "=m" (jmp->regs[4]) : : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", @@ -49,26 +46,25 @@ static inline int setjmp(jmp_buf jmp) #else "adr r0, jmp_target\n" #endif - "mov r1, %1\n" + "mov r1, %0\n" "mov r2, sp\n" "stm r1!, {r0, r2, r4, r5, r6, r7}\n" - "b 2f\n" ".align 2\n" "jmp_target: \n" - "mov %0, #1\n" - "2:\n" - : "+l" (r) + : : "l" (&jmp->target) : "r0", "r1", "r2", "r3", /* "r4", "r5", "r6", "r7", */ "r8", "r9", "r10", "r11", /* sp, */ "ip", "lr", "cc", "memory"); #endif - return r; + return jmp->ret; } -static inline __noreturn void longjmp(jmp_buf jmp) +static inline __noreturn void longjmp(jmp_buf jmp, int ret) { + jmp->ret = ret; + #ifdef CONFIG_ARM64 asm volatile( "ldr x0, %0\n" diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h index 78a7fac..3a4e902 100644 --- a/arch/arm/include/asm/setup.h +++ b/arch/arm/include/asm/setup.h @@ -132,7 +132,7 @@ struct tag_ramdisk { /* describes where the compressed ramdisk image lives (virtual address) */ /* * this one accidentally used virtual addresses - as such, - * its depreciated. + * it's deprecated. */ #define ATAG_INITRD 0x54410005 diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 6f312d6..a0bda28 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -33,15 +33,6 @@ enum { }; #endif -/** - * Board specific load method for boards that have a special way of loading - * U-Boot, which does not fit with the existing SPL code. - * - * @return 0 on success, negative errno value on failure. - */ - -int spl_board_load_image(void); - /* Linker symbols. */ extern char __bss_start[], __bss_end[]; diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 7b7b867..c18e1e3 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -223,6 +223,10 @@ void __noreturn psci_system_reset(bool smc); */ void save_boot_params_ret(void); +#ifdef CONFIG_ARMV7_LPAE +void switch_to_hypervisor_ret(void); +#endif + #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); #ifdef __ARM_ARCH_7A__ diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index a0d0d9b..0627728 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -51,9 +51,9 @@ /* MDIO module input frequency */ #ifdef CONFIG_SOC_K2G -#define EMAC_MDIO_BUS_FREQ (clk_get_rate(sys_clk0_3_clk)) +#define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(sys_clk0_3_clk)) #else -#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk)) +#define EMAC_MDIO_BUS_FREQ (ks_clk_get_rate(pass_pll_clk)) #endif /* MDIO clock output frequency */ #define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index 3587ad6..e606d47 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -47,7 +47,7 @@ void __weak board_init_f(ulong dummy) * arg: Pointer to paramter image in RAM */ #ifdef CONFIG_SPL_OS_BOOT -void __noreturn jump_to_image_linux(void *arg) +void __noreturn jump_to_image_linux(struct spl_image_info *spl_image, void *arg) { unsigned long machid = 0xffffffff; #ifdef CONFIG_MACH_TYPE @@ -58,7 +58,7 @@ void __noreturn jump_to_image_linux(void *arg) typedef void (*image_entry_arg_t)(int, int, void *) __attribute__ ((noreturn)); image_entry_arg_t image_entry = - (image_entry_arg_t)(uintptr_t) spl_image.entry_point; + (image_entry_arg_t)(uintptr_t) spl_image->entry_point; cleanup_before_linux(); image_entry(0, machid, arg); } diff --git a/arch/arm/mach-keystone/clock.c b/arch/arm/mach-keystone/clock.c index b25db1e..d8804724 100644 --- a/arch/arm/mach-keystone/clock.c +++ b/arch/arm/mach-keystone/clock.c @@ -341,7 +341,7 @@ static unsigned long pll_freq_get(int pll) return ret; } -unsigned long clk_get_rate(unsigned int clk) +unsigned long ks_clk_get_rate(unsigned int clk) { unsigned long freq = 0; @@ -381,37 +381,37 @@ unsigned long clk_get_rate(unsigned int clk) freq = pll_freq_get(CORE_PLL) / pll0div_read(4); break; case sys_clk0_2_clk: - freq = clk_get_rate(sys_clk0_clk) / 2; + freq = ks_clk_get_rate(sys_clk0_clk) / 2; break; case sys_clk0_3_clk: - freq = clk_get_rate(sys_clk0_clk) / 3; + freq = ks_clk_get_rate(sys_clk0_clk) / 3; break; case sys_clk0_4_clk: - freq = clk_get_rate(sys_clk0_clk) / 4; + freq = ks_clk_get_rate(sys_clk0_clk) / 4; break; case sys_clk0_6_clk: - freq = clk_get_rate(sys_clk0_clk) / 6; + freq = ks_clk_get_rate(sys_clk0_clk) / 6; break; case sys_clk0_8_clk: - freq = clk_get_rate(sys_clk0_clk) / 8; + freq = ks_clk_get_rate(sys_clk0_clk) / 8; break; case sys_clk0_12_clk: - freq = clk_get_rate(sys_clk0_clk) / 12; + freq = ks_clk_get_rate(sys_clk0_clk) / 12; break; case sys_clk0_24_clk: - freq = clk_get_rate(sys_clk0_clk) / 24; + freq = ks_clk_get_rate(sys_clk0_clk) / 24; break; case sys_clk1_3_clk: - freq = clk_get_rate(sys_clk1_clk) / 3; + freq = ks_clk_get_rate(sys_clk1_clk) / 3; break; case sys_clk1_4_clk: - freq = clk_get_rate(sys_clk1_clk) / 4; + freq = ks_clk_get_rate(sys_clk1_clk) / 4; break; case sys_clk1_6_clk: - freq = clk_get_rate(sys_clk1_clk) / 6; + freq = ks_clk_get_rate(sys_clk1_clk) / 6; break; case sys_clk1_12_clk: - freq = clk_get_rate(sys_clk1_clk) / 12; + freq = ks_clk_get_rate(sys_clk1_clk) / 12; break; default: break; diff --git a/arch/arm/mach-keystone/cmd_clock.c b/arch/arm/mach-keystone/cmd_clock.c index 3d5cf3f..06afa72 100644 --- a/arch/arm/mach-keystone/cmd_clock.c +++ b/arch/arm/mach-keystone/cmd_clock.c @@ -74,7 +74,7 @@ int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) clk = simple_strtoul(argv[1], NULL, 10); - freq = clk_get_rate(clk); + freq = ks_clk_get_rate(clk); if (freq) printf("clock index [%d] - frequency %lu\n", clk, freq); else diff --git a/arch/arm/mach-keystone/include/mach/clock.h b/arch/arm/mach-keystone/include/mach/clock.h index 72724aa..0d8a944 100644 --- a/arch/arm/mach-keystone/include/mach/clock.h +++ b/arch/arm/mach-keystone/include/mach/clock.h @@ -125,9 +125,7 @@ extern int speeds[]; void init_plls(void); void init_pll(const struct pll_init_data *data); struct pll_init_data *get_pll_init_data(int pll); -unsigned long clk_get_rate(unsigned int clk); -unsigned long clk_round_rate(unsigned int clk, unsigned long hz); -int clk_set_rate(unsigned int clk, unsigned long hz); +unsigned long ks_clk_get_rate(unsigned int clk); int get_max_dev_speed(int *spds); int get_max_arm_speed(int *spds); void pll_pa_clk_sel(void); diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 6d9518d..7713813 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -133,13 +133,17 @@ static int gpio_init(void) return 0; } -int spl_board_load_image(void) +#ifdef CONFIG_SPL_BUILD +static int spl_board_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr); return_to_fel(fel_stash.sp, fel_stash.lr); return 0; } +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image); +#endif void s_init(void) { diff --git a/arch/arm/mach-uniphier/boot-mode/spl_board.c b/arch/arm/mach-uniphier/boot-mode/spl_board.c index 86292b6..854ab05 100644 --- a/arch/arm/mach-uniphier/boot-mode/spl_board.c +++ b/arch/arm/mach-uniphier/boot-mode/spl_board.c @@ -65,7 +65,8 @@ int uniphier_rom_get_mmc_funcptr(int (**send_cmd)(u32, u32), return 0; } -int spl_board_load_image(void) +static int spl_board_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { int (*send_cmd)(u32 cmd, u32 arg); int (*card_blockaddr)(u32 rca); @@ -113,12 +114,12 @@ int spl_board_load_image(void) return ret; } - ret = spl_parse_image_header((void *)CONFIG_SYS_TEXT_BASE); + ret = spl_parse_image_header(spl_image, (void *)CONFIG_SYS_TEXT_BASE); if (ret) return ret; - ret = (*load_image)(dev_addr, spl_image.load_addr, - spl_image.size / 512); + ret = (*load_image)(dev_addr, spl_image->load_addr, + spl_image->size / 512); if (ret) { printf("failed to load image\n"); return ret; @@ -126,3 +127,4 @@ int spl_board_load_image(void) return 0; } +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image); diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h index 3d98a00..de3c979 100644 --- a/arch/blackfin/include/asm/config.h +++ b/arch/blackfin/include/asm/config.h @@ -171,7 +171,6 @@ } #endif -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_ARCH_MISC_INIT #define CONFIG_CPU CONFIG_BFIN_CPU diff --git a/arch/microblaze/cpu/spl.c b/arch/microblaze/cpu/spl.c index f4bb091..8e6d926 100644 --- a/arch/microblaze/cpu/spl.c +++ b/arch/microblaze/cpu/spl.c @@ -29,13 +29,13 @@ void spl_board_init(void) } #ifdef CONFIG_SPL_OS_BOOT -void __noreturn jump_to_image_linux(void *arg) +void __noreturn jump_to_image_linux(struct spl_image_info *spl_image, void *arg) { debug("Entering kernel arg pointer: 0x%p\n", arg); typedef void (*image_entry_arg_t)(char *, ulong, ulong) __attribute__ ((noreturn)); image_entry_arg_t image_entry = - (image_entry_arg_t)spl_image.entry_point; + (image_entry_arg_t)spl_image->entry_point; image_entry(NULL, 0, (ulong)arg); } diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index ef08489..cabf64c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -489,7 +489,7 @@ static void dump_spd_ddr_reg(void) for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) fsl_ddr_get_spd(spd[i], i, CONFIG_DIMM_SLOTS_PER_CTLR); - puts("SPD data of all dimms (zero vaule is omitted)...\n"); + puts("SPD data of all dimms (zero value is omitted)...\n"); puts("Byte (hex) "); k = 1; for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { @@ -543,7 +543,7 @@ static void dump_spd_ddr_reg(void) } } printf("DDR registers dump for all controllers " - "(zero vaule is omitted)...\n"); + "(zero value is omitted)...\n"); puts("Offset (hex) "); for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) printf(" Base + 0x%04x", (u32)ddr[i] & 0xFFFF); diff --git a/arch/powerpc/lib/spl.c b/arch/powerpc/lib/spl.c index 0e486cc..080b978 100644 --- a/arch/powerpc/lib/spl.c +++ b/arch/powerpc/lib/spl.c @@ -17,14 +17,14 @@ DECLARE_GLOBAL_DATA_PTR; * arg: Pointer to paramter image in RAM */ #ifdef CONFIG_SPL_OS_BOOT -void __noreturn jump_to_image_linux(void *arg) +void __noreturn jump_to_image_linux(struct spl_image_info *spl_image, void *arg) { debug("Entering kernel arg pointer: 0x%p\n", arg); typedef void (*image_entry_arg_t)(void *, ulong r4, ulong r5, ulong r6, ulong r7, ulong r8, ulong r9) __attribute__ ((noreturn)); image_entry_arg_t image_entry = - (image_entry_arg_t)spl_image.entry_point; + (image_entry_arg_t)spl_image->entry_point; image_entry(arg, 0, 0, EPAPR_MAGIC, CONFIG_SYS_BOOTMAPSZ, 0, 0); } diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index e8349c0..1ad7fb6 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -38,7 +38,8 @@ void spl_board_announce_boot_device(void) printf("%s\n", fname); } -int spl_board_load_image(void) +static int spl_board_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { char fname[256]; int ret; @@ -50,6 +51,7 @@ int spl_board_load_image(void) /* Hopefully this will not return */ return os_spl_to_uboot(fname); } +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_BOARD, spl_board_load_image); void spl_board_init(void) { diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h index 59f2401..eb3cb56 100644 --- a/arch/sandbox/include/asm/spl.h +++ b/arch/sandbox/include/asm/spl.h @@ -8,14 +8,6 @@ #define CONFIG_SPL_BOARD_LOAD_IMAGE -/** - * Board-specific load method for boards that have a special way of loading - * U-Boot, which does not fit with the existing SPL code. - * - * @return 0 on success, negative errno value on failure. - */ -int spl_board_load_image(void); - enum { BOOT_DEVICE_BOARD, }; diff --git a/board/Arcturus/ucp1020/spl.c b/board/Arcturus/ucp1020/spl.c index 9315bb7..9c19c87 100644 --- a/board/Arcturus/ucp1020/spl.c +++ b/board/Arcturus/ucp1020/spl.c @@ -119,8 +119,6 @@ void board_init_r(gd_t *gd, ulong dest_addr) #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); -#elif defined(CONFIG_SPL_SPI_BOOT) - spi_boot(); #elif defined(CONFIG_SPL_NAND_BOOT) nand_boot(); #endif diff --git a/board/amcc/acadia/Kconfig b/board/amcc/acadia/Kconfig index 7c0ef53..033deaf 100644 --- a/board/amcc/acadia/Kconfig +++ b/board/amcc/acadia/Kconfig @@ -9,8 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "acadia" -config DISPLAY_BOARDINFO - bool - default y - endif diff --git a/board/amcc/bamboo/Kconfig b/board/amcc/bamboo/Kconfig index d44a36a..c0bd40a 100644 --- a/board/amcc/bamboo/Kconfig +++ b/board/amcc/bamboo/Kconfig @@ -9,8 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "bamboo" -config DISPLAY_BOARDINFO - bool - default y - endif diff --git a/board/amcc/bubinga/Kconfig b/board/amcc/bubinga/Kconfig index fc40f6e..540d9b6 100644 --- a/board/amcc/bubinga/Kconfig +++ b/board/amcc/bubinga/Kconfig @@ -9,8 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "bubinga" -config DISPLAY_BOARDINFO - bool - default y - endif diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig index a655dbc..cea6009 100644 --- a/board/amcc/canyonlands/Kconfig +++ b/board/amcc/canyonlands/Kconfig @@ -30,8 +30,4 @@ config ARCHES endchoice -config DISPLAY_BOARDINFO - bool - default y - endif diff --git a/board/amcc/katmai/Kconfig b/board/amcc/katmai/Kconfig index 59d3ef5..fc606cf 100644 --- a/board/amcc/katmai/Kconfig +++ b/board/amcc/katmai/Kconfig @@ -9,8 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "katmai" -config DISPLAY_BOARDINFO - bool - default y - endif diff --git a/board/amcc/kilauea/Kconfig b/board/amcc/kilauea/Kconfig index 5dfd9eb..3f2f434 100644 --- a/board/amcc/kilauea/Kconfig +++ b/board/amcc/kilauea/Kconfig @@ -9,8 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "kilauea" -config DISPLAY_BOARDINFO - bool - default y - endif diff --git a/board/amcc/luan/Kconfig b/board/amcc/luan/Kconfig index 36b44ff..3df90af 100644 --- a/board/amcc/luan/Kconfig +++ b/board/amcc/luan/Kconfig @@ -9,8 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "luan" -config DISPLAY_BOARDINFO - bool - default y - endif diff --git a/board/amcc/makalu/Kconfig b/board/amcc/makalu/Kconfig index 7f8498a..31ce5f1 100644 --- a/board/amcc/makalu/Kconfig +++ b/board/amcc/makalu/Kconfig @@ -9,8 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "makalu" -config DISPLAY_BOARDINFO - bool - default y - endif diff --git a/board/amcc/redwood/Kconfig b/board/amcc/redwood/Kconfig index fee6441..d710590 100644 --- a/board/amcc/redwood/Kconfig +++ b/board/amcc/redwood/Kconfig @@ -9,8 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "redwood" -config DISPLAY_BOARDINFO - bool - default y - endif diff --git a/board/amcc/sequoia/Kconfig b/board/amcc/sequoia/Kconfig index 6e6e408..67ee3ca 100644 --- a/board/amcc/sequoia/Kconfig +++ b/board/amcc/sequoia/Kconfig @@ -9,8 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "sequoia" -config DISPLAY_BOARDINFO - bool - default y - endif diff --git a/board/amcc/walnut/Kconfig b/board/amcc/walnut/Kconfig index d4c451d..94e3dc9 100644 --- a/board/amcc/walnut/Kconfig +++ b/board/amcc/walnut/Kconfig @@ -9,8 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "walnut" -config DISPLAY_BOARDINFO - bool - default y - endif diff --git a/board/amcc/yosemite/Kconfig b/board/amcc/yosemite/Kconfig index ec51236..dfa1068 100644 --- a/board/amcc/yosemite/Kconfig +++ b/board/amcc/yosemite/Kconfig @@ -9,8 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "yosemite" -config DISPLAY_BOARDINFO - bool - default y - endif diff --git a/board/amcc/yucca/Kconfig b/board/amcc/yucca/Kconfig index 338b6a9..61d9589 100644 --- a/board/amcc/yucca/Kconfig +++ b/board/amcc/yucca/Kconfig @@ -9,8 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "yucca" -config DISPLAY_BOARDINFO - bool - default y - endif diff --git a/board/armltd/vexpress/vexpress_tc2.c b/board/armltd/vexpress/vexpress_tc2.c index ebb41a8..c7adf95 100644 --- a/board/armltd/vexpress/vexpress_tc2.c +++ b/board/armltd/vexpress/vexpress_tc2.c @@ -7,7 +7,11 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <asm/armv7.h> #include <asm/io.h> +#include <asm/u-boot.h> +#include <common.h> +#include <libfdt.h> #define SCC_BASE 0x7fff0000 @@ -31,3 +35,51 @@ bool armv7_boot_nonsec_default(void) return (readl((u32 *)(SCC_BASE + 0x700)) & ((1 << 12) | (1 << 13))) == 0; #endif } + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *fdt, bd_t *bd) +{ + int offset, tmp, len; + const struct fdt_property *prop; + const char *cci_compatible = "arm,cci-400-ctrl-if"; + +#ifdef CONFIG_ARMV7_NONSEC + if (!armv7_boot_nonsec()) + return 0; +#else + return 0; +#endif + /* Booting in nonsec mode, disable CCI access */ + offset = fdt_path_offset(fdt, "/cpus"); + if (offset < 0) { + printf("couldn't find /cpus\n"); + return offset; + } + + /* delete cci-control-port in each cpu node */ + for (tmp = fdt_first_subnode(fdt, offset); tmp >= 0; + tmp = fdt_next_subnode(fdt, tmp)) + fdt_delprop(fdt, tmp, "cci-control-port"); + + /* disable all ace cci slave ports */ + offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible", + cci_compatible, 20); + while (offset > 0) { + prop = fdt_get_property(fdt, offset, "interface-type", + &len); + if (!prop) + continue; + if (len < 4) + continue; + if (strcmp(prop->data, "ace")) + continue; + + fdt_setprop_string(fdt, offset, "status", "disabled"); + + offset = fdt_node_offset_by_prop_value(fdt, offset, "compatible", + cci_compatible, 20); + } + + return 0; +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/freescale/common/spl.h b/board/freescale/common/spl.h new file mode 100644 index 0000000..88c987e --- /dev/null +++ b/board/freescale/common/spl.h @@ -0,0 +1,13 @@ +/* + * Copyright 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FREESCALE_BOARD_SPL_H +#define __FREESCALE_BOARD_SPL_H + +void fsl_spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst); +void fsl_spi_boot(void) __noreturn; + +#endif diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 0e9b506..e58c03c 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -682,125 +682,6 @@ int checkboard(void) #include <spl.h> #include <libfdt.h> -const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { - .dram_sdclk_0 = 0x00020030, - .dram_sdclk_1 = 0x00020030, - .dram_cas = 0x00020030, - .dram_ras = 0x00020030, - .dram_reset = 0x00020030, - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x00003030, - .dram_sdodt1 = 0x00003030, - .dram_sdqs0 = 0x00000030, - .dram_sdqs1 = 0x00000030, - .dram_sdqs2 = 0x00000030, - .dram_sdqs3 = 0x00000030, - .dram_sdqs4 = 0x00000030, - .dram_sdqs5 = 0x00000030, - .dram_sdqs6 = 0x00000030, - .dram_sdqs7 = 0x00000030, - .dram_dqm0 = 0x00020030, - .dram_dqm1 = 0x00020030, - .dram_dqm2 = 0x00020030, - .dram_dqm3 = 0x00020030, - .dram_dqm4 = 0x00020030, - .dram_dqm5 = 0x00020030, - .dram_dqm6 = 0x00020030, - .dram_dqm7 = 0x00020030, -}; - -const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = { - .dram_sdclk_0 = 0x00000030, - .dram_sdclk_1 = 0x00000030, - .dram_cas = 0x00000030, - .dram_ras = 0x00000030, - .dram_reset = 0x00000030, - .dram_sdcke0 = 0x00003000, - .dram_sdcke1 = 0x00003000, - .dram_sdba2 = 0x00000000, - .dram_sdodt0 = 0x00003030, - .dram_sdodt1 = 0x00003030, - .dram_sdqs0 = 0x00000030, - .dram_sdqs1 = 0x00000030, - .dram_sdqs2 = 0x00000030, - .dram_sdqs3 = 0x00000030, - .dram_sdqs4 = 0x00000030, - .dram_sdqs5 = 0x00000030, - .dram_sdqs6 = 0x00000030, - .dram_sdqs7 = 0x00000030, - .dram_dqm0 = 0x00000030, - .dram_dqm1 = 0x00000030, - .dram_dqm2 = 0x00000030, - .dram_dqm3 = 0x00000030, - .dram_dqm4 = 0x00000030, - .dram_dqm5 = 0x00000030, - .dram_dqm6 = 0x00000030, - .dram_dqm7 = 0x00000030, -}; - -const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { - .grp_ddr_type = 0x000C0000, - .grp_ddrmode_ctl = 0x00020000, - .grp_ddrpke = 0x00000000, - .grp_addds = 0x00000030, - .grp_ctlds = 0x00000030, - .grp_ddrmode = 0x00020000, - .grp_b0ds = 0x00000030, - .grp_b1ds = 0x00000030, - .grp_b2ds = 0x00000030, - .grp_b3ds = 0x00000030, - .grp_b4ds = 0x00000030, - .grp_b5ds = 0x00000030, - .grp_b6ds = 0x00000030, - .grp_b7ds = 0x00000030, -}; - -const struct mx6_mmdc_calibration mx6_mmcd_calib = { - .p0_mpwldectrl0 = 0x001F001F, - .p0_mpwldectrl1 = 0x001F001F, - .p1_mpwldectrl0 = 0x00440044, - .p1_mpwldectrl1 = 0x00440044, - .p0_mpdgctrl0 = 0x434B0350, - .p0_mpdgctrl1 = 0x034C0359, - .p1_mpdgctrl0 = 0x434B0350, - .p1_mpdgctrl1 = 0x03650348, - .p0_mprddlctl = 0x4436383B, - .p1_mprddlctl = 0x39393341, - .p0_mpwrdlctl = 0x35373933, - .p1_mpwrdlctl = 0x48254A36, -}; - -const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = { - .p0_mpwldectrl0 = 0x001B001E, - .p0_mpwldectrl1 = 0x002E0029, - .p1_mpwldectrl0 = 0x001B002A, - .p1_mpwldectrl1 = 0x0019002C, - .p0_mpdgctrl0 = 0x43240334, - .p0_mpdgctrl1 = 0x0324031A, - .p1_mpdgctrl0 = 0x43340344, - .p1_mpdgctrl1 = 0x03280276, - .p0_mprddlctl = 0x44383A3E, - .p1_mprddlctl = 0x3C3C3846, - .p0_mpwrdlctl = 0x2E303230, - .p1_mpwrdlctl = 0x38283E34, -}; - -/* MT41K128M16JT-125 */ -static struct mx6_ddr3_cfg mem_ddr = { - .mem_speed = 1600, - .density = 2, - .width = 16, - .banks = 8, - .rowaddr = 14, - .coladdr = 10, - .pagesz = 2, - .trcd = 1375, - .trcmin = 4875, - .trasmin = 3500, -}; - static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -831,44 +712,209 @@ static void gpr_init(void) } } -/* - * This section requires the differentiation between iMX6 Sabre boards, but - * for now, it will configure only for the mx6q variant. - */ -static void spl_dram_init(void) +static int mx6q_dcd_table[] = { + 0x020e0798, 0x000C0000, + 0x020e0758, 0x00000000, + 0x020e0588, 0x00000030, + 0x020e0594, 0x00000030, + 0x020e056c, 0x00000030, + 0x020e0578, 0x00000030, + 0x020e074c, 0x00000030, + 0x020e057c, 0x00000030, + 0x020e058c, 0x00000000, + 0x020e059c, 0x00000030, + 0x020e05a0, 0x00000030, + 0x020e078c, 0x00000030, + 0x020e0750, 0x00020000, + 0x020e05a8, 0x00000030, + 0x020e05b0, 0x00000030, + 0x020e0524, 0x00000030, + 0x020e051c, 0x00000030, + 0x020e0518, 0x00000030, + 0x020e050c, 0x00000030, + 0x020e05b8, 0x00000030, + 0x020e05c0, 0x00000030, + 0x020e0774, 0x00020000, + 0x020e0784, 0x00000030, + 0x020e0788, 0x00000030, + 0x020e0794, 0x00000030, + 0x020e079c, 0x00000030, + 0x020e07a0, 0x00000030, + 0x020e07a4, 0x00000030, + 0x020e07a8, 0x00000030, + 0x020e0748, 0x00000030, + 0x020e05ac, 0x00000030, + 0x020e05b4, 0x00000030, + 0x020e0528, 0x00000030, + 0x020e0520, 0x00000030, + 0x020e0514, 0x00000030, + 0x020e0510, 0x00000030, + 0x020e05bc, 0x00000030, + 0x020e05c4, 0x00000030, + 0x021b0800, 0xa1390003, + 0x021b080c, 0x001F001F, + 0x021b0810, 0x001F001F, + 0x021b480c, 0x001F001F, + 0x021b4810, 0x001F001F, + 0x021b083c, 0x43270338, + 0x021b0840, 0x03200314, + 0x021b483c, 0x431A032F, + 0x021b4840, 0x03200263, + 0x021b0848, 0x4B434748, + 0x021b4848, 0x4445404C, + 0x021b0850, 0x38444542, + 0x021b4850, 0x4935493A, + 0x021b081c, 0x33333333, + 0x021b0820, 0x33333333, + 0x021b0824, 0x33333333, + 0x021b0828, 0x33333333, + 0x021b481c, 0x33333333, + 0x021b4820, 0x33333333, + 0x021b4824, 0x33333333, + 0x021b4828, 0x33333333, + 0x021b08b8, 0x00000800, + 0x021b48b8, 0x00000800, + 0x021b0004, 0x00020036, + 0x021b0008, 0x09444040, + 0x021b000c, 0x555A7975, + 0x021b0010, 0xFF538F64, + 0x021b0014, 0x01FF00DB, + 0x021b0018, 0x00001740, + 0x021b001c, 0x00008000, + 0x021b002c, 0x000026d2, + 0x021b0030, 0x005A1023, + 0x021b0040, 0x00000027, + 0x021b0000, 0x831A0000, + 0x021b001c, 0x04088032, + 0x021b001c, 0x00008033, + 0x021b001c, 0x00048031, + 0x021b001c, 0x09408030, + 0x021b001c, 0x04008040, + 0x021b0020, 0x00005800, + 0x021b0818, 0x00011117, + 0x021b4818, 0x00011117, + 0x021b0004, 0x00025576, + 0x021b0404, 0x00011006, + 0x021b001c, 0x00000000, +}; + +static int mx6qp_dcd_table[] = { + 0x020e0798, 0x000c0000, + 0x020e0758, 0x00000000, + 0x020e0588, 0x00000030, + 0x020e0594, 0x00000030, + 0x020e056c, 0x00000030, + 0x020e0578, 0x00000030, + 0x020e074c, 0x00000030, + 0x020e057c, 0x00000030, + 0x020e058c, 0x00000000, + 0x020e059c, 0x00000030, + 0x020e05a0, 0x00000030, + 0x020e078c, 0x00000030, + 0x020e0750, 0x00020000, + 0x020e05a8, 0x00000030, + 0x020e05b0, 0x00000030, + 0x020e0524, 0x00000030, + 0x020e051c, 0x00000030, + 0x020e0518, 0x00000030, + 0x020e050c, 0x00000030, + 0x020e05b8, 0x00000030, + 0x020e05c0, 0x00000030, + 0x020e0774, 0x00020000, + 0x020e0784, 0x00000030, + 0x020e0788, 0x00000030, + 0x020e0794, 0x00000030, + 0x020e079c, 0x00000030, + 0x020e07a0, 0x00000030, + 0x020e07a4, 0x00000030, + 0x020e07a8, 0x00000030, + 0x020e0748, 0x00000030, + 0x020e05ac, 0x00000030, + 0x020e05b4, 0x00000030, + 0x020e0528, 0x00000030, + 0x020e0520, 0x00000030, + 0x020e0514, 0x00000030, + 0x020e0510, 0x00000030, + 0x020e05bc, 0x00000030, + 0x020e05c4, 0x00000030, + 0x021b0800, 0xa1390003, + 0x021b080c, 0x001b001e, + 0x021b0810, 0x002e0029, + 0x021b480c, 0x001b002a, + 0x021b4810, 0x0019002c, + 0x021b083c, 0x43240334, + 0x021b0840, 0x0324031a, + 0x021b483c, 0x43340344, + 0x021b4840, 0x03280276, + 0x021b0848, 0x44383A3E, + 0x021b4848, 0x3C3C3846, + 0x021b0850, 0x2e303230, + 0x021b4850, 0x38283E34, + 0x021b081c, 0x33333333, + 0x021b0820, 0x33333333, + 0x021b0824, 0x33333333, + 0x021b0828, 0x33333333, + 0x021b481c, 0x33333333, + 0x021b4820, 0x33333333, + 0x021b4824, 0x33333333, + 0x021b4828, 0x33333333, + 0x021b08c0, 0x24912249, + 0x021b48c0, 0x24914289, + 0x021b08b8, 0x00000800, + 0x021b48b8, 0x00000800, + 0x021b0004, 0x00020036, + 0x021b0008, 0x24444040, + 0x021b000c, 0x555A7955, + 0x021b0010, 0xFF320F64, + 0x021b0014, 0x01ff00db, + 0x021b0018, 0x00001740, + 0x021b001c, 0x00008000, + 0x021b002c, 0x000026d2, + 0x021b0030, 0x005A1023, + 0x021b0040, 0x00000027, + 0x021b0400, 0x14420000, + 0x021b0000, 0x831A0000, + 0x021b0890, 0x00400C58, + 0x00bb0008, 0x00000000, + 0x00bb000c, 0x2891E41A, + 0x00bb0038, 0x00000564, + 0x00bb0014, 0x00000040, + 0x00bb0028, 0x00000020, + 0x00bb002c, 0x00000020, + 0x021b001c, 0x04088032, + 0x021b001c, 0x00008033, + 0x021b001c, 0x00048031, + 0x021b001c, 0x09408030, + 0x021b001c, 0x04008040, + 0x021b0020, 0x00005800, + 0x021b0818, 0x00011117, + 0x021b4818, 0x00011117, + 0x021b0004, 0x00025576, + 0x021b0404, 0x00011006, + 0x021b001c, 0x00000000, +}; + +static void ddr_init(int *table, int size) { - struct mx6_ddr_sysinfo sysinfo = { - /* width of data bus:0=16,1=32,2=64 */ - .dsize = 2, - /* config for full 4GB range so that get_mem_size() works */ - .cs_density = 32, /* 32Gb per CS */ - /* single chip select */ - .ncs = 1, - .cs1_mirror = 0, - .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ - .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ - .walat = 1, /* Write additional latency */ - .ralat = 5, /* Read additional latency */ - .mif3_mode = 3, /* Command prediction working mode */ - .bi_on = 1, /* Bank interleaving enabled */ - .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ - .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ - .ddr_type = DDR_TYPE_DDR3, - .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ - }; + int i; - if (is_mx6dqp()) { - mx6dq_dram_iocfg(64, &mx6dqp_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6dqp_mmcd_calib, &mem_ddr); - } else { - mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); - mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); - } + for (i = 0; i < size / 2 ; i++) + writel(table[2 * i + 1], table[2 * i]); +} + +static void spl_dram_init(void) +{ + if (is_mx6dq()) + ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table)); + else if (is_mx6dqp()) + ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table)); } void board_init_f(ulong dummy) { + /* DDR initialization */ + spl_dram_init(); + /* setup AIPS and disable watchdog */ arch_cpu_init(); @@ -884,9 +930,6 @@ void board_init_f(ulong dummy) /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); - /* DDR initialization */ - spl_dram_init(); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); diff --git a/board/freescale/mx6ullevk/Kconfig b/board/freescale/mx6ullevk/Kconfig new file mode 100644 index 0000000..7eec497 --- /dev/null +++ b/board/freescale/mx6ullevk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6ULL_14X14_EVK + +config SYS_BOARD + default "mx6ullevk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6ullevk" + +endif diff --git a/board/freescale/mx6ullevk/MAINTAINERS b/board/freescale/mx6ullevk/MAINTAINERS new file mode 100644 index 0000000..4137674 --- /dev/null +++ b/board/freescale/mx6ullevk/MAINTAINERS @@ -0,0 +1,6 @@ +MX6ULLEVK BOARD +M: Peng Fan <peng.fan@nxp.com> +S: Maintained +F: board/freescale/mx6ullevk/ +F: include/configs/mx6ullevk.h +F: configs/mx6ull_14x14_evk_defconfig diff --git a/board/freescale/mx6ullevk/Makefile b/board/freescale/mx6ullevk/Makefile new file mode 100644 index 0000000..c64fba4 --- /dev/null +++ b/board/freescale/mx6ullevk/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6ullevk.o diff --git a/board/freescale/mx6ullevk/imximage.cfg b/board/freescale/mx6ullevk/imximage.cfg new file mode 100644 index 0000000..4604b62 --- /dev/null +++ b/board/freescale/mx6ullevk/imximage.cfg @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ullevk/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x000C0030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000004 +DATA 4 0x021B083C 0x41640158 +DATA 4 0x021B0848 0x40403237 +DATA 4 0x021B0850 0x40403C33 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00944009 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 + +#endif diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c new file mode 100644 index 0000000..489bf21 --- /dev/null +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/io.h> +#include <common.h> +#include <fsl_esdhc.h> +#include <linux/sizes.h> +#include <mmc.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int mmc_map_to_kernel_blk(int devno) +{ + return devno; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + setenv("board_name", "EVK"); + setenv("board_rev", "14X14"); +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: MX6ULL 14x14 EVK\n"); + + return 0; +} diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index f858408..9844194 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -12,6 +12,7 @@ #include <i2c.h> #include <fsl_esdhc.h> #include <spi_flash.h> +#include "../common/spl.h" DECLARE_GLOBAL_DATA_PTR; @@ -103,7 +104,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); #elif defined(CONFIG_SPL_SPI_BOOT) - spi_boot(); + fsl_spi_boot(); #elif defined(CONFIG_SPL_NAND_BOOT) nand_boot(); #endif diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c index 04db767..6a5fe74 100644 --- a/board/freescale/p1022ds/spl.c +++ b/board/freescale/p1022ds/spl.c @@ -14,6 +14,7 @@ #include "../common/ngpixis.h" #include <fsl_esdhc.h> #include <spi_flash.h> +#include "../common/spl.h" DECLARE_GLOBAL_DATA_PTR; @@ -120,7 +121,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); #elif defined(CONFIG_SPL_SPI_BOOT) - spi_boot(); + fsl_spi_boot(); #elif defined(CONFIG_SPL_NAND_BOOT) nand_boot(); #endif diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 76a3cf4..9e8f359 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -13,6 +13,7 @@ #include <i2c.h> #include <fsl_esdhc.h> #include <spi_flash.h> +#include "../common/spl.h" DECLARE_GLOBAL_DATA_PTR; @@ -117,7 +118,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); #elif defined(CONFIG_SPL_SPI_BOOT) - spi_boot(); + fsl_spi_boot(); #elif defined(CONFIG_SPL_NAND_BOOT) nand_boot(); #endif diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c index d59d343..61bfb29 100644 --- a/board/freescale/t102xqds/spl.c +++ b/board/freescale/t102xqds/spl.c @@ -14,6 +14,7 @@ #include <spi_flash.h> #include "../common/qixis.h" #include "t102xqds_qixis.h" +#include "../common/spl.h" DECLARE_GLOBAL_DATA_PTR; @@ -132,8 +133,8 @@ void board_init_r(gd_t *gd, ulong dest_addr) (uchar *)CONFIG_ENV_ADDR); #endif #ifdef CONFIG_SPL_SPI_BOOT - spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_ENV_ADDR); + fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); #endif gd->env_addr = (ulong)(CONFIG_ENV_ADDR); @@ -146,7 +147,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); #elif defined(CONFIG_SPL_SPI_BOOT) - spi_boot(); + fsl_spi_boot(); #elif defined(CONFIG_SPL_NAND_BOOT) nand_boot(); #endif diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index bd3cbbf..6d8866e 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -13,6 +13,7 @@ #include <fsl_esdhc.h> #include <spi_flash.h> #include "../common/sleep.h" +#include "../common/spl.h" DECLARE_GLOBAL_DATA_PTR; @@ -119,8 +120,8 @@ void board_init_r(gd_t *gd, ulong dest_addr) (uchar *)CONFIG_ENV_ADDR); #endif #ifdef CONFIG_SPL_SPI_BOOT - spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_ENV_ADDR); + fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); #endif gd->env_addr = (ulong)(CONFIG_ENV_ADDR); @@ -133,7 +134,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); #elif defined(CONFIG_SPL_SPI_BOOT) - spi_boot(); + fsl_spi_boot(); #elif defined(CONFIG_SPL_NAND_BOOT) nand_boot(); #endif diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index 4b35af6..1c2023b 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -13,6 +13,7 @@ #include <fsl_esdhc.h> #include <spi_flash.h> #include "../common/sleep.h" +#include "../common/spl.h" DECLARE_GLOBAL_DATA_PTR; @@ -114,8 +115,8 @@ void board_init_r(gd_t *gd, ulong dest_addr) (uchar *)CONFIG_ENV_ADDR); #endif #ifdef CONFIG_SPL_SPI_BOOT - spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_ENV_ADDR); + fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); #endif gd->env_addr = (ulong)(CONFIG_ENV_ADDR); gd->env_valid = 1; @@ -129,7 +130,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); #elif defined(CONFIG_SPL_SPI_BOOT) - spi_boot(); + fsl_spi_boot(); #elif defined(CONFIG_SPL_NAND_BOOT) nand_boot(); #endif diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c index bb02dab..b1e1cf1 100644 --- a/board/freescale/t208xqds/spl.c +++ b/board/freescale/t208xqds/spl.c @@ -14,6 +14,7 @@ #include <spi_flash.h> #include "../common/qixis.h" #include "t208xqds_qixis.h" +#include "../common/spl.h" DECLARE_GLOBAL_DATA_PTR; @@ -118,8 +119,8 @@ void board_init_r(gd_t *gd, ulong dest_addr) (uchar *)CONFIG_ENV_ADDR); #endif #ifdef CONFIG_SPL_SPI_BOOT - spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_ENV_ADDR); + fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); #endif gd->env_addr = (ulong)(CONFIG_ENV_ADDR); @@ -132,7 +133,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); #elif defined(CONFIG_SPL_SPI_BOOT) - spi_boot(); + fsl_spi_boot(); #elif defined(CONFIG_SPL_NAND_BOOT) nand_boot(); #endif diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c index 2ff05a2..bb23865 100644 --- a/board/freescale/t208xrdb/spl.c +++ b/board/freescale/t208xrdb/spl.c @@ -12,6 +12,7 @@ #include <mmc.h> #include <fsl_esdhc.h> #include <spi_flash.h> +#include "../common/spl.h" DECLARE_GLOBAL_DATA_PTR; @@ -88,8 +89,8 @@ void board_init_r(gd_t *gd, ulong dest_addr) (uchar *)CONFIG_ENV_ADDR); #endif #ifdef CONFIG_SPL_SPI_BOOT - spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, - (uchar *)CONFIG_ENV_ADDR); + fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, + (uchar *)CONFIG_ENV_ADDR); #endif gd->env_addr = (ulong)(CONFIG_ENV_ADDR); @@ -102,7 +103,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); #elif defined(CONFIG_SPL_SPI_BOOT) - spi_boot(); + fsl_spi_boot(); #elif defined(CONFIG_SPL_NAND_BOOT) nand_boot(); #endif diff --git a/board/liebherr/lwmon5/Kconfig b/board/liebherr/lwmon5/Kconfig index 7f1bb40..ec8349d 100644 --- a/board/liebherr/lwmon5/Kconfig +++ b/board/liebherr/lwmon5/Kconfig @@ -9,8 +9,4 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "lwmon5" -config DISPLAY_BOARDINFO - bool - default y - endif diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig index d67a69a..212f994 100644 --- a/board/phytec/pcm052/Kconfig +++ b/board/phytec/pcm052/Kconfig @@ -12,4 +12,28 @@ config SYS_SOC config SYS_CONFIG_NAME default "pcm052" +config PCM052_DDR_SIZE + int + default 256 + +endif + +if TARGET_BK4R1 + +config SYS_BOARD + default "pcm052" + +config SYS_VENDOR + default "phytec" + +config SYS_SOC + default "vf610" + +config SYS_CONFIG_NAME + default "bk4r1" + +config PCM052_DDR_SIZE + int + default 512 + endif diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index e4f61e1..e75ff4f 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -152,57 +152,6 @@ static struct ddrmc_phy_setting pcm052_phy_settings[] = { int dram_init(void) { - static const struct ddr3_jedec_timings pcm052_ddr_timings = { - .tinit = 5, - .trst_pwron = 80000, - .cke_inactive = 200000, - .wrlat = 5, - .caslat_lin = 12, - .trc = 6, - .trrd = 4, - .tccd = 4, - .tbst_int_interval = 4, - .tfaw = 18, - .trp = 6, - .twtr = 4, - .tras_min = 15, - .tmrd = 4, - .trtp = 4, - .tras_max = 14040, - .tmod = 12, - .tckesr = 4, - .tcke = 3, - .trcd_int = 6, - .tras_lockout = 1, - .tdal = 10, - .bstlen = 3, - .tdll = 512, - .trp_ab = 6, - .tref = 1542, - .trfc = 64, - .tref_int = 5, - .tpdex = 3, - .txpdll = 10, - .txsnr = 68, - .txsr = 506, - .cksrx = 5, - .cksre = 5, - .freq_chg_en = 1, - .zqcl = 256, - .zqinit = 512, - .zqcs = 64, - .ref_per_zq = 64, - .zqcs_rotate = 1, - .aprebit = 10, - .cmd_age_cnt = 255, - .age_cnt = 255, - .q_fullness = 0, - .odt_rd_mapcs0 = 1, - .odt_wr_mapcs0 = 1, - .wlmrd = 40, - .wldqsen = 25, - }; - static const iomux_v3_cfg_t pcm052_pads[] = { PCM052_VF610_PAD_DDR_A15__DDR_A_15, PCM052_VF610_PAD_DDR_A14__DDR_A_14, @@ -256,11 +205,126 @@ int dram_init(void) PCM052_VF610_PAD_DDR_RESETB, }; - imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); +#if defined(CONFIG_TARGET_PCM052) + + static const struct ddr3_jedec_timings pcm052_ddr_timings = { + .tinit = 5, + .trst_pwron = 80000, + .cke_inactive = 200000, + .wrlat = 5, + .caslat_lin = 12, + .trc = 6, + .trrd = 4, + .tccd = 4, + .tbst_int_interval = 4, + .tfaw = 18, + .trp = 6, + .twtr = 4, + .tras_min = 15, + .tmrd = 4, + .trtp = 4, + .tras_max = 14040, + .tmod = 12, + .tckesr = 4, + .tcke = 3, + .trcd_int = 6, + .tras_lockout = 1, + .tdal = 10, + .bstlen = 3, + .tdll = 512, + .trp_ab = 6, + .tref = 1542, + .trfc = 64, + .tref_int = 5, + .tpdex = 3, + .txpdll = 10, + .txsnr = 68, + .txsr = 506, + .cksrx = 5, + .cksre = 5, + .freq_chg_en = 1, + .zqcl = 256, + .zqinit = 512, + .zqcs = 64, + .ref_per_zq = 64, + .zqcs_rotate = 1, + .aprebit = 10, + .cmd_age_cnt = 255, + .age_cnt = 255, + .q_fullness = 0, + .odt_rd_mapcs0 = 1, + .odt_wr_mapcs0 = 1, + .wlmrd = 40, + .wldqsen = 25, + }; ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, pcm052_phy_settings, 1, 2); +#elif defined(CONFIG_TARGET_BK4R1) + + static const struct ddr3_jedec_timings pcm052_ddr_timings = { + .tinit = 5, + .trst_pwron = 80000, + .cke_inactive = 200000, + .wrlat = 5, + .caslat_lin = 12, + .trc = 6, + .trrd = 4, + .tccd = 4, + .tbst_int_interval = 0, + .tfaw = 16, + .trp = 6, + .twtr = 4, + .tras_min = 15, + .tmrd = 4, + .trtp = 4, + .tras_max = 28080, + .tmod = 12, + .tckesr = 4, + .tcke = 3, + .trcd_int = 6, + .tras_lockout = 1, + .tdal = 12, + .bstlen = 3, + .tdll = 512, + .trp_ab = 6, + .tref = 3120, + .trfc = 104, + .tref_int = 0, + .tpdex = 3, + .txpdll = 10, + .txsnr = 108, + .txsr = 512, + .cksrx = 5, + .cksre = 5, + .freq_chg_en = 1, + .zqcl = 256, + .zqinit = 512, + .zqcs = 64, + .ref_per_zq = 64, + .zqcs_rotate = 1, + .aprebit = 10, + .cmd_age_cnt = 255, + .age_cnt = 255, + .q_fullness = 0, + .odt_rd_mapcs0 = 1, + .odt_wr_mapcs0 = 1, + .wlmrd = 40, + .wldqsen = 25, + }; + + ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, + pcm052_phy_settings, 1, 1); + +#else /* Unknown PCM052 variant */ + +#error DDR characteristics undefined for this target. Please define them. + +#endif + + imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; @@ -513,3 +577,41 @@ int checkboard(void) return 0; } + +static int do_m4go(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + ulong addr; + + /* Consume 'm4go' */ + argc--; argv++; + + /* + * Parse provided address - default to load_addr in case not provided. + */ + + if (argc) + addr = simple_strtoul(argv[0], NULL, 16); + else + addr = load_addr; + + /* + * Write boot address in PERSISTENT_ENTRY1[31:0] aka SRC_GPR2[31:0] + */ + writel(addr + 0x401, 0x4006E028); + + /* + * Start secondary processor by enabling its clock + */ + writel(0x15a5a, 0x4006B08C); + + return 1; +} + +U_BOOT_CMD( + m4go, 2 /* one arg max */, 1 /* repeatable */, do_m4go, + "start the secondary Cortex-M4 from scatter file image", + "[<addr>]\n" + " - start secondary Cortex-M4 core using a scatter file image\n" + "The argument needs to be a scatter file\n" +); diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index 48d207f..4a3d094 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -140,7 +140,7 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_SPL_OS_BOOT /* - * Do board specific preperation before SPL + * Do board specific preparation before SPL * Linux boot */ void spl_board_prepare_for_linux(void) diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 99e8254..3c16846 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -36,10 +36,10 @@ #define board_is_dra74x_evm() board_ti_is("5777xCPU") #define board_is_dra72x_evm() board_ti_is("DRA72x-T") -#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \ - (strncmp("H", board_ti_get_rev(), 1) <= 0) -#define board_is_dra72x_revc_or_later() board_is_dra72x_evm() && \ - (strncmp("C", board_ti_get_rev(), 1) <= 0) +#define board_is_dra74x_revh_or_later() (board_is_dra74x_evm() && \ + (strncmp("H", board_ti_get_rev(), 1) <= 0)) +#define board_is_dra72x_revc_or_later() (board_is_dra72x_evm() && \ + (strncmp("C", board_ti_get_rev(), 1) <= 0)) #define board_ti_get_emif_size() board_ti_get_emif1_size() + \ board_ti_get_emif2_size() @@ -828,12 +828,18 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { - if (is_dra72x() && !strcmp(name, "dra72-evm")) - return 0; - else if (!is_dra72x() && !strcmp(name, "dra7-evm")) + if (is_dra72x()) { + if (board_is_dra72x_revc_or_later()) { + if (!strcmp(name, "dra72-evm-revc")) + return 0; + } else if (!strcmp(name, "dra72-evm")) { + return 0; + } + } else if (!is_dra72x() && !strcmp(name, "dra7-evm")) { return 0; - else - return -1; + } + + return -1; } #endif diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 965252f..f785dbe 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -157,7 +157,7 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_SPL_OS_BOOT /* - * Do board specific preperation before SPL + * Do board specific preparation before SPL * Linux boot */ void spl_board_prepare_for_linux(void) diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index 8eedd65..c64e31e 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -12,17 +12,17 @@ #include <asm/gpio.h> #include <asm/imx-common/boot_mode.h> #include <asm/imx-common/iomux-v3.h> -#include <asm/imx-common/mxc_i2c.h> #include <asm/io.h> #include <common.h> #include <dm.h> #include <dm/platform_data/serial_mxc.h> #include <fsl_esdhc.h> -#include <i2c.h> #include <linux/sizes.h> #include <mmc.h> #include <miiphy.h> #include <netdev.h> +#include <power/pmic.h> +#include <power/rn5t567_pmic.h> #include <usb/ehci-ci.h> DECLARE_GLOBAL_DATA_PTR; @@ -38,9 +38,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) -#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ - PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) - #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ PAD_CTL_DSE_3P3V_49OHM) @@ -48,36 +45,6 @@ DECLARE_GLOBAL_DATA_PTR; #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) -#ifdef CONFIG_SYS_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 for PMIC */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX7D_PAD_GPIO1_IO04__I2C1_SCL | PC, - .gpio_mode = MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | PC, - .gp = IMX_GPIO_NR(1, 4), - }, - .sda = { - .i2c_mode = MX7D_PAD_GPIO1_IO05__I2C1_SDA | PC, - .gpio_mode = MX7D_PAD_GPIO1_IO05__GPIO1_IO5 | PC, - .gp = IMX_GPIO_NR(1, 5), - }, -}; -/* I2C4 for Colibri I2C */ -static struct i2c_pads_info i2c_pad_info4 = { - .scl = { - .i2c_mode = MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL | PC, - .gpio_mode = MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 | PC, - .gp = IMX_GPIO_NR(7, 8), - }, - .sda = { - .i2c_mode = MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA | PC, - .gpio_mode = MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 | PC, - .gp = IMX_GPIO_NR(7, 9), - }, -}; -#endif - int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -331,11 +298,6 @@ int board_early_init_f(void) { setup_iomux_uart(); -#ifdef CONFIG_SYS_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); -#endif - return 0; } @@ -377,6 +339,46 @@ int board_late_init(void) return 0; } +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int reg, ver; + int ret; + + + ret = pmic_get("rn5t567", &dev); + if (ret) + return ret; + ver = pmic_reg_read(dev, RN5T567_LSIVER); + reg = pmic_reg_read(dev, RN5T567_OTPVER); + + printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg); + + /* set judge and press timer of N_OE to minimal values */ + pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0); + + return 0; +} + +void reset_cpu(ulong addr) +{ + struct udevice *dev; + + pmic_get("rn5t567", &dev); + + /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */ + pmic_reg_write(dev, RN5T567_REPCNT, 0x1); + pmic_reg_write(dev, RN5T567_SLPCNT, 0x1); + + /* + * Re-power factor detection on PMIC side is not instant. 1ms + * proved to be enough time until reset takes effect. + */ + mdelay(1); +} +#endif + int checkboard(void) { printf("Model: Toradex Colibri iMX7%c\n", @@ -408,13 +410,3 @@ int board_ehci_hcd_init(int port) return 0; } #endif - -static struct mxc_serial_platdata mxc_serial_plat = { - .reg = (struct mxc_uart *)UART1_IPS_BASE_ADDR, - .use_dte = true, -}; - -U_BOOT_DEVICE(mxc_serial) = { - .name = "serial_mxc", - .platdata = &mxc_serial_plat, -}; diff --git a/board/udoo/README b/board/udoo/README new file mode 100644 index 0000000..6fbcc59 --- /dev/null +++ b/board/udoo/README @@ -0,0 +1,21 @@ +How to use U-Boot on MX6Q/DL Udoo boards +---------------------------------------- + +- Build U-Boot for MX6Q/DL Udoo boards: + +$ make mrproper +$ make udoo_defconfig +$ make + +This will generate the SPL image called SPL and the u-boot.img. + +- Flash the SPL image into the SD card: + +sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + +- Flash the u-boot.img image into the SD card: + +sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Insert the SD card in the board, power it up and U-Boot messages should +come up. diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c index c513b22..a21a3d0 100644 --- a/board/wandboard/spl.c +++ b/board/wandboard/spl.c @@ -188,7 +188,7 @@ static struct mx6_ddr_sysinfo mem_q = { .rst_to_cke = 0x23, .sde_to_rst = 0x10, .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ + .refr = 3, /* 4 refresh commands per refresh cycle */ }; static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = { @@ -231,7 +231,7 @@ static struct mx6_ddr_sysinfo mem_dl = { .rst_to_cke = 0x23, .sde_to_rst = 0x10, .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ + .refr = 3, /* 4 refresh commands per refresh cycle */ }; /* DDR 32bit 512MB */ @@ -250,7 +250,7 @@ static struct mx6_ddr_sysinfo mem_s = { .rst_to_cke = 0x23, .sde_to_rst = 0x10, .refsel = 1, /* Refresh cycles at 32KHz */ - .refr = 7, /* 8 refresh commands per refresh cycle */ + .refr = 3, /* 4 refresh commands per refresh cycle */ }; static void ccgr_init(void) diff --git a/cmd/nvedit.c b/cmd/nvedit.c index b67563b..9ca5cb5 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -15,7 +15,7 @@ * * The "environment" is stored on external storage as a list of '\0' * terminated "name=value" strings. The end of the list is marked by - * a double '\0'. The environment is preceeded by a 32 bit CRC over + * a double '\0'. The environment is preceded by a 32 bit CRC over * the data part and, in case of redundant environment, a byte of * flags. * @@ -838,7 +838,7 @@ static int do_env_delete(cmd_tbl_t *cmdtp, int flag, * With "-c" and size is NOT given, then the export command will * format the data as currently used for the persistent storage, * i. e. it will use CONFIG_ENV_SECT_SIZE as output block size and - * prepend a valid CRC32 checksum and, in case of resundant + * prepend a valid CRC32 checksum and, in case of redundant * environment, a "current" redundancy flag. If size is given, this * value will be used instead of CONFIG_ENV_SECT_SIZE; again, CRC32 * checksum and redundancy flag will be inserted. @@ -847,12 +847,12 @@ static int do_env_delete(cmd_tbl_t *cmdtp, int flag, * terminating '\0' byte) will be written; here the optional size * argument will be used to make sure not to overflow the user * provided buffer; the command will abort if the size is not - * sufficient. Any remainign space will be '\0' padded. + * sufficient. Any remaining space will be '\0' padded. * * On successful return, the variable "filesize" will be set. * Note that filesize includes the trailing/terminating '\0' byte(s). * - * Usage szenario: create a text snapshot/backup of the current settings: + * Usage scenario: create a text snapshot/backup of the current settings: * * => env export -t 100000 * => era ${backup_addr} +${filesize} @@ -970,7 +970,7 @@ sep_err: /* * env import [-d] [-t [-r] | -b | -c] addr [size] * -d: delete existing environment before importing; - * otherwise overwrite / append to existion definitions + * otherwise overwrite / append to existing definitions * -t: assume text format; either "size" must be given or the * text data must be '\0' terminated * -r: handle CRLF like LF, that means exported variables with diff --git a/cmd/onenand.c b/cmd/onenand.c index feab01a..d97844f 100644 --- a/cmd/onenand.c +++ b/cmd/onenand.c @@ -139,6 +139,12 @@ static int onenand_block_write(loff_t to, size_t len, size_t _retlen = 0; int ret; + if ((to & (mtd->writesize - 1)) != 0) { + printf("Attempt to write non block-aligned data\n"); + *retlen = 0; + return 1; + } + if (to == next_ofs) { next_ofs = to + len; to += skip_ofs; diff --git a/common/Kconfig b/common/Kconfig index c69c141..1198f26 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -219,4 +219,20 @@ config VERSION_VARIABLE Any change to this variable will be reverted at the next reset. +config DISPLAY_CPUINFO + bool "Display information about the CPU during start up" + default y if ARM || BLACKFIN || NIOS2 || X86 || XTENSA + help + Display information about the CPU that U-Boot is running on + when U-Boot starts up. The function print_cpuinfo() is called + to do this. + +config DISPLAY_BOARDINFO + bool "Display information about the board during start up" + default y if ARM || M68K || MIPS || PPC || SPARC || XTENSA + help + Display information about the board that U-Boot is running on + when U-Boot starts up. The board function checkboard() is called + to do this. + source "common/spl/Kconfig" diff --git a/common/board_f.c b/common/board_f.c index 2c88595..1b88822 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -1058,7 +1058,7 @@ void board_init_f(ulong boot_flags) { #ifdef CONFIG_SYS_GENERIC_GLOBAL_DATA /* - * For some archtectures, global data is initialized and used before + * For some architectures, global data is initialized and used before * calling this function. The data should be preserved. For others, * CONFIG_SYS_GENERIC_GLOBAL_DATA should be defined and use the stack * here to host global data until relocation. @@ -1070,7 +1070,7 @@ void board_init_f(ulong boot_flags) /* * Clear global data before it is accessed at debug print * in initcall_run_list. Otherwise the debug print probably - * get the wrong vaule of gd->have_console. + * get the wrong value of gd->have_console. */ zero_global_data(); #endif diff --git a/common/console.c b/common/console.c index 12293f3..c7f3243 100644 --- a/common/console.c +++ b/common/console.c @@ -687,15 +687,22 @@ int console_assign(int file, const char *devname) return -1; } -/* Called before relocation - use serial functions */ -int console_init_f(void) +static void console_update_silent(void) { - gd->have_console = 1; - #ifdef CONFIG_SILENT_CONSOLE if (getenv("silent") != NULL) gd->flags |= GD_FLG_SILENT; + else + gd->flags &= ~GD_FLG_SILENT; #endif +} + +/* Called before relocation - use serial functions */ +int console_init_f(void) +{ + gd->have_console = 1; + + console_update_silent(); print_pre_console_buffer(PRE_CONSOLE_FLUSHPOINT1_SERIAL); @@ -831,6 +838,8 @@ int console_init_r(void) struct list_head *pos; struct stdio_dev *dev; + console_update_silent(); + #ifdef CONFIG_SPLASH_SCREEN /* * suppress all output if splash screen is enabled and we have diff --git a/common/env_common.c b/common/env_common.c index 560cad0..7fb62e8 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -226,7 +226,7 @@ int env_import(const char *buf, int check) return 0; } -/* Emport the environment and generate CRC for it. */ +/* Export the environment and generate CRC for it. */ int env_export(env_t *env_out) { char *res; diff --git a/common/image.c b/common/image.c index a5d19ab..c0ad36a 100644 --- a/common/image.c +++ b/common/image.c @@ -161,6 +161,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_RKIMAGE, "rkimage", "Rockchip Boot Image" }, { IH_TYPE_RKSD, "rksd", "Rockchip SD Boot Image" }, { IH_TYPE_RKSPI, "rkspi", "Rockchip SPI Boot Image" }, + { IH_TYPE_VYBRIDIMAGE, "vybridimage", "Vybrid Boot Image", }, { IH_TYPE_ZYNQIMAGE, "zynqimage", "Xilinx Zynq Boot Image" }, { IH_TYPE_ZYNQMPIMAGE, "zynqmpimage", "Xilinx ZynqMP Boot Image" }, { IH_TYPE_FPGA, "fpga", "FPGA Image" }, diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 2a8ddbc..72aacab 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -61,6 +61,15 @@ config SPL_SEPARATE_BSS location is used. Normally we put the device tree at the end of BSS but with this option enabled, it goes at _image_binary_end. +config SPL_DISPLAY_PRINT + depends on SPL + bool "Display a board-specific message in SPL" + help + If this option is enabled, U-Boot will call the function + spl_display_print() immediately after displaying the SPL console + banner ("U-Boot SPL ..."). This function should be provided by + the board. + config TPL bool depends on SPL && SUPPORT_TPL @@ -163,6 +172,19 @@ config SPL_ENV_SUPPORT starting U-Boot first. Enabling this option will make getenv() and setenv() available in SPL. +config SPL_SAVEENV + bool "Support save environment" + depends on SPL && SPL_ENV_SUPPORT + help + Enable save environment support in SPL after setenv. By default + the saveenv option is not provided in SPL, but some boards need + this support in 'Falcon' boot, where SPL need to boot from + different images based on environment variable set by OS. For + example OS may set "reboot_image" environment variable to + "recovery" inorder to boot recovery image by SPL. The SPL read + "reboot_image" and act accordingly and change the reboot_image + to default mode using setenv and save the environemnt. + config SPL_ETH_SUPPORT bool "Support Ethernet" depends on SPL_ENV_SUPPORT diff --git a/common/spl/Makefile b/common/spl/Makefile index 5bd0b18..ed02635 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -25,4 +25,5 @@ obj-$(CONFIG_SPL_FAT_SUPPORT) += spl_fat.o obj-$(CONFIG_SPL_EXT_SUPPORT) += spl_ext.o obj-$(CONFIG_SPL_SATA_SUPPORT) += spl_sata.o obj-$(CONFIG_SPL_DFU_SUPPORT) += spl_dfu.o +obj-$(CONFIG_SPL_SPI_LOAD) += spl_spi.o endif diff --git a/common/spl/spl.c b/common/spl/spl.c index 57b73af..bdb165a 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -29,7 +29,6 @@ DECLARE_GLOBAL_DATA_PTR; #endif u32 *boot_params_ptr = NULL; -struct spl_image_info spl_image; /* Define board data structure */ static bd_t bdata __attribute__ ((section(".data"))); @@ -82,42 +81,43 @@ __weak void spl_board_prepare_for_boot(void) /* Nothing to do! */ } -void spl_set_header_raw_uboot(void) +void spl_set_header_raw_uboot(struct spl_image_info *spl_image) { - spl_image.size = CONFIG_SYS_MONITOR_LEN; - spl_image.entry_point = CONFIG_SYS_UBOOT_START; - spl_image.load_addr = CONFIG_SYS_TEXT_BASE; - spl_image.os = IH_OS_U_BOOT; - spl_image.name = "U-Boot"; + spl_image->size = CONFIG_SYS_MONITOR_LEN; + spl_image->entry_point = CONFIG_SYS_UBOOT_START; + spl_image->load_addr = CONFIG_SYS_TEXT_BASE; + spl_image->os = IH_OS_U_BOOT; + spl_image->name = "U-Boot"; } -int spl_parse_image_header(const struct image_header *header) +int spl_parse_image_header(struct spl_image_info *spl_image, + const struct image_header *header) { u32 header_size = sizeof(struct image_header); if (image_get_magic(header) == IH_MAGIC) { - if (spl_image.flags & SPL_COPY_PAYLOAD_ONLY) { + if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY) { /* * On some system (e.g. powerpc), the load-address and * entry-point is located at address 0. We can't load * to 0-0x40. So skip header in this case. */ - spl_image.load_addr = image_get_load(header); - spl_image.entry_point = image_get_ep(header); - spl_image.size = image_get_data_size(header); + spl_image->load_addr = image_get_load(header); + spl_image->entry_point = image_get_ep(header); + spl_image->size = image_get_data_size(header); } else { - spl_image.entry_point = image_get_load(header); + spl_image->entry_point = image_get_load(header); /* Load including the header */ - spl_image.load_addr = spl_image.entry_point - + spl_image->load_addr = spl_image->entry_point - header_size; - spl_image.size = image_get_data_size(header) + + spl_image->size = image_get_data_size(header) + header_size; } - spl_image.os = image_get_os(header); - spl_image.name = image_get_name(header); + spl_image->os = image_get_os(header); + spl_image->name = image_get_name(header); debug("spl: payload image: %.*s load addr: 0x%x size: %d\n", - (int)sizeof(spl_image.name), spl_image.name, - spl_image.load_addr, spl_image.size); + (int)sizeof(spl_image->name), spl_image->name, + spl_image->load_addr, spl_image->size); } else { #ifdef CONFIG_SPL_PANIC_ON_RAW_IMAGE /* @@ -135,13 +135,13 @@ int spl_parse_image_header(const struct image_header *header) ulong start, end; if (!bootz_setup((ulong)header, &start, &end)) { - spl_image.name = "Linux"; - spl_image.os = IH_OS_LINUX; - spl_image.load_addr = CONFIG_SYS_LOAD_ADDR; - spl_image.entry_point = CONFIG_SYS_LOAD_ADDR; - spl_image.size = end - start; + spl_image->name = "Linux"; + spl_image->os = IH_OS_LINUX; + spl_image->load_addr = CONFIG_SYS_LOAD_ADDR; + spl_image->entry_point = CONFIG_SYS_LOAD_ADDR; + spl_image->size = end - start; debug("spl: payload zImage, load addr: 0x%x size: %d\n", - spl_image.load_addr, spl_image.size); + spl_image->load_addr, spl_image->size); return 0; } #endif @@ -153,7 +153,7 @@ int spl_parse_image_header(const struct image_header *header) /* Signature not found - assume u-boot.bin */ debug("mkimage signature not found - ih_magic = %x\n", header->ih_magic); - spl_set_header_raw_uboot(); + spl_set_header_raw_uboot(spl_image); #endif } return 0; @@ -184,12 +184,18 @@ static ulong spl_ram_load_read(struct spl_load_info *load, ulong sector, return count; } -static int spl_ram_load_image(void) +static int spl_ram_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { struct image_header *header; header = (struct image_header *)CONFIG_SPL_LOAD_FIT_ADDRESS; +#if defined(CONFIG_SPL_DFU_SUPPORT) + if (bootdev->boot_device == BOOT_DEVICE_DFU) + spl_dfu_cmd(0, "dfu_alt_info_ram", "ram", "0"); +#endif + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && image_get_magic(header) == FDT_MAGIC) { struct spl_load_info load; @@ -197,7 +203,7 @@ static int spl_ram_load_image(void) debug("Found FIT\n"); load.bl_len = 1; load.read = spl_ram_load_read; - spl_load_simple_fit(&load, 0, header); + spl_load_simple_fit(spl_image, &load, 0, header); } else { debug("Legacy image\n"); /* @@ -209,11 +215,15 @@ static int spl_ram_load_image(void) header = (struct image_header *) (CONFIG_SYS_TEXT_BASE - sizeof(struct image_header)); - spl_parse_image_header(header); + spl_parse_image_header(spl_image, header); } return 0; } +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_RAM, spl_ram_load_image); +#if defined(CONFIG_SPL_DFU_SUPPORT) +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_DFU, spl_ram_load_image); +#endif #endif int spl_init(void) @@ -252,14 +262,6 @@ int spl_init(void) #define BOOT_DEVICE_NONE 0xdeadbeef #endif -static u32 spl_boot_list[] = { - BOOT_DEVICE_NONE, - BOOT_DEVICE_NONE, - BOOT_DEVICE_NONE, - BOOT_DEVICE_NONE, - BOOT_DEVICE_NONE, -}; - __weak void board_boot_order(u32 *spl_boot_list) { spl_boot_list[0] = spl_boot_device(); @@ -346,86 +348,49 @@ static void announce_boot_device(u32 boot_device) static inline void announce_boot_device(u32 boot_device) { } #endif -static int spl_load_image(u32 boot_device) +static struct spl_image_loader *spl_ll_find_loader(uint boot_device) { - switch (boot_device) { -#ifdef CONFIG_SPL_RAM_DEVICE - case BOOT_DEVICE_RAM: - return spl_ram_load_image(); -#endif -#ifdef CONFIG_SPL_MMC_SUPPORT - case BOOT_DEVICE_MMC1: - case BOOT_DEVICE_MMC2: - case BOOT_DEVICE_MMC2_2: - return spl_mmc_load_image(boot_device); -#endif -#ifdef CONFIG_SPL_UBI - case BOOT_DEVICE_NAND: - case BOOT_DEVICE_ONENAND: - return spl_ubi_load_image(boot_device); -#else -#ifdef CONFIG_SPL_NAND_SUPPORT - case BOOT_DEVICE_NAND: - return spl_nand_load_image(); -#endif -#ifdef CONFIG_SPL_ONENAND_SUPPORT - case BOOT_DEVICE_ONENAND: - return spl_onenand_load_image(); -#endif -#endif -#ifdef CONFIG_SPL_NOR_SUPPORT - case BOOT_DEVICE_NOR: - return spl_nor_load_image(); -#endif -#ifdef CONFIG_SPL_YMODEM_SUPPORT - case BOOT_DEVICE_UART: - return spl_ymodem_load_image(); -#endif -#if defined(CONFIG_SPL_SPI_SUPPORT) || defined(CONFIG_SPL_SPI_FLASH_SUPPORT) - case BOOT_DEVICE_SPI: - return spl_spi_load_image(); -#endif -#ifdef CONFIG_SPL_ETH_SUPPORT - case BOOT_DEVICE_CPGMAC: -#ifdef CONFIG_SPL_ETH_DEVICE - return spl_net_load_image(CONFIG_SPL_ETH_DEVICE); -#else - return spl_net_load_image(NULL); -#endif -#endif -#ifdef CONFIG_SPL_USBETH_SUPPORT - case BOOT_DEVICE_USBETH: - return spl_net_load_image("usb_ether"); -#endif -#ifdef CONFIG_SPL_USB_SUPPORT - case BOOT_DEVICE_USB: - return spl_usb_load_image(); -#endif -#ifdef CONFIG_SPL_DFU_SUPPORT - case BOOT_DEVICE_DFU: - spl_dfu_cmd(0, "dfu_alt_info_ram", "ram", "0"); - return spl_ram_load_image(); -#endif -#ifdef CONFIG_SPL_SATA_SUPPORT - case BOOT_DEVICE_SATA: - return spl_sata_load_image(); -#endif -#ifdef CONFIG_SPL_BOARD_LOAD_IMAGE - case BOOT_DEVICE_BOARD: - return spl_board_load_image(); -#endif - default: -#if defined(CONFIG_SPL_SERIAL_SUPPORT) && defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - puts("SPL: Unsupported Boot Device!\n"); -#endif - return -ENODEV; + struct spl_image_loader *drv = + ll_entry_start(struct spl_image_loader, spl_image_loader); + const int n_ents = + ll_entry_count(struct spl_image_loader, spl_image_loader); + struct spl_image_loader *entry; + + for (entry = drv; entry != drv + n_ents; entry++) { + if (boot_device == entry->boot_device) + return entry; } - return -EINVAL; + /* Not found */ + return NULL; +} + +static int spl_load_image(struct spl_image_info *spl_image, u32 boot_device) +{ + struct spl_boot_device bootdev; + struct spl_image_loader *loader = spl_ll_find_loader(boot_device); + + bootdev.boot_device = boot_device; + bootdev.boot_device_name = NULL; + if (loader) + return loader->load_image(spl_image, &bootdev); + +#if defined(CONFIG_SPL_SERIAL_SUPPORT) && defined(CONFIG_SPL_LIBCOMMON_SUPPORT) + puts("SPL: Unsupported Boot Device!\n"); +#endif + return -ENODEV; } void board_init_r(gd_t *dummy1, ulong dummy2) { + u32 spl_boot_list[] = { + BOOT_DEVICE_NONE, + BOOT_DEVICE_NONE, + BOOT_DEVICE_NONE, + BOOT_DEVICE_NONE, + BOOT_DEVICE_NONE, + }; + struct spl_image_info spl_image; int i; debug(">>spl:board_init_r()\n"); @@ -451,11 +416,12 @@ void board_init_r(gd_t *dummy1, ulong dummy2) spl_board_init(); #endif + memset(&spl_image, '\0', sizeof(spl_image)); board_boot_order(spl_boot_list); for (i = 0; i < ARRAY_SIZE(spl_boot_list) && spl_boot_list[i] != BOOT_DEVICE_NONE; i++) { announce_boot_device(spl_boot_list[i]); - if (!spl_load_image(spl_boot_list[i])) + if (!spl_load_image(&spl_image, spl_boot_list[i])) break; } @@ -473,7 +439,8 @@ void board_init_r(gd_t *dummy1, ulong dummy2) case IH_OS_LINUX: debug("Jumping to Linux\n"); spl_board_prepare_for_linux(); - jump_to_image_linux((void *)CONFIG_SYS_SPL_ARGS_ADDR); + jump_to_image_linux(&spl_image, + (void *)CONFIG_SYS_SPL_ARGS_ADDR); #endif default: debug("Unsupported OS image.. Jumping nevertheless..\n"); diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c index a85dc85..b93e1ea 100644 --- a/common/spl/spl_ext.c +++ b/common/spl/spl_ext.c @@ -10,9 +10,9 @@ #include <image.h> #ifdef CONFIG_SPL_EXT_SUPPORT -int spl_load_image_ext(struct blk_desc *block_dev, - int partition, - const char *filename) +int spl_load_image_ext(struct spl_image_info *spl_image, + struct blk_desc *block_dev, int partition, + const char *filename) { s32 err; struct image_header *header; @@ -48,13 +48,13 @@ int spl_load_image_ext(struct blk_desc *block_dev, goto end; } - err = spl_parse_image_header(header); + err = spl_parse_image_header(spl_image, header); if (err < 0) { puts("spl: ext: failed to parse image header\n"); goto end; } - err = ext4fs_read((char *)spl_image.load_addr, filelen, &actlen); + err = ext4fs_read((char *)spl_image->load_addr, filelen, &actlen); end: #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT @@ -67,7 +67,8 @@ end: } #ifdef CONFIG_SPL_OS_BOOT -int spl_load_image_ext_os(struct blk_desc *block_dev, int partition) +int spl_load_image_ext_os(struct spl_image_info *spl_image, + struct blk_desc *block_dev, int partition) { int err; __maybe_unused loff_t filelen, actlen; @@ -104,7 +105,8 @@ int spl_load_image_ext_os(struct blk_desc *block_dev, int partition) } file = getenv("falcon_image_file"); if (file) { - err = spl_load_image_ext(block_dev, partition, file); + err = spl_load_image_ext(spl_image, block_dev, + partition, file); if (err != 0) { puts("spl: falling back to default\n"); goto defaults; @@ -134,11 +136,12 @@ defaults: return -1; } - return spl_load_image_ext(block_dev, partition, + return spl_load_image_ext(spl_image, block_dev, partition, CONFIG_SPL_FS_LOAD_KERNEL_NAME); } #else -int spl_load_image_ext_os(struct blk_desc *block_dev, int partition) +int spl_load_image_ext_os(struct spl_image_info *spl_image, + struct blk_desc *block_dev, int partition) { return -ENOSYS; } diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c index 73d33f5..a14acce 100644 --- a/common/spl/spl_fat.c +++ b/common/spl/spl_fat.c @@ -54,9 +54,9 @@ static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset, return actread; } -int spl_load_image_fat(struct blk_desc *block_dev, - int partition, - const char *filename) +int spl_load_image_fat(struct spl_image_info *spl_image, + struct blk_desc *block_dev, int partition, + const char *filename) { int err; struct image_header *header; @@ -82,14 +82,14 @@ int spl_load_image_fat(struct blk_desc *block_dev, load.filename = (void *)filename; load.priv = NULL; - return spl_load_simple_fit(&load, 0, header); + return spl_load_simple_fit(spl_image, &load, 0, header); } else { - err = spl_parse_image_header(header); + err = spl_parse_image_header(spl_image, header); if (err) goto end; err = file_fat_read(filename, - (u8 *)(uintptr_t)spl_image.load_addr, 0); + (u8 *)(uintptr_t)spl_image->load_addr, 0); } end: @@ -103,7 +103,8 @@ end: } #ifdef CONFIG_SPL_OS_BOOT -int spl_load_image_fat_os(struct blk_desc *block_dev, int partition) +int spl_load_image_fat_os(struct spl_image_info *spl_image, + struct blk_desc *block_dev, int partition) { int err; __maybe_unused char *file; @@ -123,7 +124,8 @@ int spl_load_image_fat_os(struct blk_desc *block_dev, int partition) } file = getenv("falcon_image_file"); if (file) { - err = spl_load_image_fat(block_dev, partition, file); + err = spl_load_image_fat(spl_image, block_dev, + partition, file); if (err != 0) { puts("spl: falling back to default\n"); goto defaults; @@ -148,11 +150,12 @@ defaults: return -1; } - return spl_load_image_fat(block_dev, partition, + return spl_load_image_fat(spl_image, block_dev, partition, CONFIG_SPL_FS_LOAD_KERNEL_NAME); } #else -int spl_load_image_fat_os(struct blk_desc *block_dev, int partition) +int spl_load_image_fat_os(struct spl_image_info *spl_image, + struct blk_desc *block_dev, int partition) { return -ENOSYS; } diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index be86072..aae556f 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -123,7 +123,8 @@ static int get_aligned_image_size(struct spl_load_info *info, int data_size, return (data_size + info->bl_len - 1) / info->bl_len; } -int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit) +int spl_load_simple_fit(struct spl_image_info *spl_image, + struct spl_load_info *info, ulong sector, void *fit) { int sectors; ulong size, load; @@ -184,9 +185,9 @@ int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fit) data_size = fdt_getprop_u32(fit, node, "data-size"); load = fdt_getprop_u32(fit, node, "load"); debug("data_offset=%x, data_size=%x\n", data_offset, data_size); - spl_image.load_addr = load; - spl_image.entry_point = load; - spl_image.os = IH_OS_U_BOOT; + spl_image->load_addr = load; + spl_image->entry_point = load; + spl_image->os = IH_OS_U_BOOT; /* * Work out where to place the image. We read it so that the first diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 7c7f329..c674e61 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -18,26 +18,26 @@ DECLARE_GLOBAL_DATA_PTR; -static int mmc_load_legacy(struct mmc *mmc, ulong sector, - struct image_header *header) +static int mmc_load_legacy(struct spl_image_info *spl_image, struct mmc *mmc, + ulong sector, struct image_header *header) { u32 image_size_sectors; unsigned long count; int ret; - ret = spl_parse_image_header(header); + ret = spl_parse_image_header(spl_image, header); if (ret) return ret; /* convert size to sectors - round up */ - image_size_sectors = (spl_image.size + mmc->read_bl_len - 1) / + image_size_sectors = (spl_image->size + mmc->read_bl_len - 1) / mmc->read_bl_len; /* Read the header too to avoid extra memcpy */ count = blk_dread(mmc_get_blk_desc(mmc), sector, image_size_sectors, - (void *)(ulong)spl_image.load_addr); + (void *)(ulong)spl_image->load_addr); debug("read %x sectors to %x\n", image_size_sectors, - spl_image.load_addr); + spl_image->load_addr); if (count != image_size_sectors) return -EIO; @@ -52,7 +52,8 @@ static ulong h_spl_load_read(struct spl_load_info *load, ulong sector, return blk_dread(mmc_get_blk_desc(mmc), sector, count, buf); } -static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector) +static int mmc_load_image_raw_sector(struct spl_image_info *spl_image, + struct mmc *mmc, unsigned long sector) { unsigned long count; struct image_header *header; @@ -79,9 +80,9 @@ static int mmc_load_image_raw_sector(struct mmc *mmc, unsigned long sector) load.filename = NULL; load.bl_len = mmc->read_bl_len; load.read = h_spl_load_read; - ret = spl_load_simple_fit(&load, sector, header); + ret = spl_load_simple_fit(spl_image, &load, sector, header); } else { - ret = mmc_load_legacy(mmc, sector, header); + ret = mmc_load_legacy(spl_image, mmc, sector, header); } end: @@ -150,7 +151,8 @@ static int spl_mmc_find_device(struct mmc **mmcp, u32 boot_device) } #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION -static int mmc_load_image_raw_partition(struct mmc *mmc, int partition) +static int mmc_load_image_raw_partition(struct spl_image_info *spl_image, + struct mmc *mmc, int partition) { disk_partition_t info; int err; @@ -164,22 +166,24 @@ static int mmc_load_image_raw_partition(struct mmc *mmc, int partition) } #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - return mmc_load_image_raw_sector(mmc, info.start + - CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); + return mmc_load_image_raw_sector(spl_image, mmc, + info.start + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); #else - return mmc_load_image_raw_sector(mmc, info.start); + return mmc_load_image_raw_sector(spl_image, mmc, info.start); #endif } #else #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION -1 -static int mmc_load_image_raw_partition(struct mmc *mmc, int partition) +static int mmc_load_image_raw_partition(struct spl_image_info *spl_image, + struct mmc *mmc, int partition) { return -ENOSYS; } #endif #ifdef CONFIG_SPL_OS_BOOT -static int mmc_load_image_raw_os(struct mmc *mmc) +static int mmc_load_image_raw_os(struct spl_image_info *spl_image, + struct mmc *mmc) { unsigned long count; int ret; @@ -195,12 +199,12 @@ static int mmc_load_image_raw_os(struct mmc *mmc) return -1; } - ret = mmc_load_image_raw_sector(mmc, + ret = mmc_load_image_raw_sector(spl_image, mmc, CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR); if (ret) return ret; - if (spl_image.os != IH_OS_LINUX) { + if (spl_image->os != IH_OS_LINUX) { puts("Expected Linux image is not found. Trying to start U-boot\n"); return -ENOENT; } @@ -212,26 +216,27 @@ int spl_start_uboot(void) { return 1; } -static int mmc_load_image_raw_os(struct mmc *mmc) +static int mmc_load_image_raw_os(struct spl_image_info *spl_image, + struct mmc *mmc) { return -ENOSYS; } #endif #ifdef CONFIG_SYS_MMCSD_FS_BOOT_PARTITION -int spl_mmc_do_fs_boot(struct mmc *mmc) +static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, struct mmc *mmc) { int err = -ENOSYS; #ifdef CONFIG_SPL_FAT_SUPPORT if (!spl_start_uboot()) { - err = spl_load_image_fat_os(mmc_get_blk_desc(mmc), + err = spl_load_image_fat_os(spl_image, mmc_get_blk_desc(mmc), CONFIG_SYS_MMCSD_FS_BOOT_PARTITION); if (!err) return err; } #ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME - err = spl_load_image_fat(mmc_get_blk_desc(mmc), + err = spl_load_image_fat(spl_image, mmc_get_blk_desc(mmc), CONFIG_SYS_MMCSD_FS_BOOT_PARTITION, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); if (!err) @@ -240,13 +245,13 @@ int spl_mmc_do_fs_boot(struct mmc *mmc) #endif #ifdef CONFIG_SPL_EXT_SUPPORT if (!spl_start_uboot()) { - err = spl_load_image_ext_os(&mmc->block_dev, + err = spl_load_image_ext_os(spl_image, &mmc->block_dev, CONFIG_SYS_MMCSD_FS_BOOT_PARTITION); if (!err) return err; } #ifdef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME - err = spl_load_image_ext(&mmc->block_dev, + err = spl_load_image_ext(spl_image, &mmc->block_dev, CONFIG_SYS_MMCSD_FS_BOOT_PARTITION, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); if (!err) @@ -261,20 +266,21 @@ int spl_mmc_do_fs_boot(struct mmc *mmc) return err; } #else -int spl_mmc_do_fs_boot(struct mmc *mmc) +static int spl_mmc_do_fs_boot(struct spl_image_info *spl_image, struct mmc *mmc) { return -ENOSYS; } #endif -int spl_mmc_load_image(u32 boot_device) +static int spl_mmc_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { struct mmc *mmc = NULL; u32 boot_mode; int err = 0; __maybe_unused int part; - err = spl_mmc_find_device(&mmc, boot_device); + err = spl_mmc_find_device(&mmc, bootdev->boot_device); if (err) return err; @@ -286,7 +292,7 @@ int spl_mmc_load_image(u32 boot_device) return err; } - boot_mode = spl_boot_mode(boot_device); + boot_mode = spl_boot_mode(bootdev->boot_device); err = -EINVAL; switch (boot_mode) { case MMCSD_MODE_EMMCBOOT: @@ -312,17 +318,17 @@ int spl_mmc_load_image(u32 boot_device) debug("spl: mmc boot mode: raw\n"); if (!spl_start_uboot()) { - err = mmc_load_image_raw_os(mmc); + err = mmc_load_image_raw_os(spl_image, mmc); if (!err) return err; } - err = mmc_load_image_raw_partition(mmc, + err = mmc_load_image_raw_partition(spl_image, mmc, CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION); if (!err) return err; #if defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR) - err = mmc_load_image_raw_sector(mmc, + err = mmc_load_image_raw_sector(spl_image, mmc, CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR); if (!err) return err; @@ -331,7 +337,7 @@ int spl_mmc_load_image(u32 boot_device) case MMCSD_MODE_FS: debug("spl: mmc boot mode: fs\n"); - err = spl_mmc_do_fs_boot(mmc); + err = spl_mmc_do_fs_boot(spl_image, mmc); if (!err) return err; @@ -345,3 +351,7 @@ int spl_mmc_load_image(u32 boot_device) return err; } + +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_MMC1, spl_mmc_load_image); +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_MMC2, spl_mmc_load_image); +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_MMC2_2, spl_mmc_load_image); diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 0e35e0f..d1abda6 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -13,14 +13,15 @@ #include <fdt.h> #if defined(CONFIG_SPL_NAND_RAW_ONLY) -int spl_nand_load_image(void) +int spl_nand_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { nand_init(); nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, (void *)CONFIG_SYS_NAND_U_BOOT_DST); - spl_set_header_raw_uboot(); + spl_set_header_raw_uboot(spl_image); nand_deselect(); return 0; @@ -39,7 +40,8 @@ static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs, return 0; } -static int spl_nand_load_element(int offset, struct image_header *header) +static int spl_nand_load_element(struct spl_image_info *spl_image, + int offset, struct image_header *header) { int err; @@ -57,17 +59,18 @@ static int spl_nand_load_element(int offset, struct image_header *header) load.filename = NULL; load.bl_len = 1; load.read = spl_nand_fit_read; - return spl_load_simple_fit(&load, offset, header); + return spl_load_simple_fit(spl_image, &load, offset, header); } else { - err = spl_parse_image_header(header); + err = spl_parse_image_header(spl_image, header); if (err) return err; - return nand_spl_load_image(offset, spl_image.size, - (void *)(ulong)spl_image.load_addr); + return nand_spl_load_image(offset, spl_image->size, + (void *)(ulong)spl_image->load_addr); } } -int spl_nand_load_image(void) +static int spl_nand_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { int err; struct image_header *header; @@ -107,15 +110,15 @@ int spl_nand_load_image(void) /* load linux */ nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS, sizeof(*header), (void *)header); - err = spl_parse_image_header(header); + err = spl_parse_image_header(spl_image, header); if (err) return err; if (header->ih_os == IH_OS_LINUX) { /* happy - was a linux */ err = nand_spl_load_image( CONFIG_SYS_NAND_SPL_KERNEL_OFFS, - spl_image.size, - (void *)spl_image.load_addr); + spl_image->size, + (void *)spl_image->load_addr); nand_deselect(); return err; } else { @@ -127,17 +130,19 @@ int spl_nand_load_image(void) } #endif #ifdef CONFIG_NAND_ENV_DST - spl_nand_load_element(CONFIG_ENV_OFFSET, header); + spl_nand_load_element(spl_image, CONFIG_ENV_OFFSET, header); #ifdef CONFIG_ENV_OFFSET_REDUND - spl_nand_load_element(CONFIG_ENV_OFFSET_REDUND, header); + spl_nand_load_element(spl_image, CONFIG_ENV_OFFSET_REDUND, header); #endif #endif /* Load u-boot */ - err = spl_nand_load_element(CONFIG_SYS_NAND_U_BOOT_OFFS, header); + err = spl_nand_load_element(spl_image, CONFIG_SYS_NAND_U_BOOT_OFFS, + header); #ifdef CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND #if CONFIG_SYS_NAND_U_BOOT_OFFS != CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND if (err) - err = spl_nand_load_element(CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND, + err = spl_nand_load_element(spl_image, + CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND, header); #endif #endif @@ -145,3 +150,5 @@ int spl_nand_load_image(void) return err; } #endif +/* Use priorty 1 so that Ubi can override this */ +SPL_LOAD_IMAGE_METHOD(1, BOOT_DEVICE_NAND, spl_nand_load_image); diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c index ae71d26..f4b4bc4 100644 --- a/common/spl/spl_net.c +++ b/common/spl/spl_net.c @@ -14,7 +14,9 @@ DECLARE_GLOBAL_DATA_PTR; -int spl_net_load_image(const char *device) +#if defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT) +static int spl_net_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { int rv; @@ -27,12 +29,38 @@ int spl_net_load_image(const char *device) printf("No Ethernet devices found\n"); return -ENODEV; } - if (device) - setenv("ethact", device); + if (bootdev->boot_device_name) + setenv("ethact", bootdev->boot_device_name); rv = net_loop(BOOTP); if (rv < 0) { printf("Problem booting with BOOTP\n"); return rv; } - return spl_parse_image_header((struct image_header *)load_addr); + return spl_parse_image_header(spl_image, + (struct image_header *)load_addr); } +#endif + +#ifdef CONFIG_SPL_ETH_SUPPORT +int spl_net_load_image_cpgmac(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ +#ifdef CONFIG_SPL_ETH_DEVICE + bootdev->boot_device_name = CONFIG_SPL_ETH_DEVICE; +#endif + + return spl_net_load_image(spl_image, bootdev); +} +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_CPGMAC, spl_net_load_image_cpgmac); +#endif + +#ifdef CONFIG_SPL_USBETH_SUPPORT +int spl_net_load_image_usb(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + bootdev->boot_device_name = "usb_ether"; + + return spl_net_load_image(spl_image, bootdev); +} +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_USBETH, spl_net_load_image_usb); +#endif diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index 8ea874c..6bfa399 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -7,14 +7,15 @@ #include <common.h> #include <spl.h> -int spl_nor_load_image(void) +static int spl_nor_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { int ret; /* * Loading of the payload to SDRAM is done with skipping of * the mkimage header in this SPL NOR driver */ - spl_image.flags |= SPL_COPY_PAYLOAD_ONLY; + spl_image->flags |= SPL_COPY_PAYLOAD_ONLY; #ifdef CONFIG_SPL_OS_BOOT if (!spl_start_uboot()) { @@ -29,14 +30,14 @@ int spl_nor_load_image(void) if (image_get_os(header) == IH_OS_LINUX) { /* happy - was a Linux */ - ret = spl_parse_image_header(header); + ret = spl_parse_image_header(spl_image, header); if (ret) return ret; - memcpy((void *)spl_image.load_addr, + memcpy((void *)spl_image->load_addr, (void *)(CONFIG_SYS_OS_BASE + sizeof(struct image_header)), - spl_image.size); + spl_image->size); /* * Copy DT blob (fdt) to SDRAM. Passing pointer to @@ -59,14 +60,15 @@ int spl_nor_load_image(void) * Load real U-Boot from its location in NOR flash to its * defined location in SDRAM */ - ret = spl_parse_image_header( + ret = spl_parse_image_header(spl_image, (const struct image_header *)CONFIG_SYS_UBOOT_BASE); if (ret) return ret; - memcpy((void *)(unsigned long)spl_image.load_addr, + memcpy((void *)(unsigned long)spl_image->load_addr, (void *)(CONFIG_SYS_UBOOT_BASE + sizeof(struct image_header)), - spl_image.size); + spl_image->size); return 0; } +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_NOR, spl_nor_load_image); diff --git a/common/spl/spl_onenand.c b/common/spl/spl_onenand.c index 1a28a84..f076e2c 100644 --- a/common/spl/spl_onenand.c +++ b/common/spl/spl_onenand.c @@ -14,7 +14,8 @@ #include <asm/io.h> #include <onenand_uboot.h> -int spl_onenand_load_image(void) +static int spl_onenand_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { struct image_header *header; int ret; @@ -26,11 +27,13 @@ int spl_onenand_load_image(void) /* Load u-boot */ onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS, CONFIG_SYS_ONENAND_PAGE_SIZE, (void *)header); - ret = spl_parse_image_header(header); + ret = spl_parse_image_header(spl_image, header); if (ret) return ret; onenand_spl_load_image(CONFIG_SYS_ONENAND_U_BOOT_OFFS, - spl_image.size, (void *)spl_image.load_addr); + spl_image->size, (void *)spl_image->load_addr); return 0; } +/* Use priorty 1 so that Ubi can override this */ +SPL_LOAD_IMAGE_METHOD(1, BOOT_DEVICE_ONENAND, spl_onenand_load_image); diff --git a/common/spl/spl_sata.c b/common/spl/spl_sata.c index 9d8cc7c..a3c07cd 100644 --- a/common/spl/spl_sata.c +++ b/common/spl/spl_sata.c @@ -20,7 +20,8 @@ DECLARE_GLOBAL_DATA_PTR; -int spl_sata_load_image(void) +static int spl_sata_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { int err; struct blk_desc *stor_dev; @@ -40,12 +41,15 @@ int spl_sata_load_image(void) } #ifdef CONFIG_SPL_OS_BOOT - if (spl_start_uboot() || spl_load_image_fat_os(stor_dev, - CONFIG_SYS_SATA_FAT_BOOT_PARTITION)) + if (spl_start_uboot() || + spl_load_image_fat_os(spl_image, stor_dev, + CONFIG_SYS_SATA_FAT_BOOT_PARTITION)) #endif - err = spl_load_image_fat(stor_dev, - CONFIG_SYS_SATA_FAT_BOOT_PARTITION, + { + err = spl_load_image_fat(spl_image, stor_dev, + CONFIG_SYS_SATA_FAT_BOOT_PARTITION, CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); + } if (err) { puts("Error loading sata device\n"); return err; @@ -53,3 +57,4 @@ int spl_sata_load_image(void) return 0; } +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_SATA, spl_sata_load_image); diff --git a/drivers/mtd/spi/spi_spl_load.c b/common/spl/spl_spi.c index bac1e85..a3caafb 100644 --- a/drivers/mtd/spi/spi_spl_load.c +++ b/common/spl/spl_spi.c @@ -20,7 +20,8 @@ * Load the kernel, check for a valid header we can parse, and if found load * the kernel and then device tree. */ -static int spi_load_image_os(struct spi_flash *flash, +static int spi_load_image_os(struct spl_image_info *spl_image, + struct spi_flash *flash, struct image_header *header) { int err; @@ -32,12 +33,12 @@ static int spi_load_image_os(struct spi_flash *flash, if (image_get_magic(header) != IH_MAGIC) return -1; - err = spl_parse_image_header(header); + err = spl_parse_image_header(spl_image, header); if (err) return err; spi_flash_read(flash, CONFIG_SYS_SPI_KERNEL_OFFS, - spl_image.size, (void *)spl_image.load_addr); + spl_image->size, (void *)spl_image->load_addr); /* Read device tree. */ spi_flash_read(flash, CONFIG_SYS_SPI_ARGS_OFFS, @@ -65,7 +66,8 @@ static ulong spl_spi_fit_read(struct spl_load_info *load, ulong sector, * configured and available since this code loads the main U-Boot image * from SPI into SDRAM and starts it from there. */ -int spl_spi_load_image(void) +static int spl_spi_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { int err = 0; struct spi_flash *flash; @@ -88,7 +90,7 @@ int spl_spi_load_image(void) header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); #ifdef CONFIG_SPL_OS_BOOT - if (spl_start_uboot() || spi_load_image_os(flash, header)) + if (spl_start_uboot() || spi_load_image_os(spl_image, flash, header)) #endif { /* Load u-boot, mkimage header is 64 bytes. */ @@ -106,18 +108,20 @@ int spl_spi_load_image(void) load.filename = NULL; load.bl_len = 1; load.read = spl_spi_fit_read; - err = spl_load_simple_fit(&load, + err = spl_load_simple_fit(spl_image, &load, CONFIG_SYS_SPI_U_BOOT_OFFS, header); } else { - err = spl_parse_image_header(header); + err = spl_parse_image_header(spl_image, header); if (err) return err; err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, - spl_image.size, - (void *)spl_image.load_addr); + spl_image->size, + (void *)spl_image->load_addr); } } return err; } +/* Use priorty 1 so that boards can override this */ +SPL_LOAD_IMAGE_METHOD(1, BOOT_DEVICE_SPI, spl_spi_load_image); diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c index f97e1ef..c03910b 100644 --- a/common/spl/spl_ubi.c +++ b/common/spl/spl_ubi.c @@ -12,14 +12,15 @@ #include <ubispl.h> #include <spl.h> -int spl_ubi_load_image(u32 boot_device) +int spl_ubi_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { struct image_header *header; struct ubispl_info info; struct ubispl_load volumes[2]; int ret = 1; - switch (boot_device) { + switch (bootdev->boot_device) { #ifdef CONFIG_SPL_NAND_SUPPORT case BOOT_DEVICE_NAND: nand_init(); @@ -54,7 +55,7 @@ int spl_ubi_load_image(u32 boot_device) ret = ubispl_load_volumes(&info, volumes, 2); if (!ret) { header = (struct image_header *)volumes[0].load_addr; - spl_parse_image_header(header); + spl_parse_image_header(spl_image, header); puts("Linux loaded.\n"); goto out; } @@ -68,11 +69,14 @@ int spl_ubi_load_image(u32 boot_device) ret = ubispl_load_volumes(&info, volumes, 1); if (!ret) - spl_parse_image_header(header); + spl_parse_image_header(spl_image, header); out: #ifdef CONFIG_SPL_NAND_SUPPORT - if (boot_device == BOOT_DEVICE_NAND) + if (bootdev->boot_device == BOOT_DEVICE_NAND) nand_deselect(); #endif return ret; } +/* Use priorty 0 so that Ubi will override NAND and ONENAND methods */ +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_NAND, spl_ubi_load_image); +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_ONENAND, spl_ubi_load_image); diff --git a/common/spl/spl_usb.c b/common/spl/spl_usb.c index 04fa667..e37966e 100644 --- a/common/spl/spl_usb.c +++ b/common/spl/spl_usb.c @@ -22,7 +22,8 @@ DECLARE_GLOBAL_DATA_PTR; static int usb_stor_curr_dev = -1; /* current device */ #endif -int spl_usb_load_image(void) +static int spl_usb_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { int err; struct blk_desc *stor_dev; @@ -47,12 +48,15 @@ int spl_usb_load_image(void) debug("boot mode - FAT\n"); #ifdef CONFIG_SPL_OS_BOOT - if (spl_start_uboot() || spl_load_image_fat_os(stor_dev, - CONFIG_SYS_USB_FAT_BOOT_PARTITION)) + if (spl_start_uboot() || + spl_load_image_fat_os(spl_image, stor_dev, + CONFIG_SYS_USB_FAT_BOOT_PARTITION)) #endif - err = spl_load_image_fat(stor_dev, - CONFIG_SYS_USB_FAT_BOOT_PARTITION, - CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); + { + err = spl_load_image_fat(spl_image, stor_dev, + CONFIG_SYS_USB_FAT_BOOT_PARTITION, + CONFIG_SPL_FS_LOAD_PAYLOAD_NAME); + } if (err) { puts("Error loading from USB device\n"); @@ -61,3 +65,4 @@ int spl_usb_load_image(void) return 0; } +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_USB, spl_usb_load_image); diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c index 5402301..13e8e51 100644 --- a/common/spl/spl_ymodem.c +++ b/common/spl/spl_ymodem.c @@ -68,7 +68,8 @@ static ulong ymodem_read_fit(struct spl_load_info *load, ulong offset, return size; } -int spl_ymodem_load_image(void) +static int spl_ymodem_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { int size = 0; int err; @@ -102,17 +103,18 @@ int spl_ymodem_load_image(void) info.buf = buf; info.image_read = BUF_SIZE; load.read = ymodem_read_fit; - ret = spl_load_simple_fit(&load, 0, (void *)buf); + ret = spl_load_simple_fit(spl_image, &load, 0, (void *)buf); size = info.image_read; while ((res = xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) size += res; } else { - spl_parse_image_header((struct image_header *)buf); - ret = spl_parse_image_header((struct image_header *)buf); + spl_parse_image_header(spl_image, (struct image_header *)buf); + ret = spl_parse_image_header(spl_image, + (struct image_header *)buf); if (ret) return ret; - addr = spl_image.load_addr; + addr = spl_image->load_addr; memcpy((void *)addr, buf, res); size += res; addr += res; @@ -131,3 +133,4 @@ end_stream: printf("Loaded %d bytes\n", size); return 0; } +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_UART, spl_ymodem_load_image); diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index 5b0c65a..405405d 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M5208EVBE=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig index 3606700..f7aee4b 100644 --- a/configs/M52277EVB_defconfig +++ b/configs/M52277EVB_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_M52277EVB=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="-> " CONFIG_CMD_SF=y CONFIG_CMD_SPI=y diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig index af463c3..200bf35 100644 --- a/configs/M52277EVB_stmicro_defconfig +++ b/configs/M52277EVB_stmicro_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_M52277EVB=y CONFIG_SYS_TEXT_BASE=0x43E00000 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_I2C=y diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index eff91ec..6581802 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_M5235EVB=y CONFIG_SYS_TEXT_BASE=0xFFC00000 CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_I2C=y diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index 28c7f20..15a7f1f 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M5235EVB=y CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig index 1588c52..6c77da4 100644 --- a/configs/M5249EVB_defconfig +++ b/configs/M5249EVB_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_M5249EVB=y CONFIG_SYS_TEXT_BASE=0xffe00000 +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_AUTOBOOT is not set CONFIG_LOOPW=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index e758873..621cb8f 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M5253DEMO=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y diff --git a/configs/M5253EVBE_defconfig b/configs/M5253EVBE_defconfig index 17ded58..4b81ba4 100644 --- a/configs/M5253EVBE_defconfig +++ b/configs/M5253EVBE_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M5253EVBE=y CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NET is not set CONFIG_CMD_CACHE=y diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index 7638b18..9eb3c34 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M5272C3=y CONFIG_SYS_TEXT_BASE=0xffe00000 CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index a7af356..9abc596 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M5275EVB=y CONFIG_SYS_TEXT_BASE=0xffe00000 CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig index f415f7b..9e2f925 100644 --- a/configs/M5282EVB_defconfig +++ b/configs/M5282EVB_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M5282EVB=y CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index 9a5d36a..e1b08f4 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M53017EVB=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_MII=y diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index f09af5e..9a23f9b 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_M5329EVB=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="-> " CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index 9954afa..aa4897f 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_M5329EVB=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="-> " CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index 6f89dd2..41e5a29 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_M5373EVB=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="-> " CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig index be7a37f..cecc78e 100644 --- a/configs/M54418TWR_defconfig +++ b/configs/M54418TWR_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000" +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_IMLS is not set diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig index c04e9ca..81ddca9 100644 --- a/configs/M54418TWR_nand_mii_defconfig +++ b/configs/M54418TWR_nand_mii_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=25000000" +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_IMLS is not set diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig index 3f454e9..069245a 100644 --- a/configs/M54418TWR_nand_rmii_defconfig +++ b/configs/M54418TWR_nand_rmii_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=50000000" +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_IMLS is not set diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig index 2206554..3d80361 100644 --- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig +++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_INPUT_CLKSRC=50000000" +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_IMLS is not set diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig index 244fc73..f84fa4e 100644 --- a/configs/M54418TWR_serial_mii_defconfig +++ b/configs/M54418TWR_serial_mii_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=25000000" +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_IMLS is not set diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig index be7a37f..cecc78e 100644 --- a/configs/M54418TWR_serial_rmii_defconfig +++ b/configs/M54418TWR_serial_rmii_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_M54418TWR=y CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000" +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="-> " # CONFIG_CMD_IMLS is not set diff --git a/configs/MIP405T_defconfig b/configs/MIP405T_defconfig index e5910cd..9b96b85 100644 --- a/configs/MIP405T_defconfig +++ b/configs/MIP405T_defconfig @@ -3,6 +3,7 @@ CONFIG_IDENT_STRING="\n(c) 2003 by MPL AG Switzerland, MEV-10082-001 released" CONFIG_4xx=y CONFIG_TARGET_MIP405T=y CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/MIP405_defconfig b/configs/MIP405_defconfig index a38eac1..96b5c26 100644 --- a/configs/MIP405_defconfig +++ b/configs/MIP405_defconfig @@ -3,6 +3,7 @@ CONFIG_IDENT_STRING="\n(c) 2003 by MPL AG Switzerland, MEV-10072-001 released" CONFIG_4xx=y CONFIG_TARGET_MIP405=y CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/PATI_defconfig b/configs/PATI_defconfig index 80f077a..6ec48ff 100644 --- a/configs/PATI_defconfig +++ b/configs/PATI_defconfig @@ -3,6 +3,7 @@ CONFIG_IDENT_STRING="\n(c) 2003 by MPL AG Switzerland, MEV-10084-001 released" CONFIG_5xx=y CONFIG_TARGET_PATI=y CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="pati=> " # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_IMLS is not set diff --git a/configs/PIP405_defconfig b/configs/PIP405_defconfig index 87f2f31..f290cb1 100644 --- a/configs/PIP405_defconfig +++ b/configs/PIP405_defconfig @@ -3,6 +3,7 @@ CONFIG_IDENT_STRING="\n(c) 2002 by MPL AG Switzerland, MEV-10066-001 released" CONFIG_4xx=y CONFIG_TARGET_PIP405=y CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y CONFIG_CMD_USB=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index 27ea472..15c3389 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -4,6 +4,7 @@ CONFIG_OMAP54XX=y CONFIG_TARGET_AM57XX_EVM=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ARMV7_LPAE=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15" CONFIG_FIT=y diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig index 5cc512c..050b00f 100644 --- a/configs/amcore_defconfig +++ b/configs/amcore_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_AMCORE=y CONFIG_SYS_TEXT_BASE=0xffc00000 CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="amcore $ " CONFIG_DM=y CONFIG_DM_SERIAL=y diff --git a/configs/ap121_defconfig b/configs/ap121_defconfig index cb42e1c..d21fa04 100644 --- a/configs/ap121_defconfig +++ b/configs/ap121_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ARCH_ATH79=y CONFIG_DEFAULT_DEVICE_TREE="ap121" CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y CONFIG_SYS_PROMPT="ap121 # " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/ap143_defconfig b/configs/ap143_defconfig index 27b5c17..5bb9350 100644 --- a/configs/ap143_defconfig +++ b/configs/ap143_defconfig @@ -4,6 +4,7 @@ CONFIG_ARCH_ATH79=y CONFIG_TARGET_AP143=y CONFIG_DEFAULT_DEVICE_TREE="ap143" CONFIG_BOOTDELAY=3 +CONFIG_DISPLAY_CPUINFO=y CONFIG_SYS_PROMPT="ap143 # " # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set diff --git a/configs/apx4devkit_defconfig b/configs/apx4devkit_defconfig index 5b9c0af..9245ebb 100644 --- a/configs/apx4devkit_defconfig +++ b/configs/apx4devkit_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_BOOTDELAY=1 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set diff --git a/configs/aspenite_defconfig b/configs/aspenite_defconfig index 441e65f..0dbb245 100644 --- a/configs/aspenite_defconfig +++ b/configs/aspenite_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_ASPENITE=y CONFIG_IDENT_STRING="\nMarvell-Aspenite DB" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig index 1e41628..94e931e 100644 --- a/configs/astro_mcf5373l_defconfig +++ b/configs/astro_mcf5373l_defconfig @@ -1,6 +1,7 @@ CONFIG_M68K=y CONFIG_TARGET_ASTRO_MCF5373L=y CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="URMEL > " CONFIG_CMD_I2C=y diff --git a/configs/at91rm9200ek_defconfig b/configs/at91rm9200ek_defconfig index e4f7196..e6569aa 100644 --- a/configs/at91rm9200ek_defconfig +++ b/configs/at91rm9200ek_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91RM9200EK=y CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/at91rm9200ek_ram_defconfig b/configs/at91rm9200ek_ram_defconfig index c04cd73..ad81400 100644 --- a/configs/at91rm9200ek_ram_defconfig +++ b/configs/at91rm9200ek_ram_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91RM9200EK=y CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig index 352cdb1..d11b9a6 100644 --- a/configs/at91sam9260ek_dataflash_cs0_defconfig +++ b/configs/at91sam9260ek_dataflash_cs0_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig index e6dd305..4779d66 100644 --- a/configs/at91sam9260ek_dataflash_cs1_defconfig +++ b/configs/at91sam9260ek_dataflash_cs1_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_DATAFLASH_CS1" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig index 9b93fa8..25f9258 100644 --- a/configs/at91sam9260ek_nandflash_defconfig +++ b/configs/at91sam9260ek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig index 51b3ec1..b2a46cb 100644 --- a/configs/at91sam9261ek_dataflash_cs0_defconfig +++ b/configs/at91sam9261ek_dataflash_cs0_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig index f5ffbcd..a16e7e1 100644 --- a/configs/at91sam9261ek_dataflash_cs3_defconfig +++ b/configs/at91sam9261ek_dataflash_cs3_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_DATAFLASH_CS3" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig index c985d3a..17d0fdd 100644 --- a/configs/at91sam9261ek_nandflash_defconfig +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig index 09a1404..5b36688 100644 --- a/configs/at91sam9263ek_dataflash_cs0_defconfig +++ b/configs/at91sam9263ek_dataflash_cs0_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig index 09a1404..5b36688 100644 --- a/configs/at91sam9263ek_dataflash_defconfig +++ b/configs/at91sam9263ek_dataflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index 3a18c3b..024d750 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index e4608d2..297e4e7 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_BOOT_NORFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index 4c97c9f..237bdee 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9263EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NORFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig index 1ee26d9..f00f61b 100644 --- a/configs/at91sam9g10ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig index de6cacd..dc413b2 100644 --- a/configs/at91sam9g10ek_dataflash_cs3_defconfig +++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_DATAFLASH_CS3" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig index 257593d..325e0ee 100644 --- a/configs/at91sam9g10ek_nandflash_defconfig +++ b/configs/at91sam9g10ek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9261EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G10,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig index 182c704..67c8232 100644 --- a/configs/at91sam9g20ek_2mmc_defconfig +++ b/configs/at91sam9g20ek_2mmc_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_MMC" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig index a15351d..6d2bfa1 100644 --- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig +++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig index d4538e3..6d93ff9 100644 --- a/configs/at91sam9g20ek_dataflash_cs0_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig index 4fb0bad..8f1a682 100644 --- a/configs/at91sam9g20ek_dataflash_cs1_defconfig +++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_DATAFLASH_CS1" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig index c563165..998f863 100644 --- a/configs/at91sam9g20ek_nandflash_defconfig +++ b/configs/at91sam9g20ek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig index 0aaa888..de374cf 100644 --- a/configs/at91sam9m10g45ek_mmc_defconfig +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index 05140ac..70cb74f 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index 3eb8666..b2b53b9 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9N12EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_MMC" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index 15e1970..f2c0f3c 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index ebed1db..62b01d6 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9N12,SYS_USE_SPIFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig index 69be1d2..5d92c5f 100644 --- a/configs/at91sam9rlek_dataflash_defconfig +++ b/configs/at91sam9rlek_dataflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9RLEK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig index c49bf18..d7214f2 100644 --- a/configs/at91sam9rlek_mmc_defconfig +++ b/configs/at91sam9rlek_mmc_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9RLEK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_MMC" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig index 142122e..205e44d 100644 --- a/configs/at91sam9rlek_nandflash_defconfig +++ b/configs/at91sam9rlek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9RLEK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9RL,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index beeb8cc..441a940 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index eb88bbb..9962d1f 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9X5EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_MMC" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index 4b28d74..8fb4af7 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index 4a1ea42..2125635 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9X5,SYS_USE_SPIFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig index ca3500b..4085300 100644 --- a/configs/at91sam9xeek_dataflash_cs0_defconfig +++ b/configs/at91sam9xeek_dataflash_cs0_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS0" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig index 3e98c71..1f5e34a 100644 --- a/configs/at91sam9xeek_dataflash_cs1_defconfig +++ b/configs/at91sam9xeek_dataflash_cs1_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_DATAFLASH_CS1" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig index b8ad4c1..d00843f 100644 --- a/configs/at91sam9xeek_nandflash_defconfig +++ b/configs/at91sam9xeek_nandflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_AT91SAM9260EK=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index a5261d2..3e7f77c 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_BDI is not set diff --git a/configs/bcm11130_defconfig b/configs/bcm11130_defconfig index 57cfbd2..dd37b7e 100644 --- a/configs/bcm11130_defconfig +++ b/configs/bcm11130_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_BCM28155_AP=y CONFIG_SYS_EXTRA_OPTIONS="SYS_MMC_ENV_DEV=0" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/bcm11130_nand_defconfig b/configs/bcm11130_nand_defconfig index 586abc0..a013098 100644 --- a/configs/bcm11130_nand_defconfig +++ b/configs/bcm11130_nand_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_BCM28155_AP=y CONFIG_SYS_EXTRA_OPTIONS="NAND" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/bcm23550_w1d_defconfig b/configs/bcm23550_w1d_defconfig index 579a2ba..8d6d28c 100644 --- a/configs/bcm23550_w1d_defconfig +++ b/configs/bcm23550_w1d_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y CONFIG_TARGET_BCM23550_W1D=y CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_FASTBOOT=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/bcm28155_ap_defconfig b/configs/bcm28155_ap_defconfig index 768bd02..1ceaeda 100644 --- a/configs/bcm28155_ap_defconfig +++ b/configs/bcm28155_ap_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y CONFIG_TARGET_BCM28155_AP=y CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_FASTBOOT=y diff --git a/configs/bcm28155_w1d_defconfig b/configs/bcm28155_w1d_defconfig index 8a5111f..06539fd 100644 --- a/configs/bcm28155_w1d_defconfig +++ b/configs/bcm28155_w1d_defconfig @@ -3,6 +3,8 @@ CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y CONFIG_TARGET_BCM28155_AP=y CONFIG_SYS_EXTRA_OPTIONS="BCM_SF2_ETH,BCM_SF2_ETH_GMAC" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/bcm911360_entphn-ns_defconfig b/configs/bcm911360_entphn-ns_defconfig index 97ccec6..c2d04a6 100644 --- a/configs/bcm911360_entphn-ns_defconfig +++ b/configs/bcm911360_entphn-ns_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_BCMCYGNUS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000,ARMV7_NONSEC" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/bcm911360_entphn_defconfig b/configs/bcm911360_entphn_defconfig index bfe358b..2937801 100644 --- a/configs/bcm911360_entphn_defconfig +++ b/configs/bcm911360_entphn_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_BCMCYGNUS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x20000000" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/bcm911360k_defconfig b/configs/bcm911360k_defconfig index ccdbd31..00f6f13 100644 --- a/configs/bcm911360k_defconfig +++ b/configs/bcm911360k_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_BCMCYGNUS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/bcm958300k-ns_defconfig b/configs/bcm958300k-ns_defconfig index ff5ee54..dc26bf7 100644 --- a/configs/bcm958300k-ns_defconfig +++ b/configs/bcm958300k-ns_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_BCMCYGNUS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000,ARMV7_NONSEC" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/bcm958300k_defconfig b/configs/bcm958300k_defconfig index ccdbd31..00f6f13 100644 --- a/configs/bcm958300k_defconfig +++ b/configs/bcm958300k_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_BCMCYGNUS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/bcm958305k_defconfig b/configs/bcm958305k_defconfig index ccdbd31..00f6f13 100644 --- a/configs/bcm958305k_defconfig +++ b/configs/bcm958305k_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_BCMCYGNUS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x40000000" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/bcm958622hr_defconfig b/configs/bcm958622hr_defconfig index 4a93a2d..c7b6d5d 100644 --- a/configs/bcm958622hr_defconfig +++ b/configs/bcm958622hr_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_TARGET_BCMNSP=y CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_SIZE=0x01000000" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_AUTOBOOT is not set CONFIG_CMD_BOOTZ=y diff --git a/configs/bg0900_defconfig b/configs/bg0900_defconfig index 49ca7d9..6c14965 100644 --- a/configs/bg0900_defconfig +++ b/configs/bg0900_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig new file mode 100644 index 0000000..26d9e81 --- /dev/null +++ b/configs/bk4r1_defconfig @@ -0,0 +1,33 @@ +CONFIG_ARM=y +CONFIG_TARGET_BK4R1=y +CONFIG_DEFAULT_DEVICE_TREE="bk4r1" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND" +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_VYBRID_GPIO=y +CONFIG_NAND_VF610_NFC=y +CONFIG_SYS_NAND_BUSWIDTH_16BIT=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_CMD_DM=y +CONFIG_CMD_UBI=y diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 15365b9..8d3ef0e 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -13,6 +13,8 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,EMMC_BOOT" CONFIG_BOOTDELAY=-2 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig index 05fc1e0..f624197 100644 --- a/configs/brppt1_nand_defconfig +++ b/configs/brppt1_nand_defconfig @@ -13,6 +13,8 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,NAND" CONFIG_BOOTDELAY=-2 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig index 4855acc..474477a 100644 --- a/configs/brppt1_spi_defconfig +++ b/configs/brppt1_spi_defconfig @@ -16,6 +16,8 @@ CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT" CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=-2 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index 8fe1100..49c26e2 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -11,6 +11,8 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="SERIAL1,CONS_INDEX=1" CONFIG_BOOTDELAY=-2 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_BOOTD is not set diff --git a/configs/calimain_defconfig b/configs/calimain_defconfig index 9cc4a85..7eee28a 100644 --- a/configs/calimain_defconfig +++ b/configs/calimain_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_CALIMAIN=y CONFIG_BOOTDELAY=0 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Calimain > " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 3729722..2da4b6c 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DM_KEYBOARD=y CONFIG_DEFAULT_DEVICE_TREE="rk3288-jerry" +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_HUSH_PARSER=y diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index 588dfb2..6e46bf7 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index e8a95c8..6a32dd0 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -12,6 +12,8 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig index 400fca0..bd20de8 100644 --- a/configs/cobra5272_defconfig +++ b/configs/cobra5272_defconfig @@ -2,6 +2,7 @@ CONFIG_M68K=y CONFIG_TARGET_COBRA5272=y CONFIG_SYS_TEXT_BASE=0xffe00000 CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="COBRA > " # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 7c4d349..4eca7b9 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -3,8 +3,10 @@ CONFIG_ARCH_MX7=y CONFIG_TARGET_COLIBRI_IMX7=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y +CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Colibri iMX7 # " # CONFIG_CMD_BOOTD is not set @@ -30,8 +32,16 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y CONFIG_DFU_MMC=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y CONFIG_MTD_UBI_FASTMAP=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RN5T567=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y @@ -41,4 +51,3 @@ CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_G_DNL_MANUFACTURER="Toradex" CONFIG_G_DNL_VENDOR_NUM=0x1b67 CONFIG_G_DNL_PRODUCT_NUM=0x4020 -CONFIG_OF_LIBFDT=y diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig index e7b7bff..9a57041 100644 --- a/configs/colibri_pxa270_defconfig +++ b/configs/colibri_pxa270_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_COLIBRI_PXA270=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_IMLS is not set diff --git a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig index 88d189a..84c68b6 100644 --- a/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig +++ b/configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig @@ -9,6 +9,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SDCARD,DEVELOP" CONFIG_BOOTDELAY=10 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/controlcenterd_36BIT_SDCARD_defconfig b/configs/controlcenterd_36BIT_SDCARD_defconfig index c8679e2..0d1cc82 100644 --- a/configs/controlcenterd_36BIT_SDCARD_defconfig +++ b/configs/controlcenterd_36BIT_SDCARD_defconfig @@ -9,6 +9,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SDCARD" CONFIG_BOOTDELAY=10 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig index e94d72f..e45b4df 100644 --- a/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig +++ b/configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig @@ -4,6 +4,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_CONTROLCENTERD=y CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP" CONFIG_BOOTDELAY=-2 +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_BOOTM is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/controlcenterd_TRAILBLAZER_defconfig b/configs/controlcenterd_TRAILBLAZER_defconfig index 257fa85..cd1c6c4 100644 --- a/configs/controlcenterd_TRAILBLAZER_defconfig +++ b/configs/controlcenterd_TRAILBLAZER_defconfig @@ -4,6 +4,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_CONTROLCENTERD=y CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH" CONFIG_BOOTDELAY=-2 +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_BOOTM is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index 66d846a..c373096 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-corvus" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " diff --git a/configs/d2net_v2_defconfig b/configs/d2net_v2_defconfig index 3b94de4..fa06576 100644 --- a/configs/d2net_v2_defconfig +++ b/configs/d2net_v2_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_NET2BIG_V2=y CONFIG_IDENT_STRING=" D2 v2" CONFIG_SYS_EXTRA_OPTIONS="D2NET_V2" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="d2v2> " # CONFIG_CMD_IMLS is not set diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig index 9dc4831..25fcff1 100644 --- a/configs/da850_am18xxevm_defconfig +++ b/configs/da850_am18xxevm_defconfig @@ -9,6 +9,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50" CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index 256fd4f..e2512ff 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -9,6 +9,8 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH" CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 1ab9ff3..ead9685 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -4,6 +4,8 @@ CONFIG_TARGET_DA850EVM=y CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT" CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_CMD_ASKENV=y diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index ce7976a..8ebcbbd 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-375-db" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig index 18fcf0e..b9f0ec3 100644 --- a/configs/db-88f6820-amc_defconfig +++ b/configs/db-88f6820-amc_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-385-amc" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index a883be0..b88268b 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig index b7d2ae2..7b72825 100644 --- a/configs/db-mv784mp-gp_defconfig +++ b/configs/db-mv784mp-gp_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/devconcenter_defconfig b/configs/devconcenter_defconfig index cf41cd1..64c6e11 100644 --- a/configs/devconcenter_defconfig +++ b/configs/devconcenter_defconfig @@ -7,6 +7,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="DEVCONCENTER" CONFIG_BOOTDELAY=5 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index 57f47f6..4c4d031 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_BOOTDELAY=1 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_CMD_SPI=y diff --git a/configs/dlvision-10g_defconfig b/configs/dlvision-10g_defconfig index 621ac44..d8d35e6 100644 --- a/configs/dlvision-10g_defconfig +++ b/configs/dlvision-10g_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/dlvision_defconfig b/configs/dlvision_defconfig index 586b802..0f0ef8c 100644 --- a/configs/dlvision_defconfig +++ b/configs/dlvision_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_ELF is not set CONFIG_CMD_ASKENV=y diff --git a/configs/dns325_defconfig b/configs/dns325_defconfig index a26629d..de2c4aa 100644 --- a/configs/dns325_defconfig +++ b/configs/dns325_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_TARGET_DNS325=y CONFIG_IDENT_STRING="\nD-Link DNS-325" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/dockstar_defconfig b/configs/dockstar_defconfig index 645f652..e263c5b 100644 --- a/configs/dockstar_defconfig +++ b/configs/dockstar_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_TARGET_DOCKSTAR=y CONFIG_IDENT_STRING="\nSeagate FreeAgent DockStar" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="DockStar> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index c74dc18..14ecc24 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -4,6 +4,7 @@ CONFIG_OMAP54XX=y CONFIG_TARGET_DRA7XX_EVM=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y +CONFIG_ARMV7_LPAE=y CONFIG_SPL_STACK_R_ADDR=0x82000000 CONFIG_DEFAULT_DEVICE_TREE="dra7-evm" CONFIG_FIT=y @@ -14,6 +15,14 @@ CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_BUF_SIZE=0x2f000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y @@ -36,7 +45,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="dra7-evm dra72-evm" +CONFIG_OF_LIST="dra7-evm dra72-evm dra72-evm-revc" CONFIG_DM=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 29bea9a..a18fd14 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -18,6 +18,14 @@ CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_DMA_SUPPORT=y CONFIG_HUSH_PARSER=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_BUF_SIZE=0x2f000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index edd6c9b..bce876f 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 3ff055f..eea12fe 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_SNAPDRAGON=y CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 410C" CONFIG_DEFAULT_DEVICE_TREE="dragonboard410c" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="dragonboard410c => " # CONFIG_CMD_IMI is not set diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig index 3ff3ba4..ec9ab9b 100644 --- a/configs/dreamplug_defconfig +++ b/configs/dreamplug_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_TARGET_DREAMPLUG=y CONFIG_IDENT_STRING="\nMarvell-DreamPlug" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig index 1d16833..8d3816a 100644 --- a/configs/ds414_defconfig +++ b/configs/ds414_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-xp-synology-ds414" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/ea20_defconfig b/configs/ea20_defconfig index 0e28878..a808145 100644 --- a/configs/ea20_defconfig +++ b/configs/ea20_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_EA20=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ea20 > " # CONFIG_CMD_IMLS is not set diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index bf9177b..60eab39 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_EB_CPU5282=y CONFIG_SYS_TEXT_BASE=0xFF000000 CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400" CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="\nEB+CPU5282> " # CONFIG_CMD_LOADB is not set CONFIG_CMD_I2C=y diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index 4f6de89..1b1702e 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_EB_CPU5282=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418" CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_LOADB is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/edb9315a_defconfig b/configs/edb9315a_defconfig index 49f870a..6e7c5d8 100644 --- a/configs/edb9315a_defconfig +++ b/configs/edb9315a_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_TARGET_EDB93XX=y CONFIG_SYS_EXTRA_OPTIONS="MK_edb9315a" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="EDB9315A> " CONFIG_CMD_BOOTZ=y diff --git a/configs/edminiv2_defconfig b/configs/edminiv2_defconfig index ef221b2..036935e 100644 --- a/configs/edminiv2_defconfig +++ b/configs/edminiv2_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_TARGET_EDMINIV2=y CONFIG_IDENT_STRING=" EDMiniV2" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/espresso7420_defconfig b/configs/espresso7420_defconfig index e7163d3..2281d7e 100644 --- a/configs/espresso7420_defconfig +++ b/configs/espresso7420_defconfig @@ -4,6 +4,7 @@ CONFIG_ARCH_EXYNOS7=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_IDENT_STRING=" for ESPRESSO7420" CONFIG_DEFAULT_DEVICE_TREE="exynos7420-espresso7420" +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="ESPRESSO7420 # " # CONFIG_AUTOBOOT is not set # CONFIG_CMD_IMLS is not set diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index 0a4aead..869a6e9 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig index a89aa52..c831aab 100644 --- a/configs/ethernut5_defconfig +++ b/configs/ethernut5_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_ETHERNUT5=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/evb-rk3036_defconfig b/configs/evb-rk3036_defconfig index b49c562..6546db9 100644 --- a/configs/evb-rk3036_defconfig +++ b/configs/evb-rk3036_defconfig @@ -4,6 +4,7 @@ CONFIG_ROCKCHIP_RK3036=y CONFIG_TARGET_EVB_RK3036=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index c7396a5..85f957f 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -5,6 +5,7 @@ CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_EVB_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb" +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_HUSH_PARSER=y @@ -47,10 +48,8 @@ CONFIG_SPL_PINCTRL=y CONFIG_ROCKCHIP_RK3288_PINCTRL=y CONFIG_DM_PMIC=y CONFIG_PMIC_ACT8846=y -CONFIG_DM_REGULATOR=y CONFIG_REGULATOR_ACT8846=y CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_PWM=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_SPL_RAM=y diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 97f2966..b519d7f 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_ROCKCHIP=y CONFIG_ROCKCHIP_RK3399=y CONFIG_DEFAULT_DEVICE_TREE="rk3399-evb" CONFIG_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/fennec-rk3288_defconfig b/configs/fennec-rk3288_defconfig index a5c089b..1170b87 100644 --- a/configs/fennec-rk3288_defconfig +++ b/configs/fennec-rk3288_defconfig @@ -5,6 +5,7 @@ CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_FENNEC_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec" +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_HUSH_PARSER=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index ba461b9..a6c5094 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -5,6 +5,7 @@ CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_FIREFLY_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-firefly" +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_HUSH_PARSER=y diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig index f6e01c1..7aa1ba8 100644 --- a/configs/flea3_defconfig +++ b/configs/flea3_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_FLEA3=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="flea3 U-Boot > " CONFIG_CMD_SPI=y diff --git a/configs/gdppc440etx_defconfig b/configs/gdppc440etx_defconfig index 4df39f6..674c865 100644 --- a/configs/gdppc440etx_defconfig +++ b/configs/gdppc440etx_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_GDPPC440ETX=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/goflexhome_defconfig b/configs/goflexhome_defconfig index 22e8452..8eeeafb 100644 --- a/configs/goflexhome_defconfig +++ b/configs/goflexhome_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_TARGET_GOFLEXHOME=y CONFIG_IDENT_STRING="\nSeagate GoFlex Home" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="GoFlexHome> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/gplugd_defconfig b/configs/gplugd_defconfig index 1a8ce9a..59c9fdf 100644 --- a/configs/gplugd_defconfig +++ b/configs/gplugd_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_GPLUGD=y CONFIG_IDENT_STRING="\nMarvell-gplugD" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y # CONFIG_CMD_FLASH is not set diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig index d2ef958..765f4e7 100644 --- a/configs/gurnard_defconfig +++ b/configs/gurnard_defconfig @@ -5,6 +5,7 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9g45-gurnard" CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig index becc587..43127de 100644 --- a/configs/guruplug_defconfig +++ b/configs/guruplug_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_TARGET_GURUPLUG=y CONFIG_IDENT_STRING="\nMarvell-GuruPlug" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig index 0f726ae..acf9b84 100644 --- a/configs/gwventana_defconfig +++ b/configs/gwventana_defconfig @@ -16,6 +16,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_SPL_DMA_SUPPORT=y diff --git a/configs/h2200_defconfig b/configs/h2200_defconfig index 22f0759..ed2217a 100644 --- a/configs/h2200_defconfig +++ b/configs/h2200_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_TARGET_H2200=y CONFIG_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="> " # CONFIG_CMD_BDI is not set diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig index 56bf948..b4f3975 100644 --- a/configs/highbank_defconfig +++ b/configs/highbank_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_HIGHBANK=y CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds...\nPress <s> to stop or <d> to delay\n" diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index 3901dfe..95790bf 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_IDENT_STRING="hikey" CONFIG_DEFAULT_DEVICE_TREE="hi6220-hikey" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_MMC=y diff --git a/configs/hrcon_defconfig b/configs/hrcon_defconfig index b6b583d..bdd5a37 100644 --- a/configs/hrcon_defconfig +++ b/configs/hrcon_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/hrcon_dh_defconfig b/configs/hrcon_dh_defconfig index 82ebc5f..b558c96 100644 --- a/configs/hrcon_dh_defconfig +++ b/configs/hrcon_dh_defconfig @@ -8,6 +8,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH" CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_MMC=y CONFIG_CMD_I2C=y diff --git a/configs/ib62x0_defconfig b/configs/ib62x0_defconfig index bfeb06e..4260245 100644 --- a/configs/ib62x0_defconfig +++ b/configs/ib62x0_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_TARGET_IB62X0=y CONFIG_IDENT_STRING=" RaidSonic ICY BOX IB-NAS62x0" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ib62x0 => " CONFIG_CMD_BOOTZ=y diff --git a/configs/icon_defconfig b/configs/icon_defconfig index 6556fa6..cc08b5a 100644 --- a/configs/icon_defconfig +++ b/configs/icon_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_ICON=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/iconnect_defconfig b/configs/iconnect_defconfig index b59ff09..5b570b7 100644 --- a/configs/iconnect_defconfig +++ b/configs/iconnect_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_TARGET_ICONNECT=y CONFIG_IDENT_STRING=" Iomega iConnect" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="iconnect => " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig index c083f8a..d2fac61 100644 --- a/configs/ids8313_defconfig +++ b/configs/ids8313_defconfig @@ -8,6 +8,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xFFF00000" CONFIG_BOOTDELAY=1 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Enter password - autoboot in %d seconds...\n" diff --git a/configs/imgtec_xilfpga_defconfig b/configs/imgtec_xilfpga_defconfig index 63f03cd..1e57273 100644 --- a/configs/imgtec_xilfpga_defconfig +++ b/configs/imgtec_xilfpga_defconfig @@ -5,6 +5,7 @@ CONFIG_TARGET_XILFPGA=y CONFIG_MIPS_BOOT_FDT=y CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr" CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="MIPSfpga # " # CONFIG_CMD_IMLS is not set diff --git a/configs/inetspace_v2_defconfig b/configs/inetspace_v2_defconfig index 3a5bf5e..2144894 100644 --- a/configs/inetspace_v2_defconfig +++ b/configs/inetspace_v2_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_NETSPACE_V2=y CONFIG_IDENT_STRING=" IS v2" CONFIG_SYS_EXTRA_OPTIONS="INETSPACE_V2" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " # CONFIG_CMD_IMLS is not set diff --git a/configs/integratorap_cm720t_defconfig b/configs/integratorap_cm720t_defconfig index 7b70eed..861e231 100644 --- a/configs/integratorap_cm720t_defconfig +++ b/configs/integratorap_cm720t_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_INTEGRATOR=y CONFIG_ARCH_INTEGRATOR_AP=y CONFIG_CM720T=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-AP # " CONFIG_CMD_ARMFLASH=y diff --git a/configs/integratorap_cm920t_defconfig b/configs/integratorap_cm920t_defconfig index 4acb12a..38cd042 100644 --- a/configs/integratorap_cm920t_defconfig +++ b/configs/integratorap_cm920t_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_INTEGRATOR=y CONFIG_ARCH_INTEGRATOR_AP=y CONFIG_CM920T=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-AP # " CONFIG_CMD_ARMFLASH=y diff --git a/configs/integratorap_cm926ejs_defconfig b/configs/integratorap_cm926ejs_defconfig index dc66f59..bab0e1b 100644 --- a/configs/integratorap_cm926ejs_defconfig +++ b/configs/integratorap_cm926ejs_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_INTEGRATOR=y CONFIG_ARCH_INTEGRATOR_AP=y CONFIG_CM926EJ_S=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-AP # " CONFIG_CMD_ARMFLASH=y diff --git a/configs/integratorap_cm946es_defconfig b/configs/integratorap_cm946es_defconfig index ce16756..1bbd7ba 100644 --- a/configs/integratorap_cm946es_defconfig +++ b/configs/integratorap_cm946es_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_INTEGRATOR=y CONFIG_ARCH_INTEGRATOR_AP=y CONFIG_CM946ES=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-AP # " CONFIG_CMD_ARMFLASH=y diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig index 913ccab..29b1cd5 100644 --- a/configs/integratorcp_cm1136_defconfig +++ b/configs/integratorcp_cm1136_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_INTEGRATOR=y CONFIG_ARCH_INTEGRATOR_CP=y CONFIG_CM1136=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-CP # " CONFIG_CMD_ARMFLASH=y diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig index 17c3f94..35da8c7 100644 --- a/configs/integratorcp_cm920t_defconfig +++ b/configs/integratorcp_cm920t_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_INTEGRATOR=y CONFIG_ARCH_INTEGRATOR_CP=y CONFIG_CM920T=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-CP # " CONFIG_CMD_ARMFLASH=y diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig index c757fad..e99cd80 100644 --- a/configs/integratorcp_cm926ejs_defconfig +++ b/configs/integratorcp_cm926ejs_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_INTEGRATOR=y CONFIG_ARCH_INTEGRATOR_CP=y CONFIG_CM926EJ_S=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-CP # " CONFIG_CMD_ARMFLASH=y diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig index 196eab7..02bc0f3 100644 --- a/configs/integratorcp_cm946es_defconfig +++ b/configs/integratorcp_cm946es_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_INTEGRATOR=y CONFIG_ARCH_INTEGRATOR_CP=y CONFIG_CM946ES=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Integrator-CP # " CONFIG_CMD_ARMFLASH=y diff --git a/configs/intip_defconfig b/configs/intip_defconfig index 9e1b44a..4ee8075 100644 --- a/configs/intip_defconfig +++ b/configs/intip_defconfig @@ -7,6 +7,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="INTIB" CONFIG_BOOTDELAY=5 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/io64_defconfig b/configs/io64_defconfig index 6215c77..58db5ca 100644 --- a/configs/io64_defconfig +++ b/configs/io64_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/io_defconfig b/configs/io_defconfig index 139556e5..eeeada6 100644 --- a/configs/io_defconfig +++ b/configs/io_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/iocon_defconfig b/configs/iocon_defconfig index 2cc836d..a330a08 100644 --- a/configs/iocon_defconfig +++ b/configs/iocon_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/ipam390_defconfig b/configs/ipam390_defconfig index d0fdcac..603b41b 100644 --- a/configs/ipam390_defconfig +++ b/configs/ipam390_defconfig @@ -7,6 +7,8 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " diff --git a/configs/km_kirkwood_128m16_defconfig b/configs/km_kirkwood_128m16_defconfig index b3045c7..a3535dd 100644 --- a/configs/km_kirkwood_128m16_defconfig +++ b/configs/km_kirkwood_128m16_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile Kirkwood 128M16" CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_128M16" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" diff --git a/configs/km_kirkwood_defconfig b/configs/km_kirkwood_defconfig index f261bd4..e7461bb 100644 --- a/configs/km_kirkwood_defconfig +++ b/configs/km_kirkwood_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile Kirkwood" CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" diff --git a/configs/km_kirkwood_pci_defconfig b/configs/km_kirkwood_pci_defconfig index c2a6a43..b2dd27b 100644 --- a/configs/km_kirkwood_pci_defconfig +++ b/configs/km_kirkwood_pci_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile Kirkwood PCI" CONFIG_SYS_EXTRA_OPTIONS="KM_KIRKWOOD_PCI" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" diff --git a/configs/kmcoge5un_defconfig b/configs/kmcoge5un_defconfig index b0e5ab1..bd718f2 100644 --- a/configs/kmcoge5un_defconfig +++ b/configs/kmcoge5un_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile COGE5UN" CONFIG_SYS_EXTRA_OPTIONS="KM_COGE5UN" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" diff --git a/configs/kmnusa_defconfig b/configs/kmnusa_defconfig index d0dc6fd..b266631 100644 --- a/configs/kmnusa_defconfig +++ b/configs/kmnusa_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile NUSA" CONFIG_SYS_EXTRA_OPTIONS="KM_NUSA" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" diff --git a/configs/kmsugp1_defconfig b/configs/kmsugp1_defconfig index e7ccc0a..29a439a 100644 --- a/configs/kmsugp1_defconfig +++ b/configs/kmsugp1_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile SUGP1" CONFIG_SYS_EXTRA_OPTIONS="KM_SUGP1" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" diff --git a/configs/kmsuv31_defconfig b/configs/kmsuv31_defconfig index 9a06d58..81b98db 100644 --- a/configs/kmsuv31_defconfig +++ b/configs/kmsuv31_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile SUV31" CONFIG_SYS_EXTRA_OPTIONS="KM_SUV31" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" diff --git a/configs/kylin-rk3036_defconfig b/configs/kylin-rk3036_defconfig index d8b1eed..424cdab 100644 --- a/configs/kylin-rk3036_defconfig +++ b/configs/kylin-rk3036_defconfig @@ -4,6 +4,7 @@ CONFIG_ROCKCHIP_RK3036=y CONFIG_TARGET_KYLIN_RK3036=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3036-sdk" +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig index 5ab3a61..8b01405 100644 --- a/configs/legoev3_defconfig +++ b/configs/legoev3_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_DAVINCI=y CONFIG_TARGET_LEGOEV3=y CONFIG_BOOTDELAY=0 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Autoboot in %d seconds - press 'l' to stop...\n" diff --git a/configs/ls1012afrdm_qspi_defconfig b/configs/ls1012afrdm_qspi_defconfig index c05f031..1f3d487 100644 --- a/configs/ls1012afrdm_qspi_defconfig +++ b/configs/ls1012afrdm_qspi_defconfig @@ -9,6 +9,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_SF=y diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig index 8be68ee..c19816d 100644 --- a/configs/ls1012aqds_qspi_defconfig +++ b/configs/ls1012aqds_qspi_defconfig @@ -9,6 +9,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig index f7ef2d6..5d850f6 100644 --- a/configs/ls1012ardb_qspi_defconfig +++ b/configs/ls1012ardb_qspi_defconfig @@ -9,6 +9,7 @@ CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=10 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_GREPENV=y CONFIG_CMD_MMC=y diff --git a/configs/ls2080a_emu_defconfig b/configs/ls2080a_emu_defconfig index dfc1415..e3c02fb 100644 --- a/configs/ls2080a_emu_defconfig +++ b/configs/ls2080a_emu_defconfig @@ -7,6 +7,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A" CONFIG_BOOTDELAY=10 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set diff --git a/configs/ls2080a_simu_defconfig b/configs/ls2080a_simu_defconfig index a677cb9..081f810 100644 --- a/configs/ls2080a_simu_defconfig +++ b/configs/ls2080a_simu_defconfig @@ -7,6 +7,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A" CONFIG_BOOTDELAY=10 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set diff --git a/configs/lschlv2_defconfig b/configs/lschlv2_defconfig index 5393084..2e17a57 100644 --- a/configs/lschlv2_defconfig +++ b/configs/lschlv2_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_LSXL=y CONFIG_IDENT_STRING=" LS-CHLv2" CONFIG_SYS_EXTRA_OPTIONS="LSCHLV2" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/lsxhl_defconfig b/configs/lsxhl_defconfig index 48bacaa..2cbde40 100644 --- a/configs/lsxhl_defconfig +++ b/configs/lsxhl_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_LSXL=y CONFIG_IDENT_STRING=" LS-XHL" CONFIG_SYS_EXTRA_OPTIONS="LSXHL" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/m28evk_defconfig b/configs/m28evk_defconfig index 2bfed59..6a057e5 100644 --- a/configs/m28evk_defconfig +++ b/configs/m28evk_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set diff --git a/configs/ma5d4evk_defconfig b/configs/ma5d4evk_defconfig index 638764d..e2a68fb 100644 --- a/configs/ma5d4evk_defconfig +++ b/configs/ma5d4evk_defconfig @@ -11,6 +11,7 @@ CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4" CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/maxbcm_defconfig b/configs/maxbcm_defconfig index d689c63..70694ab 100644 --- a/configs/maxbcm_defconfig +++ b/configs/maxbcm_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="armada-xp-maxbcm" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/mgcoge3un_defconfig b/configs/mgcoge3un_defconfig index 8b9231c..becc257 100644 --- a/configs/mgcoge3un_defconfig +++ b/configs/mgcoge3un_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile COGE3UN" CONFIG_SYS_EXTRA_OPTIONS="KM_MGCOGE3UN" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" diff --git a/configs/miniarm-rk3288_defconfig b/configs/miniarm-rk3288_defconfig index 6354d1a..bc5c980 100644 --- a/configs/miniarm-rk3288_defconfig +++ b/configs/miniarm-rk3288_defconfig @@ -5,6 +5,7 @@ CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_MINIARM_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-miniarm" +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_HUSH_PARSER=y diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig index 813d064..c40020c 100644 --- a/configs/mvebu_db-88f3720_defconfig +++ b/configs/mvebu_db-88f3720_defconfig @@ -5,6 +5,8 @@ CONFIG_TARGET_MVEBU_DB_88F3720=y CONFIG_DEFAULT_DEVICE_TREE="armada-3720-db" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y diff --git a/configs/mvebu_db-88f7040_defconfig b/configs/mvebu_db-88f7040_defconfig index 4d68bdc..96a5785 100644 --- a/configs/mvebu_db-88f7040_defconfig +++ b/configs/mvebu_db-88f7040_defconfig @@ -5,6 +5,8 @@ CONFIG_TARGET_MVEBU_DB_88F7040=y CONFIG_DEFAULT_DEVICE_TREE="armada-7040-db" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_SF=y diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig index 4c1a505..ad27842 100644 --- a/configs/mx23_olinuxino_defconfig +++ b/configs/mx23_olinuxino_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig index 8db7064..023d99b 100644 --- a/configs/mx23evk_defconfig +++ b/configs/mx23evk_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_BOOTDELAY=1 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig index f833edc..bd932ff 100644 --- a/configs/mx28evk_auart_console_defconfig +++ b/configs/mx28evk_auart_console_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC" CONFIG_BOOTDELAY=1 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig index 1ab2747..42c6383 100644 --- a/configs/mx28evk_defconfig +++ b/configs/mx28evk_defconfig @@ -8,6 +8,7 @@ CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC" CONFIG_BOOTDELAY=1 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig index af35c49..0980045 100644 --- a/configs/mx28evk_nand_defconfig +++ b/configs/mx28evk_nand_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_NAND" CONFIG_BOOTDELAY=1 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig index 02a50bf..b9e9d97 100644 --- a/configs/mx28evk_spi_defconfig +++ b/configs/mx28evk_spi_defconfig @@ -7,6 +7,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_SPI_FLASH" CONFIG_BOOTDELAY=1 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/mx35pdk_defconfig b/configs/mx35pdk_defconfig index 812e6d5..c44681f 100644 --- a/configs/mx35pdk_defconfig +++ b/configs/mx35pdk_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_MX35PDK=y CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y CONFIG_CMD_MMC=y diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig index b75ba01..ef1b3a1 100644 --- a/configs/mx53loco_defconfig +++ b/configs/mx53loco_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_TARGET_MX53LOCO=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53loco/imximage.cfg" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig new file mode 100644 index 0000000..a106b5d --- /dev/null +++ b/configs/mx6ull_14x14_evk_defconfig @@ -0,0 +1,30 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_SPI=y diff --git a/configs/nas220_defconfig b/configs/nas220_defconfig index c4e7307..3000d72 100644 --- a/configs/nas220_defconfig +++ b/configs/nas220_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_TARGET_NAS220=y CONFIG_IDENT_STRING="\nNAS 220" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="nas220> " # CONFIG_CMD_IMLS is not set diff --git a/configs/neo_defconfig b/configs/neo_defconfig index 18b43e4..200a9f5 100644 --- a/configs/neo_defconfig +++ b/configs/neo_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_ELF is not set CONFIG_CMD_ASKENV=y diff --git a/configs/net2big_v2_defconfig b/configs/net2big_v2_defconfig index 122ed7a..6ed8ea1 100644 --- a/configs/net2big_v2_defconfig +++ b/configs/net2big_v2_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_NET2BIG_V2=y CONFIG_IDENT_STRING=" 2Big v2" CONFIG_SYS_EXTRA_OPTIONS="NET2BIG_V2" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="2big2> " # CONFIG_CMD_IMLS is not set diff --git a/configs/netspace_lite_v2_defconfig b/configs/netspace_lite_v2_defconfig index 0547aa6..6518752 100644 --- a/configs/netspace_lite_v2_defconfig +++ b/configs/netspace_lite_v2_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_NETSPACE_V2=y CONFIG_IDENT_STRING=" NS v2 Lite" CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_LITE_V2" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " # CONFIG_CMD_IMLS is not set diff --git a/configs/netspace_max_v2_defconfig b/configs/netspace_max_v2_defconfig index e72815d..e5e0fcb 100644 --- a/configs/netspace_max_v2_defconfig +++ b/configs/netspace_max_v2_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_NETSPACE_V2=y CONFIG_IDENT_STRING=" NS Max v2" CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MAX_V2" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " # CONFIG_CMD_IMLS is not set diff --git a/configs/netspace_mini_v2_defconfig b/configs/netspace_mini_v2_defconfig index 1422787..52e991b 100644 --- a/configs/netspace_mini_v2_defconfig +++ b/configs/netspace_mini_v2_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_NETSPACE_V2=y CONFIG_IDENT_STRING=" NS v2 Mini" CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_MINI_V2" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " # CONFIG_CMD_IMLS is not set diff --git a/configs/netspace_v2_defconfig b/configs/netspace_v2_defconfig index 6373255..8f36a60 100644 --- a/configs/netspace_v2_defconfig +++ b/configs/netspace_v2_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_NETSPACE_V2=y CONFIG_IDENT_STRING=" NS v2" CONFIG_SYS_EXTRA_OPTIONS="NETSPACE_V2" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ns2> " # CONFIG_CMD_IMLS is not set diff --git a/configs/nsa310s_defconfig b/configs/nsa310s_defconfig index ec4fb53..add5e07 100644 --- a/configs/nsa310s_defconfig +++ b/configs/nsa310s_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_KIRKWOOD=y CONFIG_TARGET_NSA310S=y CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="nsa310s => " CONFIG_CMD_BOOTZ=y diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig index ee70df0..9db718c 100644 --- a/configs/odroid-c2_defconfig +++ b/configs/odroid-c2_defconfig @@ -4,6 +4,8 @@ CONFIG_MESON_GXBB=y CONFIG_TARGET_ODROID_C2=y CONFIG_IDENT_STRING=" odroid-c2" CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 4d5f408..bcd1acb 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -6,6 +6,8 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig index be99ea9..0168579 100644 --- a/configs/openrd_base_defconfig +++ b/configs/openrd_base_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_OPENRD=y CONFIG_IDENT_STRING="\nOpenRD-Base" CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig index 87b2e45..84fa149 100644 --- a/configs/openrd_client_defconfig +++ b/configs/openrd_client_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_OPENRD=y CONFIG_IDENT_STRING="\nOpenRD-Client" CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig index c216b9b..026204d 100644 --- a/configs/openrd_ultimate_defconfig +++ b/configs/openrd_ultimate_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_OPENRD=y CONFIG_IDENT_STRING="\nOpenRD-Ultimate" CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig index 2536ca7..3e69f42 100644 --- a/configs/picosam9g45_defconfig +++ b/configs/picosam9g45_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig index 361e9bb..f9a59a60 100644 --- a/configs/pm9261_defconfig +++ b/configs/pm9261_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_PM9261=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SYS_PROMPT="pm9261> " # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig index 8d3ca22..5b0fade 100644 --- a/configs/pm9g45_defconfig +++ b/configs/pm9g45_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_PM9G45=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_IMLS is not set diff --git a/configs/pogo_e02_defconfig b/configs/pogo_e02_defconfig index cdb85d2..1882995 100644 --- a/configs/pogo_e02_defconfig +++ b/configs/pogo_e02_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_TARGET_POGO_E02=y CONFIG_IDENT_STRING="\nPogo E02" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="PogoE02> " # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index 112e6ae..2b5b26f 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -5,6 +5,7 @@ CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_POPMETAL_RK3288=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-popmetal" +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 CONFIG_HUSH_PARSER=y diff --git a/configs/portl2_defconfig b/configs/portl2_defconfig index 866171b..acc359e 100644 --- a/configs/portl2_defconfig +++ b/configs/portl2_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_KM_KIRKWOOD=y CONFIG_IDENT_STRING="\nKeymile Port-L2" CONFIG_SYS_EXTRA_OPTIONS="KM_PORTL2" CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit <SPACE> key to stop autoboot in %2ds\n" diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 8b9a890..602fc9f 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50" CONFIG_FIT=y CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index 038eb39..c3df65a 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index d9b594b..0aa0e18 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 0361256..a89cb15 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -5,6 +5,7 @@ CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_ROCK2=y CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-rock2-square" +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 # CONFIG_SPL_MMC_SUPPORT is not set diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig index bda4e95..591fa35 100644 --- a/configs/rpi_2_defconfig +++ b/configs/rpi_2_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_BCM283X=y CONFIG_TARGET_RPI_2=y CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig index 8e2c410..851deaa 100644 --- a/configs/rpi_3_32b_defconfig +++ b/configs/rpi_3_32b_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_BCM283X=y CONFIG_TARGET_RPI_3_32B=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig index b7354eb..66fcc1b 100644 --- a/configs/rpi_3_defconfig +++ b/configs/rpi_3_defconfig @@ -3,6 +3,8 @@ CONFIG_ARCH_BCM283X=y CONFIG_TARGET_RPI_3=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_IMLS is not set diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index ea39231..d912945 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -2,6 +2,8 @@ CONFIG_ARM=y CONFIG_ARCH_BCM283X=y CONFIG_TARGET_RPI=y CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " CONFIG_CMD_BOOTZ=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index 1cf5a5f..99b732c 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -17,6 +17,8 @@ CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="am335x-rut" CONFIG_FIT=y CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " diff --git a/configs/sama5d2_ptc_nandflash_defconfig b/configs/sama5d2_ptc_nandflash_defconfig index b64527d..04bd12b 100644 --- a/configs/sama5d2_ptc_nandflash_defconfig +++ b/configs/sama5d2_ptc_nandflash_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set diff --git a/configs/sama5d2_ptc_spiflash_defconfig b/configs/sama5d2_ptc_spiflash_defconfig index 9dc3976..1e8825e 100644 --- a/configs/sama5d2_ptc_spiflash_defconfig +++ b/configs/sama5d2_ptc_spiflash_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_IMLS is not set diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index 8ac42a3..23ab4d6 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index 12b7e07..f208dc2 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_SERIALFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index 521409a..4f4e51b 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index 18dfb5c..e83d047 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index ccc0b19..9573eff 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_MMC" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index 2ed8a33..73f13bd 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index 81be7f5..bff891e 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_SERIALFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 8a3d160..5ff4688 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index ad5d935..800a8b2 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index 8fc650f..e5d2f54 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index e7398dd..a3ffdd3 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index e4032f9..d49645e 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index 903ddcb..db243af 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/sansa_fuze_plus_defconfig b/configs/sansa_fuze_plus_defconfig index de07139..0bdc5aa 100644 --- a/configs/sansa_fuze_plus_defconfig +++ b/configs/sansa_fuze_plus_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set diff --git a/configs/sbc8548_PCI_33_PCIE_defconfig b/configs/sbc8548_PCI_33_PCIE_defconfig index c5fc4a0..e6145ef 100644 --- a/configs/sbc8548_PCI_33_PCIE_defconfig +++ b/configs/sbc8548_PCI_33_PCIE_defconfig @@ -5,6 +5,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,33,PCIE" CONFIG_BOOTDELAY=10 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/sbc8548_PCI_33_defconfig b/configs/sbc8548_PCI_33_defconfig index 1fd17ca..568da28 100644 --- a/configs/sbc8548_PCI_33_defconfig +++ b/configs/sbc8548_PCI_33_defconfig @@ -5,6 +5,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,33" CONFIG_BOOTDELAY=10 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/sbc8548_PCI_66_PCIE_defconfig b/configs/sbc8548_PCI_66_PCIE_defconfig index 5396e5a..bd3ccd1 100644 --- a/configs/sbc8548_PCI_66_PCIE_defconfig +++ b/configs/sbc8548_PCI_66_PCIE_defconfig @@ -5,6 +5,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,66,PCIE" CONFIG_BOOTDELAY=10 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/sbc8548_PCI_66_defconfig b/configs/sbc8548_PCI_66_defconfig index ffde056..53bcc1e 100644 --- a/configs/sbc8548_PCI_66_defconfig +++ b/configs/sbc8548_PCI_66_defconfig @@ -5,6 +5,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="PCI,66" CONFIG_BOOTDELAY=10 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/sbc8548_defconfig b/configs/sbc8548_defconfig index a8a8a93..f64868f 100644 --- a/configs/sbc8548_defconfig +++ b/configs/sbc8548_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8548=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig index a382794..d55e178 100644 --- a/configs/sbc8641d_defconfig +++ b/configs/sbc8641d_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_SBC8641D=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=10 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/sc_sps_1_defconfig b/configs/sc_sps_1_defconfig index f3b74b6..81fb434 100644 --- a/configs/sc_sps_1_defconfig +++ b/configs/sc_sps_1_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig index 67d75ec..e15355d 100644 --- a/configs/sheevaplug_defconfig +++ b/configs/sheevaplug_defconfig @@ -3,6 +3,7 @@ CONFIG_KIRKWOOD=y CONFIG_TARGET_SHEEVAPLUG=y CONFIG_IDENT_STRING="\nMarvell-Sheevaplug" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 64173c7..c0fe23a 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="at91sam9260-smartweb" CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " diff --git a/configs/smdk2410_defconfig b/configs/smdk2410_defconfig index 1cb7960..d6aa2dd 100644 --- a/configs/smdk2410_defconfig +++ b/configs/smdk2410_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_SMDK2410=y CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="SMDK2410 # " CONFIG_CMD_USB=y diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig index 28e149a..7cd5f57 100644 --- a/configs/snapper9260_defconfig +++ b/configs/snapper9260_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_SNAPPER9260=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Snapper> " # CONFIG_CMD_BDI is not set diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig index 564d5b4..1bd4426 100644 --- a/configs/snapper9g20_defconfig +++ b/configs/snapper9g20_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_SNAPPER9260=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_BDI is not set # CONFIG_CMD_IMI is not set diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index d8611bd..751769e 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk" CONFIG_FIT=y CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 42b71c3..d871c57 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk" CONFIG_FIT=y CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index f38e376..9d41d8c 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc" CONFIG_FIT=y CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index c3217f2..4d5622b 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_is1" CONFIG_FIT=y CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_STACK_R=y CONFIG_HUSH_PARSER=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 4041b68..4fe0691 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_mcvevk" CONFIG_FIT=y CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 58dc5b0..e216307 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit" CONFIG_FIT=y CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 42af4ba..076d713 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" CONFIG_FIT=y CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 814b111..0db8b37 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_STACK_R_ADDR=0x00800000 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500" CONFIG_FIT=y CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index d83f1e5..0b34ed3 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga" CONFIG_FIT=y CONFIG_BOOTDELAY=5 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y diff --git a/configs/spear300_defconfig b/configs/spear300_defconfig index 620758e..fd56667 100644 --- a/configs/spear300_defconfig +++ b/configs/spear300_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR300=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR300" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear300_nand_defconfig b/configs/spear300_nand_defconfig index 497b29d..c544b5c 100644 --- a/configs/spear300_nand_defconfig +++ b/configs/spear300_nand_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR300=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR300,NAND" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear300_usbtty_defconfig b/configs/spear300_usbtty_defconfig index 34f0ec0..ebcc237 100644 --- a/configs/spear300_usbtty_defconfig +++ b/configs/spear300_usbtty_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR300=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR300,USBTTY" CONFIG_BOOTDELAY=-1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear300_usbtty_nand_defconfig b/configs/spear300_usbtty_nand_defconfig index d2cf814..ebe0b7c 100644 --- a/configs/spear300_usbtty_nand_defconfig +++ b/configs/spear300_usbtty_nand_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR300=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR300,USBTTY,NAND" CONFIG_BOOTDELAY=-1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear310_defconfig b/configs/spear310_defconfig index 1b4483d..9b6f777 100644 --- a/configs/spear310_defconfig +++ b/configs/spear310_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR310=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR310" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear310_nand_defconfig b/configs/spear310_nand_defconfig index 6a51538..fa1af53 100644 --- a/configs/spear310_nand_defconfig +++ b/configs/spear310_nand_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR310=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,NAND" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear310_pnor_defconfig b/configs/spear310_pnor_defconfig index f6424f8..2f12f3c 100644 --- a/configs/spear310_pnor_defconfig +++ b/configs/spear310_pnor_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR310=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,FLASH_PNOR" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear310_usbtty_defconfig b/configs/spear310_usbtty_defconfig index f35d363..f4bc118 100644 --- a/configs/spear310_usbtty_defconfig +++ b/configs/spear310_usbtty_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR310=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,USBTTY" CONFIG_BOOTDELAY=-1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear310_usbtty_nand_defconfig b/configs/spear310_usbtty_nand_defconfig index a1f9fbf..342e6a0 100644 --- a/configs/spear310_usbtty_nand_defconfig +++ b/configs/spear310_usbtty_nand_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR310=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,USBTTY,NAND" CONFIG_BOOTDELAY=-1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear310_usbtty_pnor_defconfig b/configs/spear310_usbtty_pnor_defconfig index 4ac4da5..679e5e4 100644 --- a/configs/spear310_usbtty_pnor_defconfig +++ b/configs/spear310_usbtty_pnor_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR310=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR310,USBTTY,FLASH_PNOR" CONFIG_BOOTDELAY=-1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear320_defconfig b/configs/spear320_defconfig index 7b09882..5b4e29c 100644 --- a/configs/spear320_defconfig +++ b/configs/spear320_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR320=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR320" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear320_nand_defconfig b/configs/spear320_nand_defconfig index 53e3f01..bcb5631 100644 --- a/configs/spear320_nand_defconfig +++ b/configs/spear320_nand_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR320=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,NAND" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear320_pnor_defconfig b/configs/spear320_pnor_defconfig index d23eb36..5b2af90 100644 --- a/configs/spear320_pnor_defconfig +++ b/configs/spear320_pnor_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR320=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,FLASH_PNOR" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear320_usbtty_defconfig b/configs/spear320_usbtty_defconfig index 26ca01f..6a16cdb 100644 --- a/configs/spear320_usbtty_defconfig +++ b/configs/spear320_usbtty_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR320=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,USBTTY" CONFIG_BOOTDELAY=-1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear320_usbtty_nand_defconfig b/configs/spear320_usbtty_nand_defconfig index 2478fe0..2a8985c 100644 --- a/configs/spear320_usbtty_nand_defconfig +++ b/configs/spear320_usbtty_nand_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR320=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,USBTTY,NAND" CONFIG_BOOTDELAY=-1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear320_usbtty_pnor_defconfig b/configs/spear320_usbtty_pnor_defconfig index e774225..5578e93 100644 --- a/configs/spear320_usbtty_pnor_defconfig +++ b/configs/spear320_usbtty_pnor_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR320=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR320,USBTTY,FLASH_PNOR" CONFIG_BOOTDELAY=-1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear600_defconfig b/configs/spear600_defconfig index e14dcc0..5617501 100644 --- a/configs/spear600_defconfig +++ b/configs/spear600_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR600=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR600" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/spear600_nand_defconfig b/configs/spear600_nand_defconfig index 6c45fec..2381722 100644 --- a/configs/spear600_nand_defconfig +++ b/configs/spear600_nand_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR600=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,NAND" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear600_usbtty_defconfig b/configs/spear600_usbtty_defconfig index 4531168..c13f7a7 100644 --- a/configs/spear600_usbtty_defconfig +++ b/configs/spear600_usbtty_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR600=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,USBTTY" CONFIG_BOOTDELAY=-1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/spear600_usbtty_nand_defconfig b/configs/spear600_usbtty_nand_defconfig index 968e7e4..313d0d5 100644 --- a/configs/spear600_usbtty_nand_defconfig +++ b/configs/spear600_usbtty_nand_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_SPEAR600=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_SYS_EXTRA_OPTIONS="SPEAR600,USBTTY,NAND" CONFIG_BOOTDELAY=-1 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_CMD_I2C=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y diff --git a/configs/stm32f429-discovery_defconfig b/configs/stm32f429-discovery_defconfig index ae9976b..24e2221 100644 --- a/configs/stm32f429-discovery_defconfig +++ b/configs/stm32f429-discovery_defconfig @@ -3,6 +3,8 @@ CONFIG_STM32=y CONFIG_STM32F4=y CONFIG_TARGET_STM32F429_DISCOVERY=y CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " # CONFIG_CMD_SETEXPR is not set diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index e3e6333..6d71d0a 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -3,6 +3,8 @@ CONFIG_STM32=y CONFIG_STM32F7=y CONFIG_TARGET_STM32F746_DISCO=y CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot > " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/strider_con_defconfig b/configs/strider_con_defconfig index 66a0b97..1a569e1 100644 --- a/configs/strider_con_defconfig +++ b/configs/strider_con_defconfig @@ -8,6 +8,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON" CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/strider_con_dp_defconfig b/configs/strider_con_dp_defconfig index 3482653..2da2bd3 100644 --- a/configs/strider_con_dp_defconfig +++ b/configs/strider_con_dp_defconfig @@ -8,6 +8,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON_DP" CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/strider_cpu_defconfig b/configs/strider_cpu_defconfig index d554b0c..022af1f 100644 --- a/configs/strider_cpu_defconfig +++ b/configs/strider_cpu_defconfig @@ -8,6 +8,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU" CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/strider_cpu_dp_defconfig b/configs/strider_cpu_dp_defconfig index 5394d2f..454c42e 100644 --- a/configs/strider_cpu_dp_defconfig +++ b/configs/strider_cpu_dp_defconfig @@ -8,6 +8,7 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU,STRIDER_CPU_DP" CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_STOP_STR=" " diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index 4db028e..c728182 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_DEFAULT_DEVICE_TREE="stv0991" CONFIG_SYS_EXTRA_OPTIONS="STV0991" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SYS_PROMPT="STV0991> " CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" diff --git a/configs/t3corp_defconfig b/configs/t3corp_defconfig index 3e04031..f0b756d 100644 --- a/configs/t3corp_defconfig +++ b/configs/t3corp_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 17d4a02..ca80bd6 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="at91sam9g20-taurus" CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig index ec6a8f1..ef04911 100644 --- a/configs/theadorable_debug_defconfig +++ b/configs/theadorable_debug_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig index ecba1ec..fd569e5 100644 --- a/configs/theadorable_defconfig +++ b/configs/theadorable_defconfig @@ -12,6 +12,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_FIT=y CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index ba8c673..7b46703 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="am335x-draco" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " diff --git a/configs/thunderx_88xx_defconfig b/configs/thunderx_88xx_defconfig index 9bbff6c..a752b22 100644 --- a/configs/thunderx_88xx_defconfig +++ b/configs/thunderx_88xx_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_THUNDERX_88XX=y CONFIG_IDENT_STRING=" for Cavium Thunder CN88XX ARM v8 Multi-Core" CONFIG_DEFAULT_DEVICE_TREE="thunderx-88xx" CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ThunderX_88XX> " # CONFIG_CMD_IMLS is not set diff --git a/configs/ti814x_evm_defconfig b/configs/ti814x_evm_defconfig index e66ea7d..f7a7305 100644 --- a/configs/ti814x_evm_defconfig +++ b/configs/ti814x_evm_defconfig @@ -10,6 +10,8 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_BOOTDELAY=1 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot# " diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig index 318751c..2d32dd5 100644 --- a/configs/ti816x_evm_defconfig +++ b/configs/ti816x_evm_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot/ti816x# " diff --git a/configs/tplink_wdr4300_defconfig b/configs/tplink_wdr4300_defconfig index 76a615c..8d8908d 100644 --- a/configs/tplink_wdr4300_defconfig +++ b/configs/tplink_wdr4300_defconfig @@ -5,6 +5,7 @@ CONFIG_BOARD_TPLINK_WDR4300=y CONFIG_DEFAULT_DEVICE_TREE="tplink_wdr4300" CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +CONFIG_DISPLAY_CPUINFO=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_ELF is not set # CONFIG_CMD_IMLS is not set diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig index 916a9c6..c640aa7 100644 --- a/configs/usb_a9263_dataflash_defconfig +++ b/configs/usb_a9263_dataflash_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_USB_A9263=y CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="U-Boot> " # CONFIG_CMD_BDI is not set diff --git a/configs/vexpress_aemv8a_dram_defconfig b/configs/vexpress_aemv8a_dram_defconfig index 59fe412..f73179b 100644 --- a/configs/vexpress_aemv8a_dram_defconfig +++ b/configs/vexpress_aemv8a_dram_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="VExpress64# " # CONFIG_CMD_CONSOLE is not set diff --git a/configs/vexpress_aemv8a_juno_defconfig b/configs/vexpress_aemv8a_juno_defconfig index e7a0369..92a4b0b 100644 --- a/configs/vexpress_aemv8a_juno_defconfig +++ b/configs/vexpress_aemv8a_juno_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_VEXPRESS64_JUNO=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="VExpress64# " # CONFIG_CMD_CONSOLE is not set diff --git a/configs/vexpress_aemv8a_semi_defconfig b/configs/vexpress_aemv8a_semi_defconfig index 7e5b53f..a81ea0c 100644 --- a/configs/vexpress_aemv8a_semi_defconfig +++ b/configs/vexpress_aemv8a_semi_defconfig @@ -3,6 +3,8 @@ CONFIG_TARGET_VEXPRESS64_BASE_FVP=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_IDENT_STRING=" vexpress_aemv8a" CONFIG_BOOTDELAY=1 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="VExpress64# " # CONFIG_CMD_CONSOLE is not set diff --git a/configs/vexpress_ca15_tc2_defconfig b/configs/vexpress_ca15_tc2_defconfig index 2f141dd..d795279 100644 --- a/configs/vexpress_ca15_tc2_defconfig +++ b/configs/vexpress_ca15_tc2_defconfig @@ -1,5 +1,8 @@ CONFIG_ARM=y CONFIG_TARGET_VEXPRESS_CA15_TC2=y +CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/vexpress_ca5x2_defconfig b/configs/vexpress_ca5x2_defconfig index c495ee5..38d691e 100644 --- a/configs/vexpress_ca5x2_defconfig +++ b/configs/vexpress_ca5x2_defconfig @@ -1,5 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_VEXPRESS_CA5X2=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig index fcd6e26..ebca526 100644 --- a/configs/vexpress_ca9x4_defconfig +++ b/configs/vexpress_ca9x4_defconfig @@ -1,5 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_VEXPRESS_CA9X4=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_BOOTD is not set diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig index eb2cd79..34a02bd 100644 --- a/configs/vinco_defconfig +++ b/configs/vinco_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_AT91=y CONFIG_TARGET_VINCO=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_SERIALFLASH" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="vinco => " CONFIG_CMD_BOOTZ=y diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig index a2e5957..aa5d587 100644 --- a/configs/woodburn_defconfig +++ b/configs/woodburn_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_TARGET_WOODBURN=y CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="woodburn U-Boot > " CONFIG_CMD_MMC=y diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig index 379d7fa..01aae3b 100644 --- a/configs/woodburn_sd_defconfig +++ b/configs/woodburn_sd_defconfig @@ -8,6 +8,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/woodburn/imximage.cfg" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="woodburn U-Boot > " diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index d5e5b38..ca3b731 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_HUSH_PARSER=y diff --git a/configs/x600_defconfig b/configs/x600_defconfig index 47579a5..a5222b3 100644 --- a/configs/x600_defconfig +++ b/configs/x600_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_IDENT_STRING="-SPEAr" CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/xfi3_defconfig b/configs/xfi3_defconfig index 9f0c378..674c82a 100644 --- a/configs/xfi3_defconfig +++ b/configs/xfi3_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_BOOTDELAY=3 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y # CONFIG_CMD_IMLS is not set diff --git a/configs/xilinx-ppc405-generic_defconfig b/configs/xilinx-ppc405-generic_defconfig index a17cd4f..352b715 100644 --- a/configs/xilinx-ppc405-generic_defconfig +++ b/configs/xilinx-ppc405-generic_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000" CONFIG_BOOTDELAY=5 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="xlx-ppc405:/# " # CONFIG_CMD_IMLS is not set diff --git a/configs/xilinx-ppc440-generic_defconfig b/configs/xilinx-ppc440-generic_defconfig index a9dd5a7..05aa375 100644 --- a/configs/xilinx-ppc440-generic_defconfig +++ b/configs/xilinx-ppc440-generic_defconfig @@ -7,6 +7,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1" CONFIG_BOOTDELAY=5 CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="board:/# " CONFIG_CMD_ASKENV=y diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index 3be5c1b..af0dd1b 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -9,6 +9,8 @@ CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_HUSH_PARSER=y diff --git a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig index 44eaf20..490c3b2 100644 --- a/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig @@ -9,6 +9,8 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm015-dc1" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_HUSH_PARSER=y diff --git a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig index 6fcbaa1..30f4081 100644 --- a/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig @@ -12,6 +12,8 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm016-dc2" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_HUSH_PARSER=y diff --git a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig index c717f04..ec55a6d 100644 --- a/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig @@ -7,6 +7,8 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_HUSH_PARSER=y diff --git a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig index 1a27bd0..f9754b6 100644 --- a/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig +++ b/configs/xilinx_zynqmp_zc1751_xm019_dc5_defconfig @@ -8,6 +8,8 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm019-dc5" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_HUSH_PARSER=y diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig index 3f4b5f9..7134508 100644 --- a/configs/xilinx_zynqmp_zcu102_defconfig +++ b/configs/xilinx_zynqmp_zcu102_defconfig @@ -10,6 +10,8 @@ CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_HUSH_PARSER=y diff --git a/configs/xilinx_zynqmp_zcu102_revB_defconfig b/configs/xilinx_zynqmp_zcu102_revB_defconfig index 2d5fa50..7665543 100644 --- a/configs/xilinx_zynqmp_zcu102_revB_defconfig +++ b/configs/xilinx_zynqmp_zcu102_revB_defconfig @@ -10,6 +10,8 @@ CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_SPL=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_HUSH_PARSER=y diff --git a/configs/zipitz2_defconfig b/configs/zipitz2_defconfig index a776055..d9819a5 100644 --- a/configs/zipitz2_defconfig +++ b/configs/zipitz2_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_TARGET_ZIPITZ2=y +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="$ " # CONFIG_CMD_IMLS is not set diff --git a/configs/zmx25_defconfig b/configs/zmx25_defconfig index 70f47f2..8c46e16 100644 --- a/configs/zmx25_defconfig +++ b/configs/zmx25_defconfig @@ -1,6 +1,8 @@ CONFIG_ARM=y CONFIG_TARGET_ZMX25=y CONFIG_BOOTDELAY=5 +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="zmx25> " CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index ad0da0b..faaf482 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_NO_FLASH=y +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_picozed_defconfig b/configs/zynq_picozed_defconfig index 3142b58..ef37914 100644 --- a/configs/zynq_picozed_defconfig +++ b/configs/zynq_picozed_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_ARCH_ZYNQ=y CONFIG_DEFAULT_DEVICE_TREE="zynq-picozed" CONFIG_SYS_NO_FLASH=y +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zc702_defconfig b/configs/zynq_zc702_defconfig index c4f065f..acbc5a2 100644 --- a/configs/zynq_zc702_defconfig +++ b/configs/zynq_zc702_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_NO_FLASH=y +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index e1db0a7..64d95d9 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_NO_FLASH=y +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zc770_xm010_defconfig b/configs/zynq_zc770_xm010_defconfig index a1a2fe4..bec60cc 100644 --- a/configs/zynq_zc770_xm010_defconfig +++ b/configs/zynq_zc770_xm010_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM010" CONFIG_SYS_NO_FLASH=y +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zc770_xm011_defconfig b/configs/zynq_zc770_xm011_defconfig index b841fdc..489becb 100644 --- a/configs/zynq_zc770_xm011_defconfig +++ b/configs/zynq_zc770_xm011_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011" CONFIG_SYS_NO_FLASH=y +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zc770_xm012_defconfig b/configs/zynq_zc770_xm012_defconfig index 3436c9d..55a7336 100644 --- a/configs/zynq_zc770_xm012_defconfig +++ b/configs/zynq_zc770_xm012_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM012" +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zc770_xm013_defconfig b/configs/zynq_zc770_xm013_defconfig index 7a43e68f..265e641 100644 --- a/configs/zynq_zc770_xm013_defconfig +++ b/configs/zynq_zc770_xm013_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM013" CONFIG_SYS_NO_FLASH=y +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zed_defconfig b/configs/zynq_zed_defconfig index c930b53..93e9f17 100644 --- a/configs/zynq_zed_defconfig +++ b/configs/zynq_zed_defconfig @@ -5,6 +5,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_NO_FLASH=y +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/configs/zynq_zybo_defconfig b/configs/zynq_zybo_defconfig index f2c0f72..8a81ef5 100644 --- a/configs/zynq_zybo_defconfig +++ b/configs/zynq_zybo_defconfig @@ -6,6 +6,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_SYS_NO_FLASH=y +# CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL=y CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="Zynq> " diff --git a/doc/README.JFFS2 b/doc/README.JFFS2 index f0e9bc1..604e5b9 100644 --- a/doc/README.JFFS2 +++ b/doc/README.JFFS2 @@ -19,52 +19,15 @@ more or less a bubble sort. That algorithm is known to be O(n^2), thus you should really consider if you can avoid it! -There is two ways for JFFS2 to find the disk. The default way uses -the flash_info structure to find the start of a JFFS2 disk (called -partition in the code) and you can change where the partition is with -two defines. +There only one way for JFFS2 to find the disk. It uses the flash_info +structure to find the start of a JFFS2 disk (called partition in the code) +and you can change where the partition is with two defines. CONFIG_SYS_JFFS2_FIRST_BANK defined the first flash bank to use CONFIG_SYS_JFFS2_FIRST_SECTOR defines the first sector to use - - -The second way is to define CONFIG_SYS_JFFS_CUSTOM_PART and implement the -jffs2_part_info(int part_num) function in your board specific files. -In this mode CONFIG_SYS_JFFS2_FIRST_BANK and CONFIG_SYS_JFFS2_FIRST_SECTOR is not -used. - -The input is a partition number starting with 0. -Return a pointer to struct part_info or NULL for error; - -Ex jffs2_part_info() for one partition. ---- -#if defined CONFIG_SYS_JFFS_CUSTOM_PART -#include <jffs2/jffs2.h> - -static struct part_info part; - -struct part_info* -jffs2_part_info(int part_num) -{ - if(part_num==0){ - if(part.usr_priv==(void*)1) - return ∂ - - memset(&part, 0, sizeof(part)); - part.offset=(char*)0xFF800000; - part.size=1024*1024*8; - - /* Mark the struct as ready */ - part.usr_priv=(void*)1; - - return ∂ - } - return 0; -} -#endif --- TODO. diff --git a/doc/README.JFFS2_NAND b/doc/README.JFFS2_NAND index 09788d5..92fa0f6 100644 --- a/doc/README.JFFS2_NAND +++ b/doc/README.JFFS2_NAND @@ -2,23 +2,7 @@ JFFS2 NAND support: To enable, use the following #define in the board configuration file: -#define CONFIG_JFFS2_NAND 1 +#define CONFIG_JFFS2_NAND Configuration of partitions is similar to how this is done in U-Boot -for JFFS2 on top NOR flash. If a single partition is used, it can be -configured using the following #defines in the configuration file: - -#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */ -#define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */ -#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */ - -If more than a single partition is desired, the user can define a -CONFIG_SYS_JFFS_CUSTOM_PART macro and implement a - - struct part_info* jffs2_part_info(int part_num) - -function in a board-specific module. An example of such function is -available in common/cmd_jffs2.c - -The default configuration for the DAVE board has a single JFFS2 -partition of 2 MB size. +for JFFS2 on top NOR flash. diff --git a/doc/README.at91-soc b/doc/README.at91-soc deleted file mode 100644 index 9a9f74e..0000000 --- a/doc/README.at91-soc +++ /dev/null @@ -1,48 +0,0 @@ - New C structure AT91 SoC access -================================= - -The goal --------- - -Currently the at91 arch uses hundreds of address defines and special -at91_xxxx_write/read functions to access the SOC. -The u-boot project perferred method is to access memory mapped hw -regisister via a c structure. - -e.g. old - - *AT91C_PIOA_IDR = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; - *AT91C_PIOC_PUDR = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; - *AT91C_PIOC_PER = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; - *AT91C_PIOC_OER = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; - *AT91C_PIOC_PIO = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; - - at91_sys_write(AT91_RSTC_CR, - AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); - -e.g new - pin = AT91_PMX_AA_TWD | AT91_PMX_AA_TWCK; - writel(pin, &pio->pioa.idr); - writel(pin, &pio->pioa.pudr); - writel(pin, &pio->pioa.per); - writel(pin, &pio->pioa.oer); - writel(pin, &pio->pioa.sodr); - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_PROCRST | - AT91_RSTC_CR_PERRST, &rstc->cr); - -The method for updating ------------------------- - -1. add's the temporary CONFIG_AT91_LEGACY to all at91 board configs -2. Display a compile time warning, if the board has not been converted -3. add new structures for SoC access -4. Convert arch, driver and boards file to new SoC -5. remove legacy code, if all boards and drives are ready - -2013-10-30 Andreas Bießmann <andreas@biessmann.org>: - -The goal is almost reached, we could remove the CONFIG_AT91_LEGACY switch but -remain the CONFIG_ATMEL_LEGACY switch until the GPIO disaster is fixed. The -AT91 spi driver has also some CONFIG_ATMEL_LEGACY stuff left, so another point -to fix until this README can be removed. diff --git a/doc/README.imx31 b/doc/README.imx31 deleted file mode 100644 index 91ef766..0000000 --- a/doc/README.imx31 +++ /dev/null @@ -1,29 +0,0 @@ -U-Boot for Freescale i.MX31 - -This file contains information for the port of U-Boot to the Freescale -i.MX31 SoC. - -1. CONFIGURATION OPTIONS/SETTINGS ---------------------------------- - -1.1 Configuration of MC13783 SPI bus ------------------------------------- - The power management companion chip MC13783 is connected to the - i.MX31 via an SPI bus. Use the following configuration options - to setup the bus and chip select used for a particular board. - - CONFIG_MC13783_SPI_BUS -- defines the SPI bus the MC13783 is connected to. - Note that 0 is CSPI1, 1 is CSPI2 and 2 is CSPI3. - CONFIG_MC13783_SPI_CS -- define the chip select the MC13783 s connected to. - -1.2 Timer precision -------------------- - CONFIG_MX31_TIMER_HIGH_PRECISION - - Enable higher precision timer. The low-precision timer - (default) provides approximately 4% error, whereas the - high-precision timer is about 0.4% accurate. The extra - accuracy is achieved at the cost of higher computational - overhead, which, in places where time is measured, should - not be critical, so, it should be safe to enable this - option. diff --git a/doc/README.imx6 b/doc/README.imx6 index 1823fb2..73b8b0b 100644 --- a/doc/README.imx6 +++ b/doc/README.imx6 @@ -91,7 +91,7 @@ Word 0x00000002: 9f027772 00000004 2. Using imx_usb_loader for first install with SPL -------------------------------------------------- -imx_usb_loader is a very nice tool by BoundaryDevice that +imx_usb_loader is a very nice tool by Boundary Devices that allow to install U-Boot without a JTAG debugger, using the USB boot mode as described in the manual. It is a replacement for Freescale's MFGTOOLS. diff --git a/doc/README.mpc83xxads b/doc/README.mpc83xxads index 7a8b706..372fdd9 100644 --- a/doc/README.mpc83xxads +++ b/doc/README.mpc83xxads @@ -50,7 +50,6 @@ Freescale MPC83xx ADS Boards CONFIG_MPC83xx MPC83xx family CONFIG_MPC8349 MPC8349 specific - CONFIG_MPC8349ADS MPC8349ADS board specific CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet diff --git a/doc/README.nand b/doc/README.nand index f1c20ff..2295bb2 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -160,7 +160,7 @@ Configuration Options: /* * devnum is the device number to be used in nand commands - * and in mtd->name. Must be less than CONFIG_SYS_NAND_MAX_DEVICE. + * and in mtd->name. Must be less than CONFIG_SYS_MAX_NAND_DEVICE. */ if (nand_register(devnum, mtd)) error out diff --git a/doc/device-tree-bindings/pmic/rn5t567.txt b/doc/device-tree-bindings/pmic/rn5t567.txt new file mode 100644 index 0000000..e9e6885 --- /dev/null +++ b/doc/device-tree-bindings/pmic/rn5t567.txt @@ -0,0 +1,17 @@ +Ricoh RN5T567 PMIC + +This file describes the binding info for the PMIC driver. + +Required properties: +- compatible: "ricoh,rn5t567" +- reg: depending on strapping, e.g. 0x33 + +With those two properties, the PMIC device can be used to read/write +registers. + +Example: + +rn5t567@33 { + compatible = "ricoh,rn5t567"; + reg = <0x33>; +}; diff --git a/doc/device-tree-bindings/serial/mxc-serial.txt b/doc/device-tree-bindings/serial/mxc-serial.txt new file mode 100644 index 0000000..ede92a4 --- /dev/null +++ b/doc/device-tree-bindings/serial/mxc-serial.txt @@ -0,0 +1,8 @@ +NXP i.MX (MXC) UART + +Required properties: +- compatible: must be "fsl,imx7d-uart" +- reg: start address and size of the registers + +Optional properties: +- fsl,dte-mode: use DTE mode diff --git a/doc/mkimage.1 b/doc/mkimage.1 index ffa7d60..e883f07 100644 --- a/doc/mkimage.1 +++ b/doc/mkimage.1 @@ -70,7 +70,7 @@ Set compression type. Pass \-h as the compression to see the list of supported compression type. .TP -.BI "\-a [" "load addess" "]" +.BI "\-a [" "load address" "]" Set load address with a hex number. .TP diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index 5752fee..ba18135 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -41,7 +41,7 @@ * to the 256 byte-"opcodes" found on the 8086. The table which * dispatches this is found in the files optab.[ch]. * -* Each opcode proc has a comment preceeding it which gives it's table +* Each opcode proc has a comment preceding it which gives it's table * address. Several opcodes are missing (undefined) in the table. * * Each proc includes information for decoding (DECODE_PRINTF and diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index fd0c4f7..6125bbb 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -41,7 +41,7 @@ uint32_t secmem_set_cmd(uint32_t sec_mem_cmd) /*! * CAAM page allocation: * Allocates a partition from secure memory, with the id - * equal to partion_num. This will de-allocate the page + * equal to partition_num. This will de-allocate the page * if it is already allocated. The partition will have * full access permissions. The permissions are set before, * running a job descriptor. A memory page of secure RAM diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index 80ef050..7e0749f 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -1302,7 +1302,7 @@ int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, } if (mem_mask != 0) { - /* motib redundent in KW28 */ + /* motib redundant in KW28 */ CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, CS_ENABLE_REG, 0, 0x8)); diff --git a/drivers/i2c/cros_ec_tunnel.c b/drivers/i2c/cros_ec_tunnel.c index e2c6e44..9cf8e7d 100644 --- a/drivers/i2c/cros_ec_tunnel.c +++ b/drivers/i2c/cros_ec_tunnel.c @@ -11,6 +11,12 @@ #include <errno.h> #include <i2c.h> +DECLARE_GLOBAL_DATA_PTR; + +struct cros_ec_i2c_bus { + int remote_bus; +}; + static int cros_ec_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) { return 0; @@ -19,7 +25,21 @@ static int cros_ec_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) static int cros_ec_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) { - return cros_ec_i2c_tunnel(dev->parent, msg, nmsgs); + struct cros_ec_i2c_bus *i2c_bus = dev_get_priv(dev); + + return cros_ec_i2c_tunnel(dev->parent, i2c_bus->remote_bus, msg, nmsgs); +} + +static int cros_ec_i2c_ofdata_to_platdata(struct udevice *dev) +{ + struct cros_ec_i2c_bus *i2c_bus = dev_get_priv(dev); + const void *blob = gd->fdt_blob; + int node = dev->of_offset; + + i2c_bus->remote_bus = fdtdec_get_uint(blob, node, "google,remote-bus", + 0); + + return 0; } static const struct dm_i2c_ops cros_ec_i2c_ops = { @@ -36,5 +56,7 @@ U_BOOT_DRIVER(cros_ec_tunnel) = { .name = "cros_ec_tunnel", .id = UCLASS_I2C, .of_match = cros_ec_i2c_ids, + .ofdata_to_platdata = cros_ec_i2c_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct cros_ec_i2c_bus), .ops = &cros_ec_i2c_ops, }; diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index 9378e96..5225cdb 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -1058,7 +1058,8 @@ int cros_ec_decode_ec_flash(const void *blob, int node, return 0; } -int cros_ec_i2c_tunnel(struct udevice *dev, struct i2c_msg *in, int nmsgs) +int cros_ec_i2c_tunnel(struct udevice *dev, int port, struct i2c_msg *in, + int nmsgs) { struct cros_ec_dev *cdev = dev_get_uclass_priv(dev); union { @@ -1078,7 +1079,7 @@ int cros_ec_i2c_tunnel(struct udevice *dev, struct i2c_msg *in, int nmsgs) int rv; int i; - p->port = 0; + p->port = port; p->num_msgs = nmsgs; size = sizeof(*p) + p->num_msgs * sizeof(*msg); diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 6b8566c..8a100c1 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -18,6 +18,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <asm/imx-common/sys_proto.h> #define BO_CTRL_WR_UNLOCK 16 #define BM_CTRL_WR_UNLOCK 0xffff0000 @@ -61,6 +62,8 @@ #define FUSE_BANK_SIZE 0x80 #ifdef CONFIG_MX6SL #define FUSE_BANKS 8 +#elif defined(CONFIG_MX6ULL) +#define FUSE_BANKS 9 #else #define FUSE_BANKS 16 #endif @@ -72,11 +75,11 @@ #endif #if defined(CONFIG_MX6) -#include <asm/arch/sys_proto.h> /* * There is a hole in shadow registers address map of size 0x100 - * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL. + * between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX, + * iMX6UL and i.MX6ULL. * Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, * we should account for this hole in address space. * @@ -97,7 +100,10 @@ u32 fuse_bank_physical(int index) if (is_mx6sl()) { phy_index = index; - } else if (is_mx6ul()) { + } else if (is_mx6ul() || is_mx6ull()) { + if (is_mx6ull() && index == 8) + index = 7; + if (index >= 6) phy_index = fuse_bank_physical(5) + (index - 6) + 3; else @@ -112,11 +118,27 @@ u32 fuse_bank_physical(int index) } return phy_index; } + +u32 fuse_word_physical(u32 bank, u32 word_index) +{ + if (is_mx6ull()) { + if (bank == 8) + word_index = word_index + 4; + } + + return word_index; +} #else u32 fuse_bank_physical(int index) { return index; } + +u32 fuse_word_physical(u32 bank, u32 word_index) +{ + return word_index; +} + #endif static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us) @@ -142,6 +164,14 @@ static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word, return -EINVAL; } + if (is_mx6ull()) { + if ((bank == 7 || bank == 8) && + word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 3) { + printf("mxc_ocotp %s(): Invalid argument on 6ULL\n", caller); + return -EINVAL; + } + } + enable_ocotp_clk(1); wait_busy(*regs, 1); @@ -176,14 +206,16 @@ int fuse_read(u32 bank, u32 word, u32 *val) struct ocotp_regs *regs; int ret; u32 phy_bank; + u32 phy_word; ret = prepare_read(®s, bank, word, val, __func__); if (ret) return ret; phy_bank = fuse_bank_physical(bank); + phy_word = fuse_word_physical(bank, word); - *val = readl(®s->bank[phy_bank].fuse_regs[word << 2]); + *val = readl(®s->bank[phy_bank].fuse_regs[phy_word << 2]); return finish_access(regs, __func__); } @@ -237,7 +269,13 @@ static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, #ifdef CONFIG_MX7 u32 addr = bank; #else - u32 addr = bank << 3 | word; + u32 addr; + /* Bank 7 and Bank 8 only supports 4 words each for i.MX6ULL */ + if ((is_mx6ull()) && (bank > 7)) { + bank = bank - 1; + word += 4; + } + addr = bank << 3 | word; #endif set_timing(regs); @@ -325,14 +363,16 @@ int fuse_override(u32 bank, u32 word, u32 val) struct ocotp_regs *regs; int ret; u32 phy_bank; + u32 phy_word; ret = prepare_write(®s, bank, word, __func__); if (ret) return ret; phy_bank = fuse_bank_physical(bank); + phy_word = fuse_word_physical(bank, word); - writel(val, ®s->bank[phy_bank].fuse_regs[word << 2]); + writel(val, ®s->bank[phy_bank].fuse_regs[phy_word << 2]); return finish_access(regs, __func__); } diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 18351fb..d850758 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -60,6 +60,7 @@ obj-$(CONFIG_ROCKCHIP_SDHCI) += rockchip_sdhci.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o +obj-$(CONFIG_SPL_SAVEENV) += mmc_write.o else obj-$(CONFIG_GENERIC_MMC) += mmc_write.o endif diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 103b32e..9796d39 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1010,6 +1010,7 @@ static int fsl_esdhc_probe(struct udevice *dev) } upriv->mmc = priv->mmc; + priv->mmc->dev = dev; return 0; } diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h index 49ec022..d8b399e 100644 --- a/drivers/mmc/mmc_private.h +++ b/drivers/mmc/mmc_private.h @@ -28,8 +28,7 @@ ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, void *dst); #endif -#ifndef CONFIG_SPL_BUILD - +#if !(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_SAVEENV)) unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt); @@ -41,9 +40,9 @@ ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, const void *src); #endif -#else /* CONFIG_SPL_BUILD */ +#else /* CONFIG_SPL_BUILD and CONFIG_SPL_SAVEENV is not defined */ -/* SPL will never write or erase, declare dummies to reduce code size. */ +/* declare dummies to reduce code size. */ #ifdef CONFIG_BLK static inline unsigned long mmc_berase(struct udevice *dev, diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 6f47a66..f3dc409 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -8,7 +8,6 @@ obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o obj-$(CONFIG_SPL_SPI_SUNXI) += sunxi_spi_spl.o endif diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c index b915469..1dd44e2 100644 --- a/drivers/mtd/spi/fsl_espi_spl.c +++ b/drivers/mtd/spi/fsl_espi_spl.c @@ -12,7 +12,7 @@ #define ESPI_BOOT_IMAGE_ADDR 0x50 #define CONFIG_CFG_DATA_SECTOR 0 -void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst) +void fsl_spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst) { struct spi_flash *flash; @@ -31,7 +31,7 @@ void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst) * configured and available since this code loads the main U-Boot image * from SPI into SDRAM and starts it from there. */ -void spi_boot(void) +void fsl_spi_boot(void) { void (*uboot)(void) __noreturn; u32 offset, code_len, copy_len = 0; diff --git a/drivers/mtd/spi/sunxi_spi_spl.c b/drivers/mtd/spi/sunxi_spi_spl.c index e3ded5b..67c7edd 100644 --- a/drivers/mtd/spi/sunxi_spi_spl.c +++ b/drivers/mtd/spi/sunxi_spi_spl.c @@ -262,7 +262,8 @@ static void spi0_read_data(void *buf, u32 addr, u32 len) /*****************************************************************************/ -int spl_spi_load_image(void) +static int spl_spi_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) { int err; struct image_header *header; @@ -271,13 +272,15 @@ int spl_spi_load_image(void) spi0_init(); spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40); - err = spl_parse_image_header(header); + err = spl_parse_image_header(spl_image, header); if (err) return err; - spi0_read_data((void *)spl_image.load_addr, CONFIG_SYS_SPI_U_BOOT_OFFS, - spl_image.size); + spi0_read_data((void *)spl_image->load_addr, CONFIG_SYS_SPI_U_BOOT_OFFS, + spl_image->size); spi0_deinit(); return 0; } +/* Use priorty 0 to override the default if it happens to be linked in */ +SPL_LOAD_IMAGE_METHOD(0, BOOT_DEVICE_SPI, spl_spi_load_image); diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index b718481..ca11396 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -899,7 +899,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) * current transfer) have got the time to arrived before * netloop calls eth_halt */ - printf ("About preceeding transfer (eth%d):\n" + printf ("About preceding transfer (eth%d):\n" "- Sent packet number %d\n" "- Received packet number %d\n" "- Handled packet number %d\n", diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index 40b0616..949d0f3 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -222,7 +222,7 @@ int imx_pinctrl_probe(struct udevice *dev, return -ENOMEM; } - dev_info(dev, "initialized IMX pinctrl driver\n"); + dev_dbg(dev, "initialized IMX pinctrl driver\n"); return 0; } diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c index 24f139e..32b4754 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx6.c +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c @@ -12,6 +12,10 @@ static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info; +static struct imx_pinctrl_soc_info imx6_snvs_pinctrl_soc_info = { + .flags = ZERO_OFFSET_VALID, +}; + static int imx6_pinctrl_probe(struct udevice *dev) { struct imx_pinctrl_soc_info *info = @@ -26,6 +30,7 @@ static const struct udevice_id imx6_pinctrl_match[] = { { .compatible = "fsl,imx6sl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, { .compatible = "fsl,imx6sx-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, { .compatible = "fsl,imx6ul-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, + { .compatible = "fsl,imx6ull-iomuxc-snvs", .data = (ulong)&imx6_snvs_pinctrl_soc_info }, { /* sentinel */ } }; diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 69f8d51..13d293a 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -127,6 +127,14 @@ config PMIC_S5M8767 driver provides basic register access and sets up the attached regulators if regulator support is enabled. +config PMIC_RN5T567 + bool "Enable driver for Ricoh RN5T567 PMIC" + depends on DM_PMIC + ---help--- + The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO + regulators Real-Time Clock and 4 GPIOs. This driver provides + register access only. + config PMIC_TPS65090 bool "Enable driver for Texas Instruments TPS65090 PMIC" depends on DM_PMIC diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 52b4f71..37d9eb5 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o obj-$(CONFIG_PMIC_ACT8846) += act8846.o obj-$(CONFIG_PMIC_PM8916) += pm8916.o obj-$(CONFIG_PMIC_RK808) += rk808.o +obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o obj-$(CONFIG_PMIC_TPS65090) += tps65090.o obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o diff --git a/drivers/power/pmic/rn5t567.c b/drivers/power/pmic/rn5t567.c new file mode 100644 index 0000000..001e695 --- /dev/null +++ b/drivers/power/pmic/rn5t567.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2016 Toradex AG + * Stefan Agner <stefan.agner@toradex.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <power/rn5t567_pmic.h> +#include <power/pmic.h> + +static int rn5t567_reg_count(struct udevice *dev) +{ + return RN5T567_NUM_OF_REGS; +} + +static int rn5t567_write(struct udevice *dev, uint reg, const uint8_t *buff, + int len) +{ + int ret; + + ret = dm_i2c_write(dev, reg, buff, len); + if (ret) { + debug("write error to device: %p register: %#x!", dev, reg); + return ret; + } + + return 0; +} + +static int rn5t567_read(struct udevice *dev, uint reg, uint8_t *buff, int len) +{ + int ret; + + ret = dm_i2c_read(dev, reg, buff, len); + if (ret) { + debug("read error from device: %p register: %#x!", dev, reg); + return ret; + } + + return 0; +} + +static struct dm_pmic_ops rn5t567_ops = { + .reg_count = rn5t567_reg_count, + .read = rn5t567_read, + .write = rn5t567_write, +}; + +static const struct udevice_id rn5t567_ids[] = { + { .compatible = "ricoh,rn5t567" }, + { } +}; + +U_BOOT_DRIVER(pmic_rn5t567) = { + .name = "rn5t567 pmic", + .id = UCLASS_PMIC, + .of_match = rn5t567_ids, + .ops = &rn5t567_ops, +}; diff --git a/drivers/pwm/pwm-imx-util.c b/drivers/pwm/pwm-imx-util.c index f92c370..285564a 100644 --- a/drivers/pwm/pwm-imx-util.c +++ b/drivers/pwm/pwm-imx-util.c @@ -2,7 +2,7 @@ * (C) Copyright 2014 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * Basic support for the pwm modul on imx6. + * Basic support for the pwm module on imx6. * * Based on linux:drivers/pwm/pwm-imx.c * from diff --git a/drivers/pwm/pwm-imx-util.h b/drivers/pwm/pwm-imx-util.h index 45465c4..5c18651 100644 --- a/drivers/pwm/pwm-imx-util.h +++ b/drivers/pwm/pwm-imx-util.h @@ -2,7 +2,7 @@ * (C) Copyright 2014 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * Basic support for the pwm modul on imx6. + * Basic support for the pwm module on imx6. * * SPDX-License-Identifier: GPL-2.0 */ diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c index 47799fc..3f808f9 100644 --- a/drivers/pwm/pwm-imx.c +++ b/drivers/pwm/pwm-imx.c @@ -2,7 +2,7 @@ * (C) Copyright 2014 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * - * Basic support for the pwm modul on imx6. + * Basic support for the pwm module on imx6. * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 765499d..6e9b946 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -13,7 +13,6 @@ #include <serial.h> #include <watchdog.h> #include <linux/types.h> -#include <linux/compiler.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -354,8 +353,8 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) { struct ns16550_platdata *plat = dev->platdata; fdt_addr_t addr; - __maybe_unused struct clk clk; - __maybe_unused int err; + struct clk clk; + int err; /* try Processor Local Bus device first */ addr = dev_get_addr(dev); @@ -402,17 +401,15 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg-shift", 0); -#ifdef CONFIG_CLK err = clk_get_by_index(dev, 0, &clk); if (!err) { err = clk_get_rate(&clk); if (!IS_ERR_VALUE(err)) plat->clock = err; - } else if (err != -ENODEV && err != -ENOSYS) { + } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { debug("ns16550 failed to get clock\n"); return err; } -#endif if (!plat->clock) plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 8545714..4fd2b1d 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -108,6 +108,8 @@ #define UTS_RXFULL (1<<3) /* RxFIFO full */ #define UTS_SOFTRST (1<<0) /* Software reset */ +DECLARE_GLOBAL_DATA_PTR; + #ifndef CONFIG_DM_SERIAL #ifndef CONFIG_MXC_UART_BASE @@ -135,8 +137,6 @@ #define UBRC 0xac /* Baud Rate Count Register */ #define UTS 0xb4 /* UART Test Register (mx31) */ -DECLARE_GLOBAL_DATA_PTR; - #define TXTL 2 /* reset default */ #define RXTL 1 /* reset default */ #define RFDIV 4 /* divide input clock by 2 */ @@ -347,9 +347,37 @@ static const struct dm_serial_ops mxc_serial_ops = { .setbrg = mxc_serial_setbrg, }; +#if CONFIG_IS_ENABLED(OF_CONTROL) +static int mxc_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct mxc_serial_platdata *plat = dev->platdata; + fdt_addr_t addr; + + addr = dev_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->reg = (struct mxc_uart *)addr; + + plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, + "fsl,dte-mode"); + return 0; +} + +static const struct udevice_id mxc_serial_ids[] = { + { .compatible = "fsl,imx7d-uart" }, + { } +}; +#endif + U_BOOT_DRIVER(serial_mxc) = { .name = "serial_mxc", .id = UCLASS_SERIAL, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .of_match = mxc_serial_ids, + .ofdata_to_platdata = mxc_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct mxc_serial_platdata), +#endif .probe = mxc_serial_probe, .ops = &mxc_serial_ops, .flags = DM_FLAG_PRE_RELOC, diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index c8dcb27..f213587 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -594,7 +594,7 @@ static int fsl_dspi_claim_bus(struct udevice *dev) priv = dev_get_priv(bus); - /* processor special prepartion work */ + /* processor special preparation work */ cpu_dspi_claim_bus(bus->seq, slave_plat->cs); /* configure transfer mode */ diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 2938d9f..3f826d1 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -34,7 +34,7 @@ void hw_watchdog_init(void) #endif timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | - SET_WCR_WT(timeout), &wdog->wcr); + WCR_WDA | SET_WCR_WT(timeout), &wdog->wcr); hw_watchdog_reset(); } #endif diff --git a/include/clk.h b/include/clk.h index fe1f892..5a5c2ff 100644 --- a/include/clk.h +++ b/include/clk.h @@ -98,6 +98,19 @@ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk); * @return 0 if OK, or a negative error code. */ int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk); +#else +static inline int clk_get_by_index(struct udevice *dev, int index, + struct clk *clk) +{ + return -ENOSYS; +} + +static inline int clk_get_by_name(struct udevice *dev, const char *name, + struct clk *clk) +{ + return -ENOSYS; +} +#endif /** * clk_request - Request a clock by provider-specific ID. @@ -162,17 +175,5 @@ int clk_enable(struct clk *clk); int clk_disable(struct clk *clk); int soc_clk_dump(void); -#else -static inline int clk_get_by_index(struct udevice *dev, int index, - struct clk *clk) -{ - return -ENOSYS; -} -static inline int clk_get_by_name(struct udevice *dev, const char *name, - struct clk *clk) -{ - return -ENOSYS; -} -#endif #endif diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index ebe018a..2e5d6f7 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -12,7 +12,6 @@ /* * BOARD/CPU */ -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO_LATE /* diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index b2126a6..965ebc3 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -12,7 +12,6 @@ /* * BOARD/CPU */ -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO_LATE /* diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 8710307..3ec1c2a 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* * B4860 QDS board configuration file */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h index 92c69e5..81021ba 100644 --- a/include/configs/BSC9131RDB.h +++ b/include/configs/BSC9131RDB.h @@ -11,8 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - #ifdef CONFIG_BSC9131RDB #define CONFIG_BSC9131 #define CONFIG_NAND_FSL_IFC diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index 4276f65..6c5c172 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -11,8 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - #ifdef CONFIG_BSC9132QDS #define CONFIG_BSC9132 #endif diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index a61e25c..a909611 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -11,8 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - #ifdef CONFIG_C29XPCIE #define CONFIG_PPC_C29X #endif diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 603de33..2e9512a 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -20,7 +20,6 @@ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index afaf739..6232059 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -23,7 +23,6 @@ #undef CONFIG_CPCI405_6U /* enable this for 6U boards */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 599ffc7..6a55e57 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -20,8 +20,6 @@ */ #define CONFIG_M54451EVB /* M54451EVB board */ -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 8301c46..c7a9e13 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -20,8 +20,6 @@ */ #define CONFIG_M54455EVB /* M54455EVB board */ -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index a3834f0..be863ec 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -19,8 +19,6 @@ * (easy to change) */ -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index c94580e..cb2ef75 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -19,8 +19,6 @@ * (easy to change) */ -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 5b80464..c72d36a 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 90b1429..74a4c88 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 9f3dc49..92b93cc 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 095c0d8..fea5472 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 18418e3..5881e1f 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index a2fa783..7b6e8c2 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 177718e..c2f79a3 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -40,8 +40,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) #define CONFIG_SYS_LOWBOOT #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index dd2aa04..0f3e01d 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -8,8 +8,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index e010bd6..c109488 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -15,7 +15,6 @@ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XERDB 1 -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0xFE000000 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 3918160..2fe8483 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -11,7 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_SDCARD diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index fae4b0c..d568107 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -18,8 +18,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 0c2afb5..5abf0f2 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index d8dda87..c8fec70 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -11,8 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 789c62b..275c26e 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index fcd55c7..b0a343d 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 4ed06c9..2938a39 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -18,8 +18,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 39459de..de2b4d8 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 192cc2c..a40ce90 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index e063c7a..e4d55d0 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -11,8 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - #include "../board/freescale/common/ics307_clk.h" #ifndef CONFIG_SYS_TEXT_BASE diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index c1b9b6e..26f8d91 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -11,8 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* High Level Configuration Options */ #define CONFIG_MPC8610 1 /* MPC8610 specific */ #define CONFIG_MPC8610HPCD 1 /* MPC8610HPCD board specific */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 1885124..bcbccd8 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -16,8 +16,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* High Level Configuration Options */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index ab8993b..efdffc4 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -11,8 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_P1010 #define CONFIG_E500 /* BOOKE e500 family */ #include <asm/config_mpc85xx.h> diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 41e3ee8..9820eca 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -11,8 +11,6 @@ #include "../board/freescale/common/ics307_clk.h" -#define CONFIG_DISPLAY_BOARDINFO - #ifdef CONFIG_SDCARD #define CONFIG_SPL_MMC_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index c01e72d..1ae1471 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 3c3504b..814aba4 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -12,7 +12,6 @@ #define __CONFIG_H #define CONFIG_P2041RDB -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_PPC_P2041 #ifdef CONFIG_RAMBOOT_PBL diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 53e51e5..e49e5ce 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -21,7 +21,6 @@ #define CONFIG_PLU405 1 /* ...on a PLU405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFF80000 -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 0b0db20..d5e521e 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -12,7 +12,6 @@ #define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC0000 -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 956c787..b765fac 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -29,8 +29,6 @@ #define CONFIG_SYS_TEXT_BASE 0xFFF90000 #endif -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_SYS_CLK_FREQ 33333400 #if 0 /* temporary disabled because OS/9 does not like dcache on startup */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index f7f0acb..f24e902 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -12,7 +12,6 @@ #define __T1024QDS_H /* High Level Configuration Options */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e61c80d..b457184 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -12,7 +12,6 @@ #define __T1024RDB_H /* High Level Configuration Options */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_E500MC /* BOOKE e500mc family */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 9488db2..c2d0fac 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -27,7 +27,6 @@ * T1040 QDS board configuration file */ #define CONFIG_T1040QDS -#define CONFIG_DISPLAY_BOARDINFO #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 02633b6..5629584 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -11,7 +11,6 @@ * T104x RDB board configuration file */ #define CONFIG_T104xRDB -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_E500 /* BOOKE e500 family */ #include <asm/config_mpc85xx.h> diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 1c7b59c..f654e2c 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -11,7 +11,6 @@ #ifndef __T208xQDS_H #define __T208xQDS_H -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #define CONFIG_MMC #define CONFIG_USB_EHCI diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 7879eb3..cae6a3d 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -11,7 +11,6 @@ #ifndef __T2080RDB_H #define __T2080RDB_H -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_T2080RDB #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #define CONFIG_MMC diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 92b401d..a0580a8 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -11,7 +11,6 @@ #define __CONFIG_H #define CONFIG_T4240RDB -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE4 diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 14e06fb..df12dc1 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -19,7 +19,6 @@ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ -#define CONFIG_DISPLAY_BOARDINFO /* * Valid values for CONFIG_SYS_TEXT_BASE are: diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index c557ba1..2fd5fa3 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -19,7 +19,6 @@ #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ #define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 814740b..11bba09 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -19,7 +19,6 @@ #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ #define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 90e8dd9..85cef31 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -12,8 +12,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 58fd8a4..548f1bc 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -19,7 +19,6 @@ #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ #define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index 3a4f94c..582b934 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -19,7 +19,6 @@ #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ #define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 134076c..814290f 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -19,7 +19,6 @@ #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ #define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index ad6f8f4..4a657ff 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -19,7 +19,6 @@ #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index b935f31..bdfe509 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -19,7 +19,6 @@ #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ #define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 79248de..ce6b404 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -19,7 +19,6 @@ #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ #define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index d360644..66dbcb6 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -20,7 +20,6 @@ #define CONFIG_MPC860 1 #define CONFIG_MPC860T 1 #define CONFIG_MPC862 1 -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 5c6013b..478f16b 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -20,7 +20,6 @@ #define CONFIG_MPC860 1 #define CONFIG_MPC860T 1 #define CONFIG_MPC862 1 -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index c098f72..5501622 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -19,7 +19,6 @@ #define CONFIG_MPC866 1 /* This is a MPC866 CPU */ #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index 9d8a607..b246926 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -22,7 +22,6 @@ #define CONFIG_MPC885 1 /* This is a MPC885 CPU */ #define CONFIG_TQM885D 1 /* ...on a TQM88D module */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h index 57748b4..d62c9b3 100644 --- a/include/configs/UCP1020.h +++ b/include/configs/UCP1020.h @@ -14,8 +14,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_FSL_ELBC #define CONFIG_PCI #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 913b099..e012417 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -135,9 +135,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ -#define CONFIG_DISPLAY_BOARDINFO /* Display board info */ - #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */ diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 5e30511..fc6cf78 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -19,7 +19,6 @@ #define CONFIG_VOM405 1 /* ...on a VOM405 board */ #define CONFIG_SYS_TEXT_BASE 0xFFFC8000 -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h index cc211c5..1919475 100644 --- a/include/configs/a3m071.h +++ b/include/configs/a3m071.h @@ -14,7 +14,6 @@ #define CONFIG_MPC5200 #define CONFIG_A3M071 /* A3M071 board */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */ diff --git a/include/configs/a4m072.h b/include/configs/a4m072.h index bdc81ff..b5be7b2 100644 --- a/include/configs/a4m072.h +++ b/include/configs/a4m072.h @@ -19,7 +19,6 @@ #define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_A4M072 1 /* ... on A4M072 board */ #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0xFE000000 diff --git a/include/configs/ac14xx.h b/include/configs/ac14xx.h index 699ac41..b18ee91 100644 --- a/include/configs/ac14xx.h +++ b/include/configs/ac14xx.h @@ -13,7 +13,6 @@ #define __CONFIG_H #define CONFIG_AC14XX 1 -#define CONFIG_DISPLAY_BOARDINFO /* * Memory map for the ifm AC14xx board: diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h index 992948a..14a7c9d 100644 --- a/include/configs/advantech_dms-ba16.h +++ b/include/configs/advantech_dms-ba16.h @@ -28,9 +28,6 @@ #include "mx6_common.h" #include <linux/sizes.h> -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 698c924..1379795 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -29,12 +29,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap.h> -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index e18e39a..cc89a16 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -42,9 +42,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap.h> -/* Display CPU and Board information */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_R #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/ap121.h b/include/configs/ap121.h index bf5746f..2da520e 100644 --- a/include/configs/ap121.h +++ b/include/configs/ap121.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/ap143.h b/include/configs/ap143.h index 5d7e49e..ce64c94 100644 --- a/include/configs/ap143.h +++ b/include/configs/ap143.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/apf27.h b/include/configs/apf27.h index 79366be..b903ba5 100644 --- a/include/configs/apf27.h +++ b/include/configs/apf27.h @@ -25,12 +25,6 @@ #define CONFIG_SYS_NO_FLASH /* - * Board display option - */ -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_DISPLAY_CPUINFO - -/* * SPL */ #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h index 80049f7..babaf26 100644 --- a/include/configs/apx4devkit.h +++ b/include/configs/apx4devkit.h @@ -21,7 +21,6 @@ /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION #define CONFIG_CMD_DATE diff --git a/include/configs/aria.h b/include/configs/aria.h index cb50658..278676e 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -13,7 +13,6 @@ #define __CONFIG_H #define CONFIG_ARIA 1 -#define CONFIG_DISPLAY_BOARDINFO /* * Memory map for the ARIA board: diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index e3f4a7b..e616da4 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -27,8 +27,6 @@ #undef CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_USE_ARCH_MEMSET #define CONFIG_USE_ARCH_MEMCPY diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 051186d..b09ef33 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -25,7 +25,6 @@ #endif #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_ENV_VARS_UBOOT_CONFIG diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index fab0374..e1f934c 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -43,7 +43,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 867bd69..5496a9f 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -29,8 +29,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_DISPLAY_CPUINFO - #define CONFIG_ATMEL_LEGACY #define CONFIG_SYS_TEXT_BASE 0x21f00000 diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 854caf3..98a0588 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -43,8 +43,6 @@ #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO - /* * Hardware drivers */ diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 9968b14..6874608 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -28,7 +28,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index c3d07a1..403a207 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -28,7 +28,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO /* general purpose I/O */ #define CONFIG_AT91_GPIO diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index a383de6..c55c965 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -29,8 +29,6 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 -#define CONFIG_DISPLAY_CPUINFO - #define CONFIG_ATMEL_LEGACY #define CONFIG_AT91_GPIO 1 #define CONFIG_AT91_GPIO_PULLUP 1 diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index edad1dd..04c41cc 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -24,7 +24,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h index e13f736..57a6985 100644 --- a/include/configs/bg0900.h +++ b/include/configs/bg0900.h @@ -11,7 +11,6 @@ /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION #define CONFIG_CMD_NAND diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h new file mode 100644 index 0000000..5861eeb --- /dev/null +++ b/include/configs/bk4r1.h @@ -0,0 +1,33 @@ +/* + * Copyright 2016 3ADEV <http://3adev.com> + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * Configuration settings for the phytec PCM-052 SoM-based BK4R1. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Define the BK4r1-specific env commands */ +#define PCM052_EXTRA_ENV_SETTINGS \ + "set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \ + "set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0" + +/* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/ +#define PCM052_BOOTCOMMAND "run set_gpio103; sf probe; " + +/* BK4r1 net init sets GPIO122/PTE17 to enable Ethernet */ +#define PCM052_NET_INIT "run set_gpio122; " + +/* add NOR to MTD env */ +#define MTDIDS_DEFAULT "nand0=NAND,nor0=NOR" +#define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\ + ",128k(env1)"\ + ",128k(env2)"\ + ",128k(dtb)"\ + ",6144k(kernel)"\ + ",-(root);"\ + "NOR:-(nor)" + +/* now include standard PCM052 config */ + +#include "configs/pcm052.h" diff --git a/include/configs/boston.h b/include/configs/boston.h index e958054..516fd04 100644 --- a/include/configs/boston.h +++ b/include/configs/boston.h @@ -8,11 +8,6 @@ #define __CONFIGS_BOSTON_H__ /* - * General board configuration - */ -#define CONFIG_DISPLAY_BOARDINFO - -/* * CPU */ #define CONFIG_SYS_MIPS_TIMER_FREQ 30000000 diff --git a/include/configs/canmb.h b/include/configs/canmb.h index b416660..684695f 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -15,7 +15,6 @@ #define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */ -#define CONFIG_DISPLAY_BOARDINFO /* * allowed and functional CONFIG_SYS_TEXT_BASE values: diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index 065e700..a054faf 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -8,8 +8,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options */ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index e4c9358..07f0c41 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -36,12 +36,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap.h> -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) diff --git a/include/configs/cm_t3517.h b/include/configs/cm_t3517.h index a408fbf..3f8c7be 100644 --- a/include/configs/cm_t3517.h +++ b/include/configs/cm_t3517.h @@ -36,12 +36,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517 -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index 16ae952..55d8fcf 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -59,9 +59,7 @@ #undef CONFIG_BOOTM_RTEMS /* I2C configs */ -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_IPADDR 192.168.10.2 diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 597eb2c..be773a3 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -21,8 +21,6 @@ #define CONFIG_SYS_FSL_CLK #define CONFIG_ARCH_MISC_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SKIP_LOWLEVEL_INIT diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index c598300..5353258 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_RAMBOOT_PBL diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 5e60941..e6a52d8 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -37,7 +37,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index c1abcb6..fb0b277 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_CYRUS #if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040) diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index dbd2bb3..182e8ab 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -15,8 +15,6 @@ #define CONFIG_DBAU1X00 1 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ -#define CONFIG_DISPLAY_BOARDINFO - #ifdef CONFIG_DBAU1000 /* Also known as Merlot */ #define CONFIG_SOC_AU1000 1 diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 4ad118e..a71f67c 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -137,7 +137,6 @@ #define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION /* diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index d17cdbb..e72cee0 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -40,10 +40,6 @@ #include <configs/ti_omap3_common.h> -/* Display CPU and Board information */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - #define CONFIG_MISC_INIT_R #define CONFIG_REVISION_TAG 1 diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index 8cf0283..1b7651f 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -22,7 +22,6 @@ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */ -#define CONFIG_DISPLAY_BOARDINFO /* * Valid values for CONFIG_SYS_TEXT_BASE are: diff --git a/include/configs/dns325.h b/include/configs/dns325.h index 23c173e..9b192bc 100644 --- a/include/configs/dns325.h +++ b/include/configs/dns325.h @@ -81,11 +81,6 @@ #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* - * Display cpu info at boot - */ -#define CONFIG_DISPLAY_CPUINFO - -/* * Environment variables configurations */ #ifdef CONFIG_CMD_NAND diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 66ce82c..798002d 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -105,10 +105,7 @@ #define DFU_ALT_INFO_QSPI \ "dfu_alt_info_qspi=" \ - "MLO raw 0x0 0x010000;" \ - "MLO.backup1 raw 0x010000 0x010000;" \ - "MLO.backup2 raw 0x020000 0x010000;" \ - "MLO.backup3 raw 0x030000 0x010000;" \ + "MLO raw 0x0 0x040000;" \ "u-boot.img raw 0x040000 0x0100000;" \ "u-boot-spl-os raw 0x140000 0x080000;" \ "u-boot-env raw 0x1C0000 0x010000;" \ @@ -121,22 +118,21 @@ DFU_ALT_INFO_EMMC \ DFU_ALT_INFO_RAM \ DFU_ALT_INFO_QSPI - -/* Fastboot */ -#define CONFIG_USB_FUNCTION_FASTBOOT -#define CONFIG_CMD_FASTBOOT -#define CONFIG_ANDROID_BOOT_IMAGE -#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_FASTBOOT_BUF_SIZE 0x2F000000 -#define CONFIG_FASTBOOT_FLASH -#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 +#else +/* Discard fastboot in SPL build, to spare some space */ +#undef CONFIG_FASTBOOT +#undef CONFIG_USB_FUNCTION_FASTBOOT +#undef CONFIG_CMD_FASTBOOT +#undef CONFIG_ANDROID_BOOT_IMAGE +#undef CONFIG_FASTBOOT_BUF_ADDR +#undef CONFIG_FASTBOOT_BUF_SIZE +#undef CONFIG_FASTBOOT_FLASH #endif #ifdef CONFIG_SPL_BUILD #undef CONFIG_CMD_BOOTD #ifdef CONFIG_SPL_DFU_SUPPORT #define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000 -#define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_HASH_SUPPORT #define DFU_ALT_INFO_RAM \ "dfu_alt_info_ram=" \ @@ -184,10 +180,7 @@ /* * Default to using SPI for environment, etc. - * 0x000000 - 0x010000 : QSPI.SPL (64KiB) - * 0x010000 - 0x020000 : QSPI.SPL.backup1 (64KiB) - * 0x020000 - 0x030000 : QSPI.SPL.backup2 (64KiB) - * 0x030000 - 0x040000 : QSPI.SPL.backup3 (64KiB) + * 0x000000 - 0x040000 : QSPI.SPL (256KiB) * 0x040000 - 0x140000 : QSPI.u-boot (1MiB) * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB) * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB) diff --git a/include/configs/draco.h b/include/configs/draco.h index 04240c7..5e4bf48 100644 --- a/include/configs/draco.h +++ b/include/configs/draco.h @@ -19,7 +19,6 @@ #include "siemens-am33x-common.h" -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_SYS_MPUCLK 300 #define DDR_PLL_FREQ 303 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index 982d526..1671438 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -211,7 +211,6 @@ #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ -#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_LOAD_ADDR 0x00800000 diff --git a/include/configs/etamin.h b/include/configs/etamin.h index fda18b2..9e5ee91 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -69,7 +69,6 @@ CONFIG_SYS_NAND_BASE2} #define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_SYS_MPUCLK 300 #define DDR_PLL_FREQ 303 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 0895497..b4a0388 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -23,7 +23,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 /* CPU information */ -#define CONFIG_DISPLAY_CPUINFO /* Display at console. */ #define CONFIG_ARCH_CPU_INIT /* ARM asynchronous clock */ diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 38298a2..3b61a41 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -17,8 +17,6 @@ #include <linux/sizes.h> #define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h index 9e03962..d112fbc 100644 --- a/include/configs/exynos7420-common.h +++ b/include/configs/exynos7420-common.h @@ -18,7 +18,6 @@ #include <linux/sizes.h> #define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F /* Size of malloc() pool before and after relocation */ diff --git a/include/configs/flea3.h b/include/configs/flea3.h index e84803d..11d9391 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -20,8 +20,6 @@ #define CONFIG_SYS_DCACHE_OFF -#define CONFIG_DISPLAY_CPUINFO - /* Only in case the value is not present in mach-types.h */ #ifndef MACH_TYPE_FLEA3 #define MACH_TYPE_FLEA3 3668 diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 52f096e..9db75f3 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -15,6 +15,7 @@ #include <asm/arch/imx-regs.h> #include <asm/imx-common/gpio.h> +#define BX50V3_BOOTARGS_EXTRA #if defined(CONFIG_TARGET_GE_B450V3) #define CONFIG_BOARD_NAME "General Electric B450v3" #define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b450v3.dtb" @@ -24,6 +25,9 @@ #elif defined(CONFIG_TARGET_GE_B850V3) #define CONFIG_BOARD_NAME "General Electric B850v3" #define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-b850v3.dtb" +#undef BX50V3_BOOTARGS_EXTRA +#define BX50V3_BOOTARGS_EXTRA "video=DP-1:1024x768@60 " \ + "video=HDMI-A-1:1024x768@60 " #else #define CONFIG_BOARD_NAME "General Electric BA16 Generic" #define CONFIG_DEFAULT_FDT_FILE "/boot/imx6q-ba16.dtb" @@ -38,9 +42,6 @@ #include "mx6_common.h" #include <linux/sizes.h> -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG @@ -166,7 +167,8 @@ "echo 'U-Boot upgraded. Please reset'; " \ "fi\0" \ "setargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/${rootdev} rw rootwait cma=128M\0" \ + "root=/dev/${rootdev} rw rootwait cma=128M " \ + BX50V3_BOOTARGS_EXTRA "\0" \ "loadbootscript=" \ "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \ diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h index 842ed16..211dc38 100644 --- a/include/configs/gr_cpci_ax2000.h +++ b/include/configs/gr_cpci_ax2000.h @@ -14,8 +14,6 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options * (easy to change) diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h index fa10676..36a91c6 100644 --- a/include/configs/gr_ep2s60.h +++ b/include/configs/gr_ep2s60.h @@ -15,8 +15,6 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options * (easy to change) diff --git a/include/configs/gr_xc3s_1500.h b/include/configs/gr_xc3s_1500.h index 9e00ff9..b0e9001 100644 --- a/include/configs/gr_xc3s_1500.h +++ b/include/configs/gr_xc3s_1500.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options * (easy to change) diff --git a/include/configs/grsim.h b/include/configs/grsim.h index 5736540..17cac5a 100644 --- a/include/configs/grsim.h +++ b/include/configs/grsim.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options * (easy to change) diff --git a/include/configs/grsim_leon2.h b/include/configs/grsim_leon2.h index 0f3204e..1642793 100644 --- a/include/configs/grsim_leon2.h +++ b/include/configs/grsim_leon2.h @@ -12,8 +12,6 @@ #ifndef __CONFIG_H__ #define __CONFIG_H__ -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options * (easy to change) diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index f01a74a..6caa3b1 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -29,7 +29,6 @@ #include "imx6_spl.h" /* common IMX6 SPL configuration */ #include "mx6_common.h" -#undef CONFIG_DISPLAY_BOARDINFO #define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */ diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 80628dd..14c43b8 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -16,9 +16,6 @@ #define CONFIG_MX27 #define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_DISPLAY_CPUINFO - #define CONFIG_SYS_TEXT_BASE 0xc0000000 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 50dfc11..2ae6b2d 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -18,9 +18,6 @@ #define CONFIG_MX31 /* This is a mx31 */ #define CONFIG_MX31_CLK32 32000 -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 56c7ca9..0d66764 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -18,7 +18,6 @@ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_INKA4X0 1 /* INKA4x0 board */ -#define CONFIG_DISPLAY_BOARDINFO /* * Valid values for CONFIG_SYS_TEXT_BASE are: diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h index 126e02e..9181695 100644 --- a/include/configs/ipek01.h +++ b/include/configs/ipek01.h @@ -19,7 +19,6 @@ #define CONFIG_MPX5200 1 /* MPX5200 board */ #define CONFIG_MPC5200_DDR 1 /* use DDR RAM */ #define CONFIG_IPEK01 /* Motherboard is ipek01 */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0xfc000000 diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 65f53b7..aaff553 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -15,7 +15,6 @@ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_JUPITER 1 /* ... on Jupiter board */ -#define CONFIG_DISPLAY_BOARDINFO /* * Valid values for CONFIG_SYS_TEXT_BASE are: diff --git a/include/configs/kc1.h b/include/configs/kc1.h index 32be528..9e73e31 100644 --- a/include/configs/kc1.h +++ b/include/configs/kc1.h @@ -137,9 +137,6 @@ #define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_LONGHELP diff --git a/include/configs/km/km8309-common.h b/include/configs/km/km8309-common.h index d21b500..0fe89af 100644 --- a/include/configs/km/km8309-common.h +++ b/include/configs/km/km8309-common.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_KM8309_COMMON_H #define __CONFIG_KM8309_COMMON_H -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options */ diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h index ef83263..5bc546c 100644 --- a/include/configs/km/km8321-common.h +++ b/include/configs/km/km8321-common.h @@ -23,8 +23,6 @@ #ifndef __CONFIG_KM8321_COMMON_H #define __CONFIG_KM8321_COMMON_H -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options */ diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index 6a9d739..d824b1b 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -8,8 +8,6 @@ #ifndef __CONFIG_KM83XX_H #define __CONFIG_KM83XX_H -#define CONFIG_DISPLAY_BOARDINFO - /* include common defines/options for all Keymile boards */ #include "keymile-common.h" #include "km-powerpc.h" diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index 25db704..c55c5d2 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -149,7 +149,6 @@ #define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */ #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ -#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ #define CONFIG_NR_DRAM_BANKS 4 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 8166c86..6a7f929 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -20,8 +20,6 @@ #define CONFIG_NAND_ECC_BCH -#define CONFIG_DISPLAY_BOARDINFO - /* common KM defines */ #include "keymile-common.h" diff --git a/include/configs/km82xx.h b/include/configs/km82xx.h index 1f9c720..aeece20 100644 --- a/include/configs/km82xx.h +++ b/include/configs/km82xx.h @@ -29,8 +29,6 @@ #error ("Board unsupported") #endif -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_SYS_TEXT_BASE 0xFE000000 #define CONFIG_MISC_INIT_R diff --git a/include/configs/km8360.h b/include/configs/km8360.h index c8039e1..6fa4e63 100644 --- a/include/configs/km8360.h +++ b/include/configs/km8360.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* KMBEC FPGA (PRIO) */ #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 #define CONFIG_SYS_KMBEC_FPGA_SIZE 64 diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 409c30d..a5c872c 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -18,8 +18,6 @@ #include <asm/arch/rmobile.h> #define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_CMDLINE_TAG diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 5beca45..80603c9 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -98,8 +98,6 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -#define CONFIG_DISPLAY_CPUINFO - /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index f6a3ae5..eefd93d 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -15,9 +15,7 @@ #define CONFIG_SYS_FSL_CLK -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - +#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DEEP_SLEEP diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 511f573..da07329 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -15,9 +15,7 @@ #define CONFIG_SYS_FSL_CLK -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - +#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_DEEP_SLEEP #ifdef CONFIG_DEEP_SLEEP diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index b80e316..561a05a 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -9,9 +9,6 @@ #include "ls1043a_common.h" -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) #define CONFIG_SYS_TEXT_BASE 0x82000000 #elif defined(CONFIG_QSPI_BOOT) diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 70ee046..1d0a1ac 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -20,9 +20,6 @@ #endif #endif -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) #define CONFIG_SYS_TEXT_BASE 0x82000000 #else diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index d1adf3f..c0f5bd3 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -9,9 +9,6 @@ #include "ls1046a_common.h" -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) #define CONFIG_SYS_TEXT_BASE 0x82000000 #elif defined(CONFIG_QSPI_BOOT) diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 693cc8d..2fe8fc1 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -20,9 +20,6 @@ #endif #endif -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_TEXT_BASE 0x82000000 #else diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 3dd4da8..2cae966 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -211,8 +211,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -#define CONFIG_DISPLAY_CPUINFO - /* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h index 1851d41..f0ec6c4 100644 --- a/include/configs/ls2080a_simu.h +++ b/include/configs/ls2080a_simu.h @@ -146,9 +146,6 @@ #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL /* MC firmware */ -#define CONFIG_SYS_LS_MC_FW_IN_NOR -#define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL - #define CONFIG_SYS_LS_MC_DPL_IN_NOR #define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index 5e36ca7..c3870e1 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -9,8 +9,6 @@ #include "ls2080a_common.h" -#define CONFIG_DISPLAY_BOARDINFO - #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index b93e919..ee0f5fc 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -12,8 +12,6 @@ #undef CONFIG_CONS_INDEX #define CONFIG_CONS_INDEX 2 -#define CONFIG_DISPLAY_BOARDINFO - #define I2C_MUX_CH_VOL_MONITOR 0xa #define I2C_VOL_MONITOR_ADDR 0x38 #define CONFIG_VOL_MONITOR_IR36021_READ diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 4b95af3..894973f 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -16,7 +16,6 @@ /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION #define CONFIG_FAT_WRITE diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h index 5af55d8..e31fdec 100644 --- a/include/configs/m53evk.h +++ b/include/configs/m53evk.h @@ -13,7 +13,6 @@ #include <asm/arch/imx-regs.h> -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_REVISION_TAG #define CONFIG_SYS_NO_FLASH @@ -24,7 +23,6 @@ /* * U-Boot Commands */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_DOS_PARTITION #define CONFIG_FAT_WRITE diff --git a/include/configs/malta.h b/include/configs/malta.h index fc4baba..775c30a 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -12,7 +12,6 @@ */ #define CONFIG_MALTA #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MEMSIZE_IN_BYTES diff --git a/include/configs/mcx.h b/include/configs/mcx.h index b6a710f..2c17ef3 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -36,12 +36,6 @@ */ #define CONFIG_SYS_TEXT_BASE 0x80008000 -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index 4211e72..4f90c34 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -15,7 +15,6 @@ #define __CONFIG_H #define CONFIG_MECP5123 1 -#define CONFIG_DISPLAY_BOARDINFO /* * Memory map for the MECP5123 board: diff --git a/include/configs/meesc.h b/include/configs/meesc.h index df76a20..6b9bb6a 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -52,8 +52,6 @@ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_MISC_INIT_R /* Call misc_init_r */ -#define CONFIG_DISPLAY_BOARDINFO /* call checkboard() */ -#define CONFIG_DISPLAY_CPUINFO /* display cpu info and speed */ #define CONFIG_PREBOOT /* enable preboot variable */ /* diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index bad85ba..917350f 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -17,7 +17,6 @@ /* CPU and board */ #define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ #define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_HIGH_BATS 1 /* High BATs supported */ diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index e329105..0511d03 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -12,7 +12,6 @@ #define __CONFIG_H #define CONFIG_MPC5121ADS 1 -#define CONFIG_DISPLAY_BOARDINFO /* * Memory map for the MPC5121ADS board: diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index 57cb795..3075cf0 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options */ diff --git a/include/configs/munices.h b/include/configs/munices.h index 3e4c062..5a6d004 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -168,7 +168,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ -#define CONFIG_DISPLAY_BOARDINFO 1 #define CONFIG_CMDLINE_EDITING 1 /* diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index ed271c2..73e9a03 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -87,7 +87,6 @@ #define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ #define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ #define CONFIG_BOARD_EARLY_INIT_F /* call board_init_f for early inits */ -#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ #define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ #define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ #define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h index 9971c81..36ff7ce 100644 --- a/include/configs/mx23_olinuxino.h +++ b/include/configs/mx23_olinuxino.h @@ -12,7 +12,6 @@ /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION #define CONFIG_CMD_LED diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h index 0de5737..12df0ad 100644 --- a/include/configs/mx23evk.h +++ b/include/configs/mx23evk.h @@ -15,7 +15,6 @@ /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION #define CONFIG_VIDEO diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index ea0d605..64f35dd 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -20,9 +20,6 @@ #define CONFIG_SYS_TIMER_COUNTER \ (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 808736b..b460f7e 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -17,7 +17,6 @@ /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION #define CONFIG_CMD_DATE diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 8de9dec..28fa513 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -14,9 +14,6 @@ /* High Level Configuration Options */ #define CONFIG_MX31 1 /* This is a mx31 */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_SYS_TEXT_BASE 0xA0000000 #define CONFIG_MACH_TYPE MACH_TYPE_MX31ADS diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index a37646e..1401760 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -19,9 +19,6 @@ /* High Level Configuration Options */ #define CONFIG_MX31 /* This is a mx31 */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h index e57912a..3f064fd 100644 --- a/include/configs/mx35pdk.h +++ b/include/configs/mx35pdk.h @@ -18,7 +18,6 @@ /* High Level Configuration Options */ #define CONFIG_MX35 -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_SYS_FSL_CLK /* Set TEXT at the beginning of the NOR flash */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 072aafd..74df84c 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -15,9 +15,6 @@ #define CONFIG_MX51 /* in a mx51 */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_SYS_FSL_CLK #define CONFIG_SYS_TEXT_BASE 0x97800000 diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index 0419050..ed6ed71 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -11,9 +11,6 @@ #define CONFIG_MX53 -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_MACH_TYPE MACH_TYPE_MX53_ARD #include <asm/arch/imx-regs.h> diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 5e1c597..7a896c7 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -11,9 +11,6 @@ #define CONFIG_MX53 -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_MACH_TYPE MACH_TYPE_MX53_EVK #include <asm/arch/imx-regs.h> diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index d259f53..92d4dff 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -12,8 +12,6 @@ #define CONFIG_MX53 -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO #include <asm/arch/imx-regs.h> diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index 632ebba..262a913 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -11,9 +11,6 @@ #define CONFIG_MX53 -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD #include <asm/arch/imx-regs.h> diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index fb49322..411316d 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -35,8 +35,6 @@ #define CONFIG_MX6 #endif -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_SYS_FSL_CLK /* ATAGs */ diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 925a418..b1d318d 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -20,9 +20,6 @@ #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h new file mode 100644 index 0000000..f06d889 --- /dev/null +++ b/include/configs/mx6ullevk.h @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 EVK board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6ULLEVK_CONFIG_H +#define __MX6ULLEVK_CONFIG_H + + +#include <asm/arch/imx-regs.h> +#include <linux/sizes.h> +#include "mx6_common.h" +#include <asm/imx-common/gpio.h> + +#ifdef CONFIG_SECURE_BOOT +#ifndef CONFIG_CSF_SIZE +#define CONFIG_CSF_SIZE 0x4000 +#endif +#endif + +#define PHYS_SDRAM_SIZE SZ_512M + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#ifdef CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* NAND pin conflicts with usdhc2 */ +#ifdef CONFIG_SYS_USE_NAND +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif +#endif + +/* I2C configs */ +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=imx6ull-14x14-evk.dtb\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_OFFSET (12 * SZ_64K) + +#define CONFIG_CMD_BMODE + +#define CONFIG_IMX_THERMAL + +#define CONFIG_IOMUX_LPSR + +#define CONFIG_SOFT_SPI + +#endif diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index 4b1077c..748029c 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -31,8 +31,6 @@ #define CONFIG_ARCH_MISC_INIT -#define CONFIG_DISPLAY_CPUINFO - #define CONFIG_LOADADDR 0x80800000 #define CONFIG_SYS_TEXT_BASE 0x87800000 diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 83f3d95..8759685 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -22,8 +22,6 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT -#define CONFIG_DISPLAY_BOARDINFO - /* Uncomment to enable secure boot support */ /* #define CONFIG_SECURE_BOOT */ #define CONFIG_CSF_SIZE 0x4000 diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 41ebd6d..5f7a4ac 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -49,12 +49,6 @@ #include <asm/arch/mem.h> #include <linux/stringify.h> -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) diff --git a/include/configs/o2dnt-common.h b/include/configs/o2dnt-common.h index 8913784..4d79165 100644 --- a/include/configs/o2dnt-common.h +++ b/include/configs/o2dnt-common.h @@ -17,7 +17,6 @@ * High Level Configuration Options */ #define CONFIG_MPC5200 -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* running at 33.000000MHz */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index c17dcf5..8a69a5f 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -29,12 +29,6 @@ #include <configs/ti_omap3_common.h> -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - #define CONFIG_MISC_INIT_R #define CONFIG_REVISION_TAG 1 diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h index 4310bad..09f4ec0 100644 --- a/include/configs/omap3_cairo.h +++ b/include/configs/omap3_cairo.h @@ -40,12 +40,6 @@ #include <configs/ti_omap3_common.h> -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - #define CONFIG_MISC_INIT_R #define CONFIG_REVISION_TAG 1 diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 740b588..0dd63df 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -35,10 +35,6 @@ */ #define CONFIG_SYS_LONGHELP -/* Display CPU and Board information */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - /* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 9ca648d..31972bd 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -23,12 +23,6 @@ #undef CONFIG_SPL_TEXT_BASE #define CONFIG_SPL_TEXT_BASE 0x40200000 -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - #define CONFIG_MISC_INIT_R #define CONFIG_REVISION_TAG 1 diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 6a60ec3..a7649ca 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -38,10 +38,6 @@ #undef CONFIG_SPL_TEXT_BASE #define CONFIG_SPL_TEXT_BASE 0x40200000 -/* Display CPU and Board information */ - -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_LATE_INIT #define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 0036c5c..ebf7dd0 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -20,10 +20,6 @@ #define CONFIG_BCH -/* Display CPU and Board information */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - /* call misc_init_r */ #define CONFIG_MISC_INIT_R diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index fce50f5..4a9f6b7 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -18,12 +18,6 @@ #include <configs/ti_omap3_common.h> -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - #define CONFIG_MISC_INIT_R #define CONFIG_REVISION_TAG 1 diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 6397051..4dcd5de 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -31,12 +31,6 @@ /* Generic NAND definition conflicts with debug_base */ #undef CONFIG_SYS_NAND_BASE -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - #define CONFIG_MISC_INIT_R #define CONFIG_REVISION_TAG 1 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 721f9d5..276a693 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -10,8 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - #if defined(CONFIG_P1020MBG) #define CONFIG_BOARDNAME "P1020MBG-PC" #define CONFIG_P1020 diff --git a/include/configs/p1_twr.h b/include/configs/p1_twr.h index 6de9acd..f672ffe 100644 --- a/include/configs/p1_twr.h +++ b/include/configs/p1_twr.h @@ -10,7 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO #if defined(CONFIG_TWR_P1025) #define CONFIG_BOARDNAME "TWR-P1025" #define CONFIG_P1025 diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index fb5278f..c92948f 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -15,8 +15,6 @@ #define CONFIG_PB1X00 1 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ -#define CONFIG_DISPLAY_BOARDINFO - #ifdef CONFIG_PB1000 #define CONFIG_SOC_AU1000 1 #else diff --git a/include/configs/pcm030.h b/include/configs/pcm030.h index 9babe6a..dce5c25 100644 --- a/include/configs/pcm030.h +++ b/include/configs/pcm030.h @@ -350,8 +350,6 @@ RTC configuration #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ -#define CONFIG_DISPLAY_BOARDINFO 1 - /*----------------------------------------------------------------------------- Various low-level settings -----------------------------------------------------------------------------*/ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index a70c988..eb1944a 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -13,8 +13,6 @@ #define CONFIG_VF610 -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT @@ -52,15 +50,20 @@ #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_PARTITIONS #define CONFIG_MTD_DEVICE + +#ifndef MTDIDS_DEFAULT #define MTDIDS_DEFAULT "nand0=NAND" -#define MTDPARTS_DEFAULT "mtdparts=NAND:256k(spare)"\ - ",384k(bootloader)"\ +#endif + +#ifndef MTDPARTS_DEFAULT +#define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\ ",128k(env1)"\ ",128k(env2)"\ ",128k(dtb)"\ ",6144k(kernel)"\ - ",65536k(ramdisk)"\ - ",450944k(root)" + ",-(root)" +#endif + #endif #define CONFIG_MMC @@ -87,7 +90,6 @@ /* QSPI Configs*/ #ifdef CONFIG_FSL_QSPI -#define CONFIG_SPI_FLASH #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 #define CONFIG_SYS_FSL_QSPI_LE @@ -117,16 +119,38 @@ #define CONFIG_SYS_TEXT_BASE 0x3f408000 #define CONFIG_BOARD_SIZE_LIMIT 524288 -#define CONFIG_BOOTCOMMAND "run bootcmd_sd" +/* if no target-specific extra environment settings were defined by the + target, define an empty one */ +#ifndef PCM052_EXTRA_ENV_SETTINGS +#define PCM052_EXTRA_ENV_SETTINGS +#endif + +/* if no target-specific boot command was defined by the target, + define an empty one */ +#ifndef PCM052_BOOTCOMMAND +#define PCM052_BOOTCOMMAND +#endif + +/* if no target-specific extra environment settings were defined by the + target, define an empty one */ +#ifndef PCM052_NET_INIT +#define PCM052_NET_INIT +#endif + +/* boot command, including the target-defined one if any */ +#define CONFIG_BOOTCOMMAND PCM052_BOOTCOMMAND "run bootcmd_nand" + +/* Extra env settings (including the target-defined ones if any) */ #define CONFIG_EXTRA_ENV_SETTINGS \ + PCM052_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "blimg_file=u-boot.imx\0" \ - "blsec_addr=0x81000000\0" \ - "blimg_addr=0x81000400\0" \ + "blimg_file=u-boot.vyb\0" \ + "blimg_addr=0x81000000\0" \ "kernel_file=zImage\0" \ "kernel_addr=0x82000000\0" \ - "fdt_file=vf610-pcm052.dtb\0" \ + "fdt_file=zImage.dtb\0" \ "fdt_addr=0x81000000\0" \ "ram_file=uRamdisk\0" \ "ram_addr=0x83000000\0" \ @@ -137,14 +161,15 @@ "tftptimeout=1000\0" \ "tftptimeoutcountmax=1000000\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ - "bootargs_base=setenv bootargs rw mem=256M " \ + "bootargs_base=setenv bootargs rw " \ + " mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \ "console=ttyLP1,115200n8\0" \ "bootargs_sd=setenv bootargs ${bootargs} " \ "root=/dev/mmcblk0p2 rootwait\0" \ "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \ "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \ "bootargs_nand=setenv bootargs ${bootargs} " \ - "ubi.mtd=6 rootfstype=ubifs root=ubi0:rootfs\0" \ + "ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \ "bootargs_ram=setenv bootargs ${bootargs} " \ "root=/dev/ram rw initrd=${ram_addr}\0" \ "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ @@ -163,14 +188,14 @@ "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \ "nand read ${fdt_addr} dtb; " \ "nand read ${kernel_addr} kernel; " \ - "nand read ${ram_addr} ramdisk; " \ + "nand read ${ram_addr} root; " \ "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ - "update_bootloader_from_tftp=mtdparts default; " \ - "nand read ${blsec_addr} bootloader; " \ - "mw.b ${blimg_addr} 0xff 0x5FC00; " \ - "if tftp ${blimg_addr} ${tftpdir}${blimg_file}; then " \ + "update_bootloader_from_tftp=" PCM052_NET_INIT \ + "if tftp ${blimg_addr} "\ + "${tftpdir}${blimg_file}; then " \ + "mtdparts default; " \ "nand erase.part bootloader; " \ - "nand write ${blsec_addr} bootloader ${filesize}; fi\0" \ + "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ "update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \ "${kernel_file}; " \ "then mtdparts default; " \ @@ -179,7 +204,8 @@ "if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \ "nand erase.part dtb; " \ "nand write ${fdt_addr} dtb ${filesize}; fi\0" \ - "update_kernel_from_tftp=if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \ + "update_kernel_from_tftp=" PCM052_NET_INIT \ + "if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \ "then setenv fdtsize ${filesize}; " \ "if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \ "mtdparts default; " \ @@ -187,16 +213,18 @@ "nand write ${fdt_addr} dtb ${fdtsize}; " \ "nand erase.part kernel; " \ "nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \ - "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \ + "update_rootfs_from_tftp=" PCM052_NET_INIT \ + "if tftp ${sys_addr} ${tftpdir}${filesys}; " \ "then mtdparts default; " \ "nand erase.part root; " \ "ubi part root; " \ "ubi create rootfs; " \ "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \ - "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ + "update_ramdisk_from_tftp=" PCM052_NET_INIT \ + "if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ "then mtdparts default; " \ - "nand erase.part ramdisk; " \ - "nand write ${ram_addr} ramdisk ${filesize}; fi\0" + "nand erase.part root; " \ + "nand write ${ram_addr} root ${filesize}; fi\0" /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -222,7 +250,7 @@ /* Physical memory map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM (0x80000000) -#define PHYS_SDRAM_SIZE (256 * 1024 * 1024) +#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * 1024 * 1024) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h index 6d03d69..3c86b25 100644 --- a/include/configs/pdm360ng.h +++ b/include/configs/pdm360ng.h @@ -13,7 +13,6 @@ #define __CONFIG_H #define CONFIG_PDM360NG 1 -#define CONFIG_DISPLAY_BOARDINFO /* * Memory map for the PDM360NG board: diff --git a/include/configs/pepper.h b/include/configs/pepper.h index 1bc8c4b..921d331 100644 --- a/include/configs/pepper.h +++ b/include/configs/pepper.h @@ -25,8 +25,6 @@ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ #define CONFIG_ENV_IS_NOWHERE -/* Display cpuinfo */ -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 49c98d8..52b7a2a 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -10,7 +10,6 @@ #define __PIC32MZDASK_CONFIG_H /* System Configuration */ -#define CONFIG_DISPLAY_BOARDINFO /*-------------------------------------------- * CPU configuration diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index ed3b64f..686d8da 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -14,9 +14,6 @@ #include "mx6_common.h" #include <asm/imx-common/gpio.h> -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - /* Network support */ #define CONFIG_FEC_MXC diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h index 206bfa7..76c7397 100644 --- a/include/configs/picosam9g45.h +++ b/include/configs/picosam9g45.h @@ -31,7 +31,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 537a6d8..6ac42b8 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -20,8 +20,6 @@ #include <asm/hardware.h> /* ARM asynchronous clock */ -#define CONFIG_DISPLAY_BOARDINFO - #define MASTER_PLL_DIV 15 #define MASTER_PLL_MUL 162 #define MAIN_PLL_DIV 2 diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 9993248..f112c36 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -19,8 +19,6 @@ #include <asm/hardware.h> /* ARM asynchronous clock */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define MASTER_PLL_DIV 6 #define MASTER_PLL_MUL 65 diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h index 21bf088..3fa7739 100644 --- a/include/configs/pxa-common.h +++ b/include/configs/pxa-common.h @@ -9,7 +9,6 @@ #ifndef __CONFIG_PXA_COMMON_H__ #define __CONFIG_PXA_COMMON_H__ -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH /* diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index 546c508..a6abba7 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -14,7 +14,6 @@ #define CONFIG_QEMU_MIPS -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_R diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h index 6cab719..7297a81 100644 --- a/include/configs/qemu-mips64.h +++ b/include/configs/qemu-mips64.h @@ -14,7 +14,6 @@ #define CONFIG_QEMU_MIPS -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_R diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h index f8ed22a..5adad66 100644 --- a/include/configs/rastaban.h +++ b/include/configs/rastaban.h @@ -15,7 +15,6 @@ #include "siemens-am33x-common.h" -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_SYS_MPUCLK 300 #define DDR_PLL_FREQ 303 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 5733da6..b24652f 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -34,8 +34,6 @@ #undef CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_TMU_TIMER diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 7655417..1e9752b 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -43,8 +43,6 @@ #undef CONFIG_SHOW_BOOT_PROGRESS #define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_SH_GPIO_PFC diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 73830e4..724a3f4 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -18,7 +18,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_THUMB_BUILD -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) #define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 9ddfe1d..afd3257 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -18,7 +18,6 @@ #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_THUMB_BUILD -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) #define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */ diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index b026122..bec004a 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -15,7 +15,6 @@ #define CONFIG_SYS_MALLOC_LEN (32 << 20) #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_NS16550_MEM32 diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h index 13eac75..533fde4 100644 --- a/include/configs/s32v234evb.h +++ b/include/configs/s32v234evb.h @@ -18,9 +18,6 @@ #define CONFIG_S32V234 #define CONFIG_DM -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - /* Config GIC */ #define CONFIG_GICV2 #define GICD_BASE 0x7D001000 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 72286dd..f2aab35 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -21,8 +21,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ #define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO /* input clock of PLL: has 24MHz input clock at S5PC110 */ #define CONFIG_SYS_CLK_FREQ_C110 24000000 diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h index d58b963..65cf143 100644 --- a/include/configs/sansa_fuze_plus.h +++ b/include/configs/sansa_fuze_plus.h @@ -11,7 +11,6 @@ /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION #define CONFIG_VIDEO diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 567c4d5..221ca32 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -15,8 +15,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options */ diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h index 0a8a637..56a23a6 100644 --- a/include/configs/sc_sps_1.h +++ b/include/configs/sc_sps_1.h @@ -16,7 +16,6 @@ /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION /* Memory configuration */ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index fd557a9..0302740 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -47,7 +47,6 @@ #define CONFIG_INITRD_TAG /* pass initrd param to kernel */ #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* U-Boot is loaded by a bootloader */ #define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ -#define CONFIG_DISPLAY_CPUINFO /* display CPU Info at startup */ /* We set the max number of command args high to avoid HUSH bugs. */ #define CONFIG_SYS_MAXARGS 32 diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index f83a9c8..f76fa75 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -101,8 +101,6 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ - #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 0ad1a27..4292566 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -25,9 +25,6 @@ #define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - /* input clock of PLL: SMDKC100 has 12MHz input clock */ #define CONFIG_SYS_CLK_FREQ 12000000 diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 978c627..8bd5806 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -28,7 +28,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_DISPLAY_CPUINFO /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index aab286f..4a623f7 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -26,7 +26,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT diff --git a/include/configs/sniper.h b/include/configs/sniper.h index 3bc9819..0e9a4cc 100644 --- a/include/configs/sniper.h +++ b/include/configs/sniper.h @@ -148,9 +148,6 @@ #define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_LONGHELP diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index e1faf38..efd2968 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -14,7 +14,6 @@ /* * High level configuration */ -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_ARCH_MISC_INIT #define CONFIG_ARCH_EARLY_INIT_R diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 29f9522..dc6878c 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -22,7 +22,6 @@ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC8544 1 #define CONFIG_SOCRATES 1 -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index a6973c5..f609136 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -173,7 +173,6 @@ /* Miscellaneous configurable options */ #define CONFIG_ARCH_CPU_INIT #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index d261fb3..33f2ab7 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -54,7 +54,6 @@ #endif /* CPU */ -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_TIMER_CLK_FREQ 24000000 /* @@ -178,7 +177,6 @@ #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 8ce337e..61ef25a 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -10,7 +10,6 @@ #ifndef __T4QDS_H #define __T4QDS_H -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_CMD_REGINFO /* High Level Configuration Options */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index 61c563e..1527d90 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -28,12 +28,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap.h> -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h index 176f544..9e85b1d 100644 --- a/include/configs/tao3530.h +++ b/include/configs/tao3530.h @@ -32,12 +32,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap.h> -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 1be4341..3a762e3 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -47,7 +47,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO /* general purpose I/O */ #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 85501bc..d877336 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -39,7 +39,7 @@ #define CONFIG_SYS_MEMTEST_END \ (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ 0x6C000000 +#define CONFIG_SYS_BOOTMAPSZ 0x10000000 /* Serial console */ #define CONFIG_MXC_UART @@ -56,9 +56,11 @@ /* *** Command definition *** */ #define CONFIG_CMD_BMODE +#define CONFIG_CMD_PART /* Filesystems / image support */ #define CONFIG_EFI_PARTITION +#define CONFIG_PARTITION_UUIDS /* MMC */ #define CONFIG_SYS_FSL_USDHC_NUM 3 diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 1385d31..e3b2490 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -24,12 +24,6 @@ #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE #endif -/* - * Display CPU and Board information - */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ /* Environment */ diff --git a/include/configs/thuban.h b/include/configs/thuban.h index 8d7b280..e844cdd 100644 --- a/include/configs/thuban.h +++ b/include/configs/thuban.h @@ -15,7 +15,6 @@ #include "siemens-am33x-common.h" -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_SYS_MPUCLK 300 #define DDR_PLL_FREQ 303 #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index b3215a2..79f436c 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -29,8 +29,6 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG /* required for ramdisk support */ -#define CONFIG_DISPLAY_CPUINFO - #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x81000000\0" \ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index c42dedb..66d85be 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -15,7 +15,6 @@ /* U-Boot Build Configuration */ #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ #define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_DISPLAY_CPUINFO /* SoC Configuration */ #define CONFIG_ARCH_CPU_INIT @@ -68,14 +67,14 @@ #define CONFIG_CONS_INDEX 1 #ifndef CONFIG_SOC_K2G -#define CONFIG_SYS_NS16550_CLK clk_get_rate(KS2_CLK1_6) +#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6) #else -#define CONFIG_SYS_NS16550_CLK clk_get_rate(uart_pll_clk) / 2 +#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2 #endif /* SPI Configuration */ #define CONFIG_DAVINCI_SPI -#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6) +#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) #define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #define CONFIG_SYS_SPI0 @@ -314,7 +313,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/clock.h> #ifndef CONFIG_SOC_K2G -#define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6) +#define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) #else #define CONFIG_SYS_HZ_CLOCK external_clk[sys_clk] #endif diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 4115c78..f0aea2c 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -17,8 +17,6 @@ */ #define CONFIG_OMAP4430 1 /* which is in a 4430 */ #define CONFIG_MISC_INIT_R -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 #define CONFIG_SYS_THUMB_BUILD @@ -151,7 +149,6 @@ * So moving TEXT_BASE down to non-HS limit. */ #define CONFIG_SPL_TEXT_BASE 0x40300000 -#define CONFIG_SPL_DISPLAY_PRINT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ (128 << 20)) diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index a483850..29b7d96 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -17,9 +17,6 @@ #ifndef __CONFIG_TI_OMAP5_COMMON_H #define __CONFIG_TI_OMAP5_COMMON_H -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - /* Common ARM Erratas */ #define CONFIG_ARM_ERRATA_798870 @@ -160,7 +157,6 @@ #define CONFIG_SPL_TEXT_BASE 0x40300000 #endif -#define CONFIG_SPL_DISPLAY_PRINT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ (128 << 20)) diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h index 7bf8e4c..fefc902 100644 --- a/include/configs/tplink_wdr4300.h +++ b/include/configs/tplink_wdr4300.h @@ -7,8 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index c1c9495..ac7b31b 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -39,10 +39,6 @@ #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap.h> -/* Display CPU and Board information */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_SILENT_CONSOLE /* Clock Defines */ diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h index 252b3fc..2e5f38d 100644 --- a/include/configs/ts4800.h +++ b/include/configs/ts4800.h @@ -16,9 +16,6 @@ /* High Level Configuration Options */ #define CONFIG_MX51 -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - #define CONFIG_SYS_NO_FLASH /* No NOR Flash */ #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 29be00a..ead935e 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -29,8 +29,6 @@ /* #define CONFIG_SYS_ICACHE_OFF */ /* #define CONFIG_SYS_DCACHE_OFF */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_BOARD_LATE_INIT #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index 39ac189..075d9c9 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -31,8 +31,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_DISPLAY_CPUINFO - #define CONFIG_SYS_TEXT_BASE 0x23f00000 /* diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 23092db..b2d54d5 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -12,8 +12,6 @@ #define __CONFIG_H #define CONFIG_MX53 -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_FSL_CLK #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MXC_GPIO diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 03ff0c6..24f951b 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -14,7 +14,6 @@ */ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_V38B 1 /* ...on V38B board */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0xFF000000 diff --git a/include/configs/vct.h b/include/configs/vct.h index f2e0e5c..210d0ef 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -25,8 +25,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - #define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */ #define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 83d0004..7304d79 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -13,8 +13,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* * High Level Configuration Options */ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index 03586f0..af5ba61 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -13,8 +13,6 @@ #define CONFIG_VF610 -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_FSL_CLK #define CONFIG_MACH_TYPE 4146 diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 60513df..c4c66a5 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -18,8 +18,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - /* * Top level Makefile configuration choices */ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 69d0fd5..999ee6d 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -116,32 +116,6 @@ "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ "fi; " \ "fi\0" \ - "videoargs=" \ - "setenv nextcon 0; " \ - "if hdmidet; then " \ - "setenv bootargs ${bootargs} " \ - "video=mxcfb${nextcon}:dev=hdmi,1280x720M@60," \ - "if=RGB24; " \ - "setenv fbmen fbmem=28M; " \ - "setexpr nextcon ${nextcon} + 1; " \ - "else " \ - "echo - no HDMI monitor;" \ - "fi; " \ - "i2c dev 1; " \ - "if i2c probe 0x10; then " \ - "setenv bootargs ${bootargs} " \ - "video=mxcfb${nextcon}:dev=lcd,800x480@60," \ - "if=RGB666,bpp=32; " \ - "if test 0 -eq ${nextcon}; then " \ - "setenv fbmem fbmem=10M; " \ - "else " \ - "setenv fbmem ${fbmem},10M; " \ - "fi; " \ - "setexpr nextcon ${nextcon} + 1; " \ - "else " \ - "echo '- no FWBADAPT-7WVGA-LCD-F07A-0102 display';" \ - "fi; " \ - "setenv bootargs ${bootargs} ${fbmem}\0" \ "findfdt="\ "if test $board_name = C1 && test $board_rev = MX6Q ; then " \ "setenv fdtfile imx6q-wandboard.dtb; fi; " \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 9642dd9..d3b0c5e 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -21,8 +21,6 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_LATE_INIT -#define CONFIG_DISPLAY_BOARDINFO - /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR #define CONFIG_SUPPORT_EMMC_BOOT diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h index de6b183..50495bf 100644 --- a/include/configs/woodburn_common.h +++ b/include/configs/woodburn_common.h @@ -20,8 +20,6 @@ #define CONFIG_SYS_DCACHE_OFF -#define CONFIG_DISPLAY_CPUINFO - /* Only in case the value is not present in mach-types.h */ #ifndef MACH_TYPE_FLEA3 #define MACH_TYPE_FLEA3 3668 diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index ff39c31..b08641f 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -108,7 +108,6 @@ #define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION /* diff --git a/include/configs/x600.h b/include/configs/x600.h index f15b1f9..13b0b95 100644 --- a/include/configs/x600.h +++ b/include/configs/x600.h @@ -136,7 +136,6 @@ /* Miscellaneous configurable options */ #define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_BOOT_PARAMS_ADDR 0x00000100 #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 74b2522..7803aea 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -19,7 +19,6 @@ #define CONFIG_ZBOOT_32 #define CONFIG_PHYSMEM #define CONFIG_DISPLAY_BOARDINFO_LATE -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_LAST_STAGE_INIT #define CONFIG_NR_DRAM_BANKS 8 diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h index 69558fd..e291ff7 100644 --- a/include/configs/xfi3.h +++ b/include/configs/xfi3.h @@ -11,7 +11,6 @@ /* U-Boot Commands */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DOS_PARTITION #define CONFIG_VIDEO diff --git a/include/configs/xpedite1000.h b/include/configs/xpedite1000.h index bc91714..1a4bd75 100644 --- a/include/configs/xpedite1000.h +++ b/include/configs/xpedite1000.h @@ -22,7 +22,6 @@ #define CONFIG_440GX 1 /* 440 GX */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0xFFF80000 diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h index eaea33b..571ded8 100644 --- a/include/configs/xpedite517x.h +++ b/include/configs/xpedite517x.h @@ -23,7 +23,6 @@ #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ #define CONFIG_ALTIVEC 1 -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0xfff00000 diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h index f7cfc9e..273c6d4 100644 --- a/include/configs/xpedite520x.h +++ b/include/configs/xpedite520x.h @@ -21,7 +21,6 @@ #define CONFIG_SYS_BOARD_NAME "XPedite5200" #define CONFIG_SYS_FORM_PMC_XMC 1 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ -#define CONFIG_DISPLAY_BOARDINFO #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index 3306e44a..8d595c9 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -21,7 +21,6 @@ #define CONFIG_SYS_BOARD_NAME "XPedite5370" #define CONFIG_SYS_FORM_3U_VPX 1 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ -#define CONFIG_DISPLAY_BOARDINFO #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index ded6bbf..213dfa7 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_FORM_PMC_XMC 1 #define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */ #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ -#define CONFIG_DISPLAY_BOARDINFO #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xfff80000 diff --git a/include/configs/xpress.h b/include/configs/xpress.h index dd28e6a..c45dcda 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -14,9 +14,6 @@ /* SPL options */ #include "imx6_spl.h" -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (16 << 20) diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index 3e5d310..c7862be 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -112,8 +112,6 @@ #undef CONFIG_USE_IRQ /* Keep it simple, poll only */ #define CONFIG_BOARD_POSTCLK_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_MISC_INIT_R #define CONFIG_BOOTFILE "uImage" diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index f1c9bed..0118fd2 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -235,7 +235,6 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE #define CONFIG_BOARD_LATE_INIT -#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_LONGHELP #define CONFIG_CLOCKS #define CONFIG_CMD_CLK diff --git a/include/cros_ec.h b/include/cros_ec.h index 5fa5f6f..30b1908 100644 --- a/include/cros_ec.h +++ b/include/cros_ec.h @@ -395,9 +395,11 @@ struct i2c_msg; * Tunnel an I2C transfer to the EC * * @param dev CROS-EC device + * @param port The remote port on EC to use * @param msg List of messages to transfer * @param nmsgs Number of messages to transfer */ -int cros_ec_i2c_tunnel(struct udevice *dev, struct i2c_msg *msg, int nmsgs); +int cros_ec_i2c_tunnel(struct udevice *dev, int port, struct i2c_msg *msg, + int nmsgs); #endif diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h new file mode 100644 index 0000000..18de070 --- /dev/null +++ b/include/dt-bindings/clock/imx6ul-clock.h @@ -0,0 +1,253 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H +#define __DT_BINDINGS_CLOCK_IMX6UL_H + +#define IMX6UL_CLK_DUMMY 0 +#define IMX6UL_CLK_CKIL 1 +#define IMX6UL_CLK_CKIH 2 +#define IMX6UL_CLK_OSC 3 +#define IMX6UL_PLL1_BYPASS_SRC 4 +#define IMX6UL_PLL2_BYPASS_SRC 5 +#define IMX6UL_PLL3_BYPASS_SRC 6 +#define IMX6UL_PLL4_BYPASS_SRC 7 +#define IMX6UL_PLL5_BYPASS_SRC 8 +#define IMX6UL_PLL6_BYPASS_SRC 9 +#define IMX6UL_PLL7_BYPASS_SRC 10 +#define IMX6UL_CLK_PLL1 11 +#define IMX6UL_CLK_PLL2 12 +#define IMX6UL_CLK_PLL3 13 +#define IMX6UL_CLK_PLL4 14 +#define IMX6UL_CLK_PLL5 15 +#define IMX6UL_CLK_PLL6 16 +#define IMX6UL_CLK_PLL7 17 +#define IMX6UL_PLL1_BYPASS 18 +#define IMX6UL_PLL2_BYPASS 19 +#define IMX6UL_PLL3_BYPASS 20 +#define IMX6UL_PLL4_BYPASS 21 +#define IMX6UL_PLL5_BYPASS 22 +#define IMX6UL_PLL6_BYPASS 23 +#define IMX6UL_PLL7_BYPASS 24 +#define IMX6UL_CLK_PLL1_SYS 25 +#define IMX6UL_CLK_PLL2_BUS 26 +#define IMX6UL_CLK_PLL3_USB_OTG 27 +#define IMX6UL_CLK_PLL4_AUDIO 28 +#define IMX6UL_CLK_PLL5_VIDEO 29 +#define IMX6UL_CLK_PLL6_ENET 30 +#define IMX6UL_CLK_PLL7_USB_HOST 31 +#define IMX6UL_CLK_USBPHY1 32 +#define IMX6UL_CLK_USBPHY2 33 +#define IMX6UL_CLK_USBPHY1_GATE 34 +#define IMX6UL_CLK_USBPHY2_GATE 35 +#define IMX6UL_CLK_PLL2_PFD0 36 +#define IMX6UL_CLK_PLL2_PFD1 37 +#define IMX6UL_CLK_PLL2_PFD2 38 +#define IMX6UL_CLK_PLL2_PFD3 39 +#define IMX6UL_CLK_PLL3_PFD0 40 +#define IMX6UL_CLK_PLL3_PFD1 41 +#define IMX6UL_CLK_PLL3_PFD2 42 +#define IMX6UL_CLK_PLL3_PFD3 43 +#define IMX6UL_CLK_ENET_REF 44 +#define IMX6UL_CLK_ENET2_REF 45 +#define IMX6UL_CLK_ENET2_REF_125M 46 +#define IMX6UL_CLK_ENET_PTP_REF 47 +#define IMX6UL_CLK_ENET_PTP 48 +#define IMX6UL_CLK_PLL4_POST_DIV 49 +#define IMX6UL_CLK_PLL4_AUDIO_DIV 50 +#define IMX6UL_CLK_PLL5_POST_DIV 51 +#define IMX6UL_CLK_PLL5_VIDEO_DIV 52 +#define IMX6UL_CLK_PLL2_198M 53 +#define IMX6UL_CLK_PLL3_80M 54 +#define IMX6UL_CLK_PLL3_60M 55 +#define IMX6UL_CLK_STEP 56 +#define IMX6UL_CLK_PLL1_SW 57 +#define IMX6UL_CLK_AXI_ALT_SEL 58 +#define IMX6UL_CLK_AXI_SEL 59 +#define IMX6UL_CLK_PERIPH_PRE 60 +#define IMX6UL_CLK_PERIPH2_PRE 61 +#define IMX6UL_CLK_PERIPH_CLK2_SEL 62 +#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63 +#define IMX6UL_CLK_USDHC1_SEL 64 +#define IMX6UL_CLK_USDHC2_SEL 65 +#define IMX6UL_CLK_BCH_SEL 66 +#define IMX6UL_CLK_GPMI_SEL 67 +#define IMX6UL_CLK_EIM_SLOW_SEL 68 +#define IMX6UL_CLK_SPDIF_SEL 69 +#define IMX6UL_CLK_SAI1_SEL 70 +#define IMX6UL_CLK_SAI2_SEL 71 +#define IMX6UL_CLK_SAI3_SEL 72 +#define IMX6UL_CLK_LCDIF_PRE_SEL 73 +#define IMX6UL_CLK_SIM_PRE_SEL 74 +#define IMX6UL_CLK_LDB_DI0_SEL 75 +#define IMX6UL_CLK_LDB_DI1_SEL 76 +#define IMX6UL_CLK_ENFC_SEL 77 +#define IMX6UL_CLK_CAN_SEL 78 +#define IMX6UL_CLK_ECSPI_SEL 79 +#define IMX6UL_CLK_UART_SEL 80 +#define IMX6UL_CLK_QSPI1_SEL 81 +#define IMX6UL_CLK_PERCLK_SEL 82 +#define IMX6UL_CLK_LCDIF_SEL 83 +#define IMX6UL_CLK_SIM_SEL 84 +#define IMX6UL_CLK_PERIPH 85 +#define IMX6UL_CLK_PERIPH2 86 +#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87 +#define IMX6UL_CLK_LDB_DI0_DIV_7 88 +#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89 +#define IMX6UL_CLK_LDB_DI1_DIV_7 90 +#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91 +#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92 +#define IMX6UL_CLK_ARM 93 +#define IMX6UL_CLK_PERIPH_CLK2 94 +#define IMX6UL_CLK_PERIPH2_CLK2 95 +#define IMX6UL_CLK_AHB 96 +#define IMX6UL_CLK_MMDC_PODF 97 +#define IMX6UL_CLK_AXI_PODF 98 +#define IMX6UL_CLK_PERCLK 99 +#define IMX6UL_CLK_IPG 100 +#define IMX6UL_CLK_USDHC1_PODF 101 +#define IMX6UL_CLK_USDHC2_PODF 102 +#define IMX6UL_CLK_BCH_PODF 103 +#define IMX6UL_CLK_GPMI_PODF 104 +#define IMX6UL_CLK_EIM_SLOW_PODF 105 +#define IMX6UL_CLK_SPDIF_PRED 106 +#define IMX6UL_CLK_SPDIF_PODF 107 +#define IMX6UL_CLK_SAI1_PRED 108 +#define IMX6UL_CLK_SAI1_PODF 109 +#define IMX6UL_CLK_SAI2_PRED 110 +#define IMX6UL_CLK_SAI2_PODF 111 +#define IMX6UL_CLK_SAI3_PRED 112 +#define IMX6UL_CLK_SAI3_PODF 113 +#define IMX6UL_CLK_LCDIF_PRED 114 +#define IMX6UL_CLK_LCDIF_PODF 115 +#define IMX6UL_CLK_SIM_PODF 116 +#define IMX6UL_CLK_QSPI1_PDOF 117 +#define IMX6UL_CLK_ENFC_PRED 118 +#define IMX6UL_CLK_ENFC_PODF 119 +#define IMX6UL_CLK_CAN_PODF 120 +#define IMX6UL_CLK_ECSPI_PODF 121 +#define IMX6UL_CLK_UART_PODF 122 +#define IMX6UL_CLK_ADC1 123 +#define IMX6UL_CLK_ADC2 124 +#define IMX6UL_CLK_AIPSTZ1 125 +#define IMX6UL_CLK_AIPSTZ2 126 +#define IMX6UL_CLK_AIPSTZ3 127 +#define IMX6UL_CLK_APBHDMA 128 +#define IMX6UL_CLK_ASRC_IPG 129 +#define IMX6UL_CLK_ASRC_MEM 130 +#define IMX6UL_CLK_GPMI_BCH_APB 131 +#define IMX6UL_CLK_GPMI_BCH 132 +#define IMX6UL_CLK_GPMI_IO 133 +#define IMX6UL_CLK_GPMI_APB 134 +#define IMX6UL_CLK_CAAM_MEM 135 +#define IMX6UL_CLK_CAAM_ACLK 136 +#define IMX6UL_CLK_CAAM_IPG 137 +#define IMX6UL_CLK_CSI 138 +#define IMX6UL_CLK_ECSPI1 139 +#define IMX6UL_CLK_ECSPI2 140 +#define IMX6UL_CLK_ECSPI3 141 +#define IMX6UL_CLK_ECSPI4 142 +#define IMX6UL_CLK_EIM 143 +#define IMX6UL_CLK_ENET 144 +#define IMX6UL_CLK_ENET_AHB 145 +#define IMX6UL_CLK_EPIT1 146 +#define IMX6UL_CLK_EPIT2 147 +#define IMX6UL_CLK_CAN1_IPG 148 +#define IMX6UL_CLK_CAN1_SERIAL 149 +#define IMX6UL_CLK_CAN2_IPG 150 +#define IMX6UL_CLK_CAN2_SERIAL 151 +#define IMX6UL_CLK_GPT1_BUS 152 +#define IMX6UL_CLK_GPT1_SERIAL 153 +#define IMX6UL_CLK_GPT2_BUS 154 +#define IMX6UL_CLK_GPT2_SERIAL 155 +#define IMX6UL_CLK_I2C1 156 +#define IMX6UL_CLK_I2C2 157 +#define IMX6UL_CLK_I2C3 158 +#define IMX6UL_CLK_I2C4 159 +#define IMX6UL_CLK_IOMUXC 160 +#define IMX6UL_CLK_LCDIF_APB 161 +#define IMX6UL_CLK_LCDIF_PIX 162 +#define IMX6UL_CLK_MMDC_P0_FAST 163 +#define IMX6UL_CLK_MMDC_P0_IPG 164 +#define IMX6UL_CLK_OCOTP 165 +#define IMX6UL_CLK_OCRAM 166 +#define IMX6UL_CLK_PWM1 167 +#define IMX6UL_CLK_PWM2 168 +#define IMX6UL_CLK_PWM3 169 +#define IMX6UL_CLK_PWM4 170 +#define IMX6UL_CLK_PWM5 171 +#define IMX6UL_CLK_PWM6 172 +#define IMX6UL_CLK_PWM7 173 +#define IMX6UL_CLK_PWM8 174 +#define IMX6UL_CLK_PXP 175 +#define IMX6UL_CLK_QSPI 176 +#define IMX6UL_CLK_ROM 177 +#define IMX6UL_CLK_SAI1 178 +#define IMX6UL_CLK_SAI1_IPG 179 +#define IMX6UL_CLK_SAI2 180 +#define IMX6UL_CLK_SAI2_IPG 181 +#define IMX6UL_CLK_SAI3 182 +#define IMX6UL_CLK_SAI3_IPG 183 +#define IMX6UL_CLK_SDMA 184 +#define IMX6UL_CLK_SIM 185 +#define IMX6UL_CLK_SIM_S 186 +#define IMX6UL_CLK_SPBA 187 +#define IMX6UL_CLK_SPDIF 188 +#define IMX6UL_CLK_UART1_IPG 189 +#define IMX6UL_CLK_UART1_SERIAL 190 +#define IMX6UL_CLK_UART2_IPG 191 +#define IMX6UL_CLK_UART2_SERIAL 192 +#define IMX6UL_CLK_UART3_IPG 193 +#define IMX6UL_CLK_UART3_SERIAL 194 +#define IMX6UL_CLK_UART4_IPG 195 +#define IMX6UL_CLK_UART4_SERIAL 196 +#define IMX6UL_CLK_UART5_IPG 197 +#define IMX6UL_CLK_UART5_SERIAL 198 +#define IMX6UL_CLK_UART6_IPG 199 +#define IMX6UL_CLK_UART6_SERIAL 200 +#define IMX6UL_CLK_UART7_IPG 201 +#define IMX6UL_CLK_UART7_SERIAL 202 +#define IMX6UL_CLK_UART8_IPG 203 +#define IMX6UL_CLK_UART8_SERIAL 204 +#define IMX6UL_CLK_USBOH3 205 +#define IMX6UL_CLK_USDHC1 206 +#define IMX6UL_CLK_USDHC2 207 +#define IMX6UL_CLK_WDOG1 208 +#define IMX6UL_CLK_WDOG2 209 +#define IMX6UL_CLK_WDOG3 210 +#define IMX6UL_CLK_LDB_DI0 211 +#define IMX6UL_CLK_AXI 212 +#define IMX6UL_CLK_SPDIF_GCLK 213 +#define IMX6UL_CLK_GPT_3M 214 +#define IMX6UL_CLK_SIM2 215 +#define IMX6UL_CLK_SIM1 216 +#define IMX6UL_CLK_IPP_DI0 217 +#define IMX6UL_CLK_IPP_DI1 218 +#define IMX6UL_CA7_SECONDARY_SEL 219 +#define IMX6UL_CLK_PER_BCH 220 +#define IMX6UL_CLK_CSI_SEL 221 +#define IMX6UL_CLK_CSI_PODF 222 +#define IMX6UL_CLK_PLL3_120M 223 +/* For i.MX6ULL */ +#define IMX6UL_CLK_ESAI_SEL 224 +#define IMX6UL_CLK_ESAI_PRED 225 +#define IMX6UL_CLK_ESAI_PODF 226 +#define IMX6UL_CLK_ESAI_EXTAL 227 +#define IMX6UL_CLK_ESAI_MEM 228 +#define IMX6UL_CLK_ESAI_IPG 229 +#define IMX6UL_CLK_DCP_CLK 230 +#define IMX6UL_CLK_EPDC_PRE_SEL 231 +#define IMX6UL_CLK_EPDC_SEL 232 +#define IMX6UL_CLK_EPDC_PODF 233 +#define IMX6UL_CLK_EPDC_ACLK 234 +#define IMX6UL_CLK_EPDC_PIX 235 + +#define IMX6UL_CLK_END 236 + +#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ diff --git a/include/environment.h b/include/environment.h index 1fdbdad..b602e8a 100644 --- a/include/environment.h +++ b/include/environment.h @@ -16,10 +16,9 @@ * shifts the remaining entries to the front. Replacing an entry is a * combination of deleting the old value and adding the new one. * - * The environment is preceeded by a 32 bit CRC over the data part. + * The environment is preceded by a 32 bit CRC over the data part. * - ************************************************************************** - */ + *************************************************************************/ #if defined(CONFIG_ENV_IS_IN_FLASH) # ifndef CONFIG_ENV_ADDR diff --git a/include/fsl_wdog.h b/include/fsl_wdog.h index f698d4d..683c3f3 100644 --- a/include/fsl_wdog.h +++ b/include/fsl_wdog.h @@ -15,5 +15,6 @@ struct watchdog_regs { #define WCR_WDE 0x04 #define WCR_WDT 0x08 #define WCR_SRS 0x10 +#define WCR_WDA 0x20 #define SET_WCR_WT(x) (x << 8) #define WCR_WT_MSK SET_WCR_WT(0xFF) diff --git a/include/image.h b/include/image.h index 64da722..2b1296c 100644 --- a/include/image.h +++ b/include/image.h @@ -278,6 +278,7 @@ enum { IH_TYPE_ZYNQIMAGE, /* Xilinx Zynq Boot Image */ IH_TYPE_ZYNQMPIMAGE, /* Xilinx ZynqMP Boot Image */ IH_TYPE_FPGA, /* FPGA Image */ + IH_TYPE_VYBRIDIMAGE, /* VYBRID .vyb Image */ IH_TYPE_COUNT, /* Number of image types */ }; diff --git a/include/power/rn5t567_pmic.h b/include/power/rn5t567_pmic.h new file mode 100644 index 0000000..9ce601f --- /dev/null +++ b/include/power/rn5t567_pmic.h @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2016 Toradex AG + * Stefan Agner <stefan.agner@toradex.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __RN5T567_PMIC_H_ +#define __RN5T567_PMIC_H_ + +/* RN5T567 registers */ +enum { + RN5T567_LSIVER = 0x00, + RN5T567_OTPVER = 0x01, + RN5T567_IODAC = 0x02, + RN5T567_VINDAC = 0x03, + RN5T567_OUT32KEN = 0x05, + + RN5T567_CPUCNT = 0x06, + + RN5T567_PSWR = 0x07, + RN5T567_PONHIS = 0x09, + RN5T567_POFFHIS = 0x0A, + RN5T567_WATCHDOG = 0x0B, + RN5T567_WATCHDOGCNT = 0x0C, + RN5T567_PWRFUNC = 0x0D, + RN5T567_SLPCNT = 0x0E, + RN5T567_REPCNT = 0x0F, + RN5T567_PWRONTIMSET = 0x10, + RN5T567_NOETIMSETCNT = 0x11, + RN5T567_PWRIREN = 0x12, + RN5T567_PWRIRQ = 0x13, + RN5T567_PWRMON = 0x14, + RN5T567_PWRIRSEL = 0x15, + + RN5T567_DC1_SLOT = 0x16, + RN5T567_DC2_SLOT = 0x17, + RN5T567_DC3_SLOT = 0x18, + RN5T567_DC4_SLOT = 0x19, + + RN5T567_LDO1_SLOT = 0x1B, + RN5T567_LDO2_SLOT = 0x1C, + RN5T567_LDO3_SLOT = 0x1D, + RN5T567_LDO4_SLOT = 0x1E, + RN5T567_LDO5_SLOT = 0x1F, + + RN5T567_PSO0_SLOT = 0x25, + RN5T567_PSO1_SLOT = 0x26, + RN5T567_PSO2_SLOT = 0x27, + RN5T567_PSO3_SLOT = 0x28, + + RN5T567_LDORTC1_SLOT = 0x2A, + + RN5T567_DC1CTL = 0x2C, + RN5T567_DC1CTL2 = 0x2D, + RN5T567_DC2CTL = 0x2E, + RN5T567_DC2CTL2 = 0x2F, + RN5T567_DC3CTL = 0x30, + RN5T567_DC3CTL2 = 0x31, + RN5T567_DC4CTL = 0x32, + RN5T567_DC4CTL2 = 0x33, + + RN5T567_DC1DAC = 0x36, + RN5T567_DC2DAC = 0x37, + RN5T567_DC3DAC = 0x38, + RN5T567_DC4DAC = 0x39, + + RN5T567_DC1DAC_SLP = 0x3B, + RN5T567_DC2DAC_SLP = 0x3C, + RN5T567_DC3DAC_SLP = 0x3D, + RN5T567_DC4DAC_SLP = 0x3E, + + RN5T567_DCIREN = 0x40, + RN5T567_DCIRQ = 0x41, + RN5T567_DCIRMON = 0x42, + + RN5T567_LDOEN1 = 0x44, + RN5T567_LDOEN2 = 0x45, + RN5T567_LDODIS1 = 0x46, + + RN5T567_LDO1DAC = 0x4C, + RN5T567_LDO2DAC = 0x4D, + RN5T567_LDO3DAC = 0x4E, + RN5T567_LDO4DAC = 0x4F, + RN5T567_LDO5DAC = 0x50, + + RN5T567_LDORTC1DAC = 0x56, + RN5T567_LDORTC2DAC = 0x57, + + RN5T567_LDO1DAC_SLP = 0x58, + RN5T567_LDO2DAC_SLP = 0x59, + RN5T567_LDO3DAC_SLP = 0x5A, + RN5T567_LDO4DAC_SLP = 0x5B, + RN5T567_LDO5DAC_SLP = 0x5C, + + RN5T567_IOSEL = 0x90, + RN5T567_IOOUT = 0x91, + RN5T567_GPEDGE1 = 0x92, + RN5T567_EN_GPIR = 0x94, + RN5T567_IR_GPR = 0x95, + RN5T567_IR_GPF = 0x96, + RN5T567_MON_IOIN = 0x97, + RN5T567_GPLED_FUNC = 0x98, + RN5T567_INTPOL = 0x9C, + RN5T567_INTEN = 0x9D, + RN5T567_INTMON = 0x9E, + + RN5T567_PREVINDAC = 0xB0, + RN5T567_OVTEMP = 0xBC, + + RN5T567_NUM_OF_REGS = 0xBF, +}; + +#endif diff --git a/include/s_record.h b/include/s_record.h index 6db7174..81245ba 100644 --- a/include/s_record.h +++ b/include/s_record.h @@ -29,7 +29,7 @@ * 2 data record with 24-bit address * 3 data record with 32-bit address * 4 symbol record (LSI extension) - * 5 number of data records in preceeding block + * 5 number of data records in preceding block * 6 unused * 7 ending record for S3 records * 8 ending record for S2 records diff --git a/include/search.h b/include/search.h index 343dbc3..402dfd8 100644 --- a/include/search.h +++ b/include/search.h @@ -12,8 +12,8 @@ * Copyright (C) 2010-2013 Wolfgang Denk <wd@denx.de> */ -#ifndef _SEARCH_H -#define _SEARCH_H 1 +#ifndef _SEARCH_H_ +#define _SEARCH_H_ #include <stddef.h> @@ -25,7 +25,7 @@ enum env_op { env_op_overwrite, }; -/* Action which shall be performed in the call the hsearch. */ +/* Action which shall be performed in the call to hsearch. */ typedef enum { FIND, ENTER @@ -45,7 +45,7 @@ struct _ENTRY; /* * Family of hash table handling functions. The functions also * have reentrant counterparts ending with _r. The non-reentrant - * functions all work on a signle internal hashing table. + * functions all work on a single internal hash table. */ /* Data type for reentrant functions. */ @@ -55,38 +55,38 @@ struct hsearch_data { unsigned int filled; /* * Callback function which will check whether the given change for variable - * "item" to "newval" may be applied or not, and possibly apply such change. + * "__item" to "newval" may be applied or not, and possibly apply such change. * When (flag & H_FORCE) is set, it shall not print out any error message and * shall force overwriting of write-once variables. -.* Must return 0 for approval, 1 for denial. + * Must return 0 for approval, 1 for denial. */ int (*change_ok)(const ENTRY *__item, const char *newval, enum env_op, int flag); }; -/* Create a new hashing table which will at most contain NEL elements. */ +/* Create a new hash table which will contain at most "__nel" elements. */ extern int hcreate_r(size_t __nel, struct hsearch_data *__htab); -/* Destroy current internal hashing table. */ +/* Destroy current internal hash table. */ extern void hdestroy_r(struct hsearch_data *__htab); /* - * Search for entry matching ITEM.key in internal hash table. If + * Search for entry matching __item.key in internal hash table. If * ACTION is `FIND' return found entry or signal error by returning * NULL. If ACTION is `ENTER' replace existing data (if any) with - * ITEM.data. + * __item.data. * */ extern int hsearch_r(ENTRY __item, ACTION __action, ENTRY ** __retval, struct hsearch_data *__htab, int __flag); /* - * Search for an entry matching `MATCH'. Otherwise, Same semantics + * Search for an entry matching "__match". Otherwise, Same semantics * as hsearch_r(). */ extern int hmatch_r(const char *__match, int __last_idx, ENTRY ** __retval, struct hsearch_data *__htab); -/* Search and delete entry matching ITEM.key in internal hash table. */ +/* Search and delete entry matching "__key" in internal hash table. */ extern int hdelete_r(const char *__key, struct hsearch_data *__htab, int __flag); @@ -97,8 +97,6 @@ extern ssize_t hexport_r(struct hsearch_data *__htab, /* * nvars: length of vars array * vars: array of strings (variable names) to import (nvars == 0 means all) - * do_apply: whether to call callback function to check the new argument, - * and possibly apply changes (false means accept everything) */ extern int himport_r(struct hsearch_data *__htab, const char *__env, size_t __size, const char __sep, @@ -123,4 +121,4 @@ extern int hwalk_r(struct hsearch_data *__htab, int (*callback)(ENTRY *)); #define H_PROGRAMMATIC (1 << 9) /* indicate that an import is from setenv() */ #define H_ORIGIN_FLAGS (H_INTERACTIVE | H_PROGRAMMATIC) -#endif /* search.h */ +#endif /* _SEARCH_H_ */ diff --git a/include/spi_flash.h b/include/spi_flash.h index d0ce9e7..be2fe3f 100644 --- a/include/spi_flash.h +++ b/include/spi_flash.h @@ -239,7 +239,4 @@ static inline int spi_flash_protect(struct spi_flash *flash, u32 ofs, u32 len, return flash->flash_unlock(flash, ofs, len); } -void spi_boot(void) __noreturn; -void spi_spl_load_image(uint32_t offs, unsigned int size, void *vdst); - #endif /* _SPI_FLASH_H_ */ diff --git a/include/spl.h b/include/spl.h index 30eda36..e080a82 100644 --- a/include/spl.h +++ b/include/spl.h @@ -49,6 +49,7 @@ struct spl_load_info { /** * spl_load_simple_fit() - Loads a fit image from a device. + * @spl_image: Image description to set up * @info: Structure containing the information required to load data. * @sector: Sector number where FIT image is located in the device * @fdt: Pointer to the copied FIT header. @@ -57,66 +58,146 @@ struct spl_load_info { * specified load address and copies the dtb to end of u-boot image. * Returns 0 on success. */ -int spl_load_simple_fit(struct spl_load_info *info, ulong sector, void *fdt); +int spl_load_simple_fit(struct spl_image_info *spl_image, + struct spl_load_info *info, ulong sector, void *fdt); #define SPL_COPY_PAYLOAD_ONLY 1 -extern struct spl_image_info spl_image; - /* SPL common functions */ void preloader_console_init(void); u32 spl_boot_device(void); u32 spl_boot_mode(const u32 boot_device); -void spl_set_header_raw_uboot(void); -int spl_parse_image_header(const struct image_header *header); -void spl_board_prepare_for_linux(void); -void spl_board_prepare_for_boot(void); -int spl_board_ubi_load_image(u32 boot_device); -void __noreturn jump_to_image_linux(void *arg); -int spl_start_uboot(void); -void spl_display_print(void); -/* NAND SPL functions */ -int spl_nand_load_image(void); +/** + * spl_set_header_raw_uboot() - Set up a standard SPL image structure + * + * This sets up the given spl_image which the standard values obtained from + * config options: CONFIG_SYS_MONITOR_LEN, CONFIG_SYS_UBOOT_START, + * CONFIG_SYS_TEXT_BASE. + * + * @spl_image: Image description to set up + */ +void spl_set_header_raw_uboot(struct spl_image_info *spl_image); -/* OneNAND SPL functions */ -int spl_onenand_load_image(void); +/** + * spl_parse_image_header() - parse the image header and set up info + * + * This parses the legacy image header information at @header and sets up + * @spl_image according to what is found. If no image header is found, then + * a raw image or bootz is assumed. If CONFIG_SPL_PANIC_ON_RAW_IMAGE is + * enabled, then this causes a panic. If CONFIG_SPL_ABORT_ON_RAW_IMAGE is + * enabled then U-Boot gives up. Otherwise U-Boot sets up the image using + * spl_set_header_raw_uboot(), or possibly the bootz header. + * + * @spl_image: Image description to set up + * @header image header to parse + * @return 0 if a header was correctly parsed, -ve on error + */ +int spl_parse_image_header(struct spl_image_info *spl_image, + const struct image_header *header); -/* NOR SPL functions */ -int spl_nor_load_image(void); +void spl_board_prepare_for_linux(void); +void spl_board_prepare_for_boot(void); +int spl_board_ubi_load_image(u32 boot_device); -/* UBI SPL functions */ -int spl_ubi_load_image(u32 boot_device); +/** + * jump_to_image_linux() - Jump to a Linux kernel from SPL + * + * This jumps into a Linux kernel using the information in @spl_image. + * + * @spl_image: Image description to set up + * @arg: Argument to pass to Linux (typically a device tree pointer) + */ +void __noreturn jump_to_image_linux(struct spl_image_info *spl_image, + void *arg); -/* MMC SPL functions */ -int spl_mmc_load_image(u32 boot_device); +/** + * spl_start_uboot() - Check if SPL should start the kernel or U-Boot + * + * This is called by the various SPL loaders to determine whether the board + * wants to load the kernel or U-Boot. This function should be provided by + * the board. + * + * @return 0 if SPL should start the kernel, 1 if U-Boot must be started + */ +int spl_start_uboot(void); -/* YMODEM SPL functions */ -int spl_ymodem_load_image(void); +/** + * spl_display_print() - Display a board-specific message in SPL + * + * If CONFIG_SPL_DISPLAY_PRINT is enabled, U-Boot will call this function + * immediately after displaying the SPL console banner ("U-Boot SPL ..."). + * This function should be provided by the board. + */ +void spl_display_print(void); -/* SPI SPL functions */ -int spl_spi_load_image(void); +/** + * struct spl_boot_device - Describes a boot device used by SPL + * + * @boot_device: A number indicating the BOOT_DEVICE type. There are various + * BOOT_DEVICE... #defines and enums in U-Boot and they are not consistently + * numbered. + * @boot_device_name: Named boot device, or NULL if none. + * + * Note: Additional fields can be added here, bearing in mind that SPL is + * size-sensitive and common fields will be present on all boards. This + * struct can also be used to return additional information about the load + * process if that becomes useful. + */ +struct spl_boot_device { + uint boot_device; + const char *boot_device_name; +}; -/* Ethernet SPL functions */ -int spl_net_load_image(const char *device); +/** + * Holds information about a way of loading an SPL image + * + * @boot_device: Boot device that this loader supports + * @load_image: Function to call to load image + */ +struct spl_image_loader { + uint boot_device; + /** + * load_image() - Load an SPL image + * + * @spl_image: place to put image information + * @bootdev: describes the boot device to load from + */ + int (*load_image)(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev); +}; -/* USB SPL functions */ -int spl_usb_load_image(void); +/* Declare an SPL image loader */ +#define SPL_LOAD_IMAGE(__name) \ + ll_entry_declare(struct spl_image_loader, __name, spl_image_loader) -/* SATA SPL functions */ -int spl_sata_load_image(void); +/* + * __priority is the priority of this method, 0 meaning it will be the top + * choice for this device, 9 meaning it is the bottom choice. + * __boot_device is the BOOT_DEVICE_... value + * __method is the load_image function to call + */ +#define SPL_LOAD_IMAGE_METHOD(__priority, __boot_device, __method) \ + SPL_LOAD_IMAGE(__method ## __priority ## __boot_device) = { \ + .boot_device = __boot_device, \ + .load_image = __method, \ + } /* SPL FAT image functions */ -int spl_load_image_fat(struct blk_desc *block_dev, int partition, +int spl_load_image_fat(struct spl_image_info *spl_image, + struct blk_desc *block_dev, int partition, const char *filename); -int spl_load_image_fat_os(struct blk_desc *block_dev, int partition); +int spl_load_image_fat_os(struct spl_image_info *spl_image, + struct blk_desc *block_dev, int partition); void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image); /* SPL EXT image functions */ -int spl_load_image_ext(struct blk_desc *block_dev, int partition, +int spl_load_image_ext(struct spl_image_info *spl_image, + struct blk_desc *block_dev, int partition, const char *filename); -int spl_load_image_ext_os(struct blk_desc *block_dev, int partition); +int spl_load_image_ext_os(struct spl_image_info *spl_image, + struct blk_desc *block_dev, int partition); /** * spl_init() - Set up device tree and driver model in SPL if enabled @@ -152,4 +233,5 @@ bool spl_was_boot_source(void); * @return 0 on success, otherwise error code */ int spl_dfu_cmd(int usbctrl, char *dfu_alt_info, char *interface, char *devstr); + #endif diff --git a/lib/Makefile b/lib/Makefile index c81bfeb..e3383f4 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_$(SPL_)RSA) += rsa/ obj-$(CONFIG_$(SPL_)SHA1) += sha1.o obj-$(CONFIG_$(SPL_)SHA256) += sha256.o +obj-$(CONFIG_SPL_SAVEENV) += qsort.o obj-$(CONFIG_$(SPL_)OF_LIBFDT) += libfdt/ ifneq ($(CONFIG_SPL_BUILD)$(CONFIG_SPL_OF_PLATDATA),yy) obj-$(CONFIG_$(SPL_)OF_CONTROL) += fdtdec_common.o diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index be6f5e8..792db39 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -475,7 +475,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle, exit_data_size, exit_data); loaded_image_info->exit_status = exit_status; - longjmp(&loaded_image_info->exit_jmp); + longjmp(&loaded_image_info->exit_jmp, 1); panic("EFI application exited"); } diff --git a/lib/gunzip.c b/lib/gunzip.c index bc746d6..832b306 100644 --- a/lib/gunzip.c +++ b/lib/gunzip.c @@ -11,6 +11,7 @@ #include <console.h> #include <image.h> #include <malloc.h> +#include <memalign.h> #include <u-boot/zlib.h> #include <div64.h> @@ -193,7 +194,7 @@ int gzwrite(unsigned char *src, int len, s.next_in = src + i; s.avail_in = payload_size+8; - writebuf = (unsigned char *)malloc(szwritebuf); + writebuf = (unsigned char *)malloc_cache_aligned(szwritebuf); /* decompress until deflate stream ends or end of file */ do { diff --git a/lib/hashtable.c b/lib/hashtable.c index 4e52b36..f088477 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -477,11 +477,11 @@ int hdelete_r(const char *key, struct hsearch_data *htab, int flag) return 1; } +#if !(defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_SAVEENV)) /* * hexport() */ -#ifndef CONFIG_SPL_BUILD /* * Export the data stored in the hash table in linearized form. * @@ -499,7 +499,7 @@ int hdelete_r(const char *key, struct hsearch_data *htab, int flag) * * If the separator character is different from NUL, then any * separator characters and backslash characters in the values will - * be escaped by a preceeding backslash in output. This is needed for + * be escaped by a preceding backslash in output. This is needed for * example to enable multi-line values, especially when the output * shall later be parsed (for example, for re-import). * diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf index 01a739d..2f85eb9 100644 --- a/scripts/Makefile.autoconf +++ b/scripts/Makefile.autoconf @@ -46,7 +46,7 @@ quiet_cmd_autoconf_dep = GEN $@ -MQ include/config/auto.conf $(srctree)/include/common.h > $@ || { \ rm $@; false; \ } -include/autoconf.mk.dep: FORCE +include/autoconf.mk.dep: include/config.h FORCE $(call cmd,autoconf_dep) # We are migrating from board headers to Kconfig little by little. @@ -58,32 +58,44 @@ include/autoconf.mk.dep: FORCE # same CONFIG macros quiet_cmd_autoconf = GEN $@ cmd_autoconf = \ - $(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && { \ - sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp | \ + sed -n -f $(srctree)/tools/scripts/define2mk.sed $< | \ while read line; do \ if [ -n "${KCONFIG_IGNORE_DUPLICATES}" ] || \ ! grep -q "$${line%=*}=" include/config/auto.conf; then \ echo "$$line"; \ fi \ - done > $@; \ - rm $@.tmp; \ - } || { \ - rm $@.tmp; false; \ + done > $@ + +quiet_cmd_u_boot_cfg = CFG $@ + cmd_u_boot_cfg = \ + $(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && { \ + grep 'define CONFIG_' $@.tmp > $@; \ + rm $@.tmp; \ + } || { \ + rm $@.tmp; false; \ } -include/autoconf.mk: FORCE - $(call cmd,autoconf) +u-boot.cfg: include/config.h FORCE + $(call cmd,u_boot_cfg) -spl/include/autoconf.mk: FORCE +spl/u-boot.cfg: include/config.h FORCE $(Q)mkdir -p $(dir $@) - $(call cmd,autoconf,-DCONFIG_SPL_BUILD) + $(call cmd,u_boot_cfg,-DCONFIG_SPL_BUILD) -tpl/include/autoconf.mk: FORCE +tpl/u-boot.cfg: include/config.h FORCE $(Q)mkdir -p $(dir $@) - $(call cmd,autoconf,-DCONFIG_SPL_BUILD -DCONFIG_TPL_BUILD) + $(call cmd,u_boot_cfg,-DCONFIG_SPL_BUILD -DCONFIG_TPL_BUILD) + +include/autoconf.mk: u-boot.cfg + $(call cmd,autoconf) -include/autoconf.mk include/autoconf.mk.dep \ - spl/include/autoconf.mk tpl/include/autoconf.mk: include/config.h +spl/include/autoconf.mk: spl/u-boot.cfg + $(Q)mkdir -p $(dir $@) + $(call cmd,autoconf) + +tpl/include/autoconf.mk: tpl/u-boot.cfg + $(Q)mkdir -p $(dir $@) + $(call cmd,autoconf) # include/config.h # Prior to Kconfig, it was generated by mkconfig. Now it is created here. diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 4febc6b..e8cf9f3 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -156,7 +156,7 @@ spl/boot.bin: $(obj)/u-boot-spl.bin FORCE $(call if_changed,mkimage) endif -ALL-y += $(obj)/$(SPL_BIN).bin $(obj)/$(SPL_BIN).cfg +ALL-y += $(obj)/$(SPL_BIN).bin ifdef CONFIG_SAMSUNG ALL-y += $(obj)/$(BOARD)-spl.bin @@ -216,24 +216,6 @@ quiet_cmd_fdtgrep = FDTGREP $@ $(obj)/$(SPL_BIN).dtb: dts/dt.dtb $(objtree)/tools/fdtgrep FORCE $(call if_changed,fdtgrep) -quiet_cmd_cpp_cfg = CFG $@ -cmd_cpp_cfg = $(CPP) -Wp,-MD,$(depfile) $(cpp_flags) $(LDPPFLAGS) -ansi \ - -DDO_DEPS_ONLY -D__ASSEMBLY__ -x assembler-with-cpp -P -dM -E -o $@ $< - -# If .u-boot.cfg.d is still present, then either: -# a) The previous build used a Makefile that used if_changed rather than -# if_changed_dep when building u-boot.cfg, and hence any later builds will -# be unaware of the dependencies for u-boot.cfg. In this case, we must -# delete u-boot.cfg to force it and .u-boot.cfg.cmd to be rebuilt the -# correct way. -# b) The previous build failed or was interrupted while building u-boot.cfg, -# so deleting u-boot.cfg isn't going to cause any additional work. -ifneq ($(wildcard $(obj)/.$(SPL_BIN).d),) - unused := $(shell rm -f $(obj)/$(SPL_BIN).cfg) -endif -$(obj)/$(SPL_BIN).cfg: include/config.h FORCE - $(call if_changed_dep,cpp_cfg) - pythonpath = PYTHONPATH=tools quiet_cmd_dtocc = DTOC C $@ diff --git a/scripts/build-whitelist.sh b/scripts/build-whitelist.sh index 7cf7a66..f169eaa 100755 --- a/scripts/build-whitelist.sh +++ b/scripts/build-whitelist.sh @@ -45,7 +45,18 @@ cat `find . -name "Kconfig*"` |sed -n \ # Use only the options that are present in the first file but not the second. comm -23 scripts/config_whitelist.txt.tmp1 scripts/config_whitelist.txt.tmp2 \ - |sort |uniq >scripts/config_whitelist.txt -rm scripts/config_whitelist.txt.tmp1 scripts/config_whitelist.txt.tmp2 + |sort |uniq >scripts/config_whitelist.txt.tmp3 + +# If scripts/config_whitelist.txt already exists, take the intersection of the +# current list and the new one. We do not want to increase whitelist options. +if [ -r scripts/config_whitelist.txt ]; then + comm -12 scripts/config_whitelist.txt.tmp3 scripts/config_whitelist.txt \ + > scripts/config_whitelist.txt.tmp4 + mv scripts/config_whitelist.txt.tmp4 scripts/config_whitelist.txt +else + mv scripts/config_whitelist.txt.tmp3 scripts/config_whitelist.txt +fi + +rm scripts/config_whitelist.txt.tmp* unset LC_ALL LC_COLLATE diff --git a/scripts/check-config.sh b/scripts/check-config.sh index 28c8fe9..6618dfb 100755 --- a/scripts/check-config.sh +++ b/scripts/check-config.sh @@ -5,13 +5,8 @@ # Check that the u-boot.cfg file provided does not introduce any new # ad-hoc CONFIG options # -# You can generate the list of current ad-hoc CONFIG options (those which are -# not in Kconfig) with this command: -# -# export LC_ALL=C LC_COLLATE=C -# git grep CONFIG_ |tr ' \t' '\n\n' |sed -n 's/^\(CONFIG_[A-Z0-9_]*\).*/\1/p' \ -# |sort |uniq >scripts/config_whitelist.txt; -# unset LC_ALL LC_COLLATE +# Use scripts/build-whitelist.sh to generate the list of current ad-hoc +# CONFIG options (those which are not in Kconfig). # Usage # check-config.sh <path to u-boot.cfg> <path to whitelist file> <source dir> diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 24831b3..84f5756 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -4263,7 +4263,7 @@ sub process { } } -# check for case / default statements not preceeded by break/fallthrough/switch +# check for case / default statements not preceded by break/fallthrough/switch if ($line =~ /^.\s*(?:case\s+(?:$Ident|$Constant)\s*|default):/) { my $has_break = 0; my $has_statement = 0; @@ -4284,7 +4284,7 @@ sub process { } if (!$has_break && $has_statement) { WARN("MISSING_BREAK", - "Possible switch case/default not preceeded by break or fallthrough comment\n" . $herecurr); + "Possible switch case/default not preceded by break or fallthrough comment\n" . $herecurr); } } diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index d717103..04e9536 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1,4 +1,3 @@ -CONFIG_ CONFIG_16BIT CONFIG_33 CONFIG_400MHZ_MODE @@ -890,7 +889,6 @@ CONFIG_DMC_DDRTR2 CONFIG_DNET_AUTONEG_TIMEOUT CONFIG_DNP5370_EXT_WD_DISABLE CONFIG_DOS_PARTITION -CONFIG_DPLL_SSC_RATE_1PER CONFIG_DP_DDR_CTRL CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR CONFIG_DP_DDR_NUM_CTRLS @@ -1252,10 +1250,8 @@ CONFIG_FLASH_VERIFY CONFIG_FMAN_ENET CONFIG_FM_PLAT_CLK_DIV CONFIG_FO300 -CONFIG_FOO CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32 CONFIG_FORMIKE -CONFIG_FPGA CONFIG_FPGA_ALTERA CONFIG_FPGA_COUNT CONFIG_FPGA_CYCLON2 @@ -1264,7 +1260,6 @@ CONFIG_FPGA_SOCFPGA CONFIG_FPGA_SPARTAN2 CONFIG_FPGA_SPARTAN3 CONFIG_FPGA_STRATIX_V -CONFIG_FPGA_XILINX CONFIG_FPGA_ZYNQPL CONFIG_FSLDMAFEC CONFIG_FSL_CADMUS @@ -1653,7 +1648,6 @@ CONFIG_ICACHE CONFIG_ICACHE_OFF CONFIG_ICON CONFIG_ICS307_REFCLK_HZ -CONFIG_IDENT_STRING CONFIG_IDE_8xx_DIRECT CONFIG_IDE_8xx_PCCARD CONFIG_IDE_INIT_POSTRESET @@ -1726,7 +1720,6 @@ CONFIG_IRAM_TOP CONFIG_IRDA_BASE CONFIG_ISO_PARTITION CONFIG_ISP1362_USB -CONFIG_IS_ CONFIG_IS_BUILTIN CONFIG_IS_ENABLED CONFIG_IS_INVALID @@ -3983,8 +3976,6 @@ CONFIG_SCSI_SYM53C8XX CONFIG_SC_TIMER_CLK CONFIG_SDCARD CONFIG_SDHCI -CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT -CONFIG_SDHCI_CMD_MAX_TIMEOUT CONFIG_SDRAM_BANK0 CONFIG_SDRAM_BANK1 CONFIG_SDRAM_ECC @@ -4243,7 +4234,6 @@ CONFIG_SPL_BOOTROM_SAVE CONFIG_SPL_BOOT_DEVICE CONFIG_SPL_BSS_MAX_SIZE CONFIG_SPL_BSS_START_ADDR -CONFIG_SPL_BUILD CONFIG_SPL_CMT CONFIG_SPL_CMT_DEBUG CONFIG_SPL_COMMON_INIT_DDR @@ -4251,7 +4241,6 @@ CONFIG_SPL_CONSOLE CONFIG_SPL_DISPLAY_PRINT CONFIG_SPL_ETH_DEVICE CONFIG_SPL_FLUSH_IMAGE -CONFIG_SPL_FOO CONFIG_SPL_FRAMEWORK CONFIG_SPL_FSL_PBL CONFIG_SPL_FS_LOAD_ARGS_NAME @@ -7920,7 +7909,6 @@ CONFIG_SYS_XIMG_LEN CONFIG_SYS_XLB_PIPELINING CONFIG_SYS_XSVF_DEFAULT_ADDR CONFIG_SYS_XWAY_EBU_BOOTCFG -CONFIG_SYS_XXX CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_i2C_FSL @@ -7990,7 +7978,6 @@ CONFIG_TI_SPI_MMAP CONFIG_TMU_CMD_DTT CONFIG_TMU_TIMER CONFIG_TOTAL5200 -CONFIG_TPL_BUILD CONFIG_TPL_DRIVERS_MISC_SUPPORT CONFIG_TPL_PAD_TO CONFIG_TPM_TIS_BASE_ADDRESS @@ -8404,6 +8391,3 @@ CONFIG_ZYNQ_SDHCI_MAX_FREQ CONFIG_ZYNQ_SDHCI_MIN_FREQ CONFIG_ZYNQ_SERIAL CONFIG_eTSEC_MDIO_BUS -CONFIG_n -CONFIG_prefix -CONFIG_xxx diff --git a/scripts/get_default_envs.sh b/scripts/get_default_envs.sh new file mode 100755 index 0000000..7955db6 --- /dev/null +++ b/scripts/get_default_envs.sh @@ -0,0 +1,34 @@ +#! /bin/bash +# +# Copyright (C) 2016, Lukasz Majewski <l.majewski@majess.pl> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# This file extracts default envs from built u-boot +# usage: get_default_envs.sh > u-boot-env-default.txt +set -ue + +ENV_OBJ_FILE="env_common.o" +ENV_OBJ_FILE_COPY="copy_${ENV_OBJ_FILE}" + +echoerr() { echo "$@" 1>&2; } + +path=$(readlink -f $0) +env_obj_file_path=$(find ${path%/scripts*} -not -path "*/spl/*" \ + -name "${ENV_OBJ_FILE}") +[ -z "${env_obj_file_path}" ] && \ + { echoerr "File '${ENV_OBJ_FILE}' not found!"; exit 1; } + +cp ${env_obj_file_path} ${ENV_OBJ_FILE_COPY} + +# NOTE: objcopy saves its output to file passed in +# (copy_env_common.o in this case) +objcopy -O binary -j ".rodata.default_environment" ${ENV_OBJ_FILE_COPY} + +# Replace default '\0' with '\n' and sort entries +tr '\0' '\n' < ${ENV_OBJ_FILE_COPY} | sort -u + +rm ${ENV_OBJ_FILE_COPY} + +exit 0 diff --git a/tools/Makefile b/tools/Makefile index 421414b..e6f7993 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -89,6 +89,7 @@ dumpimage-mkimage-objs := aisimage.o \ os_support.o \ pblimage.o \ pbl_crc32.o \ + vybridimage.o \ $(ROCKCHIP_OBS) \ socfpgaimage.o \ lib/sha1.o \ diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index d27f57e..3dc0d53 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -643,16 +643,28 @@ int fw_parse_script(char *fname, struct env_opts *opts) return ret; } +/** + * environment_end() - compute offset of first byte right after environemnt + * @dev - index of enviroment buffer + * Return: + * device offset of first byte right after environemnt + */ +off_t environment_end(int dev) +{ + /* environment is block aligned */ + return DEVOFFSET(dev) + ENVSECTORS(dev) * DEVESIZE(dev); +} + /* * Test for bad block on NAND, just returns 0 on NOR, on NAND: * 0 - block is good * > 0 - block is bad * < 0 - failed to test */ -static int flash_bad_block (int fd, uint8_t mtd_type, loff_t *blockstart) +static int flash_bad_block(int fd, uint8_t mtd_type, loff_t blockstart) { if (mtd_type == MTD_NANDFLASH) { - int badblock = ioctl (fd, MEMGETBADBLOCK, blockstart); + int badblock = ioctl(fd, MEMGETBADBLOCK, &blockstart); if (badblock < 0) { perror ("Cannot read bad block mark"); @@ -662,7 +674,7 @@ static int flash_bad_block (int fd, uint8_t mtd_type, loff_t *blockstart) if (badblock) { #ifdef DEBUG fprintf (stderr, "Bad block at 0x%llx, skipping\n", - (unsigned long long) *blockstart); + (unsigned long long)blockstart); #endif return badblock; } @@ -677,13 +689,12 @@ static int flash_bad_block (int fd, uint8_t mtd_type, loff_t *blockstart) * the DEVOFFSET (dev) block. On NOR the loop is only run once. */ static int flash_read_buf (int dev, int fd, void *buf, size_t count, - off_t offset, uint8_t mtd_type) + off_t offset) { size_t blocklen; /* erase / write length - one block on NAND, 0 on NOR */ size_t processed = 0; /* progress counter */ size_t readlen = count; /* current read length */ - off_t top_of_range; /* end of the last block we may use */ off_t block_seek; /* offset inside the current block to the start of the data */ loff_t blockstart; /* running start of the current block - @@ -695,35 +706,27 @@ static int flash_read_buf (int dev, int fd, void *buf, size_t count, /* Offset inside a block */ block_seek = offset - blockstart; - if (mtd_type == MTD_NANDFLASH) { + if (DEVTYPE(dev) == MTD_NANDFLASH) { /* * NAND: calculate which blocks we are reading. We have * to read one block at a time to skip bad blocks. */ blocklen = DEVESIZE (dev); - /* - * To calculate the top of the range, we have to use the - * global DEVOFFSET (dev), which can be different from offset - */ - top_of_range = ((DEVOFFSET(dev) / blocklen) + - ENVSECTORS (dev)) * blocklen; - /* Limit to one block for the first read */ if (readlen > blocklen - block_seek) readlen = blocklen - block_seek; } else { blocklen = 0; - top_of_range = offset + count; } /* This only runs once on NOR flash */ while (processed < count) { - rc = flash_bad_block (fd, mtd_type, &blockstart); + rc = flash_bad_block(fd, DEVTYPE(dev), blockstart); if (rc < 0) /* block test failed */ return -1; - if (blockstart + block_seek + readlen > top_of_range) { + if (blockstart + block_seek + readlen > environment_end(dev)) { /* End of range is reached */ fprintf (stderr, "Too few good blocks within range\n"); @@ -762,12 +765,12 @@ static int flash_read_buf (int dev, int fd, void *buf, size_t count, } /* - * Write count bytes at offset, but stay within ENVSECTORS (dev) sectors of + * Write count bytes from begin of environment, but stay within + * ENVSECTORS(dev) sectors of * DEVOFFSET (dev). Similar to the read case above, on NOR and dataflash we * erase and write the whole data at once. */ -static int flash_write_buf (int dev, int fd, void *buf, size_t count, - off_t offset, uint8_t mtd_type) +static int flash_write_buf(int dev, int fd, void *buf, size_t count) { void *data; struct erase_info_user erase; @@ -783,7 +786,6 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, below offset */ off_t block_seek; /* offset inside the erase block to the start of the data */ - off_t top_of_range; /* end of the last block we may use */ loff_t blockstart; /* running start of the current block - MEMGETBADBLOCK needs 64 bits */ int rc; @@ -791,27 +793,24 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, /* * For mtd devices only offset and size of the environment do matter */ - if (mtd_type == MTD_ABSENT) { + if (DEVTYPE(dev) == MTD_ABSENT) { blocklen = count; - top_of_range = offset + count; erase_len = blocklen; - blockstart = offset; + blockstart = DEVOFFSET(dev); block_seek = 0; write_total = blocklen; } else { blocklen = DEVESIZE(dev); - top_of_range = ((DEVOFFSET(dev) / blocklen) + - ENVSECTORS(dev)) * blocklen; - - erase_offset = (offset / blocklen) * blocklen; + erase_offset = DEVOFFSET(dev); /* Maximum area we may use */ - erase_len = top_of_range - erase_offset; + erase_len = environment_end(dev) - erase_offset; blockstart = erase_offset; + /* Offset inside a block */ - block_seek = offset - erase_offset; + block_seek = DEVOFFSET(dev) - erase_offset; /* * Data size we actually write: from the start of the block @@ -836,8 +835,7 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, return -1; } - rc = flash_read_buf (dev, fd, data, write_total, erase_offset, - mtd_type); + rc = flash_read_buf(dev, fd, data, write_total, erase_offset); if (write_total != rc) return -1; @@ -864,7 +862,7 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, data = buf; } - if (mtd_type == MTD_NANDFLASH) { + if (DEVTYPE(dev) == MTD_NANDFLASH) { /* * NAND: calculate which blocks we are writing. We have * to write one block at a time to skip bad blocks. @@ -878,11 +876,11 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, /* This only runs once on NOR flash and SPI-dataflash */ while (processed < write_total) { - rc = flash_bad_block (fd, mtd_type, &blockstart); + rc = flash_bad_block(fd, DEVTYPE(dev), blockstart); if (rc < 0) /* block test failed */ return rc; - if (blockstart + erasesize > top_of_range) { + if (blockstart + erasesize > environment_end(dev)) { fprintf (stderr, "End of range reached, aborting\n"); return -1; } @@ -892,11 +890,11 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, continue; } - if (mtd_type != MTD_ABSENT) { + if (DEVTYPE(dev) != MTD_ABSENT) { erase.start = blockstart; ioctl(fd, MEMUNLOCK, &erase); /* These do not need an explicit erase cycle */ - if (mtd_type != MTD_DATAFLASH) + if (DEVTYPE(dev) != MTD_DATAFLASH) if (ioctl(fd, MEMERASE, &erase) != 0) { fprintf(stderr, "MTD erase error on %s: %s\n", @@ -923,7 +921,7 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, return -1; } - if (mtd_type != MTD_ABSENT) + if (DEVTYPE(dev) != MTD_ABSENT) ioctl(fd, MEMLOCK, &erase); processed += erasesize; @@ -1010,8 +1008,7 @@ static int flash_write (int fd_current, int fd_target, int dev_target) #endif rc = flash_write_buf(dev_target, fd_target, environment.image, - CUR_ENVSIZE, DEVOFFSET(dev_target), - DEVTYPE(dev_target)); + CUR_ENVSIZE); if (rc < 0) return rc; @@ -1035,7 +1032,7 @@ static int flash_read (int fd) int rc; rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE, - DEVOFFSET(dev_current), DEVTYPE(dev_current)); + DEVOFFSET(dev_current)); if (rc != CUR_ENVSIZE) return -1; diff --git a/tools/env/fw_env.h b/tools/env/fw_env.h index 436eca9..05588ab 100644 --- a/tools/env/fw_env.h +++ b/tools/env/fw_env.h @@ -63,6 +63,7 @@ struct env_opts { #endif int aes_flag; /* Is AES encryption used? */ uint8_t aes_key[AES_KEY_LENGTH]; + char *lockname; }; int parse_aes_key(char *key, uint8_t *bin_key); diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c index 7a17b28..443de36 100644 --- a/tools/env/fw_env_main.c +++ b/tools/env/fw_env_main.c @@ -46,6 +46,7 @@ static struct option long_options[] = { {"help", no_argument, NULL, 'h'}, {"script", required_argument, NULL, 's'}, {"noheader", required_argument, NULL, 'n'}, + {"lock", required_argument, NULL, 'l'}, {NULL, 0, NULL, 0} }; @@ -72,6 +73,7 @@ void usage_printenv(void) " -c, --config configuration file, default:" CONFIG_FILE "\n" #endif " -n, --noheader do not repeat variable name in output\n" + " -l, --lock lock node, default:/var/lock\n" "\n"); } @@ -88,6 +90,7 @@ void usage_setenv(void) #ifdef CONFIG_FILE " -c, --config configuration file, default:" CONFIG_FILE "\n" #endif + " -l, --lock lock node, default:/var/lock\n" " -s, --script batch mode to minimize writes\n" "\n" "Examples:\n" @@ -119,7 +122,7 @@ static void parse_common_args(int argc, char *argv[]) env_opts.config_file = CONFIG_FILE; #endif - while ((c = getopt_long(argc, argv, ":a:c:h", long_options, NULL)) != + while ((c = getopt_long(argc, argv, ":a:c:l:h", long_options, NULL)) != EOF) { switch (c) { case 'a': @@ -134,6 +137,9 @@ static void parse_common_args(int argc, char *argv[]) env_opts.config_file = optarg; break; #endif + case 'l': + env_opts.lockname = optarg; + break; case 'h': do_printenv ? usage_printenv() : usage_setenv(); exit(EXIT_SUCCESS); @@ -155,8 +161,8 @@ int parse_printenv_args(int argc, char *argv[]) parse_common_args(argc, argv); - while ((c = getopt_long(argc, argv, "a:c:ns:h", long_options, NULL)) != - EOF) { + while ((c = getopt_long(argc, argv, "a:c:ns:l:h", long_options, NULL)) + != EOF) { switch (c) { case 'n': noheader = 1; @@ -164,6 +170,7 @@ int parse_printenv_args(int argc, char *argv[]) case 'a': case 'c': case 'h': + case 'l': /* ignore common options */ break; default: /* '?' */ @@ -181,8 +188,8 @@ int parse_setenv_args(int argc, char *argv[]) parse_common_args(argc, argv); - while ((c = getopt_long(argc, argv, "a:c:ns:h", long_options, NULL)) != - EOF) { + while ((c = getopt_long(argc, argv, "a:c:ns:l:h", long_options, NULL)) + != EOF) { switch (c) { case 's': script_file = optarg; @@ -190,6 +197,7 @@ int parse_setenv_args(int argc, char *argv[]) case 'a': case 'c': case 'h': + case 'l': /* ignore common options */ break; default: /* '?' */ @@ -203,7 +211,7 @@ int parse_setenv_args(int argc, char *argv[]) int main(int argc, char *argv[]) { - const char *lockname = "/var/lock/" CMD_PRINTENV ".lock"; + char *lockname = "/var/lock/" CMD_PRINTENV ".lock"; int lockfd = -1; int retval = EXIT_SUCCESS; char *_cmdname; @@ -235,6 +243,18 @@ int main(int argc, char *argv[]) argc -= optind; argv += optind; + if (env_opts.lockname) { + lockname = malloc(sizeof(env_opts.lockname) + + sizeof(CMD_PRINTENV) + 10); + if (!lockname) { + fprintf(stderr, "Unable allocate memory"); + exit(EXIT_FAILURE); + } + + sprintf(lockname, "%s/%s.lock", + env_opts.lockname, CMD_PRINTENV); + } + lockfd = open(lockname, O_WRONLY | O_CREAT | O_TRUNC, 0666); if (-1 == lockfd) { fprintf(stderr, "Error opening lock file %s\n", lockname); @@ -260,6 +280,9 @@ int main(int argc, char *argv[]) } } + if (env_opts.lockname) + free(lockname); + flock(lockfd, LOCK_UN); close(lockfd); return retval; diff --git a/tools/fdtgrep.c b/tools/fdtgrep.c index 8d3fef4..b907827 100644 --- a/tools/fdtgrep.c +++ b/tools/fdtgrep.c @@ -405,7 +405,7 @@ static int display_fdt_by_regions(struct display_info *disp, const void *blob, * The output of this function may or may not be a valid FDT. To ensure it * is, these disp->flags must be set: * - * FDT_REG_SUPERNODES: ensures that subnodes are preceeded by their + * FDT_REG_SUPERNODES: ensures that subnodes are preceded by their * parents. Without this option, fragments of subnode data may be * output without the supernodes above them. This is useful for * hashing but cannot produce a valid FDT. diff --git a/tools/vybridimage.c b/tools/vybridimage.c new file mode 100644 index 0000000..a31fc10 --- /dev/null +++ b/tools/vybridimage.c @@ -0,0 +1,164 @@ +/* + * Image manipulator for Vybrid SoCs + * + * Derived from vybridimage.c + * + * (C) Copyright 2016 DENX Software Engineering GmbH + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "imagetool.h" +#include <compiler.h> +#include <image.h> + +/* + * NAND page 0 boot header + */ + +struct nand_page_0_boot_header { + union { + uint32_t fcb[128]; + uint8_t fcb_bytes[512]; + }; /* 0x00000000 - 0x000001ff */ + uint8_t sw_ecc[512]; /* 0x00000200 - 0x000003ff */ + uint32_t padding[65280]; /* 0x00000400 - 0x0003ffff */ + uint8_t ivt_prefix[1024]; /* 0x00040000 - 0x000403ff */ +}; + +/* signature byte for a readable block */ + +static struct nand_page_0_boot_header vybridimage_header; + +static int vybridimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_VYBRIDIMAGE) + return EXIT_SUCCESS; + return EXIT_FAILURE; +} + +static uint8_t vybridimage_sw_ecc(uint8_t byte) +{ + uint8_t bit0 = (byte & (1 << 0)) ? 1 : 0; + uint8_t bit1 = (byte & (1 << 1)) ? 1 : 0; + uint8_t bit2 = (byte & (1 << 2)) ? 1 : 0; + uint8_t bit3 = (byte & (1 << 3)) ? 1 : 0; + uint8_t bit4 = (byte & (1 << 4)) ? 1 : 0; + uint8_t bit5 = (byte & (1 << 5)) ? 1 : 0; + uint8_t bit6 = (byte & (1 << 6)) ? 1 : 0; + uint8_t bit7 = (byte & (1 << 7)) ? 1 : 0; + uint8_t res = 0; + + res |= ((bit6 ^ bit5 ^ bit3 ^ bit2) << 0); + res |= ((bit7 ^ bit5 ^ bit4 ^ bit2 ^ bit1) << 1); + res |= ((bit7 ^ bit6 ^ bit5 ^ bit1 ^ bit0) << 2); + res |= ((bit7 ^ bit4 ^ bit3 ^ bit0) << 3); + res |= ((bit6 ^ bit4 ^ bit3 ^ bit2 ^ bit1 ^ bit0) << 4); + + return res; +} + +static int vybridimage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + struct nand_page_0_boot_header *hdr = + (struct nand_page_0_boot_header *)ptr; + int idx; + + if (hdr->fcb[1] != 0x46434220) + return -1; + if (hdr->fcb[2] != 1) + return -1; + if (hdr->fcb[7] != 64) + return -1; + if (hdr->fcb[14] != 6) + return -1; + if (hdr->fcb[30] != 0x0001ff00) + return -1; + if (hdr->fcb[43] != 1) + return -1; + if (hdr->fcb[54] != 0) + return -1; + if (hdr->fcb[55] != 8) + return -1; + + /* check software ECC */ + for (idx = 0; idx < sizeof(hdr->fcb_bytes); idx++) { + uint8_t sw_ecc = vybridimage_sw_ecc(hdr->fcb_bytes[idx]); + if (sw_ecc != hdr->sw_ecc[idx]) + return -1; + } + + return 0; +} + +static void vybridimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + struct nand_page_0_boot_header *hdr = + (struct nand_page_0_boot_header *)ptr; + int idx; + + /* fill header with 0x00 for first 56 entries then 0xff */ + memset(&hdr->fcb[0], 0x0, 56*sizeof(uint32_t)); + memset(&hdr->fcb[56], 0xff, 72*sizeof(uint32_t)); + /* fill SW ecc and padding with 0xff */ + memset(&hdr->sw_ecc[0], 0xff, sizeof(hdr->sw_ecc)); + memset(&hdr->padding[0], 0xff, sizeof(hdr->padding)); + /* fill IVT prefix with 0x00 */ + memset(&hdr->ivt_prefix[0], 0x00, sizeof(hdr->ivt_prefix)); + + /* populate fcb */ + hdr->fcb[1] = 0x46434220; /* signature */ + hdr->fcb[2] = 0x00000001; /* version */ + hdr->fcb[5] = 2048; /* page size */ + hdr->fcb[6] = (2048+64); /* page + OOB size */ + hdr->fcb[7] = 64; /* pages per block */ + hdr->fcb[14] = 6; /* ECC mode 6 */ + hdr->fcb[26] = 128; /* fw address (0x40000) in 2K pages */ + hdr->fcb[27] = 128; /* fw address (0x40000) in 2K pages */ + hdr->fcb[30] = 0x0001ff00; /* DBBT search area start address */ + hdr->fcb[33] = 2048; /* BB marker physical offset */ + hdr->fcb[43] = 1; /* DISBBM */ + hdr->fcb[54] = 0; /* DISBB_Search */ + hdr->fcb[55] = 8; /* Bad block search limit */ + + /* compute software ECC */ + for (idx = 0; idx < sizeof(hdr->fcb_bytes); idx++) + hdr->sw_ecc[idx] = vybridimage_sw_ecc(hdr->fcb_bytes[idx]); +} + +static void vybridimage_print_hdr_field(struct nand_page_0_boot_header *hdr, + int idx) +{ + printf("header.fcb[%d] = %08x\n", idx, hdr->fcb[idx]); +} + +static void vybridimage_print_header(const void *ptr) +{ + struct nand_page_0_boot_header *hdr = + (struct nand_page_0_boot_header *)ptr; + int idx; + + for (idx = 0; idx < 56; idx++) + vybridimage_print_hdr_field(hdr, idx); +} + +/* + * vybridimage parameters + */ +U_BOOT_IMAGE_TYPE( + vybridimage, + "Vybrid Boot Image", + sizeof(vybridimage_header), + (void *)&vybridimage_header, + NULL, + vybridimage_verify_header, + vybridimage_print_header, + vybridimage_set_header, + NULL, + vybridimage_check_image_types, + NULL, + NULL +); |