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-rw-r--r--arch/arc/dts/Makefile1
-rw-r--r--arch/arc/dts/axs10x.dts45
-rw-r--r--board/synopsys/axs101/axs101.c12
-rw-r--r--configs/axs101_defconfig11
-rw-r--r--configs/axs103_defconfig11
-rw-r--r--include/configs/axs101.h31
6 files changed, 72 insertions, 39 deletions
diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile
index d481fcd..d4772ec 100644
--- a/arch/arc/dts/Makefile
+++ b/arch/arc/dts/Makefile
@@ -2,6 +2,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
+dtb-$(CONFIG_TARGET_AXS101) += axs10x.dtb
dtb-$(CONFIG_TARGET_ARCANGEL4) += arcangel4.dtb
dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb
diff --git a/arch/arc/dts/axs10x.dts b/arch/arc/dts/axs10x.dts
new file mode 100644
index 0000000..8fe1837
--- /dev/null
+++ b/arch/arc/dts/axs10x.dts
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ console = &uart0;
+ };
+
+ clocks {
+ apbclk: apbclk {
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ uart0: serial0@e0022000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0xe0022000 0x1000>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ };
+
+ ethernet@e0018000 {
+ #interrupt-cells = <1>;
+ compatible = "altr,socfpga-stmmac";
+ reg = < 0xe0018000 0x2000 >;
+ interrupts = < 25 >;
+ interrupt-names = "macirq";
+ phy-mode = "gmii";
+ snps,pbl = < 32 >;
+ clocks = <&apbclk>;
+ clock-names = "stmmaceth";
+ max-speed = <100>;
+ };
+};
diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs101/axs101.c
index aa446b9..84ee2bf 100644
--- a/board/synopsys/axs101/axs101.c
+++ b/board/synopsys/axs101/axs101.c
@@ -7,8 +7,6 @@
#include <common.h>
#include <dwmmc.h>
#include <malloc.h>
-#include <netdev.h>
-#include <phy.h>
#include "axs10x.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -35,16 +33,6 @@ int board_mmc_init(bd_t *bis)
return 0;
}
-int board_eth_init(bd_t *bis)
-{
- if (designware_initialize(ARC_DWGMAC_BASE,
- PHY_INTERFACE_MODE_RGMII) >= 0)
- return 1;
-
- return 0;
-}
-
-
#define AXS_MB_CREG 0xE0011000
int board_early_init_f(void)
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index fdb3149..8e5d2e5 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -1,12 +1,21 @@
CONFIG_ARC=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARC_CACHE_LINE_SHIFT=5
+CONFIG_DM_SERIAL=y
CONFIG_SYS_CLK_FREQ=750000000
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_DEFAULT_DEVICE_TREE="axs10x"
CONFIG_SYS_PROMPT="AXS# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_NETDEVICES=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index b3dbb8d..cbd63fe 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -1,11 +1,20 @@
CONFIG_ARC=y
CONFIG_ISA_ARCV2=y
+CONFIG_DM_SERIAL=y
CONFIG_SYS_CLK_FREQ=50000000
CONFIG_SYS_TEXT_BASE=0x81000000
+CONFIG_DEFAULT_DEVICE_TREE="axs10x"
CONFIG_SYS_PROMPT="AXS# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_NETDEVICES=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_CLK=y
+CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/include/configs/axs101.h b/include/configs/axs101.h
index 450291c..9a7e0dc 100644
--- a/include/configs/axs101.h
+++ b/include/configs/axs101.h
@@ -39,6 +39,8 @@
#define CONFIG_BOARD_TYPES
#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_OF_LIBFDT
+
/*
* NAND Flash configuration
*/
@@ -48,28 +50,14 @@
/*
* UART configuration
- *
- * CONFIG_CONS_INDEX = 1 - Debug UART
- * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
*/
-#define CONFIG_CONS_INDEX 4
+#define CONFIG_DW_SERIAL
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#if (CONFIG_CONS_INDEX == 1)
- /* Debug UART */
-# define CONFIG_SYS_NS16550_CLK 33333000
-#else
- /* FPGA UARTs use different clock */
-# define CONFIG_SYS_NS16550_CLK 33333333
-#endif
-#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000)
-#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
-#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
-#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
+#define CONFIG_SYS_NS16550_CLK 33333333
#define CONFIG_SYS_NS16550_MEM32
-
#define CONFIG_BAUDRATE 115200
+
/*
* I2C configuration
*/
@@ -119,18 +107,11 @@
#define CONFIG_DW_AUTONEG
/*
- * Command line configuration
+ * Commands still not supported in Kconfig
*/
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_FAT
-#define CONFIG_CMD_I2C
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NAND
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_RARP
-
-#define CONFIG_OF_LIBFDT
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS 16