diff options
Diffstat (limited to 'arch/arm/cpu/arm926ejs/pantheon/cpu.c')
| -rw-r--r-- | arch/arm/cpu/arm926ejs/pantheon/cpu.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c index 8b2eafa..db9b348 100644 --- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c +++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c @@ -23,8 +23,8 @@ */ #include <common.h> +#include <asm/arch/cpu.h> #include <asm/arch/pantheon.h> -#include <asm/io.h> #define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1)) #define SET_MRVL_ID (1<<8) @@ -42,6 +42,9 @@ int arch_cpu_init(void) struct panthmpmu_registers *mpmu = (struct panthmpmu_registers*) PANTHEON_MPMU_BASE; + struct panthapmu_registers *apmu = + (struct panthapmu_registers *) PANTHEON_APMU_BASE; + /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */ val = readl(&cpuregs->cpu_conf); val = val | SET_MRVL_ID; @@ -65,6 +68,14 @@ int arch_cpu_init(void) writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi); #endif +#ifdef CONFIG_MV_SDHCI + /* Enable mmc clock */ + writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST, + &apmu->sd1); + writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST, + &apmu->sd3); +#endif + icache_enable(); return 0; |