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-rw-r--r--arch/arm/cpu/armv7/ls102xa/Kconfig47
1 files changed, 47 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 17f1975..28bf778 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -3,6 +3,8 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
+ select SYS_FSL_DDR_BE
+ select SYS_FSL_DDR_VER_50
menu "LS102xA architecture"
depends on ARCH_LS1021A
@@ -22,6 +24,10 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
+config NUM_DDR_CONTROLLERS
+ int "Maximum DDR controllers"
+ default 1
+
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
@@ -34,6 +40,47 @@ config SYS_FSL_SRDS_2
config SYS_HAS_SERDES
bool
+config SYS_FSL_DDR
+ bool "Freescale DDR driver"
+ help
+ Select Freescale General DDR driver, shared between most Freescale
+ PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
+ based Layerscape SoCs (such as ls2080a).
+
+config SYS_FSL_DDR_BE
+ bool
+ default y
+ help
+ Access DDR registers in big-endian.
+
+config SYS_FSL_DDR_VER
+ int
+ default 50 if SYS_FSL_DDR_VER_50
+
+config SYS_FSL_DDR_VER_50
+ bool
+
+config SYS_FSL_DDRC_ARM_GEN3
+ bool
+
+config SYS_FSL_DDRC_GEN4
+ bool
+
+config SYS_FSL_DDR3
+ bool "Freescale DDR3 controller"
+ depends on !SYS_FSL_DDR4
+ select SYS_FSL_DDR
+ select SYS_FSL_DDRC_ARM_GEN3
+ help
+ Enable Freescale DDR3 controller on ARM-based SoCs.
+
+config SYS_FSL_DDR4
+ bool "Freescale DDR4 controller"
+ select SYS_FSL_DDR
+ select SYS_FSL_DDRC_GEN4
+ help
+ Enable Freescale DDR4 controller.
+
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1021A