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Diffstat (limited to 'arch/arm/cpu/armv8/Kconfig')
| -rw-r--r-- | arch/arm/cpu/armv8/Kconfig | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 22dce88..472b2ba 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -3,6 +3,24 @@ if ARM64 config ARMV8_MULTIENTRY bool "Enable multiple CPUs to enter into U-Boot" +config ARMV8_SET_SMPEN + bool "Enable data coherency with other cores in cluster" + help + Say Y here if there is not any trust firmware to set + CPUECTLR_EL1.SMPEN bit before U-Boot. + + For A53, it enables data coherency with other cores in the + cluster, and for A57/A72, it enables receiving of instruction + cache and TLB maintenance operations. + Cortex A53/57/72 cores require CPUECTLR_EL1.SMPEN set even + for single core systems. Unfortunately write access to this + register may be controlled by EL3/EL2 firmware. To be more + precise, by default (if there is EL2/EL3 firmware running) + this register is RO for NS EL1. + This switch can be used to avoid writing to CPUECTLR_EL1, + it can be safely enabled when EL2/EL3 initialized SMPEN bit + or when CPU implementation doesn't include that register. + config ARMV8_SPIN_TABLE bool "Support spin-table enable method" depends on ARMV8_MULTIENTRY && OF_LIBFDT |