diff options
Diffstat (limited to 'arch/arm/cpu/armv8')
-rw-r--r-- | arch/arm/cpu/armv8/Makefile | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Makefile | 21 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 (renamed from arch/arm/cpu/armv8/fsl-lsch3/README) | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c (renamed from arch/arm/cpu/armv8/fsl-lsch3/cpu.c) | 248 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.h (renamed from arch/arm/cpu/armv8/fsl-lsch3/cpu.h) | 2 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fdt.c (renamed from arch/arm/cpu/armv8/fsl-lsch3/fdt.c) | 17 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c (renamed from arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c) | 8 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c (renamed from arch/arm/cpu/armv8/fsl-lsch3/speed.c) | 12 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S (renamed from arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S) | 14 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c (renamed from arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c) | 3 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/mp.c (renamed from arch/arm/cpu/armv8/fsl-lsch3/mp.c) | 16 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c (renamed from arch/arm/cpu/armv8/fsl-lsch3/soc.c) | 35 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/spl.c | 76 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/Makefile | 13 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/mp.h | 38 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-lsch3/speed.h | 7 |
16 files changed, 212 insertions, 302 deletions
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index adb11b3..48c041b 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -15,6 +15,6 @@ obj-y += cache.o obj-y += tlb.o obj-y += transition.o -obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/ +obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/ obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/ obj-$(CONFIG_TARGET_HIKEY) += hisilicon/ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile new file mode 100644 index 0000000..ccb3aa5 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -0,0 +1,21 @@ +# +# Copyright 2014-2015, Freescale Semiconductor +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o +obj-y += lowlevel.o +obj-y += soc.o +obj-$(CONFIG_MP) += mp.o +obj-$(CONFIG_OF_LIBFDT) += fdt.o +obj-$(CONFIG_SPL) += spl.o + +ifneq ($(CONFIG_FSL_LSCH3),) +obj-y += fsl_lsch3_speed.o +obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o +endif + +ifneq ($(CONFIG_LS2085A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o +endif diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 index 08da7e4..03e18f6 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 @@ -1,5 +1,5 @@ # -# Copyright 2014 Freescale Semiconductor +# Copyright 2014-2015 Freescale Semiconductor # # SPDX-License-Identifier: GPL-2.0+ # diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index eb1213e..be7442d 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2014-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -10,34 +10,28 @@ #include <asm/system.h> #include <asm/armv8/mmu.h> #include <asm/io.h> -#include <asm/arch-fsl-lsch3/soc.h> -#include <asm/arch-fsl-lsch3/immap_lsch3.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include <asm/arch/cpu.h> +#include <asm/arch/speed.h> +#ifdef CONFIG_MP +#include <asm/arch/mp.h> +#endif +#include <fm_eth.h> #include <fsl_debug_server.h> #include <fsl-mc/fsl_mc.h> -#include <asm/arch/fsl_serdes.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif -#include "cpu.h" -#include "mp.h" -#include "speed.h" DECLARE_GLOBAL_DATA_PTR; -static struct cpu_type cpu_type_list[] = { -#ifdef CONFIG_LS2085A - CPU_TYPE_ENTRY(LS2085, LS2085, 8), - CPU_TYPE_ENTRY(LS2080, LS2080, 8), - CPU_TYPE_ENTRY(LS2045, LS2045, 4), -#endif -}; - void cpu_name(char *name) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); unsigned int i, svr, ver; - svr = in_le32(&gur->svr); + svr = gur_in32(&gur->svr); ver = SVR_SOC_VER(svr); for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) @@ -54,146 +48,6 @@ void cpu_name(char *name) } #ifndef CONFIG_SYS_DCACHE_OFF - -#define SECTION_SHIFT_L0 39UL -#define SECTION_SHIFT_L1 30UL -#define SECTION_SHIFT_L2 21UL -#define BLOCK_SIZE_L0 0x8000000000 -#define BLOCK_SIZE_L1 0x40000000 -#define BLOCK_SIZE_L2 0x200000 - -#define NUM_OF_ENTRY 512 - -#define TCR_EL2_PS_40BIT (2 << 16) -#define LSCH3_VA_BITS (40) -#define LSCH3_TCR (TCR_TG0_4K | \ - TCR_EL2_PS_40BIT | \ - TCR_SHARED_NON | \ - TCR_ORGN_NC | \ - TCR_IRGN_NC | \ - TCR_T0SZ(LSCH3_VA_BITS)) -#define LSCH3_TCR_FINAL (TCR_TG0_4K | \ - TCR_EL2_PS_40BIT | \ - TCR_SHARED_OUTER | \ - TCR_ORGN_WBWA | \ - TCR_IRGN_WBWA | \ - TCR_T0SZ(LSCH3_VA_BITS)) - -#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 -#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 -#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 -#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 -#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 -#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000 -#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000 -#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 -#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 -#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 -#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 -#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 -#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000 -#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000 -#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000 -#define CONFIG_SYS_FSL_MC_BASE 0x80c000000 -#define CONFIG_SYS_FSL_MC_SIZE 0x4000000 -#define CONFIG_SYS_FSL_NI_BASE 0x810000000 -#define CONFIG_SYS_FSL_NI_SIZE 0x8000000 -#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000 -#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000 -#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000 -#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000 -#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000 -#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000 -#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000 -#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000 -#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000 -#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000 -#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000 -#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000 - -struct sys_mmu_table { - u64 virt_addr; - u64 phys_addr; - u64 size; - u64 memory_type; - u64 share; -}; - -static const struct sys_mmu_table lsch3_early_mmu_table[] = { - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, - /* For IFC Region #1, only the first 4MB is cache-enabled */ - { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, - CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, - CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, - MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, -}; - -static const struct sys_mmu_table lsch3_final_mmu_table[] = { - { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, - { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, - CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, - CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, - CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - /* For QBMAN portal, only the first 64MB is cache-enabled */ - { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, - CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, - CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, - MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, -#ifdef CONFIG_LS2085A - { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, -#endif - { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, - CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, - CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, - CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, - { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, -}; - -struct table_info { - u64 *ptr; - u64 table_base; - u64 entry_size; -}; - /* * Set the block entries according to the information of the table. */ @@ -311,6 +165,7 @@ static inline void early_mmu_setup(void) u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000); u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000); u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000); + struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; /* Invalidate all table entries */ @@ -320,19 +175,21 @@ static inline void early_mmu_setup(void) set_pgtable_table(level0_table, 0, level1_table0); set_pgtable_table(level0_table, 1, level1_table1); set_pgtable_table(level1_table0, 0, level2_table0); + +#ifdef CONFIG_FSL_LSCH3 set_pgtable_table(level1_table0, CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1, level2_table1); - +#endif /* Find the table and fill in the block entries */ - for (i = 0; i < ARRAY_SIZE(lsch3_early_mmu_table); i++) { - if (find_table(&lsch3_early_mmu_table[i], + for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) { + if (find_table(&early_mmu_table[i], &table, level0_table) == 0) { /* * If find_table() returns error, it cannot be dealt * with here. Breakpoint can be added for debugging. */ - set_block_entry(&lsch3_early_mmu_table[i], &table); + set_block_entry(&early_mmu_table[i], &table); /* * If set_block_entry() returns error, it cannot be * dealt with here too. @@ -341,7 +198,9 @@ static inline void early_mmu_setup(void) } el = current_el(); - set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES); + + set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR, + MEMORY_ATTRIBUTES); set_sctlr(get_sctlr() | CR_M); } @@ -353,6 +212,8 @@ static inline void early_mmu_setup(void) * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB. * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB. * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB. + * + * For LSCH3: * Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB. */ static inline void final_mmu_setup(void) @@ -362,7 +223,9 @@ static inline void final_mmu_setup(void) u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000); u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000); u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000); +#ifdef CONFIG_FSL_LSCH3 u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000); +#endif struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; /* Invalidate all table entries */ @@ -372,23 +235,25 @@ static inline void final_mmu_setup(void) set_pgtable_table(level0_table, 0, level1_table0); set_pgtable_table(level0_table, 1, level1_table1); set_pgtable_table(level1_table0, 0, level2_table0); +#ifdef CONFIG_FSL_LSCH3 set_pgtable_table(level1_table0, CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1, level2_table1); +#endif /* Find the table and fill in the block entries */ - for (i = 0; i < ARRAY_SIZE(lsch3_final_mmu_table); i++) { - if (find_table(&lsch3_final_mmu_table[i], + for (i = 0; i < ARRAY_SIZE(final_mmu_table); i++) { + if (find_table(&final_mmu_table[i], &table, level0_table) == 0) { - if (set_block_entry(&lsch3_final_mmu_table[i], + if (set_block_entry(&final_mmu_table[i], &table) != 0) { printf("MMU error: could not set block entry for %p\n", - &lsch3_final_mmu_table[i]); + &final_mmu_table[i]); } } else { printf("MMU error: could not find the table for %p\n", - &lsch3_final_mmu_table[i]); + &final_mmu_table[i]); } } @@ -398,7 +263,8 @@ static inline void final_mmu_setup(void) /* point TTBR to the new table */ el = current_el(); - set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR_FINAL, + + set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL, MEMORY_ATTRIBUTES); /* * MMU is already enabled, just need to invalidate TLB to load the @@ -434,8 +300,9 @@ static inline u32 initiator_type(u32 cluster, int init_id) { struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; - u32 type = in_le32(&gur->tp_ityp[idx]); + u32 type = 0; + type = gur_in32(&gur->tp_ityp[idx]); if (type & TP_ITYP_AV) return type; @@ -450,7 +317,8 @@ u32 cpu_mask(void) do { int j; - cluster = in_le32(&gur->tp_cluster[i].lower); + + cluster = gur_in32(&gur->tp_cluster[i].lower); for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { type = initiator_type(cluster, j); if (type) { @@ -460,7 +328,7 @@ u32 cpu_mask(void) } } i++; - } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + } while ((cluster & TP_CLUSTER_EOC) == 0x0); return mask; } @@ -482,7 +350,8 @@ int fsl_qoriq_core_to_cluster(unsigned int core) do { int j; - cluster = in_le32(&gur->tp_cluster[i].lower); + + cluster = gur_in32(&gur->tp_cluster[i].lower); for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { if (initiator_type(cluster, j)) { if (count == core) @@ -491,7 +360,7 @@ int fsl_qoriq_core_to_cluster(unsigned int core) } } i++; - } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + } while ((cluster & TP_CLUSTER_EOC) == 0x0); return -1; /* cannot identify the cluster */ } @@ -505,7 +374,8 @@ u32 fsl_qoriq_core_to_type(unsigned int core) do { int j; - cluster = in_le32(&gur->tp_cluster[i].lower); + + cluster = gur_in32(&gur->tp_cluster[i].lower); for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { type = initiator_type(cluster, j); if (type) { @@ -515,7 +385,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core) } } i++; - } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC); + } while ((cluster & TP_CLUSTER_EOC) == 0x0); return -1; /* cannot identify the cluster */ } @@ -527,15 +397,13 @@ int print_cpuinfo(void) struct sys_info sysinfo; char buf[32]; unsigned int i, core; - u32 type; + u32 type, rcw; puts("SoC: "); cpu_name(buf); - printf(" %s (0x%x)\n", buf, in_le32(&gur->svr)); - + printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr)); memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); - get_sys_info(&sysinfo); puts("Clock Configuration:"); for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { @@ -551,18 +419,20 @@ int print_cpuinfo(void) printf("\n Bus: %-4s MHz ", strmhz(buf, sysinfo.freq_systembus)); printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); +#ifdef CONFIG_FSL_LSCH3 printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); +#endif puts("\n"); - /* Display the RCW, so that no one gets confused as to what RCW + /* + * Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. */ puts("Reset Configuration Word (RCW):"); for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { - u32 rcw = in_le32(&gur->rcwsr[i]); - + rcw = gur_in32(&gur->rcwsr[i]); if ((i % 4) == 0) - printf("\n %02x:", i * 4); + printf("\n %08x:", i * 4); printf(" %08x", rcw); } puts("\n"); @@ -590,11 +460,13 @@ int cpu_eth_init(bd_t *bis) int arch_early_init_r(void) { - int rv; - rv = fsl_lsch3_wake_seconday_cores(); +#ifdef CONFIG_MP + int rv = 1; + rv = fsl_layerscape_wake_seconday_cores(); if (rv) printf("Did not wake secondary cores\n"); +#endif #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); @@ -605,7 +477,9 @@ int arch_early_init_r(void) int timer_init(void) { u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; +#ifdef CONFIG_FSL_LSCH3 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; +#endif #ifdef COUNTER_FREQUENCY_REAL unsigned long cntfrq = COUNTER_FREQUENCY_REAL; @@ -613,10 +487,12 @@ int timer_init(void) asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory"); #endif +#ifdef CONFIG_FSL_LSCH3 /* Enable timebase for all clusters. * It is safe to do so even some clusters are not enabled. */ out_le32(cltbenr, 0xf); +#endif /* Enable clock for timer * This is a global setting. @@ -632,7 +508,7 @@ void reset_cpu(ulong addr) u32 val; /* Raise RESET_REQ_B */ - val = in_le32(rstcr); + val = scfg_in32(rstcr); val |= 0x02; - out_le32(rstcr, val); + scfg_out32(rstcr, val); } diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h index 2e3312b..8072f3c 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h @@ -1,5 +1,5 @@ /* - * Copyright 2014, Freescale Semiconductor + * Copyright 2014-2015, Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 922e8a0..4839e33 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2014-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,11 +7,16 @@ #include <common.h> #include <libfdt.h> #include <fdt_support.h> -#include <asm/arch-fsl-lsch3/fdt.h> +#include <phy.h> +#ifdef CONFIG_FSL_LSCH3 +#include <asm/arch/fdt.h> +#endif #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif -#include "mp.h" +#ifdef CONFIG_MP +#include <asm/arch/mp.h> +#endif #ifdef CONFIG_MP void ft_fixup_cpu(void *blob) @@ -150,6 +155,7 @@ void append_mmu_masters(void *blob, const char *smmu_path, * for all DPAA2 devices. * */ +#ifdef CONFIG_FSL_LSCH3 static void fdt_fixup_smmu(void *blob) { int nodeoffset; @@ -165,6 +171,7 @@ static void fdt_fixup_smmu(void *blob) fdt_fixup_smmu_pcie(blob); #endif } +#endif void ft_cpu_setup(void *blob, bd_t *bd) { @@ -181,9 +188,11 @@ void ft_cpu_setup(void *blob, bd_t *bd) ft_pci_setup(blob, bd); #endif -#if defined(CONFIG_FSL_ESDHC) +#ifdef CONFIG_FSL_ESDHC fdt_fixup_esdhc(blob, bd); #endif +#ifdef CONFIG_FSL_LSCH3 fdt_fixup_smmu(blob); +#endif } diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index ae08343..2ab8da6 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -1,5 +1,5 @@ /* - * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2014-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,7 +8,7 @@ #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/fsl_serdes.h> -#include <asm/arch-fsl-lsch3/immap_lsch3.h> +#include <asm/arch/soc.h> #include <fsl-mc/ldpaa_wriop.h> #ifdef CONFIG_SYS_FSL_SRDS_1 @@ -35,7 +35,7 @@ int is_serdes_configured(enum srds_prtcl device) int serdes_get_first_lane(u32 sd, enum srds_prtcl device) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - u32 cfg = in_le32(&gur->rcwsr[28]); + u32 cfg = gur_in32(&gur->rcwsr[28]); int i; switch (sd) { @@ -76,7 +76,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map)); - cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask; + cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask; cfg >>= sd_prctl_shift; printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg); diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index d9f137c..4054c3c 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -1,5 +1,5 @@ /* - * Copyright 2014, Freescale Semiconductor, Inc. + * Copyright 2014-2015, Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ * @@ -11,8 +11,8 @@ #include <fsl_ifc.h> #include <asm/processor.h> #include <asm/io.h> -#include <asm/arch-fsl-lsch3/immap_lsch3.h> #include <asm/arch/clock.h> +#include <asm/arch/soc.h> #include "cpu.h" DECLARE_GLOBAL_DATA_PTR; @@ -83,15 +83,15 @@ void get_sys_info(struct sys_info *sys_info) sys_info->freq_ddrbus2 = sysclk; #endif - sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >> + sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK; /* Platform clock is half of platform PLL */ sys_info->freq_systembus /= 2; - sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >> + sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK; - sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >> + sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) & FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK; @@ -118,7 +118,7 @@ void get_sys_info(struct sys_info *sys_info) } #if defined(CONFIG_FSL_IFC) - ccr = in_le32(&ifc_regs.gregs->ifc_ccr); + ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr); ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1; sys_info->freq_localbus = sys_info->freq_systembus / ccr; diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 6b19d36..41e1704 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -1,5 +1,5 @@ /* - * (C) Copyright 2014 Freescale Semiconductor + * (C) Copyright 2014-2015 Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ * @@ -10,11 +10,14 @@ #include <linux/linkage.h> #include <asm/gic.h> #include <asm/macro.h> -#include "mp.h" +#ifdef CONFIG_MP +#include <asm/arch/mp.h> +#endif ENTRY(lowlevel_init) mov x29, lr /* Save LR */ +#ifdef CONFIG_FSL_LSCH3 /* Add fully-coherent masters to DVM domain */ ldr x0, =CCI_MN_BASE ldr x1, =CCI_MN_RNF_NODEID_LIST @@ -81,6 +84,7 @@ ENTRY(lowlevel_init) ldr x0, =CCI_S2_QOS_CONTROL_BASE(20) ldr x1, =0x00FF000C bl ccn504_set_qos +#endif /* Set the SMMU page size in the sACR register */ ldr x1, =SMMU_BASE @@ -106,10 +110,12 @@ ENTRY(lowlevel_init) branch_if_master x0, x1, 2f +#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY) ldr x0, =secondary_boot_func blr x0 -2: +#endif +2: #ifdef CONFIG_FSL_TZPC_BP147 /* Set Non Secure access for all devices protected via TZPC */ ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */ @@ -245,6 +251,7 @@ ENTRY(__asm_flush_l3_cache) ret ENDPROC(__asm_flush_l3_cache) +#ifdef CONFIG_MP /* Keep literals not used by the secondary boot code outside it */ .ltorg @@ -353,3 +360,4 @@ __real_cntfrq: /* Secondary Boot Code ends here */ __secondary_boot_code_size: .quad .-secondary_boot_code +#endif diff --git a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c index 0b79a50..ea3114c 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c @@ -1,12 +1,11 @@ /* - * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2014-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <asm/arch/fsl_serdes.h> -#include <asm/arch-fsl-lsch3/immap_lsch3.h> struct serdes_config { u8 protocol; diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index da7853a..1b13d32 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2014-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,9 +7,8 @@ #include <common.h> #include <asm/io.h> #include <asm/system.h> -#include <asm/io.h> -#include <asm/arch-fsl-lsch3/immap_lsch3.h> -#include "mp.h" +#include <asm/arch/mp.h> +#include <asm/arch/soc.h> DECLARE_GLOBAL_DATA_PTR; @@ -23,7 +22,7 @@ phys_addr_t determine_mp_bootpg(void) return (phys_addr_t)&secondary_boot_code; } -int fsl_lsch3_wake_seconday_cores(void) +int fsl_layerscape_wake_seconday_cores(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); @@ -48,9 +47,10 @@ int fsl_lsch3_wake_seconday_cores(void) (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE)); printf("Waking secondary cores to start from %lx\n", gd->relocaddr); - out_le32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); - out_le32(&gur->bootlocptrl, (u32)gd->relocaddr); - out_le32(&gur->scratchrw[6], 1); + + gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); + gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr); + gur_out32(&gur->scratchrw[6], 1); asm volatile("dsb st" : : : "memory"); rst->brrl = cores; asm volatile("dsb st" : : : "memory"); diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 2538001..73e48a7 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -1,19 +1,18 @@ /* - * Copyright 2015 Freescale Semiconductor + * Copyright 2014-2015 Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <fsl_ifc.h> -#include <nand.h> -#include <spl.h> -#include <asm/arch-fsl-lsch3/soc.h> +#include <asm/arch/soc.h> #include <asm/io.h> #include <asm/global_data.h> DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_LS2085A static void erratum_a008751(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A008751 @@ -77,31 +76,11 @@ void fsl_lsch3_early_init_f(void) init_early_memctl_regs(); /* tighten IFC timing */ erratum_a009203(); } +#endif -#ifdef CONFIG_SPL_BUILD -void board_init_f(ulong dummy) -{ - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - - arch_cpu_init(); - board_early_init_f(); - timer_init(); - env_init(); - gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); - - serial_init(); - console_init_f(); - dram_init(); - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - board_init_r(NULL, 0); -} - -u32 spl_boot_device(void) +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) { - return BOOT_DEVICE_NAND; + return 0; } #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c new file mode 100644 index 0000000..2f30d4b --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -0,0 +1,76 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <asm/io.h> +#include <fsl_ifc.h> +#include <fsl_csu.h> +#include <i2c.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ +#ifdef CONFIG_SPL_MMC_SUPPORT + return BOOT_DEVICE_MMC1; +#endif +#ifdef CONFIG_SPL_NAND_SUPPORT + return BOOT_DEVICE_NAND; +#endif + return 0; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: +#ifdef CONFIG_SPL_FAT_SUPPORT + return MMCSD_MODE_FAT; +#else + return MMCSD_MODE_RAW; +#endif + case BOOT_DEVICE_NAND: + return 0; + default: + puts("spl: error: unsupported device\n"); + hang(); + } +} + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + /* Set global data pointer */ + gd = &gdata; + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); +#ifdef CONFIG_LS2085A + arch_cpu_init(); +#endif +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + board_early_init_f(); + timer_init(); +#ifdef CONFIG_LS2085A + env_init(); +#endif + get_clocks(); + + preloader_console_init(); + +#ifdef CONFIG_SPL_I2C_SUPPORT + i2c_init_all(); +#endif + dram_init(); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + board_init_r(NULL, 0); +} +#endif diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile deleted file mode 100644 index 9f7815b..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright 2014, Freescale Semiconductor -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += cpu.o -obj-y += lowlevel.o -obj-y += soc.o -obj-y += speed.o -obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o -obj-$(CONFIG_MP) += mp.o -obj-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/cpu/armv8/fsl-lsch3/mp.h deleted file mode 100644 index c985d6a..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright 2014, Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _FSL_CH3_MP_H -#define _FSL_CH3_MP_H - -/* -* Each spin table element is defined as -* struct { -* uint64_t entry_addr; -* uint64_t status; -* uint64_t lpid; -* }; -* we pad this struct to 64 bytes so each entry is in its own cacheline -* the actual spin table is an array of these structures -*/ -#define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 -#define SPIN_TABLE_ELEM_STATUS_IDX 1 -#define SPIN_TABLE_ELEM_LPID_IDX 2 -#define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ -#define SPIN_TABLE_ELEM_SIZE 64 - -#define id_to_core(x) ((x & 3) | (x >> 6)) -#ifndef __ASSEMBLY__ -extern u64 __spin_table[]; -extern u64 __real_cntfrq; -extern u64 *secondary_boot_code; -extern size_t __secondary_boot_code_size; -int fsl_lsch3_wake_seconday_cores(void); -void *get_spin_tbl_addr(void); -phys_addr_t determine_mp_bootpg(void); -void secondary_boot_func(void); -int is_core_online(u64 cpu_id); -#endif -#endif /* _FSL_CH3_MP_H */ diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.h b/arch/arm/cpu/armv8/fsl-lsch3/speed.h deleted file mode 100644 index 15af5b9..0000000 --- a/arch/arm/cpu/armv8/fsl-lsch3/speed.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright 2014, Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -void get_sys_info(struct sys_info *sys_info); |