diff options
Diffstat (limited to 'arch/arm/cpu/armv8')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/soc.c | 24 |
2 files changed, 27 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 5dd455c..465976f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -6,6 +6,7 @@ config ARCH_LS1012A select SYS_FSL_DDR_BE select SYS_FSL_MMDC select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_ERRATUM_A009798 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F @@ -19,6 +20,7 @@ config ARCH_LS1043A select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A008850 select SYS_FSL_ERRATUM_A009660 + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009929 select SYS_FSL_ERRATUM_A009942 @@ -44,6 +46,7 @@ config ARCH_LS1046A select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R @@ -73,6 +76,7 @@ config ARCH_LS2080A select SYS_FSL_ERRATUM_A008514 select SYS_FSL_ERRATUM_A008585 select SYS_FSL_ERRATUM_A009635 + select SYS_FSL_ERRATUM_A009798 select SYS_FSL_ERRATUM_A009663 select SYS_FSL_ERRATUM_A009801 select SYS_FSL_ERRATUM_A009803 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 0943e83..c4aaa1a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -1,5 +1,5 @@ /* - * Copyright 2014-2015 Freescale Semiconductor + * Copyright 2014-2017 Freescale Semiconductor * * SPDX-License-Identifier: GPL-2.0+ */ @@ -26,6 +26,25 @@ DECLARE_GLOBAL_DATA_PTR; +static void erratum_a009798(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A009798 +#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A) +u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; +u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4); +scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE); +val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4); +scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE); +val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4); +scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE); +#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A) +u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; +u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4); +scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE); +#endif +#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ +} + bool soc_has_dp_ddr(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -198,6 +217,8 @@ void fsl_lsch3_early_init_f(void) #endif erratum_a008514(); erratum_a008336(); + erratum_a009008(); + erratum_a009798(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. @@ -473,6 +494,7 @@ void fsl_lsch2_early_init_f(void) erratum_a009929(); erratum_a009660(); erratum_a010539(); + erratum_a009798(); } #endif |