diff options
Diffstat (limited to 'arch/arm/cpu')
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 21 | ||||
-rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 4 |
2 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 3a26e88..48812b9 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -68,6 +68,8 @@ config ARCH_LS1088A select SYS_FSL_DDR select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 select SYS_FSL_ERRATUM_A009803 select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010165 @@ -75,6 +77,7 @@ config ARCH_LS1088A select SYS_FSL_ERRATUM_A008850 select SYS_FSL_HAS_CCI400 select SYS_FSL_HAS_DDR4 + select SYS_FSL_HAS_RGMII select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE @@ -427,6 +430,18 @@ config RESV_RAM be at the high end of physical memory. The reserve RAM may be excluded from memory bank(s) passed to OS, or marked as reserved. +config SYS_FSL_EC1 + bool + help + Ethernet controller 1, this is connected to MAC3. + Provides DPAA2 capabilities + +config SYS_FSL_EC2 + bool + help + Ethernet controller 2, this is connected to MAC4. + Provides DPAA2 capabilities + config SYS_FSL_ERRATUM_A008336 bool @@ -463,6 +478,12 @@ config SYS_FSL_ERRATUM_A009798 config SYS_FSL_ERRATUM_A009008 bool + +config SYS_FSL_HAS_RGMII + bool + depends on SYS_FSL_EC1 || SYS_FSL_EC2 + + config SYS_MC_RSV_MEM_ALIGN hex "Management Complex reserved memory alignment" depends on RESV_RAM diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index ec58065..3c9a5ed 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -517,6 +517,10 @@ int arch_early_init_r(void) printf("Did not wake secondary cores\n"); } +#ifdef CONFIG_SYS_FSL_HAS_RGMII + fsl_rgmii_init(); +#endif + #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); #endif |