diff options
Diffstat (limited to 'arch/arm/cpu')
37 files changed, 855 insertions, 246 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index 781d83f..52a6824 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -51,15 +51,6 @@ u32 get_cpu_type(void) } /** - * get_board_rev() - setup to pass kernel board revision information - * returns: 0 for the ATAG REVISION tag value. - */ -u32 __weak get_board_rev(void) -{ - return 0; -} - -/** * get_device_type(): tell if GP/HS/EMU/TST */ u32 get_device_type(void) diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2e6a207..2d55782 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -12,3 +12,7 @@ obj-y += fsl_epu.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o obj-$(CONFIG_SPL) += spl.o + +ifdef CONFIG_ARMV7_PSCI +obj-y += psci.o +endif diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 71a1753..e01d911 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -29,29 +29,30 @@ void ft_fixup_enet_phy_connect_type(void *fdt) char phy[16]; int phy_node; int i = 0; - int enet_id = 0; uint32_t ph; while ((dev = eth_get_dev_by_index(i++)) != NULL) { - if (strstr(dev->name, "eTSEC1")) - enet_id = 0; - else if (strstr(dev->name, "eTSEC2")) - enet_id = 1; - else if (strstr(dev->name, "eTSEC3")) - enet_id = 2; - else + if (strstr(dev->name, "eTSEC1")) { + strcpy(enet, "ethernet0"); + strcpy(phy, "enet0_rgmii_phy"); + } else if (strstr(dev->name, "eTSEC2")) { + strcpy(enet, "ethernet1"); + strcpy(phy, "enet1_rgmii_phy"); + } else if (strstr(dev->name, "eTSEC3")) { + strcpy(enet, "ethernet2"); + strcpy(phy, "enet2_rgmii_phy"); + } else { continue; + } priv = dev->priv; if (priv->flags & TSEC_SGMII) continue; - sprintf(enet, "ethernet%d", enet_id); enet_path = fdt_get_alias(fdt, enet); if (!enet_path) continue; - sprintf(phy, "enet%d_rgmii_phy", enet_id); phy_path = fdt_get_alias(fdt, phy); if (!phy_path) continue; diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S new file mode 100644 index 0000000..cf5cd48 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/psci.S @@ -0,0 +1,126 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Author: Wang Dongsheng <dongsheng.wang@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> + +#include <asm/armv7.h> +#include <asm/arch-armv7/generictimer.h> +#include <asm/psci.h> + +#define SCFG_CORE0_SFT_RST 0x130 +#define SCFG_CORESRENCR 0x204 + +#define DCFG_CCSR_BRR 0x0E4 +#define DCFG_CCSR_SCRATCHRW1 0x200 + + .pushsection ._secure.text, "ax" + + .arch_extension sec + +#define ONE_MS (GENERIC_TIMER_CLK / 1000) +#define RESET_WAIT (30 * ONE_MS) + + @ r1 = target CPU + @ r2 = target PC +.globl psci_cpu_on +psci_cpu_on: + push {lr} + + @ Clear and Get the correct CPU number + @ r1 = 0xf01 + and r1, r1, #0xff + + mov r0, r1 + bl psci_get_cpu_stack_top + str r2, [r0] + dsb + + @ Get DCFG base address + movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff) + movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16) + + @ Detect target CPU state + ldr r2, [r4, #DCFG_CCSR_BRR] + rev r2, r2 + lsr r2, r2, r1 + ands r2, r2, #1 + beq holdoff_release + + @ Reset target CPU + @ Get SCFG base address + movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff) + movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16) + + @ Enable CORE Soft Reset + movw r5, #0 + movt r5, #(1 << 15) + rev r5, r5 + str r5, [r0, #SCFG_CORESRENCR] + + @ Get CPUx offset register + mov r6, #0x4 + mul r6, r6, r1 + add r2, r0, r6 + + @ Do reset on target CPU + movw r5, #0 + movt r5, #(1 << 15) + rev r5, r5 + str r5, [r2, #SCFG_CORE0_SFT_RST] + + @ Wait target CPU up + timer_wait r2, RESET_WAIT + + @ Disable CORE soft reset + mov r5, #0 + str r5, [r0, #SCFG_CORESRENCR] + +holdoff_release: + @ Release on target CPU + ldr r2, [r4, #DCFG_CCSR_BRR] + mov r6, #1 + lsl r6, r6, r1 @ 32 bytes per CPU + + rev r6, r6 + orr r2, r2, r6 + str r2, [r4, #DCFG_CCSR_BRR] + + @ Set secondary boot entry + ldr r6, =psci_cpu_entry + rev r6, r6 + str r6, [r4, #DCFG_CCSR_SCRATCHRW1] + + isb + dsb + + @ Return + mov r0, #ARM_PSCI_RET_SUCCESS + + pop {lr} + bx lr + +.globl psci_cpu_off +psci_cpu_off: + bl psci_cpu_off_common + +1: wfi + b 1b + +.globl psci_arch_init +psci_arch_init: + mov r6, lr + + bl psci_get_cpu_id + bl psci_get_cpu_stack_top + mov sp, r0 + + bx r6 + + .globl psci_text_end +psci_text_end: + .popsection diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index f3725b2..464a5d1 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -26,9 +26,7 @@ ifeq ($(CONFIG_SYS_DCACHE_OFF),) obj-y += omap-cache.o endif -ifeq ($(CONFIG_OMAP34XX),) obj-y += boot-common.o -endif obj-y += lowlevel_init.o obj-y += mem-common.o diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index bbc6bed..5ec46fa 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -17,27 +17,34 @@ #include <asm/arch/sys_proto.h> #include <watchdog.h> #include <scsi.h> +#include <i2c.h> DECLARE_GLOBAL_DATA_PTR; +__weak u32 omap_sys_boot_device(void) +{ + return BOOT_DEVICE_NONE; +} + void save_omap_boot_params(void) { - u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); - u8 boot_device; - u32 dev_desc, dev_data; + u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); + struct omap_boot_parameters *omap_boot_params; + u32 boot_device; + u32 boot_mode; - if ((rom_params < NON_SECURE_SRAM_START) || - (rom_params > NON_SECURE_SRAM_END)) + if ((boot_params < NON_SECURE_SRAM_START) || + (boot_params > NON_SECURE_SRAM_END)) return; - /* - * rom_params can be type casted to omap_boot_parameters and - * used. But it not correct to assume that romcode structure - * encoding would be same as u-boot. So use the defined offsets. - */ - boot_device = *((u8 *)(rom_params + BOOT_DEVICE_OFFSET)); + omap_boot_params = (struct omap_boot_parameters *)boot_params; + + boot_device = omap_boot_params->boot_device; + boot_mode = MMCSD_MODE_UNDEFINED; + + /* Boot device */ -#if defined(BOOT_DEVICE_NAND_I2C) +#ifdef BOOT_DEVICE_NAND_I2C /* * Re-map NAND&I2C boot-device to the "normal" NAND boot-device. * Otherwise the SPL boot IF can't handle this device correctly. @@ -47,61 +54,109 @@ void save_omap_boot_params(void) if (boot_device == BOOT_DEVICE_NAND_I2C) boot_device = BOOT_DEVICE_NAND; #endif - gd->arch.omap_boot_params.omap_bootdevice = boot_device; +#ifdef BOOT_DEVICE_QSPI_4 + /* + * We get different values for QSPI_1 and QSPI_4 being used, but + * don't actually care about this difference. Rather than + * mangle the later code, if we're coming in as QSPI_4 just + * change to the QSPI_1 value. + */ + if (boot_device == BOOT_DEVICE_QSPI_4) + boot_device = BOOT_DEVICE_SPI; +#endif +#if (defined(BOOT_DEVICE_UART) && !defined(CONFIG_SPL_YMODEM_SUPPORT)) || \ + (defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_SUPPORT)) || \ + (defined(BOOT_DEVICE_USBETH) && !defined(CONFIG_SPL_USBETH_SUPPORT)) + /* + * When booting from peripheral booting, the boot device is not usable + * as-is (unless there is support for it), so the boot device is instead + * figured out using the SYS_BOOT pins. + */ + switch (boot_device) { +#ifdef BOOT_DEVICE_UART + case BOOT_DEVICE_UART: +#endif +#ifdef BOOT_DEVICE_USB + case BOOT_DEVICE_USB: +#endif + boot_device = omap_sys_boot_device(); + + /* MMC raw mode will fallback to FS mode. */ + if ((boot_device >= MMC_BOOT_DEVICES_START) && + (boot_device <= MMC_BOOT_DEVICES_END)) + boot_mode = MMCSD_MODE_RAW; - gd->arch.omap_boot_params.ch_flags = - *((u8 *)(rom_params + CH_FLAGS_OFFSET)); + break; + } +#endif + gd->arch.omap_boot_device = boot_device; + + /* Boot mode */ + +#ifdef CONFIG_OMAP34XX if ((boot_device >= MMC_BOOT_DEVICES_START) && (boot_device <= MMC_BOOT_DEVICES_END)) { -#if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX) && \ - !defined(CONFIG_AM43XX) - if ((omap_hw_init_context() == - OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) { - gd->arch.omap_boot_params.omap_bootmode = - *((u8 *)(rom_params + BOOT_MODE_OFFSET)); - } else -#endif - { - dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET)); - dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET)); - gd->arch.omap_boot_params.omap_bootmode = - *((u32 *)(dev_data + BOOT_MODE_OFFSET)); + switch (boot_device) { + case BOOT_DEVICE_MMC1: + boot_mode = MMCSD_MODE_FS; + break; + case BOOT_DEVICE_MMC2: + boot_mode = MMCSD_MODE_RAW; + break; } } - -#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) +#else /* - * We get different values for QSPI_1 and QSPI_4 being used, but - * don't actually care about this difference. Rather than - * mangle the later code, if we're coming in as QSPI_4 just - * change to the QSPI_1 value. + * If the boot device was dynamically changed and doesn't match what + * the bootrom initially booted, we cannot use the boot device + * descriptor to figure out the boot mode. */ - if (gd->arch.omap_boot_params.omap_bootdevice == 11) - gd->arch.omap_boot_params.omap_bootdevice = BOOT_DEVICE_SPI; + if ((boot_device == omap_boot_params->boot_device) && + (boot_device >= MMC_BOOT_DEVICES_START) && + (boot_device <= MMC_BOOT_DEVICES_END)) { + boot_params = omap_boot_params->boot_device_descriptor; + if ((boot_params < NON_SECURE_SRAM_START) || + (boot_params > NON_SECURE_SRAM_END)) + return; + + boot_params = *((u32 *)(boot_params + DEVICE_DATA_OFFSET)); + if ((boot_params < NON_SECURE_SRAM_START) || + (boot_params > NON_SECURE_SRAM_END)) + return; + + boot_mode = *((u32 *)(boot_params + BOOT_MODE_OFFSET)); + + if (boot_mode != MMCSD_MODE_FS && + boot_mode != MMCSD_MODE_RAW) +#ifdef CONFIG_SUPPORT_EMMC_BOOT + boot_mode = MMCSD_MODE_EMMCBOOT; +#else + boot_mode = MMCSD_MODE_UNDEFINED; +#endif + } +#endif + + gd->arch.omap_boot_mode = boot_mode; + +#if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \ + !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX) + + /* CH flags */ + + gd->arch.omap_ch_flags = omap_boot_params->ch_flags; #endif } #ifdef CONFIG_SPL_BUILD u32 spl_boot_device(void) { - return (u32) (gd->arch.omap_boot_params.omap_bootdevice); + return gd->arch.omap_boot_device; } u32 spl_boot_mode(void) { - u32 val = gd->arch.omap_boot_params.omap_bootmode; - - if (val == MMCSD_MODE_RAW) - return MMCSD_MODE_RAW; - else if (val == MMCSD_MODE_FS) - return MMCSD_MODE_FS; - else -#ifdef CONFIG_SUPPORT_EMMC_BOOT - return MMCSD_MODE_EMMCBOOT; -#else - return MMCSD_MODE_UNDEFINED; -#endif + return gd->arch.omap_boot_mode; } void spl_board_init(void) @@ -116,9 +171,12 @@ void spl_board_init(void) /* Prepare console output */ preloader_console_init(); -#ifdef CONFIG_SPL_NAND_SUPPORT +#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT) gpmc_init(); #endif +#ifdef CONFIG_SPL_I2C_SUPPORT + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); +#endif #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) arch_misc_init(); #endif @@ -150,9 +208,11 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) image_entry_noargs_t image_entry = (image_entry_noargs_t) spl_image->entry_point; + u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); + debug("image entry point: 0x%X\n", spl_image->entry_point); /* Pass the saved boot_params from rom code */ - image_entry((u32 *)&gd->arch.omap_boot_params); + image_entry((u32 *)boot_params); } #endif @@ -163,7 +223,7 @@ void arch_preboot_os(void) } #endif -#if defined(CONFIG_CMD_FASTBOOT) && !defined(CONFIG_ENV_IS_NOWHERE) +#if defined(CONFIG_USB_FUNCTION_FASTBOOT) && !defined(CONFIG_ENV_IS_NOWHERE) int fb_set_reboot_flag(void) { printf("Setting reboot to fastboot flag ...\n"); diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 6c8f3bc..80794f9 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -90,7 +90,9 @@ void __weak srcomp_enable(void) */ int arch_cpu_init(void) { +#ifdef CONFIG_SPL save_omap_boot_params(); +#endif return 0; } #endif /* CONFIG_ARCH_CPU_INIT */ diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 746df92..5283135 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -16,8 +16,9 @@ #include <asm/arch/spl.h> #include <linux/linkage.h> -#ifndef CONFIG_OMAP34XX +#ifdef CONFIG_SPL ENTRY(save_boot_params) + ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS str r0, [r1] b save_boot_params_ret diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index cf86046..b2fce96 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -8,6 +8,7 @@ obj-y := lowlevel_init.o obj-y += board.o +obj-y += boot.o obj-y += clock.o obj-y += sys_info.o ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index b064c0c..17cb5b7 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -18,7 +18,6 @@ */ #include <common.h> #include <dm.h> -#include <mmc.h> #include <spl.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> @@ -27,8 +26,6 @@ #include <asm/armv7.h> #include <asm/gpio.h> #include <asm/omap_common.h> -#include <asm/arch/mmc_host_def.h> -#include <i2c.h> #include <linux/compiler.h> DECLARE_GLOBAL_DATA_PTR; @@ -73,62 +70,6 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx; #endif -#ifdef CONFIG_SPL_BUILD -/* -* We use static variables because global data is not ready yet. -* Initialized data is available in SPL right from the beginning. -* We would not typically need to save these parameters in regular -* U-Boot. This is needed only in SPL at the moment. -*/ -u32 omap3_boot_device = BOOT_DEVICE_NAND; - -/* auto boot mode detection is not possible for OMAP3 - hard code */ -u32 spl_boot_mode(void) -{ - switch (spl_boot_device()) { - case BOOT_DEVICE_MMC2: - return MMCSD_MODE_RAW; - case BOOT_DEVICE_MMC1: - return MMCSD_MODE_FS; - break; - default: - puts("spl: ERROR: unknown device - can't select boot mode\n"); - hang(); - } -} - -u32 spl_boot_device(void) -{ - return omap3_boot_device; -} - -int board_mmc_init(bd_t *bis) -{ - switch (spl_boot_device()) { - case BOOT_DEVICE_MMC1: - omap_mmc_init(0, 0, 0, -1, -1); - break; - case BOOT_DEVICE_MMC2: - case BOOT_DEVICE_MMC2_2: - omap_mmc_init(1, 0, 0, -1, -1); - break; - } - return 0; -} - -void spl_board_init(void) -{ - preloader_console_init(); -#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT) - gpmc_init(); -#endif -#ifdef CONFIG_SPL_I2C_SUPPORT - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); -#endif -} -#endif /* CONFIG_SPL_BUILD */ - - /****************************************************************************** * Routine: secure_unlock * Description: Setup security registers for access diff --git a/arch/arm/cpu/armv7/omap3/boot.c b/arch/arm/cpu/armv7/omap3/boot.c new file mode 100644 index 0000000..66576b2 --- /dev/null +++ b/arch/arm/cpu/armv7/omap3/boot.c @@ -0,0 +1,58 @@ +/* + * OMAP3 boot + * + * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <spl.h> + +static u32 boot_devices[] = { + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_NAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC2_2, +}; + +u32 omap_sys_boot_device(void) +{ + struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + u32 sys_boot; + + /* Grab the first 5 bits of the status register for SYS_BOOT. */ + sys_boot = readl(&ctrl_base->status) & ((1 << 5) - 1); + + if (sys_boot >= (sizeof(boot_devices) / sizeof(u32))) + return BOOT_DEVICE_NONE; + + return boot_devices[sys_boot]; +} diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S b/arch/arm/cpu/armv7/omap3/lowlevel_init.S index 2497613..1e58772 100644 --- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S @@ -16,16 +16,6 @@ #include <asm/arch/clocks_omap3.h> #include <linux/linkage.h> -#ifdef CONFIG_SPL_BUILD -ENTRY(save_boot_params) - ldr r4, =omap3_boot_device - ldr r5, [r0, #0x4] - and r5, r5, #0xff - str r5, [r4] - b save_boot_params_ret -ENDPROC(save_boot_params) -#endif - /* * Funtion for making PPA HAL API calls in secure devices * Input: diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c b/arch/arm/cpu/armv7/omap3/sys_info.c index bbb65bb..ab60a03 100644 --- a/arch/arm/cpu/armv7/omap3/sys_info.c +++ b/arch/arm/cpu/armv7/omap3/sys_info.c @@ -196,10 +196,12 @@ u32 get_gpmc0_width(void) * get_board_rev() - setup to pass kernel board revision information * returns:(bit[0-3] sub version, higher bit[7-4] is higher version) *************************************************************************/ +#ifdef CONFIG_REVISION_TAG u32 __weak get_board_rev(void) { return 0x20; } +#endif /******************************************************** * get_base(); get upper addr of current execution diff --git a/arch/arm/cpu/armv7/omap4/Makefile b/arch/arm/cpu/armv7/omap4/Makefile index 76a032a..564f1f6 100644 --- a/arch/arm/cpu/armv7/omap4/Makefile +++ b/arch/arm/cpu/armv7/omap4/Makefile @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-y += boot.o obj-y += sdram_elpida.o obj-y += hwinit.o obj-y += emif.o diff --git a/arch/arm/cpu/armv7/omap4/boot.c b/arch/arm/cpu/armv7/omap4/boot.c new file mode 100644 index 0000000..4b5aa77 --- /dev/null +++ b/arch/arm/cpu/armv7/omap4/boot.c @@ -0,0 +1,60 @@ +/* + * OMAP4 boot + * + * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/omap_common.h> +#include <spl.h> + +static u32 boot_devices[] = { + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIPWAIT, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_ONENAND, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIP, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_MMC2_2, + BOOT_DEVICE_NONE, + BOOT_DEVICE_XIPWAIT, +}; + +u32 omap_sys_boot_device(void) +{ + u32 sys_boot; + + /* Grab the first 5 bits of the status register for SYS_BOOT. */ + sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 5) - 1); + + if (sys_boot >= (sizeof(boot_devices) / sizeof(u32))) + return BOOT_DEVICE_NONE; + + return boot_devices[sys_boot]; +} diff --git a/arch/arm/cpu/armv7/omap4/prcm-regs.c b/arch/arm/cpu/armv7/omap4/prcm-regs.c index 1ed146b..8698ec7 100644 --- a/arch/arm/cpu/armv7/omap4/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap4/prcm-regs.c @@ -279,6 +279,7 @@ struct prcm_regs const omap4_prcm = { }; struct omap_sys_ctrl_regs const omap4_ctrl = { + .control_status = 0x4A0022C4, .control_id_code = 0x4A002204, .control_std_fuse_opp_bgap = 0x4a002260, .control_status = 0x4a0022c4, diff --git a/arch/arm/cpu/armv7/omap5/Makefile b/arch/arm/cpu/armv7/omap5/Makefile index e709f14..f2930d5 100644 --- a/arch/arm/cpu/armv7/omap5/Makefile +++ b/arch/arm/cpu/armv7/omap5/Makefile @@ -5,6 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # +obj-y += boot.o obj-y += hwinit.o obj-y += emif.o obj-y += sdram.o diff --git a/arch/arm/cpu/armv7/omap5/boot.c b/arch/arm/cpu/armv7/omap5/boot.c new file mode 100644 index 0000000..583becc --- /dev/null +++ b/arch/arm/cpu/armv7/omap5/boot.c @@ -0,0 +1,46 @@ +/* + * OMAP5 boot + * + * Copyright (C) 2015 Paul Kocialkowski <contact@paulk.fr> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/omap_common.h> +#include <spl.h> + +static u32 boot_devices[] = { +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) + BOOT_DEVICE_MMC2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_SATA, + BOOT_DEVICE_XIP, + BOOT_DEVICE_XIP, + BOOT_DEVICE_SPI, + BOOT_DEVICE_SPI, +#else + BOOT_DEVICE_MMC2, + BOOT_DEVICE_NAND, + BOOT_DEVICE_MMC1, + BOOT_DEVICE_SATA, + BOOT_DEVICE_XIP, + BOOT_DEVICE_MMC2, + BOOT_DEVICE_XIPWAIT, +#endif +}; + +u32 omap_sys_boot_device(void) +{ + u32 sys_boot; + + /* Grab the first 4 bits of the status register for SYS_BOOT. */ + sys_boot = readl((u32 *) (*ctrl)->control_status) & ((1 << 4) - 1); + + if (sys_boot >= (sizeof(boot_devices) / sizeof(u32))) + return BOOT_DEVICE_NONE; + + return boot_devices[sys_boot]; +} diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 5f39aa0..f01846e 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -11,6 +11,7 @@ */ #include <common.h> +#include <mmc.h> #include <i2c.h> #include <serial.h> #ifdef CONFIG_SPL_BUILD @@ -22,6 +23,7 @@ #include <asm/arch/gpio.h> #include <asm/arch/sys_proto.h> #include <asm/arch/timer.h> +#include <asm/arch/mmc.h> #include <linux/compiler.h> @@ -121,17 +123,18 @@ void s_init(void) } #ifdef CONFIG_SPL_BUILD +DECLARE_GLOBAL_DATA_PTR; + /* The sunxi internal brom will try to loader external bootloader * from mmc0, nand flash, mmc2. - * Unfortunately we can't check how SPL was loaded so assume - * it's always the first SD/MMC controller */ u32 spl_boot_device(void) { + struct mmc *mmc0, *mmc1; /* - * When booting from the SD card, the "eGON.BT0" signature is expected - * to be found in memory at the address 0x0004 (see the "mksunxiboot" - * tool, which generates this header). + * When booting from the SD card or NAND memory, the "eGON.BT0" + * signature is expected to be found in memory at the address 0x0004 + * (see the "mksunxiboot" tool, which generates this header). * * When booting in the FEL mode over USB, this signature is patched in * memory and replaced with something else by the 'fel' tool. This other @@ -139,15 +142,40 @@ u32 spl_boot_device(void) * valid bootable SD card image (because the BROM would refuse to * execute the SPL in this case). * - * This branch is just making a decision at runtime whether to load - * the main u-boot binary from the SD card (if the "eGON.BT0" signature - * is found) or return to the FEL code in the BROM to wait and receive - * the main u-boot binary over USB. + * This checks for the signature and if it is not found returns to + * the FEL code in the BROM to wait and receive the main u-boot + * binary over USB. If it is found, it determines where SPL was + * read from. */ - if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */ - return BOOT_DEVICE_MMC1; - else + if (readl(4) != 0x4E4F4765 || readl(8) != 0x3054422E) /* eGON.BT0 */ return BOOT_DEVICE_BOARD; + + /* The BROM will try to boot from mmc0 first, so try that first. */ + mmc_initialize(gd->bd); + mmc0 = find_mmc_device(0); + if (sunxi_mmc_has_egon_boot_signature(mmc0)) + return BOOT_DEVICE_MMC1; + + /* Fallback to booting NAND if enabled. */ + if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT)) + return BOOT_DEVICE_NAND; + + if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) { + mmc1 = find_mmc_device(1); + if (sunxi_mmc_has_egon_boot_signature(mmc1)) { + /* + * spl_mmc.c: spl_mmc_load_image() is hard-coded to + * use find_mmc_device(0), no matter what we + * return. Swap mmc0 and mmc2 to make this work. + */ + mmc0->block_dev.dev = 1; + mmc1->block_dev.dev = 0; + return BOOT_DEVICE_MMC2; + } + } + + panic("Could not determine boot source\n"); + return -1; /* Never reached */ } /* No confirmation data available in SPL yet. Hardcode bootmode */ diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c index 165c052..c53671a 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a23.c @@ -26,7 +26,6 @@ #include <asm/arch/clock.h> #include <asm/arch/dram.h> #include <asm/arch/prcm.h> -#include <linux/kconfig.h> static const struct dram_para dram_para = { .clock = CONFIG_DRAM_CLK, diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c index ebba438..fa1620c 100644 --- a/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c +++ b/arch/arm/cpu/armv7/sunxi/dram_sun8i_a33.c @@ -14,7 +14,6 @@ #include <asm/arch/clock.h> #include <asm/arch/dram.h> #include <asm/arch/prcm.h> -#include <linux/kconfig.h> /* PLL runs at 2x dram-clk, controller runs at PLL / 4 (dram-clk / 2) */ #define DRAM_CLK_MUL 2 diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S index d4cb51e..4ff46e4 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S @@ -18,6 +18,8 @@ */ #include <config.h> + +#include <asm/arch-armv7/generictimer.h> #include <asm/gic.h> #include <asm/macro.h> #include <asm/psci.h> @@ -43,26 +45,6 @@ #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000 -.macro timer_wait reg, ticks - @ Program CNTP_TVAL - movw \reg, #(\ticks & 0xffff) - movt \reg, #(\ticks >> 16) - mcr p15, 0, \reg, c14, c2, 0 - isb - @ Enable physical timer, mask interrupt - mov \reg, #3 - mcr p15, 0, \reg, c14, c2, 1 - @ Poll physical timer until ISTATUS is on -1: isb - mrc p15, 0, \reg, c14, c2, 1 - ands \reg, \reg, #4 - bne 1b - @ Disable timer - mov \reg, #0 - mcr p15, 0, \reg, c14, c2, 1 - isb -.endm - .globl psci_fiq_enter psci_fiq_enter: push {r0-r12} diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S index bbfeec8..e15d587 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S @@ -18,6 +18,8 @@ */ #include <config.h> + +#include <asm/arch-armv7/generictimer.h> #include <asm/gic.h> #include <asm/macro.h> #include <asm/psci.h> @@ -43,26 +45,6 @@ #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000 -.macro timer_wait reg, ticks - @ Program CNTP_TVAL - movw \reg, #(\ticks & 0xffff) - movt \reg, #(\ticks >> 16) - mcr p15, 0, \reg, c14, c2, 0 - isb - @ Enable physical timer, mask interrupt - mov \reg, #3 - mcr p15, 0, \reg, c14, c2, 1 - @ Poll physical timer until ISTATUS is on -1: isb - mrc p15, 0, \reg, c14, c2, 1 - ands \reg, \reg, #4 - bne 1b - @ Disable timer - mov \reg, #0 - mcr p15, 0, \reg, c14, c2, 1 - isb -.endm - .globl psci_fiq_enter psci_fiq_enter: push {r0-r12} diff --git a/arch/arm/cpu/armv7/sunxi/usb_phy.c b/arch/arm/cpu/armv7/sunxi/usb_phy.c index b07d67f..4d63a74 100644 --- a/arch/arm/cpu/armv7/sunxi/usb_phy.c +++ b/arch/arm/cpu/armv7/sunxi/usb_phy.c @@ -44,6 +44,7 @@ static struct sunxi_usb_phy { int usb_rst_mask; int gpio_vbus; int gpio_vbus_det; + int gpio_id_det; int id; int init_count; int power_on_count; @@ -82,6 +83,14 @@ static int get_vbus_detect_gpio(int index) return -EINVAL; } +static int get_id_detect_gpio(int index) +{ + switch (index) { + case 0: return sunxi_name_to_gpio(CONFIG_USB0_ID_DET); + } + return -EINVAL; +} + static void usb_phy_write(struct sunxi_usb_phy *phy, int addr, int data, int len) { @@ -228,10 +237,8 @@ int sunxi_usb_phy_vbus_detect(int index) struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; int err, retries = 3; - if (phy->gpio_vbus_det < 0) { - eprintf("Error: invalid vbus detection pin\n"); + if (phy->gpio_vbus_det < 0) return phy->gpio_vbus_det; - } err = gpio_get_value(phy->gpio_vbus_det); /* @@ -247,6 +254,16 @@ int sunxi_usb_phy_vbus_detect(int index) return err; } +int sunxi_usb_phy_id_detect(int index) +{ + struct sunxi_usb_phy *phy = &sunxi_usb_phy[index]; + + if (phy->gpio_id_det < 0) + return phy->gpio_id_det; + + return gpio_get_value(phy->gpio_id_det); +} + int sunxi_usb_phy_probe(void) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; @@ -275,6 +292,18 @@ int sunxi_usb_phy_probe(void) if (ret) return ret; } + + phy->gpio_id_det = get_id_detect_gpio(i); + if (phy->gpio_id_det >= 0) { + ret = gpio_request(phy->gpio_id_det, "usb_id_det"); + if (ret) + return ret; + ret = gpio_direction_input(phy->gpio_id_det); + if (ret) + return ret; + sunxi_gpio_set_pull(phy->gpio_id_det, + SUNXI_GPIO_PULL_UP); + } } setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE); @@ -298,6 +327,9 @@ int sunxi_usb_phy_remove(void) if (phy->gpio_vbus_det >= 0) gpio_free(phy->gpio_vbus_det); + + if (phy->gpio_id_det >= 0) + gpio_free(phy->gpio_id_det); } return 0; diff --git a/arch/arm/cpu/armv7m/stm32f4/clock.c b/arch/arm/cpu/armv7m/stm32f4/clock.c index 2eded1f..d520a13 100644 --- a/arch/arm/cpu/armv7m/stm32f4/clock.c +++ b/arch/arm/cpu/armv7m/stm32f4/clock.c @@ -92,7 +92,20 @@ struct pll_psc { #error "CONFIG_STM32_HSE_HZ not defined!" #else #if (CONFIG_STM32_HSE_HZ == 8000000) -struct pll_psc pll_psc_168 = { +#if (CONFIG_SYS_CLK_FREQ == 180000000) +/* 180 MHz */ +struct pll_psc sys_pll_psc = { + .pll_m = 8, + .pll_n = 360, + .pll_p = 2, + .pll_q = 8, + .ahb_psc = AHB_PSC_1, + .apb1_psc = APB_PSC_4, + .apb2_psc = APB_PSC_2 +}; +#else +/* default 168 MHz */ +struct pll_psc sys_pll_psc = { .pll_m = 8, .pll_n = 336, .pll_p = 2, @@ -101,6 +114,7 @@ struct pll_psc pll_psc_168 = { .apb1_psc = APB_PSC_4, .apb2_psc = APB_PSC_2 }; +#endif #else #error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists" #endif @@ -122,19 +136,19 @@ int configure_clocks(void) while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY)) ; - /* Enable high performance mode, System frequency up to 168 MHz */ + /* Enable high performance mode, System frequency up to 180 MHz */ setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN); writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr); setbits_le32(&STM32_RCC->cfgr, (( - pll_psc_168.ahb_psc << RCC_CFGR_HPRE_SHIFT) - | (pll_psc_168.apb1_psc << RCC_CFGR_PPRE1_SHIFT) - | (pll_psc_168.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); - - writel(pll_psc_168.pll_m - | (pll_psc_168.pll_n << RCC_PLLCFGR_PLLN_SHIFT) - | (((pll_psc_168.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) - | (pll_psc_168.pll_q << RCC_PLLCFGR_PLLQ_SHIFT), + sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT) + | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT) + | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); + + writel(sys_pll_psc.pll_m + | (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT) + | (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) + | (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT), &STM32_RCC->pllcfgr); setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC); diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index dee5e25..6466ebb 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -16,4 +16,4 @@ obj-y += tlb.o obj-y += transition.o obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/ -obj-$(CONFIG_TARGET_XILINX_ZYNQMP) += zynqmp/ +obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/ diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index c5ec529..c22f7b6 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -25,9 +25,9 @@ void set_pgtable_section(u64 *page_table, u64 index, u64 section, /* to activate the MMU we need to set up virtual memory */ static void mmu_setup(void) { - int i, j, el; bd_t *bd = gd->bd; - u64 *page_table = (u64 *)gd->arch.tlb_addr; + u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j; + int el; /* Setup an identity-mapping for all spaces */ for (i = 0; i < (PGTABLE_SIZE >> 3); i++) { @@ -139,6 +139,37 @@ int dcache_status(void) return (get_sctlr() & CR_C) != 0; } +u64 *__weak arch_get_page_table(void) { + puts("No page table offset defined\n"); + + return NULL; +} + +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ + u64 *page_table = arch_get_page_table(); + u64 upto, end; + + if (page_table == NULL) + return; + + end = ALIGN(start + size, (1 << MMU_SECTION_SHIFT)) >> + MMU_SECTION_SHIFT; + start = start >> MMU_SECTION_SHIFT; + for (upto = start; upto < end; upto++) { + page_table[upto] &= ~PMD_ATTRINDX_MASK; + page_table[upto] |= PMD_ATTRINDX(option); + } + asm volatile("dsb sy"); + __asm_invalidate_tlb_all(); + asm volatile("dsb sy"); + asm volatile("isb"); + start = start << MMU_SECTION_SHIFT; + end = end << MMU_SECTION_SHIFT; + flush_dcache_range(start, end); + asm volatile("dsb sy"); +} #else /* CONFIG_SYS_DCACHE_OFF */ void invalidate_dcache_all(void) @@ -170,6 +201,11 @@ int dcache_status(void) return 0; } +void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, + enum dcache_option option) +{ +} + #endif /* CONFIG_SYS_DCACHE_OFF */ #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README index 37f07fb..3c15479 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/README +++ b/arch/arm/cpu/armv8/fsl-lsch3/README @@ -9,6 +9,31 @@ Freescale LayerScape with Chassis Generation 3 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3, for example LS2085A. +DDR Layout +============ +Entire DDR region splits into two regions. + - Region 1 is at address 0x8000_0000 to 0xffff_ffff. + - Region 2 is at 0x80_8000_0000 to the top of total memory, + for example 16GB, 0x83_ffff_ffff. + +All DDR memory is marked as cache-enabled. + +When MC and Debug server is enabled, they carve 512MB away from the high +end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB +with MC and Debug server enabled. Linux only sees 15.5GB. + +The reserved 512MB layout looks like + + +---------------+ <-- top/end of memory + | 256MB | debug server + +---------------+ + | 256MB | MC + +---------------+ + | ... | + +MC requires the memory to be aligned with 512MB, so even debug server is +not enabled, 512MB is reserved, not 256MB. + Flash Layout ============ diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 6714577..d02c0be 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -9,6 +9,7 @@ #include <asm/system.h> #include <asm/armv8/mmu.h> #include <asm/io.h> +#include <asm/arch-fsl-lsch3/soc.h> #include <asm/arch-fsl-lsch3/immap_lsch3.h> #include <fsl_debug_server.h> #include <fsl-mc/fsl_mc.h> @@ -22,6 +23,35 @@ DECLARE_GLOBAL_DATA_PTR; +static struct cpu_type cpu_type_list[] = { +#ifdef CONFIG_LS2085A + CPU_TYPE_ENTRY(LS2085, LS2085, 8), + CPU_TYPE_ENTRY(LS2080, LS2080, 8), + CPU_TYPE_ENTRY(LS2045, LS2045, 4), +#endif +}; + +void cpu_name(char *name) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int i, svr, ver; + + svr = in_le32(&gur->svr); + ver = SVR_SOC_VER(svr); + + for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) + if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) { + strcpy(name, cpu_type_list[i].name); + + if (IS_E_PROCESSOR(svr)) + strcat(name, "E"); + break; + } + + if (i == ARRAY_SIZE(cpu_type_list)) + strcpy(name, "unknown"); +} + #ifndef CONFIG_SYS_DCACHE_OFF /* * To start MMU before DDR is available, we create MMU table in SRAM. @@ -52,6 +82,12 @@ DECLARE_GLOBAL_DATA_PTR; TCR_ORGN_NC | \ TCR_IRGN_NC | \ TCR_T0SZ(LSCH3_VA_BITS)) +#define LSCH3_TCR_FINAL (TCR_TG0_4K | \ + TCR_EL2_PS_40BIT | \ + TCR_SHARED_OUTER | \ + TCR_ORGN_WBWA | \ + TCR_IRGN_WBWA | \ + TCR_T0SZ(LSCH3_VA_BITS)) /* * Final MMU @@ -236,21 +272,8 @@ static inline void final_mmu_setup(void) /* point TTBR to the new table */ el = current_el(); - asm volatile("dsb sy"); - if (el == 1) { - asm volatile("msr ttbr0_el1, %0" - : : "r" ((u64)level0_table) : "memory"); - } else if (el == 2) { - asm volatile("msr ttbr0_el2, %0" - : : "r" ((u64)level0_table) : "memory"); - } else if (el == 3) { - asm volatile("msr ttbr0_el3, %0" - : : "r" ((u64)level0_table) : "memory"); - } else { - hang(); - } - asm volatile("isb"); - + set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR_FINAL, + MEMORY_ATTRIBUTES); /* * MMU is already enabled, just need to invalidate TLB to load the * new table. The new table is compatible with the current table, if @@ -380,6 +403,13 @@ int print_cpuinfo(void) unsigned int i, core; u32 type; + puts("SoC: "); + + cpu_name(buf); + printf(" %s (0x%x)\n", buf, in_le32(&gur->svr)); + + memset((u8 *)buf, 0x00, ARRAY_SIZE(buf)); + get_sys_info(&sysinfo); puts("Clock Configuration:"); for_each_cpu(i, core, cpu_numcores(), cpu_mask()) { @@ -394,8 +424,8 @@ int print_cpuinfo(void) } printf("\n Bus: %-4s MHz ", strmhz(buf, sysinfo.freq_systembus)); - printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus)); - printf(" DP-DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2)); + printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus)); + printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2)); puts("\n"); /* Display the RCW, so that no one gets confused as to what RCW diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c index d370023..567c419 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c @@ -7,6 +7,7 @@ #include <common.h> #include <libfdt.h> #include <fdt_support.h> +#include <asm/arch-fsl-lsch3/fdt.h> #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif @@ -58,6 +59,113 @@ void ft_fixup_cpu(void *blob) } #endif +/* + * the burden is on the the caller to not request a count + * exceeding the bounds of the stream_ids[] array + */ +void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt) +{ + int i; + + if (count > max_cnt) { + printf("\n%s: ERROR: max per-device stream ID count exceed\n", + __func__); + return; + } + + for (i = 0; i < count; i++) + stream_ids[i] = start_id++; +} + +/* + * This function updates the mmu-masters property on the SMMU + * node as per the SMMU binding-- phandle and list of stream IDs + * for each MMU master. + */ +void append_mmu_masters(void *blob, const char *smmu_path, + const char *master_name, u32 *stream_ids, int count) +{ + u32 phandle; + int smmu_nodeoffset; + int master_nodeoffset; + int i; + + /* get phandle of mmu master device */ + master_nodeoffset = fdt_path_offset(blob, master_name); + if (master_nodeoffset < 0) { + printf("\n%s: ERROR: master not found\n", __func__); + return; + } + phandle = fdt_get_phandle(blob, master_nodeoffset); + if (!phandle) { /* if master has no phandle, create one */ + phandle = fdt_create_phandle(blob, master_nodeoffset); + if (!phandle) { + printf("\n%s: ERROR: unable to create phandle\n", + __func__); + return; + } + } + + /* append it to mmu-masters */ + smmu_nodeoffset = fdt_path_offset(blob, smmu_path); + if (fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters", + phandle) < 0) { + printf("\n%s: ERROR: unable to update SMMU node\n", __func__); + return; + } + + /* for each stream ID, append to mmu-masters */ + for (i = 0; i < count; i++) { + fdt_appendprop_u32(blob, smmu_nodeoffset, "mmu-masters", + stream_ids[i]); + } + + /* fix up #stream-id-cells with stream ID count */ + if (fdt_setprop_u32(blob, master_nodeoffset, "#stream-id-cells", + count) < 0) + printf("\n%s: ERROR: unable to update #stream-id-cells\n", + __func__); +} + + +/* + * The info below summarizes how streamID partitioning works + * for ls2085a and how it is conveyed to the OS via the device tree. + * + * -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA) + * -all legacy devices get a unique ICID assigned and programmed in + * their AMQR registers by u-boot + * -u-boot updates the hardware device tree with streamID properties + * for each platform/legacy device (smmu-masters property) + * + * -PCIe + * -for each PCI controller that is active (as per RCW settings), + * u-boot will allocate a range of ICID and convey that to Linux via + * the device tree (smmu-masters property) + * + * -DPAA2 + * -u-boot will allocate a range of ICIDs to be used by the Management + * Complex for containers and will set these values in the MC DPC image. + * -the MC is responsible for allocating and setting up ICIDs + * for all DPAA2 devices. + * + */ +static void fdt_fixup_smmu(void *blob) +{ + int nodeoffset; + + nodeoffset = fdt_path_offset(blob, "/iommu@5000000"); + if (nodeoffset < 0) { + printf("\n%s: WARNING: no SMMU node found\n", __func__); + return; + } + + /* fixup for all PCI controllers */ +#ifdef CONFIG_PCI + fdt_fixup_smmu_pcie(blob); +#endif +} + void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_MP @@ -69,7 +177,13 @@ void ft_cpu_setup(void *blob, bd_t *bd) "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + #if defined(CONFIG_FSL_ESDHC) fdt_fixup_esdhc(blob, bd); #endif + + fdt_fixup_smmu(blob); } diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c index cac4f92..d9f137c 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c @@ -180,6 +180,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) switch (clk) { case MXC_I2C_CLK: return get_bus_freq(0) / 2; + case MXC_DSPI_CLK: + return get_bus_freq(0) / 2; default: printf("Unsupported clock\n"); } diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index e5f2766..e70bed4 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -115,18 +115,18 @@ apply_a57_core_errata: #ifdef CONFIG_ARM_ERRATA_828024 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ /* Disable non-allocate hint of w-b-n-a memory type */ - mov x0, #0x1 << 49 + orr x0, x0, #1 << 49 /* Disable write streaming no L1-allocate threshold */ - mov x0, #0x3 << 25 + orr x0, x0, #3 << 25 /* Disable write streaming no-allocate threshold */ - mov x0, #0x3 << 27 + orr x0, x0, #3 << 27 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ #endif #ifdef CONFIG_ARM_ERRATA_826974 mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */ /* Disable speculative load execution ahead of a DMB */ - mov x0, #0x1 << 59 + orr x0, x0, #1 << 59 msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */ #endif diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig new file mode 100644 index 0000000..c8fcfb6 --- /dev/null +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -0,0 +1,23 @@ +if ARCH_ZYNQMP + +choice + prompt "Xilinx ZynqMP board select" + +config TARGET_ZYNQMP_EP + bool "ZynqMP EP Board" + +endchoice + +config SYS_BOARD + default "zynqmp" + +config SYS_VENDOR + default "xilinx" + +config SYS_SOC + default "zynqmp" + +config SYS_CONFIG_NAME + default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP + +endif diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile index efab5ea..d0ed222 100644 --- a/arch/arm/cpu/armv8/zynqmp/Makefile +++ b/arch/arm/cpu/armv8/zynqmp/Makefile @@ -8,3 +8,4 @@ obj-y += clk.o obj-y += cpu.o obj-$(CONFIG_MP) += mp.o +obj-y += slcr.o diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c index 17e32a7..dcb80b5 100644 --- a/arch/arm/cpu/armv8/zynqmp/mp.c +++ b/arch/arm/cpu/armv8/zynqmp/mp.c @@ -216,12 +216,7 @@ int cpu_release(int nr, int argc, char * const argv[]) printf("R5 lockstep mode\n"); set_r5_tcm_mode(LOCK); set_r5_halt_mode(HALT, LOCK); - - if (boot_addr == 0) - set_r5_start(0); - else - set_r5_start(1); - + set_r5_start(boot_addr); enable_clock_r5(); release_r5_reset(LOCK); set_r5_halt_mode(RELEASE, LOCK); diff --git a/arch/arm/cpu/armv8/zynqmp/slcr.c b/arch/arm/cpu/armv8/zynqmp/slcr.c new file mode 100644 index 0000000..713e9a6 --- /dev/null +++ b/arch/arm/cpu/armv8/zynqmp/slcr.c @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2014 - 2015 Xilinx, Inc. + * Michal Simek <michal.simek@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <malloc.h> +#include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clk.h> + +/* + * zynq_slcr_mio_get_status - Get the status of MIO peripheral. + * + * @peri_name: Name of the peripheral for checking MIO status + * @get_pins: Pointer to array of get pin for this peripheral + * @num_pins: Number of pins for this peripheral + * @mask: Mask value + * @check_val: Required check value to get the status of periph + */ +struct zynq_slcr_mio_get_status { + const char *peri_name; + const int *get_pins; + int num_pins; + u32 mask; + u32 check_val; +}; + +static const struct zynq_slcr_mio_get_status mio_periphs[] = { +}; + +/* + * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral. + * + * @periph: Name of the peripheral + * + * Returns count to indicate the number of pins configured for the + * given @periph. + */ +int zynq_slcr_get_mio_pin_status(const char *periph) +{ + const struct zynq_slcr_mio_get_status *mio_ptr; + int val, i, j; + int mio = 0; + + for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) { + if (strcmp(periph, mio_periphs[i].peri_name) == 0) { + mio_ptr = &mio_periphs[i]; + for (j = 0; j < mio_ptr->num_pins; j++) { + val = readl(&slcr_base->mio_pin + [mio_ptr->get_pins[j]]); + if ((val & mio_ptr->mask) == mio_ptr->check_val) + mio++; + } + break; + } + } + + return mio; +} diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index a8be204..c5b4f7c 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -32,17 +32,17 @@ SECTIONS } . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*_i2c_*))); - } - - . = .; #ifdef CONFIG_SPL_DM .u_boot_list : { KEEP(*(SORT(.u_boot_list_*_driver_*))); KEEP(*(SORT(.u_boot_list_*_uclass_*))); } #endif + . = .; + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*_i2c_*))); + } + . = ALIGN(4); __image_copy_end = .; @@ -66,7 +66,7 @@ SECTIONS . = ALIGN(4); __bss_end = .; } - + __bss_size = __bss_end - __bss_start; .dynsym _image_binary_end : { *(.dynsym) } .dynbss : { *(.dynbss) } .dynstr : { *(.dynstr*) } |