3 files changed, 57 insertions, 0 deletions

diff --git a/arch/arm/include/asm/imx-common/boot_mode.h b/arch/arm/include/asm/imx-common/boot_mode.h
index de0205c..a8239f2 100644
--- a/arch/arm/include/asm/imx-common/boot_mode.h
+++ b/arch/arm/include/asm/imx-common/boot_mode.h
@@ -9,6 +9,27 @@
 #define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \
 	((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1)
 
+enum boot_device {
+	WEIM_NOR_BOOT,
+	ONE_NAND_BOOT,
+	PATA_BOOT,
+	SATA_BOOT,
+	I2C_BOOT,
+	SPI_NOR_BOOT,
+	SD1_BOOT,
+	SD2_BOOT,
+	SD3_BOOT,
+	SD4_BOOT,
+	MMC1_BOOT,
+	MMC2_BOOT,
+	MMC3_BOOT,
+	MMC4_BOOT,
+	NAND_BOOT,
+	QSPI_BOOT,
+	UNKNOWN_BOOT,
+	BOOT_DEV_NUM = UNKNOWN_BOOT,
+};
+
 struct boot_mode {
 	const char *name;
 	unsigned cfg_val;
diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h
index 6954ee9..5673fb4 100644
--- a/arch/arm/include/asm/imx-common/sys_proto.h
+++ b/arch/arm/include/asm/imx-common/sys_proto.h
@@ -17,9 +17,12 @@
 
 /* returns MXC_CPU_ value */
 #define cpu_type(rev) (((rev) >> 12) & 0xff)
+#define soc_type(rev) (((rev) >> 12) & 0xf0)
 /* both macros return/take MXC_CPU_ constants */
 #define get_cpu_type() (cpu_type(get_cpu_rev()))
+#define get_soc_type() (soc_type(get_cpu_rev()))
 #define is_cpu_type(cpu) (get_cpu_type() == cpu)
+#define is_soc_type(soc) (get_soc_type() == soc)
 
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
 
@@ -32,6 +35,10 @@ u32 imx_ddr_size(void);
 void sdelay(unsigned long);
 void set_chipselect_size(int const);
 
+void init_aips(void);
+void init_src(void);
+void imx_set_wdog_powerdown(bool enable);
+
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
diff --git a/arch/arm/include/asm/imx-common/syscounter.h b/arch/arm/include/asm/imx-common/syscounter.h
new file mode 100644
index 0000000..bdbe26c
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/syscounter.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SYSTEM_COUNTER_H
+#define _ASM_ARCH_SYSTEM_COUNTER_H
+
+/* System Counter */
+struct sctr_regs {
+	u32 cntcr;
+	u32 cntsr;
+	u32 cntcv1;
+	u32 cntcv2;
+	u32 resv1[4];
+	u32 cntfid0;
+	u32 cntfid1;
+	u32 cntfid2;
+	u32 resv2[1001];
+	u32 counterid[1];
+};
+
+#define SC_CNTCR_ENABLE		(1 << 0)
+#define SC_CNTCR_HDBG		(1 << 1)
+#define SC_CNTCR_FREQ0		(1 << 8)
+#define SC_CNTCR_FREQ1		(1 << 9)
+
+#endif