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-rw-r--r--arch/arm/include/asm/arch-vf610/clock.h39
-rw-r--r--arch/arm/include/asm/arch-vf610/crm_regs.h225
-rw-r--r--arch/arm/include/asm/arch-vf610/imx-regs.h419
-rw-r--r--arch/arm/include/asm/arch-vf610/iomux-vf610.h101
4 files changed, 784 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h
new file mode 100644
index 0000000..04e418c
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/clock.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H
+
+#include <common.h>
+
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_BUS_CLK,
+ MXC_IPG_CLK,
+ MXC_UART_CLK,
+ MXC_ESDHC_CLK,
+ MXC_FEC_CLK,
+};
+
+void enable_ocotp_clk(unsigned char enable);
+unsigned int mxc_get_clock(enum mxc_clock clk);
+
+#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
new file mode 100644
index 0000000..e3f703d
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
+#define __ARCH_ARM_MACH_VF610_CCM_REGS_H__
+
+#ifndef __ASSEMBLY__
+
+/* Clock Controller Module (CCM) */
+struct ccm_reg {
+ u32 ccr;
+ u32 csr;
+ u32 ccsr;
+ u32 cacrr;
+ u32 cscmr1;
+ u32 cscdr1;
+ u32 cscdr2;
+ u32 cscdr3;
+ u32 cscmr2;
+ u32 cscdr4;
+ u32 ctor;
+ u32 clpcr;
+ u32 cisr;
+ u32 cimr;
+ u32 ccosr;
+ u32 cgpr;
+ u32 ccgr0;
+ u32 ccgr1;
+ u32 ccgr2;
+ u32 ccgr3;
+ u32 ccgr4;
+ u32 ccgr5;
+ u32 ccgr6;
+ u32 ccgr7;
+ u32 ccgr8;
+ u32 ccgr9;
+ u32 ccgr10;
+ u32 ccgr11;
+ u32 cmeor0;
+ u32 cmeor1;
+ u32 cmeor2;
+ u32 cmeor3;
+ u32 cmeor4;
+ u32 cmeor5;
+ u32 cppdsr;
+ u32 ccowr;
+ u32 ccpgr0;
+ u32 ccpgr1;
+ u32 ccpgr2;
+ u32 ccpgr3;
+};
+
+/* Analog components control digital interface (ANADIG) */
+struct anadig_reg {
+ u32 pll3_ctrl;
+ u32 resv0[3];
+ u32 pll7_ctrl;
+ u32 resv1[3];
+ u32 pll2_ctrl;
+ u32 resv2[3];
+ u32 pll2_ss;
+ u32 resv3[3];
+ u32 pll2_num;
+ u32 resv4[3];
+ u32 pll2_denom;
+ u32 resv5[3];
+ u32 pll4_ctrl;
+ u32 resv6[3];
+ u32 pll4_num;
+ u32 resv7[3];
+ u32 pll4_denom;
+ u32 pll6_ctrl;
+ u32 resv8[3];
+ u32 pll6_num;
+ u32 resv9[3];
+ u32 pll6_denom;
+ u32 resv10[3];
+ u32 pll5_ctrl;
+ u32 resv11[3];
+ u32 pll3_pfd;
+ u32 resv12[3];
+ u32 pll2_pfd;
+ u32 resv13[3];
+ u32 reg_1p1;
+ u32 resv14[3];
+ u32 reg_3p0;
+ u32 resv15[3];
+ u32 reg_2p5;
+ u32 resv16[7];
+ u32 ana_misc0;
+ u32 resv17[3];
+ u32 ana_misc1;
+ u32 resv18[63];
+ u32 anadig_digprog;
+ u32 resv19[3];
+ u32 pll1_ctrl;
+ u32 resv20[3];
+ u32 pll1_ss;
+ u32 resv21[3];
+ u32 pll1_num;
+ u32 resv22[3];
+ u32 pll1_denom;
+ u32 resv23[3];
+ u32 pll1_pdf;
+ u32 resv24[3];
+ u32 pll_lock;
+};
+#endif
+
+#define CCM_CCR_FIRC_EN (1 << 16)
+#define CCM_CCR_OSCNT_MASK 0xff
+#define CCM_CCR_OSCNT(v) ((v) & 0xff)
+
+#define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET 19
+#define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK (0x7 << 19)
+#define CCM_CCSR_PLL2_PFD_CLK_SEL(v) (((v) & 0x7) << 19)
+
+#define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET 16
+#define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK (0x7 << 16)
+#define CCM_CCSR_PLL1_PFD_CLK_SEL(v) (((v) & 0x7) << 16)
+
+#define CCM_CCSR_PLL2_PFD4_EN (1 << 15)
+#define CCM_CCSR_PLL2_PFD3_EN (1 << 14)
+#define CCM_CCSR_PLL2_PFD2_EN (1 << 13)
+#define CCM_CCSR_PLL2_PFD1_EN (1 << 12)
+#define CCM_CCSR_PLL1_PFD4_EN (1 << 11)
+#define CCM_CCSR_PLL1_PFD3_EN (1 << 10)
+#define CCM_CCSR_PLL1_PFD2_EN (1 << 9)
+#define CCM_CCSR_PLL1_PFD1_EN (1 << 8)
+
+#define CCM_CCSR_DDRC_CLK_SEL(v) ((v) << 6)
+#define CCM_CCSR_FAST_CLK_SEL(v) ((v) << 5)
+
+#define CCM_CCSR_SYS_CLK_SEL_OFFSET 0
+#define CCM_CCSR_SYS_CLK_SEL_MASK 0x7
+#define CCM_CCSR_SYS_CLK_SEL(v) ((v) & 0x7)
+
+#define CCM_CACRR_IPG_CLK_DIV_OFFSET 11
+#define CCM_CACRR_IPG_CLK_DIV_MASK (0x3 << 11)
+#define CCM_CACRR_IPG_CLK_DIV(v) (((v) & 0x3) << 11)
+#define CCM_CACRR_BUS_CLK_DIV_OFFSET 3
+#define CCM_CACRR_BUS_CLK_DIV_MASK (0x7 << 3)
+#define CCM_CACRR_BUS_CLK_DIV(v) (((v) & 0x7) << 3)
+#define CCM_CACRR_ARM_CLK_DIV_OFFSET 0
+#define CCM_CACRR_ARM_CLK_DIV_MASK 0x7
+#define CCM_CACRR_ARM_CLK_DIV(v) ((v) & 0x7)
+
+#define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET 18
+#define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 18)
+#define CCM_CSCMR1_ESDHC1_CLK_SEL(v) (((v) & 0x3) << 18)
+
+#define CCM_CSCDR1_RMII_CLK_EN (1 << 24)
+
+#define CCM_CSCDR2_ESDHC1_EN (1 << 29)
+#define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET 20
+#define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK (0xf << 20)
+#define CCM_CSCDR2_ESDHC1_CLK_DIV(v) (((v) & 0xf) << 20)
+
+#define CCM_CSCMR2_RMII_CLK_SEL_OFFSET 4
+#define CCM_CSCMR2_RMII_CLK_SEL_MASK (0x3 << 4)
+#define CCM_CSCMR2_RMII_CLK_SEL(v) (((v) & 0x3) << 4)
+
+#define CCM_REG_CTRL_MASK 0xffffffff
+#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
+#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
+#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
+#define CCM_CCGR2_IOMUXC_CTRL_MASK (0x3 << 16)
+#define CCM_CCGR2_PORTA_CTRL_MASK (0x3 << 18)
+#define CCM_CCGR2_PORTB_CTRL_MASK (0x3 << 20)
+#define CCM_CCGR2_PORTC_CTRL_MASK (0x3 << 22)
+#define CCM_CCGR2_PORTD_CTRL_MASK (0x3 << 24)
+#define CCM_CCGR2_PORTE_CTRL_MASK (0x3 << 26)
+#define CCM_CCGR3_ANADIG_CTRL_MASK 0x3
+#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 << 20)
+#define CCM_CCGR4_CCM_CTRL_MASK (0x3 << 22)
+#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
+#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
+#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
+#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
+#define CCM_CCGR9_FEC0_CTRL_MASK 0x3
+#define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2)
+
+#define ANADIG_PLL2_CTRL_ENABLE (1 << 13)
+#define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12)
+#define ANADIG_PLL2_CTRL_DIV_SELECT 1
+#define ANADIG_PLL1_CTRL_ENABLE (1 << 13)
+#define ANADIG_PLL1_CTRL_POWERDOWN (1 << 12)
+#define ANADIG_PLL1_CTRL_DIV_SELECT 1
+
+#define FASE_CLK_FREQ 24000000
+#define SLOW_CLK_FREQ 32000
+#define PLL1_PFD1_FREQ 500000000
+#define PLL1_PFD2_FREQ 452000000
+#define PLL1_PFD3_FREQ 396000000
+#define PLL1_PFD4_FREQ 528000000
+#define PLL1_MAIN_FREQ 528000000
+#define PLL2_PFD1_FREQ 500000000
+#define PLL2_PFD2_FREQ 396000000
+#define PLL2_PFD3_FREQ 339000000
+#define PLL2_PFD4_FREQ 413000000
+#define PLL2_MAIN_FREQ 528000000
+#define PLL3_MAIN_FREQ 480000000
+#define PLL3_PFD3_FREQ 298000000
+#define PLL5_MAIN_FREQ 500000000
+
+#define ENET_EXTERNAL_CLK 50000000
+#define AUDIO_EXTERNAL_CLK 24576000
+
+#endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
new file mode 100644
index 0000000..c9df32a
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -0,0 +1,419 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_IMX_REGS_H__
+#define __ASM_ARCH_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define IRAM_BASE_ADDR 0x3F000000 /* internal ram */
+#define IRAM_SIZE 0x00080000 /* 512 KB */
+
+#define AIPS0_BASE_ADDR 0x40000000
+#define AIPS1_BASE_ADDR 0x40080000
+
+/* AIPS 0 */
+#define MSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001000)
+#define MSCM_IR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00001800)
+#define CA5SCU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00002000)
+#define CA5_INTD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00003000)
+#define CA5_L2C_BASE_ADDR (AIPS0_BASE_ADDR + 0x00006000)
+#define NIC0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00008000)
+#define NIC1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00009000)
+#define NIC2_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000A000)
+#define NIC3_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000B000)
+#define NIC4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000C000)
+#define NIC5_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000D000)
+#define NIC6_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000E000)
+#define NIC7_BASE_ADDR (AIPS0_BASE_ADDR + 0x0000F000)
+#define AHBTZASC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00010000)
+#define TZASC_SYS0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00011000)
+#define TZASC_SYS1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00012000)
+#define TZASC_GFX_BASE_ADDR (AIPS0_BASE_ADDR + 0x00013000)
+#define TZASC_DDR0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00014000)
+#define TZASC_DDR1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00015000)
+#define CSU_BASE_ADDR (AIPS0_BASE_ADDR + 0x00017000)
+#define DMA0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00018000)
+#define DMA0_TCD_BASE_ADDR (AIPS0_BASE_ADDR + 0x00019000)
+#define SEMA4_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001D000)
+#define FB_BASE_ADDR (AIPS0_BASE_ADDR + 0x0001E000)
+#define DMA_MUX0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00024000)
+#define UART0_BASE (AIPS0_BASE_ADDR + 0x00027000)
+#define UART1_BASE (AIPS0_BASE_ADDR + 0x00028000)
+#define UART2_BASE (AIPS0_BASE_ADDR + 0x00029000)
+#define UART3_BASE (AIPS0_BASE_ADDR + 0x0002A000)
+#define SPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002C000)
+#define SPI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002D000)
+#define SAI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0002F000)
+#define SAI1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00030000)
+#define SAI2_BASE_ADDR (AIPS0_BASE_ADDR + 0x00031000)
+#define SAI3_BASE_ADDR (AIPS0_BASE_ADDR + 0x00032000)
+#define CRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00033000)
+#define PDB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00036000)
+#define PIT_BASE_ADDR (AIPS0_BASE_ADDR + 0x00037000)
+#define FTM0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00038000)
+#define FTM1_BASE_ADDR (AIPS0_BASE_ADDR + 0x00039000)
+#define ADC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003B000)
+#define TCON0_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003D000)
+#define WDOG1_BASE_ADDR (AIPS0_BASE_ADDR + 0x0003E000)
+#define LPTMR_BASE_ADDR (AIPS0_BASE_ADDR + 0x00040000)
+#define RLE_BASE_ADDR (AIPS0_BASE_ADDR + 0x00042000)
+#define MLB_BASE_ADDR (AIPS0_BASE_ADDR + 0x00043000)
+#define QSPI0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00044000)
+#define IOMUXC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00048000)
+#define ANADIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00050000)
+#define SCSCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x00052000)
+#define ASRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x00060000)
+#define SPDIF_BASE_ADDR (AIPS0_BASE_ADDR + 0x00061000)
+#define ESAI_BASE_ADDR (AIPS0_BASE_ADDR + 0x00062000)
+#define ESAI_FIFO_BASE_ADDR (AIPS0_BASE_ADDR + 0x00063000)
+#define WDOG_BASE_ADDR (AIPS0_BASE_ADDR + 0x00065000)
+#define I2C0_BASE_ADDR (AIPS0_BASE_ADDR + 0x00066000)
+#define WKUP_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006A000)
+#define CCM_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006B000)
+#define GPC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006C000)
+#define VREG_DIG_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006D000)
+#define SRC_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006E000)
+#define CMU_BASE_ADDR (AIPS0_BASE_ADDR + 0x0006F000)
+
+/* AIPS 1 */
+#define OCOTP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00025000)
+#define DDR_BASE_ADDR (AIPS1_BASE_ADDR + 0x0002E000)
+#define ESDHC0_BASE_ADDR (AIPS1_BASE_ADDR + 0x00031000)
+#define ESDHC1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00032000)
+#define ENET_BASE_ADDR (AIPS1_BASE_ADDR + 0x00050000)
+
+/* MUX mode and PAD ctrl are in one register */
+#define CONFIG_IOMUX_SHARE_CONF_REG
+
+#define FEC_QUIRK_ENET_MAC
+
+/* MSCM interrupt rounter */
+#define MSCM_IRSPRC_CP0_EN 1
+#define MSCM_IRSPRC_NUM 112
+
+/* DDRMC */
+#define DDRMC_PHY_DQ_TIMING 0x00002613
+#define DDRMC_PHY_DQS_TIMING 0x00002615
+#define DDRMC_PHY_CTRL 0x01210080
+#define DDRMC_PHY_MASTER_CTRL 0x0001012a
+#define DDRMC_PHY_SLAVE_CTRL 0x00012020
+
+#define DDRMC_PHY50_DDR3_MODE (1 << 12)
+#define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8)
+
+#define DDRMC_CR00_DRAM_CLASS_DDR3 (0x6 << 8)
+#define DDRMC_CR00_DRAM_CLASS_LPDDR2 (0x5 << 8)
+#define DDRMC_CR00_START 1
+#define DDRMC_CR02_DRAM_TINIT(v) ((v) & 0xffffff)
+#define DDRMC_CR10_TRST_PWRON(v) (v)
+#define DDRMC_CR11_CKE_INACTIVE(v) (v)
+#define DDRMC_CR12_WRLAT(v) (((v) & 0x1f) << 8)
+#define DDRMC_CR12_CASLAT_LIN(v) ((v) & 0x3f)
+#define DDRMC_CR13_TRC(v) (((v) & 0xff) << 24)
+#define DDRMC_CR13_TRRD(v) (((v) & 0xff) << 16)
+#define DDRMC_CR13_TCCD(v) (((v) & 0x1f) << 8)
+#define DDRMC_CR13_TBST_INT_INTERVAL(v) ((v) & 0x7)
+#define DDRMC_CR14_TFAW(v) (((v) & 0x3f) << 24)
+#define DDRMC_CR14_TRP(v) (((v) & 0x1f) << 16)
+#define DDRMC_CR14_TWTR(v) (((v) & 0xf) << 8)
+#define DDRMC_CR14_TRAS_MIN(v) ((v) & 0xff)
+#define DDRMC_CR16_TMRD(v) (((v) & 0x1f) << 24)
+#define DDRMC_CR16_TRTP(v) (((v) & 0xf) << 16)
+#define DDRMC_CR17_TRAS_MAX(v) (((v) & 0x1ffff) << 8)
+#define DDRMC_CR17_TMOD(v) ((v) & 0xff)
+#define DDRMC_CR18_TCKESR(v) (((v) & 0x1f) << 8)
+#define DDRMC_CR18_TCKE(v) ((v) & 0x7)
+#define DDRMC_CR20_AP_EN (1 << 24)
+#define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16)
+#define DDRMC_CR21_TRAS_LOCKOUT (1 << 8)
+#define DDRMC_CR21_CCMAP_EN 1
+#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16)
+#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24)
+#define DDRMC_CR23_TDLL(v) ((v) & 0xff)
+#define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f)
+#define DDRMC_CR25_TREF_EN (1 << 16)
+#define DDRMC_CR26_TREF(v) (((v) & 0xffff) << 16)
+#define DDRMC_CR26_TRFC(v) ((v) & 0x3ff)
+#define DDRMC_CR28_TREF_INT(v) ((v) & 0xffff)
+#define DDRMC_CR29_TPDEX(v) ((v) & 0xffff)
+#define DDRMC_CR30_TXPDLL(v) ((v) & 0xffff)
+#define DDRMC_CR31_TXSNR(v) (((v) & 0xffff) << 16)
+#define DDRMC_CR31_TXSR(v) ((v) & 0xffff)
+#define DDRMC_CR33_EN_QK_SREF (1 << 16)
+#define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16)
+#define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8)
+#define DDRMC_CR38_FREQ_CHG_EN (1 << 8)
+#define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0xffff) << 16)
+#define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8)
+#define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3)
+#define DDRMC_CR41_PHY_INI_STRT_INI_DIS 1
+#define DDRMC_CR48_MR1_DA_0(v) (((v) & 0xffff) << 16)
+#define DDRMC_CR48_MR0_DA_0(v) ((v) & 0xffff)
+#define DDRMC_CR66_ZQCL(v) (((v) & 0xfff) << 16)
+#define DDRMC_CR66_ZQINIT(v) ((v) & 0xfff)
+#define DDRMC_CR67_ZQCS(v) ((v) & 0xfff)
+#define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8)
+#define DDRMC_CR70_REF_PER_ZQ(v) (v)
+#define DDRMC_CR72_ZQCS_ROTATE (1 << 24)
+#define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24)
+#define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16)
+#define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8)
+#define DDRMC_CR74_BANKSPLT_EN (1 << 24)
+#define DDRMC_CR74_ADDR_CMP_EN (1 << 16)
+#define DDRMC_CR74_CMD_AGE_CNT(v) (((v) & 0xff) << 8)
+#define DDRMC_CR74_AGE_CNT(v) ((v) & 0xff)
+#define DDRMC_CR75_RW_PG_EN (1 << 24)
+#define DDRMC_CR75_RW_EN (1 << 16)
+#define DDRMC_CR75_PRI_EN (1 << 8)
+#define DDRMC_CR75_PLEN 1
+#define DDRMC_CR76_NQENT_ACTDIS(v) (((v) & 0x7) << 24)
+#define DDRMC_CR76_D_RW_G_BKCN(v) (((v) & 0x3) << 16)
+#define DDRMC_CR76_W2R_SPLT_EN (1 << 8)
+#define DDRMC_CR76_CS_EN 1
+#define DDRMC_CR77_CS_MAP (1 << 24)
+#define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8)
+#define DDRMC_CR77_SWAP_EN 1
+#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
+#define DDRMC_CR79_CTLUPD_AREF (1 << 24)
+#define DDRMC_CR82_INT_MASK 0x1fffffff
+#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24)
+#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16)
+#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
+#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
+#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16)
+#define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8)
+#define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f)
+#define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8)
+#define DDRMC_CR110_RDLVL_DL_1(v) ((v) & 0xff)
+#define DDRMC_CR114_RDLVL_GTDL_2(v) (((v) & 0xffff) << 8)
+#define DDRMC_CR117_AXI0_W_PRI(v) (((v) & 0x3) << 8)
+#define DDRMC_CR117_AXI0_R_PRI(v) ((v) & 0x3)
+#define DDRMC_CR118_AXI1_W_PRI(v) (((v) & 0x3) << 24)
+#define DDRMC_CR118_AXI1_R_PRI(v) (((v) & 0x3) << 16)
+#define DDRMC_CR120_AXI0_PRI1_RPRI(v) (((v) & 0xf) << 24)
+#define DDRMC_CR120_AXI0_PRI0_RPRI(v) (((v) & 0xf) << 16)
+#define DDRMC_CR121_AXI0_PRI3_RPRI(v) (((v) & 0xf) << 8)
+#define DDRMC_CR121_AXI0_PRI2_RPRI(v) ((v) & 0xf)
+#define DDRMC_CR122_AXI1_PRI1_RPRI(v) (((v) & 0xf) << 24)
+#define DDRMC_CR122_AXI1_PRI0_RPRI(v) (((v) & 0xf) << 16)
+#define DDRMC_CR122_AXI0_PRIRLX(v) ((v) & 0x3ff)
+#define DDRMC_CR123_AXI1_PRI3_RPRI(v) (((v) & 0xf) << 8)
+#define DDRMC_CR123_AXI1_PRI2_RPRI(v) ((v) & 0xf)
+#define DDRMC_CR124_AXI1_PRIRLX(v) ((v) & 0x3ff)
+#define DDRMC_CR126_PHY_RDLAT(v) (((v) & 0x3f) << 8)
+#define DDRMC_CR132_WRLAT_ADJ(v) (((v) & 0x1f) << 8)
+#define DDRMC_CR132_RDLAT_ADJ(v) ((v) & 0x3f)
+#define DDRMC_CR139_PHY_WRLV_RESPLAT(v) (((v) & 0xff) << 24)
+#define DDRMC_CR139_PHY_WRLV_LOAD(v) (((v) & 0xff) << 16)
+#define DDRMC_CR139_PHY_WRLV_DLL(v) (((v) & 0xff) << 8)
+#define DDRMC_CR139_PHY_WRLV_EN(v) ((v) & 0xff)
+#define DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(v) (((v) & 0x1f) << 27)
+#define DDRMC_CR154_PAD_ZQ_MODE(v) (((v) & 0x3) << 21)
+#define DDRMC_CR155_AXI0_AWCACHE (1 << 10)
+#define DDRMC_CR155_PAD_ODT_BYTE1(v) ((v) & 0x7)
+#define DDRMC_CR158_TWR(v) ((v) & 0x3f)
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+/* System Reset Controller (SRC) */
+struct src {
+ u32 scr;
+ u32 sbmr1;
+ u32 srsr;
+ u32 secr;
+ u32 gpsr;
+ u32 sicr;
+ u32 simr;
+ u32 sbmr2;
+ u32 gpr0;
+ u32 gpr1;
+ u32 gpr2;
+ u32 gpr3;
+ u32 gpr4;
+ u32 hab0;
+ u32 hab1;
+ u32 hab2;
+ u32 hab3;
+ u32 hab4;
+ u32 hab5;
+ u32 misc0;
+ u32 misc1;
+ u32 misc2;
+ u32 misc3;
+};
+
+/* Periodic Interrupt Timer (PIT) */
+struct pit_reg {
+ u32 mcr;
+ u32 recv0[55];
+ u32 ltmr64h;
+ u32 ltmr64l;
+ u32 recv1[6];
+ u32 ldval0;
+ u32 cval0;
+ u32 tctrl0;
+ u32 tflg0;
+ u32 ldval1;
+ u32 cval1;
+ u32 tctrl1;
+ u32 tflg1;
+ u32 ldval2;
+ u32 cval2;
+ u32 tctrl2;
+ u32 tflg2;
+ u32 ldval3;
+ u32 cval3;
+ u32 tctrl3;
+ u32 tflg3;
+ u32 ldval4;
+ u32 cval4;
+ u32 tctrl4;
+ u32 tflg4;
+ u32 ldval5;
+ u32 cval5;
+ u32 tctrl5;
+ u32 tflg5;
+ u32 ldval6;
+ u32 cval6;
+ u32 tctrl6;
+ u32 tflg6;
+ u32 ldval7;
+ u32 cval7;
+ u32 tctrl7;
+ u32 tflg7;
+};
+
+/* Watchdog Timer (WDOG) */
+struct wdog_regs {
+ u16 wcr;
+ u16 wsr;
+ u16 wrsr;
+ u16 wicr;
+ u16 wmcr;
+};
+
+/* LPDDR2/DDR3 SDRAM Memory Controller (DDRMC) */
+struct ddrmr_regs {
+ u32 cr[162];
+ u32 rsvd[94];
+ u32 phy[53];
+};
+
+/* On-Chip One Time Programmable Controller (OCOTP) */
+struct ocotp_regs {
+ u32 ctrl;
+ u32 ctrl_set;
+ u32 ctrl_clr;
+ u32 ctrl_tog;
+ u32 timing;
+ u32 rsvd0[3];
+ u32 data;
+ u32 rsvd1[3];
+ u32 read_ctrl;
+ u32 rsvd2[3];
+ u32 read_fuse_data;
+ u32 rsvd3[7];
+ u32 scs;
+ u32 scs_set;
+ u32 scs_clr;
+ u32 scs_tog;
+ u32 crc_addr;
+ u32 rsvd4[3];
+ u32 crc_value;
+ u32 rsvd5[3];
+ u32 version;
+ u32 rsvd6[0xdb];
+
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ } bank[16];
+};
+
+struct fuse_bank0_regs {
+ u32 lock;
+ u32 rsvd0[3];
+ u32 uid_low;
+ u32 rsvd1[3];
+ u32 uid_high;
+ u32 rsvd2[0x17];
+};
+
+struct fuse_bank4_regs {
+ u32 sjc_resp0;
+ u32 rsvd0[3];
+ u32 sjc_resp1;
+ u32 rsvd1[3];
+ u32 mac_addr0;
+ u32 rsvd2[3];
+ u32 mac_addr1;
+ u32 rsvd3[3];
+ u32 mac_addr2;
+ u32 rsvd4[3];
+ u32 mac_addr3;
+ u32 rsvd5[3];
+ u32 gp1;
+ u32 rsvd6[3];
+ u32 gp2;
+ u32 rsvd7[3];
+};
+
+/* UART */
+struct lpuart_fsl {
+ u8 ubdh;
+ u8 ubdl;
+ u8 uc1;
+ u8 uc2;
+ u8 us1;
+ u8 us2;
+ u8 uc3;
+ u8 ud;
+ u8 uma1;
+ u8 uma2;
+ u8 uc4;
+ u8 uc5;
+ u8 ued;
+ u8 umodem;
+ u8 uir;
+ u8 reserved;
+ u8 upfifo;
+ u8 ucfifo;
+ u8 usfifo;
+ u8 utwfifo;
+ u8 utcfifo;
+ u8 urwfifo;
+ u8 urcfifo;
+ u8 rsvd[28];
+};
+
+/* MSCM Interrupt Router */
+struct mscm_ir {
+ u32 ircp0ir;
+ u32 ircp1ir;
+ u32 rsvd1[6];
+ u32 ircpgir;
+ u32 rsvd2[23];
+ u16 irsprc[112];
+ u16 rsvd3[848];
+};
+
+#endif /* __ASSEMBLER__*/
+
+#endif /* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
new file mode 100644
index 0000000..1c728fa
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IOMUX_VF610_H__
+#define __IOMUX_VF610_H__
+
+#include <asm/imx-common/iomux-v3.h>
+
+/* Pad control groupings */
+#define VF610_UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_25ohm | \
+ PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_SDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_20ohm | \
+ PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
+ PAD_CTL_OBE_IBE_ENABLE)
+#define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm
+
+enum {
+ VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTB4__UART1_TX = IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, VF610_UART_PAD_CTRL),
+ VF610_PAD_PTB5__UART1_RX = IOMUX_PAD(0x006c, 0x006c, 2, 0x037c, 0, VF610_UART_PAD_CTRL),
+ VF610_PAD_PTC1__RMII0_MDIO = IOMUX_PAD(0x00b8, 0x00b8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC0__RMII0_MDC = IOMUX_PAD(0x00b4, 0x00b4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC2__RMII0_CRS_DV = IOMUX_PAD(0x00bc, 0x00bc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC3__RMII0_RD1 = IOMUX_PAD(0x00c0, 0x00c0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC4__RMII0_RD0 = IOMUX_PAD(0x00c4, 0x00c4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC5__RMII0_RXER = IOMUX_PAD(0x00c8, 0x00c8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC6__RMII0_TD1 = IOMUX_PAD(0x00cc, 0x00cc, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC7__RMII0_TD0 = IOMUX_PAD(0x00D0, 0x00D0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTC8__RMII0_TXEN = IOMUX_PAD(0x00D4, 0x00D4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
+ VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTA25__ESDHC1_CMD = IOMUX_PAD(0x003c, 0x003c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTA26__ESDHC1_DAT0 = IOMUX_PAD(0x0040, 0x0040, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTA27__ESDHC1_DAT1 = IOMUX_PAD(0x0044, 0x0044, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTA28__ESDHC1_DAT2 = IOMUX_PAD(0x0048, 0x0048, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTA29__ESDHC1_DAT3 = IOMUX_PAD(0x004c, 0x004c, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A12__DDR_A_12 = IOMUX_PAD(0x022c, 0x022c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A11__DDR_A_11 = IOMUX_PAD(0x0230, 0x0230, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A10__DDR_A_10 = IOMUX_PAD(0x0234, 0x0234, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A9__DDR_A_9 = IOMUX_PAD(0x0238, 0x0238, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A8__DDR_A_8 = IOMUX_PAD(0x023c, 0x023c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A7__DDR_A_7 = IOMUX_PAD(0x0240, 0x0240, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A6__DDR_A_6 = IOMUX_PAD(0x0244, 0x0244, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A5__DDR_A_5 = IOMUX_PAD(0x0248, 0x0248, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A4__DDR_A_4 = IOMUX_PAD(0x024c, 0x024c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A3__DDR_A_3 = IOMUX_PAD(0x0250, 0x0250, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A2__DDR_A_2 = IOMUX_PAD(0x0254, 0x0254, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_A1__DDR_A_1 = IOMUX_PAD(0x0258, 0x0258, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_BA2__DDR_BA_2 = IOMUX_PAD(0x0260, 0x0260, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_BA1__DDR_BA_1 = IOMUX_PAD(0x0264, 0x0264, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_BA0__DDR_BA_0 = IOMUX_PAD(0x0268, 0x0268, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_CAS__DDR_CAS_B = IOMUX_PAD(0x026c, 0x026c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_CKE__DDR_CKE_0 = IOMUX_PAD(0x0270, 0x0270, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_CLK__DDR_CLK_0 = IOMUX_PAD(0x0274, 0x0274, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_CS__DDR_CS_B_0 = IOMUX_PAD(0x0278, 0x0278, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D15__DDR_D_15 = IOMUX_PAD(0x027c, 0x027c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D14__DDR_D_14 = IOMUX_PAD(0x0280, 0x0280, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D13__DDR_D_13 = IOMUX_PAD(0x0284, 0x0284, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D12__DDR_D_12 = IOMUX_PAD(0x0288, 0x0288, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D11__DDR_D_11 = IOMUX_PAD(0x028c, 0x028c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D10__DDR_D_10 = IOMUX_PAD(0x0290, 0x0290, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D9__DDR_D_9 = IOMUX_PAD(0x0294, 0x0294, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D8__DDR_D_8 = IOMUX_PAD(0x0298, 0x0298, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D7__DDR_D_7 = IOMUX_PAD(0x029c, 0x029c, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D6__DDR_D_6 = IOMUX_PAD(0x02a0, 0x02a0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D5__DDR_D_5 = IOMUX_PAD(0x02a4, 0x02a4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D4__DDR_D_4 = IOMUX_PAD(0x02a8, 0x02a8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D3__DDR_D_3 = IOMUX_PAD(0x02ac, 0x02ac, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D2__DDR_D_2 = IOMUX_PAD(0x02b0, 0x02b0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D1__DDR_D_1 = IOMUX_PAD(0x02b4, 0x02b4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_D0__DDR_D_0 = IOMUX_PAD(0x02b8, 0x02b8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_DQM1__DDR_DQM_1 = IOMUX_PAD(0x02bc, 0x02bc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_DQM0__DDR_DQM_0 = IOMUX_PAD(0x02c0, 0x02c0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_DQS1__DDR_DQS_1 = IOMUX_PAD(0x02c4, 0x02c4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_DQS0__DDR_DQS_0 = IOMUX_PAD(0x02c8, 0x02c8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_RAS__DDR_RAS_B = IOMUX_PAD(0x02cc, 0x02cc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_WE__DDR_WE_B = IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_ODT1__DDR_ODT_0 = IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+ VF610_PAD_DDR_ODT0__DDR_ODT_1 = IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+};
+
+#endif /* __IOMUX_VF610_H__ */