diff options
Diffstat (limited to 'arch/arm/include/asm')
46 files changed, 1595 insertions, 1810 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index 19ccf5c..5399bb8 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -14,7 +14,7 @@ #include <asm/arch/clocks_am33xx.h> #include <asm/arch/hardware.h> -#ifdef CONFIG_TI81XX +#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X) #include <asm/arch/clock_ti81xx.h> #endif diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 653ec1b..bc1dab5 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -29,6 +29,7 @@ #define NUM_OPPS 6 extern void enable_dmm_clocks(void); +extern void enable_emif_clocks(void); extern const struct dpll_params dpll_core_opp100; extern struct dpll_params dpll_mpu_opp100; diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 8cae291..e8d7d54 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -36,12 +36,6 @@ #define TCFG_RESET BIT(0) /* software reset */ #define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */ #define TCFG_IDLEMOD_SHIFT (2) /* power management */ -/* device type */ -#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) -#define TST_DEVICE 0x0 -#define EMU_DEVICE 0x1 -#define HS_DEVICE 0x2 -#define GP_DEVICE 0x3 /* cpu-id for AM43XX AM33XX and TI81XX family */ #define AM437X 0xB98C diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 43e122e..a97ebb5 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -354,9 +354,15 @@ struct ddr_ctrl { unsigned int ddrckectrl; }; +#ifdef CONFIG_TI816X +void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl, + const struct emif_regs *regs, + const struct dmm_lisa_map_regs *lisa_regs, int nrs); +#else void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr); +#endif void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); #endif /* _DDR_DEFS_H */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 3293caa..d2c5df8 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -21,7 +21,7 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 #define NON_SECURE_SRAM_IMG_END 0x4030B800 -#elif defined(CONFIG_TI81XX) +#elif defined(CONFIG_TI816X) || defined(CONFIG_TI814X) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 #define NON_SECURE_SRAM_IMG_END 0x4031B800 @@ -41,6 +41,9 @@ struct omap_boot_parameters { unsigned char boot_device; unsigned char reset_reason; }; + +#define DEVICE_TYPE_SHIFT 0x8 +#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) #endif #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h index 6935913..bf32782 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/clock.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h @@ -20,5 +20,7 @@ enum mxc_clock { }; unsigned int mxc_get_clock(enum mxc_clock clk); +ulong get_ddr_freq(ulong); +uint get_svr(void); #endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 93e6597..79e94f9 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -17,6 +17,7 @@ * To be aligned with MMU block size */ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ +#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */ #ifdef CONFIG_ARCH_LS2080A #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index d6a273a..c4e5ecc 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -353,4 +353,5 @@ static struct mm_region final_map[] = { int fsl_qoriq_core_to_cluster(unsigned int core); u32 cpu_mask(void); + #endif /* _FSL_LAYERSCAPE_CPU_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index cc3b079..497afe7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -8,6 +8,16 @@ #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ #define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ +#ifndef __ASSEMBLY__ +#include <linux/types.h> +#ifdef CONFIG_FSL_LSCH2 +#include <asm/arch/immap_lsch2.h> +#endif +#ifdef CONFIG_FSL_LSCH3 +#include <asm/arch/immap_lsch3.h> +#endif +#endif + #ifdef CONFIG_SYS_FSL_CCSR_GUR_LE #define gur_in32(a) in_le32(a) #define gur_out32(a, v) out_le32(a, v) @@ -120,4 +130,5 @@ void erratum_a010315(void); bool soc_has_dp_ddr(void); bool soc_has_aiop(void); #endif + #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */ diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index b052406..ec5b419 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -50,3 +50,10 @@ #define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3 u32 get_imx_reset_cause(void); +ulong get_systemPLLCLK(void); +ulong get_FCLK(void); +ulong get_HCLK(void); +ulong get_BCLK(void); +ulong get_PERCLK1(void); +ulong get_PERCLK2(void); +ulong get_PERCLK3(void); diff --git a/arch/arm/include/asm/arch-ls102xa/clock.h b/arch/arm/include/asm/arch-ls102xa/clock.h index fd36bb0..a1d6afe 100644 --- a/arch/arm/include/asm/arch-ls102xa/clock.h +++ b/arch/arm/include/asm/arch-ls102xa/clock.h @@ -19,5 +19,7 @@ enum mxc_clock { }; unsigned int mxc_get_clock(enum mxc_clock clk); +ulong get_ddr_freq(ulong); +uint get_svr(void); #endif /* __ASM_ARCH_LS102XA_CLOCK_H_ */ diff --git a/arch/arm/include/asm/arch-ls102xa/soc.h b/arch/arm/include/asm/arch-ls102xa/soc.h new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/soc.h diff --git a/arch/arm/include/asm/arch-omap3/omap.h b/arch/arm/include/asm/arch-omap3/omap.h index db763e4..8933f54 100644 --- a/arch/arm/include/asm/arch-omap3/omap.h +++ b/arch/arm/include/asm/arch-omap3/omap.h @@ -91,6 +91,9 @@ struct s32ktimer { unsigned int s32k_cr; /* 0x10 */ }; +#define DEVICE_TYPE_SHIFT 0x8 +#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) + #endif /* __ASSEMBLY__ */ #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index b86a776..1a3ff7d 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -100,7 +100,6 @@ struct s32ktimer { #define DEVICE_TYPE_SHIFT (0x8) #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) -#define DEVICE_GP 0x3 #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 8f31da1..2f005dd 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -127,7 +127,6 @@ struct s32ktimer { #define DEVICE_TYPE_SHIFT 0x6 #define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT) -#define DEVICE_GP 0x3 /* Output impedance control */ #define ds_120_ohm 0x0 diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h index aaef4b9..22278e1 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3036.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3036.h @@ -16,9 +16,9 @@ #define CORE_PERI_HZ 150000000 #define CORE_ACLK_HZ 300000000 -#define CPU_ACLK_HZ 150000000 -#define CPU_HCLK_HZ 300000000 -#define CPU_PCLK_HZ 300000000 +#define BUS_ACLK_HZ 148500000 +#define BUS_HCLK_HZ 148500000 +#define BUS_PCLK_HZ 74250000 #define PERI_ACLK_HZ 148500000 #define PERI_HCLK_HZ 148500000 @@ -68,102 +68,102 @@ struct pll_div { enum { /* PLLCON0*/ - PLL_POSTDIV1_MASK = 7, PLL_POSTDIV1_SHIFT = 12, - PLL_FBDIV_MASK = 0xfff, + PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT, PLL_FBDIV_SHIFT = 0, + PLL_FBDIV_MASK = 0xfff, /* PLLCON1 */ - PLL_DSMPD_MASK = 1, + PLL_RST_SHIFT = 14, PLL_DSMPD_SHIFT = 12, - PLL_LOCK_STATUS_MASK = 1, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, PLL_LOCK_STATUS_SHIFT = 10, - PLL_POSTDIV2_MASK = 7, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, PLL_POSTDIV2_SHIFT = 6, - PLL_REFDIV_MASK = 0x3f, + PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT, PLL_REFDIV_SHIFT = 0, - PLL_RST_SHIFT = 14, + PLL_REFDIV_MASK = 0x3f, /* CRU_MODE */ - GPLL_MODE_MASK = 3, GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT, GPLL_MODE_SLOW = 0, GPLL_MODE_NORM, GPLL_MODE_DEEP, - DPLL_MODE_MASK = 1, DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 1 << DPLL_MODE_SHIFT, DPLL_MODE_SLOW = 0, DPLL_MODE_NORM, - APLL_MODE_MASK = 1, APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 1 << APLL_MODE_SHIFT, APLL_MODE_SLOW = 0, APLL_MODE_NORM, /* CRU_CLK_SEL0_CON */ - CPU_CLK_PLL_SEL_MASK = 3, - CPU_CLK_PLL_SEL_SHIFT = 14, - CPU_CLK_PLL_SEL_APLL = 0, - CPU_CLK_PLL_SEL_DPLL, - CPU_CLK_PLL_SEL_GPLL, - ACLK_CPU_DIV_MASK = 0x1f, - ACLK_CPU_DIV_SHIFT = 8, - CORE_CLK_PLL_SEL_MASK = 1, + BUS_ACLK_PLL_SEL_SHIFT = 14, + BUS_ACLK_PLL_SEL_MASK = 3 << BUS_ACLK_PLL_SEL_SHIFT, + BUS_ACLK_PLL_SEL_APLL = 0, + BUS_ACLK_PLL_SEL_DPLL, + BUS_ACLK_PLL_SEL_GPLL, + BUS_ACLK_DIV_SHIFT = 8, + BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT, CORE_CLK_PLL_SEL_SHIFT = 7, + CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT, CORE_CLK_PLL_SEL_APLL = 0, CORE_CLK_PLL_SEL_GPLL, - CORE_DIV_CON_MASK = 0x1f, CORE_DIV_CON_SHIFT = 0, + CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT, /* CRU_CLK_SEL1_CON */ - CPU_PCLK_DIV_MASK = 7, - CPU_PCLK_DIV_SHIFT = 12, - CPU_HCLK_DIV_MASK = 3, - CPU_HCLK_DIV_SHIFT = 8, - CORE_ACLK_DIV_MASK = 7, + BUS_PCLK_DIV_SHIFT = 12, + BUS_PCLK_DIV_MASK = 7 << BUS_PCLK_DIV_SHIFT, + BUS_HCLK_DIV_SHIFT = 8, + BUS_HCLK_DIV_MASK = 3 << BUS_HCLK_DIV_SHIFT, CORE_ACLK_DIV_SHIFT = 4, - CORE_PERI_DIV_MASK = 0xf, + CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT, CORE_PERI_DIV_SHIFT = 0, + CORE_PERI_DIV_MASK = 0xf << CORE_PERI_DIV_SHIFT, /* CRU_CLKSEL10_CON */ - PERI_PLL_SEL_MASK = 3, PERI_PLL_SEL_SHIFT = 14, + PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT, PERI_PLL_APLL = 0, PERI_PLL_DPLL, PERI_PLL_GPLL, - PERI_PCLK_DIV_MASK = 3, PERI_PCLK_DIV_SHIFT = 12, - PERI_HCLK_DIV_MASK = 3, + PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT, PERI_HCLK_DIV_SHIFT = 8, - PERI_ACLK_DIV_MASK = 0x1f, + PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT, PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT, /* CRU_CLKSEL11_CON */ - SDIO_DIV_MASK = 0x7f, SDIO_DIV_SHIFT = 8, - MMC0_DIV_MASK = 0x7f, + SDIO_DIV_MASK = 0x7f << SDIO_DIV_SHIFT, MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0x7f << MMC0_DIV_SHIFT, /* CRU_CLKSEL12_CON */ - EMMC_PLL_MASK = 3, EMMC_PLL_SHIFT = 12, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, EMMC_SEL_APLL = 0, EMMC_SEL_DPLL, EMMC_SEL_GPLL, EMMC_SEL_24M, - SDIO_PLL_MASK = 3, SDIO_PLL_SHIFT = 10, + SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT, SDIO_SEL_APLL = 0, SDIO_SEL_DPLL, SDIO_SEL_GPLL, SDIO_SEL_24M, - MMC0_PLL_MASK = 3, MMC0_PLL_SHIFT = 8, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, MMC0_SEL_APLL = 0, MMC0_SEL_DPLL, MMC0_SEL_GPLL, MMC0_SEL_24M, - EMMC_DIV_MASK = 0x7f, EMMC_DIV_SHIFT = 0, + EMMC_DIV_MASK = 0x7f << EMMC_DIV_SHIFT, /* CRU_SOFTRST5_CON */ DDRCTRL_PSRST_SHIFT = 11, diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index d575f4a..cb0a935 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -64,135 +64,137 @@ check_member(rk3288_cru, cru_emmc_con[1], 0x021c); /* CRU_CLKSEL11_CON */ enum { HSICPHY_DIV_SHIFT = 8, - HSICPHY_DIV_MASK = 0x3f, + HSICPHY_DIV_MASK = 0x3f << HSICPHY_DIV_SHIFT, MMC0_PLL_SHIFT = 6, - MMC0_PLL_MASK = 3, + MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT, MMC0_PLL_SELECT_CODEC = 0, MMC0_PLL_SELECT_GENERAL, MMC0_PLL_SELECT_24MHZ, MMC0_DIV_SHIFT = 0, - MMC0_DIV_MASK = 0x3f, + MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT, }; /* CRU_CLKSEL12_CON */ enum { EMMC_PLL_SHIFT = 0xe, - EMMC_PLL_MASK = 3, + EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT, EMMC_PLL_SELECT_CODEC = 0, EMMC_PLL_SELECT_GENERAL, EMMC_PLL_SELECT_24MHZ, EMMC_DIV_SHIFT = 8, - EMMC_DIV_MASK = 0x3f, + EMMC_DIV_MASK = 0x3f < EMMC_DIV_SHIFT, SDIO0_PLL_SHIFT = 6, - SDIO0_PLL_MASK = 3, + SDIO0_PLL_MASK = 3 << SDIO0_PLL_SHIFT, SDIO0_PLL_SELECT_CODEC = 0, SDIO0_PLL_SELECT_GENERAL, SDIO0_PLL_SELECT_24MHZ, SDIO0_DIV_SHIFT = 0, - SDIO0_DIV_MASK = 0x3f, + SDIO0_DIV_MASK = 0x3f << SDIO0_DIV_SHIFT, }; /* CRU_CLKSEL21_CON */ enum { - MAC_DIV_CON_SHIFT = 0xf, - MAC_DIV_CON_MASK = 0x1f, + MAC_DIV_CON_SHIFT = 0xf, + MAC_DIV_CON_MASK = 0x1f << MAC_DIV_CON_SHIFT, - RMII_EXTCLK_SHIFT = 4, - RMII_EXTCLK_MASK = 1, + RMII_EXTCLK_SHIFT = 4, + RMII_EXTCLK_MASK = 1 << RMII_EXTCLK_SHIFT, RMII_EXTCLK_SELECT_INT_DIV_CLK = 0, RMII_EXTCLK_SELECT_EXT_CLK = 1, - EMAC_PLL_SHIFT = 0, - EMAC_PLL_MASK = 0x3, - EMAC_PLL_SELECT_NEW = 0x0, - EMAC_PLL_SELECT_CODEC = 0x1, - EMAC_PLL_SELECT_GENERAL = 0x2, + EMAC_PLL_SHIFT = 0, + EMAC_PLL_MASK = 0x3 << EMAC_PLL_SHIFT, + EMAC_PLL_SELECT_NEW = 0x0, + EMAC_PLL_SELECT_CODEC = 0x1, + EMAC_PLL_SELECT_GENERAL = 0x2, }; /* CRU_CLKSEL25_CON */ enum { SPI1_PLL_SHIFT = 0xf, - SPI1_PLL_MASK = 1, + SPI1_PLL_MASK = 1 << SPI1_PLL_SHIFT, SPI1_PLL_SELECT_CODEC = 0, SPI1_PLL_SELECT_GENERAL, SPI1_DIV_SHIFT = 8, - SPI1_DIV_MASK = 0x7f, + SPI1_DIV_MASK = 0x7f << SPI1_DIV_SHIFT, SPI0_PLL_SHIFT = 7, - SPI0_PLL_MASK = 1, + SPI0_PLL_MASK = 1 << SPI0_PLL_SHIFT, SPI0_PLL_SELECT_CODEC = 0, SPI0_PLL_SELECT_GENERAL, SPI0_DIV_SHIFT = 0, - SPI0_DIV_MASK = 0x7f, + SPI0_DIV_MASK = 0x7f << SPI0_DIV_SHIFT, }; /* CRU_CLKSEL37_CON */ enum { PCLK_CORE_DBG_DIV_SHIFT = 9, - PCLK_CORE_DBG_DIV_MASK = 0x1f, + PCLK_CORE_DBG_DIV_MASK = 0x1f << PCLK_CORE_DBG_DIV_SHIFT, ATCLK_CORE_DIV_CON_SHIFT = 4, - ATCLK_CORE_DIV_CON_MASK = 0x1f, + ATCLK_CORE_DIV_CON_MASK = 0x1f << ATCLK_CORE_DIV_CON_SHIFT, CLK_L2RAM_DIV_SHIFT = 0, - CLK_L2RAM_DIV_MASK = 7, + CLK_L2RAM_DIV_MASK = 7 << CLK_L2RAM_DIV_SHIFT, }; /* CRU_CLKSEL39_CON */ enum { ACLK_HEVC_PLL_SHIFT = 0xe, - ACLK_HEVC_PLL_MASK = 3, + ACLK_HEVC_PLL_MASK = 3 << ACLK_HEVC_PLL_SHIFT, ACLK_HEVC_PLL_SELECT_CODEC = 0, ACLK_HEVC_PLL_SELECT_GENERAL, ACLK_HEVC_PLL_SELECT_NEW, ACLK_HEVC_DIV_SHIFT = 8, - ACLK_HEVC_DIV_MASK = 0x1f, + ACLK_HEVC_DIV_MASK = 0x1f << ACLK_HEVC_DIV_SHIFT, SPI2_PLL_SHIFT = 7, - SPI2_PLL_MASK = 1, + SPI2_PLL_MASK = 1 << SPI2_PLL_SHIFT, SPI2_PLL_SELECT_CODEC = 0, SPI2_PLL_SELECT_GENERAL, SPI2_DIV_SHIFT = 0, - SPI2_DIV_MASK = 0x7f, + SPI2_DIV_MASK = 0x7f << SPI2_DIV_SHIFT, }; /* CRU_MODE_CON */ enum { + CRU_MODE_MASK = 3, + NPLL_MODE_SHIFT = 0xe, - NPLL_MODE_MASK = 3, + NPLL_MODE_MASK = CRU_MODE_MASK << NPLL_MODE_SHIFT, NPLL_MODE_SLOW = 0, NPLL_MODE_NORMAL, NPLL_MODE_DEEP, GPLL_MODE_SHIFT = 0xc, - GPLL_MODE_MASK = 3, + GPLL_MODE_MASK = CRU_MODE_MASK << GPLL_MODE_SHIFT, GPLL_MODE_SLOW = 0, GPLL_MODE_NORMAL, GPLL_MODE_DEEP, CPLL_MODE_SHIFT = 8, - CPLL_MODE_MASK = 3, + CPLL_MODE_MASK = CRU_MODE_MASK << CPLL_MODE_SHIFT, CPLL_MODE_SLOW = 0, CPLL_MODE_NORMAL, CPLL_MODE_DEEP, DPLL_MODE_SHIFT = 4, - DPLL_MODE_MASK = 3, + DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT, DPLL_MODE_SLOW = 0, DPLL_MODE_NORMAL, DPLL_MODE_DEEP, APLL_MODE_SHIFT = 0, - APLL_MODE_MASK = 3, + APLL_MODE_MASK = CRU_MODE_MASK << APLL_MODE_SHIFT, APLL_MODE_SLOW = 0, APLL_MODE_NORMAL, APLL_MODE_DEEP, @@ -201,21 +203,21 @@ enum { /* CRU_APLL_CON0 */ enum { CLKR_SHIFT = 8, - CLKR_MASK = 0x3f, + CLKR_MASK = 0x3f << CLKR_SHIFT, CLKOD_SHIFT = 0, - CLKOD_MASK = 0xf, + CLKOD_MASK = 0xf << CLKOD_SHIFT, }; /* CRU_APLL_CON1 */ enum { LOCK_SHIFT = 0x1f, - LOCK_MASK = 1, + LOCK_MASK = 1 << LOCK_SHIFT, LOCK_UNLOCK = 0, LOCK_LOCK, CLKF_SHIFT = 0, - CLKF_MASK = 0x1fff, + CLKF_MASK = 0x1fff << CLKF_SHIFT, }; #endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h new file mode 100644 index 0000000..4910ee7 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * Author: Andy Yan <andy.yan@rock-chips.com> + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RK3368_H +#define _ASM_ARCH_CRU_RK3368_H + +#include <common.h> + + +/* RK3368 clock numbers */ +enum rk3368_pll_id { + APLLB, + APLLL, + DPLL, + CPLL, + GPLL, + NPLL, + PLL_COUNT, +}; + +struct rk3368_cru { + struct rk3368_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + } pll[6]; + unsigned int reserved[0x28]; + unsigned int clksel_con[56]; + unsigned int reserved1[8]; + unsigned int clkgate_con[25]; + unsigned int reserved2[7]; + unsigned int glb_srst_fst_val; + unsigned int glb_srst_snd_val; + unsigned int reserved3[0x1e]; + unsigned int softrst_con[15]; + unsigned int reserved4[0x11]; + unsigned int misc_con; + unsigned int glb_cnt_th; + unsigned int glb_rst_con; + unsigned int glb_rst_st; + unsigned int reserved5[0x1c]; + unsigned int sdmmc_con[2]; + unsigned int sdio0_con[2]; + unsigned int sdio1_con[2]; + unsigned int emmc_con[2]; +}; +check_member(rk3368_cru, emmc_con[1], 0x41c); + +struct rk3368_clk_priv { + struct rk3368_cru *cru; + ulong rate; + bool has_bwadj; +}; + +enum { + /* PLL CON0 */ + PLL_NR_SHIFT = 8, + PLL_NR_MASK = GENMASK(13, 8), + PLL_OD_SHIFT = 0, + PLL_OD_MASK = GENMASK(3, 0), + + /* PLL CON1 */ + PLL_LOCK_STA = BIT(31), + PLL_NF_SHIFT = 0, + PLL_NF_MASK = GENMASK(12, 0), + + /* PLL CON2 */ + PLL_BWADJ_SHIFT = 0, + PLL_BWADJ_MASK = GENMASK(11, 0), + + /* PLL CON3 */ + PLL_MODE_SHIFT = 8, + PLL_MODE_MASK = GENMASK(9, 8), + PLL_MODE_SLOW = 0, + PLL_MODE_NORMAL = 1, + PLL_MODE_DEEP_SLOW = 3, + PLL_RESET_SHIFT = 5, + PLL_RESET = 1, + PLL_RESET_MASK = GENMASK(5, 5), + + /* CLKSEL12_CON */ + MCU_STCLK_DIV_SHIFT = 8, + MCU_STCLK_DIV_MASK = GENMASK(10, 8), + MCU_PLL_SEL_SHIFT = 7, + MCU_PLL_SEL_MASK = BIT(7), + MCU_PLL_SEL_CPLL = 0, + MCU_PLL_SEL_GPLL = 1, + MCU_CLK_DIV_SHIFT = 0, + MCU_CLK_DIV_MASK = GENMASK(4, 0), + + /* CLKSEL51_CON */ + MMC_PLL_SEL_SHIFT = 8, + MMC_PLL_SEL_MASK = GENMASK(9, 8), + MMC_PLL_SEL_CPLL = 0, + MMC_PLL_SEL_GPLL, + MMC_PLL_SEL_USBPHY_480M, + MMC_PLL_SEL_24M, + MMC_CLK_DIV_SHIFT = 0, + MMC_CLK_DIV_MASK = GENMASK(6, 0), + + /* SOFTRST1_CON */ + MCU_PO_SRST_MASK = BIT(13), + MCU_SYS_SRST_MASK = BIT(12), + + /* GLB_RST_CON */ + PMU_GLB_SRST_CTRL_SHIFT = 2, + PMU_GLB_SRST_CTRL_MASK = GENMASK(3, 2), + PMU_RST_BY_FST_GLB_SRST = 0, + PMU_RST_BY_SND_GLB_SRST = 1, + PMU_RST_DISABLE = 2, + WDT_GLB_SRST_CTRL_SHIFT = 1, + WDT_GLB_SRST_CTRL_MASK = BIT(1), + WDT_TRIGGER_SND_GLB_SRST = 0, + WDT_TRIGGER_FST_GLB_SRST = 1, + TSADC_GLB_SRST_CTRL_SHIFT = 0, + TSADC_GLB_SRST_CTRL_MASK = BIT(0), + TSADC_TRIGGER_SND_GLB_SRST = 0, + TSADC_TRIGGER_FST_GLB_SRST = 1, + +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h new file mode 100644 index 0000000..2a1ae69 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h @@ -0,0 +1,111 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * Author: Andy Yan <andy.yan@rock-chips.com> + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RV1108_H +#define _ASM_ARCH_CRU_RV1108_H + +#include <common.h> + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (600 * 1000000) +#define GPLL_HZ (594 * 1000000) + +struct rv1108_clk_priv { + struct rv1108_cru *cru; + ulong rate; +}; + +struct rv1108_cru { + struct rv1108_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int con5; + unsigned int reserved[2]; + } pll[3]; + unsigned int clksel_con[46]; + unsigned int reserved1[2]; + unsigned int clkgate_con[20]; + unsigned int reserved2[4]; + unsigned int softrst_con[13]; + unsigned int reserved3[3]; + unsigned int glb_srst_fst_val; + unsigned int glb_srst_snd_val; + unsigned int glb_cnt_th; + unsigned int misc_con; + unsigned int glb_rst_con; + unsigned int glb_rst_st; + unsigned int sdmmc_con[2]; + unsigned int sdio_con[2]; + unsigned int emmc_con[2]; +}; +check_member(rv1108_cru, emmc_con[1], 0x01ec); + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +enum { + /* PLL CON0 */ + FBDIV_MASK = 0xfff, + FBDIV_SHIFT = 0, + + /* PLL CON1 */ + POSTDIV2_SHIFT = 12, + POSTDIV2_MASK = 7 << POSTDIV2_SHIFT, + POSTDIV1_SHIFT = 8, + POSTDIV1_MASK = 7 << POSTDIV1_SHIFT, + REFDIV_MASK = 0x3f, + REFDIV_SHIFT = 0, + + /* PLL CON2 */ + LOCK_STA_SHIFT = 31, + LOCK_STA_MASK = 1 << LOCK_STA_SHIFT, + FRACDIV_MASK = 0xffffff, + FRACDIV_SHIFT = 0, + + /* PLL CON3 */ + WORK_MODE_SHIFT = 8, + WORK_MODE_MASK = 1 << WORK_MODE_SHIFT, + WORK_MODE_SLOW = 0, + WORK_MODE_NORMAL = 1, + DSMPD_SHIFT = 3, + DSMPD_MASK = 1 << DSMPD_SHIFT, + + /* CLKSEL0_CON */ + CORE_PLL_SEL_SHIFT = 8, + CORE_PLL_SEL_MASK = 3 << CORE_PLL_SEL_SHIFT, + CORE_PLL_SEL_APLL = 0, + CORE_PLL_SEL_GPLL = 1, + CORE_PLL_SEL_DPLL = 2, + CORE_CLK_DIV_SHIFT = 0, + CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, + + /* CLKSEL24_CON */ + MAC_PLL_SEL_SHIFT = 12, + MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, + MAC_PLL_SEL_APLL = 0, + MAC_PLL_SEL_GPLL = 1, + RMII_EXTCLK_SEL_SHIFT = 8, + RMII_EXTCLK_SEL_MASK = 1 << RMII_EXTCLK_SEL_SHIFT, + MAC_CLK_DIV_MASK = 0x1f, + MAC_CLK_DIV_SHIFT = 0, + + /* CLKSEL27_CON */ + SFC_PLL_SEL_SHIFT = 7, + SFC_PLL_SEL_MASK = 1 << SFC_PLL_SEL_SHIFT, + SFC_PLL_SEL_DPLL = 0, + SFC_PLL_SEL_GPLL = 1, + SFC_CLK_DIV_SHIFT = 0, + SFC_CLK_DIV_MASK = 0x3f << SFC_CLK_DIV_SHIFT, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h index 72d133c..7625f24 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h @@ -83,57 +83,56 @@ check_member(rk3036_grf, sdmmc_det_cnt, 0x304); /* GRF_GPIO0A_IOMUX */ enum { GPIO0A3_SHIFT = 6, - GPIO0A3_MASK = 1, + GPIO0A3_MASK = 1 << GPIO0A3_SHIFT, GPIO0A3_GPIO = 0, GPIO0A3_I2C1_SDA, GPIO0A2_SHIFT = 4, - GPIO0A2_MASK = 1, + GPIO0A2_MASK = 1 << GPIO0A2_SHIFT, GPIO0A2_GPIO = 0, GPIO0A2_I2C1_SCL, GPIO0A1_SHIFT = 2, - GPIO0A1_MASK = 3, + GPIO0A1_MASK = 3 << GPIO0A1_SHIFT, GPIO0A1_GPIO = 0, GPIO0A1_I2C0_SDA, GPIO0A1_PWM2, GPIO0A0_SHIFT = 0, - GPIO0A0_MASK = 3, + GPIO0A0_MASK = 3 << GPIO0A0_SHIFT, GPIO0A0_GPIO = 0, GPIO0A0_I2C0_SCL, GPIO0A0_PWM1, - }; /* GRF_GPIO0B_IOMUX */ enum { GPIO0B6_SHIFT = 12, - GPIO0B6_MASK = 3, + GPIO0B6_MASK = 3 << GPIO0B6_SHIFT, GPIO0B6_GPIO = 0, GPIO0B6_MMC1_D3, GPIO0B6_I2S1_SCLK, GPIO0B5_SHIFT = 10, - GPIO0B5_MASK = 3, + GPIO0B5_MASK = 3 << GPIO0B5_SHIFT, GPIO0B5_GPIO = 0, GPIO0B5_MMC1_D2, GPIO0B5_I2S1_SDI, GPIO0B4_SHIFT = 8, - GPIO0B4_MASK = 3, + GPIO0B4_MASK = 3 << GPIO0B4_SHIFT, GPIO0B4_GPIO = 0, GPIO0B4_MMC1_D1, GPIO0B4_I2S1_LRCKTX, GPIO0B3_SHIFT = 6, - GPIO0B3_MASK = 3, + GPIO0B3_MASK = 3 << GPIO0B3_SHIFT, GPIO0B3_GPIO = 0, GPIO0B3_MMC1_D0, GPIO0B3_I2S1_LRCKRX, GPIO0B1_SHIFT = 2, - GPIO0B1_MASK = 3, + GPIO0B1_MASK = 3 << GPIO0B1_SHIFT, GPIO0B1_GPIO = 0, GPIO0B1_MMC1_CLKOUT, GPIO0B1_I2S1_MCLK, @@ -148,28 +147,28 @@ enum { /* GRF_GPIO0C_IOMUX */ enum { GPIO0C4_SHIFT = 8, - GPIO0C4_MASK = 1, + GPIO0C4_MASK = 1 << GPIO0C4_SHIFT, GPIO0C4_GPIO = 0, GPIO0C4_DRIVE_VBUS, GPIO0C3_SHIFT = 6, - GPIO0C3_MASK = 1, + GPIO0C3_MASK = 1 << GPIO0C3_SHIFT, GPIO0C3_GPIO = 0, GPIO0C3_UART0_CTSN, GPIO0C2_SHIFT = 4, - GPIO0C2_MASK = 1, + GPIO0C2_MASK = 1 << GPIO0C2_SHIFT, GPIO0C2_GPIO = 0, GPIO0C2_UART0_RTSN, GPIO0C1_SHIFT = 2, - GPIO0C1_MASK = 1, + GPIO0C1_MASK = 1 << GPIO0C1_SHIFT, GPIO0C1_GPIO = 0, GPIO0C1_UART0_SIN, GPIO0C0_SHIFT = 0, - GPIO0C0_MASK = 1, + GPIO0C0_MASK = 1 << GPIO0C0_SHIFT, GPIO0C0_GPIO = 0, GPIO0C0_UART0_SOUT, }; @@ -177,17 +176,17 @@ enum { /* GRF_GPIO0D_IOMUX */ enum { GPIO0D4_SHIFT = 8, - GPIO0D4_MASK = 1, + GPIO0D4_MASK = 1 << GPIO0D4_SHIFT, GPIO0D4_GPIO = 0, GPIO0D4_SPDIF, GPIO0D3_SHIFT = 6, - GPIO0D3_MASK = 1, + GPIO0D3_MASK = 1 << GPIO0D3_SHIFT, GPIO0D3_GPIO = 0, GPIO0D3_PWM3, GPIO0D2_SHIFT = 4, - GPIO0D2_MASK = 1, + GPIO0D2_MASK = 1 << GPIO0D2_SHIFT, GPIO0D2_GPIO = 0, GPIO0D2_PWM0, }; @@ -195,33 +194,33 @@ enum { /* GRF_GPIO1A_IOMUX */ enum { GPIO1A5_SHIFT = 10, - GPIO1A5_MASK = 1, + GPIO1A5_MASK = 1 << GPIO1A5_SHIFT, GPIO1A5_GPIO = 0, GPIO1A5_I2S_SDI, GPIO1A4_SHIFT = 8, - GPIO1A4_MASK = 1, + GPIO1A4_MASK = 1 << GPIO1A4_SHIFT, GPIO1A4_GPIO = 0, GPIO1A4_I2S_SD0, GPIO1A3_SHIFT = 6, - GPIO1A3_MASK = 1, + GPIO1A3_MASK = 1 << GPIO1A3_SHIFT, GPIO1A3_GPIO = 0, GPIO1A3_I2S_LRCKTX, GPIO1A2_SHIFT = 4, - GPIO1A2_MASK = 6, + GPIO1A2_MASK = 6 << GPIO1A2_SHIFT, GPIO1A2_GPIO = 0, GPIO1A2_I2S_LRCKRX, GPIO1A2_I2S_PWM1_0, GPIO1A1_SHIFT = 2, - GPIO1A1_MASK = 1, + GPIO1A1_MASK = 1 << GPIO1A1_SHIFT, GPIO1A1_GPIO = 0, GPIO1A1_I2S_SCLK, GPIO1A0_SHIFT = 0, - GPIO1A0_MASK = 1, + GPIO1A0_MASK = 1 << GPIO1A0_SHIFT, GPIO1A0_GPIO = 0, GPIO1A0_I2S_MCLK, @@ -230,27 +229,27 @@ enum { /* GRF_GPIO1B_IOMUX */ enum { GPIO1B7_SHIFT = 14, - GPIO1B7_MASK = 1, + GPIO1B7_MASK = 1 << GPIO1B7_SHIFT, GPIO1B7_GPIO = 0, GPIO1B7_MMC0_CMD, GPIO1B3_SHIFT = 6, - GPIO1B3_MASK = 1, + GPIO1B3_MASK = 1 << GPIO1B3_SHIFT, GPIO1B3_GPIO = 0, GPIO1B3_HDMI_HPD, GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 1, + GPIO1B2_MASK = 1 << GPIO1B2_SHIFT, GPIO1B2_GPIO = 0, GPIO1B2_HDMI_SCL, GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 1, + GPIO1B1_MASK = 1 << GPIO1B1_SHIFT, GPIO1B1_GPIO = 0, GPIO1B1_HDMI_SDA, GPIO1B0_SHIFT = 0, - GPIO1B0_MASK = 1, + GPIO1B0_MASK = 1 << GPIO1B0_SHIFT, GPIO1B0_GPIO = 0, GPIO1B0_HDMI_CEC, }; @@ -258,36 +257,36 @@ enum { /* GRF_GPIO1C_IOMUX */ enum { GPIO1C5_SHIFT = 10, - GPIO1C5_MASK = 3, + GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, GPIO1C5_GPIO = 0, GPIO1C5_MMC0_D3, GPIO1C5_JTAG_TMS, GPIO1C4_SHIFT = 8, - GPIO1C4_MASK = 3, + GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, GPIO1C4_GPIO = 0, GPIO1C4_MMC0_D2, GPIO1C4_JTAG_TCK, GPIO1C3_SHIFT = 6, - GPIO1C3_MASK = 3, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, GPIO1C3_GPIO = 0, GPIO1C3_MMC0_D1, GPIO1C3_UART2_SOUT, GPIO1C2_SHIFT = 4, - GPIO1C2_MASK = 3, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT , GPIO1C2_GPIO = 0, GPIO1C2_MMC0_D0, GPIO1C2_UART2_SIN, GPIO1C1_SHIFT = 2, - GPIO1C1_MASK = 1, + GPIO1C1_MASK = 1 << GPIO1C1_SHIFT, GPIO1C1_GPIO = 0, GPIO1C1_MMC0_DETN, GPIO1C0_SHIFT = 0, - GPIO1C0_MASK = 1, + GPIO1C0_MASK = 1 << GPIO1C0_SHIFT, GPIO1C0_GPIO = 0, GPIO1C0_MMC0_CLKOUT, }; @@ -295,56 +294,56 @@ enum { /* GRF_GPIO1D_IOMUX */ enum { GPIO1D7_SHIFT = 14, - GPIO1D7_MASK = 3, + GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, GPIO1D7_GPIO = 0, GPIO1D7_NAND_D7, GPIO1D7_EMMC_D7, GPIO1D7_SPI_CSN1, GPIO1D6_SHIFT = 12, - GPIO1D6_MASK = 3, + GPIO1D6_MASK = 3 << GPIO1D6_SHIFT, GPIO1D6_GPIO = 0, GPIO1D6_NAND_D6, GPIO1D6_EMMC_D6, GPIO1D6_SPI_CSN0, GPIO1D5_SHIFT = 10, - GPIO1D5_MASK = 3, + GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, GPIO1D5_GPIO = 0, GPIO1D5_NAND_D5, GPIO1D5_EMMC_D5, GPIO1D5_SPI_TXD, GPIO1D4_SHIFT = 8, - GPIO1D4_MASK = 3, + GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, GPIO1D4_GPIO = 0, GPIO1D4_NAND_D4, GPIO1D4_EMMC_D4, GPIO1D4_SPI_RXD, GPIO1D3_SHIFT = 6, - GPIO1D3_MASK = 3, + GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, GPIO1D3_GPIO = 0, GPIO1D3_NAND_D3, GPIO1D3_EMMC_D3, GPIO1D3_SFC_SIO3, GPIO1D2_SHIFT = 4, - GPIO1D2_MASK = 3, + GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, GPIO1D2_GPIO = 0, GPIO1D2_NAND_D2, GPIO1D2_EMMC_D2, GPIO1D2_SFC_SIO2, GPIO1D1_SHIFT = 2, - GPIO1D1_MASK = 3, + GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, GPIO1D1_GPIO = 0, GPIO1D1_NAND_D1, GPIO1D1_EMMC_D1, GPIO1D1_SFC_SIO1, GPIO1D0_SHIFT = 0, - GPIO1D0_MASK = 3, + GPIO1D0_MASK = 3 << GPIO1D0_SHIFT, GPIO1D0_GPIO = 0, GPIO1D0_NAND_D0, GPIO1D0_EMMC_D0, @@ -354,42 +353,42 @@ enum { /* GRF_GPIO2A_IOMUX */ enum { GPIO2A7_SHIFT = 14, - GPIO2A7_MASK = 1, + GPIO2A7_MASK = 1 << GPIO2A7_SHIFT, GPIO2A7_GPIO = 0, GPIO2A7_TESTCLK_OUT, GPIO2A6_SHIFT = 12, - GPIO2A6_MASK = 1, + GPIO2A6_MASK = 1 << GPIO2A6_SHIFT, GPIO2A6_GPIO = 0, GPIO2A6_NAND_CS0, GPIO2A4_SHIFT = 8, - GPIO2A4_MASK = 3, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, GPIO2A4_GPIO = 0, GPIO2A4_NAND_RDY, GPIO2A4_EMMC_CMD, GPIO2A3_SFC_CLK, GPIO2A3_SHIFT = 6, - GPIO2A3_MASK = 3, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, GPIO2A3_GPIO = 0, GPIO2A3_NAND_RDN, GPIO2A4_SFC_CSN1, GPIO2A2_SHIFT = 4, - GPIO2A2_MASK = 3, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, GPIO2A2_GPIO = 0, GPIO2A2_NAND_WRN, GPIO2A4_SFC_CSN0, GPIO2A1_SHIFT = 2, - GPIO2A1_MASK = 3, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, GPIO2A1_GPIO = 0, GPIO2A1_NAND_CLE, GPIO2A1_EMMC_CLKOUT, GPIO2A0_SHIFT = 0, - GPIO2A0_MASK = 3, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, GPIO2A0_GPIO = 0, GPIO2A0_NAND_ALE, GPIO2A0_SPI_CLK, @@ -398,28 +397,28 @@ enum { /* GRF_GPIO2B_IOMUX */ enum { GPIO2B7_SHIFT = 14, - GPIO2B7_MASK = 1, + GPIO2B7_MASK = 1 << GPIO2B7_SHIFT, GPIO2B7_GPIO = 0, GPIO2B7_MAC_RXER, GPIO2B6_SHIFT = 12, - GPIO2B6_MASK = 3, + GPIO2B6_MASK = 3 << GPIO2B6_SHIFT, GPIO2B6_GPIO = 0, GPIO2B6_MAC_CLKOUT, GPIO2B6_MAC_CLKIN, GPIO2B5_SHIFT = 10, - GPIO2B5_MASK = 1, + GPIO2B5_MASK = 1 << GPIO2B5_SHIFT, GPIO2B5_GPIO = 0, GPIO2B5_MAC_TXEN, GPIO2B4_SHIFT = 8, - GPIO2B4_MASK = 1, + GPIO2B4_MASK = 1 << GPIO2B4_SHIFT, GPIO2B4_GPIO = 0, GPIO2B4_MAC_MDIO, GPIO2B2_SHIFT = 4, - GPIO2B2_MASK = 1, + GPIO2B2_MASK = 1 << GPIO2B2_SHIFT, GPIO2B2_GPIO = 0, GPIO2B2_MAC_CRS, }; @@ -427,43 +426,43 @@ enum { /* GRF_GPIO2C_IOMUX */ enum { GPIO2C7_SHIFT = 14, - GPIO2C7_MASK = 3, + GPIO2C7_MASK = 3 << GPIO2C7_SHIFT, GPIO2C7_GPIO = 0, GPIO2C7_UART1_SOUT, GPIO2C7_TESTCLK_OUT1, GPIO2C6_SHIFT = 12, - GPIO2C6_MASK = 1, + GPIO2C6_MASK = 1 << GPIO2C6_SHIFT, GPIO2C6_GPIO = 0, GPIO2C6_UART1_SIN, GPIO2C5_SHIFT = 10, - GPIO2C5_MASK = 1, + GPIO2C5_MASK = 1 << GPIO2C5_SHIFT, GPIO2C5_GPIO = 0, GPIO2C5_I2C2_SCL, GPIO2C4_SHIFT = 8, - GPIO2C4_MASK = 1, + GPIO2C4_MASK = 1 << GPIO2C4_SHIFT, GPIO2C4_GPIO = 0, GPIO2C4_I2C2_SDA, GPIO2C3_SHIFT = 6, - GPIO2C3_MASK = 1, + GPIO2C3_MASK = 1 << GPIO2C3_SHIFT, GPIO2C3_GPIO = 0, GPIO2C3_MAC_TXD0, GPIO2C2_SHIFT = 4, - GPIO2C2_MASK = 1, + GPIO2C2_MASK = 1 << GPIO2C2_SHIFT, GPIO2C2_GPIO = 0, GPIO2C2_MAC_TXD1, GPIO2C1_SHIFT = 2, - GPIO2C1_MASK = 1, + GPIO2C1_MASK = 1 << GPIO2C1_SHIFT, GPIO2C1_GPIO = 0, GPIO2C1_MAC_RXD0, GPIO2C0_SHIFT = 0, - GPIO2C0_MASK = 1, + GPIO2C0_MASK = 1 << GPIO2C0_SHIFT, GPIO2C0_GPIO = 0, GPIO2C0_MAC_RXD1, }; @@ -471,22 +470,22 @@ enum { /* GRF_GPIO2D_IOMUX */ enum { GPIO2D6_SHIFT = 12, - GPIO2D6_MASK = 1, + GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, GPIO2D6_GPIO = 0, GPIO2D6_I2S_SDO1, GPIO2D5_SHIFT = 10, - GPIO2D5_MASK = 1, + GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, GPIO2D5_GPIO = 0, GPIO2D5_I2S_SDO2, GPIO2D4_SHIFT = 8, - GPIO2D4_MASK = 1, + GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, GPIO2D4_GPIO = 0, GPIO2D4_I2S_SDO3, GPIO2D1_SHIFT = 2, - GPIO2D1_MASK = 1, + GPIO2D1_MASK = 1 << GPIO2D1_SHIFT, GPIO2D1_GPIO = 0, GPIO2D1_MAC_MDC, }; diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h index 7d56b8c..fbc4a0d 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h @@ -813,7 +813,7 @@ enum { (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), RK3288_TXCLK_DLY_ENA_GMAC_DISABLE = 0, RK3288_TXCLK_DLY_ENA_GMAC_ENABLE = - (1 << RK3288_RXCLK_DLY_ENA_GMAC_SHIFT), + (1 << RK3288_TXCLK_DLY_ENA_GMAC_SHIFT), RK3288_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7, RK3288_CLK_RX_DL_CFG_GMAC_MASK = diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h index 2776cef..f0a0781 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h @@ -131,4 +131,118 @@ struct rk3328_sgrf_regs { }; check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0); +enum { + /* GPIO0A_IOMUX */ + GPIO0A5_SEL_SHIFT = 10, + GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT, + GPIO0A5_I2C3_SCL = 2, + + GPIO0A6_SEL_SHIFT = 12, + GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT, + GPIO0A6_I2C3_SDA = 2, + + GPIO0A7_SEL_SHIFT = 14, + GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT, + GPIO0A7_EMMC_DATA0 = 2, + + /* GPIO0D_IOMUX*/ + GPIO0D6_SEL_SHIFT = 12, + GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT, + GPIO0D6_GPIO = 0, + GPIO0D6_SDMMC0_PWRENM1 = 3, + + /* GPIO1A_IOMUX */ + GPIO1A0_SEL_SHIFT = 0, + GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT, + GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555, + + /* GPIO2A_IOMUX */ + GPIO2A0_SEL_SHIFT = 0, + GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT, + GPIO2A0_UART2_TX_M1 = 1, + + GPIO2A1_SEL_SHIFT = 2, + GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT, + GPIO2A1_UART2_RX_M1 = 1, + + GPIO2A2_SEL_SHIFT = 4, + GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT, + GPIO2A2_PWM_IR = 1, + + GPIO2A4_SEL_SHIFT = 8, + GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT, + GPIO2A4_PWM_0 = 1, + GPIO2A4_I2C1_SDA, + + GPIO2A5_SEL_SHIFT = 10, + GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT, + GPIO2A5_PWM_1 = 1, + GPIO2A5_I2C1_SCL, + + GPIO2A6_SEL_SHIFT = 12, + GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT, + GPIO2A6_PWM_2 = 1, + + GPIO2A7_SEL_SHIFT = 14, + GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_SDMMC0_PWRENM0, + + /* GPIO2BL_IOMUX */ + GPIO2BL0_SEL_SHIFT = 0, + GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT, + GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15, + + GPIO2BL3_SEL_SHIFT = 6, + GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT, + GPIO2BL3_SPI_CSN0_M0 = 1, + + GPIO2BL4_SEL_SHIFT = 8, + GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT, + GPIO2BL4_SPI_CSN1_M0 = 1, + + GPIO2BL5_SEL_SHIFT = 10, + GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT, + GPIO2BL5_I2C2_SDA = 1, + + GPIO2BL6_SEL_SHIFT = 12, + GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT, + GPIO2BL6_I2C2_SCL = 1, + + /* GPIO2D_IOMUX */ + GPIO2D0_SEL_SHIFT = 0, + GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT, + GPIO2D0_I2C0_SCL = 1, + + GPIO2D1_SEL_SHIFT = 2, + GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT, + GPIO2D1_I2C0_SDA = 1, + + GPIO2D4_SEL_SHIFT = 8, + GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT, + GPIO2D4_EMMC_DATA1234 = 0xaa, + + /* GPIO3C_IOMUX */ + GPIO3C0_SEL_SHIFT = 0, + GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT, + GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa, + + /* COM_IOMUX */ + IOMUX_SEL_UART2_SHIFT = 0, + IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT, + IOMUX_SEL_UART2_M0 = 0, + IOMUX_SEL_UART2_M1, + + IOMUX_SEL_SPI_SHIFT = 4, + IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT, + IOMUX_SEL_SPI_M0 = 0, + IOMUX_SEL_SPI_M1, + IOMUX_SEL_SPI_M2, + + IOMUX_SEL_SDMMC_SHIFT = 7, + IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT, + IOMUX_SEL_SDMMC_M0 = 0, + IOMUX_SEL_SDMMC_M1, +}; + #endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */ diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h new file mode 100644 index 0000000..3233dc3 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h @@ -0,0 +1,440 @@ +/* (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_GRF_RK3368_H +#define _ASM_ARCH_GRF_RK3368_H + +#include <common.h> + +struct rk3368_grf { + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + u32 gpio2a_iomux; + u32 gpio2b_iomux; + u32 gpio2c_iomux; + u32 gpio2d_iomux; + u32 gpio3a_iomux; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + u32 gpio3d_iomux; + u32 reserved[0x34]; + u32 gpio1a_pull; + u32 gpio1b_pull; + u32 gpio1c_pull; + u32 gpio1d_pull; + u32 gpio2a_pull; + u32 gpio2b_pull; + u32 gpio2c_pull; + u32 gpio2d_pull; + u32 gpio3a_pull; + u32 gpio3b_pull; + u32 gpio3c_pull; + u32 gpio3d_pull; + u32 reserved1[0x34]; + u32 gpio1a_drv; + u32 gpio1b_drv; + u32 gpio1c_drv; + u32 gpio1d_drv; + u32 gpio2a_drv; + u32 gpio2b_drv; + u32 gpio2c_drv; + u32 gpio2d_drv; + u32 gpio3a_drv; + u32 gpio3b_drv; + u32 gpio3c_drv; + u32 gpio3d_drv; + u32 reserved2[0x34]; + u32 gpio1l_sr; + u32 gpio1h_sr; + u32 gpio2l_sr; + u32 gpio2h_sr; + u32 gpio3l_sr; + u32 gpio3h_sr; + u32 reserved3[0x1a]; + u32 gpio_smt; + u32 reserved4[0x1f]; + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 soc_con6; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 soc_con12; + u32 soc_con13; + u32 soc_con14; + u32 soc_con15; + u32 soc_con16; + u32 soc_con17; +}; +check_member(rk3368_grf, soc_con17, 0x444); + +struct rk3368_pmu_grf { + u32 gpio0a_iomux; + u32 gpio0b_iomux; + u32 gpio0c_iomux; + u32 gpio0d_iomux; + u32 gpio0a_pull; + u32 gpio0b_pull; + u32 gpio0c_pull; + u32 gpio0d_pull; + u32 gpio0a_drv; + u32 gpio0b_drv; + u32 gpio0c_drv; + u32 gpio0d_drv; + u32 gpio0l_sr; + u32 gpio0h_sr; +}; +check_member(rk3368_pmu_grf, gpio0h_sr, 0x34); + +/*GRF_GPIO0C_IOMUX*/ +enum { + GPIO0C7_SHIFT = 14, + GPIO0C7_MASK = 3 << GPIO0C7_SHIFT, + GPIO0C7_GPIO = 0, + GPIO0C7_LCDC_D19, + GPIO0C7_TRACE_D9, + GPIO0C7_UART1_RTSN, + + GPIO0C6_SHIFT = 12, + GPIO0C6_MASK = 3 << GPIO0C6_SHIFT, + GPIO0C6_GPIO = 0, + GPIO0C6_LCDC_D18, + GPIO0C6_TRACE_D8, + GPIO0C6_UART1_CTSN, + + GPIO0C5_SHIFT = 10, + GPIO0C5_MASK = 3 << GPIO0C5_SHIFT, + GPIO0C5_GPIO = 0, + GPIO0C5_LCDC_D17, + GPIO0C5_TRACE_D7, + GPIO0C5_UART1_SOUT, + + GPIO0C4_SHIFT = 8, + GPIO0C4_MASK = 3 << GPIO0C4_SHIFT, + GPIO0C4_GPIO = 0, + GPIO0C4_LCDC_D16, + GPIO0C4_TRACE_D6, + GPIO0C4_UART1_SIN, + + GPIO0C3_SHIFT = 6, + GPIO0C3_MASK = 3 << GPIO0C3_SHIFT, + GPIO0C3_GPIO = 0, + GPIO0C3_LCDC_D15, + GPIO0C3_TRACE_D5, + GPIO0C3_MCU_JTAG_TDO, + + GPIO0C2_SHIFT = 4, + GPIO0C2_MASK = 3 << GPIO0C2_SHIFT, + GPIO0C2_GPIO = 0, + GPIO0C2_LCDC_D14, + GPIO0C2_TRACE_D4, + GPIO0C2_MCU_JTAG_TDI, + + GPIO0C1_SHIFT = 2, + GPIO0C1_MASK = 3 << GPIO0C1_SHIFT, + GPIO0C1_GPIO = 0, + GPIO0C1_LCDC_D13, + GPIO0C1_TRACE_D3, + GPIO0C1_MCU_JTAG_TRTSN, + + GPIO0C0_SHIFT = 0, + GPIO0C0_MASK = 3 << GPIO0C0_SHIFT, + GPIO0C0_GPIO = 0, + GPIO0C0_LCDC_D12, + GPIO0C0_TRACE_D2, + GPIO0C0_MCU_JTAG_TDO, +}; + +/*GRF_GPIO0D_IOMUX*/ +enum { + GPIO0D7_SHIFT = 14, + GPIO0D7_MASK = 3 << GPIO0D7_SHIFT, + GPIO0D7_GPIO = 0, + GPIO0D7_LCDC_DCLK, + GPIO0D7_TRACE_CTL, + GPIO0D7_PMU_DEBUG5, + + GPIO0D6_SHIFT = 12, + GPIO0D6_MASK = 3 << GPIO0D6_SHIFT, + GPIO0D6_GPIO = 0, + GPIO0D6_LCDC_DEN, + GPIO0D6_TRACE_CLK, + GPIO0D6_PMU_DEBUG4, + + GPIO0D5_SHIFT = 10, + GPIO0D5_MASK = 3 << GPIO0D5_SHIFT, + GPIO0D5_GPIO = 0, + GPIO0D5_LCDC_VSYNC, + GPIO0D5_TRACE_D15, + GPIO0D5_PMU_DEBUG3, + + GPIO0D4_SHIFT = 8, + GPIO0D4_MASK = 3 << GPIO0D4_SHIFT, + GPIO0D4_GPIO = 0, + GPIO0D4_LCDC_HSYNC, + GPIO0D4_TRACE_D14, + GPIO0D4_PMU_DEBUG2, + + GPIO0D3_SHIFT = 6, + GPIO0D3_MASK = 3 << GPIO0D3_SHIFT, + GPIO0D3_GPIO = 0, + GPIO0D3_LCDC_D23, + GPIO0D3_TRACE_D13, + GPIO0D3_UART4_SIN, + + GPIO0D2_SHIFT = 4, + GPIO0D2_MASK = 3 << GPIO0D2_SHIFT, + GPIO0D2_GPIO = 0, + GPIO0D2_LCDC_D22, + GPIO0D2_TRACE_D12, + GPIO0D2_UART4_SOUT, + + GPIO0D1_SHIFT = 2, + GPIO0D1_MASK = 3 << GPIO0D1_SHIFT, + GPIO0D1_GPIO = 0, + GPIO0D1_LCDC_D21, + GPIO0D1_TRACE_D11, + GPIO0D1_UART4_RTSN, + + GPIO0D0_SHIFT = 0, + GPIO0D0_MASK = 3 << GPIO0D0_SHIFT, + GPIO0D0_GPIO = 0, + GPIO0D0_LCDC_D20, + GPIO0D0_TRACE_D10, + GPIO0D0_UART4_CTSN, +}; + +/*GRF_GPIO2A_IOMUX*/ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_SDMMC0_D2, + GPIO2A7_JTAG_TCK, + + GPIO2A6_SHIFT = 12, + GPIO2A6_MASK = 3 << GPIO2A6_SHIFT, + GPIO2A6_GPIO = 0, + GPIO2A6_SDMMC0_D1, + GPIO2A6_UART2_SIN, + + GPIO2A5_SHIFT = 10, + GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, + GPIO2A5_GPIO = 0, + GPIO2A5_SDMMC0_D0, + GPIO2A5_UART2_SOUT, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, + GPIO2A4_GPIO = 0, + GPIO2A4_FLASH_DQS, + GPIO2A4_EMMC_CLKO, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, + GPIO2A3_GPIO = 0, + GPIO2A3_FLASH_CSN3, + GPIO2A3_EMMC_RSTNO, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, + GPIO2A2_GPIO = 0, + GPIO2A2_FLASH_CSN2, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, + GPIO2A1_GPIO = 0, + GPIO2A1_FLASH_CSN1, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, + GPIO2A0_GPIO = 0, + GPIO2A0_FLASH_CSN0, +}; + +/*GRF_GPIO2D_IOMUX*/ +enum { + GPIO2D7_SHIFT = 14, + GPIO2D7_MASK = 3 << GPIO2D7_SHIFT, + GPIO2D7_GPIO = 0, + GPIO2D7_SDIO0_D3, + + GPIO2D6_SHIFT = 12, + GPIO2D6_MASK = 3 << GPIO2D6_SHIFT, + GPIO2D6_GPIO = 0, + GPIO2D6_SDIO0_D2, + + GPIO2D5_SHIFT = 10, + GPIO2D5_MASK = 3 << GPIO2D5_SHIFT, + GPIO2D5_GPIO = 0, + GPIO2D5_SDIO0_D1, + + GPIO2D4_SHIFT = 8, + GPIO2D4_MASK = 3 << GPIO2D4_SHIFT, + GPIO2D4_GPIO = 0, + GPIO2D4_SDIO0_D0, + + GPIO2D3_SHIFT = 6, + GPIO2D3_MASK = 3 << GPIO2D3_SHIFT, + GPIO2D3_GPIO = 0, + GPIO2D3_UART0_RTS0, + + GPIO2D2_SHIFT = 4, + GPIO2D2_MASK = 3 << GPIO2D2_SHIFT, + GPIO2D2_GPIO = 0, + GPIO2D2_UART0_CTS0, + + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, + GPIO2D1_GPIO = 0, + GPIO2D1_UART0_SOUT, + + GPIO2D0_SHIFT = 0, + GPIO2D0_MASK = 3 << GPIO2D0_SHIFT, + GPIO2D0_GPIO = 0, + GPIO2D0_UART0_SIN, +}; + +/*GRF_GPIO3C_IOMUX*/ +enum { + GPIO3C7_SHIFT = 14, + GPIO3C7_MASK = 3 << GPIO3C7_SHIFT, + GPIO3C7_GPIO = 0, + GPIO3C7_EDPHDMI_CECINOUT, + GPIO3C7_ISP_FLASHTRIGIN, + + GPIO3C6_SHIFT = 12, + GPIO3C6_MASK = 3 << GPIO3C6_SHIFT, + GPIO3C6_GPIO = 0, + GPIO3C6_MAC_CLK, + GPIO3C6_ISP_SHUTTERTRIG, + + GPIO3C5_SHIFT = 10, + GPIO3C5_MASK = 3 << GPIO3C5_SHIFT, + GPIO3C5_GPIO = 0, + GPIO3C5_MAC_RXER, + GPIO3C5_ISP_PRELIGHTTRIG, + + GPIO3C4_SHIFT = 8, + GPIO3C4_MASK = 3 << GPIO3C4_SHIFT, + GPIO3C4_GPIO = 0, + GPIO3C4_MAC_RXDV, + GPIO3C4_ISP_FLASHTRIGOUT, + + GPIO3C3_SHIFT = 6, + GPIO3C3_MASK = 3 << GPIO3C3_SHIFT, + GPIO3C3_GPIO = 0, + GPIO3C3_MAC_RXDV, + GPIO3C3_EMMC_RSTNO, + + GPIO3C2_SHIFT = 4, + GPIO3C2_MASK = 3 << GPIO3C2_SHIFT, + GPIO3C2_MAC_MDC = 0, + GPIO3C2_ISP_SHUTTEREN, + + GPIO3C1_SHIFT = 2, + GPIO3C1_MASK = 3 << GPIO3C1_SHIFT, + GPIO3C1_GPIO = 0, + GPIO3C1_MAC_RXD2, + GPIO3C1_UART3_RTSN, + + GPIO3C0_SHIFT = 0, + GPIO3C0_MASK = 3 << GPIO3C0_SHIFT, + GPIO3C0_GPIO = 0, + GPIO3C0_MAC_RXD1, + GPIO3C0_UART3_CTSN, + GPIO3C0_GPS_RFCLK, +}; + +/*GRF_GPIO3D_IOMUX*/ +enum { + GPIO3D7_SHIFT = 14, + GPIO3D7_MASK = 3 << GPIO3D7_SHIFT, + GPIO3D7_GPIO = 0, + GPIO3D7_SC_VCC18V, + GPIO3D7_I2C2_SDA, + GPIO3D7_GPUJTAG_TCK, + + GPIO3D6_SHIFT = 12, + GPIO3D6_MASK = 3 << GPIO3D6_SHIFT, + GPIO3D6_GPIO = 0, + GPIO3D6_IR_TX, + GPIO3D6_UART3_SOUT, + GPIO3D6_PWM3, + + GPIO3D5_SHIFT = 10, + GPIO3D5_MASK = 3 << GPIO3D5_SHIFT, + GPIO3D5_GPIO = 0, + GPIO3D5_IR_RX, + GPIO3D5_UART3_SIN, + + GPIO3D4_SHIFT = 8, + GPIO3D4_MASK = 3 << GPIO3D4_SHIFT, + GPIO3D4_GPIO = 0, + GPIO3D4_MAC_TXCLKOUT, + GPIO3D4_SPI1_CSN1, + + GPIO3D3_SHIFT = 6, + GPIO3D3_MASK = 3 << GPIO3D3_SHIFT, + GPIO3D3_GPIO = 0, + GPIO3D3_HDMII2C_SCL, + GPIO3D3_I2C5_SCL, + + GPIO3D2_SHIFT = 4, + GPIO3D2_MASK = 3 << GPIO3D2_SHIFT, + GPIO3D2_GPIO = 0, + GPIO3D2_HDMII2C_SDA, + GPIO3D2_I2C5_SDA, + + GPIO3D1_SHIFT = 2, + GPIO3D1_MASK = 3 << GPIO3D1_SHIFT, + GPIO3D1_GPIO = 0, + GPIO3D1_MAC_RXCLKIN, + GPIO3D1_I2C4_SCL, + + GPIO3D0_SHIFT = 0, + GPIO3D0_MASK = 3 << GPIO3D0_SHIFT, + GPIO3D0_GPIO = 0, + GPIO3D0_MAC_MDIO, + GPIO3D0_I2C4_SDA, +}; + +/*GRF_SOC_CON11/12/13*/ +enum { + MCU_SRAM_BASE_BIT27_BIT12_SHIFT = 0, + MCU_SRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), +}; + +/*GRF_SOC_CON12*/ +enum { + MCU_EXSRAM_BASE_BIT27_BIT12_SHIFT = 0, + MCU_EXSRAM_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), +}; + +/*GRF_SOC_CON13*/ +enum { + MCU_EXPERI_BASE_BIT27_BIT12_SHIFT = 0, + MCU_EXPERI_BASE_BIT27_BIT12_MASK = GENMASK(15, 0), +}; + +/*GRF_SOC_CON14*/ +enum { + MCU_EXPERI_BASE_BIT31_BIT28_SHIFT = 12, + MCU_EXPERI_BASE_BIT31_BIT28_MASK = GENMASK(15, 12), + MCU_EXSRAM_BASE_BIT31_BIT28_SHIFT = 8, + MCU_EXSRAM_BASE_BIT31_BIT28_MASK = GENMASK(11, 8), + MCU_SRAM_BASE_BIT31_BIT28_SHIFT = 4, + MCU_SRAM_BASE_BIT31_BIT28_MASK = GENMASK(7, 4), + MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0, + MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0), +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h index eda9956..8d21eb7 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3399.h @@ -534,6 +534,9 @@ enum { GRF_DSI0_VOP_SEL_MASK = 1 << GRF_DSI0_VOP_SEL_SHIFT, GRF_DSI0_VOP_SEL_B = 0, GRF_DSI0_VOP_SEL_L = 1, + GRF_RK3399_HDMI_VOP_SEL_MASK = 1 << 6, + GRF_RK3399_HDMI_VOP_SEL_B = 0 << 6, + GRF_RK3399_HDMI_VOP_SEL_L = 1 << 6, /* GRF_SOC_CON22 */ GRF_DPHY_TX0_RXMODE_SHIFT = 0, diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h new file mode 100644 index 0000000..c816a5b --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h @@ -0,0 +1,509 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_GRF_RV1108_H +#define _ASM_ARCH_GRF_RV1108_H + +#include <common.h> + +struct rv1108_grf { + u32 reserved[4]; + u32 gpio1a_iomux; + u32 gpio1b_iomux; + u32 gpio1c_iomux; + u32 gpio1d_iomux; + u32 gpio2a_iomux; + u32 gpio2b_iomux; + u32 gpio2c_iomux; + u32 gpio2d_iomux; + u32 gpio3a_iomux; + u32 gpio3b_iomux; + u32 gpio3c_iomux; + u32 gpio3d_iomux; + u32 reserved1[52]; + u32 gpio1a_pull; + u32 gpio1b_pull; + u32 gpio1c_pull; + u32 gpio1d_pull; + u32 gpio2a_pull; + u32 gpio2b_pull; + u32 gpio2c_pull; + u32 gpio2d_pull; + u32 gpio3a_pull; + u32 gpio3b_pull; + u32 gpio3c_pull; + u32 gpio3d_pull; + u32 reserved2[52]; + u32 gpio1a_drv; + u32 gpio1b_drv; + u32 gpio1c_drv; + u32 gpio1d_drv; + u32 gpio2a_drv; + u32 gpio2b_drv; + u32 gpio2c_drv; + u32 gpio2d_drv; + u32 gpio3a_drv; + u32 gpio3b_drv; + u32 gpio3c_drv; + u32 gpio3d_drv; + u32 reserved3[50]; + u32 gpio1l_sr; + u32 gpio1h_sr; + u32 gpio2l_sr; + u32 gpio2h_sr; + u32 gpio3l_sr; + u32 gpio3h_sr; + u32 reserved4[26]; + u32 gpio1l_smt; + u32 gpio1h_smt; + u32 gpio2l_smt; + u32 gpio2h_smt; + u32 gpio3l_smt; + u32 gpio3h_smt; + u32 reserved5[24]; + u32 soc_con0; + u32 soc_con1; + u32 soc_con2; + u32 soc_con3; + u32 soc_con4; + u32 soc_con5; + u32 soc_con6; + u32 soc_con7; + u32 soc_con8; + u32 soc_con9; + u32 soc_con10; + u32 soc_con11; + u32 reserved6[20]; + u32 soc_status0; + u32 soc_status1; + u32 reserved7[30]; + u32 cpu_con0; + u32 cpu_con1; + u32 reserved8[30]; + u32 os_reg0; + u32 os_reg1; + u32 os_reg2; + u32 os_reg3; + u32 reserved9[29]; + u32 ddr_status; + u32 reserved10[30]; + u32 sig_det_con; + u32 reserved11[3]; + u32 sig_det_status; + u32 reserved12[3]; + u32 sig_det_clr; + u32 reserved13[23]; + u32 host_con0; + u32 host_con1; + u32 reserved14[2]; + u32 dma_con0; + u32 dma_con1; + u32 reserved15[539]; + u32 uoc_status; + u32 host_status; + u32 gmac_con0; + u32 chip_id; +}; +check_member(rv1108_grf, chip_id, 0xf90); + +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 3 << GPIO1B7_SHIFT, + GPIO1B7_GPIO = 0, + GPIO1B7_LCDC_D12, + GPIO1B7_I2S_SDIO2_M0, + GPIO1B7_GMAC_RXDV, + + GPIO1B6_SHIFT = 12, + GPIO1B6_MASK = 3 << GPIO1B6_SHIFT, + GPIO1B6_GPIO = 0, + GPIO1B6_LCDC_D13, + GPIO1B6_I2S_LRCLKTX_M0, + GPIO1B6_GMAC_RXD1, + + GPIO1B5_SHIFT = 10, + GPIO1B5_MASK = 3 << GPIO1B5_SHIFT, + GPIO1B5_GPIO = 0, + GPIO1B5_LCDC_D14, + GPIO1B5_I2S_SDIO1_M0, + GPIO1B5_GMAC_RXD0, + + GPIO1B4_SHIFT = 8, + GPIO1B4_MASK = 3 << GPIO1B4_SHIFT, + GPIO1B4_GPIO = 0, + GPIO1B4_LCDC_D15, + GPIO1B4_I2S_MCLK_M0, + GPIO1B4_GMAC_TXEN, + + GPIO1B3_SHIFT = 6, + GPIO1B3_MASK = 3 << GPIO1B3_SHIFT, + GPIO1B3_GPIO = 0, + GPIO1B3_LCDC_D16, + GPIO1B3_I2S_SCLK_M0, + GPIO1B3_GMAC_TXD1, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, + GPIO1B2_GPIO = 0, + GPIO1B2_LCDC_D17, + GPIO1B2_I2S_SDIO_M0, + GPIO1B2_GMAC_TXD0, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, + GPIO1B1_GPIO = 0, + GPIO1B1_LCDC_D9, + GPIO1B1_PWM7, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 3, + GPIO1B0_GPIO = 0, + GPIO1B0_LCDC_D8, + GPIO1B0_PWM6, +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C7_SHIFT = 14, + GPIO1C7_MASK = 3 << GPIO1C7_SHIFT, + GPIO1C7_GPIO = 0, + GPIO1C7_CIF_D5, + GPIO1C7_I2S_SDIO2_M1, + + GPIO1C6_SHIFT = 12, + GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, + GPIO1C6_GPIO = 0, + GPIO1C6_CIF_D4, + GPIO1C6_I2S_LRCLKTX_M1, + + GPIO1C5_SHIFT = 10, + GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, + GPIO1C5_GPIO = 0, + GPIO1C5_LCDC_CLK, + GPIO1C5_GMAC_CLK, + + GPIO1C4_SHIFT = 8, + GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, + GPIO1C4_GPIO = 0, + GPIO1C4_LCDC_HSYNC, + GPIO1C4_GMAC_MDC, + + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, + GPIO1C3_GPIO = 0, + GPIO1C3_LCDC_VSYNC, + GPIO1C3_GMAC_MDIO, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT, + GPIO1C2_GPIO = 0, + GPIO1C2_LCDC_EN, + GPIO1C2_I2S_SDIO3_M0, + GPIO1C2_GMAC_RXER, + + GPIO1C1_SHIFT = 2, + GPIO1C1_MASK = 3 << GPIO1C1_SHIFT, + GPIO1C1_GPIO = 0, + GPIO1C1_LCDC_D10, + GPIO1C1_I2S_SDI_M0, + GPIO1C1_PWM4, + + GPIO1C0_SHIFT = 0, + GPIO1C0_MASK = 3, + GPIO1C0_GPIO = 0, + GPIO1C0_LCDC_D11, + GPIO1C0_I2S_LRCLKRX_M0, +}; + +/* GRF_GPIO1D_OIMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, + GPIO1D7_GPIO = 0, + GPIO1D7_HDMI_CEC, + GPIO1D7_DSP_RTCK, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 1 << GPIO1D6_SHIFT, + GPIO1D6_GPIO = 0, + GPIO1D6_HDMI_HPD_M0, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, + GPIO1D5_GPIO = 0, + GPIO1D5_UART2_RTSN, + GPIO1D5_HDMI_SDA_M0, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, + GPIO1D4_GPIO = 0, + GPIO1D4_UART2_CTSN, + GPIO1D4_HDMI_SCL_M0, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, + GPIO1D3_GPIO = 0, + GPIO1D3_UART0_SOUT, + GPIO1D3_SPI_TXD_M0, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, + GPIO1D2_GPIO = 0, + GPIO1D2_UART0_SIN, + GPIO1D2_SPI_RXD_M0, + GPIO1D2_DSP_TDI, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, + GPIO1D1_GPIO = 0, + GPIO1D1_UART0_RTSN, + GPIO1D1_SPI_CSN0_M0, + GPIO1D1_DSP_TMS, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 3, + GPIO1D0_GPIO = 0, + GPIO1D0_UART0_CTSN, + GPIO1D0_SPI_CLK_M0, + GPIO1D0_DSP_TCK, +}; + +/* GRF_GPIO2A_IOMUX */ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_FLASH_D7, + GPIO2A7_EMMC_D7, + + GPIO2A6_SHIFT = 12, + GPIO2A6_MASK = 3 << GPIO2A6_SHIFT, + GPIO2A6_GPIO = 0, + GPIO2A6_FLASH_D6, + GPIO2A6_EMMC_D6, + + GPIO2A5_SHIFT = 10, + GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, + GPIO2A5_GPIO = 0, + GPIO2A5_FLASH_D5, + GPIO2A5_EMMC_D5, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, + GPIO2A4_GPIO = 0, + GPIO2A4_FLASH_D4, + GPIO2A4_EMMC_D4, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, + GPIO2A3_GPIO = 0, + GPIO2A3_FLASH_D3, + GPIO2A3_EMMC_D3, + GPIO2A3_SFC_HOLD_IO3, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, + GPIO2A2_GPIO = 0, + GPIO2A2_FLASH_D2, + GPIO2A2_EMMC_D2, + GPIO2A2_SFC_WP_IO2, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, + GPIO2A1_GPIO = 0, + GPIO2A1_FLASH_D1, + GPIO2A1_EMMC_D1, + GPIO2A1_SFC_SO_IO1, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, + GPIO2A0_GPIO = 0, + GPIO2A0_FLASH_D0, + GPIO2A0_EMMC_D0, + GPIO2A0_SFC_SI_IO0, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2B7_SHIFT = 14, + GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, + GPIO2B7_GPIO = 0, + GPIO2B7_FLASH_CS1, + GPIO2B7_SFC_CLK, + + GPIO2B6_SHIFT = 12, + GPIO2B6_MASK = 1 << GPIO2B6_SHIFT, + GPIO2B6_GPIO = 0, + GPIO2B6_EMMC_CLKO, + + GPIO2B5_SHIFT = 10, + GPIO2B5_MASK = 1 << GPIO2B5_SHIFT, + GPIO2B5_GPIO = 0, + GPIO2B5_FLASH_CS0, + + GPIO2B4_SHIFT = 8, + GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, + GPIO2B4_GPIO = 0, + GPIO2B4_FLASH_RDY, + GPIO2B4_EMMC_CMD, + GPIO2B4_SFC_CSN0, + + GPIO2B3_SHIFT = 6, + GPIO2B3_MASK = 1 << GPIO2B3_SHIFT, + GPIO2B3_GPIO = 0, + GPIO2B3_FLASH_RDN, + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = 1 << GPIO2B2_SHIFT, + GPIO2B2_GPIO = 0, + GPIO2B2_FLASH_WRN, + + GPIO2B1_SHIFT = 2, + GPIO2B1_MASK = 1 << GPIO2B1_SHIFT, + GPIO2B1_GPIO = 0, + GPIO2B1_FLASH_CLE, + + GPIO2B0_SHIFT = 0, + GPIO2B0_MASK = 1 << GPIO2B0_SHIFT, + GPIO2B0_GPIO = 0, + GPIO2B0_FLASH_ALE, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D7_SHIFT = 14, + GPIO2D7_MASK = 1 << GPIO2D7_SHIFT, + GPIO2D7_GPIO = 0, + GPIO2D7_SDIO_D0, + + GPIO2D6_SHIFT = 12, + GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, + GPIO2D6_GPIO = 0, + GPIO2D6_SDIO_CMD, + + GPIO2D5_SHIFT = 10, + GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, + GPIO2D5_GPIO = 0, + GPIO2D5_SDIO_CLKO, + + GPIO2D4_SHIFT = 8, + GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, + GPIO2D4_GPIO = 0, + GPIO2D4_I2C1_SCL, + + GPIO2D3_SHIFT = 6, + GPIO2D3_MASK = 1 << GPIO2D3_SHIFT, + GPIO2D3_GPIO = 0, + GPIO2D3_I2C1_SDA, + + GPIO2D2_SHIFT = 4, + GPIO2D2_MASK = 3 << GPIO2D2_SHIFT, + GPIO2D2_GPIO = 0, + GPIO2D2_UART2_SOUT_M0, + GPIO2D2_JTAG_TCK, + + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, + GPIO2D1_GPIO = 0, + GPIO2D1_UART2_SIN_M0, + GPIO2D1_JTAG_TMS, + GPIO2D1_DSP_TMS, + + GPIO2D0_SHIFT = 0, + GPIO2D0_MASK = 3, + GPIO2D0_GPIO = 0, + GPIO2D0_UART0_CTSN, + GPIO2D0_SPI_CLK_M0, + GPIO2D0_DSP_TCK, +}; + +/* GRF_GPIO3A_IOMUX */ +enum { + GPIO3A7_SHIFT = 14, + GPIO3A7_MASK = 1 << GPIO3A7_SHIFT, + GPIO3A7_GPIO = 0, + + GPIO3A6_SHIFT = 12, + GPIO3A6_MASK = 1 << GPIO3A6_SHIFT, + GPIO3A6_GPIO = 0, + GPIO3A6_UART1_SOUT, + + GPIO3A5_SHIFT = 10, + GPIO3A5_MASK = 1 << GPIO3A5_SHIFT, + GPIO3A5_GPIO = 0, + GPIO3A5_UART1_SIN, + + GPIO3A4_SHIFT = 8, + GPIO3A4_MASK = 1 << GPIO3A4_SHIFT, + GPIO3A4_GPIO = 0, + GPIO3A4_UART1_CTSN, + + GPIO3A3_SHIFT = 6, + GPIO3A3_MASK = 1 << GPIO3A3_SHIFT, + GPIO3A3_GPIO = 0, + GPIO3A3_UART1_RTSN, + + GPIO3A2_SHIFT = 4, + GPIO3A2_MASK = 1 << GPIO3A2_SHIFT, + GPIO3A2_GPIO = 0, + GPIO3A2_SDIO_D3, + + GPIO3A1_SHIFT = 2, + GPIO3A1_MASK = 1 << GPIO3A1_SHIFT, + GPIO3A1_GPIO = 0, + GPIO3A1_SDIO_D2, + + GPIO3A0_SHIFT = 0, + GPIO3A0_MASK = 1, + GPIO3A0_GPIO = 0, + GPIO3A0_SDIO_D1, +}; + +/* GRF_GPIO3C_IOMUX */ +enum { + GPIO3C7_SHIFT = 14, + GPIO3C7_MASK = 1 << GPIO3C7_SHIFT, + GPIO3C7_GPIO = 0, + GPIO3C7_CIF_CLKI, + + GPIO3C6_SHIFT = 12, + GPIO3C6_MASK = 1 << GPIO3C6_SHIFT, + GPIO3C6_GPIO = 0, + GPIO3C6_CIF_VSYNC, + + GPIO3C5_SHIFT = 10, + GPIO3C5_MASK = 1 << GPIO3C5_SHIFT, + GPIO3C5_GPIO = 0, + GPIO3C5_SDMMC_CMD, + + GPIO3C4_SHIFT = 8, + GPIO3C4_MASK = 1 << GPIO3C4_SHIFT, + GPIO3C4_GPIO = 0, + GPIO3C4_SDMMC_CLKO, + + GPIO3C3_SHIFT = 6, + GPIO3C3_MASK = 3 << GPIO3C3_SHIFT, + GPIO3C3_GPIO = 0, + GPIO3C3_SDMMC_D0, + GPIO3C3_UART2_SOUT_M1, + + GPIO3C2_SHIFT = 4, + GPIO3C2_MASK = 3 << GPIO3C2_SHIFT, + GPIO3C2_GPIO = 0, + GPIO3C2_SDMMC_D1, + GPIO3C2_UART2_SIN_M1, + + GPIOC1_SHIFT = 2, + GPIOC1_MASK = 1 << GPIOC1_SHIFT, + GPIOC1_GPIO = 0, + GPIOC1_SDMMC_D2, + + GPIOC0_SHIFT = 0, + GPIOC0_MASK = 1, + GPIO3C0_GPIO = 0, + GPIO3C0_SDMMC_D3, +}; +#endif diff --git a/arch/arm/include/asm/arch-rockchip/periph.h b/arch/arm/include/asm/arch-rockchip/periph.h index 8018d47..9f4bc2e 100644 --- a/arch/arm/include/asm/arch-rockchip/periph.h +++ b/arch/arm/include/asm/arch-rockchip/periph.h @@ -42,6 +42,7 @@ enum periph_id { PERIPH_ID_SDMMC2, PERIPH_ID_HDMI, PERIPH_ID_GMAC, + PERIPH_ID_SFC, PERIPH_ID_COUNT, diff --git a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h index d5599ec..21e59be 100644 --- a/arch/arm/include/asm/arch-rockchip/vop_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/vop_rk3288.h @@ -197,9 +197,20 @@ enum vop_modes { #define V_DSP_DEN_POL(x) (((x) & 1) << 6) #define V_DSP_VSYNC_POL(x) (((x) & 1) << 5) #define V_DSP_HSYNC_POL(x) (((x) & 1) << 4) +#define V_DSP_PIN_POL(x) (((x) & 0xf) << 4) #define V_DSP_OUT_MODE(x) ((x) & 0xf) /* VOP_DSP_CTRL1 */ +#define V_RK3399_DSP_MIPI_POL(x) ((x) << 28) +#define V_RK3399_DSP_EDP_POL(x) ((x) << 24) +#define V_RK3399_DSP_HDMI_POL(x) ((x) << 20) +#define V_RK3399_DSP_LVDS_POL(x) ((x) << 16) + +#define M_RK3399_DSP_MIPI_POL (V_RK3399_DSP_MIPI_POL(0xf)) +#define M_RK3399_DSP_EDP_POL (V_RK3399_DSP_EDP_POL(0xf)) +#define M_RK3399_DSP_HDMI_POL (V_RK3399_DSP_HDMI_POL(0xf)) +#define M_RK3399_DSP_LVDS_POL (V_RK3399_DSP_LVDS_POL(0xf)) + #define M_DSP_LAYER3_SEL (3 << 14) #define M_DSP_LAYER2_SEL (3 << 12) #define M_DSP_LAYER1_SEL (3 << 10) diff --git a/arch/arm/include/asm/arch-s3c24x0/gpio.h b/arch/arm/include/asm/arch-s3c24x0/gpio.h deleted file mode 100644 index a749b64..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/gpio.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2012. - * - * Gabriel Huau <contact@huau-gabriel.fr> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _S3C24X0_GPIO_H_ -#define _S3C24X0_GPIO_H_ - -enum s3c2440_gpio { - GPA0, - GPA1, - GPA2, - GPA3, - GPA4, - GPA5, - GPA6, - GPA7, - GPA8, - GPA9, - GPA10, - GPA11, - GPA12, - GPA13, - GPA14, - GPA15, - GPA16, - GPA17, - GPA18, - GPA19, - GPA20, - GPA21, - GPA22, - GPA23, - GPA24, - - GPB0 = 32, - GPB1, - GPB2, - GPB3, - GPB4, - GPB5, - GPB6, - GPB7, - GPB8, - GPB9, - GPB10, - - GPC0 = 64, - GPC1, - GPC2, - GPC3, - GPC4, - GPC5, - GPC6, - GPC7, - GPC8, - GPC9, - GPC10, - GPC11, - GPC12, - GPC13, - GPC14, - GPC15, - - GPD0 = 96, - GPD1, - GPD2, - GPD3, - GPD4, - GPD5, - GPD6, - GPD7, - GPD8, - GPD9, - GPD10, - GPD11, - GPD12, - GPD13, - GPD14, - GPD15, - - GPE0 = 128, - GPE1, - GPE2, - GPE3, - GPE4, - GPE5, - GPE6, - GPE7, - GPE8, - GPE9, - GPE10, - GPE11, - GPE12, - GPE13, - GPE14, - GPE15, - - GPF0 = 160, - GPF1, - GPF2, - GPF3, - GPF4, - GPF5, - GPF6, - GPF7, - - GPG0 = 192, - GPG1, - GPG2, - GPG3, - GPG4, - GPG5, - GPG6, - GPG7, - GPG8, - GPG9, - GPG10, - GPG11, - GPG12, - GPG13, - GPG14, - GPG15, - - GPH0 = 224, - GPH1, - GPH2, - GPH3, - GPH4, - GPH5, - GPH6, - GPH7, - GPH8, - GPH9, - GPH10, - - GPJ0 = 256, - GPJ1, - GPJ2, - GPJ3, - GPJ4, - GPJ5, - GPJ6, - GPJ7, - GPJ8, - GPJ9, - GPJ10, - GPJ11, - GPJ12, -}; - -#endif diff --git a/arch/arm/include/asm/arch-s3c24x0/iomux.h b/arch/arm/include/asm/arch-s3c24x0/iomux.h deleted file mode 100644 index 9811644..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/iomux.h +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (c) 2012 - * - * Gabriel Huau <contact@huau-gabriel.fr> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _S3C24X0_IOMUX_H_ -#define _S3C24X0_IOMUX_H_ - -enum s3c2440_iomux_func { - /* PORT A */ - IOMUXA_ADDR0 = 1, - IOMUXA_ADDR16 = (1 << 1), - IOMUXA_ADDR17 = (1 << 2), - IOMUXA_ADDR18 = (1 << 3), - IOMUXA_ADDR19 = (1 << 4), - IOMUXA_ADDR20 = (1 << 5), - IOMUXA_ADDR21 = (1 << 6), - IOMUXA_ADDR22 = (1 << 7), - IOMUXA_ADDR23 = (1 << 8), - IOMUXA_ADDR24 = (1 << 9), - IOMUXA_ADDR25 = (1 << 10), - IOMUXA_ADDR26 = (1 << 11), - IOMUXA_nGCS1 = (1 << 12), - IOMUXA_nGCS2 = (1 << 13), - IOMUXA_nGCS3 = (1 << 14), - IOMUXA_nGCS4 = (1 << 15), - IOMUXA_nGCS5 = (1 << 16), - IOMUXA_CLE = (1 << 17), - IOMUXA_ALE = (1 << 18), - IOMUXA_nFWE = (1 << 19), - IOMUXA_nFRE = (1 << 20), - IOMUXA_nRSTOUT = (1 << 21), - IOMUXA_nFCE = (1 << 22), - - /* PORT B */ - IOMUXB_nXDREQ0 = (2 << 20), - IOMUXB_nXDACK0 = (2 << 18), - IOMUXB_nXDREQ1 = (2 << 16), - IOMUXB_nXDACK1 = (2 << 14), - IOMUXB_nXBREQ = (2 << 12), - IOMUXB_nXBACK = (2 << 10), - IOMUXB_TCLK0 = (2 << 8), - IOMUXB_TOUT3 = (2 << 6), - IOMUXB_TOUT2 = (2 << 4), - IOMUXB_TOUT1 = (2 << 2), - IOMUXB_TOUT0 = 2, - - /* PORT C */ - IOMUXC_VS7 = (2 << 30), - IOMUXC_VS6 = (2 << 28), - IOMUXC_VS5 = (2 << 26), - IOMUXC_VS4 = (2 << 24), - IOMUXC_VS3 = (2 << 22), - IOMUXC_VS2 = (2 << 20), - IOMUXC_VS1 = (2 << 18), - IOMUXC_VS0 = (2 << 16), - IOMUXC_LCD_LPCREVB = (2 << 14), - IOMUXC_LCD_LPCREV = (2 << 12), - IOMUXC_LCD_LPCOE = (2 << 10), - IOMUXC_VM = (2 << 8), - IOMUXC_VFRAME = (2 << 6), - IOMUXC_VLINE = (2 << 4), - IOMUXC_VCLK = (2 << 2), - IOMUXC_LEND = 2, - IOMUXC_I2SSDI = (3 << 8), - - /* PORT D */ - IOMUXD_VS23 = (2 << 30), - IOMUXD_VS22 = (2 << 28), - IOMUXD_VS21 = (2 << 26), - IOMUXD_VS20 = (2 << 24), - IOMUXD_VS19 = (2 << 22), - IOMUXD_VS18 = (2 << 20), - IOMUXD_VS17 = (2 << 18), - IOMUXD_VS16 = (2 << 16), - IOMUXD_VS15 = (2 << 14), - IOMUXD_VS14 = (2 << 12), - IOMUXD_VS13 = (2 << 10), - IOMUXD_VS12 = (2 << 8), - IOMUXD_VS11 = (2 << 6), - IOMUXD_VS10 = (2 << 4), - IOMUXD_VS9 = (2 << 2), - IOMUXD_VS8 = 2, - IOMUXD_nSS0 = (3 << 30), - IOMUXD_nSS1 = (3 << 28), - IOMUXD_SPICLK1 = (3 << 20), - IOMUXD_SPIMOSI1 = (3 << 18), - IOMUXD_SPIMISO1 = (3 << 16), - - /* PORT E */ - IOMUXE_IICSDA = (2 << 30), - IOMUXE_IICSCL = (2 << 28), - IOMUXE_SPICLK0 = (2 << 26), - IOMUXE_SPIMOSI0 = (2 << 24), - IOMUXE_SPIMISO0 = (2 << 22), - IOMUXE_SDDAT3 = (2 << 20), - IOMUXE_SDDAT2 = (2 << 18), - IOMUXE_SDDAT1 = (2 << 16), - IOMUXE_SDDAT0 = (2 << 14), - IOMUXE_SDCMD = (2 << 12), - IOMUXE_SDCLK = (2 << 10), - IOMUXE_I2SDO = (2 << 8), - IOMUXE_I2SDI = (2 << 6), - IOMUXE_CDCLK = (2 << 4), - IOMUXE_I2SSCLK = (2 << 2), - IOMUXE_I2SLRCK = 2, - IOMUXE_AC_SDATA_OUT = (3 << 8), - IOMUXE_AC_SDATA_IN = (3 << 6), - IOMUXE_AC_nRESET = (3 << 4), - IOMUXE_AC_BIT_CLK = (3 << 2), - IOMUXE_AC_SYNC = 3, - - /* PORT F */ - IOMUXF_EINT7 = (2 << 14), - IOMUXF_EINT6 = (2 << 12), - IOMUXF_EINT5 = (2 << 10), - IOMUXF_EINT4 = (2 << 8), - IOMUXF_EINT3 = (2 << 6), - IOMUXF_EINT2 = (2 << 4), - IOMUXF_EINT1 = (2 << 2), - IOMUXF_EINT0 = 2, - - /* PORT G */ - IOMUXG_EINT23 = (2 << 30), - IOMUXG_EINT22 = (2 << 28), - IOMUXG_EINT21 = (2 << 26), - IOMUXG_EINT20 = (2 << 24), - IOMUXG_EINT19 = (2 << 22), - IOMUXG_EINT18 = (2 << 20), - IOMUXG_EINT17 = (2 << 18), - IOMUXG_EINT16 = (2 << 16), - IOMUXG_EINT15 = (2 << 14), - IOMUXG_EINT14 = (2 << 12), - IOMUXG_EINT13 = (2 << 10), - IOMUXG_EINT12 = (2 << 8), - IOMUXG_EINT11 = (2 << 6), - IOMUXG_EINT10 = (2 << 4), - IOMUXG_EINT9 = (2 << 2), - IOMUXG_EINT8 = 2, - IOMUXG_TCLK1 = (3 << 22), - IOMUXG_nCTS1 = (3 << 20), - IOMUXG_nRTS1 = (3 << 18), - IOMUXG_SPICLK1 = (3 << 14), - IOMUXG_SPIMOSI1 = (3 << 12), - IOMUXG_SPIMISO1 = (3 << 10), - IOMUXG_LCD_PWRDN = (3 << 8), - IOMUXG_nSS1 = (3 << 6), - IOMUXG_nSS0 = (3 << 4), - - /* PORT H */ - IOMUXH_CLKOUT1 = (2 << 20), - IOMUXH_CLKOUT0 = (2 << 18), - IOMUXH_UEXTCLK = (2 << 16), - IOMUXH_RXD2 = (2 << 14), - IOMUXH_TXD2 = (2 << 12), - IOMUXH_RXD1 = (2 << 10), - IOMUXH_TXD1 = (2 << 8), - IOMUXH_RXD0 = (2 << 6), - IOMUXH_TXD0 = (2 << 4), - IOMUXH_nRTS0 = (2 << 2), - IOMUXH_nCTS0 = 2, - IOMUXH_nCTS1 = (3 << 14), - IOMUXH_nRTS1 = (3 << 12), - - /* PORT J */ - IOMUXJ_CAMRESET = (2 << 24), - IOMUXJ_CAMCLKOUT = (2 << 22), - IOMUXJ_CAMHREF = (2 << 20), - IOMUXJ_CAMVSYNC = (2 << 18), - IOMUXJ_CAMPCLK = (2 << 16), - IOMUXJ_CAMDATA7 = (2 << 14), - IOMUXJ_CAMDATA6 = (2 << 12), - IOMUXJ_CAMDATA5 = (2 << 10), - IOMUXJ_CAMDATA4 = (2 << 8), - IOMUXJ_CAMDATA3 = (2 << 6), - IOMUXJ_CAMDATA2 = (2 << 4), - IOMUXJ_CAMDATA1 = (2 << 2), - IOMUXJ_CAMDATA0 = 2 -}; - -#endif diff --git a/arch/arm/include/asm/arch-s3c24x0/memory.h b/arch/arm/include/asm/arch-s3c24x0/memory.h deleted file mode 100644 index d6a787b..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/memory.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * linux/include/asm-arm/arch-s3c2400/memory.h by garyj@denx.de - * based on - * linux/include/asm-arm/arch-sa1100/memory.h - * - * Copyright (c) 1999 Nicolas Pitre <nico@visuaide.com> - */ - -#ifndef __ASM_ARCH_MEMORY_H -#define __ASM_ARCH_MEMORY_H - - -/* - * Task size: 3GB - */ -#define TASK_SIZE (0xc0000000UL) -#define TASK_SIZE_26 (0x04000000UL) - -/* - * This decides where the kernel will search for a free chunk of vm - * space during mmap's. - */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) - -/* - * Page offset: 3GB - */ -#define PAGE_OFFSET (0xc0000000UL) - -/* - * Physical DRAM offset is 0x0c000000 on the S3C2400 - */ -#define PHYS_OFFSET (0x0c000000UL) - -/* Modified for S3C2400, by chc, 20010509 */ -#define RAM_IN_BANK_0 32*1024*1024 -#define RAM_IN_BANK_1 0 -#define RAM_IN_BANK_2 0 -#define RAM_IN_BANK_3 0 - -#define MEM_SIZE (RAM_IN_BANK_0+RAM_IN_BANK_1+RAM_IN_BANK_2+RAM_IN_BANK_3) - - -/* translation macros */ -#define __virt_to_phys__is_a_macro -#define __phys_to_virt__is_a_macro - -#if (RAM_IN_BANK_1 + RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0) - -#define __virt_to_phys(x) ( (x) - PAGE_OFFSET + 0x0c000000 ) -#define __phys_to_virt(x) ( (x) - 0x0c000000 + PAGE_OFFSET ) - -#elif (RAM_IN_BANK_0 == RAM_IN_BANK_1) && \ - (RAM_IN_BANK_2 + RAM_IN_BANK_3 == 0) - -/* Two identical banks */ -#define __virt_to_phys(x) \ - ( ((x) < PAGE_OFFSET+RAM_IN_BANK_0) ? \ - ((x) - PAGE_OFFSET + _DRAMBnk0) : \ - ((x) - PAGE_OFFSET - RAM_IN_BANK_0 + _DRAMBnk1) ) -#define __phys_to_virt(x) \ - ( ((x)&0x07ffffff) + \ - (((x)&0x08000000) ? PAGE_OFFSET+RAM_IN_BANK_0 : PAGE_OFFSET) ) -#else - -/* It's more efficient for all other cases to use the function call */ -#undef __virt_to_phys__is_a_macro -#undef __phys_to_virt__is_a_macro -extern unsigned long __virt_to_phys(unsigned long vpage); -extern unsigned long __phys_to_virt(unsigned long ppage); - -#endif - -/* - * Virtual view <-> DMA view memory address translations - * virt_to_bus: Used to translate the virtual address to an - * address suitable to be passed to set_dma_addr - * bus_to_virt: Used to convert an address for DMA operations - * to an address that the kernel can use. - * - * On the SA1100, bus addresses are equivalent to physical addresses. - */ -#define __virt_to_bus__is_a_macro -#define __virt_to_bus(x) __virt_to_phys(x) -#define __bus_to_virt__is_a_macro -#define __bus_to_virt(x) __phys_to_virt(x) - - -#ifdef CONFIG_DISCONTIGMEM -#error "CONFIG_DISCONTIGMEM will not work on S3C2400" -/* - * Because of the wide memory address space between physical RAM banks on the - * SA1100, it's much more convenient to use Linux's NUMA support to implement - * our memory map representation. Assuming all memory nodes have equal access - * characteristics, we then have generic discontiguous memory support. - * - * Of course, all this isn't mandatory for SA1100 implementations with only - * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. - * - * The nodes are matched with the physical memory bank addresses which are - * incidentally the same as virtual addresses. - * - * node 0: 0xc0000000 - 0xc7ffffff - * node 1: 0xc8000000 - 0xcfffffff - * node 2: 0xd0000000 - 0xd7ffffff - * node 3: 0xd8000000 - 0xdfffffff - */ - -#define NR_NODES 4 - -/* - * Given a kernel address, find the home node of the underlying memory. - */ -#define KVADDR_TO_NID(addr) \ - (((unsigned long)(addr) - 0xc0000000) >> 27) - -/* - * Given a physical address, convert it to a node id. - */ -#define PHYS_TO_NID(addr) KVADDR_TO_NID(__phys_to_virt(addr)) - -/* - * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory - * and returns the mem_map of that node. - */ -#define ADDR_TO_MAPBASE(kaddr) \ - NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr))) - -/* - * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory - * and returns the index corresponding to the appropriate page in the - * node's mem_map. - */ -#define LOCAL_MAP_NR(kvaddr) \ - (((unsigned long)(kvaddr) & 0x07ffffff) >> PAGE_SHIFT) - -/* - * Given a kaddr, virt_to_page returns a pointer to the corresponding - * mem_map entry. - */ -#define virt_to_page(kaddr) \ - (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr)) - -/* - * VALID_PAGE returns a non-zero value if given page pointer is valid. - * This assumes all node's mem_maps are stored within the node they refer to. - */ -#define VALID_PAGE(page) \ -({ unsigned int node = KVADDR_TO_NID(page); \ - ( (node < NR_NODES) && \ - ((unsigned)((page) - NODE_MEM_MAP(node)) < NODE_DATA(node)->node_size) ); \ -}) - -#else - -#define PHYS_TO_NID(addr) (0) - -#endif -#endif /* __ASM_ARCH_MEMORY_H */ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2400.h b/arch/arm/include/asm/arch-s3c24x0/s3c2400.h deleted file mode 100644 index 2389118..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/s3c2400.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************ - * NAME : s3c2400.h - * Version : 31.3.2003 - * - * Based on S3C2400X User's manual Rev 1.1 - ************************************************/ - -#ifndef __S3C2400_H__ -#define __S3C2400_H__ - -#define S3C24X0_UART_CHANNELS 2 -#define S3C24X0_SPI_CHANNELS 1 -#define PALETTE (0x14A00400) /* SJS */ - -enum s3c24x0_uarts_nr { - S3C24X0_UART0, - S3C24X0_UART1, -}; - -/*S3C2400 device base addresses */ -#define S3C24X0_MEMCTL_BASE 0x14000000 -#define S3C24X0_USB_HOST_BASE 0x14200000 -#define S3C24X0_INTERRUPT_BASE 0x14400000 -#define S3C24X0_DMA_BASE 0x14600000 -#define S3C24X0_CLOCK_POWER_BASE 0x14800000 -#define S3C24X0_LCD_BASE 0x14A00000 -#define S3C24X0_UART_BASE 0x15000000 -#define S3C24X0_TIMER_BASE 0x15100000 -#define S3C24X0_USB_DEVICE_BASE 0x15200140 -#define S3C24X0_WATCHDOG_BASE 0x15300000 -#define S3C24X0_I2C_BASE 0x15400000 -#define S3C24X0_I2S_BASE 0x15508000 -#define S3C24X0_GPIO_BASE 0x15600000 -#define S3C24X0_RTC_BASE 0x15700000 -#define S3C24X0_ADC_BASE 0x15800000 -#define S3C24X0_SPI_BASE 0x15900000 -#define S3C2400_MMC_BASE 0x15A00000 - -/* include common stuff */ -#include <asm/arch/s3c24x0.h> - - -static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) -{ - return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; -} - -static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) -{ - return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; -} - -static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) -{ - return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; -} - -static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) -{ - return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; -} - -static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) -{ - return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; -} - -static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) -{ - return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; -} - -static inline struct s3c24x0_uart - *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) -{ - return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); -} - -static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) -{ - return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; -} - -static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) -{ - return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; -} - -static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) -{ - return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; -} - -static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) -{ - return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; -} - -static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) -{ - return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; -} - -static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) -{ - return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; -} - -static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) -{ - return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; -} - -static inline struct s3c2400_adc *s3c2400_get_base_adc(void) -{ - return (struct s3c2400_adc *)S3C24X0_ADC_BASE; -} - -static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) -{ - return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; -} - -static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void) -{ - return (struct s3c2400_mmc *)S3C2400_MMC_BASE; -} - -#endif /*__S3C2400_H__*/ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h b/arch/arm/include/asm/arch-s3c24x0/s3c2410.h deleted file mode 100644 index 8773ce3..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/s3c2410.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************ - * NAME : s3c2410.h - * Version : 31.3.2003 - * - * Based on S3C2410X User's manual Rev 1.1 - ************************************************/ - -#ifndef __S3C2410_H__ -#define __S3C2410_H__ - -#define S3C24X0_UART_CHANNELS 3 -#define S3C24X0_SPI_CHANNELS 2 - -/* S3C2410 only supports 512 Byte HW ECC */ -#define S3C2410_ECCSIZE 512 -#define S3C2410_ECCBYTES 3 - -enum s3c24x0_uarts_nr { - S3C24X0_UART0, - S3C24X0_UART1, - S3C24X0_UART2 -}; - -/* S3C2410 device base addresses */ -#define S3C24X0_MEMCTL_BASE 0x48000000 -#define S3C24X0_USB_HOST_BASE 0x49000000 -#define S3C24X0_INTERRUPT_BASE 0x4A000000 -#define S3C24X0_DMA_BASE 0x4B000000 -#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 -#define S3C24X0_LCD_BASE 0x4D000000 -#define S3C2410_NAND_BASE 0x4E000000 -#define S3C24X0_UART_BASE 0x50000000 -#define S3C24X0_TIMER_BASE 0x51000000 -#define S3C24X0_USB_DEVICE_BASE 0x52000140 -#define S3C24X0_WATCHDOG_BASE 0x53000000 -#define S3C24X0_I2C_BASE 0x54000000 -#define S3C24X0_I2S_BASE 0x55000000 -#define S3C24X0_GPIO_BASE 0x56000000 -#define S3C24X0_RTC_BASE 0x57000000 -#define S3C2410_ADC_BASE 0x58000000 -#define S3C24X0_SPI_BASE 0x59000000 -#define S3C2410_SDI_BASE 0x5A000000 - - -/* include common stuff */ -#include <asm/arch/s3c24x0.h> - - -static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) -{ - return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; -} - -static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) -{ - return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; -} - -static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) -{ - return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; -} - -static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) -{ - return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; -} - -static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) -{ - return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; -} - -static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) -{ - return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; -} - -static inline struct s3c24x0_nand *s3c24x0_get_base_nand(void) -{ - return (struct s3c24x0_nand *)S3C2410_NAND_BASE; -} - -static inline struct s3c24x0_uart - *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) -{ - return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); -} - -static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) -{ - return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; -} - -static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) -{ - return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; -} - -static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) -{ - return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; -} - -static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) -{ - return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; -} - -static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) -{ - return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; -} - -static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) -{ - return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; -} - -static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) -{ - return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; -} - -static inline struct s3c2410_adc *s3c2410_get_base_adc(void) -{ - return (struct s3c2410_adc *)S3C2410_ADC_BASE; -} - -static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) -{ - return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; -} - -static inline struct s3c24x0_sdi *s3c24x0_get_base_sdi(void) -{ - return (struct s3c24x0_sdi *)S3C2410_SDI_BASE; -} - -#endif /*__S3C2410_H__*/ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h deleted file mode 100644 index 7a525f2..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * (C) Copyright 2003 - * David Mueller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************ - * NAME : s3c2440.h - * Version : 31.3.2003 - * - * Based on S3C2440 User's manual Rev x.x - ************************************************/ - -#ifndef __S3C2440_H__ -#define __S3C2440_H__ - -#define S3C24X0_UART_CHANNELS 3 -#define S3C24X0_SPI_CHANNELS 2 - -/* S3C2440 only supports 512 Byte HW ECC */ -#define S3C2440_ECCSIZE 512 -#define S3C2440_ECCBYTES 3 - -enum s3c24x0_uarts_nr { - S3C24X0_UART0, - S3C24X0_UART1, - S3C24X0_UART2 -}; - -/* S3C2440 device base addresses */ -#define S3C24X0_MEMCTL_BASE 0x48000000 -#define S3C24X0_USB_HOST_BASE 0x49000000 -#define S3C24X0_INTERRUPT_BASE 0x4A000000 -#define S3C24X0_DMA_BASE 0x4B000000 -#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 -#define S3C24X0_LCD_BASE 0x4D000000 -#define S3C2440_NAND_BASE 0x4E000000 -#define S3C24X0_UART_BASE 0x50000000 -#define S3C24X0_TIMER_BASE 0x51000000 -#define S3C24X0_USB_DEVICE_BASE 0x52000140 -#define S3C24X0_WATCHDOG_BASE 0x53000000 -#define S3C24X0_I2C_BASE 0x54000000 -#define S3C24X0_I2S_BASE 0x55000000 -#define S3C24X0_GPIO_BASE 0x56000000 -#define S3C24X0_RTC_BASE 0x57000000 -#define S3C2440_ADC_BASE 0x58000000 -#define S3C24X0_SPI_BASE 0x59000000 -#define S3C2440_SDI_BASE 0x5A000000 - -/* include common stuff */ -#include <asm/arch/s3c24x0.h> - -static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) -{ - return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; -} - -static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) -{ - return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; -} - -static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) -{ - return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; -} - -static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) -{ - return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; -} - -static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) -{ - return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; -} - -static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) -{ - return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; -} - -static inline struct s3c24x0_nand *s3c24x0_get_base_nand(void) -{ - return (struct s3c24x0_nand *)S3C2440_NAND_BASE; -} - -static inline struct s3c24x0_uart - *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) -{ - return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); -} - -static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) -{ - return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; -} - -static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) -{ - return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; -} - -static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) -{ - return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; -} - -static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) -{ - return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; -} - -static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) -{ - return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; -} - -static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) -{ - return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; -} - -static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) -{ - return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; -} - -static inline struct s3c2440_adc *s3c2440_get_base_adc(void) -{ - return (struct s3c2440_adc *)S3C2440_ADC_BASE; -} - -static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) -{ - return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; -} - -static inline struct s3c24x0_sdi *s3c24x0_get_base_sdi(void) -{ - return (struct s3c24x0_sdi *)S3C2440_SDI_BASE; -} - -#endif /*__S3C2440_H__*/ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h deleted file mode 100644 index 2dae9fc..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h +++ /dev/null @@ -1,708 +0,0 @@ -/* - * (C) Copyright 2003 - * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/************************************************ - * NAME : s3c24x0.h - * Version : 31.3.2003 - * - * common stuff for SAMSUNG S3C24X0 SoC - ************************************************/ - -#ifndef __S3C24X0_H__ -#define __S3C24X0_H__ - -/* Memory controller (see manual chapter 5) */ -struct s3c24x0_memctl { - u32 bwscon; - u32 bankcon[8]; - u32 refresh; - u32 banksize; - u32 mrsrb6; - u32 mrsrb7; -}; - - -/* USB HOST (see manual chapter 12) */ -struct s3c24x0_usb_host { - u32 HcRevision; - u32 HcControl; - u32 HcCommonStatus; - u32 HcInterruptStatus; - u32 HcInterruptEnable; - u32 HcInterruptDisable; - u32 HcHCCA; - u32 HcPeriodCuttendED; - u32 HcControlHeadED; - u32 HcControlCurrentED; - u32 HcBulkHeadED; - u32 HcBuldCurrentED; - u32 HcDoneHead; - u32 HcRmInterval; - u32 HcFmRemaining; - u32 HcFmNumber; - u32 HcPeriodicStart; - u32 HcLSThreshold; - u32 HcRhDescriptorA; - u32 HcRhDescriptorB; - u32 HcRhStatus; - u32 HcRhPortStatus1; - u32 HcRhPortStatus2; -}; - - -/* INTERRUPT (see manual chapter 14) */ -struct s3c24x0_interrupt { - u32 srcpnd; - u32 intmod; - u32 intmsk; - u32 priority; - u32 intpnd; - u32 intoffset; -#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) - u32 subsrcpnd; - u32 intsubmsk; -#endif -}; - - -/* DMAS (see manual chapter 8) */ -struct s3c24x0_dma { - u32 disrc; -#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) - u32 disrcc; -#endif - u32 didst; -#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) - u32 didstc; -#endif - u32 dcon; - u32 dstat; - u32 dcsrc; - u32 dcdst; - u32 dmasktrig; -#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) \ - || defined(CONFIG_S3C2440) - u32 res[1]; -#endif -}; - -struct s3c24x0_dmas { - struct s3c24x0_dma dma[4]; -}; - - -/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */ -/* (see S3C2410 manual chapter 7) */ -struct s3c24x0_clock_power { - u32 locktime; - u32 mpllcon; - u32 upllcon; - u32 clkcon; - u32 clkslow; - u32 clkdivn; -#if defined(CONFIG_S3C2440) - u32 camdivn; -#endif -}; - - -/* LCD CONTROLLER (see manual chapter 15) */ -struct s3c24x0_lcd { - u32 lcdcon1; - u32 lcdcon2; - u32 lcdcon3; - u32 lcdcon4; - u32 lcdcon5; - u32 lcdsaddr1; - u32 lcdsaddr2; - u32 lcdsaddr3; - u32 redlut; - u32 greenlut; - u32 bluelut; - u32 res[8]; - u32 dithmode; - u32 tpal; -#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) - u32 lcdintpnd; - u32 lcdsrcpnd; - u32 lcdintmsk; - u32 lpcsel; -#endif -}; - - -/* NAND FLASH (see manual chapter 6) */ -struct s3c24x0_nand { - u32 nfconf; -#ifndef CONFIG_S3C2410 - u32 nfcont; -#endif - u32 nfcmd; - u32 nfaddr; - u32 nfdata; -#ifndef CONFIG_S3C2410 - u32 nfeccd0; - u32 nfeccd1; - u32 nfeccd; -#endif - u32 nfstat; -#ifdef CONFIG_S3C2410 - u32 nfecc; -#else - u32 nfstat0; - u32 nfstat1; - u32 nfmecc0; - u32 nfmecc1; - u32 nfsecc; - u32 nfsblk; - u32 nfeblk; -#endif -}; - -/* UART (see manual chapter 11) */ -struct s3c24x0_uart { - u32 ulcon; - u32 ucon; - u32 ufcon; - u32 umcon; - u32 utrstat; - u32 uerstat; - u32 ufstat; - u32 umstat; -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 utxh; - u8 res2[3]; - u8 urxh; -#else /* Little Endian */ - u8 utxh; - u8 res1[3]; - u8 urxh; - u8 res2[3]; -#endif - u32 ubrdiv; -}; - - -/* PWM TIMER (see manual chapter 10) */ -struct s3c24x0_timer { - u32 tcntb; - u32 tcmpb; - u32 tcnto; -}; - -struct s3c24x0_timers { - u32 tcfg0; - u32 tcfg1; - u32 tcon; - struct s3c24x0_timer ch[4]; - u32 tcntb4; - u32 tcnto4; -}; - - -/* USB DEVICE (see manual chapter 13) */ -struct s3c24x0_usb_dev_fifos { -#ifdef __BIG_ENDIAN - u8 res[3]; - u8 ep_fifo_reg; -#else /* little endian */ - u8 ep_fifo_reg; - u8 res[3]; -#endif -}; - -struct s3c24x0_usb_dev_dmas { -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 ep_dma_con; - u8 res2[3]; - u8 ep_dma_unit; - u8 res3[3]; - u8 ep_dma_fifo; - u8 res4[3]; - u8 ep_dma_ttc_l; - u8 res5[3]; - u8 ep_dma_ttc_m; - u8 res6[3]; - u8 ep_dma_ttc_h; -#else /* little endian */ - u8 ep_dma_con; - u8 res1[3]; - u8 ep_dma_unit; - u8 res2[3]; - u8 ep_dma_fifo; - u8 res3[3]; - u8 ep_dma_ttc_l; - u8 res4[3]; - u8 ep_dma_ttc_m; - u8 res5[3]; - u8 ep_dma_ttc_h; - u8 res6[3]; -#endif -}; - -struct s3c24x0_usb_device { -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 func_addr_reg; - u8 res2[3]; - u8 pwr_reg; - u8 res3[3]; - u8 ep_int_reg; - u8 res4[15]; - u8 usb_int_reg; - u8 res5[3]; - u8 ep_int_en_reg; - u8 res6[15]; - u8 usb_int_en_reg; - u8 res7[3]; - u8 frame_num1_reg; - u8 res8[3]; - u8 frame_num2_reg; - u8 res9[3]; - u8 index_reg; - u8 res10[7]; - u8 maxp_reg; - u8 res11[3]; - u8 ep0_csr_in_csr1_reg; - u8 res12[3]; - u8 in_csr2_reg; - u8 res13[7]; - u8 out_csr1_reg; - u8 res14[3]; - u8 out_csr2_reg; - u8 res15[3]; - u8 out_fifo_cnt1_reg; - u8 res16[3]; - u8 out_fifo_cnt2_reg; -#else /* little endian */ - u8 func_addr_reg; - u8 res1[3]; - u8 pwr_reg; - u8 res2[3]; - u8 ep_int_reg; - u8 res3[15]; - u8 usb_int_reg; - u8 res4[3]; - u8 ep_int_en_reg; - u8 res5[15]; - u8 usb_int_en_reg; - u8 res6[3]; - u8 frame_num1_reg; - u8 res7[3]; - u8 frame_num2_reg; - u8 res8[3]; - u8 index_reg; - u8 res9[7]; - u8 maxp_reg; - u8 res10[7]; - u8 ep0_csr_in_csr1_reg; - u8 res11[3]; - u8 in_csr2_reg; - u8 res12[3]; - u8 out_csr1_reg; - u8 res13[7]; - u8 out_csr2_reg; - u8 res14[3]; - u8 out_fifo_cnt1_reg; - u8 res15[3]; - u8 out_fifo_cnt2_reg; - u8 res16[3]; -#endif /* __BIG_ENDIAN */ - struct s3c24x0_usb_dev_fifos fifo[5]; - struct s3c24x0_usb_dev_dmas dma[5]; -}; - - -/* WATCH DOG TIMER (see manual chapter 18) */ -struct s3c24x0_watchdog { - u32 wtcon; - u32 wtdat; - u32 wtcnt; -}; - -/* IIS (see manual chapter 21) */ -struct s3c24x0_i2s { -#ifdef __BIG_ENDIAN - u16 res1; - u16 iiscon; - u16 res2; - u16 iismod; - u16 res3; - u16 iispsr; - u16 res4; - u16 iisfcon; - u16 res5; - u16 iisfifo; -#else /* little endian */ - u16 iiscon; - u16 res1; - u16 iismod; - u16 res2; - u16 iispsr; - u16 res3; - u16 iisfcon; - u16 res4; - u16 iisfifo; - u16 res5; -#endif -}; - - -/* I/O PORT (see manual chapter 9) */ -struct s3c24x0_gpio { -#ifdef CONFIG_S3C2400 - u32 pacon; - u32 padat; - - u32 pbcon; - u32 pbdat; - u32 pbup; - - u32 pccon; - u32 pcdat; - u32 pcup; - - u32 pdcon; - u32 pddat; - u32 pdup; - - u32 pecon; - u32 pedat; - u32 peup; - - u32 pfcon; - u32 pfdat; - u32 pfup; - - u32 pgcon; - u32 pgdat; - u32 pgup; - - u32 opencr; - - u32 misccr; - u32 extint; -#endif -#ifdef CONFIG_S3C2410 - u32 gpacon; - u32 gpadat; - u32 res1[2]; - u32 gpbcon; - u32 gpbdat; - u32 gpbup; - u32 res2; - u32 gpccon; - u32 gpcdat; - u32 gpcup; - u32 res3; - u32 gpdcon; - u32 gpddat; - u32 gpdup; - u32 res4; - u32 gpecon; - u32 gpedat; - u32 gpeup; - u32 res5; - u32 gpfcon; - u32 gpfdat; - u32 gpfup; - u32 res6; - u32 gpgcon; - u32 gpgdat; - u32 gpgup; - u32 res7; - u32 gphcon; - u32 gphdat; - u32 gphup; - u32 res8; - - u32 misccr; - u32 dclkcon; - u32 extint0; - u32 extint1; - u32 extint2; - u32 eintflt0; - u32 eintflt1; - u32 eintflt2; - u32 eintflt3; - u32 eintmask; - u32 eintpend; - u32 gstatus0; - u32 gstatus1; - u32 gstatus2; - u32 gstatus3; - u32 gstatus4; -#endif -#if defined(CONFIG_S3C2440) - u32 gpacon; - u32 gpadat; - u32 res1[2]; - u32 gpbcon; - u32 gpbdat; - u32 gpbup; - u32 res2; - u32 gpccon; - u32 gpcdat; - u32 gpcup; - u32 res3; - u32 gpdcon; - u32 gpddat; - u32 gpdup; - u32 res4; - u32 gpecon; - u32 gpedat; - u32 gpeup; - u32 res5; - u32 gpfcon; - u32 gpfdat; - u32 gpfup; - u32 res6; - u32 gpgcon; - u32 gpgdat; - u32 gpgup; - u32 res7; - u32 gphcon; - u32 gphdat; - u32 gphup; - u32 res8; - - u32 misccr; - u32 dclkcon; - u32 extint0; - u32 extint1; - u32 extint2; - u32 eintflt0; - u32 eintflt1; - u32 eintflt2; - u32 eintflt3; - u32 eintmask; - u32 eintpend; - u32 gstatus0; - u32 gstatus1; - u32 gstatus2; - u32 gstatus3; - u32 gstatus4; - - u32 res9; - u32 dsc0; - u32 dsc1; - u32 mslcon; - u32 gpjcon; - u32 gpjdat; - u32 gpjup; - u32 res10; -#endif -}; - - -/* RTC (see manual chapter 17) */ -struct s3c24x0_rtc { -#ifdef __BIG_ENDIAN - u8 res1[67]; - u8 rtccon; - u8 res2[3]; - u8 ticnt; - u8 res3[11]; - u8 rtcalm; - u8 res4[3]; - u8 almsec; - u8 res5[3]; - u8 almmin; - u8 res6[3]; - u8 almhour; - u8 res7[3]; - u8 almdate; - u8 res8[3]; - u8 almmon; - u8 res9[3]; - u8 almyear; - u8 res10[3]; - u8 rtcrst; - u8 res11[3]; - u8 bcdsec; - u8 res12[3]; - u8 bcdmin; - u8 res13[3]; - u8 bcdhour; - u8 res14[3]; - u8 bcddate; - u8 res15[3]; - u8 bcdday; - u8 res16[3]; - u8 bcdmon; - u8 res17[3]; - u8 bcdyear; -#else /* little endian */ - u8 res0[64]; - u8 rtccon; - u8 res1[3]; - u8 ticnt; - u8 res2[11]; - u8 rtcalm; - u8 res3[3]; - u8 almsec; - u8 res4[3]; - u8 almmin; - u8 res5[3]; - u8 almhour; - u8 res6[3]; - u8 almdate; - u8 res7[3]; - u8 almmon; - u8 res8[3]; - u8 almyear; - u8 res9[3]; - u8 rtcrst; - u8 res10[3]; - u8 bcdsec; - u8 res11[3]; - u8 bcdmin; - u8 res12[3]; - u8 bcdhour; - u8 res13[3]; - u8 bcddate; - u8 res14[3]; - u8 bcdday; - u8 res15[3]; - u8 bcdmon; - u8 res16[3]; - u8 bcdyear; - u8 res17[3]; -#endif -}; - - -/* ADC (see manual chapter 16) */ -struct s3c2400_adc { - u32 adccon; - u32 adcdat; -}; - - -/* ADC (see manual chapter 16) */ -struct s3c2410_adc { - u32 adccon; - u32 adctsc; - u32 adcdly; - u32 adcdat0; - u32 adcdat1; -}; - - -/* SPI (see manual chapter 22) */ -struct s3c24x0_spi_channel { - u8 spcon; - u8 res1[3]; - u8 spsta; - u8 res2[3]; - u8 sppin; - u8 res3[3]; - u8 sppre; - u8 res4[3]; - u8 sptdat; - u8 res5[3]; - u8 sprdat; - u8 res6[3]; - u8 res7[16]; -}; - -struct s3c24x0_spi { - struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS]; -}; - - -/* MMC INTERFACE (see S3C2400 manual chapter 19) */ -struct s3c2400_mmc { -#ifdef __BIG_ENDIAN - u8 res1[3]; - u8 mmcon; - u8 res2[3]; - u8 mmcrr; - u8 res3[3]; - u8 mmfcon; - u8 res4[3]; - u8 mmsta; - u16 res5; - u16 mmfsta; - u8 res6[3]; - u8 mmpre; - u16 res7; - u16 mmlen; - u8 res8[3]; - u8 mmcr7; - u32 mmrsp[4]; - u8 res9[3]; - u8 mmcmd0; - u32 mmcmd1; - u16 res10; - u16 mmcr16; - u8 res11[3]; - u8 mmdat; -#else - u8 mmcon; - u8 res1[3]; - u8 mmcrr; - u8 res2[3]; - u8 mmfcon; - u8 res3[3]; - u8 mmsta; - u8 res4[3]; - u16 mmfsta; - u16 res5; - u8 mmpre; - u8 res6[3]; - u16 mmlen; - u16 res7; - u8 mmcr7; - u8 res8[3]; - u32 mmrsp[4]; - u8 mmcmd0; - u8 res9[3]; - u32 mmcmd1; - u16 mmcr16; - u16 res10; - u8 mmdat; - u8 res11[3]; -#endif -}; - - -/* SD INTERFACE (see S3C2410 manual chapter 19) */ -struct s3c24x0_sdi { - u32 sdicon; - u32 sdipre; - u32 sdicarg; - u32 sdiccon; - u32 sdicsta; - u32 sdirsp0; - u32 sdirsp1; - u32 sdirsp2; - u32 sdirsp3; - u32 sdidtimer; - u32 sdibsize; - u32 sdidcon; - u32 sdidcnt; - u32 sdidsta; - u32 sdifsta; -#ifdef CONFIG_S3C2410 - u32 sdidat; - u32 sdiimsk; -#else - u32 sdiimsk; - u32 sdidat; -#endif -}; - -#ifdef CONFIG_CMD_MMC -#include <mmc.h> -int s3cmmc_initialize(bd_t *bis, int (*getcd)(struct mmc *), - int (*getwp)(struct mmc *)); -#endif - -#endif /*__S3C24X0_H__*/ diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h deleted file mode 100644 index 393cc9d..0000000 --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * (C) Copyright 2009 - * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifdef CONFIG_S3C2400 - #include <asm/arch/s3c2400.h> -#elif defined CONFIG_S3C2410 - #include <asm/arch/s3c2410.h> -#elif defined CONFIG_S3C2440 - #include <asm/arch/s3c2440.h> -#else - #error Please define the s3c24x0 cpu type -#endif diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index 6aa5e91..2419062 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -34,7 +34,9 @@ #define SUNXI_MS_BASE 0x01c07000 #define SUNXI_TVD_BASE 0x01c08000 #define SUNXI_CSI0_BASE 0x01c09000 +#ifndef CONFIG_MACH_SUNXI_H3_H5 #define SUNXI_TVE0_BASE 0x01c0a000 +#endif #define SUNXI_EMAC_BASE 0x01c0b000 #define SUNXI_LCD0_BASE 0x01c0C000 #define SUNXI_LCD1_BASE 0x01c0d000 @@ -161,10 +163,18 @@ defined(CONFIG_MACH_SUN50I) /* module sram */ #define SUNXI_SRAM_C_BASE 0x01d00000 +#ifndef CONFIG_MACH_SUN8I_H3 #define SUNXI_DE_FE0_BASE 0x01e00000 +#else +#define SUNXI_TVE0_BASE 0x01e00000 +#endif #define SUNXI_DE_FE1_BASE 0x01e20000 #define SUNXI_DE_BE0_BASE 0x01e60000 +#ifndef CONFIG_MACH_SUN50I_H5 #define SUNXI_DE_BE1_BASE 0x01e40000 +#else +#define SUNXI_TVE0_BASE 0x01e40000 +#endif #define SUNXI_MP_BASE 0x01e80000 #define SUNXI_AVG_BASE 0x01ea0000 diff --git a/arch/arm/include/asm/arch-sunxi/display2.h b/arch/arm/include/asm/arch-sunxi/display2.h index b5875f9..359cacd 100644 --- a/arch/arm/include/asm/arch-sunxi/display2.h +++ b/arch/arm/include/asm/arch-sunxi/display2.h @@ -90,6 +90,23 @@ struct de_ui { u32 ovl_size; }; +struct de_csc { + u32 csc_ctl; + u8 res[0xc]; + u32 coef11; + u32 coef12; + u32 coef13; + u32 coef14; + u32 coef21; + u32 coef22; + u32 coef23; + u32 coef24; + u32 coef31; + u32 coef32; + u32 coef33; + u32 coef34; +}; + /* * DE register constants. */ diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h index f452f88..80abac9 100644 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -24,10 +24,8 @@ #include <asm/arch/dram_sun8i_a33.h> #elif defined(CONFIG_MACH_SUN8I_A83T) #include <asm/arch/dram_sun8i_a83t.h> -#elif defined(CONFIG_MACH_SUNXI_H3_H5) || \ - defined(CONFIG_MACH_SUN8I_R40) || \ - defined(CONFIG_MACH_SUN50I) -#include <asm/arch/dram_sun8i_h3.h> +#elif defined(CONFIG_SUNXI_DRAM_DW) +#include <asm/arch/dram_sunxi_dw.h> #elif defined(CONFIG_MACH_SUN9I) #include <asm/arch/dram_sun9i.h> #else diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h index 2770986..03fd46b 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_h3.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h @@ -53,9 +53,9 @@ struct sunxi_mctl_com_reg { #define MCTL_CR_SEQUENTIAL (0x1 << 15) #define MCTL_CR_INTERLEAVED (0x0 << 15) -#define MCTL_CR_32BIT (0x1 << 12) -#define MCTL_CR_16BIT (0x0 << 12) -#define MCTL_CR_BUS_WIDTH(x) ((x) == 32 ? MCTL_CR_32BIT : MCTL_CR_16BIT) +#define MCTL_CR_FULL_WIDTH (0x1 << 12) +#define MCTL_CR_HALF_WIDTH (0x0 << 12) +#define MCTL_CR_BUS_FULL_WIDTH(x) ((x) << 12) #define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) #define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4) @@ -205,4 +205,34 @@ struct sunxi_mctl_ctl_reg { #define DXBDLR_WRITE_DELAY(x) ((x) << 8) #define DXBDLR_READ_DELAY(x) ((x) << 0) +/* + * The delay parameters below allow to allegedly specify delay times of some + * unknown unit for each individual bit trace in each of the four data bytes + * the 32-bit wide access consists of. Also three control signals can be + * adjusted individually. + */ +#define BITS_PER_BYTE 8 +#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) +/* The eight data lines (DQn) plus DM, DQS and DQSN */ +#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) +struct dram_para { + u16 page_size; + u8 bus_full_width; + u8 dual_rank; + u8 row_bits; + u8 bank_bits; + const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; + const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; + const u8 ac_delays[31]; +}; + +static inline int ns_to_t(int nanoseconds) +{ + const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; + + return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); +} + +void mctl_set_timing_params(uint16_t socid, struct dram_para *para); + #endif /* _SUNXI_DRAM_SUN8I_H3_H */ diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 388afcb..f62b2a4 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -288,6 +288,9 @@ void clock_init(void); /* Initialize the PLLs */ void clock_early_init(void); +/* @return true if hardware indicates that clock_early_init() was called */ +bool clock_early_init_done(void); + /* Returns a pointer to the clock source register for a peripheral */ u32 *get_periph_source_reg(enum periph_id periph_id); diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index 7b11895..d91d98a 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -8,6 +8,8 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H +#define PAYLOAD_ARG_CNT 5 + int zynq_slcr_get_mio_pin_status(const char *periph); unsigned int zynqmp_get_silicon_version(void); @@ -16,4 +18,10 @@ void psu_init(void); void handoff_setup(void); +void zynqmp_pmufw_version(void); +int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value); +int zynqmp_mmio_read(const u32 address, u32 *value); +int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, + u32 *ret_payload); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/bootm.h b/arch/arm/include/asm/bootm.h index 436c35a..4c9bb86 100644 --- a/arch/arm/include/asm/bootm.h +++ b/arch/arm/include/asm/bootm.h @@ -41,6 +41,7 @@ extern void udc_disconnect(void); #define BOOTM_ENABLE_INITRD_TAG 0 #endif +struct tag_serialnr; #ifdef CONFIG_SERIAL_TAG #define BOOTM_ENABLE_SERIAL_TAG 1 void get_board_serial(struct tag_serialnr *serialnr); diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index c1a70b1..d2ca277 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -484,6 +484,7 @@ struct omap_sys_ctrl_regs { u32 ctrl_core_sma_sw_1; }; +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) struct dpll_params { u32 m; u32 n; @@ -516,6 +517,7 @@ struct dpll_regs { u32 cm_div_h23_dpll; u32 cm_div_h24_dpll; }; +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ struct dplls { const struct dpll_params *mpu; @@ -539,6 +541,7 @@ struct pmic_data { int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data); }; +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) enum { OPP_LOW, OPP_NOM, @@ -584,6 +587,7 @@ struct vcores_data { struct volts eve; struct volts iva; }; +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ extern struct prcm_regs const **prcm; extern struct prcm_regs const omap5_es1_prcm; @@ -595,6 +599,8 @@ extern struct dplls dra7xx_dplls; extern struct vcores_data const **omap_vcores; extern const u32 sys_clk_array[8]; extern struct omap_sys_ctrl_regs const **ctrl; +extern struct omap_sys_ctrl_regs const am33xx_ctrl; +extern struct omap_sys_ctrl_regs const omap3_ctrl; extern struct omap_sys_ctrl_regs const omap4_ctrl; extern struct omap_sys_ctrl_regs const omap5_ctrl; extern struct omap_sys_ctrl_regs const dra7xx_ctrl; @@ -611,6 +617,7 @@ const struct dpll_params *get_iva_dpll_params(struct dplls const *); const struct dpll_params *get_usb_dpll_params(struct dplls const *); const struct dpll_params *get_abe_dpll_params(struct dplls const *); +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) void do_enable_clocks(u32 const *clk_domains, u32 const *clk_modules_hw_auto, u32 const *clk_modules_explicit_en, @@ -619,6 +626,7 @@ void do_enable_clocks(u32 const *clk_domains, void do_disable_clocks(u32 const *clk_domains, u32 const *clk_modules_disable, u8 wait_for_disable); +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ void setup_post_dividers(u32 const base, const struct dpll_params *params); @@ -630,7 +638,9 @@ void enable_basic_uboot_clocks(void); void enable_usb_clocks(int index); void disable_usb_clocks(int index); +#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX) void scale_vcores(struct vcores_data const *); +#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */ int get_voltrail_opp(int rail_offset); u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic); void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic); @@ -638,11 +648,19 @@ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, u32 txdone, u32 txdone_mask, u32 opp); s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); +struct tag_serialnr; + void omap_die_id_serial(void); void omap_die_id_get_board_serial(struct tag_serialnr *serialnr); void omap_die_id_usbethaddr(void); void omap_die_id_display(void); +#ifdef CONFIG_FASTBOOT_FLASH +void omap_set_fastboot_vars(void); +#else +static inline void omap_set_fastboot_vars(void) { } +#endif + void recalibrate_iodelay(void); void omap_smc1(u32 service, u32 val); @@ -748,7 +766,6 @@ static inline u8 is_dra72x(void) * silicon device type * Moving to common from cpu.h, since it is shared by various omap devices */ -#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10)) #define TST_DEVICE 0x0 #define EMU_DEVICE 0x1 #define HS_DEVICE 0x2 diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 5d7f7e6..0e67470 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -29,6 +29,7 @@ enum { BOOT_DEVICE_I2C, BOOT_DEVICE_BOARD, BOOT_DEVICE_DFU, + BOOT_DEVICE_XIP, BOOT_DEVICE_NONE }; #endif diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index b931c22..ef4fca6 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -13,6 +13,8 @@ #ifndef _U_BOOT_ARM_H_ #define _U_BOOT_ARM_H_ 1 +#ifndef __ASSEMBLY__ + /* for the following variables, see start.S */ extern ulong IRQ_STACK_START; /* top of IRQ stack */ extern ulong FIQ_STACK_START; /* top of FIQ stack */ @@ -45,6 +47,8 @@ ulong get_timer_masked (void); void udelay_masked (unsigned long usec); /* calls to c from vectors.S */ +struct pt_regs; + void bad_mode(void); void do_undefined_instruction(struct pt_regs *pt_regs); void do_software_interrupt(struct pt_regs *pt_regs); @@ -59,4 +63,6 @@ void do_fiq(struct pt_regs *pt_regs); void do_irq(struct pt_regs *pt_regswq); #endif +#endif /* __ASSEMBLY__ */ + #endif /* _U_BOOT_ARM_H_ */ diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h index ca3abd7..ef9196f 100644 --- a/arch/arm/include/asm/u-boot.h +++ b/arch/arm/include/asm/u-boot.h @@ -22,6 +22,7 @@ /* Use the generic board which requires a unified bd_info */ #include <asm-generic/u-boot.h> +#include <asm/u-boot-arm.h> /* For image.h:image_check_target_arch() */ #ifndef CONFIG_ARM64 |