diff options
Diffstat (limited to 'arch/arm/include')
60 files changed, 1975 insertions, 546 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h index 3249437..d8bf872 100644 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -36,7 +36,7 @@ struct module_pin_mux { /* Pad control register offset */ #define PAD_CTRL_BASE 0x800 -#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \ +#define OFFSET(x) (unsigned int) (&((struct pad_signals *)\ (PAD_CTRL_BASE))->x) /* diff --git a/arch/arm/include/asm/arch-armada-xp/config.h b/arch/arm/include/asm/arch-armada-xp/config.h new file mode 100644 index 0000000..00ee775 --- /dev/null +++ b/arch/arm/include/asm/arch-armada-xp/config.h @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2011 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Lei Wen <leiwen@marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This file should be included in board config header file. + * + * It supports common definitions for Armada XP platforms + */ + +#ifndef _ARMADA_XP_CONFIG_H +#define _ARMADA_XP_CONFIG_H + +#include <asm/arch/soc.h> + +#define MV88F78X60 /* for the DDR training bin_hdr code */ + +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* + * By default kwbimage.cfg from board specific folder is used + * If for some board, different configuration file need to be used, + * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file + */ +#ifndef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg +#endif /* CONFIG_SYS_KWD_CONFIG */ + +/* Add target to build it automatically upon "make" */ +#define CONFIG_BUILD_TARGET "u-boot.kwb" + +/* end of 16M scrubbed by training in bootrom */ +#define CONFIG_SYS_INIT_SP_ADDR 0x00FF0000 +#define CONFIG_NR_DRAM_BANKS_MAX 2 + +#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE + +/* + * SPI Flash configuration + */ +#ifdef CONFIG_CMD_SF +#define CONFIG_HARD_SPI 1 +#define CONFIG_KIRKWOOD_SPI 1 +#ifndef CONFIG_ENV_SPI_BUS +# define CONFIG_ENV_SPI_BUS 0 +#endif +#ifndef CONFIG_ENV_SPI_CS +# define CONFIG_ENV_SPI_CS 0 +#endif +#ifndef CONFIG_ENV_SPI_MAX_HZ +# define CONFIG_ENV_SPI_MAX_HZ 50000000 +#endif +#endif + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */ +#define CONFIG_PHYLIB +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ +#endif /* CONFIG_CMD_NET */ + +/* + * I2C related stuff + */ +#ifdef CONFIG_CMD_I2C +#ifndef CONFIG_SYS_I2C_SOFT +#define CONFIG_I2C_MVTWSI +#endif +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#endif /* _ARMADA_XP_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-armada-xp/cpu.h b/arch/arm/include/asm/arch-armada-xp/cpu.h new file mode 100644 index 0000000..6b60c21 --- /dev/null +++ b/arch/arm/include/asm/arch-armada-xp/cpu.h @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ARMADA_XP_CPU_H +#define _ARMADA_XP_CPU_H + +#include <asm/system.h> + +#ifndef __ASSEMBLY__ + +#define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00) +#define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08) + +enum memory_bank { + BANK0, + BANK1, + BANK2, + BANK3 +}; + +enum cpu_winen { + CPU_WIN_DISABLE, + CPU_WIN_ENABLE +}; + +enum cpu_target { + CPU_TARGET_DRAM = 0x0, + CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1, + CPU_TARGET_ETH23 = 0x3, + CPU_TARGET_PCIE02 = 0x4, + CPU_TARGET_ETH01 = 0x7, + CPU_TARGET_PCIE13 = 0x8, + CPU_TARGET_SASRAM = 0x9, + CPU_TARGET_NAND = 0xd, +}; + +enum cpu_attrib { + CPU_ATTR_SASRAM = 0x01, + CPU_ATTR_DRAM_CS0 = 0x0e, + CPU_ATTR_DRAM_CS1 = 0x0d, + CPU_ATTR_DRAM_CS2 = 0x0b, + CPU_ATTR_DRAM_CS3 = 0x07, + CPU_ATTR_NANDFLASH = 0x2f, + CPU_ATTR_SPIFLASH = 0x1e, + CPU_ATTR_BOOTROM = 0x1d, + CPU_ATTR_PCIE_IO = 0xe0, + CPU_ATTR_PCIE_MEM = 0xe8, + CPU_ATTR_DEV_CS0 = 0x3e, + CPU_ATTR_DEV_CS1 = 0x3d, + CPU_ATTR_DEV_CS2 = 0x3b, + CPU_ATTR_DEV_CS3 = 0x37, +}; + +/* + * Default Device Address MAP BAR values + */ +#define DEFADR_PCI_MEM 0x90000000 +#define DEFADR_PCI_IO 0xC0000000 +#define DEFADR_SPIF 0xF4000000 +#define DEFADR_BOOTROM 0xF8000000 + +struct mbus_win { + u32 base; + u32 size; + u8 target; + u8 attr; +}; + +/* + * System registers + * Ref: Datasheet sec:A.28 + */ +struct mvebu_system_registers { + u8 pad1[0x60]; + u32 rstoutn_mask; /* 0x60 */ + u32 sys_soft_rst; /* 0x64 */ +}; + +/* + * GPIO Registers + * Ref: Datasheet sec:A.19 + */ +struct kwgpio_registers { + u32 dout; + u32 oe; + u32 blink_en; + u32 din_pol; + u32 din; + u32 irq_cause; + u32 irq_mask; + u32 irq_level; +}; + +/* + * functions + */ +unsigned int mvebu_sdram_bar(enum memory_bank bank); +unsigned int mvebu_sdram_bs(enum memory_bank bank); +void mvebu_sdram_size_adjust(enum memory_bank bank); +int mvebu_mbus_probe(struct mbus_win windows[], int count); +#endif /* __ASSEMBLY__ */ +#endif /* _ARMADA_XP_CPU_H */ diff --git a/arch/arm/include/asm/arch-armada-xp/soc.h b/arch/arm/include/asm/arch-armada-xp/soc.h new file mode 100644 index 0000000..963e7ac --- /dev/null +++ b/arch/arm/include/asm/arch-armada-xp/soc.h @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com> + * + * Header file for the Marvell's Feroceon CPU core. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_ARMADA_XP_H +#define _ASM_ARCH_ARMADA_XP_H + +#define SOC_MV78460_ID 0x7846 + +/* TCLK Core Clock definition */ +#ifndef CONFIG_SYS_TCLK +#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ +#endif + +/* SOC specific definations */ +#define INTREG_BASE 0xd0000000 +#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080) +#define SOC_REGS_PHY_BASE 0xf1000000 +#define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x) + +#define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504)) +#define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600)) +#define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000)) +#define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000)) +#define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100)) +#define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000)) +#define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100)) +#define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140)) +#define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180)) +#define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200)) +#define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000)) +#define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180)) +#define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300)) +#define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000)) +#define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000)) +#define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000)) +#define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000)) +#define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000)) + +#define SDRAM_MAX_CS 4 +#define SDRAM_ADDR_MASK 0xFF000000 + +/* Armada XP GbE controller has 4 ports */ +#define MAX_MVNETA_DEVS 4 + +/* Kirkwood CPU memory windows */ +#define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA +#define MVCPU_WIN_ENABLE CPU_WIN_ENABLE +#define MVCPU_WIN_DISABLE CPU_WIN_DISABLE + +#endif /* _ASM_ARCH_ARMADA_XP_H */ diff --git a/arch/arm/include/asm/arch-bcm2835/gpio.h b/arch/arm/include/asm/arch-bcm2835/gpio.h index 9a49b6e..db42896 100644 --- a/arch/arm/include/asm/arch-bcm2835/gpio.h +++ b/arch/arm/include/asm/arch-bcm2835/gpio.h @@ -52,4 +52,13 @@ struct bcm2835_gpio_regs { u32 gppudclk[2]; }; +/** + * struct bcm2835_gpio_platdata - GPIO platform description + * + * @base: Base address of GPIO controller + */ +struct bcm2835_gpio_platdata { + unsigned long base; +}; + #endif /* _BCM2835_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h index dded857..61f427d 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/include/asm/arch-bcm2835/mbox.h @@ -119,6 +119,20 @@ struct bcm2835_mbox_tag_hdr { * }; */ +#define BCM2835_MBOX_TAG_GET_MAC_ADDRESS 0x00010003 + +struct bcm2835_mbox_tag_get_mac_address { + struct bcm2835_mbox_tag_hdr tag_hdr; + union { + struct { + } req; + struct { + u8 mac[6]; + u8 pad[2]; + } resp; + } body; +}; + #define BCM2835_MBOX_TAG_GET_ARM_MEMORY 0x00010005 struct bcm2835_mbox_tag_get_arm_mem { diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 8fb5c23..ad2ece6 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -284,7 +284,7 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_Y65, EXYNOS4_GPIO_Y66, EXYNOS4_GPIO_Y67, - EXYNOS4_GPIO_X00 = 896, /* 896 0x380 */ + EXYNOS4_GPIO_X00, /* 256 0x100 */ EXYNOS4_GPIO_X01, EXYNOS4_GPIO_X02, EXYNOS4_GPIO_X03, @@ -292,7 +292,7 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_X05, EXYNOS4_GPIO_X06, EXYNOS4_GPIO_X07, - EXYNOS4_GPIO_X10, /* 904 0x388 */ + EXYNOS4_GPIO_X10, /* 264 0x108 */ EXYNOS4_GPIO_X11, EXYNOS4_GPIO_X12, EXYNOS4_GPIO_X13, @@ -300,7 +300,7 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_X15, EXYNOS4_GPIO_X16, EXYNOS4_GPIO_X17, - EXYNOS4_GPIO_X20, /* 912 0x390 */ + EXYNOS4_GPIO_X20, /* 272 0x110 */ EXYNOS4_GPIO_X21, EXYNOS4_GPIO_X22, EXYNOS4_GPIO_X23, @@ -308,7 +308,7 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_X25, EXYNOS4_GPIO_X26, EXYNOS4_GPIO_X27, - EXYNOS4_GPIO_X30, /* 920 0x398 */ + EXYNOS4_GPIO_X30, /* 280 0x118 */ EXYNOS4_GPIO_X31, EXYNOS4_GPIO_X32, EXYNOS4_GPIO_X33, @@ -318,7 +318,7 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_X37, /* GPIO_PART3_STARTS */ - EXYNOS4_GPIO_MAX_PORT_PART_2, /* 928 0x3A0 */ + EXYNOS4_GPIO_MAX_PORT_PART_2, /* 288 0x120 */ EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2, EXYNOS4_GPIO_Z1, EXYNOS4_GPIO_Z2, @@ -389,7 +389,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_D15, EXYNOS4X12_GPIO_D16, EXYNOS4X12_GPIO_D17, - EXYNOS4X12_GPIO_F00 = 96, /* 96 0x60 */ + EXYNOS4X12_GPIO_F00, /* 56 0x38 */ EXYNOS4X12_GPIO_F01, EXYNOS4X12_GPIO_F02, EXYNOS4X12_GPIO_F03, @@ -397,7 +397,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_F05, EXYNOS4X12_GPIO_F06, EXYNOS4X12_GPIO_F07, - EXYNOS4X12_GPIO_F10, /* 104 0x68 */ + EXYNOS4X12_GPIO_F10, /* 64 0x40 */ EXYNOS4X12_GPIO_F11, EXYNOS4X12_GPIO_F12, EXYNOS4X12_GPIO_F13, @@ -405,7 +405,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_F15, EXYNOS4X12_GPIO_F16, EXYNOS4X12_GPIO_F17, - EXYNOS4X12_GPIO_F20, /* 112 0x70 */ + EXYNOS4X12_GPIO_F20, /* 72 0x48 */ EXYNOS4X12_GPIO_F21, EXYNOS4X12_GPIO_F22, EXYNOS4X12_GPIO_F23, @@ -413,7 +413,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_F25, EXYNOS4X12_GPIO_F26, EXYNOS4X12_GPIO_F27, - EXYNOS4X12_GPIO_F30, /* 120 0x78 */ + EXYNOS4X12_GPIO_F30, /* 80 0x50 */ EXYNOS4X12_GPIO_F31, EXYNOS4X12_GPIO_F32, EXYNOS4X12_GPIO_F33, @@ -421,7 +421,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_F35, EXYNOS4X12_GPIO_F36, EXYNOS4X12_GPIO_F37, - EXYNOS4X12_GPIO_J00 = 144, /* 144 0x90 */ + EXYNOS4X12_GPIO_J00, /* 88 0x58 */ EXYNOS4X12_GPIO_J01, EXYNOS4X12_GPIO_J02, EXYNOS4X12_GPIO_J03, @@ -429,7 +429,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_J05, EXYNOS4X12_GPIO_J06, EXYNOS4X12_GPIO_J07, - EXYNOS4X12_GPIO_J10, /* 152 0x98 */ + EXYNOS4X12_GPIO_J10, /* 96 0x60 */ EXYNOS4X12_GPIO_J11, EXYNOS4X12_GPIO_J12, EXYNOS4X12_GPIO_J13, @@ -439,8 +439,8 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_J17, /* GPIO_PART2_STARTS */ - EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 160 0xA0 */ - EXYNOS4X12_GPIO_K00 = 176, /* 176 0xB0 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */ + EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1, EXYNOS4X12_GPIO_K01, EXYNOS4X12_GPIO_K02, EXYNOS4X12_GPIO_K03, @@ -448,7 +448,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_K05, EXYNOS4X12_GPIO_K06, EXYNOS4X12_GPIO_K07, - EXYNOS4X12_GPIO_K10, /* 184 0xB8 */ + EXYNOS4X12_GPIO_K10, /* 112 0x70 */ EXYNOS4X12_GPIO_K11, EXYNOS4X12_GPIO_K12, EXYNOS4X12_GPIO_K13, @@ -456,7 +456,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_K15, EXYNOS4X12_GPIO_K16, EXYNOS4X12_GPIO_K17, - EXYNOS4X12_GPIO_K20, /* 192 0xC0 */ + EXYNOS4X12_GPIO_K20, /* 120 0x78 */ EXYNOS4X12_GPIO_K21, EXYNOS4X12_GPIO_K22, EXYNOS4X12_GPIO_K23, @@ -464,7 +464,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_K25, EXYNOS4X12_GPIO_K26, EXYNOS4X12_GPIO_K27, - EXYNOS4X12_GPIO_K30, /* 200 0xC8 */ + EXYNOS4X12_GPIO_K30, /* 128 0x80 */ EXYNOS4X12_GPIO_K31, EXYNOS4X12_GPIO_K32, EXYNOS4X12_GPIO_K33, @@ -472,7 +472,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_K35, EXYNOS4X12_GPIO_K36, EXYNOS4X12_GPIO_K37, - EXYNOS4X12_GPIO_L00, /* 208 0xD0 */ + EXYNOS4X12_GPIO_L00, /* 136 0x88 */ EXYNOS4X12_GPIO_L01, EXYNOS4X12_GPIO_L02, EXYNOS4X12_GPIO_L03, @@ -480,7 +480,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_L05, EXYNOS4X12_GPIO_L06, EXYNOS4X12_GPIO_L07, - EXYNOS4X12_GPIO_L10, /* 216 0xD8 */ + EXYNOS4X12_GPIO_L10, /* 144 0x90 */ EXYNOS4X12_GPIO_L11, EXYNOS4X12_GPIO_L12, EXYNOS4X12_GPIO_L13, @@ -488,7 +488,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_L15, EXYNOS4X12_GPIO_L16, EXYNOS4X12_GPIO_L17, - EXYNOS4X12_GPIO_L20, /* 224 0xE0 */ + EXYNOS4X12_GPIO_L20, /* 152 0x98 */ EXYNOS4X12_GPIO_L21, EXYNOS4X12_GPIO_L22, EXYNOS4X12_GPIO_L23, @@ -496,7 +496,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_L25, EXYNOS4X12_GPIO_L26, EXYNOS4X12_GPIO_L27, - EXYNOS4X12_GPIO_Y00, /* 232 0xE8 */ + EXYNOS4X12_GPIO_Y00, /* 160 0xa0 */ EXYNOS4X12_GPIO_Y01, EXYNOS4X12_GPIO_Y02, EXYNOS4X12_GPIO_Y03, @@ -504,7 +504,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y05, EXYNOS4X12_GPIO_Y06, EXYNOS4X12_GPIO_Y07, - EXYNOS4X12_GPIO_Y10, /* 240 0xF0 */ + EXYNOS4X12_GPIO_Y10, /* 168 0xa8 */ EXYNOS4X12_GPIO_Y11, EXYNOS4X12_GPIO_Y12, EXYNOS4X12_GPIO_Y13, @@ -512,7 +512,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y15, EXYNOS4X12_GPIO_Y16, EXYNOS4X12_GPIO_Y17, - EXYNOS4X12_GPIO_Y20, /* 248 0xF8 */ + EXYNOS4X12_GPIO_Y20, /* 176 0xb0 */ EXYNOS4X12_GPIO_Y21, EXYNOS4X12_GPIO_Y22, EXYNOS4X12_GPIO_Y23, @@ -520,7 +520,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y25, EXYNOS4X12_GPIO_Y26, EXYNOS4X12_GPIO_Y27, - EXYNOS4X12_GPIO_Y30, /* 256 0x100 */ + EXYNOS4X12_GPIO_Y30, /* 184 0xb8 */ EXYNOS4X12_GPIO_Y31, EXYNOS4X12_GPIO_Y32, EXYNOS4X12_GPIO_Y33, @@ -528,7 +528,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y35, EXYNOS4X12_GPIO_Y36, EXYNOS4X12_GPIO_Y37, - EXYNOS4X12_GPIO_Y40, /* 264 0x108 */ + EXYNOS4X12_GPIO_Y40, /* 192 0xc0 */ EXYNOS4X12_GPIO_Y41, EXYNOS4X12_GPIO_Y42, EXYNOS4X12_GPIO_Y43, @@ -536,7 +536,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y45, EXYNOS4X12_GPIO_Y46, EXYNOS4X12_GPIO_Y47, - EXYNOS4X12_GPIO_Y50, /* 272 0x110 */ + EXYNOS4X12_GPIO_Y50, /* 200 0xc8 */ EXYNOS4X12_GPIO_Y51, EXYNOS4X12_GPIO_Y52, EXYNOS4X12_GPIO_Y53, @@ -544,7 +544,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y55, EXYNOS4X12_GPIO_Y56, EXYNOS4X12_GPIO_Y57, - EXYNOS4X12_GPIO_Y60, /* 280 0x118 */ + EXYNOS4X12_GPIO_Y60, /* 208 0xd0 */ EXYNOS4X12_GPIO_Y61, EXYNOS4X12_GPIO_Y62, EXYNOS4X12_GPIO_Y63, @@ -552,7 +552,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y65, EXYNOS4X12_GPIO_Y66, EXYNOS4X12_GPIO_Y67, - EXYNOS4X12_GPIO_M00 = 312, /* 312 0xF0 */ + EXYNOS4X12_GPIO_M00, /* 216 0xd8 */ EXYNOS4X12_GPIO_M01, EXYNOS4X12_GPIO_M02, EXYNOS4X12_GPIO_M03, @@ -560,7 +560,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M05, EXYNOS4X12_GPIO_M06, EXYNOS4X12_GPIO_M07, - EXYNOS4X12_GPIO_M10, /* 320 0xF8 */ + EXYNOS4X12_GPIO_M10, /* 224 0xe0 */ EXYNOS4X12_GPIO_M11, EXYNOS4X12_GPIO_M12, EXYNOS4X12_GPIO_M13, @@ -568,7 +568,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M15, EXYNOS4X12_GPIO_M16, EXYNOS4X12_GPIO_M17, - EXYNOS4X12_GPIO_M20, /* 328 0x100 */ + EXYNOS4X12_GPIO_M20, /* 232 0xe8 */ EXYNOS4X12_GPIO_M21, EXYNOS4X12_GPIO_M22, EXYNOS4X12_GPIO_M23, @@ -576,7 +576,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M25, EXYNOS4X12_GPIO_M26, EXYNOS4X12_GPIO_M27, - EXYNOS4X12_GPIO_M30, /* 336 0x108 */ + EXYNOS4X12_GPIO_M30, /* 240 0xf0 */ EXYNOS4X12_GPIO_M31, EXYNOS4X12_GPIO_M32, EXYNOS4X12_GPIO_M33, @@ -584,7 +584,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M35, EXYNOS4X12_GPIO_M36, EXYNOS4X12_GPIO_M37, - EXYNOS4X12_GPIO_M40, /* 344 0x110 */ + EXYNOS4X12_GPIO_M40, /* 248 0xf8 */ EXYNOS4X12_GPIO_M41, EXYNOS4X12_GPIO_M42, EXYNOS4X12_GPIO_M43, @@ -592,7 +592,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M45, EXYNOS4X12_GPIO_M46, EXYNOS4X12_GPIO_M47, - EXYNOS4X12_GPIO_X00 = 928, /* 928 0x3A0 */ + EXYNOS4X12_GPIO_X00, /* 256 0x100 */ EXYNOS4X12_GPIO_X01, EXYNOS4X12_GPIO_X02, EXYNOS4X12_GPIO_X03, @@ -600,7 +600,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_X05, EXYNOS4X12_GPIO_X06, EXYNOS4X12_GPIO_X07, - EXYNOS4X12_GPIO_X10, /* 936 0x3A8 */ + EXYNOS4X12_GPIO_X10, /* 264 0x108 */ EXYNOS4X12_GPIO_X11, EXYNOS4X12_GPIO_X12, EXYNOS4X12_GPIO_X13, @@ -608,7 +608,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_X15, EXYNOS4X12_GPIO_X16, EXYNOS4X12_GPIO_X17, - EXYNOS4X12_GPIO_X20, /* 944 0x3B0 */ + EXYNOS4X12_GPIO_X20, /* 272 0x110 */ EXYNOS4X12_GPIO_X21, EXYNOS4X12_GPIO_X22, EXYNOS4X12_GPIO_X23, @@ -616,7 +616,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_X25, EXYNOS4X12_GPIO_X26, EXYNOS4X12_GPIO_X27, - EXYNOS4X12_GPIO_X30, /* 952 0x3B8 */ + EXYNOS4X12_GPIO_X30, /* 280 0x118 */ EXYNOS4X12_GPIO_X31, EXYNOS4X12_GPIO_X32, EXYNOS4X12_GPIO_X33, @@ -626,7 +626,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_X37, /* GPIO_PART3_STARTS */ - EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 960 0x3C0 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */ EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2, EXYNOS4X12_GPIO_Z1, EXYNOS4X12_GPIO_Z2, @@ -637,7 +637,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Z7, /* GPIO_PART4_STARTS */ - EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 968 0x3C8 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */ EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3, EXYNOS4X12_GPIO_V01, EXYNOS4X12_GPIO_V02, @@ -646,7 +646,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_V05, EXYNOS4X12_GPIO_V06, EXYNOS4X12_GPIO_V07, - EXYNOS4X12_GPIO_V10, /* 976 0x3D0 */ + EXYNOS4X12_GPIO_V10, /* 304 0x130 */ EXYNOS4X12_GPIO_V11, EXYNOS4X12_GPIO_V12, EXYNOS4X12_GPIO_V13, @@ -654,7 +654,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_V15, EXYNOS4X12_GPIO_V16, EXYNOS4X12_GPIO_V17, - EXYNOS4X12_GPIO_V20 = 992, /* 992 0x3E0 */ + EXYNOS4X12_GPIO_V20, /* 312 0x138 */ EXYNOS4X12_GPIO_V21, EXYNOS4X12_GPIO_V22, EXYNOS4X12_GPIO_V23, @@ -662,7 +662,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_V25, EXYNOS4X12_GPIO_V26, EXYNOS4X12_GPIO_V27, - EXYNOS4X12_GPIO_V30 = 1000, /* 1000 0x3E8 */ + EXYNOS4X12_GPIO_V30, /* 320 0x140 */ EXYNOS4X12_GPIO_V31, EXYNOS4X12_GPIO_V32, EXYNOS4X12_GPIO_V33, @@ -670,7 +670,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_V35, EXYNOS4X12_GPIO_V36, EXYNOS4X12_GPIO_V37, - EXYNOS4X12_GPIO_V40 = 1016, /* 1016 0x3F8 */ + EXYNOS4X12_GPIO_V40, /* 328 0x148 */ EXYNOS4X12_GPIO_V41, EXYNOS4X12_GPIO_V42, EXYNOS4X12_GPIO_V43, @@ -1504,12 +1504,7 @@ static const struct gpio_name_num_table exynos5420_gpio_table[] = { void gpio_cfg_pin(int gpio, int cfg); void gpio_set_pull(int gpio, int mode); void gpio_set_drv(int gpio, int mode); -int gpio_direction_input(unsigned gpio); -int gpio_direction_output(unsigned gpio, int value); -int gpio_set_value(unsigned gpio, int value); -int gpio_get_value(unsigned gpio); void gpio_set_rate(int gpio, int mode); -struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio); int s5p_gpio_get_pin(unsigned gpio); #endif diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h index df33a78..d013b83 100644 --- a/arch/arm/include/asm/arch-keystone/clock-k2e.h +++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h @@ -25,27 +25,28 @@ enum ext_clk_e { extern unsigned int external_clk[ext_clk_count]; -enum clk_e { - core_pll_clk, - pass_pll_clk, - ddr3_pll_clk, - sys_clk0_clk, - sys_clk0_1_clk, - sys_clk0_2_clk, - sys_clk0_3_clk, - sys_clk0_4_clk, - sys_clk0_6_clk, - sys_clk0_8_clk, - sys_clk0_12_clk, - sys_clk0_24_clk, - sys_clk1_clk, - sys_clk1_3_clk, - sys_clk1_4_clk, - sys_clk1_6_clk, - sys_clk1_12_clk, - sys_clk2_clk, - sys_clk3_clk -}; +#define CLK_LIST(CLK)\ + CLK(0, core_pll_clk)\ + CLK(1, pass_pll_clk)\ + CLK(2, ddr3_pll_clk)\ + CLK(3, sys_clk0_clk)\ + CLK(4, sys_clk0_1_clk)\ + CLK(5, sys_clk0_2_clk)\ + CLK(6, sys_clk0_3_clk)\ + CLK(7, sys_clk0_4_clk)\ + CLK(8, sys_clk0_6_clk)\ + CLK(9, sys_clk0_8_clk)\ + CLK(10, sys_clk0_12_clk)\ + CLK(11, sys_clk0_24_clk)\ + CLK(12, sys_clk1_clk)\ + CLK(13, sys_clk1_3_clk)\ + CLK(14, sys_clk1_4_clk)\ + CLK(15, sys_clk1_6_clk)\ + CLK(16, sys_clk1_12_clk)\ + CLK(17, sys_clk2_clk)\ + CLK(18, sys_clk3_clk) + +#define PLLSET_CMD_LIST "<pa|ddr3>" #define KS2_CLK1_6 sys_clk0_6_clk diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h index bdb869b..f28d5f0 100644 --- a/arch/arm/include/asm/arch-keystone/clock-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h @@ -28,29 +28,30 @@ enum ext_clk_e { extern unsigned int external_clk[ext_clk_count]; -enum clk_e { - core_pll_clk, - pass_pll_clk, - tetris_pll_clk, - ddr3a_pll_clk, - ddr3b_pll_clk, - sys_clk0_clk, - sys_clk0_1_clk, - sys_clk0_2_clk, - sys_clk0_3_clk, - sys_clk0_4_clk, - sys_clk0_6_clk, - sys_clk0_8_clk, - sys_clk0_12_clk, - sys_clk0_24_clk, - sys_clk1_clk, - sys_clk1_3_clk, - sys_clk1_4_clk, - sys_clk1_6_clk, - sys_clk1_12_clk, - sys_clk2_clk, - sys_clk3_clk -}; +#define CLK_LIST(CLK)\ + CLK(0, core_pll_clk)\ + CLK(1, pass_pll_clk)\ + CLK(2, tetris_pll_clk)\ + CLK(3, ddr3a_pll_clk)\ + CLK(4, ddr3b_pll_clk)\ + CLK(5, sys_clk0_clk)\ + CLK(6, sys_clk0_1_clk)\ + CLK(7, sys_clk0_2_clk)\ + CLK(8, sys_clk0_3_clk)\ + CLK(9, sys_clk0_4_clk)\ + CLK(10, sys_clk0_6_clk)\ + CLK(11, sys_clk0_8_clk)\ + CLK(12, sys_clk0_12_clk)\ + CLK(13, sys_clk0_24_clk)\ + CLK(14, sys_clk1_clk)\ + CLK(15, sys_clk1_3_clk)\ + CLK(16, sys_clk1_4_clk)\ + CLK(17, sys_clk1_6_clk)\ + CLK(18, sys_clk1_12_clk)\ + CLK(19, sys_clk2_clk)\ + CLK(20, sys_clk3_clk) + +#define PLLSET_CMD_LIST "<pa|arm|ddr3a|ddr3b>" #define KS2_CLK1_6 sys_clk0_6_clk diff --git a/arch/arm/include/asm/arch-keystone/clock-k2l.h b/arch/arm/include/asm/arch-keystone/clock-k2l.h new file mode 100644 index 0000000..bb9a5c4 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/clock-k2l.h @@ -0,0 +1,95 @@ +/* + * K2L: Clock management APIs + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_K2L_H +#define __ASM_ARCH_CLOCK_K2L_H + +enum ext_clk_e { + sys_clk, + alt_core_clk, + pa_clk, + tetris_clk, + ddr3_clk, + pcie_clk, + sgmii_clk, + usb_clk, + rp1_clk, + ext_clk_count /* number of external clocks */ +}; + +extern unsigned int external_clk[ext_clk_count]; + +#define CLK_LIST(CLK)\ + CLK(0, core_pll_clk)\ + CLK(1, pass_pll_clk)\ + CLK(2, tetris_pll_clk)\ + CLK(3, ddr3_pll_clk)\ + CLK(4, sys_clk0_clk)\ + CLK(5, sys_clk0_1_clk)\ + CLK(6, sys_clk0_2_clk)\ + CLK(7, sys_clk0_3_clk)\ + CLK(8, sys_clk0_4_clk)\ + CLK(9, sys_clk0_6_clk)\ + CLK(10, sys_clk0_8_clk)\ + CLK(11, sys_clk0_12_clk)\ + CLK(12, sys_clk0_24_clk)\ + CLK(13, sys_clk1_clk)\ + CLK(14, sys_clk1_3_clk)\ + CLK(15, sys_clk1_4_clk)\ + CLK(16, sys_clk1_6_clk)\ + CLK(17, sys_clk1_12_clk)\ + CLK(18, sys_clk2_clk)\ + CLK(19, sys_clk3_clk)\ + +#define PLLSET_CMD_LIST "<pa|arm|ddr3>" + +#define KS2_CLK1_6 sys_clk0_6_clk + +/* PLL identifiers */ +enum pll_type_e { + CORE_PLL, + PASS_PLL, + TETRIS_PLL, + DDR3_PLL, +}; + +enum { + SPD800, + SPD1000, + SPD1200, + SPD1350, + SPD1400, + SPD_RSV +}; + +#define CORE_PLL_799 {CORE_PLL, 13, 1, 2} +#define CORE_PLL_983 {CORE_PLL, 16, 1, 2} +#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2} +#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2} +#define CORE_PLL_1198 {CORE_PLL, 39, 2, 2} +#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2} +#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2} +#define PASS_PLL_983 {PASS_PLL, 16, 1, 2} +#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2} +#define TETRIS_PLL_491 {TETRIS_PLL, 8, 1, 2} +#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2} +#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2} +#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2} +#define TETRIS_PLL_1000 {TETRIS_PLL, 114, 7, 2} +#define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2} +#define TETRIS_PLL_1198 {TETRIS_PLL, 39, 2, 2} +#define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2} +#define TETRIS_PLL_1352 {TETRIS_PLL, 22, 1, 2} +#define TETRIS_PLL_1401 {TETRIS_PLL, 114, 5, 2} +#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} +#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} +#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} +#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6} + +#endif diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h index dae000e..9f6cfb2 100644 --- a/arch/arm/include/asm/arch-keystone/clock.h +++ b/arch/arm/include/asm/arch-keystone/clock.h @@ -20,10 +20,22 @@ #include <asm/arch/clock-k2e.h> #endif +#ifdef CONFIG_SOC_K2L +#include <asm/arch/clock-k2l.h> +#endif + #define MAIN_PLL CORE_PLL #include <asm/types.h> +#define GENERATE_ENUM(NUM, ENUM) ENUM = NUM, +#define GENERATE_INDX_STR(NUM, STRING) #NUM"\t- "#STRING"\n" +#define CLOCK_INDEXES_LIST CLK_LIST(GENERATE_INDX_STR) + +enum clk_e { + CLK_LIST(GENERATE_ENUM) +}; + struct keystone_pll_regs { u32 reg0; u32 reg1; @@ -46,6 +58,7 @@ void init_pll(const struct pll_init_data *data); unsigned long clk_get_rate(unsigned int clk); unsigned long clk_round_rate(unsigned int clk, unsigned long hz); int clk_set_rate(unsigned int clk, unsigned long hz); +void pass_pll_pa_clk_enable(void); int get_max_dev_speed(void); int get_max_arm_speed(void); diff --git a/arch/arm/include/asm/arch-keystone/ddr3.h b/arch/arm/include/asm/arch-keystone/ddr3.h index 6bf35d3..b044d6f 100644 --- a/arch/arm/include/asm/arch-keystone/ddr3.h +++ b/arch/arm/include/asm/arch-keystone/ddr3.h @@ -49,8 +49,14 @@ struct ddr3_emif_config { }; void ddr3_init(void); +int ddr3_get_size(void); void ddr3_reset_ddrphy(void); +void ddr3_init_ecc(u32 base); +void ddr3_disable_ecc(u32 base); +void ddr3_check_ecc_int(u32 base); +int ddr3_ecc_support_rmw(u32 base); void ddr3_err_reset_workaround(void); +void ddr3_enable_ecc(u32 base, int test); void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); diff --git a/arch/arm/include/asm/arch-keystone/emac_defs.h b/arch/arm/include/asm/arch-keystone/emac_defs.h deleted file mode 100644 index 9cd8925..0000000 --- a/arch/arm/include/asm/arch-keystone/emac_defs.h +++ /dev/null @@ -1,237 +0,0 @@ -/* - * emac definitions for keystone2 devices - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _EMAC_DEFS_H_ -#define _EMAC_DEFS_H_ - -#include <asm/arch/hardware.h> -#include <asm/io.h> - -#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900) -#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300) -#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100) - -#define KEYSTONE2_EMAC_GIG_ENABLE - -#define MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110) - -#ifdef CONFIG_SOC_K2HK -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk)) -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */ -#endif - -/* MII Status Register */ -#define MII_STATUS_REG 1 -#define MII_STATUS_LINK_MASK (0x4) - -/* Marvell 88E1111 PHY ID */ -#define PHY_MARVELL_88E1111 (0x01410cc0) - -#define MDIO_CONTROL_IDLE (0x80000000) -#define MDIO_CONTROL_ENABLE (0x40000000) -#define MDIO_CONTROL_FAULT_ENABLE (0x40000) -#define MDIO_CONTROL_FAULT (0x80000) -#define MDIO_USERACCESS0_GO (0x80000000) -#define MDIO_USERACCESS0_WRITE_READ (0x0) -#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) -#define MDIO_USERACCESS0_ACK (0x20000000) - -#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) -#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) -#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) -#define EMAC_MACCONTROL_GIGFORCE (1 << 17) -#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) - -#define EMAC_MIN_ETHERNET_PKT_SIZE 60 - -struct mac_sl_cfg { - u_int32_t max_rx_len; /* Maximum receive packet length. */ - u_int32_t ctl; /* Control bitfield */ -}; - -/* - * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t - */ -#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES (1 << 24) -#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES (1 << 23) -#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES (1 << 22) -#define GMACSL_RX_ENABLE_EXT_CTL (1 << 18) -#define GMACSL_RX_ENABLE_GIG_FORCE (1 << 17) -#define GMACSL_RX_ENABLE_IFCTL_B (1 << 16) -#define GMACSL_RX_ENABLE_IFCTL_A (1 << 15) -#define GMACSL_RX_ENABLE_CMD_IDLE (1 << 11) -#define GMACSL_TX_ENABLE_SHORT_GAP (1 << 10) -#define GMACSL_ENABLE_GIG_MODE (1 << 7) -#define GMACSL_TX_ENABLE_PACE (1 << 6) -#define GMACSL_ENABLE (1 << 5) -#define GMACSL_TX_ENABLE_FLOW_CTL (1 << 4) -#define GMACSL_RX_ENABLE_FLOW_CTL (1 << 3) -#define GMACSL_ENABLE_LOOPBACK (1 << 1) -#define GMACSL_ENABLE_FULL_DUPLEX (1 << 0) - -/* - * DEFINTITION: function return values - */ -#define GMACSL_RET_OK 0 -#define GMACSL_RET_INVALID_PORT -1 -#define GMACSL_RET_WARN_RESET_INCOMPLETE -2 -#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3 -#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4 - -/* Register offsets */ -#define CPGMACSL_REG_ID 0x00 -#define CPGMACSL_REG_CTL 0x04 -#define CPGMACSL_REG_STATUS 0x08 -#define CPGMACSL_REG_RESET 0x0c -#define CPGMACSL_REG_MAXLEN 0x10 -#define CPGMACSL_REG_BOFF 0x14 -#define CPGMACSL_REG_RX_PAUSE 0x18 -#define CPGMACSL_REG_TX_PAURSE 0x1c -#define CPGMACSL_REG_EM_CTL 0x20 -#define CPGMACSL_REG_PRI 0x24 - -/* Soft reset register values */ -#define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0) -#define CPGMAC_REG_RESET_VAL_RESET (1 << 0) - -/* Maxlen register values */ -#define CPGMAC_REG_MAXLEN_LEN 0x3fff - -/* Control bitfields */ -#define CPSW_CTL_P2_PASS_PRI_TAGGED (1 << 5) -#define CPSW_CTL_P1_PASS_PRI_TAGGED (1 << 4) -#define CPSW_CTL_P0_PASS_PRI_TAGGED (1 << 3) -#define CPSW_CTL_P0_ENABLE (1 << 2) -#define CPSW_CTL_VLAN_AWARE (1 << 1) -#define CPSW_CTL_FIFO_LOOPBACK (1 << 0) - -#define DEVICE_CPSW_NUM_PORTS 5 /* 5 switch ports */ -#define DEVICE_CPSW_BASE (0x02090800) -#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */ -#define SWITCH_MAX_PKT_SIZE 9000 - -/* Register offsets */ -#define CPSW_REG_CTL 0x004 -#define CPSW_REG_STAT_PORT_EN 0x00c -#define CPSW_REG_MAXLEN 0x040 -#define CPSW_REG_ALE_CONTROL 0x608 -#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4) - -/* Register values */ -#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf -#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000) -#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010) -#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3 - -#define SGMII_REG_STATUS_LOCK BIT(4) -#define SGMII_REG_STATUS_LINK BIT(0) -#define SGMII_REG_STATUS_AUTONEG BIT(2) -#define SGMII_REG_CONTROL_AUTONEG BIT(0) -#define SGMII_REG_CONTROL_MASTER BIT(5) -#define SGMII_REG_MR_ADV_ENABLE BIT(0) -#define SGMII_REG_MR_ADV_LINK BIT(15) -#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12) -#define SGMII_REG_MR_ADV_GIG_MODE BIT(11) - -#define SGMII_LINK_MAC_MAC_AUTONEG 0 -#define SGMII_LINK_MAC_PHY 1 -#define SGMII_LINK_MAC_MAC_FORCED 2 -#define SGMII_LINK_MAC_FIBER 3 -#define SGMII_LINK_MAC_PHY_FORCED 4 - -#define TARGET_SGMII_BASE KS2_PASS_BASE + 0x00090100 -#define TARGET_SGMII_BASE_ADDRESSES {KS2_PASS_BASE + 0x00090100, \ - KS2_PASS_BASE + 0x00090200, \ - KS2_PASS_BASE + 0x00090400, \ - KS2_PASS_BASE + 0x00090500} - -#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100)) - -/* - * SGMII registers - */ -#define SGMII_IDVER_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000) -#define SGMII_SRESET_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004) -#define SGMII_CTL_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010) -#define SGMII_STATUS_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014) -#define SGMII_MRADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018) -#define SGMII_LPADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020) -#define SGMII_TXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030) -#define SGMII_RXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034) -#define SGMII_AUXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038) - -#define DEVICE_EMACSL_BASE(x) (KS2_PASS_BASE + 0x00090900 + (x) * 0x040) -#define DEVICE_N_GMACSL_PORTS 4 -#define DEVICE_EMACSL_RESET_POLL_COUNT 100 - -#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604) - -#ifdef CONFIG_SOC_K2HK -#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI 0x06060606 -#endif - -#define hw_config_streaming_switch() \ - writel(DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI,\ - DEVICE_PSTREAM_CFG_REG_ADDR); - -/* EMAC MDIO Registers Structure */ -struct mdio_regs { - dv_reg version; - dv_reg control; - dv_reg alive; - dv_reg link; - dv_reg linkintraw; - dv_reg linkintmasked; - u_int8_t rsvd0[8]; - dv_reg userintraw; - dv_reg userintmasked; - dv_reg userintmaskset; - dv_reg userintmaskclear; - u_int8_t rsvd1[80]; - dv_reg useraccess0; - dv_reg userphysel0; - dv_reg useraccess1; - dv_reg userphysel1; -}; - -/* Ethernet MAC Registers Structure */ -struct emac_regs { - dv_reg idver; - dv_reg maccontrol; - dv_reg macstatus; - dv_reg soft_reset; - dv_reg rx_maxlen; - u32 rsvd0; - dv_reg rx_pause; - dv_reg tx_pause; - dv_reg emcontrol; - dv_reg pri_map; - u32 rsvd1[6]; -}; - -#define SGMII_ACCESS(port, reg) \ - *((volatile unsigned int *)(sgmiis[port] + reg)) - -struct eth_priv_t { - char int_name[32]; - int rx_flow; - int phy_addr; - int slave_port; - int sgmii_link_type; -}; - -extern struct eth_priv_t eth_priv_cfg[]; - -int keystone2_emac_initialize(struct eth_priv_t *eth_priv); -void sgmii_serdes_setup_156p25mhz(void); -void sgmii_serdes_shutdown(void); - -#endif /* _EMAC_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h index 62172a4..9512756 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h @@ -34,11 +34,34 @@ #define KS2_LPSC_PCIE_1 27 #define KS2_LPSC_XGE 50 +/* MSMC */ +#define KS2_MSMC_SEGMENT_PCIE1 13 + /* Chip Interrupt Controller */ #define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ #define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ +/* SGMII SerDes */ +#define KS2_SGMII_SERDES2_BASE 0x02324000 +#define KS2_LANES_PER_SGMII_SERDES 4 + /* Number of DSP cores */ #define KS2_NUM_DSPS 1 +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_CTRL_BASE 0x24186000 +#define KS2_NETCP_PDMA_TX_BASE 0x24187000 +#define KS2_NETCP_PDMA_TX_CH_NUM 21 +#define KS2_NETCP_PDMA_RX_BASE 0x24188000 +#define KS2_NETCP_PDMA_RX_CH_NUM 91 +#define KS2_NETCP_PDMA_SCHED_BASE 0x24186100 +#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x24189000 +#define KS2_NETCP_PDMA_RX_FLOW_NUM 96 +#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001 +#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002 +#define KS2_NETCP_PDMA_TX_SND_QUEUE 896 + +/* NETCP */ +#define KS2_NETCP_BASE 0x24000000 + #endif diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index eb132f7..5a9ea4f 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -10,8 +10,6 @@ #ifndef __ASM_ARCH_HARDWARE_K2HK_H #define __ASM_ARCH_HARDWARE_K2HK_H -#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) - #define KS2_ARM_PLL_EN BIT(13) /* PA SS Registers */ @@ -81,7 +79,30 @@ #define KS2_DDR3B_EMIF_DATA_BASE 0x60000000 #define KS2_DDR3B_DDRPHYC 0x02328000 +#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 /* DDR3 ECC system irq number */ +#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D /* DDR3 ECC int mapped to CIC2 + channel 29 */ + +/* SGMII SerDes */ +#define KS2_LANES_PER_SGMII_SERDES 4 + /* Number of DSP cores */ #define KS2_NUM_DSPS 8 +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_CTRL_BASE 0x02004000 +#define KS2_NETCP_PDMA_TX_BASE 0x02004400 +#define KS2_NETCP_PDMA_TX_CH_NUM 9 +#define KS2_NETCP_PDMA_RX_BASE 0x02004800 +#define KS2_NETCP_PDMA_RX_CH_NUM 26 +#define KS2_NETCP_PDMA_SCHED_BASE 0x02004c00 +#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x02005000 +#define KS2_NETCP_PDMA_RX_FLOW_NUM 32 +#define KS2_NETCP_PDMA_RX_FREE_QUEUE 4001 +#define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002 +#define KS2_NETCP_PDMA_TX_SND_QUEUE 648 + +/* NETCP */ +#define KS2_NETCP_BASE 0x02000000 + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2l.h b/arch/arm/include/asm/arch-keystone/hardware-k2l.h new file mode 100644 index 0000000..05532ad --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/hardware-k2l.h @@ -0,0 +1,101 @@ +/* + * K2L: SoC definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_HARDWARE_K2L_H +#define __ASM_ARCH_HARDWARE_K2L_H + +#define KS2_ARM_PLL_EN BIT(13) + +/* PA SS Registers */ +#define KS2_PASS_BASE 0x26000000 + +/* Power and Sleep Controller (PSC) Domains */ +#define KS2_LPSC_MOD 0 +#define KS2_LPSC_DFE_IQN_SYS 1 +#define KS2_LPSC_USB 2 +#define KS2_LPSC_EMIF25_SPI 3 +#define KS2_LPSC_TSIP 4 +#define KS2_LPSC_DEBUGSS_TRC 5 +#define KS2_LPSC_TETB_TRC 6 +#define KS2_LPSC_PKTPROC 7 +#define KS2_LPSC_PA KS2_LPSC_PKTPROC +#define KS2_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC KS2_LPSC_SGMII +#define KS2_LPSC_CRYPTO 9 +#define KS2_LPSC_PCIE0 10 +#define KS2_LPSC_PCIE1 11 +#define KS2_LPSC_JESD_MISC 12 +#define KS2_LPSC_CHIP_SRSS 13 +#define KS2_LPSC_MSMC 14 +#define KS2_LPSC_GEM_1 16 +#define KS2_LPSC_GEM_2 17 +#define KS2_LPSC_GEM_3 18 +#define KS2_LPSC_EMIF4F_DDR3 23 +#define KS2_LPSC_TAC 25 +#define KS2_LPSC_RAC 26 +#define KS2_LPSC_DDUC4X_CFR2X_BB 27 +#define KS2_LPSC_FFTC_A 28 +#define KS2_LPSC_OSR 34 +#define KS2_LPSC_TCP3D_0 35 +#define KS2_LPSC_TCP3D_1 37 +#define KS2_LPSC_VCP2X4_A 39 +#define KS2_LPSC_VCP2X4_B 40 +#define KS2_LPSC_VCP2X4_C 41 +#define KS2_LPSC_VCP2X4_D 42 +#define KS2_LPSC_BCP 47 +#define KS2_LPSC_DPD4X 48 +#define KS2_LPSC_FFTC_B 49 +#define KS2_LPSC_IQN_AIL 50 + +/* MSMC */ +#define KS2_MSMC_SEGMENT_PCIE1 14 + +/* Chip Interrupt Controller */ +#define KS2_CIC2_DDR3_ECC_IRQ_NUM 0x0D3 +#define KS2_CIC2_DDR3_ECC_CHAN_NUM 0x01D + +/* OSR */ +#define KS2_OSR_DATA_BASE 0x70000000 /* OSR data base */ +#define KS2_OSR_CFG_BASE 0x02348c00 /* OSR config base */ +#define KS2_OSR_ECC_VEC 0x08 /* ECC Vector reg */ +#define KS2_OSR_ECC_CTRL 0x14 /* ECC control reg */ + +/* OSR ECC Vector register */ +#define KS2_OSR_ECC_VEC_TRIG_RD BIT(15) /* trigger a read op */ +#define KS2_OSR_ECC_VEC_RD_DONE BIT(24) /* read complete */ + +#define KS2_OSR_ECC_VEC_RAM_ID_SH 0 /* RAM ID shift */ +#define KS2_OSR_ECC_VEC_RD_ADDR_SH 16 /* read address shift */ + +/* OSR ECC control register */ +#define KS2_OSR_ECC_CTRL_EN BIT(0) /* ECC enable bit */ +#define KS2_OSR_ECC_CTRL_CHK BIT(1) /* ECC check bit */ +#define KS2_OSR_ECC_CTRL_RMW BIT(2) /* ECC check bit */ + +/* Number of OSR RAM banks */ +#define KS2_OSR_NUM_RAM_BANKS 4 + +/* OSR memory size */ +#define KS2_OSR_SIZE 0x100000 + +/* Number of DSP cores */ +#define KS2_NUM_DSPS 4 + +/* NETCP pktdma */ +#define KS2_NETCP_PDMA_CTRL_BASE 0x26186000 +#define KS2_NETCP_PDMA_TX_BASE 0x26187000 +#define KS2_NETCP_PDMA_TX_CH_NUM 21 +#define KS2_NETCP_PDMA_RX_BASE 0x26188000 +#define KS2_NETCP_PDMA_RX_CH_NUM 91 +#define KS2_NETCP_PDMA_SCHED_BASE 0x26186100 +#define KS2_NETCP_PDMA_RX_FLOW_BASE 0x26189000 +#define KS2_NETCP_PDMA_RX_FLOW_NUM 96 +#define KS2_NETCP_PDMA_TX_SND_QUEUE 896 + +#endif /* __ASM_ARCH_HARDWARE_K2L_H */ diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index 76e6441..c6a54d8 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -87,6 +87,52 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_DDR3_PLLCTRL_PHY_RESET 0x80000000 +/* DDR3 ECC */ +#define KS2_DDR3_ECC_INT_STATUS_OFFSET 0x0AC +#define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET 0x0B4 +#define KS2_DDR3_ECC_CTRL_OFFSET 0x110 +#define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET 0x114 +#define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET 0x130 +#define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET 0x13C + +/* DDR3 ECC Interrupt Status register */ +#define KS2_DDR3_1B_ECC_ERR_SYS BIT(5) +#define KS2_DDR3_2B_ECC_ERR_SYS BIT(4) +#define KS2_DDR3_WR_ECC_ERR_SYS BIT(3) + +/* DDR3 ECC Control register */ +#define KS2_DDR3_ECC_EN BIT(31) +#define KS2_DDR3_ECC_ADDR_RNG_PROT BIT(30) +#define KS2_DDR3_ECC_VERIFY_EN BIT(29) +#define KS2_DDR3_ECC_RMW_EN BIT(28) +#define KS2_DDR3_ECC_ADDR_RNG_1_EN BIT(0) + +#define KS2_DDR3_ECC_ENABLE (KS2_DDR3_ECC_EN | \ + KS2_DDR3_ECC_ADDR_RNG_PROT | \ + KS2_DDR3_ECC_VERIFY_EN) + +/* EDMA */ +#define KS2_EDMA0_BASE 0x02700000 + +/* EDMA3 register offsets */ +#define KS2_EDMA_QCHMAP0 0x0200 +#define KS2_EDMA_IPR 0x1068 +#define KS2_EDMA_ICR 0x1070 +#define KS2_EDMA_QEECR 0x1088 +#define KS2_EDMA_QEESR 0x108c +#define KS2_EDMA_PARAM_1(x) (0x4020 + (4 * x)) + +/* Chip Interrupt Controller */ +#define KS2_CIC2_BASE 0x02608000 + +/* Chip Interrupt Controller register offsets */ +#define KS2_CIC_CTRL 0x04 +#define KS2_CIC_HOST_CTRL 0x0C +#define KS2_CIC_GLOBAL_ENABLE 0x10 +#define KS2_CIC_SYS_ENABLE_IDX_SET 0x28 +#define KS2_CIC_HOST_ENABLE_IDX_SET 0x34 +#define KS2_CIC_CHAN_MAP(n) (0x0400 + (n << 2)) + #define KS2_UART0_BASE 0x02530c00 #define KS2_UART1_BASE 0x02531000 @@ -140,19 +186,51 @@ typedef volatile unsigned int *dv_reg_p; /* Flag from ks2_debug options to check if DSPs need to stay ON */ #define DBG_LEAVE_DSPS_ON 0x1 +/* MSMC control */ +#define KS2_MSMC_CTRL_BASE 0x0bc00000 +#define KS2_MSMC_DATA_BASE 0x0c000000 +#define KS2_MSMC_SEGMENT_TETRIS 8 +#define KS2_MSMC_SEGMENT_NETCP 9 +#define KS2_MSMC_SEGMENT_QM_PDSP 10 +#define KS2_MSMC_SEGMENT_PCIE0 11 + +/* MSMC segment size shift bits */ +#define KS2_MSMC_SEG_SIZE_SHIFT 12 +#define KS2_MSMC_MAP_SEG_NUM (2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT)) +#define KS2_MSMC_DST_SEG_BASE (CONFIG_SYS_LPAE_SDRAM_BASE >> \ + KS2_MSMC_SEG_SIZE_SHIFT) + /* Device speed */ #define KS2_REV1_DEVSPEED (KS2_DEVICE_STATE_CTRL_BASE + 0xc98) #define KS2_EFUSE_BOOTROM (KS2_DEVICE_STATE_CTRL_BASE + 0xc90) +#define KS2_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) /* Queue manager */ -#define KS2_QM_MANAGER_BASE 0x02a02000 +#define KS2_QM_BASE_ADDRESS 0x23a80000 +#define KS2_QM_CONF_BASE 0x02a02000 #define KS2_QM_DESC_SETUP_BASE 0x02a03000 -#define KS2_QM_MANAGER_QUEUES_BASEi 0x02a80000 +#define KS2_QM_STATUS_RAM_BASE 0x02a06000 +#define KS2_QM_INTD_CONF_BASE 0x02a0c000 +#define KS2_QM_PDSP1_CMD_BASE 0x02a20000 +#define KS2_QM_PDSP1_CTRL_BASE 0x02a0f000 +#define KS2_QM_PDSP1_IRAM_BASE 0x02a10000 +#define KS2_QM_MANAGER_QUEUES_BASE 0x02a80000 #define KS2_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 #define KS2_QM_QUEUE_STATUS_BASE 0x02a40000 +#define KS2_QM_LINK_RAM_BASE 0x00100000 +#define KS2_QM_REGION_NUM 64 +#define KS2_QM_QPOOL_NUM 4000 -/* MSMC control */ -#define KS2_MSMC_CTRL_BASE 0x0bc00000 +/* USB */ +#define KS2_USB_SS_BASE 0x02680000 +#define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x10000) +#define KS2_DEV_USB_PHY_BASE 0x02620738 +#define KS2_USB_PHY_CFG_BASE 0x02630000 + +#define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110) + +/* SGMII SerDes */ +#define KS2_SGMII_SERDES_BASE 0x0232a000 #ifdef CONFIG_SOC_K2HK #include <asm/arch/hardware-k2hk.h> @@ -162,6 +240,10 @@ typedef volatile unsigned int *dv_reg_p; #include <asm/arch/hardware-k2e.h> #endif +#ifdef CONFIG_SOC_K2L +#include <asm/arch/hardware-k2l.h> +#endif + #ifndef __ASSEMBLY__ static inline int cpu_is_k2hk(void) { @@ -179,6 +261,14 @@ static inline int cpu_is_k2e(void) return (part_no == 0xb9a6) ? 1 : 0; } +static inline int cpu_is_k2l(void) +{ + unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); + unsigned int part_no = (jtag_id >> 12) & 0xffff; + + return (part_no == 0xb9a7) ? 1 : 0; +} + static inline int cpu_revision(void) { unsigned int jtag_id = __raw_readl(KS2_JTAG_ID_REG); diff --git a/arch/arm/include/asm/arch-keystone/msmc.h b/arch/arm/include/asm/arch-keystone/msmc.h index c320db5..083f5ba 100644 --- a/arch/arm/include/asm/arch-keystone/msmc.h +++ b/arch/arm/include/asm/arch-keystone/msmc.h @@ -12,6 +12,34 @@ #include <asm/arch/hardware.h> +enum mpax_seg_size { + MPAX_SEG_4K = 0x0b, + MPAX_SEG_8K, + MPAX_SEG_16K, + MPAX_SEG_32K, + MPAX_SEG_64K, + MPAX_SEG_128K, + MPAX_SEG_256K, + MPAX_SEG_512K, + MPAX_SEG_1M, + MPAX_SEG_2M, + MPAX_SEG_4M, + MPAX_SEG_8M, + MPAX_SEG_16M, + MPAX_SEG_32M, + MPAX_SEG_64M, + MPAX_SEG_128M, + MPAX_SEG_256M, + MPAX_SEG_512M, + MPAX_SEG_1G, + MPAX_SEG_2G, + MPAX_SEG_4G +}; + void msmc_share_all_segments(int priv_id); +void msmc_get_ses_mpax(int priv_id, int ses_pair, u32 *mpax); +void msmc_set_ses_mpax(int priv_id, int ses_pair, u32 *mpax); +void msmc_map_ses_segment(int priv_id, int ses_pair, + u32 src_pfn, u32 dst_pfn, enum mpax_seg_size size); #endif diff --git a/arch/arm/include/asm/arch-keystone/spl.h b/arch/arm/include/asm/arch-keystone/spl.h deleted file mode 100644 index a7102d5..0000000 --- a/arch/arm/include/asm/arch-keystone/spl.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2012-2014 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT_DEVICE_SPI 2 - -#endif diff --git a/arch/arm/include/asm/arch-keystone/xhci-keystone.h b/arch/arm/include/asm/arch-keystone/xhci-keystone.h new file mode 100644 index 0000000..3aab4e0 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/xhci-keystone.h @@ -0,0 +1,21 @@ +/* + * USB 3.0 DRD Controller + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define USB3_PHY_REF_SSP_EN BIT(29) +#define USB3_PHY_OTG_VBUSVLDECTSEL BIT(16) + +/* KEYSTONE2 XHCI PHY register structure */ +struct keystone_xhci_phy { + unsigned int phy_utmi; /* ctl0 */ + unsigned int phy_pipe; /* ctl1 */ + unsigned int phy_param_ctrl_1; /* ctl2 */ + unsigned int phy_param_ctrl_2; /* ctl3 */ + unsigned int phy_clock; /* ctl4 */ + unsigned int phy_pll; /* ctl5 */ +}; diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h index f7bfa0e..ccc8e4e 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -23,7 +23,7 @@ #error "SOC Name not defined" #endif /* CONFIG_KW88F6281 */ -#include <asm/arch/kirkwood.h> +#include <asm/arch/soc.h> #define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_SYS_CACHELINE_SIZE 32 /* default Dcache Line length for kirkwood */ diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h index 97daa40..926d347 100644 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ b/arch/arm/include/asm/arch-kirkwood/cpu.h @@ -140,11 +140,11 @@ struct kwgpio_registers { * functions */ unsigned char get_random_hex(void); -unsigned int kw_sdram_bar(enum memory_bank bank); -unsigned int kw_sdram_bs(enum memory_bank bank); -void kw_sdram_size_adjust(enum memory_bank bank); +unsigned int mvebu_sdram_bar(enum memory_bank bank); +unsigned int mvebu_sdram_bs(enum memory_bank bank); +void mvebu_sdram_size_adjust(enum memory_bank bank); int kw_config_adr_windows(void); -void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, +void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, unsigned int gpp0_oe, unsigned int gpp1_oe); int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, unsigned int mpp16_23, unsigned int mpp24_31, diff --git a/arch/arm/include/asm/arch-kirkwood/gpio.h b/arch/arm/include/asm/arch-kirkwood/gpio.h index 5f4d786..aa8c5da 100644 --- a/arch/arm/include/asm/arch-kirkwood/gpio.h +++ b/arch/arm/include/asm/arch-kirkwood/gpio.h @@ -21,14 +21,14 @@ #define GPIO_MAX 50 #define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000) -#define GPIO_OUT(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00) -#define GPIO_IO_CONF(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04) -#define GPIO_BLINK_EN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08) -#define GPIO_IN_POL(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) -#define GPIO_DATA_IN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10) -#define GPIO_EDGE_CAUSE(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14) -#define GPIO_EDGE_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18) -#define GPIO_LEVEL_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) +#define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00) +#define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04) +#define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08) +#define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) +#define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10) +#define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14) +#define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18) +#define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) /* * Kirkwood-specific GPIO API diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/soc.h index 3ea51d7..58ed71b 100644 --- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h +++ b/arch/arm/include/asm/arch-kirkwood/soc.h @@ -22,18 +22,19 @@ #define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470)) #define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478)) +#define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500)) #define KW_TWSI_BASE (KW_REGISTER(0x11000)) #define KW_UART0_BASE (KW_REGISTER(0x12000)) #define KW_UART1_BASE (KW_REGISTER(0x12100)) #define KW_MPP_BASE (KW_REGISTER(0x10000)) -#define KW_GPIO0_BASE (KW_REGISTER(0x10100)) -#define KW_GPIO1_BASE (KW_REGISTER(0x10140)) +#define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100)) +#define MVEBU_GPIO1_BASE (KW_REGISTER(0x10140)) #define KW_RTC_BASE (KW_REGISTER(0x10300)) #define KW_NANDF_BASE (KW_REGISTER(0x10418)) -#define KW_SPI_BASE (KW_REGISTER(0x10600)) +#define MVEBU_SPI_BASE (KW_REGISTER(0x10600)) #define KW_CPU_WIN_BASE (KW_REGISTER(0x20000)) #define KW_CPU_REG_BASE (KW_REGISTER(0x20100)) -#define KW_TIMER_BASE (KW_REGISTER(0x20300)) +#define MVEBU_TIMER_BASE (KW_REGISTER(0x20300)) #define KW_REG_PCIE_BASE (KW_REGISTER(0x40000)) #define KW_USB20_BASE (KW_REGISTER(0x50000)) #define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index a500b5b..f2c9687 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -19,6 +19,8 @@ #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) +#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) @@ -66,6 +68,7 @@ #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_DCU_BE +#define CONFIG_SYS_FSL_SEC_LE #define DCU_LAYER_MAX_NUM 16 @@ -76,6 +79,7 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h b/arch/arm/include/asm/arch-mvebu/spi.h index e512dce..e512dce 100644 --- a/arch/arm/include/asm/arch-kirkwood/spi.h +++ b/arch/arm/include/asm/arch-mvebu/spi.h diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 09dfc90..062f3de 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -10,6 +10,8 @@ #ifndef __SYS_PROTO_H__ #define __SYS_PROTO_H__ +#include <asm/imx-common/regs-common.h> + int mxs_reset_block(struct mxs_register_32 *reg); int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h index 2f83206..eba4a5c 100644 --- a/arch/arm/include/asm/arch-omap3/mux.h +++ b/arch/arm/include/asm/arch-omap3/mux.h @@ -281,7 +281,7 @@ #define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 #define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A #define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 -#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C +#define CONTROL_PADCONF_JTAG_NTRST 0x0A1C #define CONTROL_PADCONF_JTAG_TCK 0x0A1E #define CONTROL_PADCONF_JTAG_TMS 0x0A20 #define CONTROL_PADCONF_JTAG_TDI 0x0A22 @@ -443,7 +443,7 @@ #define OMAP34XX_CTRL_WKUP_CTRL (OMAP34XX_CTRL_BASE + 0x0A5C) #define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6) -#define MUX_VAL(OFFSET,VALUE)\ +#define MUX_VAL(OFFSET, VALUE)\ writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); #define CP(x) (CONTROL_PADCONF_##x) diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 5866bf2..34bd8c5 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -64,6 +64,7 @@ void try_unlock_memory(void); u32 get_boot_type(void); void invalidate_dcache(u32); u32 wait_on_value(u32, u32, void *, u32); +void cancel_out(u32 *num, u32 *den, u32 den_limit); void sdelay(unsigned long); void make_cs1_contiguous(void); void omap_nand_switch_ecc(uint32_t, uint32_t); diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index d5dbc22..2de205e 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -682,8 +682,7 @@ enum s5pc110_gpio_pin { S5PC110_GPIO_MP285, S5PC110_GPIO_MP286, S5PC110_GPIO_MP287, - S5PC110_GPIO_RES, - S5PC110_GPIO_H00 = (S5PC110_GPIO_RES + (48 * 8)), + S5PC110_GPIO_H00, S5PC110_GPIO_H01, S5PC110_GPIO_H02, S5PC110_GPIO_H03, @@ -815,11 +814,7 @@ static const struct gpio_name_num_table s5pc110_gpio_table[] = { void gpio_cfg_pin(int gpio, int cfg); void gpio_set_pull(int gpio, int mode); void gpio_set_drv(int gpio, int mode); -int gpio_direction_output(unsigned gpio, int value); -int gpio_set_value(unsigned gpio, int value); -int gpio_get_value(unsigned gpio); void gpio_set_rate(int gpio, int mode); -struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio); int s5p_gpio_get_pin(unsigned gpio); /* GPIO pins per bank */ diff --git a/arch/arm/include/asm/arch-socfpga/spl.h b/arch/arm/include/asm/arch-socfpga/spl.h deleted file mode 100644 index 7e310d5..0000000 --- a/arch/arm/include/asm/arch-socfpga/spl.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2012 Pavel Machek <pavel@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SOCFPGA_SPL_H_ -#define _SOCFPGA_SPL_H_ - -/* Symbols from linker script */ -extern char __malloc_start, __malloc_end, __stack_start; - -#define BOOT_DEVICE_RAM 1 - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 5669f39..c562f62 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -15,12 +15,17 @@ #define CLK_GATE_CLOSE 0x0 /* clock control module regs definition */ +#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I) +#include <asm/arch/clock_sun6i.h> +#else #include <asm/arch/clock_sun4i.h> +#endif #ifndef __ASSEMBLY__ int clock_init(void); int clock_twi_onoff(int port, int state); void clock_set_pll1(unsigned int hz); +unsigned int clock_get_pll5p(void); unsigned int clock_get_pll6(void); void clock_init_safe(void); void clock_init_uart(void); diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 1ba997a..90af8e2 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -199,13 +199,16 @@ struct sunxi_ccm_reg { #define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3) #define CCM_PLL5_CTRL_M1_X(n) ((n) - 1) #define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4) +#define CCM_PLL5_CTRL_K_SHIFT 4 #define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3) #define CCM_PLL5_CTRL_K_X(n) ((n) - 1) #define CCM_PLL5_CTRL_LDO (0x1 << 7) #define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8) +#define CCM_PLL5_CTRL_N_SHIFT 8 #define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f) #define CCM_PLL5_CTRL_N_X(n) (n) #define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16) +#define CCM_PLL5_CTRL_P_SHIFT 16 #define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3) #define CCM_PLL5_CTRL_P_X(n) ((n) - 1) #define CCM_PLL5_CTRL_BW (0x1 << 18) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h new file mode 100644 index 0000000..1397b35 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -0,0 +1,205 @@ +/* + * sun6i clock register definitions + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CLOCK_SUN6I_H +#define _SUNXI_CLOCK_SUN6I_H + +struct sunxi_ccm_reg { + u32 pll1_cfg; /* 0x00 pll1 control */ + u32 reserved0; + u32 pll2_cfg; /* 0x08 pll2 control */ + u32 reserved1; + u32 pll3_cfg; /* 0x10 pll3 control */ + u32 reserved2; + u32 pll4_cfg; /* 0x18 pll4 control */ + u32 reserved3; + u32 pll5_cfg; /* 0x20 pll5 control */ + u32 reserved4; + u32 pll6_cfg; /* 0x28 pll6 control */ + u32 reserved5; + u32 pll7_cfg; /* 0x30 pll7 control */ + u32 reserved6; + u32 pll8_cfg; /* 0x38 pll8 control */ + u32 reserved7; + u32 mipi_pll_cfg; /* 0x40 MIPI pll control */ + u32 pll9_cfg; /* 0x44 pll9 control */ + u32 pll10_cfg; /* 0x48 pll10 control */ + u32 reserved8; + u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */ + u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */ + u32 apb2_div; /* 0x58 APB2 divide ratio */ + u32 axi_gate; /* 0x5c axi module clock gating */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb1_gate; /* 0x68 apb1 module clock gating */ + u32 apb2_gate; /* 0x6c apb2 module clock gating */ + u32 reserved9[4]; + u32 nand0_clk_cfg; /* 0x80 nand0 clock control */ + u32 nand1_clk_cfg; /* 0x84 nand1 clock control */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 ts_clk_cfg; /* 0x98 transport stream clock control */ + u32 ss_clk_cfg; /* 0x9c security system clock control */ + u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */ + u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */ + u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */ + u32 spi3_clk_cfg; /* 0xac spi3 clock control */ + u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/ + u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */ + u32 reserved10[2]; + u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */ + u32 reserved11[2]; + u32 usb_clk_cfg; /* 0xcc USB clock control */ + u32 gmac_clk_cfg; /* 0xd0 GMAC clock control */ + u32 reserved12[7]; + u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */ + u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ + u32 reserved13[2]; + u32 dram_clk_gate; /* 0x100 DRAM module gating */ + u32 be0_clk_cfg; /* 0x104 BE0 module clock */ + u32 be1_clk_cfg; /* 0x108 BE1 module clock */ + u32 fe0_clk_cfg; /* 0x10c FE0 module clock */ + u32 fe1_clk_cfg; /* 0x110 FE1 module clock */ + u32 mp_clk_cfg; /* 0x114 MP module clock */ + u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */ + u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */ + u32 reserved14[3]; + u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */ + u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */ + u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */ + u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */ + u32 ve_clk_cfg; /* 0x13c VE module clock */ + u32 adda_clk_cfg; /* 0x140 ADDA module clock */ + u32 avs_clk_cfg; /* 0x144 AVS module clock */ + u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/ + u32 reserved15; + u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ + u32 ps_clk_cfg; /* 0x154 PS module clock */ + u32 mtc_clk_cfg; /* 0x158 MTC module clock */ + u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */ + u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */ + u32 reserved16; + u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */ + u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */ + u32 reserved17[4]; + u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */ + u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */ + u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */ + u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */ + u32 reserved18[4]; + u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */ + u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */ + u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */ + u32 reserved19[21]; + u32 pll_lock; /* 0x200 PLL Lock Time */ + u32 pll1_lock; /* 0x204 PLL1 Lock Time */ + u32 reserved20[6]; + u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */ + u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */ + u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */ + u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */ + u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */ + u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */ + u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */ + u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */ + u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */ + u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */ + u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */ + u32 reserved21[13]; + u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */ + u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */ + u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */ + u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */ + u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */ + u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */ + u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */ + u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */ + u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */ + u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */ + u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */ + u32 reserved22[5]; + u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */ + u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ + u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */ + u32 reserved23; + u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */ + u32 reserved24; + u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */ +}; + +/* apb2 bit field */ +#define APB2_CLK_SRC_LOSC (0x0 << 24) +#define APB2_CLK_SRC_OSC24M (0x1 << 24) +#define APB2_CLK_SRC_PLL6 (0x2 << 24) +#define APB2_CLK_SRC_MASK (0x3 << 24) +#define APB2_CLK_RATE_N_1 (0x0 << 16) +#define APB2_CLK_RATE_N_2 (0x1 << 16) +#define APB2_CLK_RATE_N_4 (0x2 << 16) +#define APB2_CLK_RATE_N_8 (0x3 << 16) +#define APB2_CLK_RATE_N_MASK (3 << 16) +#define APB2_CLK_RATE_M(m) (((m)-1) << 0) +#define APB2_CLK_RATE_M_MASK (0x1f << 0) + +/* apb2 gate field */ +#define APB2_GATE_UART_SHIFT (16) +#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT) +#define APB2_GATE_TWI_SHIFT (0) +#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT) + +/* cpu_axi_cfg bits */ +#define AXI_DIV_SHIFT 0 +#define ATB_DIV_SHIFT 8 +#define CPU_CLK_SRC_SHIFT 16 + +#define AXI_DIV_1 0 +#define AXI_DIV_2 1 +#define AXI_DIV_3 2 +#define AXI_DIV_4 3 +#define ATB_DIV_1 0 +#define ATB_DIV_2 1 +#define ATB_DIV_4 2 +#define CPU_CLK_SRC_OSC24M 1 +#define CPU_CLK_SRC_PLL1 2 + +#define PLL1_CFG_DEFAULT 0x90011b21 + +#define PLL6_CFG_DEFAULT 0x90041811 + +#define CCM_PLL6_CTRL_N_SHIFT 8 +#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) +#define CCM_PLL6_CTRL_K_SHIFT 4 +#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) + +#define AHB_GATE_OFFSET_MMC3 11 +#define AHB_GATE_OFFSET_MMC2 10 +#define AHB_GATE_OFFSET_MMC1 9 +#define AHB_GATE_OFFSET_MMC0 8 +#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) + +#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) +#define CCM_MMC_CTRL_PLL6 (0x1 << 24) + +#define CCM_MMC_CTRL_ENABLE (0x1 << 31) + +#define AHB_RESET_OFFSET_MMC3 11 +#define AHB_RESET_OFFSET_MMC2 10 +#define AHB_RESET_OFFSET_MMC1 9 +#define AHB_RESET_OFFSET_MMC0 8 +#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n)) + +/* apb2 reset */ +#define APB2_RESET_UART_SHIFT (16) +#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) +#define APB2_RESET_TWI_SHIFT (0) +#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) + +#endif /* _SUNXI_CLOCK_SUN6I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index a987e51d..0de79a0 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -95,6 +95,11 @@ #define SUNXI_MALI400_BASE 0x01c40000 #define SUNXI_GMAC_BASE 0x01c50000 +#define SUNXI_DRAM_COM_BASE 0x01c62000 +#define SUNXI_DRAM_CTL_BASE 0x01c63000 +#define SUNXI_DRAM_PHY_CH1_BASE 0x01c65000 +#define SUNXI_DRAM_PHY_CH2_BASE 0x01c66000 + /* module sram */ #define SUNXI_SRAM_C_BASE 0x01d00000 @@ -105,6 +110,11 @@ #define SUNXI_MP_BASE 0x01e80000 #define SUNXI_AVG_BASE 0x01ea0000 +#define SUNXI_PRCM_BASE 0x01f01400 +#define SUNXI_R_UART_BASE 0x01f02800 +#define SUNXI_R_PIO_BASE 0x01f02c00 +#define SUNXI_P2WI_BASE 0x01f03400 + /* CoreSight Debug Module */ #define SUNXI_CSDM_BASE 0x3f500000 diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index f7f3d8c..7bb6499 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -10,6 +10,7 @@ #define _SUNXI_GPIO_H #include <linux/types.h> +#include <asm/arch/cpu.h> /* * sunxi has 9 banks of gpio, they are: @@ -27,8 +28,27 @@ #define SUNXI_GPIO_G 6 #define SUNXI_GPIO_H 7 #define SUNXI_GPIO_I 8 + +/* + * This defines the number of GPIO banks for the _main_ GPIO controller. + * You should fix up the padding in struct sunxi_gpio_reg below if you + * change this. + */ #define SUNXI_GPIO_BANKS 9 +/* + * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) + * at a different register offset. + * + * sun6i has 2 banks: + * PL0 - PL8 | PM0 - PM7 + * + * sun8i has 1 bank: + * PL0 - PL11 + */ +#define SUNXI_GPIO_L 11 +#define SUNXI_GPIO_M 12 + struct sunxi_gpio { u32 cfg[4]; u32 dat; @@ -50,8 +70,9 @@ struct sunxi_gpio_reg { struct sunxi_gpio_int gpio_int; }; -#define BANK_TO_GPIO(bank) \ - &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] +#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ + &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) #define GPIO_BANK(pin) ((pin) >> 5) #define GPIO_NUM(pin) ((pin) & 0x1f) @@ -75,6 +96,8 @@ struct sunxi_gpio_reg { #define SUNXI_GPIO_G_NR 32 #define SUNXI_GPIO_H_NR 32 #define SUNXI_GPIO_I_NR 32 +#define SUNXI_GPIO_L_NR 32 +#define SUNXI_GPIO_M_NR 32 #define SUNXI_GPIO_NEXT(__gpio) \ ((__gpio##_START) + (__gpio##_NR) + 0) @@ -89,6 +112,8 @@ enum sunxi_gpio_number { SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), + SUNXI_GPIO_L_START = 352, + SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), }; /* SUNXI GPIO number definitions */ @@ -101,6 +126,8 @@ enum sunxi_gpio_number { #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) +#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) +#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) /* GPIO pin function config */ #define SUNXI_GPIO_INPUT 0 @@ -117,6 +144,8 @@ enum sunxi_gpio_number { #define SUN5I_GPB19_UART0_TX 2 #define SUN5I_GPB20_UART0_RX 2 +#define SUN5I_GPG3_SDC1 2 + #define SUN5I_GPG3_UART1_TX 4 #define SUN5I_GPG4_UART1_RX 4 @@ -125,15 +154,27 @@ enum sunxi_gpio_number { #define SUNXI_GPF0_SDC0 2 #define SUNXI_GPF2_SDC0 2 + +#ifdef CONFIG_SUN8I +#define SUNXI_GPF2_UART0_TX 3 +#define SUNXI_GPF4_UART0_RX 3 +#else #define SUNXI_GPF2_UART0_TX 4 #define SUNXI_GPF4_UART0_RX 4 +#endif #define SUN4I_GPG0_SDC1 4 #define SUN4I_GPH22_SDC1 5 +#define SUN6I_GPH20_UART0_TX 2 +#define SUN6I_GPH21_UART0_RX 2 + #define SUN4I_GPI4_SDC3 2 +#define SUN8I_GPL2_R_UART_TX 2 +#define SUN8I_GPL3_R_UART_RX 2 + /* GPIO pin pull-up/down config */ #define SUNXI_GPIO_PULL_DISABLE 0 #define SUNXI_GPIO_PULL_UP 1 diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h index 53196e3..8a21674 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -43,7 +43,10 @@ struct sunxi_mmc { u32 chda; /* 0x90 */ u32 cbda; /* 0x94 */ u32 res1[26]; - u32 fifo; /* 0x100 FIFO access address */ +#if defined(CONFIG_SUN6I) || defined(CONFIG_SUN8I) + u32 res2[64]; +#endif + u32 fifo; /* 0x100 (0x200 on sun6i) FIFO access address */ }; #define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) @@ -120,5 +123,5 @@ struct sunxi_mmc { #define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) #define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) -int sunxi_mmc_init(int sdc_no); +struct mmc *sunxi_mmc_init(int sdc_no); #endif /* _SUNXI_MMC_H */ diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h new file mode 100644 index 0000000..3d3bfa6 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -0,0 +1,238 @@ +/* + * Sunxi A31 Power Management Unit register definition. + * + * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> + * http://linux-sunxi.org + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Berg Xing <bergxing@allwinnertech.com> + * Tom Cubie <tangliang@allwinnertech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_PRCM_H +#define _SUNXI_PRCM_H + +#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4) +#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3) +#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1) +#define PRCM_CPUS_CFG_PRE_DIV(n) \ + __PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n)) +#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8) +#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f) +#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1) +#define PRCM_CPUS_CFG_POST_DIV(n) \ + __PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n)) +#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16) +#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3) +#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0 +#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1 +#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2 +#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3 +#define PRCM_CPUS_CFG_CLK_SRC_LOSC \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC) +#define PRCM_CPUS_CFG_CLK_SRC_HOSC \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC) +#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6) +#define PRCM_CPUS_CFG_CLK_SRC_PDIV \ + __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV) + +#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0) +#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3) +#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1) +#define PRCM_APB0_RATIO_DIV(n) \ + __PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n)) + +#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0) +#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1) + +#define PRCM_APB0_GATE_PIO (0x1 << 0) +#define PRCM_APB0_GATE_IR (0x1 << 1) +#define PRCM_APB0_GATE_TIMER01 (0x1 << 2) +#define PRCM_APB0_GATE_P2WI (0x1 << 3) +#define PRCM_APB0_GATE_UART (0x1 << 4) +#define PRCM_APB0_GATE_1WIRE (0x1 << 5) +#define PRCM_APB0_GATE_I2C (0x1 << 6) + +#define PRCM_APB0_RESET_PIO (0x1 << 0) +#define PRCM_APB0_RESET_IR (0x1 << 1) +#define PRCM_APB0_RESET_TIMER01 (0x1 << 2) +#define PRCM_APB0_RESET_P2WI (0x1 << 3) +#define PRCM_APB0_RESET_UART (0x1 << 4) +#define PRCM_APB0_RESET_1WIRE (0x1 << 5) +#define PRCM_APB0_RESET_I2C (0x1 << 6) + +#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0) +#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1) +#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4) +#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \ + __PRCM_PLL_CTRL_USB_CLK_SRC(0x3) +#define __PRCM_PLL_CTRL_USB_CLK_0 0x0 +#define __PRCM_PLL_CTRL_USB_CLK_1 0x1 +#define __PRCM_PLL_CTRL_USB_CLK_2 0x2 +#define __PRCM_PLL_CTRL_USB_CLK_3 0x3 +#define PRCM_PLL_CTRL_USB_CLK_0 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0) +#define PRCM_PLL_CTRL_USB_CLK_1 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1) +#define PRCM_PLL_CTRL_USB_CLK_2 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2) +#define PRCM_PLL_CTRL_USB_CLK_3 \ + __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3) +#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12) +#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \ + __PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3) +#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \ + __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) +#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20) +#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3) +#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0 +#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1 +#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2 +#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3 +#define PRCM_PLL_CTRL_HOSC_CLK_0 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0) +#define PRCM_PLL_CTRL_HOSC_CLK_1 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1) +#define PRCM_PLL_CTRL_HOSC_CLK_2 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2) +#define PRCM_PLL_CTRL_HOSC_CLK_3 \ + __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3) +#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24) +#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0) +#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1) +#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2) +#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3) +#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */ +#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16) +#define PRCM_PLL_CTRL_LDO_OUT_MASK \ + __PRCM_PLL_CTRL_LDO_OUT(0x7) +/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */ +#define PRCM_PLL_CTRL_LDO_OUT_L(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7) +#define PRCM_PLL_CTRL_LDO_OUT_H(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7) +#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000) +#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \ + __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160) +#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24) + +#define PRCM_CLK_1WIRE_GATE (0x1 << 31) + +#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0) +#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf) +#define __PRCM_CLK_MOD0_M_X(n) (n - 1) +#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n)) +#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8) +#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7) +#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16) +#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3) +#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1) +#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n)) +#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20) +#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7) +#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24) +#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7) +#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31) + +#define PRCM_APB0_RESET_PIO (0x1 << 0) +#define PRCM_APB0_RESET_IR (0x1 << 1) +#define PRCM_APB0_RESET_TIMER01 (0x1 << 2) +#define PRCM_APB0_RESET_P2WI (0x1 << 3) +#define PRCM_APB0_RESET_UART (0x1 << 4) +#define PRCM_APB0_RESET_1WIRE (0x1 << 5) +#define PRCM_APB0_RESET_I2C (0x1 << 6) + +#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8) +#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7) +#define __PRCM_CLK_OUTD_M_X() ((n) - 1) +#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n)) +#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20) +#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7) +#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1) +#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n) +#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24) +#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3) +#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0 +#define __PRCM_CLK_OUTD_SRC_LOSC 0x1 +#define __PRCM_CLK_OUTD_SRC_HOSC 0x2 +#define __PRCM_CLK_OUTD_SRC_ERR 0x3 +#define PRCM_CLK_OUTD_SRC_LOSC2 \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2) +#define PRCM_CLK_OUTD_SRC_LOSC \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC) +#define PRCM_CLK_OUTD_SRC_HOSC \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC) +#define PRCM_CLK_OUTD_SRC_ERR \ +#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR) +#define PRCM_CLK_OUTD_EN (0x1 << 31) + +#define PRCM_CPU0_PWROFF (0x1 << 0) +#define PRCM_CPU1_PWROFF (0x1 << 1) +#define PRCM_CPU2_PWROFF (0x1 << 2) +#define PRCM_CPU3_PWROFF (0x1 << 3) +#define PRCM_CPU_ALL_PWROFF (0xf << 0) + +#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0) +#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1) +#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2) +#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3) + +#define PRCM_VDD_GPU_PWROFF (0x1 << 0) + +#define PRCM_VDD_SYS_RESET (0x1 << 0) + +#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0) +#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff) + +#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0) +#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff) + +#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0) +#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff) + +#ifndef __ASSEMBLY__ +struct sunxi_prcm_reg { + u32 cpus_cfg; /* 0x000 */ + u8 res0[0x8]; /* 0x004 */ + u32 apb0_ratio; /* 0x00c */ + u32 cpu0_cfg; /* 0x010 */ + u32 cpu1_cfg; /* 0x014 */ + u32 cpu2_cfg; /* 0x018 */ + u32 cpu3_cfg; /* 0x01c */ + u8 res1[0x8]; /* 0x020 */ + u32 apb0_gate; /* 0x028 */ + u8 res2[0x14]; /* 0x02c */ + u32 pll_ctrl0; /* 0x040 */ + u32 pll_ctrl1; /* 0x044 */ + u8 res3[0x8]; /* 0x048 */ + u32 clk_1wire; /* 0x050 */ + u32 clk_ir; /* 0x054 */ + u8 res4[0x58]; /* 0x058 */ + u32 apb0_reset; /* 0x0b0 */ + u8 res5[0x3c]; /* 0x0b4 */ + u32 clk_outd; /* 0x0f0 */ + u8 res6[0xc]; /* 0x0f4 */ + u32 cpu_pwroff; /* 0x100 */ + u8 res7[0xc]; /* 0x104 */ + u32 vdd_sys_pwroff; /* 0x110 */ + u8 res8[0x4]; /* 0x114 */ + u32 gpu_pwroff; /* 0x118 */ + u8 res9[0x4]; /* 0x11c */ + u32 vdd_pwr_reset; /* 0x120 */ + u8 res10[0x20]; /* 0x124 */ + u32 cpu1_pwr_clamp; /* 0x144 */ + u32 cpu2_pwr_clamp; /* 0x148 */ + u32 cpu3_pwr_clamp; /* 0x14c */ + u8 res11[0x30]; /* 0x150 */ + u32 dram_pwr; /* 0x180 */ + u8 res12[0xc]; /* 0x184 */ + u32 dram_tst; /* 0x190 */ +}; + +void prcm_apb0_enable(u32 flags); +#endif /* __ASSEMBLY__ */ +#endif /* _PRCM_H */ diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h index 58e14fd..03a0684 100644 --- a/arch/arm/include/asm/arch-sunxi/timer.h +++ b/arch/arm/include/asm/arch-sunxi/timer.h @@ -11,14 +11,10 @@ #ifndef _SUNXI_TIMER_H_ #define _SUNXI_TIMER_H_ -#define WDT_CTRL_RESTART (0x1 << 0) -#define WDT_CTRL_KEY (0x0a57 << 1) -#define WDT_MODE_EN (0x1 << 0) -#define WDT_MODE_RESET_EN (0x1 << 1) - #ifndef __ASSEMBLY__ #include <linux/types.h> +#include <asm/arch/watchdog.h> /* General purpose timer */ struct sunxi_timer { @@ -43,12 +39,6 @@ struct sunxi_64cnt { u32 hi; /* 0xa8 */ }; -/* Watchdog */ -struct sunxi_wdog { - u32 ctl; /* 0x90 */ - u32 mode; /* 0x94 */ -}; - /* Rtc */ struct sunxi_rtc { u32 ctl; /* 0x100 */ @@ -77,15 +67,20 @@ struct sunxi_timer_reg { struct sunxi_timer timer[6]; /* We have 6 timers */ u8 res2[16]; struct sunxi_avs avs; - struct sunxi_wdog wdog; - u8 res3[8]; - struct sunxi_64cnt cnt64; +#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) + struct sunxi_wdog wdog; /* 0x90 */ + /* XXX the following is not accurate for sun5i/sun7i */ + struct sunxi_64cnt cnt64; /* 0xa0 */ u8 res4[0x58]; struct sunxi_rtc rtc; struct sunxi_alarm alarm; struct sunxi_tgp tgp[4]; u8 res5[8]; u32 cpu_cfg; +#else /* CONFIG_SUN6I || CONFIG_SUN8I || ... */ + u8 res3[16]; + struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */ +#endif }; #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/include/asm/arch-sunxi/watchdog.h new file mode 100644 index 0000000..ccc8fa3 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/watchdog.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2014 + * Chen-Yu Tsai <wens@csie.org> + * + * Watchdog register definitions + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_WATCHDOG_H_ +#define _SUNXI_WATCHDOG_H_ + +#define WDT_CTRL_RESTART (0x1 << 0) +#define WDT_CTRL_KEY (0x0a57 << 1) + +#if defined(CONFIG_SUN4I) || defined(CONFIG_SUN5I) || defined(CONFIG_SUN7I) + +#define WDT_MODE_EN (0x1 << 0) +#define WDT_MODE_RESET_EN (0x1 << 1) + +struct sunxi_wdog { + u32 ctl; /* 0x00 */ + u32 mode; /* 0x04 */ + u32 res[2]; +}; + +#else + +#define WDT_CFG_RESET (0x1) +#define WDT_MODE_EN (0x1) + +struct sunxi_wdog { + u32 irq_en; /* 0x00 */ + u32 irq_sta; /* 0x04 */ + u32 res1[2]; + u32 ctl; /* 0x10 */ + u32 cfg; /* 0x14 */ + u32 mode; /* 0x18 */ + u32 res2; +}; + +#endif + +#endif /* _SUNXI_WATCHDOG_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h index ff77364..783bb3c 100644 --- a/arch/arm/include/asm/arch-tegra/board.h +++ b/arch/arm/include/asm/arch-tegra/board.h @@ -24,10 +24,11 @@ void gpio_early_init(void); /* overrideable GPIO config */ * an empty stub function will be called. */ -void pinmux_init(void); /* overrideable general pinmux setup */ -void pin_mux_usb(void); /* overrideable USB pinmux setup */ -void pin_mux_spi(void); /* overrideable SPI pinmux setup */ -void pin_mux_nand(void); /* overrideable NAND pinmux setup */ -void pin_mux_display(void); /* overrideable DISPLAY pinmux setup */ +void pinmux_init(void); /* overridable general pinmux setup */ +void pin_mux_usb(void); /* overridable USB pinmux setup */ +void pin_mux_spi(void); /* overridable SPI pinmux setup */ +void pin_mux_nand(void); /* overridable NAND pinmux setup */ +void pin_mux_mmc(void); /* overridable mmc pinmux setup */ +void pin_mux_display(void); /* overridable DISPLAY pinmux setup */ #endif diff --git a/arch/arm/include/asm/arch-tegra114/mc.h b/arch/arm/include/asm/arch-tegra114/mc.h new file mode 100644 index 0000000..044b1e0 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/mc.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA114_MC_H_ +#define _TEGRA114_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[4]; /* offset 0x00 - 0x0C */ + u32 mc_smmu_config; /* offset 0x10 */ + u32 mc_smmu_tlb_config; /* offset 0x14 */ + u32 mc_smmu_ptc_config; /* offset 0x18 */ + u32 mc_smmu_ptb_asid; /* offset 0x1C */ + u32 mc_smmu_ptb_data; /* offset 0x20 */ + u32 reserved1[3]; /* offset 0x24 - 0x2C */ + u32 mc_smmu_tlb_flush; /* offset 0x30 */ + u32 mc_smmu_ptc_flush; /* offset 0x34 */ + u32 reserved2[6]; /* offset 0x38 - 0x4C */ + u32 mc_emem_cfg; /* offset 0x50 */ + u32 mc_emem_adr_cfg; /* offset 0x54 */ + u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ + u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ + u32 reserved3[12]; /* offset 0x60 - 0x8C */ + u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ + u32 reserved4[338]; /* offset 0x100 - 0x644 */ + u32 mc_video_protect_bom; /* offset 0x648 */ + u32 mc_video_protect_size_mb; /* offset 0x64c */ + u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ +}; + +#endif /* _TEGRA114_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra114/tegra.h b/arch/arm/include/asm/arch-tegra114/tegra.h index 5d426b5..c3d061e 100644 --- a/arch/arm/include/asm/arch-tegra114/tegra.h +++ b/arch/arm/include/asm/arch-tegra114/tegra.h @@ -19,6 +19,7 @@ #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T114 */ #define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */ +#define NV_PA_MC_BASE 0x70019000 #include <asm/arch-tegra/tegra.h> diff --git a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h b/arch/arm/include/asm/arch-tegra114/tegra114_spi.h deleted file mode 100644 index 48197bc..0000000 --- a/arch/arm/include/asm/arch-tegra114/tegra114_spi.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * NVIDIA Tegra SPI controller - * - * Copyright 2010-2013 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA114_SPI_H_ -#define _TEGRA114_SPI_H_ - -#include <asm/types.h> - -int tegra114_spi_init(int *node_list, int count); -int tegra114_spi_cs_is_valid(unsigned int bus, unsigned int cs); -struct spi_slave *tegra114_spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); -void tegra114_spi_free_slave(struct spi_slave *slave); -int tegra114_spi_claim_bus(struct spi_slave *slave); -void tegra114_spi_cs_activate(struct spi_slave *slave); -void tegra114_spi_cs_deactivate(struct spi_slave *slave); -int tegra114_spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags); - -#endif /* _TEGRA114_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/mc.h b/arch/arm/include/asm/arch-tegra20/mc.h new file mode 100644 index 0000000..9c6e3ff --- /dev/null +++ b/arch/arm/include/asm/arch-tegra20/mc.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA20_MC_H_ +#define _TEGRA20_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[3]; /* offset 0x00 - 0x08 */ + u32 mc_emem_cfg; /* offset 0x0C */ + u32 mc_emem_adr_cfg; /* offset 0x10 */ + u32 mc_emem_arb_cfg0; /* offset 0x14 */ + u32 mc_emem_arb_cfg1; /* offset 0x18 */ + u32 mc_emem_arb_cfg2; /* offset 0x1C */ + u32 reserved1; /* offset 0x20 */ + u32 mc_gart_cfg; /* offset 0x24 */ + u32 mc_gart_entry_addr; /* offset 0x28 */ + u32 mc_gart_entry_data; /* offset 0x2C */ + u32 mc_gart_error_req; /* offset 0x30 */ + u32 mc_gart_error_addr; /* offset 0x34 */ + u32 reserved2; /* offset 0x38 */ + u32 mc_timeout_ctrl; /* offset 0x3C */ + u32 reserved3[6]; /* offset 0x40 - 0x54 */ + u32 mc_decerr_emem_others_status; /* offset 0x58 */ + u32 mc_decerr_emem_others_adr; /* offset 0x5C */ + u32 reserved4[40]; /* offset 0x60 - 0xFC */ + u32 reserved5[93]; /* offset 0x100 - 0x270 */ +}; + +#endif /* _TEGRA20_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra.h b/arch/arm/include/asm/arch-tegra20/tegra.h index 18856ac..22774ab 100644 --- a/arch/arm/include/asm/arch-tegra20/tegra.h +++ b/arch/arm/include/asm/arch-tegra20/tegra.h @@ -9,6 +9,7 @@ #define _TEGRA20_H_ #define NV_PA_SDRAM_BASE 0x00000000 +#define NV_PA_MC_BASE 0x7000F000 #include <asm/arch-tegra/tegra.h> diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h b/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h deleted file mode 100644 index e8cc68c..0000000 --- a/arch/arm/include/asm/arch-tegra20/tegra20_sflash.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * NVIDIA Tegra20 SPI-FLASH controller - * - * Copyright 2010-2012 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA20_SPI_H_ -#define _TEGRA20_SPI_H_ - -#include <asm/types.h> - -int tegra20_spi_cs_is_valid(unsigned int bus, unsigned int cs); -struct spi_slave *tegra20_spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); -void tegra20_spi_free_slave(struct spi_slave *slave); -int tegra20_spi_init(int *node_list, int count); -int tegra20_spi_claim_bus(struct spi_slave *slave); -void tegra20_spi_cs_activate(struct spi_slave *slave); -void tegra20_spi_cs_deactivate(struct spi_slave *slave); -int tegra20_spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags); - -#endif /* _TEGRA20_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h b/arch/arm/include/asm/arch-tegra20/tegra20_slink.h deleted file mode 100644 index 5aa74dd..0000000 --- a/arch/arm/include/asm/arch-tegra20/tegra20_slink.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * NVIDIA Tegra SPI-SLINK controller - * - * Copyright 2010-2013 NVIDIA Corporation - * - * This software may be used and distributed according to the - * terms of the GNU Public License, Version 2, incorporated - * herein by reference. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _TEGRA30_SPI_H_ -#define _TEGRA30_SPI_H_ - -#include <asm/types.h> - -int tegra30_spi_init(int *node_list, int count); -int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs); -struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode); -void tegra30_spi_free_slave(struct spi_slave *slave); -int tegra30_spi_claim_bus(struct spi_slave *slave); -void tegra30_spi_cs_activate(struct spi_slave *slave); -void tegra30_spi_cs_deactivate(struct spi_slave *slave); -int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *data_out, void *data_in, unsigned long flags); - -#endif /* _TEGRA30_SPI_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/mc.h b/arch/arm/include/asm/arch-tegra30/mc.h new file mode 100644 index 0000000..242a1fc --- /dev/null +++ b/arch/arm/include/asm/arch-tegra30/mc.h @@ -0,0 +1,38 @@ +/* + * (C) Copyright 2014 + * NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _TEGRA30_MC_H_ +#define _TEGRA30_MC_H_ + +/** + * Defines the memory controller registers we need/care about + */ +struct mc_ctlr { + u32 reserved0[4]; /* offset 0x00 - 0x0C */ + u32 mc_smmu_config; /* offset 0x10 */ + u32 mc_smmu_tlb_config; /* offset 0x14 */ + u32 mc_smmu_ptc_config; /* offset 0x18 */ + u32 mc_smmu_ptb_asid; /* offset 0x1C */ + u32 mc_smmu_ptb_data; /* offset 0x20 */ + u32 reserved1[3]; /* offset 0x24 - 0x2C */ + u32 mc_smmu_tlb_flush; /* offset 0x30 */ + u32 mc_smmu_ptc_flush; /* offset 0x34 */ + u32 mc_smmu_asid_security; /* offset 0x38 */ + u32 reserved2[5]; /* offset 0x3C - 0x4C */ + u32 mc_emem_cfg; /* offset 0x50 */ + u32 mc_emem_adr_cfg; /* offset 0x54 */ + u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */ + u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */ + u32 reserved3[12]; /* offset 0x60 - 0x8C */ + u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */ + u32 reserved4[338]; /* offset 0x100 - 0x644 */ + u32 mc_video_protect_bom; /* offset 0x648 */ + u32 mc_video_protect_size_mb; /* offset 0x64c */ + u32 mc_video_protect_reg_ctrl; /* offset 0x650 */ +}; + +#endif /* _TEGRA30_MC_H_ */ diff --git a/arch/arm/include/asm/arch-tegra30/tegra.h b/arch/arm/include/asm/arch-tegra30/tegra.h index c02c5d8..9367179 100644 --- a/arch/arm/include/asm/arch-tegra30/tegra.h +++ b/arch/arm/include/asm/arch-tegra30/tegra.h @@ -17,6 +17,7 @@ #ifndef _TEGRA30_H_ #define _TEGRA30_H_ +#define NV_PA_MC_BASE 0x7000F000 #define NV_PA_SDRAM_BASE 0x80000000 /* 0x80000000 for real T30 */ #include <asm/arch-tegra/tegra.h> diff --git a/arch/arm/include/asm/arch-uniphier/platdevice.h b/arch/arm/include/asm/arch-uniphier/platdevice.h new file mode 100644 index 0000000..cdf7d13 --- /dev/null +++ b/arch/arm/include/asm/arch-uniphier/platdevice.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014 Panasonic Corporation + * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef ARCH_PLATDEVICE_H +#define ARCH_PLATDEVICE_H + +#include <dm/platdata.h> +#include <dm/platform_data/serial-uniphier.h> + +#define SERIAL_DEVICE(n, ba, clk) \ +static struct uniphier_serial_platform_data serial_device##n = { \ + .base = ba, \ + .uartclk = clk \ +}; \ +U_BOOT_DEVICE(serial##n) = { \ + .name = DRIVER_NAME, \ + .platdata = &serial_device##n \ +}; + +#endif /* ARCH_PLATDEVICE_H */ diff --git a/arch/arm/include/asm/imx-common/mxc_i2c.h b/arch/arm/include/asm/imx-common/mxc_i2c.h index 182c2f3..af86163 100644 --- a/arch/arm/include/asm/imx-common/mxc_i2c.h +++ b/arch/arm/include/asm/imx-common/mxc_i2c.h @@ -52,8 +52,8 @@ struct i2c_pads_info { &mx6q_##name : &mx6s_##name #endif -void setup_i2c(unsigned i2c_index, int speed, int slave_addr, - struct i2c_pads_info *p); +int setup_i2c(unsigned i2c_index, int speed, int slave_addr, + struct i2c_pads_info *p); void bus_i2c_init(void *base, int speed, int slave_addr, int (*idle_bus_fn)(void *p), void *p); int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 560924e..d4a447b 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1107,6 +1107,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_ARMADILLO_800EVA 3863 #define MACH_TYPE_KZM9G 4140 #define MACH_TYPE_COLIBRI_T30 4493 +#define MACH_TYPE_APALIS_T30 4513 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -14248,6 +14249,18 @@ extern unsigned int __machine_arch_type; # define machine_is_colibri_t30() (0) #endif +#ifdef CONFIG_MACH_APALIS_T30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APALIS_T30 +# endif +# define machine_is_apalis_t30() (machine_arch_type == MACH_TYPE_APALIS_T30) +#else +# define machine_is_apalis_t30() (0) +#endif + /* * These have not yet been registered */ diff --git a/arch/arm/include/asm/omap_gpio.h b/arch/arm/include/asm/omap_gpio.h index 5d25d04..839af54 100644 --- a/arch/arm/include/asm/omap_gpio.h +++ b/arch/arm/include/asm/omap_gpio.h @@ -23,6 +23,21 @@ #include <asm/arch/cpu.h> +enum gpio_method { + METHOD_GPIO_24XX = 4, +}; + +#ifdef CONFIG_DM_GPIO + +/* Information about a GPIO bank */ +struct omap_gpio_platdata { + int bank_index; + ulong base; /* address of registers in physical memory */ + enum gpio_method method; +}; + +#else + struct gpio_bank { void *base; int method; @@ -30,8 +45,6 @@ struct gpio_bank { extern const struct gpio_bank *const omap_gpio_bank; -#define METHOD_GPIO_24XX 4 - /** * Check if gpio is valid. * @@ -39,4 +52,6 @@ extern const struct gpio_bank *const omap_gpio_bank; * @return 1 if ok, 0 on error */ int gpio_is_valid(int gpio); +#endif + #endif /* _GPIO_H_ */ diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index e5daf89..8acd7cd 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -7,7 +7,7 @@ #ifndef _ASM_SPL_H_ #define _ASM_SPL_H_ -#if defined(CONFIG_OMAP) || defined(CONFIG_SOCFPGA) \ +#if defined(CONFIG_OMAP) \ || defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \ || defined(CONFIG_EXYNOS4210) /* Platform-specific defines */ diff --git a/arch/arm/include/asm/arch-keystone/keystone_nav.h b/arch/arm/include/asm/ti-common/keystone_nav.h index ab81eaf..696d8c6 100644 --- a/arch/arm/include/asm/arch-keystone/keystone_nav.h +++ b/arch/arm/include/asm/ti-common/keystone_nav.h @@ -13,10 +13,6 @@ #include <asm/arch/hardware.h> #include <asm/io.h> -enum soc_type_t { - k2hk -}; - #define QM_OK 0 #define QM_ERR -1 #define QM_DESC_TYPE_HOST 0 @@ -173,6 +169,8 @@ struct pktdma_cfg { u32 rx_flow; /* flow that is used for RX */ }; +extern struct pktdma_cfg netcp_pktdma; + /* * packet dma user allocates memory for rx buffers * and describe it in the following structure @@ -184,10 +182,10 @@ struct rx_buff_desc { u32 rx_flow; }; -int netcp_close(void); -int netcp_init(struct rx_buff_desc *rx_buffers); -int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2); -void *netcp_recv(u32 **pkt, int *num_bytes); -void netcp_release_rxhd(void *hd); +int ksnav_close(struct pktdma_cfg *pktdma); +int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers); +int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2); +void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes); +void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd); #endif /* _KEYSTONE_NAV_H_ */ diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h new file mode 100644 index 0000000..011c03c --- /dev/null +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -0,0 +1,249 @@ +/* + * emac definitions for keystone2 devices + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _KEYSTONE_NET_H_ +#define _KEYSTONE_NET_H_ + +#include <asm/io.h> + +/* EMAC */ +#ifdef CONFIG_KSNET_NETCP_V1_0 + +#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000) +#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900) +#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300) +#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100) +#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x040) + +/* Register offsets */ +#define CPGMACSL_REG_CTL 0x04 +#define CPGMACSL_REG_STATUS 0x08 +#define CPGMACSL_REG_RESET 0x0c +#define CPGMACSL_REG_MAXLEN 0x10 + +#elif defined CONFIG_KSNET_NETCP_V1_5 + +#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000) +#define CPGMACSL_REG_RX_PRI_MAP 0x020 +#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x22000) +#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x00f00) +#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x00100) +#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000) + +/* Register offsets */ +#define CPGMACSL_REG_CTL 0x330 +#define CPGMACSL_REG_STATUS 0x334 +#define CPGMACSL_REG_RESET 0x338 +#define CPGMACSL_REG_MAXLEN 0x024 + +#endif + +#define KEYSTONE2_EMAC_GIG_ENABLE + +#define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE + +/* MDIO module input frequency */ +#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk)) +/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ + +/* MII Status Register */ +#define MII_STATUS_REG 1 +#define MII_STATUS_LINK_MASK 0x4 + +#define MDIO_CONTROL_IDLE 0x80000000 +#define MDIO_CONTROL_ENABLE 0x40000000 +#define MDIO_CONTROL_FAULT_ENABLE 0x40000 +#define MDIO_CONTROL_FAULT 0x80000 +#define MDIO_USERACCESS0_GO 0x80000000 +#define MDIO_USERACCESS0_WRITE_READ 0x0 +#define MDIO_USERACCESS0_WRITE_WRITE 0x40000000 +#define MDIO_USERACCESS0_ACK 0x20000000 + +#define EMAC_MACCONTROL_MIIEN_ENABLE 0x20 +#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1 +#define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7) +#define EMAC_MACCONTROL_GIGFORCE BIT(17) +#define EMAC_MACCONTROL_RMIISPEED_100 BIT(15) + +#define EMAC_MIN_ETHERNET_PKT_SIZE 60 + +struct mac_sl_cfg { + u_int32_t max_rx_len; /* Maximum receive packet length. */ + u_int32_t ctl; /* Control bitfield */ +}; + +/** + * Definition: Control bitfields used in the ctl field of mac_sl_cfg + */ +#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES BIT(24) +#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES BIT(23) +#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES BIT(22) +#define GMACSL_RX_ENABLE_EXT_CTL BIT(18) +#define GMACSL_RX_ENABLE_GIG_FORCE BIT(17) +#define GMACSL_RX_ENABLE_IFCTL_B BIT(16) +#define GMACSL_RX_ENABLE_IFCTL_A BIT(15) +#define GMACSL_RX_ENABLE_CMD_IDLE BIT(11) +#define GMACSL_TX_ENABLE_SHORT_GAP BIT(10) +#define GMACSL_ENABLE_GIG_MODE BIT(7) +#define GMACSL_TX_ENABLE_PACE BIT(6) +#define GMACSL_ENABLE BIT(5) +#define GMACSL_TX_ENABLE_FLOW_CTL BIT(4) +#define GMACSL_RX_ENABLE_FLOW_CTL BIT(3) +#define GMACSL_ENABLE_LOOPBACK BIT(1) +#define GMACSL_ENABLE_FULL_DUPLEX BIT(0) + +/* EMAC SL function return values */ +#define GMACSL_RET_OK 0 +#define GMACSL_RET_INVALID_PORT -1 +#define GMACSL_RET_WARN_RESET_INCOMPLETE -2 +#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3 +#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4 + +/* EMAC SL register definitions */ +#define DEVICE_EMACSL_RESET_POLL_COUNT 100 + +/* Soft reset register values */ +#define CPGMAC_REG_RESET_VAL_RESET_MASK BIT(0) +#define CPGMAC_REG_RESET_VAL_RESET BIT(0) +#define CPGMAC_REG_MAXLEN_LEN 0x3fff + +/* CPSW */ +/* Control bitfields */ +#define CPSW_CTL_P2_PASS_PRI_TAGGED BIT(5) +#define CPSW_CTL_P1_PASS_PRI_TAGGED BIT(4) +#define CPSW_CTL_P0_PASS_PRI_TAGGED BIT(3) +#define CPSW_CTL_P0_ENABLE BIT(2) +#define CPSW_CTL_VLAN_AWARE BIT(1) +#define CPSW_CTL_FIFO_LOOPBACK BIT(0) + +#define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS +#define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1) + +#ifdef CONFIG_KSNET_NETCP_V1_0 + +#define DEVICE_CPSW_BASE (GBETH_BASE + 0x800) +#define CPSW_REG_CTL 0x004 +#define CPSW_REG_STAT_PORT_EN 0x00c +#define CPSW_REG_MAXLEN 0x040 +#define CPSW_REG_ALE_CONTROL 0x608 +#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x) * 4) +#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf + +#elif defined CONFIG_KSNET_NETCP_V1_5 + +#define DEVICE_CPSW_BASE (GBETH_BASE + 0x20000) +#define CPSW_REG_CTL 0x00004 +#define CPSW_REG_STAT_PORT_EN 0x00014 +#define CPSW_REG_MAXLEN 0x01024 +#define CPSW_REG_ALE_CONTROL 0x1e008 +#define CPSW_REG_ALE_PORTCTL(x) (0x1e040 + (x) * 4) +#define CPSW_REG_VAL_STAT_ENABLE_ALL 0x1ff + +#endif + +#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000) +#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010) +#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3 + +#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE +#define SWITCH_MAX_PKT_SIZE 9000 + +/* SGMII */ +#define SGMII_REG_STATUS_LOCK BIT(4) +#define SGMII_REG_STATUS_LINK BIT(0) +#define SGMII_REG_STATUS_AUTONEG BIT(2) +#define SGMII_REG_CONTROL_AUTONEG BIT(0) +#define SGMII_REG_CONTROL_MASTER BIT(5) +#define SGMII_REG_MR_ADV_ENABLE BIT(0) +#define SGMII_REG_MR_ADV_LINK BIT(15) +#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12) +#define SGMII_REG_MR_ADV_GIG_MODE BIT(11) + +#define SGMII_LINK_MAC_MAC_AUTONEG 0 +#define SGMII_LINK_MAC_PHY 1 +#define SGMII_LINK_MAC_MAC_FORCED 2 +#define SGMII_LINK_MAC_FIBER 3 +#define SGMII_LINK_MAC_PHY_FORCED 4 + +#ifdef CONFIG_KSNET_NETCP_V1_0 +#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100)) +#elif defined CONFIG_KSNET_NETCP_V1_5 +#define SGMII_OFFSET(x) ((x) * 0x100) +#endif + +#define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000) +#define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004) +#define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010) +#define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014) +#define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018) +#define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020) +#define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030) +#define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034) +#define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038) + +/* PSS */ +#ifdef CONFIG_KSNET_NETCP_V1_0 + +#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x604) +#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606 +#define hw_config_streaming_switch()\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR); + +#elif defined CONFIG_KSNET_NETCP_V1_5 + +#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x500) +#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0 + +#define hw_config_streaming_switch()\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR);\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR+4);\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR+8);\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR+12); + +#endif + +/* EMAC MDIO Registers Structure */ +struct mdio_regs { + u32 version; + u32 control; + u32 alive; + u32 link; + u32 linkintraw; + u32 linkintmasked; + u32 rsvd0[2]; + u32 userintraw; + u32 userintmasked; + u32 userintmaskset; + u32 userintmaskclear; + u32 rsvd1[20]; + u32 useraccess0; + u32 userphysel0; + u32 useraccess1; + u32 userphysel1; +}; + +struct eth_priv_t { + char int_name[32]; + int rx_flow; + int phy_addr; + int slave_port; + int sgmii_link_type; + struct phy_device *phy_dev; +}; + +int keystone2_emac_initialize(struct eth_priv_t *eth_priv); +void sgmii_serdes_setup_156p25mhz(void); +void sgmii_serdes_shutdown(void); + +#endif /* _KEYSTONE_NET_H_ */ diff --git a/arch/arm/include/asm/ti-common/keystone_serdes.h b/arch/arm/include/asm/ti-common/keystone_serdes.h new file mode 100644 index 0000000..2e92411 --- /dev/null +++ b/arch/arm/include/asm/ti-common/keystone_serdes.h @@ -0,0 +1,55 @@ +/* + * Texas Instruments Keystone SerDes driver + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TI_KEYSTONE_SERDES_H__ +#define __TI_KEYSTONE_SERDES_H__ + +/* SERDES Reference clock */ +enum ks2_serdes_clock { + SERDES_CLOCK_100M, /* 100 MHz */ + SERDES_CLOCK_122P88M, /* 122.88 MHz */ + SERDES_CLOCK_125M, /* 125 MHz */ + SERDES_CLOCK_156P25M, /* 156.25 MHz */ + SERDES_CLOCK_312P5M, /* 312.5 MHz */ +}; + +/* SERDES Lane Baud Rate */ +enum ks2_serdes_rate { + SERDES_RATE_4P9152G, /* 4.9152 GBaud */ + SERDES_RATE_5G, /* 5 GBaud */ + SERDES_RATE_6P144G, /* 6.144 GBaud */ + SERDES_RATE_6P25G, /* 6.25 GBaud */ + SERDES_RATE_10p3125g, /* 10.3215 GBaud */ + SERDES_RATE_12p5g, /* 12.5 GBaud */ +}; + +/* SERDES Lane Rate Mode */ +enum ks2_serdes_rate_mode { + SERDES_FULL_RATE, + SERDES_HALF_RATE, + SERDES_QUARTER_RATE, +}; + +/* SERDES PHY TYPE */ +enum ks2_serdes_interface { + SERDES_PHY_SGMII, + SERDES_PHY_PCSR, /* XGE SERDES */ +}; + +struct ks2_serdes { + enum ks2_serdes_clock clk; + enum ks2_serdes_rate rate; + enum ks2_serdes_rate_mode rate_mode; + enum ks2_serdes_interface intf; + u32 loopback; +}; + +int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes); + +#endif /* __TI_KEYSTONE_SERDES_H__ */ diff --git a/arch/arm/include/asm/ti-common/ti-edma3.h b/arch/arm/include/asm/ti-common/ti-edma3.h new file mode 100644 index 0000000..5adc1da --- /dev/null +++ b/arch/arm/include/asm/ti-common/ti-edma3.h @@ -0,0 +1,121 @@ +/* + * Enhanced Direct Memory Access (EDMA3) Controller + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _EDMA3_H_ +#define _EDMA3_H_ + +#include <linux/stddef.h> + +#define EDMA3_PARSET_NULL_LINK 0xffff + +/* + * All parameter RAM set options + * opt field in edma3_param_set_config structure + */ +#define EDMA3_SLOPT_PRIV_LEVEL BIT(31) +#define EDMA3_SLOPT_PRIV_ID(id) ((0xf & (id)) << 24) +#define EDMA3_SLOPT_INTERM_COMP_CHAIN_ENB BIT(23) +#define EDMA3_SLOPT_TRANS_COMP_CHAIN_ENB BIT(22) +#define EDMA3_SLOPT_INTERM_COMP_INT_ENB BIT(21) +#define EDMA3_SLOPT_TRANS_COMP_INT_ENB BIT(20) +#define EDMA3_SLOPT_COMP_CODE(code) ((0x3f & (code)) << 12) +#define EDMA3_SLOPT_FIFO_WIDTH_8 0 +#define EDMA3_SLOPT_FIFO_WIDTH_16 (1 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_32 (2 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_64 (3 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_128 (4 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_256 (5 << 8) +#define EDMA3_SLOPT_FIFO_WIDTH_SET(w) ((w & 0x7) << 8) +#define EDMA3_SLOPT_STATIC BIT(3) +#define EDMA3_SLOPT_AB_SYNC BIT(2) +#define EDMA3_SLOPT_DST_ADDR_CONST_MODE BIT(1) +#define EDMA3_SLOPT_SRC_ADDR_CONST_MODE BIT(0) + +enum edma3_address_mode { + INCR = 0, + FIFO = 1 +}; + +enum edma3_fifo_width { + W8BIT = 0, + W16BIT = 1, + W32BIT = 2, + W64BIT = 3, + W128BIT = 4, + W256BIT = 5 +}; + +enum edma3_sync_dimension { + ASYNC = 0, + ABSYNC = 1 +}; + +/* PaRAM slots are laid out like this */ +struct edma3_slot_layout { + u32 opt; + u32 src; + u32 a_b_cnt; + u32 dst; + u32 src_dst_bidx; + u32 link_bcntrld; + u32 src_dst_cidx; + u32 ccnt; +} __packed; + +/* + * Use this to assign trigger word number of edma3_slot_layout struct. + * trigger_word_name - is the exact name from edma3_slot_layout. + */ +#define EDMA3_TWORD(trigger_word_name)\ + (offsetof(struct edma3_slot_layout, trigger_word_name) / 4) + +struct edma3_slot_config { + u32 opt; + u32 src; + u32 dst; + int bcnt; + int acnt; + int ccnt; + int src_bidx; + int dst_bidx; + int src_cidx; + int dst_cidx; + int bcntrld; + int link; +}; + +struct edma3_channel_config { + int slot; + int chnum; + int complete_code; /* indicate pending complete interrupt */ + int trigger_slot_word; /* only used for qedma */ +}; + +void qedma3_start(u32 base, struct edma3_channel_config *cfg); +void qedma3_stop(u32 base, struct edma3_channel_config *cfg); +void edma3_slot_configure(u32 base, int slot, struct edma3_slot_config *cfg); +int edma3_check_for_transfer(u32 base, struct edma3_channel_config *cfg); +void edma3_write_slot(u32 base, int slot, struct edma3_slot_layout *param); +void edma3_read_slot(u32 base, int slot, struct edma3_slot_layout *param); + +void edma3_set_dest(u32 base, int slot, u32 dst, enum edma3_address_mode mode, + enum edma3_fifo_width width); +void edma3_set_dest_index(u32 base, unsigned slot, int bidx, int cidx); +void edma3_set_dest_addr(u32 base, int slot, u32 dst); + +void edma3_set_src(u32 base, int slot, u32 src, enum edma3_address_mode mode, + enum edma3_fifo_width width); +void edma3_set_src_index(u32 base, unsigned slot, int bidx, int cidx); +void edma3_set_src_addr(u32 base, int slot, u32 src); + +void edma3_set_transfer_params(u32 base, int slot, int acnt, + int bcnt, int ccnt, u16 bcnt_rld, + enum edma3_sync_dimension sync_mode); + +#endif diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index b16694c..f97f3dd 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -45,4 +45,19 @@ void reset_timer_masked (void); ulong get_timer_masked (void); void udelay_masked (unsigned long usec); +/* calls to c from vectors.S */ +void bad_mode(void); +void do_undefined_instruction(struct pt_regs *pt_regs); +void do_software_interrupt(struct pt_regs *pt_regs); +void do_prefetch_abort(struct pt_regs *pt_regs); +void do_data_abort(struct pt_regs *pt_regs); +void do_not_used(struct pt_regs *pt_regs); +#ifdef CONFIG_ARM64 +void do_fiq(struct pt_regs *pt_regs, unsigned int esr); +void do_irq(struct pt_regs *pt_regs, unsigned int esr); +#else +void do_fiq(struct pt_regs *pt_regs); +void do_irq(struct pt_regs *pt_regswq); +#endif + #endif /* _U_BOOT_ARM_H_ */ |