diff options
Diffstat (limited to 'arch/arm/include')
-rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-rdc.h | 16 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 29 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx6/mx6sx_rdc.h | 155 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx7/imx-rdc.h | 16 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx7/imx-regs.h | 11 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx7/mx7d_rdc.h | 163 | ||||
-rw-r--r-- | arch/arm/include/asm/imx-common/rdc-sema.h | 100 |
7 files changed, 490 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx6/imx-rdc.h b/arch/arm/include/asm/arch-mx6/imx-rdc.h new file mode 100644 index 0000000..c4d3bb4 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/imx-rdc.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX_RDC_H__ +#define __IMX_RDC_H__ + +#if defined(CONFIG_MX6SX) +#include "mx6sx_rdc.h" +#else +#error "Please select cpu" +#endif /* CONFIG_MX6SX */ + +#endif /* __IMX_RDC_H__*/ diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5c45bf6..f3c26dc 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -356,6 +356,30 @@ extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); #define SRC_SCR_CORE_3_ENABLE_OFFSET 24 #define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET) +struct rdc_regs { + u32 vir; /* Version information */ + u32 reserved1[8]; + u32 stat; /* Status */ + u32 intctrl; /* Interrupt and Control */ + u32 intstat; /* Interrupt Status */ + u32 reserved2[116]; + u32 mda[32]; /* Master Domain Assignment */ + u32 reserved3[96]; + u32 pdap[104]; /* Peripheral Domain Access Permissions */ + u32 reserved4[88]; + struct { + u32 mrsa; /* Memory Region Start Address */ + u32 mrea; /* Memory Region End Address */ + u32 mrc; /* Memory Region Control */ + u32 mrvs; /* Memory Region Violation Status */ + } mem_region[55]; +}; + +struct rdc_sema_regs { + u8 gate[64]; /* Gate */ + u16 rstgt; /* Reset Gate */ +}; + /* WEIM registers */ struct weim { u32 cs0gcr1; @@ -414,6 +438,11 @@ struct src { u32 gpr10; }; +#define SRC_SCR_M4_ENABLE_OFFSET 22 +#define SRC_SCR_M4_ENABLE_MASK (1 << 22) +#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 4 +#define SRC_SCR_M4C_NON_SCLR_RST_MASK (1 << 4) + /* GPR1 bitfields */ #define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30) #define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28) diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h b/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h new file mode 100644 index 0000000..addfe01 --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6sx_rdc.h @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6SX_RDC_H__ +#define __MX6SX_RDC_H__ + +#define RDC_SEMA_PROC_ID 2 /* The processor ID for main CPU */ + +enum { + RDC_PER_PWM1 = 0, + RDC_PER_PWM2, + RDC_PER_PWM3, + RDC_PER_PWM4, + RDC_PER_CAN1, + RDC_PER_CAN2, + RDC_PER_GPT, + RDC_PER_GPIO1, + RDC_PER_GPIO2, + RDC_PER_GPIO3, + RDC_PER_GPIO4, + RDC_PER_GPIO5, + RDC_PER_GPIO6, + RDC_PER_GPIO7, + RDC_PER_KPP, + RDC_PER_WDOG1, + RDC_PER_WODG2, + RDC_PER_CCM, + RDC_PER_ANATOPDIG, + RDC_PER_SNVSHP, + RDC_PER_EPIT1, + RDC_PER_EPIT2, + RDC_PER_SRC, + RDC_PER_GPC, + RDC_PER_IOMUXC, + RDC_PER_IOMUXCGPR, + RDC_PER_CANFD1, + RDC_PER_SDMA, + RDC_PER_CANFD2, + RDC_PER_SEMA1, + RDC_PER_SEMA2, + RDC_PER_RDC, + RDC_PER_AIPSTZ1_GE1, + RDC_PER_AIPSTZ2_GE2, + RDC_PER_USBO2H_PL301, + RDC_PER_USBO2H_USB, + RDC_PER_ENET1, + RDC_PER_MLB25, + RDC_PER_USDHC1, + RDC_PER_USDHC2, + RDC_PER_USDHC3, + RDC_PER_USDHC4, + RDC_PER_I2C1, + RDC_PER_I2C2, + RDC_PER_I2C3, + RDC_PER_ROMCP, + RDC_PER_MMDC, + RDC_PER_ENET2, + RDC_PER_EIM, + RDC_PER_OCOTP, + RDC_PER_CSU, + RDC_PER_PERFMON1, + RDC_PER_PERFMON2, + RDC_PER_AXIMON, + RDC_PER_TZASC1, + RDC_PER_SAI1, + RDC_PER_AUDMUX, + RDC_PER_SAI2, + RDC_PER_QSPI1, + RDC_PER_QSPI2, + RDC_PER_UART2, + RDC_PER_UART3, + RDC_PER_UART4, + RDC_PER_UART5, + RDC_PER_I2C4, + RDC_PER_QOSC, + RDC_PER_CAAM, + RDC_PER_DAP, + RDC_PER_ADC1, + RDC_PER_ADC2, + RDC_PER_WDOG3, + RDC_PER_ECSPI5, + RDC_PER_SEMA4, + RDC_PER_MUPORT1, + RDC_PER_CANFD_CPU, + RDC_PER_MUPORT2, + RDC_PER_UART6, + RDC_PER_PWM5, + RDC_PER_PWM6, + RDC_PER_PWM7, + RDC_PER_PWM8, + RDC_PER_AIPSTZ3_GE0, + RDC_PER_AIPSTZ3_GE1, + RDC_PER_RESERVED1, + RDC_PER_SPDIF, + RDC_PER_ECSPI1, + RDC_PER_ECSPI2, + RDC_PER_ECSPI3, + RDC_PER_ECSPI4, + RDC_PER_RESERVED2, + RDC_PER_RESERVED3, + RDC_PER_UART1, + RDC_PER_ESAI, + RDC_PER_SSI1, + RDC_PER_SSI2, + RDC_PER_SSI3, + RDC_PER_ASRC, + RDC_PER_RESERVED4, + RDC_PER_SPBA_MA, + RDC_PER_GIS, + RDC_PER_DCIC1, + RDC_PER_DCIC2, + RDC_PER_CSI1, + RDC_PER_PXP, + RDC_PER_CSI2, + RDC_PER_LCDIF1, + RDC_PER_LCDIF2, + RDC_PER_VADC, + RDC_PER_VDEC, + RDC_PER_SPBA_DISPLAYMIX, +}; + +enum { + RDC_MA_A9_L2CACHE = 0, + RDC_MA_M4, + RDC_MA_GPU, + RDC_MA_CSI1, + RDC_MA_CSI2, + RDC_MA_LCDIF1, + RDC_MA_LCDIF2, + RDC_MA_PXP, + RDC_MA_PCIE_CTRL, + RDC_MA_DAP, + RDC_MA_CAAM, + RDC_MA_SDMA_PERI, + RDC_MA_SDMA_BURST, + RDC_MA_APBHDMA, + RDC_MA_RAWNAND, + RDC_MA_USDHC1, + RDC_MA_USDHC2, + RDC_MA_USDHC3, + RDC_MA_USDHC4, + RDC_MA_USB, + RDC_MA_MLB, + RDC_MA_TEST, + RDC_MA_ENET1_TX, + RDC_MA_ENET1_RX, + RDC_MA_ENET2_TX, + RDC_MA_ENET2_RX, + RDC_MA_SDMA, +}; + +#endif /* __MX6SX_RDC_H__*/ diff --git a/arch/arm/include/asm/arch-mx7/imx-rdc.h b/arch/arm/include/asm/arch-mx7/imx-rdc.h new file mode 100644 index 0000000..dbeed56 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/imx-rdc.h @@ -0,0 +1,16 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX_RDC_H__ +#define __IMX_RDC_H__ + +#if defined(CONFIG_MX7D) +#include "mx7d_rdc.h" +#else +#error "Please select cpu" +#endif /* CONFIG_MX7D */ + +#endif /* __IMX_RDC_H__*/ diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index 58a25c7..a3106e7 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -212,10 +212,16 @@ #define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR #define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR +#define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR +#define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR +#define RDC_BASE_ADDR RDC_IPS_BASE_ADDR #define FEC_QUIRK_ENET_MAC #define SNVS_LPGPR 0x68 +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + 0x1000) + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/imx-common/regs-lcdif.h> #include <asm/types.h> @@ -257,6 +263,11 @@ struct src { u32 ddrc_rcr; }; +#define SRC_M4RCR_M4C_NON_SCLR_RST_OFFSET 0 +#define SRC_M4RCR_M4C_NON_SCLR_RST_MASK (1 << 0) +#define SRC_M4RCR_ENABLE_M4_OFFSET 3 +#define SRC_M4RCR_ENABLE_M4_MASK (1 << 3) + /* GPR0 Bit Fields */ #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 diff --git a/arch/arm/include/asm/arch-mx7/mx7d_rdc.h b/arch/arm/include/asm/arch-mx7/mx7d_rdc.h new file mode 100644 index 0000000..9073cbd --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/mx7d_rdc.h @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_RDC_H__ +#define __MX7D_RDC_H__ + +#define RDC_SEMA_PROC_ID 2 /* The processor ID for main CPU */ + +enum { + RDC_PER_GPIO1 = 0, + RDC_PER_GPIO2, + RDC_PER_GPIO3, + RDC_PER_GPIO4, + RDC_PER_GPIO5, + RDC_PER_GPIO6, + RDC_PER_GPIO7, + RDC_PER_IOMUXC_LPSR_GPR, + RDC_PER_WDOG1, + RDC_PER_WDOG2, + RDC_PER_WDOG3, + RDC_PER_WDOG4, + RDC_PER_IOMUXC_LPSR, + RDC_PER_GPT1, + RDC_PER_GPT2, + RDC_PER_GPT3, + RDC_PER_GPT4, + RDC_PER_ROMCP, + RDC_PER_KPP, + RDC_PER_IOMUXC, + RDC_PER_IOMUXCGPR, + RDC_PER_OCOTP, + RDC_PER_ANATOP_DIG, + RDC_PER_SNVS_HP, + RDC_PER_CCM, + RDC_PER_SRC, + RDC_PER_GPC, + RDC_PER_SEMA1, + RDC_PER_SEMA2, + RDC_PER_RDC, + RDC_PER_CSU, + RDC_PER_RESERVED1, + RDC_PER_RESERVED2, + RDC_PER_ADC1, + RDC_PER_ADC2, + RDC_PER_ECSPI4, + RDC_PER_FLEX_TIMER1, + RDC_PER_FLEX_TIMER2, + RDC_PER_PWM1, + RDC_PER_PWM2, + RDC_PER_PWM3, + RDC_PER_PWM4, + RDC_PER_SYSTEM_COUNTER_READ, + RDC_PER_SYSTEM_COUNTER_COMPARE, + RDC_PER_SYSTEM_COUNTER_CONTROL, + RDC_PER_PCIE_PHY, + RDC_PER_RESERVED3, + RDC_PER_EPDC, + RDC_PER_PXP, + RDC_PER_CSI, + RDC_PER_RESERVED4, + RDC_PER_LCDIF, + RDC_PER_RESERVED5, + RDC_PER_MIPI_CSI, + RDC_PER_MIPI_DSI, + RDC_PER_RESERVED6, + RDC_PER_TZASC, + RDC_PER_DDR_PHY, + RDC_PER_DDRC, + RDC_PER_RESERVED7, + RDC_PER_PERFMON1, + RDC_PER_PERFMON2, + RDC_PER_AXI_DEBUG_MON, + RDC_PER_QOSC, + RDC_PER_FLEXCAN1, + RDC_PER_FLEXCAN2, + RDC_PER_I2C1, + RDC_PER_I2C2, + RDC_PER_I2C3, + RDC_PER_I2C4, + RDC_PER_UART4, + RDC_PER_UART5, + RDC_PER_UART6, + RDC_PER_UART7, + RDC_PER_MU_A, + RDC_PER_MU_B, + RDC_PER_SEMAPHORE_HS, + RDC_PER_USB_PL301, + RDC_PER_RESERVED8, + RDC_PER_RESERVED9, + RDC_PER_RESERVED10, + RDC_PER_USB1, + RDC_PER_USB2, + RDC_PER_USB3, + RDC_PER_USDHC1, + RDC_PER_USDHC2, + RDC_PER_USDHC3, + RDC_PER_RESERVED11, + RDC_PER_RESERVED12, + RDC_PER_SIM1, + RDC_PER_SIM2, + RDC_PER_QSPI, + RDC_PER_WEIM, + RDC_PER_SDMA, + RDC_PER_ENET1, + RDC_PER_ENET2, + RDC_PER_RESERVED13, + RDC_PER_RESERVED14, + RDC_PER_ECSPI1, + RDC_PER_ECSPI2, + RDC_PER_ECSPI3, + RDC_PER_RESERVED15, + RDC_PER_UART1, + RDC_PER_UART2, + RDC_PER_UART3, + RDC_PER_RESERVED16, + RDC_PER_SAI1, + RDC_PER_SAI2, + RDC_PER_SAI3, + RDC_PER_RESERVED17, + RDC_PER_RESERVED18, + RDC_PER_SPBA, + RDC_PER_DAP, + RDC_PER_RESERVED19, + RDC_PER_RESERVED20, + RDC_PER_RESERVED21, + RDC_PER_CAAM, + RDC_PER_RESERVED22, +}; + +enum { + RDC_MA_A7 = 0, + RDC_MA_M4, + RDC_MA_PCIE, + RDC_MA_CSI, + RDC_MA_EPDC, + RDC_MA_LCDIF, + RDC_MA_DISPLAY_PORT, + RDC_MA_PXP, + RDC_MA_CORESIGHT, + RDC_MA_DAP, + RDC_MA_CAAM, + RDC_MA_SDMA_PERI, + RDC_MA_SDMA_BURST, + RDC_MA_APBHDMA, + RDC_MA_RAWNAND, + RDC_MA_USDHC1, + RDC_MA_USDHC2, + RDC_MA_USDHC3, + RDC_MA_NC1, + RDC_MA_USB, + RDC_MA_NC2, + RDC_MA_TEST, + RDC_MA_ENET1_TX, + RDC_MA_ENET1_RX, + RDC_MA_ENET2_TX, + RDC_MA_ENET2_RX, + RDC_MA_SDMA, +}; + +#endif /* __MX7D_RDC_H__*/ diff --git a/arch/arm/include/asm/imx-common/rdc-sema.h b/arch/arm/include/asm/imx-common/rdc-sema.h new file mode 100644 index 0000000..2c61e56 --- /dev/null +++ b/arch/arm/include/asm/imx-common/rdc-sema.h @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __RDC_SEMA_H__ +#define __RDC_SEMA_H__ + +/* + * rdc_peri_cfg_t and rdc_ma_cft_t use the same layout. + * + * [ 23 22 | 21 20 | 19 18 | 17 16 ] | [ 15 - 8 ] | [ 7 - 0 ] + * d3 d2 d1 d0 | master id | peri id + * d[x] means domain[x], x can be [3 - 0]. + */ +typedef u32 rdc_peri_cfg_t; +typedef u32 rdc_ma_cfg_t; + +#define RDC_PERI_SHIFT 0 +#define RDC_PERI_MASK 0xFF + +#define RDC_DOMAIN_SHIFT_BASE 16 +#define RDC_DOMAIN_MASK 0xFF0000 +#define RDC_DOMAIN_SHIFT(x) (RDC_DOMAIN_SHIFT_BASE + ((x << 1))) +#define RDC_DOMAIN(x) ((rdc_peri_cfg_t)(0x3 << RDC_DOMAIN_SHIFT(x))) + +#define RDC_MASTER_SHIFT 8 +#define RDC_MASTER_MASK 0xFF00 +#define RDC_MASTER_CFG(master_id, domain_id) (rdc_ma_cfg_t)((master_id << 8) | \ + (domain_id << RDC_DOMAIN_SHIFT_BASE)) + +/* The Following macro definitions are common to i.MX6SX and i.MX7D */ +#define SEMA_GATES_NUM 64 + +#define RDC_MDA_DID_SHIFT 0 +#define RDC_MDA_DID_MASK (0x3 << RDC_MDA_DID_SHIFT) +#define RDC_MDA_LCK_SHIFT 31 +#define RDC_MDA_LCK_MASK (0x1 << RDC_MDA_LCK_SHIFT) + +#define RDC_PDAP_DW_SHIFT(domain) ((domain) << 1) +#define RDC_PDAP_DR_SHIFT(domain) (1 + RDC_PDAP_DW_SHIFT(domain)) +#define RDC_PDAP_DW_MASK(domain) (1 << RDC_PDAP_DW_SHIFT(domain)) +#define RDC_PDAP_DR_MASK(domain) (1 << RDC_PDAP_DR_SHIFT(domain)) +#define RDC_PDAP_DRW_MASK(domain) (RDC_PDAP_DW_MASK(domain) | \ + RDC_PDAP_DR_MASK(domain)) + +#define RDC_PDAP_SREQ_SHIFT 30 +#define RDC_PDAP_SREQ_MASK (0x1 << RDC_PDAP_SREQ_SHIFT) +#define RDC_PDAP_LCK_SHIFT 31 +#define RDC_PDAP_LCK_MASK (0x1 << RDC_PDAP_LCK_SHIFT) + +#define RDC_MRSA_SADR_SHIFT 7 +#define RDC_MRSA_SADR_MASK (0x1ffffff << RDC_MRSA_SADR_SHIFT) + +#define RDC_MREA_EADR_SHIFT 7 +#define RDC_MREA_EADR_MASK (0x1ffffff << RDC_MREA_EADR_SHIFT) + +#define RDC_MRC_DW_SHIFT(domain) (domain) +#define RDC_MRC_DR_SHIFT(domain) (1 + RDC_MRC_DW_SHIFT(domain)) +#define RDC_MRC_DW_MASK(domain) (1 << RDC_MRC_DW_SHIFT(domain)) +#define RDC_MRC_DR_MASK(domain) (1 << RDC_MRC_DR_SHIFT(domain)) +#define RDC_MRC_DRW_MASK(domain) (RDC_MRC_DW_MASK(domain) | \ + RDC_MRC_DR_MASK(domain)) +#define RDC_MRC_ENA_SHIFT 30 +#define RDC_MRC_ENA_MASK (0x1 << RDC_MRC_ENA_SHIFT) +#define RDC_MRC_LCK_SHIFT 31 +#define RDC_MRC_LCK_MASK (0x1 << RDC_MRC_LCK_SHIFT) + +#define RDC_MRVS_VDID_SHIFT 0 +#define RDC_MRVS_VDID_MASK (0x3 << RDC_MRVS_VDID_SHIFT) +#define RDC_MRVS_AD_SHIFT 4 +#define RDC_MRVS_AD_MASK (0x1 << RDC_MRVS_AD_SHIFT) +#define RDC_MRVS_VADDR_SHIFT 5 +#define RDC_MRVS_VADDR_MASK (0x7ffffff << RDC_MRVS_VADDR_SHIFT) + +#define RDC_SEMA_GATE_GTFSM_SHIFT 0 +#define RDC_SEMA_GATE_GTFSM_MASK (0xf << RDC_SEMA_GATE_GTFSM_SHIFT) +#define RDC_SEMA_GATE_LDOM_SHIFT 5 +#define RDC_SEMA_GATE_LDOM_MASK (0x3 << RDC_SEMA_GATE_LDOM_SHIFT) + +#define RDC_SEMA_RSTGT_RSTGDP_SHIFT 0 +#define RDC_SEMA_RSTGT_RSTGDP_MASK (0xff << RDC_SEMA_RSTGT_RSTGDP_SHIFT) +#define RDC_SEMA_RSTGT_RSTGSM_SHIFT 2 +#define RDC_SEMA_RSTGT_RSTGSM_MASK (0x3 << RDC_SEMA_RSTGT_RSTGSM_SHIFT) +#define RDC_SEMA_RSTGT_RSTGMS_SHIFT 4 +#define RDC_SEMA_RSTGT_RSTGMS_MASK (0xf << RDC_SEMA_RSTGT_RSTGMS_SHIFT) +#define RDC_SEMA_RSTGT_RSTGTN_SHIFT 8 +#define RDC_SEMA_RSTGT_RSTGTN_MASK (0xff << RDC_SEMA_RSTGT_RSTGTN_SHIFT) + +int imx_rdc_check_permission(int per_id, int dom_id); +int imx_rdc_sema_lock(int per_id); +int imx_rdc_sema_unlock(int per_id); +int imx_rdc_setup_peri(rdc_peri_cfg_t p); +int imx_rdc_setup_peripherals(rdc_peri_cfg_t const *peripherals_list, + unsigned count); +int imx_rdc_setup_ma(rdc_ma_cfg_t p); +int imx_rdc_setup_masters(rdc_ma_cfg_t const *masters_list, unsigned count); + +#endif /* __RDC_SEMA_H__*/ |