diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/Kconfig | 17 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/ls102xa/Kconfig | 61 | ||||
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 87 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 30 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-ls102xa/config.h | 6 |
5 files changed, 76 insertions, 125 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 38080c0..0ed36cd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -464,10 +464,16 @@ config ARCH_MESON config ARCH_MX7 bool "Freescale MX7" select CPU_V7 + select SYS_FSL_HAS_SEC if SECURE_BOOT + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE config ARCH_MX6 bool "Freescale MX6" select CPU_V7 + select SYS_FSL_HAS_SEC if SECURE_BOOT + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE config ARCH_MX5 bool "Freescale MX5" @@ -540,6 +546,7 @@ config ARCH_RMOBILE config TARGET_S32V234EVB bool "Support s32v234evb" select ARM64 + select SYS_FSL_ERRATUM_ESDHC111 config ARCH_SNAPDRAGON bool "Qualcomm Snapdragon SoCs" @@ -596,22 +603,31 @@ config TARGET_TS4600 config TARGET_TS4800 bool "Support TS4800" select CPU_V7 + select SYS_FSL_ERRATUM_ESDHC_A001 config TARGET_VF610TWR bool "Support vf610twr" select CPU_V7 + select SYS_FSL_ERRATUM_ESDHC111 config TARGET_COLIBRI_VF bool "Support Colibri VF50/61" select CPU_V7 + select SYS_FSL_ERRATUM_ESDHC111 config TARGET_PCM052 bool "Support pcm-052" select CPU_V7 + select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_ESDHC135 + select SYS_FSL_ERRATUM_ESDHC_A001 config TARGET_BK4R1 bool "Support BK4r1" select CPU_V7 + select SYS_FSL_ERRATUM_ESDHC111 + select SYS_FSL_ERRATUM_ESDHC135 + select SYS_FSL_ERRATUM_ESDHC_A001 config ARCH_ZYNQ bool "Xilinx Zynq Platform" @@ -764,6 +780,7 @@ config TARGET_LS1021AQDS select ARCH_LS1021A select ARCH_SUPPORT_PSCI select LS1_DEEP_SLEEP + select SYS_FSL_DDR config TARGET_LS1021ATWR bool "Support ls1021atwr" diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index f94568a..9ffb90e 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -1,10 +1,19 @@ config ARCH_LS1021A bool + select SYS_FSL_ERRATUM_A008378 + select SYS_FSL_ERRATUM_A008407 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_SRDS_1 select SYS_HAS_SERDES - select SYS_FSL_DDR_BE - select SYS_FSL_DDR_VER_50 + select SYS_FSL_DDR_BE if SYS_FSL_DDR + select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR + select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR + select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE menu "LS102xA architecture" depends on ARCH_LS1021A @@ -24,10 +33,6 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. -config NUM_DDR_CONTROLLERS - int "Maximum DDR controllers" - default 1 - config SECURE_BOOT bool "Secure Boot" help @@ -46,50 +51,12 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool -config SYS_FSL_DDR - bool "Freescale DDR driver" - help - Select Freescale General DDR driver, shared between most Freescale - PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- - based Layerscape SoCs (such as ls2080a). - -config SYS_FSL_DDR_BE - bool - default y - help - Access DDR registers in big-endian. - -config SYS_FSL_DDR_VER - int - default 50 if SYS_FSL_DDR_VER_50 - -config SYS_FSL_DDR_VER_50 - bool - -config SYS_FSL_DDRC_ARM_GEN3 - bool - -config SYS_FSL_DDRC_GEN4 - bool - -config SYS_FSL_DDR3 - bool "Freescale DDR3 controller" - depends on !SYS_FSL_DDR4 - select SYS_FSL_DDR - select SYS_FSL_DDRC_ARM_GEN3 - help - Enable Freescale DDR3 controller on ARM-based SoCs. - -config SYS_FSL_DDR4 - bool "Freescale DDR4 controller" - select SYS_FSL_DDR - select SYS_FSL_DDRC_GEN4 - help - Enable Freescale DDR4 controller. - config SYS_FSL_IFC_BANK_COUNT int "Maximum banks of Integrated flash controller" depends on ARCH_LS1021A default 8 +config SYS_FSL_ERRATUM_A008407 + bool + endmenu diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index cc0dc88..de0b580 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -8,31 +8,62 @@ config ARCH_LS1012A config ARCH_LS1043A bool select FSL_LSCH2 + select SYS_FSL_DDR select SYS_FSL_DDR_BE select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A008850 + select SYS_FSL_ERRATUM_A009660 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009929 + select SYS_FSL_ERRATUM_A009942 select SYS_FSL_ERRATUM_A010315 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_HAS_DDR3 + select SYS_FSL_HAS_DDR4 config ARCH_LS1046A bool select FSL_LSCH2 + select SYS_FSL_DDR select SYS_FSL_DDR_BE - select SYS_FSL_DDR4 select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A008511 + select SYS_FSL_ERRATUM_A009801 + select SYS_FSL_ERRATUM_A009803 + select SYS_FSL_ERRATUM_A009942 + select SYS_FSL_ERRATUM_A010165 select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_HAS_DDR4 select SYS_FSL_SRDS_2 config ARCH_LS2080A bool select FSL_LSCH3 - select SYS_FSL_DDR4 + select SYS_FSL_DDR select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 select SYS_FSL_HAS_DP_DDR + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE select SYS_FSL_SRDS_2 + select SYS_FSL_ERRATUM_A008336 + select SYS_FSL_ERRATUM_A008511 + select SYS_FSL_ERRATUM_A008514 + select SYS_FSL_ERRATUM_A008585 + select SYS_FSL_ERRATUM_A009635 + select SYS_FSL_ERRATUM_A009663 + select SYS_FSL_ERRATUM_A009801 + select SYS_FSL_ERRATUM_A009803 + select SYS_FSL_ERRATUM_A009942 + select SYS_FSL_ERRATUM_A010165 config FSL_LSCH2 bool + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_BE select SYS_FSL_SRDS_1 select SYS_HAS_SERDES @@ -65,9 +96,6 @@ config FSL_PPA_ARMV8_PSCI implemented under the common ARMv8 PSCI framework. endmenu -config SYS_FSL_MMDC - bool - config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" @@ -87,11 +115,6 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores. -config NUM_DDR_CONTROLLERS - int "Maximum DDR controllers" - default 3 if ARCH_LS2080A - default 1 - config SECURE_BOOT bool help @@ -123,49 +146,25 @@ config SYS_FSL_SRDS_2 config SYS_HAS_SERDES bool -config SYS_FSL_DDR - bool "Freescale DDR driver" - help - Select Freescale General DDR driver, shared between most Freescale - PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- - based Layerscape SoCs (such as ls2080a). +endmenu -config SYS_FSL_DDR_BE +config SYS_FSL_ERRATUM_A008336 bool - help - Access DDR registers in big-endian. -config SYS_FSL_DDR_LE +config SYS_FSL_ERRATUM_A008514 bool - help - Access DDR registers in little-endian. - -config SYS_FSL_DDR_VER - int - default 50 if SYS_FSL_DDR_VER_50 -config SYS_FSL_DDR_VER_50 +config SYS_FSL_ERRATUM_A008585 bool -config SYS_FSL_DDRC_ARM_GEN3 +config SYS_FSL_ERRATUM_A008850 bool -config SYS_FSL_DDRC_GEN4 +config SYS_FSL_ERRATUM_A009635 bool -config SYS_FSL_DDR3 - bool "Freescale DDR3 controller" - depends on !SYS_FSL_DDR4 - select SYS_FSL_DDR - select SYS_FSL_DDRC_ARM_GEN3 - help - Enable Freescale DDR3 controller on ARM-based SoCs. - -config SYS_FSL_DDR4 - bool "Freescale DDR4 controller" - select SYS_FSL_DDR - select SYS_FSL_DDRC_GEN4 - help - Enable Freescale DDR4 controller. +config SYS_FSL_ERRATUM_A009660 + bool -endmenu +config SYS_FSL_ERRATUM_A009929 + bool diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index c50894a..6073d44 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -55,10 +55,6 @@ #define CONFIG_SYS_FSL_SFP_LE #define CONFIG_SYS_FSL_SRK_LE -/* SEC */ -#define CONFIG_SYS_FSL_SEC_LE -#define CONFIG_SYS_FSL_SEC_COMPAT 5 - /* Security Monitor */ #define CONFIG_SYS_FSL_SEC_MON_LE @@ -115,17 +111,7 @@ #define EPU_EPCTR5 0x700060a14ULL #define EPU_EPGCR 0x700060000ULL -#define CONFIG_SYS_FSL_ERRATUM_A008336 -#define CONFIG_SYS_FSL_ERRATUM_A008511 -#define CONFIG_SYS_FSL_ERRATUM_A008514 -#define CONFIG_SYS_FSL_ERRATUM_A008585 #define CONFIG_SYS_FSL_ERRATUM_A008751 -#define CONFIG_SYS_FSL_ERRATUM_A009635 -#define CONFIG_SYS_FSL_ERRATUM_A009663 -#define CONFIG_SYS_FSL_ERRATUM_A009801 -#define CONFIG_SYS_FSL_ERRATUM_A009803 -#define CONFIG_SYS_FSL_ERRATUM_A009942 -#define CONFIG_SYS_FSL_ERRATUM_A010165 /* ARM A57 CORE ERRATA */ #define CONFIG_ARM_ERRATA_826974 @@ -135,7 +121,6 @@ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_FSL_LSCH2) -#define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ @@ -146,7 +131,6 @@ #define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_CCSR_GUR_BE #define CONFIG_SYS_FSL_PEX_LUT_BE -#define CONFIG_SYS_FSL_SEC_BE /* SoC related */ #ifdef CONFIG_LS1043A @@ -175,17 +159,12 @@ #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 -#define CONFIG_SYS_FSL_ERRATUM_A008850 -#define CONFIG_SYS_FSL_ERRATUM_A009663 -#define CONFIG_SYS_FSL_ERRATUM_A009929 -#define CONFIG_SYS_FSL_ERRATUM_A009942 -#define CONFIG_SYS_FSL_ERRATUM_A009660 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 -#elif defined(CONFIG_ARCH_LS1012A) -#undef CONFIG_SYS_FSL_DDRC_ARM_GEN3 +#elif defined(CONFIG_ARCH_LS1012A) #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 + #elif defined(CONFIG_ARCH_LS1046A) #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 @@ -210,11 +189,6 @@ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 -#define CONFIG_SYS_FSL_ERRATUM_A008511 -#define CONFIG_SYS_FSL_ERRATUM_A009801 -#define CONFIG_SYS_FSL_ERRATUM_A009803 -#define CONFIG_SYS_FSL_ERRATUM_A009942 -#define CONFIG_SYS_FSL_ERRATUM_A010165 #else #error SoC not defined #endif diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index ec65cc0..fccd4ff 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -91,7 +91,6 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) #define CONFIG_DOS_PARTITION -#define CONFIG_SYS_FSL_ERRATUM_A008407 #ifdef CONFIG_DDR_SPD #define CONFIG_VERY_BIG_RAM @@ -106,7 +105,6 @@ #define CONFIG_SYS_FSL_QSPI_BE #define CONFIG_SYS_FSL_DCU_BE #define CONFIG_SYS_FSL_SEC_MON_LE -#define CONFIG_SYS_FSL_SEC_LE #define CONFIG_SYS_FSL_SFP_VER_3_2 #define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SRK_LE @@ -114,11 +112,7 @@ #define DCU_LAYER_MAX_NUM 16 #ifdef CONFIG_LS102XA -#define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_SYS_FSL_ERRATUM_A008378 -#define CONFIG_SYS_FSL_ERRATUM_A009663 -#define CONFIG_SYS_FSL_ERRATUM_A009942 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined |