diff options
Diffstat (limited to 'arch/arm')
45 files changed, 869 insertions, 279 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index 5566310..aae3f09 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -14,7 +14,6 @@ endif obj-$(CONFIG_TI816X) += clock_ti816x.o obj-y += sys_info.o -obj-y += mem.o obj-y += ddr.o obj-y += emif4.o obj-y += board.o diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c deleted file mode 100644 index 56c9e7d..0000000 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Author : - * Mansoor Ahamed <mansoor.ahamed@ti.com> - * - * Initial Code from: - * Manikandan Pillai <mani.pillai@ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mem.h> -#include <asm/arch/sys_proto.h> -#include <command.h> - -struct gpmc *gpmc_cfg; - - -void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, - u32 size) -{ - writel(0, &cs->config7); - sdelay(1000); - /* Delay for settling */ - writel(gpmc_config[0], &cs->config1); - writel(gpmc_config[1], &cs->config2); - writel(gpmc_config[2], &cs->config3); - writel(gpmc_config[3], &cs->config4); - writel(gpmc_config[4], &cs->config5); - writel(gpmc_config[5], &cs->config6); - /* Enable the config */ - writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | - (1 << 6)), &cs->config7); - sdelay(2000); -} - -/***************************************************** - * gpmc_init(): init gpmc bus - * Init GPMC for x16, MuxMode (SDRAM in x32). - * This code can only be executed from SRAM or SDRAM. - *****************************************************/ -void gpmc_init(void) -{ - /* putting a blanket check on GPMC based on ZeBu for now */ - gpmc_cfg = (struct gpmc *)GPMC_BASE; -#if defined(CONFIG_NOR) -/* configure GPMC for NOR */ - const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, - STNOR_GPMC_CONFIG2, - STNOR_GPMC_CONFIG3, - STNOR_GPMC_CONFIG4, - STNOR_GPMC_CONFIG5, - STNOR_GPMC_CONFIG6, - STNOR_GPMC_CONFIG7 - }; - u32 size = GPMC_SIZE_16M; - u32 base = CONFIG_SYS_FLASH_BASE; -#elif defined(CONFIG_NAND) -/* configure GPMC for NAND */ - const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, - 0 - }; - u32 size = GPMC_SIZE_256M; - u32 base = CONFIG_SYS_NAND_BASE; -#else - const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 }; - u32 size = 0; - u32 base = 0; -#endif - /* global settings */ - writel(0x00000008, &gpmc_cfg->sysconfig); - writel(0x00000000, &gpmc_cfg->irqstatus); - writel(0x00000000, &gpmc_cfg->irqenable); -#ifdef CONFIG_NOR - writel(0x00000200, &gpmc_cfg->config); -#else - writel(0x00000012, &gpmc_cfg->config); -#endif - /* - * Disable the GPMC0 config set by ROM code - */ - writel(0, &gpmc_cfg->cs[0].config7); - sdelay(1000); - /* enable chip-select specific configurations */ - enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); -} diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index 50eb598..2ce682f 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -79,12 +79,24 @@ u32 get_sysboot_value(void) } #ifdef CONFIG_DISPLAY_CPUINFO +static char *cpu_revs[] = { + "1.0", + "2.0", + "2.1"}; + + +static char *dev_types[] = { + "TST", + "EMU", + "HS", + "GP"}; + /** * Print CPU information */ int print_cpuinfo(void) { - char *cpu_s, *sec_s; + char *cpu_s, *sec_s, *rev_s; switch (get_cpu_type()) { case AM335X: @@ -94,28 +106,21 @@ int print_cpuinfo(void) cpu_s = "TI81XX"; break; default: - cpu_s = "Unknown cpu type"; + cpu_s = "Unknown CPU type"; break; } - switch (get_device_type()) { - case TST_DEVICE: - sec_s = "TST"; - break; - case EMU_DEVICE: - sec_s = "EMU"; - break; - case HS_DEVICE: - sec_s = "HS"; - break; - case GP_DEVICE: - sec_s = "GP"; - break; - default: + if (get_cpu_rev() < ARRAY_SIZE(cpu_revs)) + rev_s = cpu_revs[get_cpu_rev()]; + else + rev_s = "?"; + + if (get_device_type() < ARRAY_SIZE(dev_types)) + sec_s = dev_types[get_device_type()]; + else sec_s = "?"; - } - printf("%s-%s rev %d\n", cpu_s, sec_s, get_cpu_rev()); + printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s); return 0; } diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 59f5352..5f5132f 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -27,8 +27,4 @@ obj-y += boot-common.o obj-y += lowlevel_init.o endif -ifndef CONFIG_SPL_BUILD -ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) obj-y += mem-common.o -endif -endif diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 429c4be..71c0cc8 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1384,8 +1384,10 @@ void sdram_init(void) if (sdram_type == EMIF_SDRAM_TYPE_DDR3 && (!in_sdram && !warm_reset())) { - do_bug0039_workaround(EMIF1_BASE); - do_bug0039_workaround(EMIF2_BASE); + if (emif1_enabled) + do_bug0039_workaround(EMIF1_BASE); + if (emif2_enabled) + do_bug0039_workaround(EMIF2_BASE); } debug("<<sdram_init()\n"); diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 8ebc0ce..ba97d9e 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -185,7 +185,7 @@ u32 omap_sdram_size(void) { u32 section, i, valid; u64 sdram_start = 0, sdram_end = 0, addr, - size, total_size = 0, trap_size = 0; + size, total_size = 0, trap_size = 0, trap_start = 0; for (i = 0; i < 4; i++) { section = __raw_readl(DMM_BASE + i*4); @@ -194,8 +194,8 @@ u32 omap_sdram_size(void) addr = section & EMIF_SYS_ADDR_MASK; /* See if the address is valid */ - if ((addr >= DRAM_ADDR_SPACE_START) && - (addr < DRAM_ADDR_SPACE_END)) { + if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) && + (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) { size = ((section & EMIF_SYS_SIZE_MASK) >> EMIF_SYS_SIZE_SHIFT); size = 1 << size; @@ -208,12 +208,15 @@ u32 omap_sdram_size(void) sdram_end = addr + size; } else { trap_size = size; + trap_start = addr; } - } - } - total_size = (sdram_end - sdram_start) - (trap_size); + + if ((trap_start >= sdram_start) && (trap_start < sdram_end)) + total_size = (sdram_end - sdram_start) - (trap_size); + else + total_size = sdram_end - sdram_start; return total_size; } diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index afc1bc1..944ef84 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -2,31 +2,136 @@ * (C) Copyright 2010 * Texas Instruments, <www.ti.com> * - * Steve Sakoman <steve@sakoman.com> + * Author : + * Mansoor Ahamed <mansoor.ahamed@ti.com> + * + * Initial Code from: + * Manikandan Pillai <mani.pillai@ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> * * SPDX-License-Identifier: GPL-2.0+ */ +#include <common.h> +#include <asm/io.h> #include <asm/arch/cpu.h> +#include <asm/arch/mem.h> #include <asm/arch/sys_proto.h> +#include <command.h> +#include <linux/mtd/omap_gpmc.h> struct gpmc *gpmc_cfg; +#if defined(CONFIG_OMAP34XX) +/******************************************************** + * mem_ok() - test used to see if timings are correct + * for a part. Helps in guessing which part + * we are currently using. + *******************************************************/ +u32 mem_ok(u32 cs) +{ + u32 val1, val2, addr; + u32 pattern = 0x12345678; + + addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); + + writel(0x0, addr + 0x400); /* clear pos A */ + writel(pattern, addr); /* pattern to pos B */ + writel(0x0, addr + 4); /* remove pattern off the bus */ + val1 = readl(addr + 0x400); /* get pos A value */ + val2 = readl(addr); /* get val2 */ + writel(0x0, addr + 0x400); /* clear pos A */ + + if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */ + return 0; + else + return 1; +} +#endif + +void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, + u32 size) +{ + writel(0, &cs->config7); + sdelay(1000); + /* Delay for settling */ + writel(gpmc_config[0], &cs->config1); + writel(gpmc_config[1], &cs->config2); + writel(gpmc_config[2], &cs->config3); + writel(gpmc_config[3], &cs->config4); + writel(gpmc_config[4], &cs->config5); + writel(gpmc_config[5], &cs->config6); + /* Enable the config */ + writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), &cs->config7); + sdelay(2000); +} + /***************************************************** * gpmc_init(): init gpmc bus + * Init GPMC for x16, MuxMode (SDRAM in x32). * This code can only be executed from SRAM or SDRAM. *****************************************************/ void gpmc_init(void) { + /* putting a blanket check on GPMC based on ZeBu for now */ gpmc_cfg = (struct gpmc *)GPMC_BASE; - +#if defined(CONFIG_NOR) +/* configure GPMC for NOR */ + const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, + STNOR_GPMC_CONFIG2, + STNOR_GPMC_CONFIG3, + STNOR_GPMC_CONFIG4, + STNOR_GPMC_CONFIG5, + STNOR_GPMC_CONFIG6, + STNOR_GPMC_CONFIG7 + }; + u32 size = GPMC_SIZE_16M; + u32 base = CONFIG_SYS_FLASH_BASE; +#elif defined(CONFIG_NAND) +/* configure GPMC for NAND */ + const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, + 0 + }; + u32 size = GPMC_SIZE_256M; + u32 base = CONFIG_SYS_NAND_BASE; +#elif defined(CONFIG_CMD_ONENAND) + const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1, + ONENAND_GPMC_CONFIG2, + ONENAND_GPMC_CONFIG3, + ONENAND_GPMC_CONFIG4, + ONENAND_GPMC_CONFIG5, + ONENAND_GPMC_CONFIG6, + 0 + }; + u32 base = PISMO1_ONEN_BASE; + u32 size = PISMO1_ONEN_SIZE; +#else + const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 }; + u32 size = 0; + u32 base = 0; +#endif /* global settings */ - writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */ - writel(0, &gpmc_cfg->timeout_control);/* timeout disable */ - + writel(0x00000008, &gpmc_cfg->sysconfig); + writel(0x00000000, &gpmc_cfg->irqstatus); + writel(0x00000000, &gpmc_cfg->irqenable); + writel(0x00000000, &gpmc_cfg->timeout_control); +#ifdef CONFIG_NOR + writel(0x00000200, &gpmc_cfg->config); +#else + writel(0x00000012, &gpmc_cfg->config); +#endif /* * Disable the GPMC0 config set by ROM code - * It conflicts with our MPDB (both at 0x08000000) */ writel(0, &gpmc_cfg->cs[0].config7); + sdelay(1000); + /* enable chip-select specific configurations */ + enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); } diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index 39ff257..cf86046 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -9,7 +9,6 @@ obj-y := lowlevel_init.o obj-y += board.o obj-y += clock.o -obj-y += mem.o obj-y += sys_info.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index ad97132..4baca11 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -372,6 +372,38 @@ struct vcores_data dra752_volts = { .iva.pmic = &tps659038, }; +struct vcores_data dra722_volts = { + .mpu.value = 1000, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = 0x23, + .mpu.pmic = &tps659038, + + .eve.value = 1000, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = 0x2f, + .eve.pmic = &tps659038, + + .gpu.value = 1000, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = 0x2f, + .gpu.pmic = &tps659038, + + .core.value = 1000, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = 0x27, + .core.pmic = &tps659038, + + .iva.value = 1000, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = 0x2f, + .iva.pmic = &tps659038, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -558,6 +590,13 @@ void hw_data_init(void) *ctrl = &dra7xx_ctrl; break; + case DRA722_ES1_0: + *prcm = &dra7xx_prcm; + *dplls_data = &dra7xx_dplls; + *omap_vcores = &dra722_volts; + *ctrl = &dra7xx_ctrl; + break; + default: printf("\n INVALID OMAP REVISION "); } @@ -580,6 +619,7 @@ void get_ioregs(const struct ctrl_ioregs **regs) break; case DRA752_ES1_0: case DRA752_ES1_1: + case DRA722_ES1_0: *regs = &ioregs_dra7xx_es1; break; diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 93feb16..a8a474a 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -336,6 +336,9 @@ void init_omap_revision(void) case DRA752_CONTROL_ID_CODE_ES1_1: *omap_si_rev = DRA752_ES1_1; break; + case DRA722_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = DRA722_ES1_0; + break; default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; } diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 7292161..ff08ef4 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -447,10 +447,10 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_wkup_control_spare_r = 0x4AE0C5B4, .control_wkup_control_spare_r_c0 = 0x4AE0C5B8, .control_srcomp_east_side_wkup = 0x4AE0C5BC, - .control_efuse_1 = 0x4AE0C5C0, - .control_efuse_2 = 0x4AE0C5C4, - .control_efuse_3 = 0x4AE0C5C8, - .control_efuse_4 = 0x4AE0C5CC, + .control_efuse_1 = 0x4AE0C5C8, + .control_efuse_2 = 0x4AE0C5CC, + .control_efuse_3 = 0x4AE0C5D0, + .control_efuse_4 = 0x4AE0C5D4, .control_efuse_13 = 0x4AE0C5F0, }; diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 16a91f9..e2ebab8 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -229,6 +229,17 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { .is_ma_present = 0x1 }; +/* + * DRA722 EVM EMIF1 CONFIGURATION + */ +const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80600100, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) { switch (omap_revision()) { @@ -255,6 +266,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) break; } break; + case DRA722_ES1_0: default: *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; } @@ -275,8 +287,11 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs break; case DRA752_ES1_0: case DRA752_ES1_1: - default: *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2; + break; + case DRA722_ES1_0: + default: + *dmm_lisa_regs = &lisa_map_2G_x_2; } } @@ -463,6 +478,7 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, break; case DRA752_ES1_0: case DRA752_ES1_1: + case DRA722_ES1_0: if (emif_nr == 1) { *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1; *size = @@ -630,6 +646,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations) break; case DRA752_ES1_0: case DRA752_ES1_1: + case DRA722_ES1_0: bug_00339_regs_ptr = dra_bug_00339_regs; *iterations = sizeof(dra_bug_00339_regs)/ sizeof(dra_bug_00339_regs[0]); diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c index f49f990..46d6e60 100644 --- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c +++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c @@ -913,7 +913,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { /* SEL_SCIF3 [2] */ FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, /* SEL_IEB [2] */ - FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, + FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, /* SEL_MMC [1] */ FN_SEL_MMC_0, FN_SEL_MMC_1, /* SEL_SCIF5 [1] */ diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 7626b5c..816d0c5 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -14,6 +14,9 @@ void lowlevel_init(void) { } +#define ZYNQ_SILICON_VER_MASK 0xF0000000 +#define ZYNQ_SILICON_VER_SHIFT 28 + int arch_cpu_init(void) { zynq_slcr_unlock(); @@ -42,6 +45,16 @@ int arch_cpu_init(void) return 0; } +unsigned int zynq_get_silicon_version(void) +{ + unsigned int ver; + + ver = (readl(&devcfg_base->mctrl) & + ZYNQ_SILICON_VER_MASK) >> ZYNQ_SILICON_VER_SHIFT; + + return ver; +} + void reset_cpu(ulong addr) { zynq_slcr_cpu_reset(); diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/cpu/armv7/zynq/ddrc.c index ba6a6ae..e0ed3bf 100644 --- a/arch/arm/cpu/armv7/zynq/ddrc.c +++ b/arch/arm/cpu/armv7/zynq/ddrc.c @@ -40,11 +40,8 @@ void zynq_ddrc_init(void) * first stage bootloader. To get ECC to work all memory has * been initialized by writing any value. */ - memset(0, 0, 1 * 1024 * 1024); + memset((void *)0, 0, 1 * 1024 * 1024); } else { puts("Memory: ECC disabled\n"); } - - if (width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT) - gd->ram_size /= 2; } diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index d7c1882..934ccc3 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -8,26 +8,75 @@ #include <asm/io.h> #include <malloc.h> #include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> #include <asm/arch/clk.h> #define SLCR_LOCK_MAGIC 0x767B #define SLCR_UNLOCK_MAGIC 0xDF0D +#define SLCR_USB_L1_SEL 0x04 + #define SLCR_IDCODE_MASK 0x1F000 #define SLCR_IDCODE_SHIFT 12 +/* + * zynq_slcr_mio_get_status - Get the status of MIO peripheral. + * + * @peri_name: Name of the peripheral for checking MIO status + * @get_pins: Pointer to array of get pin for this peripheral + * @num_pins: Number of pins for this peripheral + * @mask: Mask value + * @check_val: Required check value to get the status of periph + */ +struct zynq_slcr_mio_get_status { + const char *peri_name; + const int *get_pins; + int num_pins; + u32 mask; + u32 check_val; +}; + +static const int usb0_pins[] = { + 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39 +}; + +static const int usb1_pins[] = { + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51 +}; + +static const struct zynq_slcr_mio_get_status mio_periphs[] = { + { + "usb0", + usb0_pins, + ARRAY_SIZE(usb0_pins), + SLCR_USB_L1_SEL, + SLCR_USB_L1_SEL, + }, + { + "usb1", + usb1_pins, + ARRAY_SIZE(usb1_pins), + SLCR_USB_L1_SEL, + SLCR_USB_L1_SEL, + }, +}; + static int slcr_lock = 1; /* 1 means locked, 0 means unlocked */ void zynq_slcr_lock(void) { - if (!slcr_lock) + if (!slcr_lock) { writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock); + slcr_lock = 1; + } } void zynq_slcr_unlock(void) { - if (slcr_lock) + if (slcr_lock) { writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock); + slcr_lock = 0; + } } /* Reset the entire system */ @@ -82,7 +131,7 @@ void zynq_slcr_devcfg_disable(void) { zynq_slcr_unlock(); - /* Disable AXI interface */ + /* Disable AXI interface by asserting FPGA resets */ writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl); /* Set Level Shifters DT618760 */ @@ -98,7 +147,7 @@ void zynq_slcr_devcfg_enable(void) /* Set Level Shifters DT618760 */ writel(0xF, &slcr_base->lvl_shftr_en); - /* Disable AXI interface */ + /* Enable AXI interface by de-asserting FPGA resets */ writel(0x0, &slcr_base->fpga_rst_ctrl); zynq_slcr_lock(); @@ -115,3 +164,33 @@ u32 zynq_slcr_get_idcode(void) return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >> SLCR_IDCODE_SHIFT; } + +/* + * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral. + * + * @periph: Name of the peripheral + * + * Returns count to indicate the number of pins configured for the + * given @periph. + */ +int zynq_slcr_get_mio_pin_status(const char *periph) +{ + const struct zynq_slcr_mio_get_status *mio_ptr; + int val, i, j; + int mio = 0; + + for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) { + if (strcmp(periph, mio_periphs[i].peri_name) == 0) { + mio_ptr = &mio_periphs[i]; + for (j = 0; j < mio_ptr->num_pins; j++) { + val = readl(&slcr_base->mio_pin + [mio_ptr->get_pins[j]]); + if ((val & mio_ptr->mask) == mio_ptr->check_val) + mio++; + } + break; + } + } + + return mio; +} diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/cpu/armv7/zynq/spl.c index fcad762..d73e5cb 100644 --- a/arch/arm/cpu/armv7/zynq/spl.c +++ b/arch/arm/cpu/armv7/zynq/spl.c @@ -28,6 +28,13 @@ void board_init_f(ulong dummy) board_init_r(NULL, 0); } +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + board_init(); +} +#endif + u32 spl_boot_device(void) { u32 mode; @@ -67,3 +74,11 @@ int spl_start_uboot(void) return 0; } #endif + +__weak void ps7_init(void) +{ + /* + * This function is overridden by the one in + * board/xilinx/zynq/ps7_init.c, if it exists. + */ +} diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index f20b8bd..2d076f1 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -10,4 +10,198 @@ / { compatible = "xlnx,zynq-7000"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + clocks = <&clkc 3>; + clock-latency = <1000>; + operating-points = < + /* kHz uV */ + 666667 1000000 + 333334 1000000 + 222223 1000000 + >; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + clocks = <&clkc 3>; + }; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 5 4>, <0 6 4>; + interrupt-parent = <&intc>; + reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges; + + i2c0: zynq-i2c@e0004000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <&clkc 38>; + interrupt-parent = <&intc>; + interrupts = <0 25 4>; + reg = <0xe0004000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: zynq-i2c@e0005000 { + compatible = "cdns,i2c-r1p10"; + status = "disabled"; + clocks = <&clkc 39>; + interrupt-parent = <&intc>; + interrupts = <0 48 4>; + reg = <0xe0005000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + intc: interrupt-controller@f8f01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0xF8F01000 0x1000>, + <0xF8F00100 0x100>; + }; + + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xF8F02000 0x1000>; + arm,data-latency = <3 2 2>; + arm,tag-latency = <2 2 2>; + cache-unified; + cache-level = <2>; + }; + + uart0: uart@e0000000 { + compatible = "xlnx,xuartps"; + status = "disabled"; + clocks = <&clkc 23>, <&clkc 40>; + clock-names = "ref_clk", "aper_clk"; + reg = <0xE0000000 0x1000>; + interrupts = <0 27 4>; + }; + + uart1: uart@e0001000 { + compatible = "xlnx,xuartps"; + status = "disabled"; + clocks = <&clkc 24>, <&clkc 41>; + clock-names = "ref_clk", "aper_clk"; + reg = <0xE0001000 0x1000>; + interrupts = <0 50 4>; + }; + + gem0: ethernet@e000b000 { + compatible = "cdns,gem"; + reg = <0xe000b000 0x4000>; + status = "disabled"; + interrupts = <0 22 4>; + clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; + clock-names = "pclk", "hclk", "tx_clk"; + }; + + gem1: ethernet@e000c000 { + compatible = "cdns,gem"; + reg = <0xe000c000 0x4000>; + status = "disabled"; + interrupts = <0 45 4>; + clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; + clock-names = "pclk", "hclk", "tx_clk"; + }; + + sdhci0: ps7-sdhci@e0100000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 21>, <&clkc 32>; + interrupt-parent = <&intc>; + interrupts = <0 24 4>; + reg = <0xe0100000 0x1000>; + } ; + + sdhci1: ps7-sdhci@e0101000 { + compatible = "arasan,sdhci-8.9a"; + status = "disabled"; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 22>, <&clkc 33>; + interrupt-parent = <&intc>; + interrupts = <0 47 4>; + reg = <0xe0101000 0x1000>; + } ; + + slcr: slcr@f8000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "xlnx,zynq-slcr", "syscon"; + reg = <0xF8000000 0x1000>; + ranges; + clkc: clkc@100 { + #clock-cells = <1>; + compatible = "xlnx,ps7-clkc"; + ps-clk-frequency = <33333333>; + fclk-enable = <0>; + clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", + "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", + "dci", "lqspi", "smc", "pcap", "gem0", "gem1", + "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", + "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", + "dma", "usb0_aper", "usb1_aper", "gem0_aper", + "gem1_aper", "sdio0_aper", "sdio1_aper", + "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", + "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", + "gpio_aper", "lqspi_aper", "smc_aper", "swdt", + "dbg_trc", "dbg_apb"; + reg = <0x100 0x100>; + }; + }; + + global_timer: timer@f8f00200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0xf8f00200 0x20>; + interrupts = <1 11 0x301>; + interrupt-parent = <&intc>; + clocks = <&clkc 4>; + }; + + ttc0: ttc0@f8001000 { + interrupt-parent = <&intc>; + interrupts = < 0 10 4 0 11 4 0 12 4 >; + compatible = "cdns,ttc"; + clocks = <&clkc 6>; + reg = <0xF8001000 0x1000>; + }; + + ttc1: ttc1@f8002000 { + interrupt-parent = <&intc>; + interrupts = < 0 37 4 0 38 4 0 39 4 >; + compatible = "cdns,ttc"; + clocks = <&clkc 6>; + reg = <0xF8002000 0x1000>; + }; + scutimer: scutimer@f8f00600 { + interrupt-parent = <&intc>; + interrupts = < 1 13 0x301 >; + compatible = "arm,cortex-a9-twd-timer"; + reg = < 0xf8f00600 0x20 >; + clocks = <&clkc 4>; + } ; + }; }; diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index 6da71c1..c373a2c 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -11,4 +11,13 @@ / { model = "Zynq MicroZED Board"; compatible = "xlnx,zynq-microzed", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 667dc28..4fa0b00 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -11,4 +11,13 @@ / { model = "Zynq ZC702 Board"; compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index 526fc88..2a80195 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -11,4 +11,13 @@ / { model = "Zynq ZC706 Board"; compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 8b542a1..5e661749 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -11,4 +11,13 @@ / { model = "Zynq ZC770 XM010 Board"; compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc770-xm012.dts b/arch/arm/dts/zynq-zc770-xm012.dts index 0379a07..127a661 100644 --- a/arch/arm/dts/zynq-zc770-xm012.dts +++ b/arch/arm/dts/zynq-zc770-xm012.dts @@ -11,4 +11,13 @@ / { model = "Zynq ZC770 XM012 Board"; compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zc770-xm013.dts b/arch/arm/dts/zynq-zc770-xm013.dts index a4f9e05..c61c7e7 100644 --- a/arch/arm/dts/zynq-zc770-xm013.dts +++ b/arch/arm/dts/zynq-zc770-xm013.dts @@ -11,4 +11,13 @@ / { model = "Zynq ZC770 XM013 Board"; compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0 0x40000000>; + }; }; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index 91a5deb..70cc8a6 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -11,4 +11,13 @@ / { model = "Zynq ZED Board"; compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; + + aliases { + serial0 = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0 0x20000000>; + }; }; diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 91ff2ad..33a82fc 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -11,6 +11,7 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ #include <linux/mtd/omap_gpmc.h> +#include <asm/ti-common/sys_proto.h> #include <asm/arch/cpu.h> #define BOARD_REV_ID 0x0 diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 1804191..bdb1435 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -344,6 +344,7 @@ enum { * MAP - Map this CS to which address(GPMC address space)- Absolute address * >>24 before being used. */ +#define GPMC_SIZE_256M 0x0 #define GPMC_SIZE_128M 0x8 #define GPMC_SIZE_64M 0xC #define GPMC_SIZE_32M 0xE diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index c21fb54..f7595ae 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -12,6 +12,8 @@ #include <asm/types.h> #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ +#include <asm/arch/hardware.h> + #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct gptimer { @@ -57,9 +59,6 @@ struct watchdog { #define TCLR_AR (0x1 << 1) #define TCLR_PRE (0x1 << 5) -/* GPMC BASE */ -#define GPMC_BASE (OMAP44XX_GPMC_BASE) - /* I2C base */ #define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000) #define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000) diff --git a/arch/arm/include/asm/arch-omap4/hardware.h b/arch/arm/include/asm/arch-omap4/hardware.h new file mode 100644 index 0000000..f7011b4 --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/hardware.h @@ -0,0 +1,26 @@ +/* + * hardware.h + * + * hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OMAP_HARDWARE_H +#define __OMAP_HARDWARE_H + +#include <asm/arch/omap.h> + +/* + * Common hardware definitions + */ + +/* BCH Error Location Module */ +#define ELM_BASE 0x48078000 + +/* GPMC Base address */ +#define GPMC_BASE 0x50000000 + +#endif diff --git a/arch/arm/include/asm/arch-omap4/mem.h b/arch/arm/include/asm/arch-omap4/mem.h new file mode 100644 index 0000000..d2e708b --- /dev/null +++ b/arch/arm/include/asm/arch-omap4/mem.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * + * Author + * Mansoor Ahamed <mansoor.ahamed@ti.com> + * + * Initial Code from: + * Richard Woodruff <r-woodruff2@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MEM_H_ +#define _MEM_H_ + +/* + * GPMC settings - + * Definitions is as per the following format + * #define <PART>_GPMC_CONFIG<x> <value> + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL + */ +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define M_NAND_GPMC_CONFIG1 0x00000800 +#define M_NAND_GPMC_CONFIG2 0x001e1e00 +#define M_NAND_GPMC_CONFIG3 0x001e1e00 +#define M_NAND_GPMC_CONFIG4 0x16051807 +#define M_NAND_GPMC_CONFIG5 0x00151e1e +#define M_NAND_GPMC_CONFIG6 0x16000f80 +#define M_NAND_GPMC_CONFIG7 0x00000008 + +#define STNOR_GPMC_CONFIG1 0x00001200 +#define STNOR_GPMC_CONFIG2 0x00101000 +#define STNOR_GPMC_CONFIG3 0x00030301 +#define STNOR_GPMC_CONFIG4 0x10041004 +#define STNOR_GPMC_CONFIG5 0x000C1010 +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000F48 + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h index f66da0d..d43dc26 100644 --- a/arch/arm/include/asm/arch-omap4/omap.h +++ b/arch/arm/include/asm/arch-omap4/omap.h @@ -60,9 +60,6 @@ /* Watchdog Timer2 - MPU watchdog */ #define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000) -/* GPMC */ -#define OMAP44XX_GPMC_BASE 0x50000000 - /* * Hardware Register Details */ diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 80172f3..83d858f 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -14,6 +14,7 @@ #include <asm/omap_common.h> #include <linux/mtd/omap_gpmc.h> #include <asm/arch/mux_omap4.h> +#include <asm/ti-common/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -53,54 +54,4 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); void setup_warmreset_time(void); - -static inline u32 running_from_sdram(void) -{ - u32 pc; - asm volatile ("mov %0, pc" : "=r" (pc)); - return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) && - (pc < OMAP44XX_DRAM_ADDR_SPACE_END)); -} - -static inline u8 uboot_loaded_by_spl(void) -{ - /* - * u-boot can be running from sdram either because of configuration - * Header or by SPL. If because of CH, then the romcode sets the - * CHSETTINGS executed bit to true in the boot parameter structure that - * it passes to the bootloader.This parameter is stored in the ch_flags - * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a - * mandatory section if CH is present. - */ - if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) - return 0; - else - return running_from_sdram(); -} -/* - * The basic hardware init of OMAP(s_init()) can happen in 4 - * different contexts: - * 1. SPL running from SRAM - * 2. U-Boot running from FLASH - * 3. Non-XIP U-Boot loaded to SDRAM by SPL - * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the - * Configuration Header feature - * - * This function finds this context. - * Defining as inline may help in compiling out unused functions in SPL - */ -static inline u32 omap_hw_init_context(void) -{ -#ifdef CONFIG_SPL_BUILD - return OMAP_INIT_CONTEXT_SPL; -#else - if (uboot_loaded_by_spl()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; - else if (running_from_sdram()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; - else - return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; -#endif -} - #endif diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index 5f1d745..6109b92 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -14,6 +14,8 @@ #include <asm/types.h> #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */ +#include <asm/arch/hardware.h> + #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ struct gptimer { @@ -63,9 +65,6 @@ struct watchdog { #define TCLR_AR (0x1 << 1) #define TCLR_PRE (0x1 << 5) -/* GPMC BASE */ -#define GPMC_BASE (OMAP54XX_GPMC_BASE) - /* I2C base */ #define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000) #define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000) diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h new file mode 100644 index 0000000..f7011b4 --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/hardware.h @@ -0,0 +1,26 @@ +/* + * hardware.h + * + * hardware specific header + * + * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __OMAP_HARDWARE_H +#define __OMAP_HARDWARE_H + +#include <asm/arch/omap.h> + +/* + * Common hardware definitions + */ + +/* BCH Error Location Module */ +#define ELM_BASE 0x48078000 + +/* GPMC Base address */ +#define GPMC_BASE 0x50000000 + +#endif diff --git a/arch/arm/include/asm/arch-omap5/mem.h b/arch/arm/include/asm/arch-omap5/mem.h new file mode 100644 index 0000000..d2e708b --- /dev/null +++ b/arch/arm/include/asm/arch-omap5/mem.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * + * Author + * Mansoor Ahamed <mansoor.ahamed@ti.com> + * + * Initial Code from: + * Richard Woodruff <r-woodruff2@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MEM_H_ +#define _MEM_H_ + +/* + * GPMC settings - + * Definitions is as per the following format + * #define <PART>_GPMC_CONFIG<x> <value> + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * M_NAND - Micron NAND + * STNOR - STMicrolelctronics M29W128GL + */ +#define GPMC_SIZE_256M 0x0 +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define M_NAND_GPMC_CONFIG1 0x00000800 +#define M_NAND_GPMC_CONFIG2 0x001e1e00 +#define M_NAND_GPMC_CONFIG3 0x001e1e00 +#define M_NAND_GPMC_CONFIG4 0x16051807 +#define M_NAND_GPMC_CONFIG5 0x00151e1e +#define M_NAND_GPMC_CONFIG6 0x16000f80 +#define M_NAND_GPMC_CONFIG7 0x00000008 + +#define STNOR_GPMC_CONFIG1 0x00001200 +#define STNOR_GPMC_CONFIG2 0x00101000 +#define STNOR_GPMC_CONFIG3 0x00030301 +#define STNOR_GPMC_CONFIG4 0x10041004 +#define STNOR_GPMC_CONFIG5 0x000C1010 +#define STNOR_GPMC_CONFIG6 0x08070280 +#define STNOR_GPMC_CONFIG7 0x00000F48 + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index e35a81a..b9600cf 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -23,11 +23,6 @@ #define OMAP54XX_L4_WKUP_BASE 0x4Ae00000 #define OMAP54XX_L4_PER_BASE 0x48000000 -#define OMAP54XX_DRAM_ADDR_SPACE_START 0x80000000 -#define OMAP54XX_DRAM_ADDR_SPACE_END 0xFFFFFFFF -#define DRAM_ADDR_SPACE_START OMAP54XX_DRAM_ADDR_SPACE_START -#define DRAM_ADDR_SPACE_END OMAP54XX_DRAM_ADDR_SPACE_END - /* CONTROL ID CODE */ #define CONTROL_CORE_ID_CODE 0x4A002204 #define CONTROL_WKUP_ID_CODE 0x4AE0C204 @@ -45,6 +40,7 @@ #define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F #define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F #define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F +#define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F /* UART */ #define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000) @@ -60,9 +56,6 @@ /* Watchdog Timer2 - MPU watchdog */ #define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000) -/* GPMC */ -#define OMAP54XX_GPMC_BASE 0x50000000 - /* QSPI */ #define QSPI_BASE 0x4B300000 diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index bf12c73..1038303 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -14,6 +14,7 @@ #include <asm/omap_common.h> #include <linux/mtd/omap_gpmc.h> #include <asm/arch/clock.h> +#include <asm/ti-common/sys_proto.h> DECLARE_GLOBAL_DATA_PTR; @@ -56,55 +57,6 @@ void get_ioregs(const struct ctrl_ioregs **regs); void srcomp_enable(void); void setup_warmreset_time(void); -static inline u32 running_from_sdram(void) -{ - u32 pc; - asm volatile ("mov %0, pc" : "=r" (pc)); - return ((pc >= OMAP54XX_DRAM_ADDR_SPACE_START) && - (pc < OMAP54XX_DRAM_ADDR_SPACE_END)); -} - -static inline u8 uboot_loaded_by_spl(void) -{ - /* - * u-boot can be running from sdram either because of configuration - * Header or by SPL. If because of CH, then the romcode sets the - * CHSETTINGS executed bit to true in the boot parameter structure that - * it passes to the bootloader.This parameter is stored in the ch_flags - * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a - * mandatory section if CH is present. - */ - if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) - return 0; - else - return running_from_sdram(); -} -/* - * The basic hardware init of OMAP(s_init()) can happen in 4 - * different contexts: - * 1. SPL running from SRAM - * 2. U-Boot running from FLASH - * 3. Non-XIP U-Boot loaded to SDRAM by SPL - * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the - * Configuration Header feature - * - * This function finds this context. - * Defining as inline may help in compiling out unused functions in SPL - */ -static inline u32 omap_hw_init_context(void) -{ -#ifdef CONFIG_SPL_BUILD - return OMAP_INIT_CONTEXT_SPL; -#else - if (uboot_loaded_by_spl()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; - else if (running_from_sdram()) - return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; - else - return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; -#endif -} - static inline u32 div_round_up(u32 num, u32 den) { return (num + den - 1)/den; diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h index 444e361..74b5f1d 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h @@ -1,5 +1,5 @@ -#ifndef __ASM_R8A7790_H__ -#define __ASM_R8A7790_H__ +#ifndef __ASM_R8A7790_GPIO_H__ +#define __ASM_R8A7790_GPIO_H__ /* Pin Function Controller: * GPIO_FN_xx - GPIO used to select pin function @@ -384,4 +384,4 @@ enum { GPIO_FN_TCLK1_B, }; -#endif /* __ASM_R8A7790_H__ */ +#endif /* __ASM_R8A7790_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h index d3cf0c1..42e8259 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h @@ -1,5 +1,5 @@ -#ifndef __ASM_R8A7791_H__ -#define __ASM_R8A7791_H__ +#ifndef __ASM_R8A7791_GPIO_H__ +#define __ASM_R8A7791_GPIO_H__ /* Pin Function Controller: * GPIO_FN_xx - GPIO used to select pin function @@ -435,4 +435,4 @@ enum { GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B, }; -#endif /* __ASM_R8A7791_H__ */ +#endif /* __ASM_R8A7791_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h index 4791825..592c524 100644 --- a/arch/arm/include/asm/arch-rmobile/r8a7791.h +++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h @@ -45,6 +45,7 @@ #define DBSC3_1_QOS_W13_BASE 0xE67A2D00 #define DBSC3_1_QOS_W14_BASE 0xE67A2E00 #define DBSC3_1_QOS_W15_BASE 0xE67A2F00 +#define DBSC3_1_DBADJ2 0xE67A00C8 #define R8A7791_CUT_ES2X 2 #define IS_R8A7791_ES2() \ diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h index 4331d31..41240f3 100644 --- a/arch/arm/include/asm/arch-rmobile/rcar-base.h +++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h @@ -21,6 +21,14 @@ #define GPIO5_BASE 0xE6055000 #define SH_QSPI_BASE 0xE6B10000 +/* SCIF */ +#define SCIF0_BASE 0xE6E60000 +#define SCIF1_BASE 0xE6E68000 +#define SCIF2_BASE 0xE6E58000 +#define SCIF3_BASE 0xE6EA8000 +#define SCIF4_BASE 0xE6EE0000 +#define SCIF5_BASE 0xE6EE8000 + #define S3C_BASE 0xE6784000 #define S3C_INT_BASE 0xE6784A00 #define S3C_MEDIA_BASE 0xE6784B00 diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 39184da..2aede0c 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -22,9 +22,12 @@ #define ZYNQ_SPI_BASEADDR0 0xE0006000 #define ZYNQ_SPI_BASEADDR1 0xE0007000 #define ZYNQ_DDRC_BASEADDR 0xF8006000 +#define ZYNQ_EFUSE_BASEADDR 0xF800D000 +#define ZYNQ_USB_BASEADDR0 0xE0002000 +#define ZYNQ_USB_BASEADDR1 0xE0003000 /* Bootmode setting values */ -#define ZYNQ_BM_MASK 0xF +#define ZYNQ_BM_MASK 0x7 #define ZYNQ_BM_NOR 0x2 #define ZYNQ_BM_SD 0x5 #define ZYNQ_BM_JTAG 0x0 @@ -130,4 +133,12 @@ struct ddrc_regs { }; #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR) +struct efuse_reg { + u32 reserved1[4]; + u32 status; + u32 reserved2[3]; +}; + +#define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR) + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index a68e1b3..53c30ec 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -15,7 +15,9 @@ extern void zynq_slcr_devcfg_disable(void); extern void zynq_slcr_devcfg_enable(void); extern u32 zynq_slcr_get_boot_mode(void); extern u32 zynq_slcr_get_idcode(void); +extern int zynq_slcr_get_mio_pin_status(const char *periph); extern void zynq_ddrc_init(void); +extern unsigned int zynq_get_silicon_version(void); /* Driver extern functions */ extern int zynq_sdhci_init(u32 regbase); diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 729723a..d1344ee 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -576,12 +576,6 @@ s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb); void usb_fake_mac_from_die_id(u32 *id); -/* HW Init Context */ -#define OMAP_INIT_CONTEXT_SPL 0 -#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1 -#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 -#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 - /* ABB */ #define OMAP_ABB_NOMINAL_OPP 0 #define OMAP_ABB_FAST_OPP 1 @@ -645,6 +639,7 @@ static inline u8 is_dra7xx(void) /* DRA7XX */ #define DRA752_ES1_0 0x07520100 #define DRA752_ES1_1 0x07520110 +#define DRA722_ES1_0 0x07220100 /* * SRAM scratch space entries diff --git a/arch/arm/include/asm/ti-common/sys_proto.h b/arch/arm/include/asm/ti-common/sys_proto.h new file mode 100644 index 0000000..d3ab75f --- /dev/null +++ b/arch/arm/include/asm/ti-common/sys_proto.h @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2014 + * Texas Instruments, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _TI_COMMON_SYS_PROTO_H_ +#define _TI_COMMON_SYS_PROTO_H_ + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_OMAP_COMMON +#define TI_ARMV7_DRAM_ADDR_SPACE_START 0x80000000 +#define TI_ARMV7_DRAM_ADDR_SPACE_END 0xFFFFFFFF + +#define OMAP_INIT_CONTEXT_SPL 0 +#define OMAP_INIT_CONTEXT_UBOOT_FROM_NOR 1 +#define OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL 2 +#define OMAP_INIT_CONTEXT_UBOOT_AFTER_CH 3 + +static inline u32 running_from_sdram(void) +{ + u32 pc; + asm volatile ("mov %0, pc" : "=r" (pc)); + return ((pc >= TI_ARMV7_DRAM_ADDR_SPACE_START) && + (pc < TI_ARMV7_DRAM_ADDR_SPACE_END)); +} + +static inline u8 uboot_loaded_by_spl(void) +{ + /* + * u-boot can be running from sdram either because of configuration + * Header or by SPL. If because of CH, then the romcode sets the + * CHSETTINGS executed bit to true in the boot parameter structure that + * it passes to the bootloader.This parameter is stored in the ch_flags + * variable by both SPL and u-boot.Check out for CHSETTINGS, which is a + * mandatory section if CH is present. + */ + if ((gd->arch.omap_boot_params.ch_flags) & (CH_FLAGS_CHSETTINGS)) + return 0; + else + return running_from_sdram(); +} + +/* + * The basic hardware init of OMAP(s_init()) can happen in 4 + * different contexts: + * 1. SPL running from SRAM + * 2. U-Boot running from FLASH + * 3. Non-XIP U-Boot loaded to SDRAM by SPL + * 4. Non-XIP U-Boot loaded to SDRAM by ROM code using the + * Configuration Header feature + * + * This function finds this context. + * Defining as inline may help in compiling out unused functions in SPL + */ +static inline u32 omap_hw_init_context(void) +{ +#ifdef CONFIG_SPL_BUILD + return OMAP_INIT_CONTEXT_SPL; +#else + if (uboot_loaded_by_spl()) + return OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL; + else if (running_from_sdram()) + return OMAP_INIT_CONTEXT_UBOOT_AFTER_CH; + else + return OMAP_INIT_CONTEXT_UBOOT_FROM_NOR; +#endif +} +#endif + +#endif |