summaryrefslogtreecommitdiff
path: root/arch/arm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/cpu/armv8/zynqmp/Kconfig1
-rw-r--r--arch/arm/dts/s5pc1xx-goni.dts165
-rw-r--r--arch/arm/dts/sunxi-u-boot.dtsi14
-rw-r--r--arch/arm/dts/tegra124-nyan-big-u-boot.dtsi15
-rw-r--r--arch/arm/dts/tegra124-nyan-big.dts2
-rw-r--r--arch/arm/dts/tegra20-u-boot.dtsi8
-rw-r--r--arch/arm/dts/tegra20.dtsi2
-rw-r--r--arch/arm/dts/zynq-7000.dtsi4
-rw-r--r--arch/arm/dts/zynqmp.dtsi1
-rw-r--r--arch/arm/include/asm/arch-zynqmp/hardware.h2
-rw-r--r--arch/arm/mach-mvebu/armada8k/cpu.c58
11 files changed, 251 insertions, 21 deletions
diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index f354aae..e175e6e 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -43,6 +43,7 @@ config SYS_CONFIG_NAME
config BOOT_INIT_FILE
string "boot.bin init register filename"
+ depends on SPL
default ""
help
Add register writes to boot.bin format (max 256 pairs).
diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts
index 7bbfe59..e80132d 100644
--- a/arch/arm/dts/s5pc1xx-goni.dts
+++ b/arch/arm/dts/s5pc1xx-goni.dts
@@ -19,6 +19,7 @@
serial2 = "/serial@e2900800";
console = "/serial@e2900800";
pinctrl0 = &pinctrl0;
+ i2c3 = &i2c_pmic;
};
pinctrl0: pinctrl@e0200000 {
@@ -32,4 +33,168 @@
id = <2>;
};
+ i2c_pmic: i2c-pmic {
+ compatible = "i2c-gpio";
+ gpios = <&gpj4 0 0>, /* sda */
+ <&gpj4 3 0>; /* scl */
+ i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ pmic@66 {
+ compatible = "maxim,max8998";
+ reg = <0x66 0 0>;
+
+ voltage-regulators {
+ ldo2_reg: LDO2 {
+ regulator-compatible = "LDO2";
+ regulator-name = "VALIVE_1.1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-compatible = "LDO3";
+ regulator-name = "VUSB+MIPI_1.1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-compatible = "LDO4";
+ regulator-name = "VADC_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-compatible = "LDO5";
+ regulator-name = "VTF_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-compatible = "LDO6";
+ regulator-name = "VCC_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-compatible = "LDO7";
+ regulator-name = "VLCD_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ ldo8_reg: LDO8 {
+ regulator-compatible = "LDO8";
+ regulator-name = "VUSB+VDAC_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo9_reg: LDO9 {
+ regulator-compatible = "LDO9";
+ regulator-name = "VCC+VCAM_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo10_reg: LDO10 {
+ regulator-compatible = "LDO10";
+ regulator-name = "VPLL_1.1V";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-boot-on;
+ };
+
+ ldo11_reg: LDO11 {
+ regulator-compatible = "LDO11";
+ regulator-name = "CAM_IO_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo12_reg: LDO12 {
+ regulator-compatible = "LDO12";
+ regulator-name = "CAM_ISP_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ ldo13_reg: LDO13 {
+ regulator-compatible = "LDO13";
+ regulator-name = "CAM_A_2.8V";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo14_reg: LDO14 {
+ regulator-compatible = "LDO14";
+ regulator-name = "CAM_CIF_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo15_reg: LDO15 {
+ regulator-compatible = "LDO15";
+ regulator-name = "CAM_AF_3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ ldo16_reg: LDO16 {
+ regulator-compatible = "LDO16";
+ regulator-name = "VMIPI_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo17_reg: LDO17 {
+ regulator-compatible = "LDO17";
+ regulator-name = "CAM_8M_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-compatible = "BUCK1";
+ regulator-name = "VARM_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-compatible = "BUCK2";
+ regulator-name = "VINT_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-compatible = "BUCK3";
+ regulator-name = "VCC_1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-compatible = "BUCK4";
+ regulator-name = "CAM_CORE_1.2V";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+ };
+ };
+ };
+
};
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
new file mode 100644
index 0000000..5adfd9b
--- /dev/null
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -0,0 +1,14 @@
+#include <config.h>
+
+/ {
+ binman {
+ filename = "u-boot-sunxi-with-spl.bin";
+ pad-byte = <0xff>;
+ blob {
+ filename = "spl/sunxi-spl.bin";
+ };
+ u-boot-img {
+ pos = <CONFIG_SPL_PAD_TO>;
+ };
+ };
+};
diff --git a/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
new file mode 100644
index 0000000..fff1d78
--- /dev/null
+++ b/arch/arm/dts/tegra124-nyan-big-u-boot.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2016 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ host1x@50000000 {
+ u-boot,dm-pre-reloc;
+ dc@54200000 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts
index 3758395..62f89d0 100644
--- a/arch/arm/dts/tegra124-nyan-big.dts
+++ b/arch/arm/dts/tegra124-nyan-big.dts
@@ -27,9 +27,7 @@
};
host1x@50000000 {
- u-boot,dm-pre-reloc;
dc@54200000 {
- u-boot,dm-pre-reloc;
display-timings {
timing@0 {
clock-frequency = <69500000>;
diff --git a/arch/arm/dts/tegra20-u-boot.dtsi b/arch/arm/dts/tegra20-u-boot.dtsi
new file mode 100644
index 0000000..9b9835d
--- /dev/null
+++ b/arch/arm/dts/tegra20-u-boot.dtsi
@@ -0,0 +1,8 @@
+/ {
+ host1x@50000000 {
+ u-boot,dm-pre-reloc;
+ dc@54200000 {
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index 84bb1b0..e21ee25 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -10,7 +10,6 @@
interrupt-parent = <&lic>;
host1x@50000000 {
- u-boot,dm-pre-reloc;
compatible = "nvidia,tegra20-host1x", "simple-bus";
reg = <0x50000000 0x00024000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
@@ -78,7 +77,6 @@
};
dc@54200000 {
- u-boot,dm-pre-reloc;
compatible = "nvidia,tegra20-dc";
reg = <0x54200000 0x00040000>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 6df0329..668f54e 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -16,7 +16,7 @@
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
@@ -30,7 +30,7 @@
>;
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index ab5c243..de1f160 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -7,6 +7,7 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
+
/ {
compatible = "xlnx,zynqmp";
#address-cells = <2>;
diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index 5908c50..041b43c 100644
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -18,8 +18,6 @@
#define ARASAN_NAND_BASEADDR 0xFF100000
-#define ZYNQMP_SATA_BASEADDR 0xFD0C0000
-
#define ZYNQMP_USB0_XHCI_BASEADDR 0xFE200000
#define ZYNQMP_USB1_XHCI_BASEADDR 0xFE300000
diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c
index 2719d68..2325e9a 100644
--- a/arch/arm/mach-mvebu/armada8k/cpu.c
+++ b/arch/arm/mach-mvebu/armada8k/cpu.c
@@ -21,7 +21,33 @@ DECLARE_GLOBAL_DATA_PTR;
#define RFU_GLOBAL_SW_RST (MVEBU_RFU_BASE + 0x84)
#define RFU_SW_RESET_OFFSET 0
+/*
+ * The following table includes all memory regions for Armada 7k and
+ * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets
+ * define these regions at the beginning of the struct so that they
+ * can be easier removed later dynamically if an Armada 7k device is detected.
+ * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt
+ */
+#define ARMADA_7K8K_COMMON_REGIONS_START 2
static struct mm_region mvebu_mem_map[] = {
+ /* Armada 80x0 memory regions include the CP1 (slave) units */
+ {
+ /* SRAM, MMIO regions - CP110 slave region */
+ .phys = 0xf4000000UL,
+ .virt = 0xf4000000UL,
+ .size = 0x02000000UL, /* 32MiB internal registers */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ },
+ {
+ /* PCI CP1 regions */
+ .phys = 0xfa000000UL,
+ .virt = 0xfa000000UL,
+ .size = 0x04000000UL, /* 64MiB CP110 slave PCI space */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ },
+ /* Armada 80x0 and 70x0 common memory regions start here */
{
/* RAM */
.phys = 0x0UL,
@@ -47,29 +73,35 @@ static struct mm_region mvebu_mem_map[] = {
PTE_BLOCK_NON_SHARE
},
{
- /* SRAM, MMIO regions - CP110 slave region */
- .phys = 0xf4000000UL,
- .virt = 0xf4000000UL,
- .size = 0x02000000UL, /* 32MiB internal registers */
+ /* PCI CP0 regions */
+ .phys = 0xf6000000UL,
+ .virt = 0xf6000000UL,
+ .size = 0x04000000UL, /* 64MiB CP110 master PCI space */
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE
},
{
- /* PCI regions */
- .phys = 0xf8000000UL,
- .virt = 0xf8000000UL,
- .size = 0x08000000UL, /* 128MiB PCI space (master & slave) */
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE
- },
- {
- /* List terminator */
0,
}
};
struct mm_region *mem_map = mvebu_mem_map;
+void enable_caches(void)
+{
+ /*
+ * Armada 7k is not equipped with the CP110 slave CP. In case this
+ * code runs on an Armada 7k device, lets remove the CP110 slave
+ * entries from the memory mapping by moving the start to the
+ * common regions.
+ */
+ if (of_machine_is_compatible("marvell,armada7040"))
+ mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START];
+
+ icache_enable();
+ dcache_enable();
+}
+
void reset_cpu(ulong ignored)
{
u32 reg;
generated by cgit v0.10.2 at 2024-08-11 13:52:50 (GMT)