diff options
Diffstat (limited to 'arch/arm')
105 files changed, 3617 insertions, 4050 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index bb64b9c..64e0ee4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -588,6 +588,7 @@ config ARCH_OMAP2PLUS bool "TI OMAP2+" select CPU_V7 select SPL_BOARD_INIT if SPL + select SPL_STACK_R if SPL select SUPPORT_SPL imply FIT @@ -630,6 +631,14 @@ config ARCH_MX5 select CPU_V7 select BOARD_EARLY_INIT_F +config ARCH_QEMU + bool "QEMU Virtual Platform" + select CPU_V7 + select ARCH_SUPPORT_PSCI + select DM + select DM_SERIAL + select OF_CONTROL + config ARCH_RMOBILE bool "Renesas ARM SoCs" select DM @@ -693,8 +702,7 @@ config ARCH_SUNXI select USB_STORAGE if DISTRO_DEFAULTS select USB_KEYBOARD if DISTRO_DEFAULTS select USE_TINY_PRINTF - imply CMD_FASTBOOT - imply FASTBOOT + imply CMD_GPT imply FAT_WRITE imply PRE_CONSOLE_BUFFER imply SPL_GPIO_SUPPORT @@ -704,7 +712,7 @@ config ARCH_SUNXI imply SPL_MMC_SUPPORT if MMC imply SPL_POWER_SUPPORT imply SPL_SERIAL_SUPPORT - imply USB_FUNCTION_FASTBOOT + imply USB_GADGET config TARGET_TS4600 bool "Support TS4600" @@ -1114,6 +1122,9 @@ config ARCH_ROCKCHIP imply FAT_WRITE imply USB_FUNCTION_FASTBOOT imply SPL_SYSRESET + imply TPL_SYSRESET + imply ADC + imply SARADC_ROCKCHIP config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" @@ -1168,6 +1179,8 @@ source "arch/arm/mach-rmobile/Kconfig" source "arch/arm/mach-meson/Kconfig" +source "arch/arm/mach-qemu/Kconfig" + source "arch/arm/mach-rockchip/Kconfig" source "arch/arm/mach-s5pc1xx/Kconfig" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 6698c04..a90ee0a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -260,8 +260,8 @@ static void erratum_rcw_src(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 static void erratum_a009203(void) { - u8 __iomem *ptr; #ifdef CONFIG_SYS_I2C + u8 __iomem *ptr; #ifdef I2C1_BASE_ADDR ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); @@ -297,7 +297,9 @@ void bypass_smmu(void) void fsl_lsch3_early_init_f(void) { erratum_rcw_src(); +#ifdef CONFIG_FSL_IFC init_early_memctl_regs(); /* tighten IFC timing */ +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 erratum_a009203(); #endif @@ -323,11 +325,14 @@ int sata_init(void) { struct ccsr_ahci __iomem *ccsr_ahci; +#ifdef CONFIG_SYS_SATA2 ccsr_ahci = (void *)CONFIG_SYS_SATA2; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); +#endif +#ifdef CONFIG_SYS_SATA1 ccsr_ahci = (void *)CONFIG_SYS_SATA1; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); @@ -335,6 +340,7 @@ int sata_init(void) ahci_init((void __iomem *)CONFIG_SYS_SATA1); scsi_scan(false); +#endif return 0; } diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7c062f0..5b90280 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -313,8 +313,8 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \ sun8i-r16-parrot.dtb dtb-$(CONFIG_MACH_SUN8I_A83T) += \ sun8i-a83t-allwinner-h8homlet-v2.dtb \ - sun8i-a83t-cubietruck-plus.dtb \ - sun8i-a83t-sinovoip-bpi-m3.dtb + sun8i-a83t-bananapi-m3.dtb \ + sun8i-a83t-cubietruck-plus.dtb dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h2-plus-orangepi-zero.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ diff --git a/arch/arm/dts/am3517-evm-u-boot.dtsi b/arch/arm/dts/am3517-evm-u-boot.dtsi new file mode 100644 index 0000000..24a67db --- /dev/null +++ b/arch/arm/dts/am3517-evm-u-boot.dtsi @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2017 + * Logic PD - http://www.logicpd.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + chosen { + stdout-path = &uart3; + }; +}; diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts new file mode 100644 index 0000000..0e4a125 --- /dev/null +++ b/arch/arm/dts/am3517-evm.dts @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am3517.dtsi" + +/ { + model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)"; + compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vmmc_fixed: vmmc { + compatible = "regulator-fixed"; + regulator-name = "vmmc_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&davinci_emac { + status = "okay"; +}; + +&davinci_mdio { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; +}; + +&i2c2 { + clock-frequency = <400000>; +}; + +&i2c3 { + clock-frequency = <400000>; +}; + +&mmc1 { + vmmc-supply = <&vmmc_fixed>; + bus-width = <4>; +}; + +&mmc2 { + status = "disabled"; +}; + +&mmc3 { + status = "disabled"; +}; + diff --git a/arch/arm/dts/am3517-u-boot.dtsi b/arch/arm/dts/am3517-u-boot.dtsi new file mode 100644 index 0000000..2190052 --- /dev/null +++ b/arch/arm/dts/am3517-u-boot.dtsi @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2017 + * Logic PD - http://www.logicpd.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +&uart4 { + reg-shift = <2>; +}; diff --git a/arch/arm/dts/am3517.dtsi b/arch/arm/dts/am3517.dtsi new file mode 100644 index 0000000..00da3f2 --- /dev/null +++ b/arch/arm/dts/am3517.dtsi @@ -0,0 +1,107 @@ +/* + * Device Tree Source for am3517 SoC + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include "omap3.dtsi" + +/ { + aliases { + serial3 = &uart4; + can = &hecc; + }; + + ocp@68000000 { + am35x_otg_hs: am35x_otg_hs@5c040000 { + compatible = "ti,omap3-musb"; + ti,hwmods = "am35x_otg_hs"; + status = "disabled"; + reg = <0x5c040000 0x1000>; + interrupts = <71>; + interrupt-names = "mc"; + }; + + davinci_emac: ethernet@0x5c000000 { + compatible = "ti,am3517-emac"; + ti,hwmods = "davinci_emac"; + status = "disabled"; + reg = <0x5c000000 0x30000>; + interrupts = <67 68 69 70>; + syscon = <&scm_conf>; + ti,davinci-ctrl-reg-offset = <0x10000>; + ti,davinci-ctrl-mod-reg-offset = <0>; + ti,davinci-ctrl-ram-offset = <0x20000>; + ti,davinci-ctrl-ram-size = <0x2000>; + ti,davinci-rmii-en = /bits/ 8 <1>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + + davinci_mdio: ethernet@0x5c030000 { + compatible = "ti,davinci_mdio"; + ti,hwmods = "davinci_mdio"; + status = "disabled"; + reg = <0x5c030000 0x1000>; + bus_freq = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + uart4: serial@4809e000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart4"; + status = "disabled"; + reg = <0x4809e000 0x400>; + interrupts = <84>; + dmas = <&sdma 55 &sdma 54>; + dma-names = "tx", "rx"; + clock-frequency = <48000000>; + }; + + omap3_pmx_core2: pinmux@480025d8 { + compatible = "ti,omap3-padconf", "pinctrl-single"; + reg = <0x480025d8 0x24>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <1>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + + hecc: can@5c050000 { + compatible = "ti,am3517-hecc"; + status = "disabled"; + reg = <0x5c050000 0x80>, + <0x5c053000 0x180>, + <0x5c052000 0x200>; + reg-names = "hecc", "hecc-ram", "mbx"; + interrupts = <24>; + clocks = <&hecc_ck>; + }; + }; +}; + +&iva { + status = "disabled"; +}; + +&mailbox { + status = "disabled"; +}; + +&mmu_isp { + status = "disabled"; +}; + +&smartreflex_mpu_iva { + status = "disabled"; +}; + +/include/ "am35xx-clocks.dtsi" +/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi" diff --git a/arch/arm/dts/am35xx-clocks.dtsi b/arch/arm/dts/am35xx-clocks.dtsi new file mode 100644 index 0000000..00dd1f0 --- /dev/null +++ b/arch/arm/dts/am35xx-clocks.dtsi @@ -0,0 +1,128 @@ +/* + * Device Tree Source for OMAP3 clock data + * + * Copyright (C) 2013 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +&scm_clocks { + emac_ick: emac_ick@32c { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&ipss_ick>; + reg = <0x032c>; + ti,bit-shift = <1>; + }; + + emac_fck: emac_fck@32c { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&rmii_ck>; + reg = <0x032c>; + ti,bit-shift = <9>; + }; + + vpfe_ick: vpfe_ick@32c { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&ipss_ick>; + reg = <0x032c>; + ti,bit-shift = <2>; + }; + + vpfe_fck: vpfe_fck@32c { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&pclk_ck>; + reg = <0x032c>; + ti,bit-shift = <10>; + }; + + hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&ipss_ick>; + reg = <0x032c>; + ti,bit-shift = <0>; + }; + + hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&sys_ck>; + reg = <0x032c>; + ti,bit-shift = <8>; + }; + + hecc_ck: hecc_ck@32c { + #clock-cells = <0>; + compatible = "ti,am35xx-gate-clock"; + clocks = <&sys_ck>; + reg = <0x032c>; + ti,bit-shift = <3>; + }; +}; +&cm_clocks { + ipss_ick: ipss_ick@a10 { + #clock-cells = <0>; + compatible = "ti,am35xx-interface-clock"; + clocks = <&core_l3_ick>; + reg = <0x0a10>; + ti,bit-shift = <4>; + }; + + rmii_ck: rmii_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + pclk_ck: pclk_ck { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <27000000>; + }; + + uart4_ick_am35xx: uart4_ick_am35xx@a10 { + #clock-cells = <0>; + compatible = "ti,omap3-interface-clock"; + clocks = <&core_l4_ick>; + reg = <0x0a10>; + ti,bit-shift = <23>; + }; + + uart4_fck_am35xx: uart4_fck_am35xx@a00 { + #clock-cells = <0>; + compatible = "ti,wait-gate-clock"; + clocks = <&core_48m_fck>; + reg = <0x0a00>; + ti,bit-shift = <23>; + }; +}; + +&cm_clockdomains { + core_l3_clkdm: core_l3_clkdm { + compatible = "ti,clockdomain"; + clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>, + <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>, + <&hecc_ck>; + }; + + core_l4_clkdm: core_l4_clkdm { + compatible = "ti,clockdomain"; + clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>, + <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>, + <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>, + <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>, + <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>, + <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>, + <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>, + <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>, + <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>, + <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>, + <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, + <&uart4_ick_am35xx>, <&uart4_fck_am35xx>; + }; +}; diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts b/arch/arm/dts/at91-sama5d2_xplained.dts index b00aaa2..01326a1 100644 --- a/arch/arm/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/dts/at91-sama5d2_xplained.dts @@ -41,6 +41,31 @@ }; apb { + hlcdc: hlcdc@f0000000 { + atmel,vl-bpix = <4>; + atmel,guard-time = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>; + status = "okay"; + u-boot,dm-pre-reloc; + + display-timings { + u-boot,dm-pre-reloc; + 480x272 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hsync-len = <41>; + hfront-porch = <2>; + hback-porch = <2>; + vfront-porch = <2>; + vback-porch = <2>; + vsync-len = <11>; + u-boot,dm-pre-reloc; + }; + }; + }; + qspi0: spi@f0020000 { status = "okay"; @@ -117,6 +142,41 @@ bias-disable; }; + pinctrl_lcd_base: pinctrl_lcd_base { + pinmux = <PIN_PC30__LCDVSYNC>, + <PIN_PC31__LCDHSYNC>, + <PIN_PD1__LCDDEN>, + <PIN_PD0__LCDPCK>; + bias-disable; + }; + + pinctrl_lcd_pwm: pinctrl_lcd_pwm { + pinmux = <PIN_PC28__LCDPWM>; + bias-disable; + }; + + pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 { + pinmux = <PIN_PC10__LCDDAT2>, + <PIN_PC11__LCDDAT3>, + <PIN_PC12__LCDDAT4>, + <PIN_PC13__LCDDAT5>, + <PIN_PC14__LCDDAT6>, + <PIN_PC15__LCDDAT7>, + <PIN_PC16__LCDDAT10>, + <PIN_PC17__LCDDAT11>, + <PIN_PC18__LCDDAT12>, + <PIN_PC19__LCDDAT13>, + <PIN_PC20__LCDDAT14>, + <PIN_PC21__LCDDAT15>, + <PIN_PC22__LCDDAT18>, + <PIN_PC23__LCDDAT19>, + <PIN_PC24__LCDDAT20>, + <PIN_PC25__LCDDAT21>, + <PIN_PC26__LCDDAT22>, + <PIN_PC27__LCDDAT23>; + bias-disable; + }; + pinctrl_macb0_phy_irq: macb0_phy_irq { pinmux = <PIN_PC9__GPIO>; bias-disable; diff --git a/arch/arm/dts/at91-sama5d4_xplained.dts b/arch/arm/dts/at91-sama5d4_xplained.dts index 0592b31..ea35dc2 100644 --- a/arch/arm/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/dts/at91-sama5d4_xplained.dts @@ -74,6 +74,31 @@ ahb { apb { + hlcdc: hlcdc@f0000000 { + atmel,vl-bpix = <4>; + atmel,guard-time = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb888>; + status = "okay"; + u-boot,dm-pre-reloc; + + display-timings { + u-boot,dm-pre-reloc; + 480x272 { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hsync-len = <41>; + hfront-porch = <2>; + hback-porch = <2>; + vfront-porch = <2>; + vback-porch = <2>; + vsync-len = <11>; + u-boot,dm-pre-reloc; + }; + }; + }; + spi0: spi@f8010000 { u-boot,dm-pre-reloc; cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; diff --git a/arch/arm/dts/at91-sama5d4ek.dts b/arch/arm/dts/at91-sama5d4ek.dts index b965f5b..a5d7545 100644 --- a/arch/arm/dts/at91-sama5d4ek.dts +++ b/arch/arm/dts/at91-sama5d4ek.dts @@ -75,6 +75,32 @@ ahb { apb { + hlcdc: hlcdc@f0000000 { + atmel,vl-bpix = <4>; + atmel,output-mode = <18>; + atmel,guard-time = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>; + status = "okay"; + u-boot,dm-pre-reloc; + + display-timings { + u-boot,dm-pre-reloc; + 800x480 { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hsync-len = <5>; + hfront-porch = <128>; + hback-porch = <0>; + vfront-porch = <23>; + vback-porch = <22>; + vsync-len = <5>; + u-boot,dm-pre-reloc; + }; + }; + }; + adc0: adc@fc034000 { pinctrl-names = "default"; pinctrl-0 = < diff --git a/arch/arm/dts/axp223.dtsi b/arch/arm/dts/axp223.dtsi new file mode 100644 index 0000000..b91b6c1 --- /dev/null +++ b/arch/arm/dts/axp223.dtsi @@ -0,0 +1,58 @@ +/* + * Copyright 2016 Free Electrons + * + * Quentin Schulz <quentin.schulz@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * AXP223 Integrated Power Management Chip + * http://www.x-powers.com/product/AXP22X.php + * http://dl.linux-sunxi.org/AXP/AXP223-en.pdf + * + * The AXP223 shares most of its logic with the AXP221 but it has some + * differences, for the VBUS driver for example. + */ + +#include "axp22x.dtsi" + +&usb_power_supply { + compatible = "x-powers,axp223-usb-power-supply"; +}; diff --git a/arch/arm/dts/axp22x.dtsi b/arch/arm/dts/axp22x.dtsi index 458b668..87fb08e 100644 --- a/arch/arm/dts/axp22x.dtsi +++ b/arch/arm/dts/axp22x.dtsi @@ -52,6 +52,16 @@ interrupt-controller; #interrupt-cells = <1>; + ac_power_supply: ac-power-supply { + compatible = "x-powers,axp221-ac-power-supply"; + status = "disabled"; + }; + + battery_power_supply: battery-power-supply { + compatible = "x-powers,axp221-battery-power-supply"; + status = "disabled"; + }; + regulators { /* Default work frequency for buck regulators */ x-powers,dcdc-freq = <3000>; diff --git a/arch/arm/dts/da850-evm-u-boot.dtsi b/arch/arm/dts/da850-evm-u-boot.dtsi new file mode 100644 index 0000000..5cc5a81 --- /dev/null +++ b/arch/arm/dts/da850-evm-u-boot.dtsi @@ -0,0 +1,23 @@ +/* + * da850-evm U-Boot Additions + * + * Copyright (C) 2017 Logic PD, Inc. + * Copyright (C) Adam Ford + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + chosen { + stdout-path = &serial2; + }; + + aliases { + i2c0 = &i2c0; + spi0 = &spi1; + }; +}; + +&flash { + compatible = "m25p64", "spi-flash"; +}; diff --git a/arch/arm/dts/da850-evm.dts b/arch/arm/dts/da850-evm.dts new file mode 100644 index 0000000..67e72bc --- /dev/null +++ b/arch/arm/dts/da850-evm.dts @@ -0,0 +1,304 @@ +/* + * Device Tree for DA850 EVM board + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation, version 2. + */ +/dts-v1/; +#include "da850.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + compatible = "ti,da850-evm", "ti,da850"; + model = "DA850/AM1808/OMAP-L138 EVM"; + + soc@1c00000 { + pmx_core: pinmux@14120 { + status = "okay"; + + mcasp0_pins: pinmux_mcasp0_pins { + pinctrl-single,bits = < + /* + * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR, + * AFSR, AMUTE + */ + 0x00 0x11111111 0xffffffff + /* AXR11, AXR12 */ + 0x04 0x00011000 0x000ff000 + >; + }; + nand_pins: nand_pins { + pinctrl-single,bits = < + /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */ + 0x1c 0x10110110 0xf0ff0ff0 + /* + * EMA_D[0], EMA_D[1], EMA_D[2], + * EMA_D[3], EMA_D[4], EMA_D[5], + * EMA_D[6], EMA_D[7] + */ + 0x24 0x11111111 0xffffffff + /* EMA_A[1], EMA_A[2] */ + 0x30 0x01100000 0x0ff00000 + >; + }; + }; + serial0: serial@42000 { + status = "okay"; + }; + serial1: serial@10c000 { + status = "okay"; + }; + serial2: serial@10d000 { + status = "okay"; + }; + rtc0: rtc@23000 { + status = "okay"; + }; + i2c0: i2c@22000 { + status = "okay"; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + tps: tps@48 { + reg = <0x48>; + }; + tlv320aic3106: tlv320aic3106@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x18>; + status = "okay"; + + /* Regulators */ + IOVDD-supply = <&vdcdc2_reg>; + /* Derived from VBAT: Baseboard 3.3V / 1.8V */ + AVDD-supply = <&vbat>; + DRVDD-supply = <&vbat>; + DVDD-supply = <&vbat>; + }; + tca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + wdt: wdt@21000 { + status = "okay"; + }; + mmc0: mmc@40000 { + max-frequency = <50000000>; + bus-width = <4>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + }; + spi1: spi@30e000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins &spi1_cs0_pin>; + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p64"; + spi-max-frequency = <30000000>; + m25p,fast-read; + reg = <0>; + partition@0 { + label = "U-Boot-SPL"; + reg = <0x00000000 0x00010000>; + read-only; + }; + partition@1 { + label = "U-Boot"; + reg = <0x00010000 0x00080000>; + read-only; + }; + partition@2 { + label = "U-Boot-Env"; + reg = <0x00090000 0x00010000>; + read-only; + }; + partition@3 { + label = "Kernel"; + reg = <0x000a0000 0x00280000>; + }; + partition@4 { + label = "Filesystem"; + reg = <0x00320000 0x00400000>; + }; + partition@5 { + label = "MAC-Address"; + reg = <0x007f0000 0x00010000>; + read-only; + }; + }; + }; + mdio: mdio@224000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + bus_freq = <2200000>; + }; + eth0: ethernet@220000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mii_pins>; + }; + gpio: gpio@226000 { + status = "okay"; + }; + }; + vbat: fixedregulator0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "DA850/OMAP-L138 EVM"; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out"; + simple-audio-card,routing = + "LINE1L", "Line In", + "LINE1R", "Line In", + "Line Out", "LLOUT", + "Line Out", "RLOUT"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + system-clock-frequency = <24576000>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <24576000>; + }; + }; +}; + +/include/ "tps6507x.dtsi" + +&tps { + vdcdc1_2-supply = <&vbat>; + vdcdc3-supply = <&vbat>; + vldo1_2-supply = <&vbat>; + + regulators { + vdcdc1_reg: regulator@0 { + regulator-name = "VDCDC1_3.3V"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3450000>; + regulator-always-on; + regulator-boot-on; + }; + + vdcdc2_reg: regulator@1 { + regulator-name = "VDCDC2_3.3V"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <3450000>; + regulator-always-on; + regulator-boot-on; + ti,defdcdc_default = <1>; + }; + + vdcdc3_reg: regulator@2 { + regulator-name = "VDCDC3_1.2V"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + ti,defdcdc_default = <1>; + }; + + ldo1_reg: regulator@3 { + regulator-name = "LDO1_1.8V"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo2_reg: regulator@4 { + regulator-name = "LDO2_1.2V"; + regulator-min-microvolt = <1140000>; + regulator-max-microvolt = <1320000>; + regulator-always-on; + regulator-boot-on; + }; + }; +}; + +&mcasp0 { + #sound-dai-cells = <0>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 0 0 + 0 0 0 0 + 0 0 0 1 + 2 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&edma0 { + ti,edma-reserved-slot-ranges = <32 50>; +}; + +&edma1 { + ti,edma-reserved-slot-ranges = <32 90>; +}; + +&aemif { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins>; + status = "ok"; + cs3 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <3>; + + nand@2000000,0 { + compatible = "ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x02000000 0x02000000 + 1 0x00000000 0x00008000>; + + ti,davinci-chipselect = <1>; + ti,davinci-mask-ale = <0>; + ti,davinci-mask-cle = <0>; + ti,davinci-mask-chipsel = <0>; + ti,davinci-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + ti,davinci-nand-use-bbt; + }; + }; +}; + +&vpif { + pinctrl-names = "default"; + pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>; + status = "okay"; +}; diff --git a/arch/arm/dts/da850.dtsi b/arch/arm/dts/da850.dtsi new file mode 100644 index 0000000..02e2f8f --- /dev/null +++ b/arch/arm/dts/da850.dtsi @@ -0,0 +1,581 @@ +/* + * Copyright 2012 DENX Software Engineering GmbH + * Heiko Schocher <hs@denx.de> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + arm { + #address-cells = <1>; + #size-cells = <1>; + ranges; + intc: interrupt-controller@fffee000 { + compatible = "ti,cp-intc"; + interrupt-controller; + #interrupt-cells = <1>; + ti,intc-size = <101>; + reg = <0xfffee000 0x2000>; + }; + }; + + aliases { + spi0 = &spi0; + }; + + soc@1c00000 { + compatible = "simple-bus"; + model = "da850"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x01c00000 0x400000>; + interrupt-parent = <&intc>; + + pmx_core: pinmux@14120 { + compatible = "pinctrl-single"; + reg = <0x14120 0x50>; + #address-cells = <1>; + #size-cells = <0>; + #pinctrl-cells = <2>; + pinctrl-single,bit-per-mux; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xf>; + status = "disabled"; + + serial0_rtscts_pins: pinmux_serial0_rtscts_pins { + pinctrl-single,bits = < + /* UART0_RTS UART0_CTS */ + 0x0c 0x22000000 0xff000000 + >; + }; + serial0_rxtx_pins: pinmux_serial0_rxtx_pins { + pinctrl-single,bits = < + /* UART0_TXD UART0_RXD */ + 0x0c 0x00220000 0x00ff0000 + >; + }; + serial1_rtscts_pins: pinmux_serial1_rtscts_pins { + pinctrl-single,bits = < + /* UART1_CTS UART1_RTS */ + 0x00 0x00440000 0x00ff0000 + >; + }; + serial1_rxtx_pins: pinmux_serial1_rxtx_pins { + pinctrl-single,bits = < + /* UART1_TXD UART1_RXD */ + 0x10 0x22000000 0xff000000 + >; + }; + serial2_rtscts_pins: pinmux_serial2_rtscts_pins { + pinctrl-single,bits = < + /* UART2_CTS UART2_RTS */ + 0x00 0x44000000 0xff000000 + >; + }; + serial2_rxtx_pins: pinmux_serial2_rxtx_pins { + pinctrl-single,bits = < + /* UART2_TXD UART2_RXD */ + 0x10 0x00220000 0x00ff0000 + >; + }; + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,bits = < + /* I2C0_SDA,I2C0_SCL */ + 0x10 0x00002200 0x0000ff00 + >; + }; + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,bits = < + /* I2C1_SDA, I2C1_SCL */ + 0x10 0x00440000 0x00ff0000 + >; + }; + mmc0_pins: pinmux_mmc_pins { + pinctrl-single,bits = < + /* MMCSD0_DAT[3] MMCSD0_DAT[2] + * MMCSD0_DAT[1] MMCSD0_DAT[0] + * MMCSD0_CMD MMCSD0_CLK + */ + 0x28 0x00222222 0x00ffffff + >; + }; + ehrpwm0a_pins: pinmux_ehrpwm0a_pins { + pinctrl-single,bits = < + /* EPWM0A */ + 0xc 0x00000002 0x0000000f + >; + }; + ehrpwm0b_pins: pinmux_ehrpwm0b_pins { + pinctrl-single,bits = < + /* EPWM0B */ + 0xc 0x00000020 0x000000f0 + >; + }; + ehrpwm1a_pins: pinmux_ehrpwm1a_pins { + pinctrl-single,bits = < + /* EPWM1A */ + 0x14 0x00000002 0x0000000f + >; + }; + ehrpwm1b_pins: pinmux_ehrpwm1b_pins { + pinctrl-single,bits = < + /* EPWM1B */ + 0x14 0x00000020 0x000000f0 + >; + }; + ecap0_pins: pinmux_ecap0_pins { + pinctrl-single,bits = < + /* ECAP0_APWM0 */ + 0x8 0x20000000 0xf0000000 + >; + }; + ecap1_pins: pinmux_ecap1_pins { + pinctrl-single,bits = < + /* ECAP1_APWM1 */ + 0x4 0x40000000 0xf0000000 + >; + }; + ecap2_pins: pinmux_ecap2_pins { + pinctrl-single,bits = < + /* ECAP2_APWM2 */ + 0x4 0x00000004 0x0000000f + >; + }; + spi0_pins: pinmux_spi0_pins { + pinctrl-single,bits = < + /* SIMO, SOMI, CLK */ + 0xc 0x00001101 0x0000ff0f + >; + }; + spi0_cs0_pin: pinmux_spi0_cs0 { + pinctrl-single,bits = < + /* CS0 */ + 0x10 0x00000010 0x000000f0 + >; + }; + spi0_cs3_pin: pinmux_spi0_cs3_pin { + pinctrl-single,bits = < + /* CS3 */ + 0xc 0x01000000 0x0f000000 + >; + }; + spi1_pins: pinmux_spi1_pins { + pinctrl-single,bits = < + /* SIMO, SOMI, CLK */ + 0x14 0x00110100 0x00ff0f00 + >; + }; + spi1_cs0_pin: pinmux_spi1_cs0 { + pinctrl-single,bits = < + /* CS0 */ + 0x14 0x00000010 0x000000f0 + >; + }; + mdio_pins: pinmux_mdio_pins { + pinctrl-single,bits = < + /* MDIO_CLK, MDIO_D */ + 0x10 0x00000088 0x000000ff + >; + }; + mii_pins: pinmux_mii_pins { + pinctrl-single,bits = < + /* + * MII_TXEN, MII_TXCLK, MII_COL + * MII_TXD_3, MII_TXD_2, MII_TXD_1 + * MII_TXD_0 + */ + 0x8 0x88888880 0xfffffff0 + /* + * MII_RXER, MII_CRS, MII_RXCLK + * MII_RXDV, MII_RXD_3, MII_RXD_2 + * MII_RXD_1, MII_RXD_0 + */ + 0xc 0x88888888 0xffffffff + >; + }; + lcd_pins: pinmux_lcd_pins { + pinctrl-single,bits = < + /* + * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5], + * LCD_D[6], LCD_D[7] + */ + 0x40 0x22222200 0xffffff00 + /* + * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13], + * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1] + */ + 0x44 0x22222222 0xffffffff + /* LCD_D[8], LCD_D[9] */ + 0x48 0x00000022 0x000000ff + + /* LCD_PCLK */ + 0x48 0x02000000 0x0f000000 + /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */ + 0x4c 0x02000022 0x0f0000ff + >; + }; + vpif_capture_pins: vpif_capture_pins { + pinctrl-single,bits = < + /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */ + 0x38 0x11111111 0xffffffff + /* VP_DIN[10..15,0..1] */ + 0x3c 0x11111111 0xffffffff + /* VP_DIN[8..9] */ + 0x40 0x00000011 0x000000ff + >; + }; + vpif_display_pins: vpif_display_pins { + pinctrl-single,bits = < + /* VP_DOUT[2..7] */ + 0x40 0x11111100 0xffffff00 + /* VP_DOUT[10..15,0..1] */ + 0x44 0x11111111 0xffffffff + /* VP_DOUT[8..9] */ + 0x48 0x00000011 0x000000ff + /* + * VP_CLKOUT3, VP_CLKIN3, + * VP_CLKOUT2, VP_CLKIN2 + */ + 0x4c 0x00111100 0x00ffff00 + >; + }; + }; + prictrl: priority-controller@14110 { + compatible = "ti,da850-mstpri"; + reg = <0x14110 0x0c>; + status = "disabled"; + }; + cfgchip: chip-controller@1417c { + compatible = "ti,da830-cfgchip", "syscon", "simple-mfd"; + reg = <0x1417c 0x14>; + + usb_phy: usb-phy { + compatible = "ti,da830-usb-phy"; + #phy-cells = <1>; + status = "disabled"; + }; + }; + edma0: edma@0 { + compatible = "ti,edma3-tpcc"; + /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */ + reg = <0x0 0x8000>; + reg-names = "edma3_cc"; + interrupts = <11 12>; + interrupt-names = "edma3_ccint", "edma3_ccerrint"; + #dma-cells = <2>; + + ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; + }; + edma0_tptc0: tptc@8000 { + compatible = "ti,edma3-tptc"; + reg = <0x8000 0x400>; + interrupts = <13>; + interrupt-names = "edm3_tcerrint"; + }; + edma0_tptc1: tptc@8400 { + compatible = "ti,edma3-tptc"; + reg = <0x8400 0x400>; + interrupts = <32>; + interrupt-names = "edm3_tcerrint"; + }; + edma1: edma@230000 { + compatible = "ti,edma3-tpcc"; + /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */ + reg = <0x230000 0x8000>; + reg-names = "edma3_cc"; + interrupts = <93 94>; + interrupt-names = "edma3_ccint", "edma3_ccerrint"; + #dma-cells = <2>; + + ti,tptcs = <&edma1_tptc0 7>; + }; + edma1_tptc0: tptc@238000 { + compatible = "ti,edma3-tptc"; + reg = <0x238000 0x400>; + interrupts = <95>; + interrupt-names = "edm3_tcerrint"; + }; + serial0: serial@42000 { + compatible = "ti,da830-uart", "ns16550a"; + reg = <0x42000 0x100>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <25>; + status = "disabled"; + }; + serial1: serial@10c000 { + compatible = "ti,da830-uart", "ns16550a"; + reg = <0x10c000 0x100>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <53>; + status = "disabled"; + }; + serial2: serial@10d000 { + compatible = "ti,da830-uart", "ns16550a"; + reg = <0x10d000 0x100>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <61>; + status = "disabled"; + }; + rtc0: rtc@23000 { + compatible = "ti,da830-rtc"; + reg = <0x23000 0x1000>; + interrupts = <19 + 19>; + status = "disabled"; + }; + i2c0: i2c@22000 { + compatible = "ti,davinci-i2c"; + reg = <0x22000 0x1000>; + interrupts = <15>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c1: i2c@228000 { + compatible = "ti,davinci-i2c"; + reg = <0x228000 0x1000>; + interrupts = <51>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + wdt: wdt@21000 { + compatible = "ti,davinci-wdt"; + reg = <0x21000 0x1000>; + status = "disabled"; + }; + mmc0: mmc@40000 { + compatible = "ti,da830-mmc"; + reg = <0x40000 0x1000>; + cap-sd-highspeed; + cap-mmc-highspeed; + interrupts = <16>; + dmas = <&edma0 16 0>, <&edma0 17 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + vpif: video@217000 { + compatible = "ti,da850-vpif"; + reg = <0x217000 0x1000>; + interrupts = <92>; + status = "disabled"; + + /* VPIF capture port */ + port@0 { + #address-cells = <1>; + #size-cells = <0>; + }; + + /* VPIF display port */ + port@1 { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + mmc1: mmc@21b000 { + compatible = "ti,da830-mmc"; + reg = <0x21b000 0x1000>; + cap-sd-highspeed; + cap-mmc-highspeed; + interrupts = <72>; + dmas = <&edma1 28 0>, <&edma1 29 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + ehrpwm0: pwm@300000 { + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x300000 0x2000>; + status = "disabled"; + }; + ehrpwm1: pwm@302000 { + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x302000 0x2000>; + status = "disabled"; + }; + ecap0: ecap@306000 { + compatible = "ti,da850-ecap", "ti,am3352-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x306000 0x80>; + status = "disabled"; + }; + ecap1: ecap@307000 { + compatible = "ti,da850-ecap", "ti,am3352-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x307000 0x80>; + status = "disabled"; + }; + ecap2: ecap@308000 { + compatible = "ti,da850-ecap", "ti,am3352-ecap", + "ti,am33xx-ecap"; + #pwm-cells = <3>; + reg = <0x308000 0x80>; + status = "disabled"; + }; + spi0: spi@41000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,da830-spi"; + reg = <0x41000 0x1000>; + num-cs = <6>; + ti,davinci-spi-intr-line = <1>; + interrupts = <20>; + dmas = <&edma0 14 0>, <&edma0 15 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi1: spi@30e000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,da830-spi"; + reg = <0x30e000 0x1000>; + num-cs = <4>; + ti,davinci-spi-intr-line = <1>; + interrupts = <56>; + dmas = <&edma0 18 0>, <&edma0 19 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + usb0: usb@200000 { + compatible = "ti,da830-musb"; + reg = <0x200000 0x1000>; + ranges; + interrupts = <58>; + interrupt-names = "mc"; + dr_mode = "otg"; + phys = <&usb_phy 0>; + phy-names = "usb-phy"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <1>; + + dmas = <&cppi41dma 0 0 &cppi41dma 1 0 + &cppi41dma 2 0 &cppi41dma 3 0 + &cppi41dma 0 1 &cppi41dma 1 1 + &cppi41dma 2 1 &cppi41dma 3 1>; + dma-names = + "rx1", "rx2", "rx3", "rx4", + "tx1", "tx2", "tx3", "tx4"; + + cppi41dma: dma-controller@201000 { + compatible = "ti,da830-cppi41"; + reg = <0x201000 0x1000 + 0x202000 0x1000 + 0x204000 0x4000>; + reg-names = "controller", + "scheduler", "queuemgr"; + interrupts = <58>; + #dma-cells = <2>; + #dma-channels = <4>; + status = "okay"; + }; + }; + sata: sata@218000 { + compatible = "ti,da850-ahci"; + reg = <0x218000 0x2000>, <0x22c018 0x4>; + interrupts = <67>; + status = "disabled"; + }; + mdio: mdio@224000 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x224000 0x1000>; + status = "disabled"; + }; + eth0: ethernet@220000 { + compatible = "ti,davinci-dm6467-emac"; + reg = <0x220000 0x4000>; + ti,davinci-ctrl-reg-offset = <0x3000>; + ti,davinci-ctrl-mod-reg-offset = <0x2000>; + ti,davinci-ctrl-ram-offset = <0>; + ti,davinci-ctrl-ram-size = <0x2000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <33 + 34 + 35 + 36 + >; + status = "disabled"; + }; + usb1: usb@225000 { + compatible = "ti,da830-ohci"; + reg = <0x225000 0x1000>; + interrupts = <59>; + phys = <&usb_phy 1>; + phy-names = "usb-phy"; + status = "disabled"; + }; + gpio: gpio@226000 { + compatible = "ti,dm6441-gpio"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x226000 0x1000>; + interrupts = <42 IRQ_TYPE_EDGE_BOTH + 43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH + 45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH + 47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH + 49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>; + ti,ngpio = <144>; + ti,davinci-gpio-unbanked = <0>; + status = "disabled"; + interrupt-controller; + #interrupt-cells = <2>; + }; + pinconf: pin-controller@22c00c { + compatible = "ti,da850-pupd"; + reg = <0x22c00c 0x8>; + status = "disabled"; + }; + + mcasp0: mcasp@100000 { + compatible = "ti,da830-mcasp-audio"; + reg = <0x100000 0x2000>, + <0x102000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <54>; + interrupt-names = "common"; + status = "disabled"; + dmas = <&edma0 1 1>, + <&edma0 0 1>; + dma-names = "tx", "rx"; + }; + + lcdc: display@213000 { + compatible = "ti,da850-tilcdc"; + reg = <0x213000 0x1000>; + interrupts = <52>; + max-pixelclock = <37500>; + status = "disabled"; + }; + }; + aemif: aemif@68000000 { + compatible = "ti,da850-aemif"; + #address-cells = <2>; + #size-cells = <1>; + + reg = <0x68000000 0x00008000>; + ranges = <0 0 0x60000000 0x08000000 + 1 0 0x68000000 0x00008000>; + status = "disabled"; + }; + memctrl: memory-controller@b0000000 { + compatible = "ti,da850-ddr-controller"; + reg = <0xb0000000 0xe8>; + status = "disabled"; + }; +}; diff --git a/arch/arm/dts/fsl-ls2081a-rdb.dts b/arch/arm/dts/fsl-ls2081a-rdb.dts index 6489362..aa4aa68 100644 --- a/arch/arm/dts/fsl-ls2081a-rdb.dts +++ b/arch/arm/dts/fsl-ls2081a-rdb.dts @@ -41,7 +41,7 @@ bus-num = <0>; status = "okay"; - qflash0: n25q512a@0 { + qflash0: s25fs512s@0 { #address-cells = <1>; #size-cells = <1>; compatible = "spi-flash"; @@ -49,7 +49,7 @@ reg = <0>; }; - qflash1: n25q512a@1 { + qflash1: s25fs512s@1 { #address-cells = <1>; #size-cells = <1>; compatible = "spi-flash"; diff --git a/arch/arm/dts/omap3.dtsi b/arch/arm/dts/omap3.dtsi index e6f9c9a..56c9472 100644 --- a/arch/arm/dts/omap3.dtsi +++ b/arch/arm/dts/omap3.dtsi @@ -716,14 +716,12 @@ usbhsohci: ohci@48064400 { compatible = "ti,ohci-omap3"; reg = <0x48064400 0x400>; - interrupt-parent = <&intc>; interrupts = <76>; }; usbhsehci: ehci@48064800 { compatible = "ti,ehci-omap"; reg = <0x48064800 0x400>; - interrupt-parent = <&intc>; interrupts = <77>; }; }; @@ -834,7 +832,6 @@ reg-names = "tx", "rx"; - interrupt-parent = <&intc>; interrupts = <67>, <68>; }; @@ -847,7 +844,6 @@ reg-names = "tx", "rx"; - interrupt-parent = <&intc>; interrupts = <69>, <70>; }; diff --git a/arch/arm/dts/omap5-u-boot.dtsi b/arch/arm/dts/omap5-u-boot.dtsi index 2eeed6f..fdaa692 100644 --- a/arch/arm/dts/omap5-u-boot.dtsi +++ b/arch/arm/dts/omap5-u-boot.dtsi @@ -60,10 +60,30 @@ }; }; +&gpio1 { + u-boot,dm-spl; +}; + &gpio2 { u-boot,dm-spl; }; +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpio6 { + u-boot,dm-spl; +}; + &gpio7 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index 64f1c2d..ae0b0a4 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -40,7 +40,6 @@ }; &dmc { - rockchip,sdram-channel = /bits/ 8 <1 10 3 2 1 0 15 15>; rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3 0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4 0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1 diff --git a/arch/arm/dts/rk3288-popmetal.dtsi b/arch/arm/dts/rk3288-popmetal.dtsi index dd6ce8b..63785eb 100644 --- a/arch/arm/dts/rk3288-popmetal.dtsi +++ b/arch/arm/dts/rk3288-popmetal.dtsi @@ -491,6 +491,10 @@ }; }; +&saradc { + status = "okay"; +}; + &tsadc { rockchip,hw-tshut-mode = <0>; rockchip,hw-tshut-polarity = <0>; diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index 8a14c65..3dd9d81 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -42,6 +42,10 @@ }; }; +&saradc { + status = "okay"; +}; + &uart2 { status = "okay"; }; @@ -87,3 +91,121 @@ vbus-supply = <&vcc5v0_host_xhci>; status = "okay"; }; + +&i2c1 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + status = "okay"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + gpio-controller; + #gpio-cells = <2>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <6001>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <6001>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_18: LDO_REG1 { + regulator-name = "vdd_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_18emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio2_a6 */ + }; + }; +}; + diff --git a/arch/arm/dts/rk3368-px5-evb.dts b/arch/arm/dts/rk3368-px5-evb.dts index c7478f7..e9c5eba 100644 --- a/arch/arm/dts/rk3368-px5-evb.dts +++ b/arch/arm/dts/rk3368-px5-evb.dts @@ -296,6 +296,10 @@ }; }; +&saradc { + status = "okay"; +}; + &tsadc { status = "okay"; rockchip,hw-tshut-mode = <0>; /* CRU */ diff --git a/arch/arm/dts/rk3368-sheep.dts b/arch/arm/dts/rk3368-sheep.dts index 7c190f7..27befad 100644 --- a/arch/arm/dts/rk3368-sheep.dts +++ b/arch/arm/dts/rk3368-sheep.dts @@ -260,6 +260,10 @@ }; }; +&saradc { + status = "okay"; +}; + &tsadc { status = "okay"; rockchip,hw-tshut-mode = <0>; /* CRU */ diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index be0c6d9..0e5d8d7 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -149,6 +149,10 @@ status = "okay"; }; +&saradc { + status = "okay"; +}; + &sdmmc { bus-width = <4>; status = "okay"; diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index a04878e..65ab380 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -20,7 +20,8 @@ chosen { stdout-path = "serial0:115200n8"; - u-boot,spl-boot-order = &spiflash, &sdhci, &sdmmc; + u-boot,spl-boot-order = \ + "same-as-spl", &spiflash, &sdhci, &sdmmc; }; aliases { @@ -100,6 +101,24 @@ regulator-max-microvolt = <3300000>; }; + /* + * The Qseven BIOS_DISABLE signal on the RK3399-Q7 keeps the on-module + * eMMC and SPI flash powered-down initially (in fact it keeps the + * reset signal asserted). Even though it is an enable signal, we + * model this as a regulator. + */ + bios_enable: bios_enable { + compatible = "regulator-fixed"; + u-boot,dm-pre-reloc; + regulator-name = "bios_enable"; + enable-active-low; + gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vccadc_ref: vccadc-ref { compatible = "regulator-fixed"; regulator-name = "vcc1v8_sys"; @@ -458,7 +477,7 @@ }; &pcie_phy { - status = "okay"; + status = "okay"; }; &pmu_io_domains { @@ -485,7 +504,7 @@ }; &sdmmc { - u-boot,dm-pre-reloc; + u-boot,dm-pre-reloc; clock-frequency = <150000000>; clock-freq-min-max = <100000 150000000>; supports-sd; @@ -532,10 +551,15 @@ status = "okay"; }; +&gpio3 { + u-boot,dm-pre-reloc; +}; + &pinctrl { /* Pins that are not explicitely used by any devices */ pinctrl-names = "default"; pinctrl-0 = <&puma_pin_hog>; + hog { puma_pin_hog: puma_pin_hog { rockchip,pins = @@ -575,7 +599,7 @@ i2c8 { i2c8_xfer_a: i2c8-xfer { rockchip,pins = <1 21 RK_FUNC_1 &pcfg_pull_up>, - <1 20 RK_FUNC_1 &pcfg_pull_up>; + <1 20 RK_FUNC_1 &pcfg_pull_up>; }; }; }; @@ -651,4 +675,3 @@ &spi5 { status = "okay"; }; - diff --git a/arch/arm/dts/rv1108-evb.dts b/arch/arm/dts/rv1108-evb.dts index 2b221b6..8e857b2 100644 --- a/arch/arm/dts/rv1108-evb.dts +++ b/arch/arm/dts/rv1108-evb.dts @@ -39,6 +39,10 @@ snps,reset-gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; }; +&saradc { + status = "okay"; +}; + &sfc { status = "okay"; flash@0 { diff --git a/arch/arm/dts/rv1108.dtsi b/arch/arm/dts/rv1108.dtsi index 3153dfe..31b4d93 100644 --- a/arch/arm/dts/rv1108.dtsi +++ b/arch/arm/dts/rv1108.dtsi @@ -126,6 +126,17 @@ reg = <0x10300000 0x1000>; }; + saradc: saradc@1038c000 { + compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc"; + reg = <0x1038c000 0x100>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + clock-frequency = <1000000>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + status = "disabled"; + }; + pmugrf: syscon@20060000 { compatible = "rockchip,rv1108-pmugrf", "syscon"; reg = <0x20060000 0x1000>; diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index b02a602..7520446 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -69,6 +69,13 @@ #size-cells = <1>; u-boot,dm-pre-reloc; + hlcdc: hlcdc@f0000000 { + compatible = "atmel,at91sam9x5-hlcdc"; + reg = <0xf0000000 0x2000>; + clocks = <&lcdc_clk>; + status = "disabled"; + }; + pmc: pmc@f0014000 { compatible = "atmel,sama5d2-pmc", "syscon"; reg = <0xf0014000 0x160>; diff --git a/arch/arm/dts/sama5d36ek_cmp.dts b/arch/arm/dts/sama5d36ek_cmp.dts index be41490..c17bc9f 100644 --- a/arch/arm/dts/sama5d36ek_cmp.dts +++ b/arch/arm/dts/sama5d36ek_cmp.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "sama5d36.dtsi" #include "sama5d3xmb_cmp.dtsi" +#include "sama5d3xdm.dtsi" / { model = "Atmel SAMA5D36-EK"; diff --git a/arch/arm/dts/sama5d3_lcd.dtsi b/arch/arm/dts/sama5d3_lcd.dtsi index 14d7c2b..10fb3a9 100644 --- a/arch/arm/dts/sama5d3_lcd.dtsi +++ b/arch/arm/dts/sama5d3_lcd.dtsi @@ -14,31 +14,12 @@ ahb { apb { hlcdc: hlcdc@f0030000 { - compatible = "atmel,sama5d3-hlcdc"; + compatible = "atmel,at91sam9x5-hlcdc"; reg = <0xf0030000 0x2000>; interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; clock-names = "periph_clk","sys_clk", "slow_clk"; status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; }; pinctrl@fffff200 { diff --git a/arch/arm/dts/sama5d3xdm.dtsi b/arch/arm/dts/sama5d3xdm.dtsi index 035ab72..b3df9af 100644 --- a/arch/arm/dts/sama5d3xdm.dtsi +++ b/arch/arm/dts/sama5d3xdm.dtsi @@ -10,6 +10,32 @@ / { ahb { apb { + hlcdc: hlcdc@f0030000 { + atmel,vl-bpix = <4>; + atmel,output-mode = <24>; + atmel,guard-time = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb888_alt>; + status = "okay"; + u-boot,dm-pre-reloc; + + display-timings { + u-boot,dm-pre-reloc; + 800x480 { + clock-frequency = <24000000>; + hactive = <800>; + vactive = <480>; + hsync-len = <5>; + hfront-porch = <64>; + hback-porch = <64>; + vfront-porch = <22>; + vback-porch = <21>; + vsync-len = <5>; + u-boot,dm-pre-reloc; + }; + }; + }; + i2c1: i2c@f0018000 { qt1070: keyboard@1b { compatible = "qt1070"; diff --git a/arch/arm/dts/sama5d4.dtsi b/arch/arm/dts/sama5d4.dtsi index c6512ae..8072b8a 100644 --- a/arch/arm/dts/sama5d4.dtsi +++ b/arch/arm/dts/sama5d4.dtsi @@ -320,31 +320,12 @@ u-boot,dm-pre-reloc; hlcdc: hlcdc@f0000000 { - compatible = "atmel,sama5d4-hlcdc"; + compatible = "atmel,at91sam9x5-hlcdc"; reg = <0xf0000000 0x4000>; interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; clock-names = "periph_clk","sys_clk", "slow_clk"; status = "disabled"; - - hlcdc-display-controller { - compatible = "atmel,hlcdc-display-controller"; - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - }; - }; - - hlcdc_pwm: hlcdc-pwm { - compatible = "atmel,hlcdc-pwm"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd_pwm>; - #pwm-cells = <3>; - }; }; dma1: dma-controller@f0004000 { diff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi b/arch/arm/dts/stm32h743-pinctrl.dtsi index d3e11d5..e4f4aa5 100644 --- a/arch/arm/dts/stm32h743-pinctrl.dtsi +++ b/arch/arm/dts/stm32h743-pinctrl.dtsi @@ -244,6 +244,32 @@ slew-rate = <3>; }; }; + + sdmmc1_pins: sdmmc@0 { + pins { + pinmux = <STM32H7_PC8_FUNC_SDMMC1_D0>, + <STM32H7_PC9_FUNC_SDMMC1_D1>, + <STM32H7_PC10_FUNC_SDMMC1_D2>, + <STM32H7_PC11_FUNC_SDMMC1_D3>, + <STM32H7_PC12_FUNC_SDMMC1_CK>, + <STM32H7_PD2_FUNC_SDMMC1_CMD>; + + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + }; + + pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 { + pins { + pinmux = <STM32H7_PB8_FUNC_SDMMC1_CKIN>, + <STM32H7_PB9_FUNC_SDMMC1_CDIR>, + <STM32H7_PC6_FUNC_SDMMC1_D0DIR>, + <STM32H7_PC7_FUNC_SDMMC1_D123DIR>; + drive-push-pull; + slew-rate = <3>; + }; + }; }; }; }; diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi index 16e9308..d5b8d87 100644 --- a/arch/arm/dts/stm32h743.dtsi +++ b/arch/arm/dts/stm32h743.dtsi @@ -43,6 +43,7 @@ #include "skeleton.dtsi" #include "armv7-m.dtsi" #include <dt-bindings/clock/stm32h7-clks.h> +#include <dt-bindings/mfd/stm32h7-rcc.h> / { clocks { @@ -76,7 +77,7 @@ }; usart1: serial@40011000 { - compatible = "st,stm32h7-usart", "st,stm32h7-uart"; + compatible = "st,stm32h7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; status = "disabled"; @@ -84,7 +85,7 @@ }; usart2: serial@40004400 { - compatible = "st,stm32h7-usart", "st,stm32h7-uart"; + compatible = "st,stm32h7-uart"; reg = <0x40004400 0x400>; interrupts = <38>; status = "disabled"; @@ -120,6 +121,18 @@ compatible = "fixed-clock"; clock-frequency = <4000000>; }; + + sdmmc1: sdmmc@52007000 { + compatible = "st,stm32-sdmmc2"; + reg = <0x52007000 0x1000>; + interrupts = <49>; + clocks = <&rcc SDMMC1_CK>; + resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; + st,idma = <1>; + cap-sd-highspeed; + cap-mmc-highspeed; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts index bef7e90..917a859 100644 --- a/arch/arm/dts/stm32h743i-disco.dts +++ b/arch/arm/dts/stm32h743i-disco.dts @@ -60,6 +60,7 @@ aliases { serial0 = &usart2; + mmc0 = &sdmmc1; gpio0 = &gpioa; gpio1 = &gpiob; gpio2 = &gpioc; @@ -98,3 +99,11 @@ st,sdram-refcount = <1539>; }; }; + +&sdmmc1 { + status = "okay"; + pinctrl-0 = <&sdmmc1_pins>; + pinctrl-names = "default"; + bus-width = <4>; + cd-gpios = <&gpioi 8 1>; +}; diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts index 0e01ce5..28c876b 100644 --- a/arch/arm/dts/stm32h743i-eval.dts +++ b/arch/arm/dts/stm32h743i-eval.dts @@ -98,3 +98,12 @@ st,sdram-refcount = <1539>; }; }; + +&sdmmc1 { + status = "okay"; + pinctrl-0 = <&sdmmc1_pins>, + <&pinctrl_sdmmc1_level_shifter>; + pinctrl-names = "default"; + bus-width = <4>; + st,dirpol; +}; diff --git a/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts index ba5bca0..4c03cc3 100644 --- a/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts +++ b/arch/arm/dts/sun7i-a20-bananapi-m1-plus.dts @@ -105,6 +105,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &ehci0 { status = "okay"; }; @@ -132,16 +136,14 @@ status = "okay"; axp209: pmic@34 { - compatible = "x-powers,axp209"; reg = <0x34>; interrupt-parent = <&nmi_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - interrupt-controller; - #interrupt-cells = <1>; }; }; +#include "axp209.dtsi" + &ir0 { pinctrl-names = "default"; pinctrl-0 = <&ir0_rx_pins_a>; @@ -167,10 +169,10 @@ mmc-pwrseq = <&mmc3_pwrseq>; bus-width = <4>; non-removable; - enable-sdio-wakeup; + wakeup-source; status = "okay"; - brcmf: bcrmf@1 { + brcmf: wifi@1 { reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&pio>; @@ -181,7 +183,7 @@ &mmc3_pins_a { /* AP6210 requires pull-up */ - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + bias-pull-up; }; &ohci0 { @@ -192,38 +194,81 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { gmac_power_pin_bpi_m1p: gmac_power_pin@0 { - allwinner,pins = "PH23"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH23"; + function = "gpio_out"; }; led_pins_bpi_m1p: led_pins@0 { - allwinner,pins = "PH24", "PH25"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH24", "PH25"; + function = "gpio_out"; }; mmc0_cd_pin_bpi_m1p: mmc0_cd_pin@0 { - allwinner,pins = "PH10"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PH10"; + function = "gpio_in"; + bias-pull-up; }; mmc3_pwrseq_pin_bpi_m1p: mmc3_pwrseq_pin@0 { - allwinner,pins = "PH22"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH22"; + function = "gpio_out"; }; }; +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_usb0_vbus>; + /* VBUS on usb host ports are tied to DC5V and therefore always on */ + status = "okay"; +}; diff --git a/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts b/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts new file mode 100644 index 0000000..d99e7b1 --- /dev/null +++ b/arch/arm/dts/sun7i-a20-olinuxino-micro-emmc.dts @@ -0,0 +1,70 @@ + /* + * Copyright 2017 Olimex Ltd. + * Stefan Mavrodiev <stefan@olimex.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun7i-a20-olinuxino-micro.dts" + +/ { + model = "Olimex A20-OLinuXino-MICRO-eMMC"; + compatible = "olimex,a20-olinuxino-micro-emmc", "allwinner,sun7i-a20"; + + mmc2_pwrseq: pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&mmc2_pwrseq>; + status = "okay"; + + emmc: emmc@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi index f97c38f..ea50dda 100644 --- a/arch/arm/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/dts/sun8i-a23-a33.dtsi @@ -46,7 +46,8 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/clock/sun8i-a23-a33-ccu.h> +#include <dt-bindings/reset/sun8i-a23-a33-ccu.h> / { interrupt-parent = <&gic>; @@ -60,7 +61,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll6 0>; + clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>, + <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>; status = "disabled"; }; }; @@ -80,7 +83,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; @@ -102,151 +105,16 @@ #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; + clock-accuracy = <50000>; clock-output-names = "osc24M"; }; - osc32k: osc32k_clk { + ext_osc32k: ext_osc32k_clk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; - clock-output-names = "osc32k"; - }; - - pll1: clk@01c20000 { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-pll1-clk"; - reg = <0x01c20000 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll1"; - }; - - /* dummy clock until actually implemented */ - pll5: pll5_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "pll5"; - }; - - pll6: clk@01c20028 { - #clock-cells = <1>; - compatible = "allwinner,sun6i-a31-pll6-clk"; - reg = <0x01c20028 0x4>; - clocks = <&osc24M>; - clock-output-names = "pll6", "pll6x2"; - }; - - cpu: cpu_clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-cpu-clk"; - reg = <0x01c20050 0x4>; - - /* - * PLL1 is listed twice here. - * While it looks suspicious, it's actually documented - * that way both in the datasheet and in the code from - * Allwinner. - */ - clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>; - clock-output-names = "cpu"; - }; - - axi: axi_clk@01c20050 { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-axi-clk"; - reg = <0x01c20050 0x4>; - clocks = <&cpu>; - clock-output-names = "axi"; - }; - - ahb1: ahb1_clk@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun6i-a31-ahb1-clk"; - reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; - clock-output-names = "ahb1"; - }; - - apb1: apb1_clk@01c20054 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb0-clk"; - reg = <0x01c20054 0x4>; - clocks = <&ahb1>; - clock-output-names = "apb1"; - }; - - apb1_gates: clk@01c20068 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a23-apb1-gates-clk"; - reg = <0x01c20068 0x4>; - clocks = <&apb1>; - clock-indices = <0>, <5>, - <12>, <13>; - clock-output-names = "apb1_codec", "apb1_pio", - "apb1_daudio0", "apb1_daudio1"; - }; - - apb2: clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; - clock-output-names = "apb2"; - }; - - apb2_gates: clk@01c2006c { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a23-apb2-gates-clk"; - reg = <0x01c2006c 0x4>; - clocks = <&apb2>; - clock-indices = <0>, <1>, - <2>, <16>, - <17>, <18>, - <19>, <20>; - clock-output-names = "apb2_i2c0", "apb2_i2c1", - "apb2_i2c2", "apb2_uart0", - "apb2_uart1", "apb2_uart2", - "apb2_uart3", "apb2_uart4"; - }; - - mmc0_clk: clk@01c20088 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc0", - "mmc0_output", - "mmc0_sample"; - }; - - mmc1_clk: clk@01c2008c { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc1", - "mmc1_output", - "mmc1_sample"; - }; - - mmc2_clk: clk@01c20090 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-mmc-clk"; - reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "mmc2", - "mmc2_output", - "mmc2_sample"; - }; - - usb_clk: clk@01c200cc { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "allwinner,sun8i-a23-usb-clk"; - reg = <0x01c200cc 0x4>; - clocks = <&osc24M>; - clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic", - "usb_hsic_12M", "usb_ohci0"; + clock-accuracy = <50000>; + clock-output-names = "ext-osc32k"; }; }; @@ -260,24 +128,23 @@ compatible = "allwinner,sun8i-a23-dma"; reg = <0x01c02000 0x1000>; interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 6>; - resets = <&ahb1_rst 6>; + clocks = <&ccu CLK_BUS_DMA>; + resets = <&ccu RST_BUS_DMA>; #dma-cells = <1>; }; mmc0: mmc@01c0f000 { - compatible = "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c0f000 0x1000>; - clocks = <&ahb1_gates 8>, - <&mmc0_clk 0>, - <&mmc0_clk 1>, - <&mmc0_clk 2>; + clocks = <&ccu CLK_BUS_MMC0>, + <&ccu CLK_MMC0>, + <&ccu CLK_MMC0_OUTPUT>, + <&ccu CLK_MMC0_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 8>; + resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -286,18 +153,17 @@ }; mmc1: mmc@01c10000 { - compatible = "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c10000 0x1000>; - clocks = <&ahb1_gates 9>, - <&mmc1_clk 0>, - <&mmc1_clk 1>, - <&mmc1_clk 2>; + clocks = <&ccu CLK_BUS_MMC1>, + <&ccu CLK_MMC1>, + <&ccu CLK_MMC1_OUTPUT>, + <&ccu CLK_MMC1_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 9>; + resets = <&ccu RST_BUS_MMC1>; reset-names = "ahb"; interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -306,18 +172,17 @@ }; mmc2: mmc@01c11000 { - compatible = "allwinner,sun7i-a20-mmc", - "allwinner,sun5i-a13-mmc"; + compatible = "allwinner,sun7i-a20-mmc"; reg = <0x01c11000 0x1000>; - clocks = <&ahb1_gates 10>, - <&mmc2_clk 0>, - <&mmc2_clk 1>, - <&mmc2_clk 2>; + clocks = <&ccu CLK_BUS_MMC2>, + <&ccu CLK_MMC2>, + <&ccu CLK_MMC2_OUTPUT>, + <&ccu CLK_MMC2_SAMPLE>; clock-names = "ahb", "mmc", "output", "sample"; - resets = <&ahb1_rst 10>; + resets = <&ccu RST_BUS_MMC2>; reset-names = "ahb"; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -325,12 +190,55 @@ #size-cells = <0>; }; + nfc: nand@01c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_NAND>; + reset-names = "ahb"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@01c19000 { + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01c19000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + status = "disabled"; + }; + + usbphy: phy@01c19400 { + /* + * compatible and address regions get set in + * SoC specific dtsi file + */ + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names = "usb0_reset", + "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + ehci0: usb@01c1a000 { compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 26>; - resets = <&ahb1_rst 26>; + clocks = <&ccu CLK_BUS_EHCI>; + resets = <&ccu RST_BUS_EHCI>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; @@ -340,101 +248,100 @@ compatible = "allwinner,sun8i-a23-ohci", "generic-ohci"; reg = <0x01c1a400 0x100>; interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 29>, <&usb_clk 16>; - resets = <&ahb1_rst 29>; + clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>; + resets = <&ccu RST_BUS_OHCI>; phys = <&usbphy 1>; phy-names = "usb"; status = "disabled"; }; + ccu: clock@01c20000 { + reg = <0x01c20000 0x400>; + clocks = <&osc24M>, <&rtc 0>; + clock-names = "hosc", "losc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + pio: pinctrl@01c20800 { /* compatible gets set in SoC specific dtsi file */ reg = <0x01c20800 0x400>; /* interrupts get set in SoC specific dtsi file */ - clocks = <&apb1_gates 5>; + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; + clock-names = "apb", "hosc", "losc"; gpio-controller; interrupt-controller; #interrupt-cells = <3>; #gpio-cells = <3>; uart0_pins_a: uart0@0 { - allwinner,pins = "PF2", "PF4"; - allwinner,function = "uart0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PF2", "PF4"; + function = "uart0"; + }; + + uart1_pins_a: uart1@0 { + pins = "PG6", "PG7"; + function = "uart1"; + }; + + uart1_pins_cts_rts_a: uart1-cts-rts@0 { + pins = "PG8", "PG9"; + function = "uart1"; }; mmc0_pins_a: mmc0@0 { - allwinner,pins = "PF0", "PF1", "PF2", - "PF3", "PF4", "PF5"; - allwinner,function = "mmc0"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + function = "mmc0"; + drive-strength = <30>; + bias-pull-up; }; mmc1_pins_a: mmc1@0 { - allwinner,pins = "PG0", "PG1", "PG2", - "PG3", "PG4", "PG5"; - allwinner,function = "mmc1"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + function = "mmc1"; + drive-strength = <30>; + bias-pull-up; }; mmc2_8bit_pins: mmc2_8bit { - allwinner,pins = "PC5", "PC6", "PC8", - "PC9", "PC10", "PC11", - "PC12", "PC13", "PC14", - "PC15", "PC16"; - allwinner,function = "mmc2"; - allwinner,drive = <SUN4I_PINCTRL_30_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", + "PC15", "PC16"; + function = "mmc2"; + drive-strength = <30>; + bias-pull-up; }; pwm0_pins: pwm0 { - allwinner,pins = "PH0"; - allwinner,function = "pwm0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH0"; + function = "pwm0"; }; i2c0_pins_a: i2c0@0 { - allwinner,pins = "PH2", "PH3"; - allwinner,function = "i2c0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH2", "PH3"; + function = "i2c0"; }; i2c1_pins_a: i2c1@0 { - allwinner,pins = "PH4", "PH5"; - allwinner,function = "i2c1"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PH4", "PH5"; + function = "i2c1"; }; i2c2_pins_a: i2c2@0 { - allwinner,pins = "PE12", "PE13"; - allwinner,function = "i2c2"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PE12", "PE13"; + function = "i2c2"; }; - }; - - ahb1_rst: reset@01c202c0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202c0 0xc>; - }; - apb1_rst: reset@01c202d0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202d0 0x4>; - }; - - apb2_rst: reset@01c202d8 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-clock-reset"; - reg = <0x01c202d8 0x4>; + lcd_rgb666_pins: lcd-rgb666@0 { + pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", + "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", + "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", + "PD24", "PD25", "PD26", "PD27"; + function = "lcd0"; + }; }; timer@01c20c00 { @@ -472,8 +379,8 @@ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 16>; - resets = <&apb2_rst 16>; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; dmas = <&dma 6>, <&dma 6>; dma-names = "rx", "tx"; status = "disabled"; @@ -485,8 +392,8 @@ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 17>; - resets = <&apb2_rst 17>; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; dmas = <&dma 7>, <&dma 7>; dma-names = "rx", "tx"; status = "disabled"; @@ -498,8 +405,8 @@ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 18>; - resets = <&apb2_rst 18>; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; dmas = <&dma 8>, <&dma 8>; dma-names = "rx", "tx"; status = "disabled"; @@ -511,8 +418,8 @@ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 19>; - resets = <&apb2_rst 19>; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; dmas = <&dma 9>, <&dma 9>; dma-names = "rx", "tx"; status = "disabled"; @@ -524,8 +431,8 @@ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; reg-io-width = <4>; - clocks = <&apb2_gates 20>; - resets = <&apb2_rst 20>; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; dmas = <&dma 10>, <&dma 10>; dma-names = "rx", "tx"; status = "disabled"; @@ -535,8 +442,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2ac00 0x400>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 0>; - resets = <&apb2_rst 0>; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -546,8 +453,8 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b000 0x400>; interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 1>; - resets = <&apb2_rst 1>; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -557,17 +464,44 @@ compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2b400 0x400>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb2_gates 2>; - resets = <&apb2_rst 2>; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; + mali: gpu@1c40000 { + compatible = "allwinner,sun8i-a23-mali", + "allwinner,sun7i-a20-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_BUS_GPU>; + #cooling-cells = <2>; + + assigned-clocks = <&ccu CLK_GPU>; + assigned-clock-rates = <384000000>; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, + <0x01c82000 0x2000>, <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupt-controller; @@ -580,13 +514,16 @@ reg = <0x01f00000 0x54>; interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clock-output-names = "osc32k"; + clocks = <&ext_osc32k>; + #clock-cells = <1>; }; - nmi_intc: interrupt-controller@01f00c0c { - compatible = "allwinner,sun6i-a31-sc-nmi"; + nmi_intc: interrupt-controller@1f00c00 { + compatible = "allwinner,sun6i-a31-r-intc"; interrupt-controller; #interrupt-cells = <2>; - reg = <0x01f00c0c 0x38>; + reg = <0x01f00c00 0x400>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; }; @@ -632,6 +569,10 @@ compatible = "allwinner,sun6i-a31-clock-reset"; #reset-cells = <1>; }; + + codec_analog: codec-analog { + compatible = "allwinner,sun8i-a23-codec-analog"; + }; }; cpucfg@01f01c00 { @@ -654,7 +595,8 @@ compatible = "allwinner,sun8i-a23-r-pinctrl"; reg = <0x01f02c00 0x400>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&apb0_gates 0>; + clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>; + clock-names = "apb", "hosc", "losc"; resets = <&apb0_rst 0>; gpio-controller; interrupt-controller; @@ -664,17 +606,15 @@ #gpio-cells = <3>; r_rsb_pins: r_rsb { - allwinner,pins = "PL0", "PL1"; - allwinner,function = "s_rsb"; - allwinner,drive = <SUN4I_PINCTRL_20_MA>; - allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + pins = "PL0", "PL1"; + function = "s_rsb"; + drive-strength = <20>; + bias-pull-up; }; r_uart_pins_a: r_uart@0 { - allwinner,pins = "PL2", "PL3"; - allwinner,function = "s_uart"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PL2", "PL3"; + function = "s_uart"; }; }; diff --git a/arch/arm/dts/sun8i-a23.dtsi b/arch/arm/dts/sun8i-a23.dtsi index 92e6616..4d1f929 100644 --- a/arch/arm/dts/sun8i-a23.dtsi +++ b/arch/arm/dts/sun8i-a23.dtsi @@ -49,78 +49,40 @@ reg = <0x40000000 0x40000000>; }; - clocks { - ahb1_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a23-ahb1-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb1>; - clock-indices = <1>, <6>, - <8>, <9>, <10>, - <13>, <14>, - <19>, <20>, - <21>, <24>, <26>, - <29>, <32>, <36>, - <40>, <44>, <46>, - <52>, <53>, - <54>, <57>; - clock-output-names = "ahb1_mipidsi", "ahb1_dma", - "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2", - "ahb1_nand", "ahb1_sdram", - "ahb1_hstimer", "ahb1_spi0", - "ahb1_spi1", "ahb1_otg", "ahb1_ehci", - "ahb1_ohci", "ahb1_ve", "ahb1_lcd", - "ahb1_csi", "ahb1_be", "ahb1_fe", - "ahb1_gpu", "ahb1_msgbox", - "ahb1_spinlock", "ahb1_drc"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5>; - clock-output-names = "mbus"; - }; - }; - soc@01c00000 { - usb_otg: usb@01c19000 { - compatible = "allwinner,sun6i-a31-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ahb1_gates 24>; - resets = <&ahb1_rst 24>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; - status = "disabled"; - }; - - usbphy: phy@01c19400 { - compatible = "allwinner,sun8i-a23-usb-phy"; - reg = <0x01c19400 0x10>, - <0x01c1a800 0x4>; - reg-names = "phy_ctrl", - "pmu1"; - clocks = <&usb_clk 8>, - <&usb_clk 9>; - clock-names = "usb0_phy", - "usb1_phy"; - resets = <&usb_clk 0>, - <&usb_clk 1>; - reset-names = "usb0_reset", - "usb1_reset"; + codec: codec@01c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a23-codec"; + reg = <0x01c22c00 0x400>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "apb", "codec"; + resets = <&ccu RST_BUS_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + allwinner,codec-analog-controls = <&codec_analog>; status = "disabled"; - #phy-cells = <1>; }; }; }; +&ccu { + compatible = "allwinner,sun8i-a23-ccu"; +}; + &pio { compatible = "allwinner,sun8i-a23-pinctrl"; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; }; + +&usb_otg { + compatible = "allwinner,sun6i-a31-musb"; +}; + +&usbphy { + compatible = "allwinner,sun8i-a23-usb-phy"; + reg = <0x01c19400 0x10>, <0x01c1a800 0x4>; + reg-names = "phy_ctrl", "pmu1"; +}; diff --git a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts index fef6abc..b1bc88c 100644 --- a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts +++ b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts @@ -61,6 +61,31 @@ chosen { stdout-path = "serial0:115200n8"; }; + + panel { + compatible = "netron-dy,e231732"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + panel_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_panel>; + }; + }; + }; +}; + +&de { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; }; &ehci0 { @@ -207,12 +232,30 @@ regulator-name = "vcc-rtc"; }; +&tcon0 { + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rgb666_pins>; + status = "okay"; +}; + +&tcon0_out { + tcon0_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_input>; + }; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_b>; status = "okay"; }; +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + &usbphy { status = "okay"; usb1_vbus-supply = <®_vcc5v0>; /* USB1 VBUS is always on */ diff --git a/arch/arm/dts/sun8i-a33.dtsi b/arch/arm/dts/sun8i-a33.dtsi index 001d840..2266091 100644 --- a/arch/arm/dts/sun8i-a33.dtsi +++ b/arch/arm/dts/sun8i-a33.dtsi @@ -43,19 +43,137 @@ */ #include "sun8i-a23-a33.dtsi" +#include <dt-bindings/thermal/thermal.h> / { + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-120000000 { + opp-hz = /bits/ 64 <120000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-504000000 { + opp-hz = /bits/ 64 <504000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-648000000 { + opp-hz = /bits/ 64 <648000000>; + opp-microvolt = <1040000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-720000000 { + opp-hz = /bits/ 64 <720000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-912000000 { + opp-hz = /bits/ 64 <912000000>; + opp-microvolt = <1200000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1200000>; + clock-latency-ns = <244144>; /* 8 32k periods */ + }; + }; + cpus { + cpu@0 { + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + }; + cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; + operating-points-v2 = <&cpu0_opp_table>; }; cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + de: display-engine { + compatible = "allwinner,sun8i-a33-display-engine"; + allwinner,pipelines = <&fe0>; + status = "disabled"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&ths>; + }; + + mali_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + opp-144000000 { + opp-hz = /bits/ 64 <144000000>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; }; }; @@ -63,113 +181,310 @@ reg = <0x40000000 0x80000000>; }; - clocks { - /* Dummy clock for pll11 (DDR1) until actually implemented */ - pll11: pll11_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <0>; - clock-output-names = "pll11"; - }; - - ahb1_gates: clk@01c20060 { - #clock-cells = <1>; - compatible = "allwinner,sun8i-a33-ahb1-gates-clk"; - reg = <0x01c20060 0x8>; - clocks = <&ahb1>; - clock-indices = <1>, <5>, - <6>, <8>, <9>, - <10>, <13>, <14>, - <19>, <20>, - <21>, <24>, <26>, - <29>, <32>, <36>, - <40>, <44>, <46>, - <52>, <53>, - <54>, <57>, - <58>; - clock-output-names = "ahb1_mipidsi", "ahb1_ss", - "ahb1_dma","ahb1_mmc0", "ahb1_mmc1", - "ahb1_mmc2", "ahb1_nand", "ahb1_sdram", - "ahb1_hstimer", "ahb1_spi0", - "ahb1_spi1", "ahb1_otg", "ahb1_ehci", - "ahb1_ohci", "ahb1_ve", "ahb1_lcd", - "ahb1_csi", "ahb1_be", "ahb1_fe", - "ahb1_gpu", "ahb1_msgbox", - "ahb1_spinlock", "ahb1_drc", - "ahb1_sat"; - }; - - ss_clk: clk@01c2009c { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; - reg = <0x01c2009c 0x4>; - clocks = <&osc24M>, <&pll6 0>; - clock-output-names = "ss"; - }; - - mbus_clk: clk@01c2015c { - #clock-cells = <0>; - compatible = "allwinner,sun8i-a23-mbus-clk"; - reg = <0x01c2015c 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&pll5>, <&pll11>; - clock-output-names = "mbus"; + sound: sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "sun8i-a33-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&link_codec>; + simple-audio-card,bitclock-master = <&link_codec>; + simple-audio-card,mclk-fs = <512>; + simple-audio-card,aux-devs = <&codec_analog>; + simple-audio-card,routing = + "Left DAC", "AIF1 Slot 0 Left", + "Right DAC", "AIF1 Slot 0 Right"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&dai>; + }; + + link_codec: simple-audio-card,codec { + sound-dai = <&codec>; }; }; soc@01c00000 { + tcon0: lcd-controller@01c0c000 { + compatible = "allwinner,sun8i-a33-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_LCD>, + <&ccu CLK_LCD_CH0>; + clock-names = "ahb", + "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_LCD>; + reset-names = "lcd"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + }; + }; + crypto: crypto-engine@01c15000 { compatible = "allwinner,sun4i-a10-crypto"; reg = <0x01c15000 0x1000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ahb1_gates 5>, <&ss_clk>; + clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>; clock-names = "ahb", "mod"; - resets = <&ahb1_rst 5>; + resets = <&ccu RST_BUS_SS>; reset-names = "ahb"; }; - usb_otg: usb@01c19000 { - compatible = "allwinner,sun8i-a33-musb"; - reg = <0x01c19000 0x0400>; - clocks = <&ahb1_gates 24>; - resets = <&ahb1_rst 24>; - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "mc"; - phys = <&usbphy 0>; - phy-names = "usb"; - extcon = <&usbphy 0>; + dai: dai@01c22c00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun6i-a31-i2s"; + reg = <0x01c22c00 0x200>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_CODEC>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + codec: codec@01c22e00 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun8i-a33-codec"; + reg = <0x01c22e00 0x400>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; + clock-names = "bus", "mod"; status = "disabled"; }; - usbphy: phy@01c19400 { - compatible = "allwinner,sun8i-a33-usb-phy"; - reg = <0x01c19400 0x14>, - <0x01c1a800 0x4>; - reg-names = "phy_ctrl", - "pmu1"; - clocks = <&usb_clk 8>, - <&usb_clk 9>; - clock-names = "usb0_phy", - "usb1_phy"; - resets = <&usb_clk 0>, - <&usb_clk 1>; - reset-names = "usb0_reset", - "usb1_reset"; + ths: ths@01c25000 { + compatible = "allwinner,sun8i-a33-ths"; + reg = <0x01c25000 0x100>; + #thermal-sensor-cells = <0>; + #io-channel-cells = <0>; + }; + + fe0: display-frontend@01e00000 { + compatible = "allwinner,sun8i-a33-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DE_FE>, <&ccu CLK_DE_FE>, + <&ccu CLK_DRAM_DE_FE>; + clock-names = "ahb", "mod", + "ram"; + resets = <&ccu RST_BUS_DE_FE>; status = "disabled"; - #phy-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; + }; + + be0: display-backend@01e60000 { + compatible = "allwinner,sun8i-a33-display-backend"; + reg = <0x01e60000 0x10000>, <0x01e80000 0x1000>; + reg-names = "be", "sat"; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DE_BE>, <&ccu CLK_DE_BE>, + <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_BUS_SAT>; + clock-names = "ahb", "mod", + "ram", "sat"; + resets = <&ccu RST_BUS_DE_BE>, <&ccu RST_BUS_SAT>; + reset-names = "be", "sat"; + assigned-clocks = <&ccu CLK_DE_BE>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_drc0: endpoint@0 { + reg = <0>; + remote-endpoint = <&drc0_in_be0>; + }; + }; + }; + }; + + drc0: drc@01e70000 { + compatible = "allwinner,sun8i-a33-drc"; + reg = <0x01e70000 0x10000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_DRC>, <&ccu CLK_DRC>, + <&ccu CLK_DRAM_DRC>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_DRC>; + + assigned-clocks = <&ccu CLK_DRC>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + drc0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + drc0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_drc0>; + }; + }; + + drc0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + drc0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_drc0>; + }; + }; + }; + }; + }; + + thermal-zones { + cpu_thermal { + /* milliseconds */ + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&ths>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map2 { + trip = <&gpu_alert0>; + cooling-device = <&mali 1 THERMAL_NO_LIMIT>; + }; + + map3 { + trip = <&gpu_alert1>; + cooling-device = <&mali 2 THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_alert0: gpu_alert0 { + /* milliCelsius */ + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_alert1: cpu_alert1 { + /* milliCelsius */ + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpu_alert1: gpu_alert1 { + /* milliCelsius */ + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_crit: cpu_crit { + /* milliCelsius */ + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; }; }; +&ccu { + compatible = "allwinner,sun8i-a33-ccu"; +}; + +&mali { + operating-points-v2 = <&mali_opp_table>; +}; + &pio { compatible = "allwinner,sun8i-a33-pinctrl"; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; uart0_pins_b: uart0@1 { - allwinner,pins = "PB0", "PB1"; - allwinner,function = "uart0"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + pins = "PB0", "PB1"; + function = "uart0"; }; }; + +&usb_otg { + compatible = "allwinner,sun8i-a33-musb"; +}; + +&usbphy { + compatible = "allwinner,sun8i-a33-usb-phy"; + reg = <0x01c19400 0x14>, <0x01c1a800 0x4>; + reg-names = "phy_ctrl", "pmu1"; +}; diff --git a/arch/arm/dts/sun8i-a83t-sinovoip-bpi-m3.dts b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts index dfc16a0..dfc16a0 100644 --- a/arch/arm/dts/sun8i-a83t-sinovoip-bpi-m3.dts +++ b/arch/arm/dts/sun8i-a83t-bananapi-m3.dts diff --git a/arch/arm/dts/tps6507x.dtsi b/arch/arm/dts/tps6507x.dtsi new file mode 100644 index 0000000..4c326e5 --- /dev/null +++ b/arch/arm/dts/tps6507x.dtsi @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * Integrated Power Management Chip + * http://www.ti.com/lit/ds/symlink/tps65070.pdf + */ + +&tps { + compatible = "ti,tps6507x"; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + vdcdc1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "VDCDC1"; + }; + + vdcdc2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "VDCDC2"; + }; + + vdcdc3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "VDCDC3"; + }; + + ldo1_reg: regulator@3 { + reg = <3>; + regulator-compatible = "LDO1"; + }; + + ldo2_reg: regulator@4 { + reg = <4>; + regulator-compatible = "LDO2"; + }; + + }; +}; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index a0dac86..4d79924 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -106,6 +106,7 @@ static struct mm_region early_map[] = { { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_SIZE1, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, +#ifdef CONFIG_FSL_IFC /* For IFC Region #1, only the first 4MB is cache-enabled */ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_SIZE1_1, @@ -120,6 +121,7 @@ static struct mm_region early_map[] = { CONFIG_SYS_FSL_IFC_SIZE1, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, +#endif { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) @@ -129,11 +131,13 @@ static struct mm_region early_map[] = { #endif PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, +#ifdef CONFIG_FSL_IFC /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, +#endif { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | @@ -163,10 +167,12 @@ static struct mm_region early_map[] = { CONFIG_SYS_FSL_QSPI_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, +#ifdef CONFIG_FSL_IFC { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, +#endif { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) @@ -211,11 +217,13 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, +#ifdef CONFIG_FSL_IFC { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_SIZE2, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, +#endif { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | @@ -310,10 +318,12 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, +#ifdef CONFIG_FSL_IFC { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, +#endif { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_SIZE1, PTE_BLOCK_MEMTYPE(MT_NORMAL) | diff --git a/arch/arm/include/asm/arch-rockchip/bootrom.h b/arch/arm/include/asm/arch-rockchip/bootrom.h index 92eb878..169cc5e 100644 --- a/arch/arm/include/asm/arch-rockchip/bootrom.h +++ b/arch/arm/include/asm/arch-rockchip/bootrom.h @@ -24,4 +24,22 @@ void back_to_bootrom(void); */ void _back_to_bootrom_s(void); +/** + * Boot-device identifiers as used by the BROM + */ +enum { + BROM_BOOTSOURCE_NAND = 1, + BROM_BOOTSOURCE_EMMC = 2, + BROM_BOOTSOURCE_SPINOR = 3, + BROM_BOOTSOURCE_SPINAND = 4, + BROM_BOOTSOURCE_SD = 5, + BROM_BOOTSOURCE_USB = 10, + BROM_LAST_BOOTSOURCE = BROM_BOOTSOURCE_USB +}; + +/** + * Locations of the boot-device identifier in SRAM + */ +#define RK3399_BROM_BOOTSOURCE_ID_ADDR 0xff8c0010 + #endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h index 2b1197f..5f6a5fb 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h @@ -89,6 +89,11 @@ enum { MCU_CLK_DIV_SHIFT = 0, MCU_CLK_DIV_MASK = GENMASK(4, 0), + /* CLKSEL_CON25 */ + CLK_SARADC_DIV_CON_SHIFT = 8, + CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8), + CLK_SARADC_DIV_CON_WIDTH = 8, + /* CLKSEL43_CON */ GMAC_MUX_SEL_EXTCLK = BIT(8), diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h index 2a1ae69..ad2dc96 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rv1108.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1108.h @@ -90,6 +90,11 @@ enum { CORE_CLK_DIV_SHIFT = 0, CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT, + /* CLKSEL_CON22 */ + CLK_SARADC_DIV_CON_SHIFT= 0, + CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0), + CLK_SARADC_DIV_CON_WIDTH= 10, + /* CLKSEL24_CON */ MAC_PLL_SEL_SHIFT = 12, MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT, diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h index 7625f24..d995b7d 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3036.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3036.h @@ -209,10 +209,10 @@ enum { GPIO1A3_I2S_LRCKTX, GPIO1A2_SHIFT = 4, - GPIO1A2_MASK = 6 << GPIO1A2_SHIFT, + GPIO1A2_MASK = 3 << GPIO1A2_SHIFT, GPIO1A2_GPIO = 0, GPIO1A2_I2S_LRCKRX, - GPIO1A2_I2S_PWM1_0, + GPIO1A2_PWM1_0, GPIO1A1_SHIFT = 2, GPIO1A1_MASK = 1 << GPIO1A1_SHIFT, diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h new file mode 100644 index 0000000..b40da40 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_rk322x.h @@ -0,0 +1,581 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_SDRAM_RK322X_H +#define _ASM_ARCH_SDRAM_RK322X_H + +#include <common.h> + +enum { + DDR3 = 3, + LPDDR2 = 5, + LPDDR3 = 6, + UNUSED = 0xFF, +}; + +struct rk322x_sdram_channel { + /* + * bit width in address, eg: + * 8 banks using 3 bit to address, + * 2 cs using 1 bit to address. + */ + u8 rank; + u8 col; + u8 bk; + u8 bw; + u8 dbw; + u8 row_3_4; + u8 cs0_row; + u8 cs1_row; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + /* + * For of-platdata, which would otherwise convert this into two + * byte-swapped integers. With a size of 9 bytes, this struct will + * appear in of-platdata as a byte array. + * + * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff) + */ + u8 dummy; +#endif +}; + +struct rk322x_ddr_pctl { + u32 scfg; + u32 sctl; + u32 stat; + u32 intrstat; + u32 reserved0[(0x40 - 0x10) / 4]; + u32 mcmd; + u32 powctl; + u32 powstat; + u32 cmdtstat; + u32 cmdtstaten; + u32 reserved1[(0x60 - 0x54) / 4]; + u32 mrrcfg0; + u32 mrrstat0; + u32 mrrstat1; + u32 reserved2[(0x7c - 0x6c) / 4]; + + u32 mcfg1; + u32 mcfg; + u32 ppcfg; + u32 mstat; + u32 lpddr2zqcfg; + u32 reserved3; + + u32 dtupdes; + u32 dtuna; + u32 dtune; + u32 dtuprd0; + u32 dtuprd1; + u32 dtuprd2; + u32 dtuprd3; + u32 dtuawdt; + u32 reserved4[(0xc0 - 0xb4) / 4]; + + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; + u32 tref_mem_ddr3; + u32 reserved5[(0x180 - 0x14c) / 4]; + u32 ecccfg; + u32 ecctst; + u32 eccclr; + u32 ecclog; + u32 reserved6[(0x200 - 0x190) / 4]; + u32 dtuwactl; + u32 dturactl; + u32 dtucfg; + u32 dtuectl; + u32 dtuwd0; + u32 dtuwd1; + u32 dtuwd2; + u32 dtuwd3; + u32 dtuwdm; + u32 dturd0; + u32 dturd1; + u32 dturd2; + u32 dturd3; + u32 dtulfsrwd; + u32 dtulfsrrd; + u32 dtueaf; + /* dfi control registers */ + u32 dfitctrldelay; + u32 dfiodtcfg; + u32 dfiodtcfg1; + u32 dfiodtrankmap; + /* dfi write data registers */ + u32 dfitphywrdata; + u32 dfitphywrlat; + u32 reserved7[(0x260 - 0x258) / 4]; + u32 dfitrddataen; + u32 dfitphyrdlat; + u32 reserved8[(0x270 - 0x268) / 4]; + u32 dfitphyupdtype0; + u32 dfitphyupdtype1; + u32 dfitphyupdtype2; + u32 dfitphyupdtype3; + u32 dfitctrlupdmin; + u32 dfitctrlupdmax; + u32 dfitctrlupddly; + u32 reserved9; + u32 dfiupdcfg; + u32 dfitrefmski; + u32 dfitctrlupdi; + u32 reserved10[(0x2ac - 0x29c) / 4]; + u32 dfitrcfg0; + u32 dfitrstat0; + u32 dfitrwrlvlen; + u32 dfitrrdlvlen; + u32 dfitrrdlvlgateen; + u32 dfiststat0; + u32 dfistcfg0; + u32 dfistcfg1; + u32 reserved11; + u32 dfitdramclken; + u32 dfitdramclkdis; + u32 dfistcfg2; + u32 dfistparclr; + u32 dfistparlog; + u32 reserved12[(0x2f0 - 0x2e4) / 4]; + + u32 dfilpcfg0; + u32 reserved13[(0x300 - 0x2f4) / 4]; + u32 dfitrwrlvlresp0; + u32 dfitrwrlvlresp1; + u32 dfitrwrlvlresp2; + u32 dfitrrdlvlresp0; + u32 dfitrrdlvlresp1; + u32 dfitrrdlvlresp2; + u32 dfitrwrlvldelay0; + u32 dfitrwrlvldelay1; + u32 dfitrwrlvldelay2; + u32 dfitrrdlvldelay0; + u32 dfitrrdlvldelay1; + u32 dfitrrdlvldelay2; + u32 dfitrrdlvlgatedelay0; + u32 dfitrrdlvlgatedelay1; + u32 dfitrrdlvlgatedelay2; + u32 dfitrcmd; + u32 reserved14[(0x3f8 - 0x340) / 4]; + u32 ipvr; + u32 iptr; +}; +check_member(rk322x_ddr_pctl, iptr, 0x03fc); + +struct rk322x_ddr_phy { + u32 ddrphy_reg[0x100]; +}; + +struct rk322x_pctl_timing { + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; + u32 trefi_mem_ddr3; +}; + +struct rk322x_phy_timing { + u32 mr[4]; + u32 mr11; + u32 bl; + u32 cl_al; +}; + +struct rk322x_msch_timings { + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; + u32 activate; + u32 devtodev; +}; + +struct rk322x_service_sys { + u32 id_coreid; + u32 id_revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; + u32 activate; + u32 devtodev; +}; + +struct rk322x_base_params { + struct rk322x_msch_timings noc_timing; + u32 ddrconfig; + u32 ddr_freq; + u32 dramtype; + /* + * unused for rk322x + */ + u32 stride; + u32 odt; +}; + +/* PCT_DFISTCFG0 */ +#define DFI_INIT_START BIT(0) +#define DFI_DATA_BYTE_DISABLE_EN BIT(2) + +/* PCT_DFISTCFG1 */ +#define DFI_DRAM_CLK_SR_EN BIT(0) +#define DFI_DRAM_CLK_DPD_EN BIT(1) + +/* PCT_DFISTCFG2 */ +#define DFI_PARITY_INTR_EN BIT(0) +#define DFI_PARITY_EN BIT(1) + +/* PCT_DFILPCFG0 */ +#define TLP_RESP_TIME_SHIFT 16 +#define LP_SR_EN BIT(8) +#define LP_PD_EN BIT(0) + +/* PCT_DFITCTRLDELAY */ +#define TCTRL_DELAY_TIME_SHIFT 0 + +/* PCT_DFITPHYWRDATA */ +#define TPHY_WRDATA_TIME_SHIFT 0 + +/* PCT_DFITPHYRDLAT */ +#define TPHY_RDLAT_TIME_SHIFT 0 + +/* PCT_DFITDRAMCLKDIS */ +#define TDRAM_CLK_DIS_TIME_SHIFT 0 + +/* PCT_DFITDRAMCLKEN */ +#define TDRAM_CLK_EN_TIME_SHIFT 0 + +/* PCTL_DFIODTCFG */ +#define RANK0_ODT_WRITE_SEL BIT(3) +#define RANK1_ODT_WRITE_SEL BIT(11) + +/* PCTL_DFIODTCFG1 */ +#define ODT_LEN_BL8_W_SHIFT 16 + +/* PUBL_ACDLLCR */ +#define ACDLLCR_DLLDIS BIT(31) +#define ACDLLCR_DLLSRST BIT(30) + +/* PUBL_DXDLLCR */ +#define DXDLLCR_DLLDIS BIT(31) +#define DXDLLCR_DLLSRST BIT(30) + +/* PUBL_DLLGCR */ +#define DLLGCR_SBIAS BIT(30) + +/* PUBL_DXGCR */ +#define DQSRTT BIT(9) +#define DQRTT BIT(10) + +/* PIR */ +#define PIR_INIT BIT(0) +#define PIR_DLLSRST BIT(1) +#define PIR_DLLLOCK BIT(2) +#define PIR_ZCAL BIT(3) +#define PIR_ITMSRST BIT(4) +#define PIR_DRAMRST BIT(5) +#define PIR_DRAMINIT BIT(6) +#define PIR_QSTRN BIT(7) +#define PIR_RVTRN BIT(8) +#define PIR_ICPC BIT(16) +#define PIR_DLLBYP BIT(17) +#define PIR_CTLDINIT BIT(18) +#define PIR_CLRSR BIT(28) +#define PIR_LOCKBYP BIT(29) +#define PIR_ZCALBYP BIT(30) +#define PIR_INITBYP BIT(31) + +/* PGCR */ +#define PGCR_DFTLMT_SHIFT 3 +#define PGCR_DFTCMP_SHIFT 2 +#define PGCR_DQSCFG_SHIFT 1 +#define PGCR_ITMDMD_SHIFT 0 + +/* PGSR */ +#define PGSR_IDONE BIT(0) +#define PGSR_DLDONE BIT(1) +#define PGSR_ZCDONE BIT(2) +#define PGSR_DIDONE BIT(3) +#define PGSR_DTDONE BIT(4) +#define PGSR_DTERR BIT(5) +#define PGSR_DTIERR BIT(6) +#define PGSR_DFTERR BIT(7) +#define PGSR_RVERR BIT(8) +#define PGSR_RVEIRR BIT(9) + +/* PTR0 */ +#define PRT_ITMSRST_SHIFT 18 +#define PRT_DLLLOCK_SHIFT 6 +#define PRT_DLLSRST_SHIFT 0 + +/* PTR1 */ +#define PRT_DINIT0_SHIFT 0 +#define PRT_DINIT1_SHIFT 19 + +/* PTR2 */ +#define PRT_DINIT2_SHIFT 0 +#define PRT_DINIT3_SHIFT 17 + +/* DCR */ +#define DDRMD_LPDDR 0 +#define DDRMD_DDR 1 +#define DDRMD_DDR2 2 +#define DDRMD_DDR3 3 +#define DDRMD_LPDDR2_LPDDR3 4 +#define DDRMD_MASK 7 +#define DDRMD_SHIFT 0 +#define PDQ_MASK 7 +#define PDQ_SHIFT 4 + +/* DXCCR */ +#define DQSNRES_MASK 0xf +#define DQSNRES_SHIFT 8 +#define DQSRES_MASK 0xf +#define DQSRES_SHIFT 4 + +/* DTPR */ +#define TDQSCKMAX_SHIFT 27 +#define TDQSCKMAX_MASK 7 +#define TDQSCK_SHIFT 24 +#define TDQSCK_MASK 7 + +/* DSGCR */ +#define DQSGX_SHIFT 5 +#define DQSGX_MASK 7 +#define DQSGE_SHIFT 8 +#define DQSGE_MASK 7 + +/* SCTL */ +#define INIT_STATE 0 +#define CFG_STATE 1 +#define GO_STATE 2 +#define SLEEP_STATE 3 +#define WAKEUP_STATE 4 + +/* STAT */ +#define LP_TRIG_SHIFT 4 +#define LP_TRIG_MASK 7 +#define PCTL_STAT_MASK 7 +#define INIT_MEM 0 +#define CONFIG 1 +#define CONFIG_REQ 2 +#define ACCESS 3 +#define ACCESS_REQ 4 +#define LOW_POWER 5 +#define LOW_POWER_ENTRY_REQ 6 +#define LOW_POWER_EXIT_REQ 7 + +/* ZQCR*/ +#define PD_OUTPUT_SHIFT 0 +#define PU_OUTPUT_SHIFT 5 +#define PD_ONDIE_SHIFT 10 +#define PU_ONDIE_SHIFT 15 +#define ZDEN_SHIFT 28 + +/* DDLGCR */ +#define SBIAS_BYPASS BIT(23) + +/* MCFG */ +#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24 +#define PD_IDLE_SHIFT 8 +#define MDDR_EN (2 << 22) +#define LPDDR2_EN (3 << 22) +#define LPDDR3_EN (1 << 22) +#define DDR2_EN (0 << 5) +#define DDR3_EN (1 << 5) +#define LPDDR2_S2 (0 << 6) +#define LPDDR2_S4 (1 << 6) +#define MDDR_LPDDR2_BL_2 (0 << 20) +#define MDDR_LPDDR2_BL_4 (1 << 20) +#define MDDR_LPDDR2_BL_8 (2 << 20) +#define MDDR_LPDDR2_BL_16 (3 << 20) +#define DDR2_DDR3_BL_4 0 +#define DDR2_DDR3_BL_8 1 +#define TFAW_SHIFT 18 +#define PD_EXIT_SLOW (0 << 17) +#define PD_EXIT_FAST (1 << 17) +#define PD_TYPE_SHIFT 16 +#define BURSTLENGTH_SHIFT 20 + +/* POWCTL */ +#define POWER_UP_START BIT(0) + +/* POWSTAT */ +#define POWER_UP_DONE BIT(0) + +/* MCMD */ +enum { + DESELECT_CMD = 0, + PREA_CMD, + REF_CMD, + MRS_CMD, + ZQCS_CMD, + ZQCL_CMD, + RSTL_CMD, + MRR_CMD = 8, + DPDE_CMD, +}; + +#define BANK_ADDR_MASK 7 +#define BANK_ADDR_SHIFT 17 +#define CMD_ADDR_MASK 0x1fff +#define CMD_ADDR_SHIFT 4 + +#define LPDDR23_MA_SHIFT 4 +#define LPDDR23_MA_MASK 0xff +#define LPDDR23_OP_SHIFT 12 +#define LPDDR23_OP_MASK 0xff + +#define START_CMD (1u << 31) + +/* DDRPHY REG */ +enum { + /* DDRPHY_REG0 */ + SOFT_RESET_MASK = 3, + SOFT_DERESET_ANALOG = 1 << 2, + SOFT_DERESET_DIGITAL = 1 << 3, + SOFT_RESET_SHIFT = 2, + + /* DDRPHY REG1 */ + PHY_DDR3 = 0, + PHY_DDR2 = 1, + PHY_LPDDR3 = 2, + PHY_LPDDR2 = 3, + + PHT_BL_8 = 1 << 2, + PHY_BL_4 = 0 << 2, + + /* DDRPHY_REG2 */ + MEMORY_SELECT_DDR3 = 0 << 0, + MEMORY_SELECT_LPDDR3 = 2 << 0, + MEMORY_SELECT_LPDDR2 = 3 << 0, + DQS_SQU_CAL_SEL_CS0_CS1 = 0 << 4, + DQS_SQU_CAL_SEL_CS1 = 1 << 4, + DQS_SQU_CAL_SEL_CS0 = 2 << 4, + DQS_SQU_CAL_NORMAL_MODE = 0 << 1, + DQS_SQU_CAL_BYPASS_MODE = 1 << 1, + DQS_SQU_CAL_START = 1 << 0, + DQS_SQU_NO_CAL = 0 << 0, +}; + +/* CK pull up/down driver strength control */ +enum { + PHY_RON_RTT_DISABLE = 0, + PHY_RON_RTT_451OHM = 1, + PHY_RON_RTT_225OHM, + PHY_RON_RTT_150OHM, + PHY_RON_RTT_112OHM, + PHY_RON_RTT_90OHM, + PHY_RON_RTT_75OHM, + PHY_RON_RTT_64OHM = 7, + + PHY_RON_RTT_56OHM = 16, + PHY_RON_RTT_50OHM, + PHY_RON_RTT_45OHM, + PHY_RON_RTT_41OHM, + PHY_RON_RTT_37OHM, + PHY_RON_RTT_34OHM, + PHY_RON_RTT_33OHM, + PHY_RON_RTT_30OHM = 23, + + PHY_RON_RTT_28OHM = 24, + PHY_RON_RTT_26OHM, + PHY_RON_RTT_25OHM, + PHY_RON_RTT_23OHM, + PHY_RON_RTT_22OHM, + PHY_RON_RTT_21OHM, + PHY_RON_RTT_20OHM, + PHY_RON_RTT_19OHM = 31, +}; + +/* DQS squelch DLL delay */ +enum { + DQS_DLL_NO_DELAY = 0, + DQS_DLL_22P5_DELAY, + DQS_DLL_45_DELAY, + DQS_DLL_67P5_DELAY, + DQS_DLL_90_DELAY, + DQS_DLL_112P5_DELAY, + DQS_DLL_135_DELAY, + DQS_DLL_157P5_DELAY, +}; + +/* GRF_SOC_CON0 */ +#define GRF_DDR_16BIT_EN (((0x1 << 0) << 16) | (0x1 << 0)) +#define GRF_DDR_32BIT_EN (((0x1 << 0) << 16) | (0x0 << 0)) +#define GRF_MSCH_NOC_16BIT_EN (((0x1 << 7) << 16) | (0x1 << 7)) +#define GRF_MSCH_NOC_32BIT_EN (((0x1 << 7) << 16) | (0x0 << 7)) + +#define GRF_DDRPHY_BUFFEREN_CORE_EN (((0x1 << 8) << 16) | (0x0 << 8)) +#define GRF_DDRPHY_BUFFEREN_CORE_DIS (((0x1 << 8) << 16) | (0x1 << 8)) + +#define GRF_DDR3_EN (((0x1 << 6) << 16) | (0x1 << 6)) +#define GRF_LPDDR2_3_EN (((0x1 << 6) << 16) | (0x0 << 6)) + +#define PHY_DRV_ODT_SET(n) (((n) << 4) | (n)) +#define DDR3_DLL_RESET (1 << 8) + +#endif /* _ASM_ARCH_SDRAM_RK322X_H */ diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h index 35423e1..e428d59 100644 --- a/arch/arm/include/asm/arch-rockchip/sys_proto.h +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h @@ -7,4 +7,27 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H +#ifdef CONFIG_ROCKCHIP_RK3288 +#include <asm/armv7.h> + +static void configure_l2ctlr(void) +{ + uint32_t l2ctlr; + + l2ctlr = read_l2ctlr(); + l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ + + /* + * Data RAM write latency: 2 cycles + * Data RAM read latency: 2 cycles + * Data RAM setup latency: 1 cycle + * Tag RAM write latency: 1 cycle + * Tag RAM read latency: 1 cycle + * Tag RAM setup latency: 1 cycle + */ + l2ctlr |= (1 << 3 | 1 << 0); + write_l2ctlr(l2ctlr); +} +#endif /* CONFIG_ROCKCHIP_RK3288 */ + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h index 9358397..a70b179 100644 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -78,4 +78,6 @@ typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct boot_file_he #define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0) +uint32_t sunxi_get_boot_device(void); + #endif diff --git a/arch/arm/include/asm/arch-sunxi/usb_phy.h b/arch/arm/include/asm/arch-sunxi/usb_phy.h index cef6c98..5a9cacb 100644 --- a/arch/arm/include/asm/arch-sunxi/usb_phy.h +++ b/arch/arm/include/asm/arch-sunxi/usb_phy.h @@ -19,10 +19,3 @@ void sunxi_usb_phy_power_off(int index); int sunxi_usb_phy_vbus_detect(int index); int sunxi_usb_phy_id_detect(int index); void sunxi_usb_phy_enable_squelch_detect(int index, int enable); - -/* Not really phy related, but we have to declare this somewhere ... */ -#if defined(CONFIG_USB_MUSB_HOST) || defined(CONFIG_USB_MUSB_GADGET) -void sunxi_musb_board_init(void); -#else -#define sunxi_musb_board_init() -#endif diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a20702e..efc515e 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -61,6 +61,27 @@ #include <asm/io.h> #include <asm/barriers.h> +/* read L2 control register (L2CTLR) */ +static inline uint32_t read_l2ctlr(void) +{ + uint32_t val = 0; + + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); + + return val; +} + +/* write L2 control register (L2CTLR) */ +static inline void write_l2ctlr(uint32_t val) +{ + /* + * Note: L2CTLR can only be written when the L2 memory system + * is idle, ie before the MMU is enabled. + */ + asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory"); + isb(); +} + /* * Workaround for ARM errata # 798870 * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 5834f5b..5df7472 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -35,35 +35,6 @@ static inline void sync(void) } /* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)((unsigned long)paddr); -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -static inline phys_addr_t virt_to_phys(void * vaddr) -{ - return (phys_addr_t)((unsigned long)vaddr); -} - -/* * Generic virtual read/write. Note that we don't support half-word * read/writes. We define __arch_*[bl] here, and leave __arch_*w * to the architecture specific code. @@ -426,6 +397,7 @@ out: #endif /* __mem_isa */ #endif /* __KERNEL__ */ +#include <asm-generic/io.h> #include <iotrace.h> #endif /* __ASM_ARM_IO_H */ diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h index e1916f7..0c8652a 100644 --- a/arch/arm/include/asm/macro.h +++ b/arch/arm/include/asm/macro.h @@ -131,6 +131,7 @@ lr .req x30 /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */ mrs \xreg1, mpidr_el1 lsr \xreg2, \xreg1, #32 + lsl \xreg2, \xreg2, #32 lsl \xreg1, \xreg1, #40 lsr \xreg1, \xreg1, #40 orr \xreg1, \xreg1, \xreg2 diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 62fad45..9c46c93 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -95,8 +95,7 @@ ENTRY(_main) */ ldr x0, [x18, #GD_START_ADDR_SP] /* x0 <- gd->start_addr_sp */ bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ - ldr x18, [x18, #GD_BD] /* x18 <- gd->bd */ - sub x18, x18, #GD_SIZE /* new GD is below bd */ + ldr x18, [x18, #GD_NEW_GD] /* x18 <- gd->new_gd */ adr lr, relocation_return ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */ diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S index c760053..fdba004 100644 --- a/arch/arm/lib/relocate_64.S +++ b/arch/arm/lib/relocate_64.S @@ -73,6 +73,6 @@ relocate_done: isb sy 4: ldp x0, x1, [sp, #16] bl __asm_flush_dcache_range -5: ldp x29, x30, [sp],#16 +5: ldp x29, x30, [sp],#32 ret ENDPROC(relocate_code) diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 0e71b69..7e85b69 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -141,6 +141,7 @@ config TARGET_AT91SAM9X5EK select AT91SAM9X5 select SUPPORT_SPL select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT config TARGET_SAMA5D2_PTC bool "SAMA5D2 PTC board" @@ -153,6 +154,7 @@ config TARGET_SAMA5D2_XPLAINED select SAMA5D2 select SUPPORT_SPL select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT config TARGET_SAMA5D27_SOM1_EK bool "SAMA5D27 SOM1 EK board" @@ -185,12 +187,14 @@ config TARGET_SAMA5D4_XPLAINED select SAMA5D4 select SUPPORT_SPL select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT config TARGET_SAMA5D4EK bool "SAMA5D4 Evaluation Kit" select SAMA5D4 select SUPPORT_SPL select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT config TARGET_MA5D4EVK bool "Aries MA5D4EVK Evaluation Kit" diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 5944f99..fb94c96 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -99,7 +99,7 @@ u32 spl_boot_device(void) #ifdef CONFIG_SPL_USB_GADGET_SUPPORT int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) { - put_unaligned(CONFIG_G_DNL_PRODUCT_NUM + 0xfff, &dev->idProduct); + put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM + 0xfff, &dev->idProduct); return 0; } diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 1445731..74a63dd 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -62,6 +62,11 @@ int mvebu_soc_family(void) case SOC_88F6820_ID: case SOC_88F6828_ID: return MVEBU_SOC_A38X; + + case SOC_98DX3236_ID: + case SOC_98DX3336_ID: + case SOC_98DX4251_ID: + return MVEBU_SOC_MSYS; } return MVEBU_SOC_UNKNOWN; @@ -107,13 +112,15 @@ static const struct sar_freq_modes sar_freq_tab[] = { #elif defined(CONFIG_ARMADA_38X) /* SAR frequency values for Armada 38x */ static const struct sar_freq_modes sar_freq_tab[] = { - { 0x0, 0x0, 666, 333, 333 }, - { 0x2, 0x0, 800, 400, 400 }, - { 0x4, 0x0, 1066, 533, 533 }, - { 0x6, 0x0, 1200, 600, 600 }, - { 0x8, 0x0, 1332, 666, 666 }, - { 0xc, 0x0, 1600, 800, 800 }, - { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ + { 0x0, 0x0, 666, 333, 333 }, + { 0x2, 0x0, 800, 400, 400 }, + { 0x4, 0x0, 1066, 533, 533 }, + { 0x6, 0x0, 1200, 600, 600 }, + { 0x8, 0x0, 1332, 666, 666 }, + { 0xc, 0x0, 1600, 800, 800 }, + { 0x10, 0x0, 1866, 933, 933 }, + { 0x13, 0x0, 2000, 1000, 933 }, + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ }; #else /* SAR frequency values for Armada XP */ @@ -208,6 +215,15 @@ int print_cpuinfo(void) case SOC_88F6828_ID: puts("MV88F6828-"); break; + case SOC_98DX3236_ID: + puts("98DX3236-"); + break; + case SOC_98DX3336_ID: + puts("98DX3336-"); + break; + case SOC_98DX4251_ID: + puts("98DX4251-"); + break; default: puts("Unknown-"); break; diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c index e3f304c..e634905 100644 --- a/arch/arm/mach-mvebu/dram.c +++ b/arch/arm/mach-mvebu/dram.c @@ -179,11 +179,11 @@ static void dram_ecc_scrubbing(void) reg_write(REG_SDRAM_CONFIG_ADDR, temp); for (cs = 0; cs < CONFIG_NR_DRAM_BANKS; cs++) { - size = mvebu_sdram_bs(cs) - 1; + size = mvebu_sdram_bs(cs); if (size == 0) continue; - total = (u64)size + 1; + total = (u64)size; total_mem += (u32)(total / (1 << 30)); start_addr = 0; mv_xor_init2(cs); @@ -194,7 +194,7 @@ static void dram_ecc_scrubbing(void) size -= start_addr; } - mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size, + mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size - 1, SCRUB_MAGIC, SCRUB_MAGIC); /* Wait for previous transfer completion */ @@ -216,6 +216,35 @@ static int ecc_enabled(void) return 0; } + +/* Return the width of the DRAM bus, or 0 for unknown. */ +static int bus_width(void) +{ + int full_width = 0; + + if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS)) + full_width = 1; + + switch (mvebu_soc_family()) { + case MVEBU_SOC_AXP: + return full_width ? 64 : 32; + break; + case MVEBU_SOC_A375: + case MVEBU_SOC_A38X: + case MVEBU_SOC_MSYS: + return full_width ? 32 : 16; + default: + return 0; + } +} + +static int cycle_mode(void) +{ + int val = reg_read(REG_DUNIT_CTRL_LOW_ADDR); + + return (val >> REG_DUNIT_CTRL_LOW_2T_OFFS) & REG_DUNIT_CTRL_LOW_2T_MASK; +} + #else static void dram_ecc_scrubbing(void) { @@ -295,10 +324,26 @@ int dram_init_banksize(void) void board_add_ram_info(int use_default) { struct sar_freq_modes sar_freq; + int mode; + int width; get_sar_freq(&sar_freq); printf(" (%d MHz, ", sar_freq.d_clk); + width = bus_width(); + if (width) + printf("%d-bit, ", width); + + mode = cycle_mode(); + /* Mode 0 = Single cycle + * Mode 1 = Two cycles (2T) + * Mode 2 = Three cycles (3T) + */ + if (mode == 1) + printf("2T, "); + if (mode == 2) + printf("3T, "); + if (ecc_enabled()) printf("ECC"); else diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 2dc9b1d..cfd0952 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -76,9 +76,6 @@ */ #ifdef CONFIG_CMD_NET #define CONFIG_MII /* expose smi ove miiphy interface */ -#if !defined(CONFIG_ARMADA_375) -#define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */ -#endif #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ #define CONFIG_ARP_TIMEOUT 200 #define CONFIG_NET_RETRY_COUNT 50 diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index d241eea..b67b77a 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -65,6 +65,7 @@ enum { MVEBU_SOC_AXP, MVEBU_SOC_A375, MVEBU_SOC_A38X, + MVEBU_SOC_MSYS, MVEBU_SOC_UNKNOWN, }; diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 0900e40..1d30276 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -18,6 +18,9 @@ #define SOC_88F6810_ID 0x6810 #define SOC_88F6820_ID 0x6820 #define SOC_88F6828_ID 0x6828 +#define SOC_98DX3236_ID 0xf410 +#define SOC_98DX3336_ID 0xf400 +#define SOC_98DX4251_ID 0xfc00 /* A375 revisions */ #define MV_88F67XX_A0_ID 0x3 @@ -139,6 +142,7 @@ #define BOOT_DEV_SEL_MASK (0x3f << BOOT_DEV_SEL_OFFS) #define BOOT_FROM_UART 0x28 +#define BOOT_FROM_UART_ALT 0x3f #define BOOT_FROM_SPI 0x32 #define BOOT_FROM_MMC 0x30 #define BOOT_FROM_MMC_ALT 0x31 diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c index 3cf02a5..a72a769 100644 --- a/arch/arm/mach-mvebu/spl.c +++ b/arch/arm/mach-mvebu/spl.c @@ -42,6 +42,9 @@ static u32 get_boot_device(void) return BOOT_DEVICE_MMC1; #endif case BOOT_FROM_UART: +#ifdef BOOT_FROM_UART_ALT + case BOOT_FROM_UART_ALT: +#endif return BOOT_DEVICE_UART; case BOOT_FROM_SPI: default: diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 913a44a..ae86b69 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -241,7 +241,7 @@ int arch_misc_init(void) #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER) ret = usb_ether_init(); if (ret) { - error("USB ether init failed\n"); + pr_err("USB ether init failed\n"); return ret; } #endif diff --git a/arch/arm/mach-omap2/hwinit-common.c b/arch/arm/mach-omap2/hwinit-common.c index 7324d52..56890a0 100644 --- a/arch/arm/mach-omap2/hwinit-common.c +++ b/arch/arm/mach-omap2/hwinit-common.c @@ -165,9 +165,11 @@ void early_system_init(void) * to prevent overwrites. */ save_omap_boot_params(); - spl_early_init(); #endif do_board_detect(); +#ifdef CONFIG_SPL_BUILD + spl_early_init(); +#endif vcores_init(); #ifdef CONFIG_DEBUG_UART_OMAP debug_uart_init(); diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index 11f5f05..4dbf9a2 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -22,6 +22,11 @@ choice config TARGET_AM3517_EVM bool "AM3517 EVM" + select DM + select DM_SERIAL + select DM_GPIO + select DM_I2C + select DM_MMC config TARGET_MT_VENTOUX bool "TeeJet Mt.Ventoux" diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 52e1785..2630e7d 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -41,6 +41,9 @@ #define PPA_SERV_HAL_SETUP_EMIF_FW_REGION (PPA_HAL_SERVICES_START_INDEX + 26) #define PPA_SERV_HAL_LOCK_EMIF_FW (PPA_HAL_SERVICES_START_INDEX + 27) +/* Offset of header size if image is signed as ISW */ +#define HEADER_SIZE_OFFSET (0x6D) + int tee_loaded = 0; /* Argument for PPA_SERV_HAL_TEE_LOAD_MASTER */ @@ -125,6 +128,9 @@ int secure_boot_verify_image(void **image, size_t *size) } *size = sig_addr - cert_addr; /* Subtract out the signature size */ + /* Subtract header if present */ + if (strncmp((char *)sig_addr, "CERT_ISW_", 9) == 0) + *size = ((u32 *)*image)[HEADER_SIZE_OFFSET]; cert_size = *size; /* Check if image load address is 32-bit aligned */ diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c index 0b0bf18..d4f171b 100644 --- a/arch/arm/mach-omap2/utils.c +++ b/arch/arm/mach-omap2/utils.c @@ -87,15 +87,14 @@ static u32 omap_mmc_get_part_size(const char *part) dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV); if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) { - error("invalid mmc device\n"); + pr_err("invalid mmc device\n"); return 0; } - res = part_get_info_by_name(dev_desc, part, &info); - if (res < 0) { - error("cannot find partition: '%s'\n", part); + /* Check only for EFI (GPT) partition table */ + res = part_get_info_by_name_type(dev_desc, part, &info, PART_TYPE_EFI); + if (res < 0) return 0; - } /* Calculate size in bytes */ sz = (info.size * (u64)info.blksz); @@ -111,13 +110,10 @@ static void omap_set_fastboot_userdata_size(void) u32 sz_kb; sz_kb = omap_mmc_get_part_size("userdata"); - if (sz_kb == 0) { - buf[0] = '\0'; - printf("Warning: fastboot.userdata_size: unable to calc\n"); - } else { - sprintf(buf, "%u", sz_kb); - } + if (sz_kb == 0) + return; /* probably it's not Android partition table */ + sprintf(buf, "%u", sz_kb); env_set("fastboot.userdata_size", buf); } #else diff --git a/arch/arm/mach-qemu/Kconfig b/arch/arm/mach-qemu/Kconfig new file mode 100644 index 0000000..3500b56 --- /dev/null +++ b/arch/arm/mach-qemu/Kconfig @@ -0,0 +1,12 @@ +if ARCH_QEMU + +config SYS_VENDOR + default "emulation" + +config SYS_BOARD + default "qemu-arm" + +config SYS_CONFIG_NAME + default "qemu-arm" + +endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 79e9704..daafc8d 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -12,6 +12,7 @@ obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o +obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index d3866bf..406207e 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -151,7 +151,7 @@ void board_init_f(ulong dummy) */ pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); if (IS_ERR(pmu)) - error("pmu syscon returned %ld\n", PTR_ERR(pmu)); + pr_err("pmu syscon returned %ld\n", PTR_ERR(pmu)); SAVE_SP_ADDR = readl(&pmu->sys_reg[2]); ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index 622e046..96859a5 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -26,7 +26,7 @@ int board_late_init(void) grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); if (IS_ERR(grf)) { - error("grf syscon returned %ld\n", PTR_ERR(grf)); + pr_err("grf syscon returned %ld\n", PTR_ERR(grf)); } else { /* enable noc remap to mimic legacy loaders */ rk_clrsetreg(&grf->soc_con0, diff --git a/arch/arm/mach-rockchip/rk3188/Makefile b/arch/arm/mach-rockchip/rk3188/Makefile index 2dc9511..7fa0104 100644 --- a/arch/arm/mach-rockchip/rk3188/Makefile +++ b/arch/arm/mach-rockchip/rk3188/Makefile @@ -6,6 +6,5 @@ ifndef CONFIG_TPL_BUILD obj-y += clk_rk3188.o -obj-y += sdram_rk3188.o obj-y += syscon_rk3188.o endif diff --git a/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c b/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c deleted file mode 100644 index 9d8b225..0000000 --- a/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c +++ /dev/null @@ -1,953 +0,0 @@ -/* - * (C) Copyright 2015 Google, Inc - * Copyright 2014 Rockchip Inc. - * - * SPDX-License-Identifier: GPL-2.0 - * - * Adapted from the very similar rk3288 ddr init. - */ - -#include <common.h> -#include <clk.h> -#include <dm.h> -#include <dt-structs.h> -#include <errno.h> -#include <ram.h> -#include <regmap.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3188.h> -#include <asm/arch/ddr_rk3188.h> -#include <asm/arch/grf_rk3188.h> -#include <asm/arch/pmu_rk3188.h> -#include <asm/arch/sdram.h> -#include <asm/arch/sdram_common.h> -#include <linux/err.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct chan_info { - struct rk3288_ddr_pctl *pctl; - struct rk3288_ddr_publ *publ; - struct rk3188_msch *msch; -}; - -struct dram_info { - struct chan_info chan[1]; - struct ram_info info; - struct clk ddr_clk; - struct rk3188_cru *cru; - struct rk3188_grf *grf; - struct rk3188_sgrf *sgrf; - struct rk3188_pmu *pmu; -}; - -struct rk3188_sdram_params { -#if CONFIG_IS_ENABLED(OF_PLATDATA) - struct dtd_rockchip_rk3188_dmc of_plat; -#endif - struct rk3288_sdram_channel ch[2]; - struct rk3288_sdram_pctl_timing pctl_timing; - struct rk3288_sdram_phy_timing phy_timing; - struct rk3288_base_params base; - int num_channels; - struct regmap *map; -}; - -const int ddrconf_table[] = { - /* - * [5:4] row(13+n) - * [1:0] col(9+n), assume bw=2 - * row col,bw - */ - 0, - ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), - ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), - ((0 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), - ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), - ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), - ((0 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), - ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), - ((0 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), - 0, - 0, - 0, - 0, - 0, - 0, - 0, -}; - -#define TEST_PATTEN 0x5aa5f00f -#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4) -#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4) - -#ifdef CONFIG_SPL_BUILD -static void copy_to_reg(u32 *dest, const u32 *src, u32 n) -{ - int i; - - for (i = 0; i < n / sizeof(u32); i++) { - writel(*src, dest); - src++; - dest++; - } -} - -static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) -{ - u32 phy_ctl_srstn_shift = 13; - u32 ctl_psrstn_shift = 11; - u32 ctl_srstn_shift = 10; - u32 phy_psrstn_shift = 9; - u32 phy_srstn_shift = 8; - - rk_clrsetreg(&cru->cru_softrst_con[5], - 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift | - 1 << ctl_srstn_shift | 1 << phy_psrstn_shift | - 1 << phy_srstn_shift, - phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift | - ctl << ctl_srstn_shift | phy << phy_psrstn_shift | - phy << phy_srstn_shift); -} - -static void ddr_phy_ctl_reset(struct rk3188_cru *cru, u32 ch, u32 n) -{ - u32 phy_ctl_srstn_shift = 13; - - rk_clrsetreg(&cru->cru_softrst_con[5], - 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift); -} - -static void phy_pctrl_reset(struct rk3188_cru *cru, - struct rk3288_ddr_publ *publ, - int channel) -{ - int i; - - ddr_reset(cru, channel, 1, 1); - udelay(1); - clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); - for (i = 0; i < 4; i++) - clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); - - udelay(10); - setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); - for (i = 0; i < 4; i++) - setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); - - udelay(10); - ddr_reset(cru, channel, 1, 0); - udelay(10); - ddr_reset(cru, channel, 0, 0); - udelay(10); -} - -static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ, - u32 freq) -{ - int i; - - if (freq <= 250000000) { - if (freq <= 150000000) - clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); - else - setbits_le32(&publ->dllgcr, SBIAS_BYPASS); - setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); - for (i = 0; i < 4; i++) - setbits_le32(&publ->datx8[i].dxdllcr, - DXDLLCR_DLLDIS); - - setbits_le32(&publ->pir, PIR_DLLBYP); - } else { - clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); - clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); - for (i = 0; i < 4; i++) { - clrbits_le32(&publ->datx8[i].dxdllcr, - DXDLLCR_DLLDIS); - } - - clrbits_le32(&publ->pir, PIR_DLLBYP); - } -} - -static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) -{ - writel(DFI_INIT_START, &pctl->dfistcfg0); - writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, - &pctl->dfistcfg1); - writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); - writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, - &pctl->dfilpcfg0); - - writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); - writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); - writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); - writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); - writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); - writel(1, &pctl->dfitphyupdtype0); - - /* cs0 and cs1 write odt enable */ - writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), - &pctl->dfiodtcfg); - /* odt write length */ - writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); - /* phyupd and ctrlupd disabled */ - writel(0, &pctl->dfiupdcfg); -} - -static void ddr_set_enable(struct rk3188_grf *grf, uint channel, bool enable) -{ - uint val = 0; - - if (enable) - val = 1 << DDR_16BIT_EN_SHIFT; - - rk_clrsetreg(&grf->ddrc_con0, 1 << DDR_16BIT_EN_SHIFT, val); -} - -static void ddr_set_ddr3_mode(struct rk3188_grf *grf, uint channel, - bool ddr3_mode) -{ - uint mask, val; - - mask = MSCH4_MAINDDR3_MASK << MSCH4_MAINDDR3_SHIFT; - val = ddr3_mode << MSCH4_MAINDDR3_SHIFT; - rk_clrsetreg(&grf->soc_con2, mask, val); -} - -static void ddr_rank_2_row15en(struct rk3188_grf *grf, bool enable) -{ - uint mask, val; - - mask = RANK_TO_ROW15_EN_MASK << RANK_TO_ROW15_EN_SHIFT; - val = enable << RANK_TO_ROW15_EN_SHIFT; - rk_clrsetreg(&grf->soc_con2, mask, val); -} - -static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, - struct rk3188_sdram_params *sdram_params, - struct rk3188_grf *grf) -{ - copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, - sizeof(sdram_params->pctl_timing)); - switch (sdram_params->base.dramtype) { - case DDR3: - if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { - writel(sdram_params->pctl_timing.tcl - 3, - &pctl->dfitrddataen); - } else { - writel(sdram_params->pctl_timing.tcl - 2, - &pctl->dfitrddataen); - } - writel(sdram_params->pctl_timing.tcwl - 1, - &pctl->dfitphywrlat); - writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN | - DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | - 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, - &pctl->mcfg); - ddr_set_ddr3_mode(grf, channel, true); - ddr_set_enable(grf, channel, true); - break; - } - - setbits_le32(&pctl->scfg, 1); -} - -static void phy_cfg(const struct chan_info *chan, int channel, - struct rk3188_sdram_params *sdram_params) -{ - struct rk3288_ddr_publ *publ = chan->publ; - struct rk3188_msch *msch = chan->msch; - uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; - u32 dinit2; - int i; - - dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000); - /* DDR PHY Timing */ - copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, - sizeof(sdram_params->phy_timing)); - writel(sdram_params->base.noc_timing, &msch->ddrtiming); - writel(0x3f, &msch->readlatency); - writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT | - DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT | - 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); - writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT | - DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT, - &publ->ptr[1]); - writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT | - DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT, - &publ->ptr[2]); - - switch (sdram_params->base.dramtype) { - case DDR3: - clrbits_le32(&publ->pgcr, 0x1f); - clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, - DDRMD_DDR3 << DDRMD_SHIFT); - break; - } - if (sdram_params->base.odt) { - /*dynamic RTT enable */ - for (i = 0; i < 4; i++) - setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); - } else { - /*dynamic RTT disable */ - for (i = 0; i < 4; i++) - clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); - } -} - -static void phy_init(struct rk3288_ddr_publ *publ) -{ - setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST - | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); - udelay(1); - while ((readl(&publ->pgsr) & - (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) != - (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) - ; -} - -static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, - u32 cmd, u32 arg) -{ - writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); - udelay(1); - while (readl(&pctl->mcmd) & START_CMD) - ; -} - -static inline void send_command_op(struct rk3288_ddr_pctl *pctl, - u32 rank, u32 cmd, u32 ma, u32 op) -{ - send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | - (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT); -} - -static void memory_init(struct rk3288_ddr_publ *publ, - u32 dramtype) -{ - setbits_le32(&publ->pir, - (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP - | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC - | (dramtype == DDR3 ? PIR_DRAMRST : 0))); - udelay(1); - while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) - != (PGSR_IDONE | PGSR_DLDONE)) - ; -} - -static void move_to_config_state(struct rk3288_ddr_publ *publ, - struct rk3288_ddr_pctl *pctl) -{ - unsigned int state; - - while (1) { - state = readl(&pctl->stat) & PCTL_STAT_MSK; - - switch (state) { - case LOW_POWER: - writel(WAKEUP_STATE, &pctl->sctl); - while ((readl(&pctl->stat) & PCTL_STAT_MSK) - != ACCESS) - ; - /* wait DLL lock */ - while ((readl(&publ->pgsr) & PGSR_DLDONE) - != PGSR_DLDONE) - ; - /* - * if at low power state,need wakeup first, - * and then enter the config, so - * fallthrough - */ - case ACCESS: - /* fallthrough */ - case INIT_MEM: - writel(CFG_STATE, &pctl->sctl); - while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) - ; - break; - case CONFIG: - return; - default: - break; - } - } -} - -static void set_bandwidth_ratio(const struct chan_info *chan, int channel, - u32 n, struct rk3188_grf *grf) -{ - struct rk3288_ddr_pctl *pctl = chan->pctl; - struct rk3288_ddr_publ *publ = chan->publ; - struct rk3188_msch *msch = chan->msch; - - if (n == 1) { - setbits_le32(&pctl->ppcfg, 1); - ddr_set_enable(grf, channel, 1); - setbits_le32(&msch->ddrtiming, 1 << 31); - /* Data Byte disable*/ - clrbits_le32(&publ->datx8[2].dxgcr, 1); - clrbits_le32(&publ->datx8[3].dxgcr, 1); - /* disable DLL */ - setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); - setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); - } else { - clrbits_le32(&pctl->ppcfg, 1); - ddr_set_enable(grf, channel, 0); - clrbits_le32(&msch->ddrtiming, 1 << 31); - /* Data Byte enable*/ - setbits_le32(&publ->datx8[2].dxgcr, 1); - setbits_le32(&publ->datx8[3].dxgcr, 1); - - /* enable DLL */ - clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); - clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); - /* reset DLL */ - clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); - clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); - udelay(10); - setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); - setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); - } - setbits_le32(&pctl->dfistcfg0, 1 << 2); -} - -static int data_training(const struct chan_info *chan, int channel, - struct rk3188_sdram_params *sdram_params) -{ - unsigned int j; - int ret = 0; - u32 rank; - int i; - u32 step[2] = { PIR_QSTRN, PIR_RVTRN }; - struct rk3288_ddr_publ *publ = chan->publ; - struct rk3288_ddr_pctl *pctl = chan->pctl; - - /* disable auto refresh */ - writel(0, &pctl->trefi); - - if (sdram_params->base.dramtype != LPDDR3) - setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); - rank = sdram_params->ch[channel].rank | 1; - for (j = 0; j < ARRAY_SIZE(step); j++) { - /* - * trigger QSTRN and RVTRN - * clear DTDONE status - */ - setbits_le32(&publ->pir, PIR_CLRSR); - - /* trigger DTT */ - setbits_le32(&publ->pir, - PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | - PIR_CLRSR); - udelay(1); - /* wait echo byte DTDONE */ - while ((readl(&publ->datx8[0].dxgsr[0]) & rank) - != rank) - ; - while ((readl(&publ->datx8[1].dxgsr[0]) & rank) - != rank) - ; - if (!(readl(&pctl->ppcfg) & 1)) { - while ((readl(&publ->datx8[2].dxgsr[0]) - & rank) != rank) - ; - while ((readl(&publ->datx8[3].dxgsr[0]) - & rank) != rank) - ; - } - if (readl(&publ->pgsr) & - (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) { - ret = -1; - break; - } - } - /* send some auto refresh to complement the lost while DTT */ - for (i = 0; i < (rank > 1 ? 8 : 4); i++) - send_command(pctl, rank, REF_CMD, 0); - - if (sdram_params->base.dramtype != LPDDR3) - clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); - - /* resume auto refresh */ - writel(sdram_params->pctl_timing.trefi, &pctl->trefi); - - return ret; -} - -static void move_to_access_state(const struct chan_info *chan) -{ - struct rk3288_ddr_publ *publ = chan->publ; - struct rk3288_ddr_pctl *pctl = chan->pctl; - unsigned int state; - - while (1) { - state = readl(&pctl->stat) & PCTL_STAT_MSK; - - switch (state) { - case LOW_POWER: - if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & - LP_TRIG_MASK) == 1) - return; - - writel(WAKEUP_STATE, &pctl->sctl); - while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) - ; - /* wait DLL lock */ - while ((readl(&publ->pgsr) & PGSR_DLDONE) - != PGSR_DLDONE) - ; - break; - case INIT_MEM: - writel(CFG_STATE, &pctl->sctl); - while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) - ; - /* fallthrough */ - case CONFIG: - writel(GO_STATE, &pctl->sctl); - while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) - ; - break; - case ACCESS: - return; - default: - break; - } - } -} - -static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum, - struct rk3188_sdram_params *sdram_params) -{ - struct rk3288_ddr_publ *publ = chan->publ; - - if (sdram_params->ch[chnum].bk == 3) - clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, - 1 << PDQ_SHIFT); - else - clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); - - writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); -} - -static void dram_all_config(const struct dram_info *dram, - struct rk3188_sdram_params *sdram_params) -{ - unsigned int chan; - u32 sys_reg = 0; - - sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; - sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; - for (chan = 0; chan < sdram_params->num_channels; chan++) { - const struct rk3288_sdram_channel *info = - &sdram_params->ch[chan]; - - sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); - sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); - sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); - sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); - sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); - sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); - sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); - sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); - sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); - - dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); - } - if (sdram_params->ch[0].rank == 2) - ddr_rank_2_row15en(dram->grf, 0); - else - ddr_rank_2_row15en(dram->grf, 1); - - writel(sys_reg, &dram->pmu->sys_reg[2]); -} - -static int sdram_rank_bw_detect(struct dram_info *dram, int channel, - struct rk3188_sdram_params *sdram_params) -{ - int reg; - int need_trainig = 0; - const struct chan_info *chan = &dram->chan[channel]; - struct rk3288_ddr_publ *publ = chan->publ; - - ddr_rank_2_row15en(dram->grf, 0); - - if (data_training(chan, channel, sdram_params) < 0) { - printf("first data training fail!\n"); - reg = readl(&publ->datx8[0].dxgsr[0]); - /* Check the result for rank 0 */ - if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { - printf("data training fail!\n"); - return -EIO; - } - - /* Check the result for rank 1 */ - if (reg & DQS_GATE_TRAINING_ERROR_RANK1) { - sdram_params->ch[channel].rank = 1; - clrsetbits_le32(&publ->pgcr, 0xF << 18, - sdram_params->ch[channel].rank << 18); - need_trainig = 1; - } - reg = readl(&publ->datx8[2].dxgsr[0]); - if (reg & (1 << 4)) { - sdram_params->ch[channel].bw = 1; - set_bandwidth_ratio(chan, channel, - sdram_params->ch[channel].bw, - dram->grf); - need_trainig = 1; - } - } - /* Assume the Die bit width are the same with the chip bit width */ - sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; - - if (need_trainig && - (data_training(chan, channel, sdram_params) < 0)) { - if (sdram_params->base.dramtype == LPDDR3) { - ddr_phy_ctl_reset(dram->cru, channel, 1); - udelay(10); - ddr_phy_ctl_reset(dram->cru, channel, 0); - udelay(10); - } - printf("2nd data training failed!"); - return -EIO; - } - - return 0; -} - -/* - * Detect ram columns and rows. - * @dram: dram info struct - * @channel: channel number to handle - * @sdram_params: sdram parameters, function will fill in col and row values - * - * Returns 0 or negative on error. - */ -static int sdram_col_row_detect(struct dram_info *dram, int channel, - struct rk3188_sdram_params *sdram_params) -{ - int row, col; - unsigned int addr; - const struct chan_info *chan = &dram->chan[channel]; - struct rk3288_ddr_pctl *pctl = chan->pctl; - struct rk3288_ddr_publ *publ = chan->publ; - int ret = 0; - - /* Detect col */ - for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + - (1 << (col + sdram_params->ch[channel].bw - 1)); - writel(TEST_PATTEN, addr); - if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) - break; - } - if (col == 8) { - printf("Col detect error\n"); - ret = -EINVAL; - goto out; - } else { - sdram_params->ch[channel].col = col; - } - - ddr_rank_2_row15en(dram->grf, 1); - move_to_config_state(publ, pctl); - writel(1, &chan->msch->ddrconf); - move_to_access_state(chan); - /* Detect row, max 15,min13 in rk3188*/ - for (row = 16; row >= 13; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); - writel(TEST_PATTEN, addr); - if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) - break; - } - if (row == 12) { - printf("Row detect error\n"); - ret = -EINVAL; - } else { - sdram_params->ch[channel].cs1_row = row; - sdram_params->ch[channel].row_3_4 = 0; - debug("chn %d col %d, row %d\n", channel, col, row); - sdram_params->ch[channel].cs0_row = row; - } - -out: - return ret; -} - -static int sdram_get_niu_config(struct rk3188_sdram_params *sdram_params) -{ - int i, tmp, size, ret = 0; - - tmp = sdram_params->ch[0].col - 9; - tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; - tmp |= ((sdram_params->ch[0].cs0_row - 13) << 4); - size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]); - for (i = 0; i < size; i++) - if (tmp == ddrconf_table[i]) - break; - if (i >= size) { - printf("niu config not found\n"); - ret = -EINVAL; - } else { - debug("niu config %d\n", i); - sdram_params->base.ddrconfig = i; - } - - return ret; -} - -static int sdram_init(struct dram_info *dram, - struct rk3188_sdram_params *sdram_params) -{ - int channel; - int zqcr; - int ret; - - if ((sdram_params->base.dramtype == DDR3 && - sdram_params->base.ddr_freq > 800000000)) { - printf("SDRAM frequency is too high!"); - return -E2BIG; - } - - ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); - if (ret) { - printf("Could not set DDR clock\n"); - return ret; - } - - for (channel = 0; channel < 1; channel++) { - const struct chan_info *chan = &dram->chan[channel]; - struct rk3288_ddr_pctl *pctl = chan->pctl; - struct rk3288_ddr_publ *publ = chan->publ; - - phy_pctrl_reset(dram->cru, publ, channel); - phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); - - dfi_cfg(pctl, sdram_params->base.dramtype); - - pctl_cfg(channel, pctl, sdram_params, dram->grf); - - phy_cfg(chan, channel, sdram_params); - - phy_init(publ); - - writel(POWER_UP_START, &pctl->powctl); - while (!(readl(&pctl->powstat) & POWER_UP_DONE)) - ; - - memory_init(publ, sdram_params->base.dramtype); - move_to_config_state(publ, pctl); - - /* Using 32bit bus width for detect */ - sdram_params->ch[channel].bw = 2; - set_bandwidth_ratio(chan, channel, - sdram_params->ch[channel].bw, dram->grf); - /* - * set cs, using n=3 for detect - * CS0, n=1 - * CS1, n=2 - * CS0 & CS1, n = 3 - */ - sdram_params->ch[channel].rank = 2, - clrsetbits_le32(&publ->pgcr, 0xF << 18, - (sdram_params->ch[channel].rank | 1) << 18); - - /* DS=40ohm,ODT=155ohm */ - zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT | - 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT | - 0x19 << PD_OUTPUT_SHIFT; - writel(zqcr, &publ->zq1cr[0]); - writel(zqcr, &publ->zq0cr[0]); - - /* Detect the rank and bit-width with data-training */ - writel(1, &chan->msch->ddrconf); - sdram_rank_bw_detect(dram, channel, sdram_params); - - if (sdram_params->base.dramtype == LPDDR3) { - u32 i; - writel(0, &pctl->mrrcfg0); - for (i = 0; i < 17; i++) - send_command_op(pctl, 1, MRR_CMD, i, 0); - } - writel(4, &chan->msch->ddrconf); - move_to_access_state(chan); - /* DDR3 and LPDDR3 are always 8 bank, no need detect */ - sdram_params->ch[channel].bk = 3; - /* Detect Col and Row number*/ - ret = sdram_col_row_detect(dram, channel, sdram_params); - if (ret) - goto error; - } - /* Find NIU DDR configuration */ - ret = sdram_get_niu_config(sdram_params); - if (ret) - goto error; - - dram_all_config(dram, sdram_params); - debug("%s done\n", __func__); - - return 0; -error: - printf("DRAM init failed!\n"); - hang(); -} - -static int setup_sdram(struct udevice *dev) -{ - struct dram_info *priv = dev_get_priv(dev); - struct rk3188_sdram_params *params = dev_get_platdata(dev); - - return sdram_init(priv, params); -} - -static int rk3188_dmc_ofdata_to_platdata(struct udevice *dev) -{ -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rk3188_sdram_params *params = dev_get_platdata(dev); - int ret; - - /* rk3188 supports only one-channel */ - params->num_channels = 1; - ret = dev_read_u32_array(dev, "rockchip,pctl-timing", - (u32 *)¶ms->pctl_timing, - sizeof(params->pctl_timing) / sizeof(u32)); - if (ret) { - printf("%s: Cannot read rockchip,pctl-timing\n", __func__); - return -EINVAL; - } - ret = dev_read_u32_array(dev, "rockchip,phy-timing", - (u32 *)¶ms->phy_timing, - sizeof(params->phy_timing) / sizeof(u32)); - if (ret) { - printf("%s: Cannot read rockchip,phy-timing\n", __func__); - return -EINVAL; - } - ret = dev_read_u32_array(dev, "rockchip,sdram-params", - (u32 *)¶ms->base, - sizeof(params->base) / sizeof(u32)); - if (ret) { - printf("%s: Cannot read rockchip,sdram-params\n", __func__); - return -EINVAL; - } - ret = regmap_init_mem(dev, ¶ms->map); - if (ret) - return ret; -#endif - - return 0; -} -#endif /* CONFIG_SPL_BUILD */ - -#if CONFIG_IS_ENABLED(OF_PLATDATA) -static int conv_of_platdata(struct udevice *dev) -{ - struct rk3188_sdram_params *plat = dev_get_platdata(dev); - struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat; - int ret; - - memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, - sizeof(plat->pctl_timing)); - memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, - sizeof(plat->phy_timing)); - memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); - /* rk3188 supports dual-channel, set default channel num to 2 */ - plat->num_channels = 1; - ret = regmap_init_mem_platdata(dev, of_plat->reg, - ARRAY_SIZE(of_plat->reg) / 2, - &plat->map); - if (ret) - return ret; - - return 0; -} -#endif - -static int rk3188_dmc_probe(struct udevice *dev) -{ -#ifdef CONFIG_SPL_BUILD - struct rk3188_sdram_params *plat = dev_get_platdata(dev); - struct regmap *map; - struct udevice *dev_clk; - int ret; -#endif - struct dram_info *priv = dev_get_priv(dev); - - priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); - -#ifdef CONFIG_SPL_BUILD -#if CONFIG_IS_ENABLED(OF_PLATDATA) - ret = conv_of_platdata(dev); - if (ret) - return ret; -#endif - map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC); - if (IS_ERR(map)) - return PTR_ERR(map); - priv->chan[0].msch = regmap_get_range(map, 0); - - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - - priv->chan[0].pctl = regmap_get_range(plat->map, 0); - priv->chan[0].publ = regmap_get_range(plat->map, 1); - - ret = rockchip_get_clk(&dev_clk); - if (ret) - return ret; - priv->ddr_clk.id = CLK_DDR; - ret = clk_request(dev_clk, &priv->ddr_clk); - if (ret) - return ret; - - priv->cru = rockchip_get_cru(); - if (IS_ERR(priv->cru)) - return PTR_ERR(priv->cru); - ret = setup_sdram(dev); - if (ret) - return ret; -#else - priv->info.base = CONFIG_SYS_SDRAM_BASE; - priv->info.size = rockchip_sdram_size( - (phys_addr_t)&priv->pmu->sys_reg[2]); -#endif - - return 0; -} - -static int rk3188_dmc_get_info(struct udevice *dev, struct ram_info *info) -{ - struct dram_info *priv = dev_get_priv(dev); - - *info = priv->info; - - return 0; -} - -static struct ram_ops rk3188_dmc_ops = { - .get_info = rk3188_dmc_get_info, -}; - -static const struct udevice_id rk3188_dmc_ids[] = { - { .compatible = "rockchip,rk3188-dmc" }, - { } -}; - -U_BOOT_DRIVER(dmc_rk3188) = { - .name = "rockchip_rk3188_dmc", - .id = UCLASS_RAM, - .of_match = rk3188_dmc_ids, - .ops = &rk3188_dmc_ops, -#ifdef CONFIG_SPL_BUILD - .ofdata_to_platdata = rk3188_dmc_ofdata_to_platdata, -#endif - .probe = rk3188_dmc_probe, - .priv_auto_alloc_size = sizeof(struct dram_info), -#ifdef CONFIG_SPL_BUILD - .platdata_auto_alloc_size = sizeof(struct rk3188_sdram_params), -#endif -}; diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c index dcd8cf8..d443114 100644 --- a/arch/arm/mach-rockchip/rk322x-board.c +++ b/arch/arm/mach-rockchip/rk322x-board.c @@ -21,12 +21,12 @@ DECLARE_GLOBAL_DATA_PTR; static void setup_boot_mode(void) { struct rk322x_grf *const grf = (void *)GRF_BASE; - int boot_mode = readl(&grf->os_reg[4]); + int boot_mode = readl(&grf->os_reg[0]); debug("boot mode %x.\n", boot_mode); /* Clear boot mode */ - writel(BOOT_NORMAL, &grf->os_reg[4]); + writel(BOOT_NORMAL, &grf->os_reg[0]); switch (boot_mode) { case BOOT_FASTBOOT: diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 6b7bf85..7b7fd5a 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -19,7 +19,10 @@ #include <asm/arch/clock.h> #include <asm/arch/hardware.h> #include <asm/arch/periph.h> +#include <asm/arch/pmu_rk3288.h> #include <asm/arch/sdram.h> +#include <asm/arch/sdram_common.h> +#include <asm/arch/sys_proto.h> #include <asm/arch/timer.h> #include <dm/pinctrl.h> #include <dm/root.h> @@ -80,46 +83,6 @@ u32 spl_boot_mode(const u32 boot_device) return MMCSD_MODE_RAW; } -/* read L2 control register (L2CTLR) */ -static inline uint32_t read_l2ctlr(void) -{ - uint32_t val = 0; - - asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); - - return val; -} - -/* write L2 control register (L2CTLR) */ -static inline void write_l2ctlr(uint32_t val) -{ - /* - * Note: L2CTLR can only be written when the L2 memory system - * is idle, ie before the MMU is enabled. - */ - asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory"); - isb(); -} - -static void configure_l2ctlr(void) -{ - uint32_t l2ctlr; - - l2ctlr = read_l2ctlr(); - l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ - - /* - * Data RAM write latency: 2 cycles - * Data RAM read latency: 2 cycles - * Data RAM setup latency: 1 cycle - * Tag RAM write latency: 1 cycle - * Tag RAM read latency: 1 cycle - * Tag RAM setup latency: 1 cycle - */ - l2ctlr |= (1 << 3 | 1 << 0); - write_l2ctlr(l2ctlr); -} - #ifdef CONFIG_SPL_MMC_SUPPORT static int configure_emmc(struct udevice *pinctrl) { @@ -243,12 +206,15 @@ void board_init_f(ulong dummy) } #endif +#if !defined(CONFIG_SUPPORT_TPL) debug("\nspl:init dram\n"); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } +#endif + #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(); #endif @@ -326,3 +292,18 @@ err: /* No way to report error here */ hang(); } + +#ifdef CONFIG_SPL_OS_BOOT + +#define PMU_BASE 0xff730000 +int dram_init_banksize(void) +{ + struct rk3288_pmu *const pmu = (void *)PMU_BASE; + size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]); + + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = size; + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk3288-board-tpl.c b/arch/arm/mach-rockchip/rk3288-board-tpl.c new file mode 100644 index 0000000..3d08b5b --- /dev/null +++ b/arch/arm/mach-rockchip/rk3288-board-tpl.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2017 Amarula Solutions + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> +#include <version.h> +#include <asm/io.h> +#include <asm/arch/bootrom.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3288.h> +#include <asm/arch/periph.h> +#include <asm/arch/pmu_rk3288.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/timer.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define GRF_BASE 0xff770000 +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + /* Example code showing how to enable the debug UART on RK3288 */ + /* Enable early UART on the RK3288 */ + struct rk3288_grf * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | + GPIO7C6_MASK << GPIO7C6_SHIFT, + GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | + GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + rockchip_timer_init(); + configure_l2ctlr(); + + ret = rockchip_get_clk(&dev); + if (ret) { + debug("CLK init failed: %d\n", ret); + return; + } + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} + +void board_return_to_bootrom(void) +{ + back_to_bootrom(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \ + U_BOOT_TIME ")\n"); +} diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 4ad2940..6beb26f 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -87,6 +87,22 @@ config TARGET_POPMETAL_RK3288 config TARGET_VYASA_RK3288 bool "Vyasa-RK3288" select BOARD_LATE_INIT + select TPL + select SUPPORT_TPL + select TPL_DM + select TPL_REGMAP + select TPL_SYSCON + select TPL_CLK + select TPL_RAM + select TPL_OF_PLATDATA + select TPL_OF_CONTROL + select TPL_BOOTROM_SUPPORT + select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL + select ROCKCHIP_BROM_HELPER + select TPL_DRIVERS_MISC_SUPPORT + select TPL_LIBCOMMON_SUPPORT + select TPL_LIBGENERIC_SUPPORT + select TPL_SERIAL_SUPPORT help Vyasa is a RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It diff --git a/arch/arm/mach-rockchip/rk3288/Makefile b/arch/arm/mach-rockchip/rk3288/Makefile index b5b28ef..a0033a0 100644 --- a/arch/arm/mach-rockchip/rk3288/Makefile +++ b/arch/arm/mach-rockchip/rk3288/Makefile @@ -6,5 +6,4 @@ obj-y += clk_rk3288.o obj-y += rk3288.o -obj-y += sdram_rk3288.o obj-y += syscon_rk3288.o diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c deleted file mode 100644 index 95efb11..0000000 --- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c +++ /dev/null @@ -1,1125 +0,0 @@ -/* - * (C) Copyright 2015 Google, Inc - * Copyright 2014 Rockchip Inc. - * - * SPDX-License-Identifier: GPL-2.0 - * - * Adapted from coreboot. - */ - -#include <common.h> -#include <clk.h> -#include <dm.h> -#include <dt-structs.h> -#include <errno.h> -#include <ram.h> -#include <regmap.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3288.h> -#include <asm/arch/ddr_rk3288.h> -#include <asm/arch/grf_rk3288.h> -#include <asm/arch/pmu_rk3288.h> -#include <asm/arch/sdram.h> -#include <asm/arch/sdram_common.h> -#include <linux/err.h> -#include <power/regulator.h> -#include <power/rk8xx_pmic.h> - -DECLARE_GLOBAL_DATA_PTR; - -struct chan_info { - struct rk3288_ddr_pctl *pctl; - struct rk3288_ddr_publ *publ; - struct rk3288_msch *msch; -}; - -struct dram_info { - struct chan_info chan[2]; - struct ram_info info; - struct clk ddr_clk; - struct rk3288_cru *cru; - struct rk3288_grf *grf; - struct rk3288_sgrf *sgrf; - struct rk3288_pmu *pmu; - bool is_veyron; -}; - -struct rk3288_sdram_params { -#if CONFIG_IS_ENABLED(OF_PLATDATA) - struct dtd_rockchip_rk3288_dmc of_plat; -#endif - struct rk3288_sdram_channel ch[2]; - struct rk3288_sdram_pctl_timing pctl_timing; - struct rk3288_sdram_phy_timing phy_timing; - struct rk3288_base_params base; - int num_channels; - struct regmap *map; -}; - -const int ddrconf_table[] = { - /* row col,bw */ - 0, - ((1 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), - ((2 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), - ((3 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), - ((4 << DDRCONF_ROW_SHIFT) | 1 << DDRCONF_COL_SHIFT), - ((1 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), - ((2 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), - ((3 << DDRCONF_ROW_SHIFT) | 2 << DDRCONF_COL_SHIFT), - ((1 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), - ((2 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), - ((3 << DDRCONF_ROW_SHIFT) | 0 << DDRCONF_COL_SHIFT), - 0, - 0, - 0, - 0, - ((4 << 4) | 2), -}; - -#define TEST_PATTEN 0x5aa5f00f -#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4) -#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4) - -#ifdef CONFIG_SPL_BUILD -static void copy_to_reg(u32 *dest, const u32 *src, u32 n) -{ - int i; - - for (i = 0; i < n / sizeof(u32); i++) { - writel(*src, dest); - src++; - dest++; - } -} - -static void ddr_reset(struct rk3288_cru *cru, u32 ch, u32 ctl, u32 phy) -{ - u32 phy_ctl_srstn_shift = 4 + 5 * ch; - u32 ctl_psrstn_shift = 3 + 5 * ch; - u32 ctl_srstn_shift = 2 + 5 * ch; - u32 phy_psrstn_shift = 1 + 5 * ch; - u32 phy_srstn_shift = 5 * ch; - - rk_clrsetreg(&cru->cru_softrst_con[10], - 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift | - 1 << ctl_srstn_shift | 1 << phy_psrstn_shift | - 1 << phy_srstn_shift, - phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift | - ctl << ctl_srstn_shift | phy << phy_psrstn_shift | - phy << phy_srstn_shift); -} - -static void ddr_phy_ctl_reset(struct rk3288_cru *cru, u32 ch, u32 n) -{ - u32 phy_ctl_srstn_shift = 4 + 5 * ch; - - rk_clrsetreg(&cru->cru_softrst_con[10], - 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift); -} - -static void phy_pctrl_reset(struct rk3288_cru *cru, - struct rk3288_ddr_publ *publ, - int channel) -{ - int i; - - ddr_reset(cru, channel, 1, 1); - udelay(1); - clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); - for (i = 0; i < 4; i++) - clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); - - udelay(10); - setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); - for (i = 0; i < 4; i++) - setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); - - udelay(10); - ddr_reset(cru, channel, 1, 0); - udelay(10); - ddr_reset(cru, channel, 0, 0); - udelay(10); -} - -static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ, - u32 freq) -{ - int i; - - if (freq <= 250000000) { - if (freq <= 150000000) - clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); - else - setbits_le32(&publ->dllgcr, SBIAS_BYPASS); - setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); - for (i = 0; i < 4; i++) - setbits_le32(&publ->datx8[i].dxdllcr, - DXDLLCR_DLLDIS); - - setbits_le32(&publ->pir, PIR_DLLBYP); - } else { - clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); - clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); - for (i = 0; i < 4; i++) { - clrbits_le32(&publ->datx8[i].dxdllcr, - DXDLLCR_DLLDIS); - } - - clrbits_le32(&publ->pir, PIR_DLLBYP); - } -} - -static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) -{ - writel(DFI_INIT_START, &pctl->dfistcfg0); - writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, - &pctl->dfistcfg1); - writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); - writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, - &pctl->dfilpcfg0); - - writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); - writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); - writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); - writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); - writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); - writel(1, &pctl->dfitphyupdtype0); - - /* cs0 and cs1 write odt enable */ - writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), - &pctl->dfiodtcfg); - /* odt write length */ - writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); - /* phyupd and ctrlupd disabled */ - writel(0, &pctl->dfiupdcfg); -} - -static void ddr_set_enable(struct rk3288_grf *grf, uint channel, bool enable) -{ - uint val = 0; - - if (enable) { - val = 1 << (channel ? DDR1_16BIT_EN_SHIFT : - DDR0_16BIT_EN_SHIFT); - } - rk_clrsetreg(&grf->soc_con0, - 1 << (channel ? DDR1_16BIT_EN_SHIFT : DDR0_16BIT_EN_SHIFT), - val); -} - -static void ddr_set_ddr3_mode(struct rk3288_grf *grf, uint channel, - bool ddr3_mode) -{ - uint mask, val; - - mask = 1 << (channel ? MSCH1_MAINDDR3_SHIFT : MSCH0_MAINDDR3_SHIFT); - val = ddr3_mode << (channel ? MSCH1_MAINDDR3_SHIFT : - MSCH0_MAINDDR3_SHIFT); - rk_clrsetreg(&grf->soc_con0, mask, val); -} - -static void ddr_set_en_bst_odt(struct rk3288_grf *grf, uint channel, - bool enable, bool enable_bst, bool enable_odt) -{ - uint mask; - bool disable_bst = !enable_bst; - - mask = channel ? - (1 << LPDDR3_EN1_SHIFT | 1 << UPCTL1_BST_DIABLE_SHIFT | - 1 << UPCTL1_LPDDR3_ODT_EN_SHIFT) : - (1 << LPDDR3_EN0_SHIFT | 1 << UPCTL0_BST_DIABLE_SHIFT | - 1 << UPCTL0_LPDDR3_ODT_EN_SHIFT); - rk_clrsetreg(&grf->soc_con2, mask, - enable << (channel ? LPDDR3_EN1_SHIFT : LPDDR3_EN0_SHIFT) | - disable_bst << (channel ? UPCTL1_BST_DIABLE_SHIFT : - UPCTL0_BST_DIABLE_SHIFT) | - enable_odt << (channel ? UPCTL1_LPDDR3_ODT_EN_SHIFT : - UPCTL0_LPDDR3_ODT_EN_SHIFT)); -} - -static void pctl_cfg(int channel, struct rk3288_ddr_pctl *pctl, - struct rk3288_sdram_params *sdram_params, - struct rk3288_grf *grf) -{ - unsigned int burstlen; - - burstlen = (sdram_params->base.noc_timing >> 18) & 0x7; - copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, - sizeof(sdram_params->pctl_timing)); - switch (sdram_params->base.dramtype) { - case LPDDR3: - writel(sdram_params->pctl_timing.tcl - 1, - &pctl->dfitrddataen); - writel(sdram_params->pctl_timing.tcwl, - &pctl->dfitphywrlat); - burstlen >>= 1; - writel(LPDDR2_S4 | 0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | - LPDDR2_EN | burstlen << BURSTLENGTH_SHIFT | - (6 - 4) << TFAW_SHIFT | PD_EXIT_FAST | - 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, - &pctl->mcfg); - ddr_set_ddr3_mode(grf, channel, false); - ddr_set_enable(grf, channel, true); - ddr_set_en_bst_odt(grf, channel, true, false, - sdram_params->base.odt); - break; - case DDR3: - if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { - writel(sdram_params->pctl_timing.tcl - 3, - &pctl->dfitrddataen); - } else { - writel(sdram_params->pctl_timing.tcl - 2, - &pctl->dfitrddataen); - } - writel(sdram_params->pctl_timing.tcwl - 1, - &pctl->dfitphywrlat); - writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN | - DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | - 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, - &pctl->mcfg); - ddr_set_ddr3_mode(grf, channel, true); - ddr_set_enable(grf, channel, true); - - ddr_set_en_bst_odt(grf, channel, false, true, false); - break; - } - - setbits_le32(&pctl->scfg, 1); -} - -static void phy_cfg(const struct chan_info *chan, int channel, - struct rk3288_sdram_params *sdram_params) -{ - struct rk3288_ddr_publ *publ = chan->publ; - struct rk3288_msch *msch = chan->msch; - uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; - u32 dinit2, tmp; - int i; - - dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000); - /* DDR PHY Timing */ - copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, - sizeof(sdram_params->phy_timing)); - writel(sdram_params->base.noc_timing, &msch->ddrtiming); - writel(0x3f, &msch->readlatency); - writel(sdram_params->base.noc_activate, &msch->activate); - writel(2 << BUSWRTORD_SHIFT | 2 << BUSRDTOWR_SHIFT | - 1 << BUSRDTORD_SHIFT, &msch->devtodev); - writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT | - DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT | - 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); - writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT | - DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT, - &publ->ptr[1]); - writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT | - DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT, - &publ->ptr[2]); - - switch (sdram_params->base.dramtype) { - case LPDDR3: - clrsetbits_le32(&publ->pgcr, 0x1F, - 0 << PGCR_DFTLMT_SHIFT | - 0 << PGCR_DFTCMP_SHIFT | - 1 << PGCR_DQSCFG_SHIFT | - 0 << PGCR_ITMDMD_SHIFT); - /* DDRMODE select LPDDR3 */ - clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, - DDRMD_LPDDR2_LPDDR3 << DDRMD_SHIFT); - clrsetbits_le32(&publ->dxccr, - DQSNRES_MASK << DQSNRES_SHIFT | - DQSRES_MASK << DQSRES_SHIFT, - 4 << DQSRES_SHIFT | 0xc << DQSNRES_SHIFT); - tmp = readl(&publ->dtpr[1]); - tmp = ((tmp >> TDQSCKMAX_SHIFT) & TDQSCKMAX_MASK) - - ((tmp >> TDQSCK_SHIFT) & TDQSCK_MASK); - clrsetbits_le32(&publ->dsgcr, - DQSGE_MASK << DQSGE_SHIFT | - DQSGX_MASK << DQSGX_SHIFT, - tmp << DQSGE_SHIFT | tmp << DQSGX_SHIFT); - break; - case DDR3: - clrbits_le32(&publ->pgcr, 0x1f); - clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, - DDRMD_DDR3 << DDRMD_SHIFT); - break; - } - if (sdram_params->base.odt) { - /*dynamic RTT enable */ - for (i = 0; i < 4; i++) - setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); - } else { - /*dynamic RTT disable */ - for (i = 0; i < 4; i++) - clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); - } -} - -static void phy_init(struct rk3288_ddr_publ *publ) -{ - setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST - | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); - udelay(1); - while ((readl(&publ->pgsr) & - (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) != - (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) - ; -} - -static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, - u32 cmd, u32 arg) -{ - writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); - udelay(1); - while (readl(&pctl->mcmd) & START_CMD) - ; -} - -static inline void send_command_op(struct rk3288_ddr_pctl *pctl, - u32 rank, u32 cmd, u32 ma, u32 op) -{ - send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | - (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT); -} - -static void memory_init(struct rk3288_ddr_publ *publ, - u32 dramtype) -{ - setbits_le32(&publ->pir, - (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP - | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC - | (dramtype == DDR3 ? PIR_DRAMRST : 0))); - udelay(1); - while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) - != (PGSR_IDONE | PGSR_DLDONE)) - ; -} - -static void move_to_config_state(struct rk3288_ddr_publ *publ, - struct rk3288_ddr_pctl *pctl) -{ - unsigned int state; - - while (1) { - state = readl(&pctl->stat) & PCTL_STAT_MSK; - - switch (state) { - case LOW_POWER: - writel(WAKEUP_STATE, &pctl->sctl); - while ((readl(&pctl->stat) & PCTL_STAT_MSK) - != ACCESS) - ; - /* wait DLL lock */ - while ((readl(&publ->pgsr) & PGSR_DLDONE) - != PGSR_DLDONE) - ; - /* - * if at low power state,need wakeup first, - * and then enter the config - * so here no break. - */ - case ACCESS: - /* no break */ - case INIT_MEM: - writel(CFG_STATE, &pctl->sctl); - while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) - ; - break; - case CONFIG: - return; - default: - break; - } - } -} - -static void set_bandwidth_ratio(const struct chan_info *chan, int channel, - u32 n, struct rk3288_grf *grf) -{ - struct rk3288_ddr_pctl *pctl = chan->pctl; - struct rk3288_ddr_publ *publ = chan->publ; - struct rk3288_msch *msch = chan->msch; - - if (n == 1) { - setbits_le32(&pctl->ppcfg, 1); - rk_setreg(&grf->soc_con0, 1 << (8 + channel)); - setbits_le32(&msch->ddrtiming, 1 << 31); - /* Data Byte disable*/ - clrbits_le32(&publ->datx8[2].dxgcr, 1); - clrbits_le32(&publ->datx8[3].dxgcr, 1); - /* disable DLL */ - setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); - setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); - } else { - clrbits_le32(&pctl->ppcfg, 1); - rk_clrreg(&grf->soc_con0, 1 << (8 + channel)); - clrbits_le32(&msch->ddrtiming, 1 << 31); - /* Data Byte enable*/ - setbits_le32(&publ->datx8[2].dxgcr, 1); - setbits_le32(&publ->datx8[3].dxgcr, 1); - - /* enable DLL */ - clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); - clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); - /* reset DLL */ - clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); - clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); - udelay(10); - setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); - setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); - } - setbits_le32(&pctl->dfistcfg0, 1 << 2); -} - -static int data_training(const struct chan_info *chan, int channel, - struct rk3288_sdram_params *sdram_params) -{ - unsigned int j; - int ret = 0; - u32 rank; - int i; - u32 step[2] = { PIR_QSTRN, PIR_RVTRN }; - struct rk3288_ddr_publ *publ = chan->publ; - struct rk3288_ddr_pctl *pctl = chan->pctl; - - /* disable auto refresh */ - writel(0, &pctl->trefi); - - if (sdram_params->base.dramtype != LPDDR3) - setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); - rank = sdram_params->ch[channel].rank | 1; - for (j = 0; j < ARRAY_SIZE(step); j++) { - /* - * trigger QSTRN and RVTRN - * clear DTDONE status - */ - setbits_le32(&publ->pir, PIR_CLRSR); - - /* trigger DTT */ - setbits_le32(&publ->pir, - PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | - PIR_CLRSR); - udelay(1); - /* wait echo byte DTDONE */ - while ((readl(&publ->datx8[0].dxgsr[0]) & rank) - != rank) - ; - while ((readl(&publ->datx8[1].dxgsr[0]) & rank) - != rank) - ; - if (!(readl(&pctl->ppcfg) & 1)) { - while ((readl(&publ->datx8[2].dxgsr[0]) - & rank) != rank) - ; - while ((readl(&publ->datx8[3].dxgsr[0]) - & rank) != rank) - ; - } - if (readl(&publ->pgsr) & - (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) { - ret = -1; - break; - } - } - /* send some auto refresh to complement the lost while DTT */ - for (i = 0; i < (rank > 1 ? 8 : 4); i++) - send_command(pctl, rank, REF_CMD, 0); - - if (sdram_params->base.dramtype != LPDDR3) - clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); - - /* resume auto refresh */ - writel(sdram_params->pctl_timing.trefi, &pctl->trefi); - - return ret; -} - -static void move_to_access_state(const struct chan_info *chan) -{ - struct rk3288_ddr_publ *publ = chan->publ; - struct rk3288_ddr_pctl *pctl = chan->pctl; - unsigned int state; - - while (1) { - state = readl(&pctl->stat) & PCTL_STAT_MSK; - - switch (state) { - case LOW_POWER: - if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & - LP_TRIG_MASK) == 1) - return; - - writel(WAKEUP_STATE, &pctl->sctl); - while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) - ; - /* wait DLL lock */ - while ((readl(&publ->pgsr) & PGSR_DLDONE) - != PGSR_DLDONE) - ; - break; - case INIT_MEM: - writel(CFG_STATE, &pctl->sctl); - while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) - ; - case CONFIG: - writel(GO_STATE, &pctl->sctl); - while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) - ; - break; - case ACCESS: - return; - default: - break; - } - } -} - -static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum, - struct rk3288_sdram_params *sdram_params) -{ - struct rk3288_ddr_publ *publ = chan->publ; - - if (sdram_params->ch[chnum].bk == 3) - clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, - 1 << PDQ_SHIFT); - else - clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); - - writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); -} - -static void dram_all_config(const struct dram_info *dram, - struct rk3288_sdram_params *sdram_params) -{ - unsigned int chan; - u32 sys_reg = 0; - - sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; - sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; - for (chan = 0; chan < sdram_params->num_channels; chan++) { - const struct rk3288_sdram_channel *info = - &sdram_params->ch[chan]; - - sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); - sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); - sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); - sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); - sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); - sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); - sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); - sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); - sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); - - dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); - } - writel(sys_reg, &dram->pmu->sys_reg[2]); - rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride); -} - -static int sdram_rank_bw_detect(struct dram_info *dram, int channel, - struct rk3288_sdram_params *sdram_params) -{ - int reg; - int need_trainig = 0; - const struct chan_info *chan = &dram->chan[channel]; - struct rk3288_ddr_publ *publ = chan->publ; - - if (data_training(chan, channel, sdram_params) < 0) { - reg = readl(&publ->datx8[0].dxgsr[0]); - /* Check the result for rank 0 */ - if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { - debug("data training fail!\n"); - return -EIO; - } else if ((channel == 1) && - (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { - sdram_params->num_channels = 1; - } - - /* Check the result for rank 1 */ - if (reg & DQS_GATE_TRAINING_ERROR_RANK1) { - sdram_params->ch[channel].rank = 1; - clrsetbits_le32(&publ->pgcr, 0xF << 18, - sdram_params->ch[channel].rank << 18); - need_trainig = 1; - } - reg = readl(&publ->datx8[2].dxgsr[0]); - if (reg & (1 << 4)) { - sdram_params->ch[channel].bw = 1; - set_bandwidth_ratio(chan, channel, - sdram_params->ch[channel].bw, - dram->grf); - need_trainig = 1; - } - } - /* Assume the Die bit width are the same with the chip bit width */ - sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; - - if (need_trainig && - (data_training(chan, channel, sdram_params) < 0)) { - if (sdram_params->base.dramtype == LPDDR3) { - ddr_phy_ctl_reset(dram->cru, channel, 1); - udelay(10); - ddr_phy_ctl_reset(dram->cru, channel, 0); - udelay(10); - } - debug("2nd data training failed!"); - return -EIO; - } - - return 0; -} - -static int sdram_col_row_detect(struct dram_info *dram, int channel, - struct rk3288_sdram_params *sdram_params) -{ - int row, col; - unsigned int addr; - const struct chan_info *chan = &dram->chan[channel]; - struct rk3288_ddr_pctl *pctl = chan->pctl; - struct rk3288_ddr_publ *publ = chan->publ; - int ret = 0; - - /* Detect col */ - for (col = 11; col >= 9; col--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + - (1 << (col + sdram_params->ch[channel].bw - 1)); - writel(TEST_PATTEN, addr); - if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) - break; - } - if (col == 8) { - printf("Col detect error\n"); - ret = -EINVAL; - goto out; - } else { - sdram_params->ch[channel].col = col; - } - - move_to_config_state(publ, pctl); - writel(4, &chan->msch->ddrconf); - move_to_access_state(chan); - /* Detect row*/ - for (row = 16; row >= 12; row--) { - writel(0, CONFIG_SYS_SDRAM_BASE); - addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); - writel(TEST_PATTEN, addr); - if ((readl(addr) == TEST_PATTEN) && - (readl(CONFIG_SYS_SDRAM_BASE) == 0)) - break; - } - if (row == 11) { - printf("Row detect error\n"); - ret = -EINVAL; - } else { - sdram_params->ch[channel].cs1_row = row; - sdram_params->ch[channel].row_3_4 = 0; - debug("chn %d col %d, row %d\n", channel, col, row); - sdram_params->ch[channel].cs0_row = row; - } - -out: - return ret; -} - -static int sdram_get_niu_config(struct rk3288_sdram_params *sdram_params) -{ - int i, tmp, size, ret = 0; - - tmp = sdram_params->ch[0].col - 9; - tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; - tmp |= ((sdram_params->ch[0].cs0_row - 12) << 4); - size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]); - for (i = 0; i < size; i++) - if (tmp == ddrconf_table[i]) - break; - if (i >= size) { - printf("niu config not found\n"); - ret = -EINVAL; - } else { - sdram_params->base.ddrconfig = i; - } - - return ret; -} - -static int sdram_get_stride(struct rk3288_sdram_params *sdram_params) -{ - int stride = -1; - int ret = 0; - long cap = sdram_params->num_channels * (1u << - (sdram_params->ch[0].cs0_row + - sdram_params->ch[0].col + - (sdram_params->ch[0].rank - 1) + - sdram_params->ch[0].bw + - 3 - 20)); - - switch (cap) { - case 512: - stride = 0; - break; - case 1024: - stride = 5; - break; - case 2048: - stride = 9; - break; - case 4096: - stride = 0xd; - break; - default: - stride = -1; - printf("could not find correct stride, cap error!\n"); - ret = -EINVAL; - break; - } - sdram_params->base.stride = stride; - - return ret; -} - -static int sdram_init(struct dram_info *dram, - struct rk3288_sdram_params *sdram_params) -{ - int channel; - int zqcr; - int ret; - - debug("%s start\n", __func__); - if ((sdram_params->base.dramtype == DDR3 && - sdram_params->base.ddr_freq > 800000000) || - (sdram_params->base.dramtype == LPDDR3 && - sdram_params->base.ddr_freq > 533000000)) { - debug("SDRAM frequency is too high!"); - return -E2BIG; - } - - debug("ddr clk dpll\n"); - ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); - debug("ret=%d\n", ret); - if (ret) { - debug("Could not set DDR clock\n"); - return ret; - } - - for (channel = 0; channel < 2; channel++) { - const struct chan_info *chan = &dram->chan[channel]; - struct rk3288_ddr_pctl *pctl = chan->pctl; - struct rk3288_ddr_publ *publ = chan->publ; - - /* map all the 4GB space to the current channel */ - if (channel) - rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x17); - else - rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, 0x1a); - phy_pctrl_reset(dram->cru, publ, channel); - phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); - - dfi_cfg(pctl, sdram_params->base.dramtype); - - pctl_cfg(channel, pctl, sdram_params, dram->grf); - - phy_cfg(chan, channel, sdram_params); - - phy_init(publ); - - writel(POWER_UP_START, &pctl->powctl); - while (!(readl(&pctl->powstat) & POWER_UP_DONE)) - ; - - memory_init(publ, sdram_params->base.dramtype); - move_to_config_state(publ, pctl); - - if (sdram_params->base.dramtype == LPDDR3) { - send_command(pctl, 3, DESELECT_CMD, 0); - udelay(1); - send_command(pctl, 3, PREA_CMD, 0); - udelay(1); - send_command_op(pctl, 3, MRS_CMD, 63, 0xfc); - udelay(1); - send_command_op(pctl, 3, MRS_CMD, 1, - sdram_params->phy_timing.mr[1]); - udelay(1); - send_command_op(pctl, 3, MRS_CMD, 2, - sdram_params->phy_timing.mr[2]); - udelay(1); - send_command_op(pctl, 3, MRS_CMD, 3, - sdram_params->phy_timing.mr[3]); - udelay(1); - } - - /* Using 32bit bus width for detect */ - sdram_params->ch[channel].bw = 2; - set_bandwidth_ratio(chan, channel, - sdram_params->ch[channel].bw, dram->grf); - /* - * set cs, using n=3 for detect - * CS0, n=1 - * CS1, n=2 - * CS0 & CS1, n = 3 - */ - sdram_params->ch[channel].rank = 2, - clrsetbits_le32(&publ->pgcr, 0xF << 18, - (sdram_params->ch[channel].rank | 1) << 18); - - /* DS=40ohm,ODT=155ohm */ - zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT | - 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT | - 0x19 << PD_OUTPUT_SHIFT; - writel(zqcr, &publ->zq1cr[0]); - writel(zqcr, &publ->zq0cr[0]); - - if (sdram_params->base.dramtype == LPDDR3) { - /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ - udelay(10); - send_command_op(pctl, - sdram_params->ch[channel].rank | 1, - MRS_CMD, 11, - sdram_params->base.odt ? 3 : 0); - if (channel == 0) { - writel(0, &pctl->mrrcfg0); - send_command_op(pctl, 1, MRR_CMD, 8, 0); - /* S8 */ - if ((readl(&pctl->mrrstat0) & 0x3) != 3) { - debug("failed!"); - return -EREMOTEIO; - } - } - } - - /* Detect the rank and bit-width with data-training */ - sdram_rank_bw_detect(dram, channel, sdram_params); - - if (sdram_params->base.dramtype == LPDDR3) { - u32 i; - writel(0, &pctl->mrrcfg0); - for (i = 0; i < 17; i++) - send_command_op(pctl, 1, MRR_CMD, i, 0); - } - writel(15, &chan->msch->ddrconf); - move_to_access_state(chan); - /* DDR3 and LPDDR3 are always 8 bank, no need detect */ - sdram_params->ch[channel].bk = 3; - /* Detect Col and Row number*/ - ret = sdram_col_row_detect(dram, channel, sdram_params); - if (ret) - goto error; - } - /* Find NIU DDR configuration */ - ret = sdram_get_niu_config(sdram_params); - if (ret) - goto error; - /* Find stride setting */ - ret = sdram_get_stride(sdram_params); - if (ret) - goto error; - - dram_all_config(dram, sdram_params); - debug("%s done\n", __func__); - - return 0; -error: - printf("DRAM init failed!\n"); - hang(); -} - -# ifdef CONFIG_ROCKCHIP_FAST_SPL -static int veyron_init(struct dram_info *priv) -{ - struct udevice *pmic; - int ret; - - ret = uclass_first_device_err(UCLASS_PMIC, &pmic); - if (ret) - return ret; - - /* Slowly raise to max CPU voltage to prevent overshoot */ - ret = rk8xx_spl_configure_buck(pmic, 1, 1200000); - if (ret) - return ret; - udelay(175);/* Must wait for voltage to stabilize, 2mV/us */ - ret = rk8xx_spl_configure_buck(pmic, 1, 1400000); - if (ret) - return ret; - udelay(100);/* Must wait for voltage to stabilize, 2mV/us */ - - rk3288_clk_configure_cpu(priv->cru, priv->grf); - - return 0; -} -# endif - -static int setup_sdram(struct udevice *dev) -{ - struct dram_info *priv = dev_get_priv(dev); - struct rk3288_sdram_params *params = dev_get_platdata(dev); - -# ifdef CONFIG_ROCKCHIP_FAST_SPL - if (priv->is_veyron) { - int ret; - - ret = veyron_init(priv); - if (ret) - return ret; - } -# endif - - return sdram_init(priv, params); -} - -static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev) -{ -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rk3288_sdram_params *params = dev_get_platdata(dev); - int ret; - - /* Rk3288 supports dual-channel, set default channel num to 2 */ - params->num_channels = 2; - ret = dev_read_u32_array(dev, "rockchip,pctl-timing", - (u32 *)¶ms->pctl_timing, - sizeof(params->pctl_timing) / sizeof(u32)); - if (ret) { - debug("%s: Cannot read rockchip,pctl-timing\n", __func__); - return -EINVAL; - } - ret = dev_read_u32_array(dev, "rockchip,phy-timing", - (u32 *)¶ms->phy_timing, - sizeof(params->phy_timing) / sizeof(u32)); - if (ret) { - debug("%s: Cannot read rockchip,phy-timing\n", __func__); - return -EINVAL; - } - ret = dev_read_u32_array(dev, "rockchip,sdram-params", - (u32 *)¶ms->base, - sizeof(params->base) / sizeof(u32)); - if (ret) { - debug("%s: Cannot read rockchip,sdram-params\n", __func__); - return -EINVAL; - } -#ifdef CONFIG_ROCKCHIP_FAST_SPL - struct dram_info *priv = dev_get_priv(dev); - - priv->is_veyron = !fdt_node_check_compatible(blob, 0, "google,veyron"); -#endif - ret = regmap_init_mem(dev, ¶ms->map); - if (ret) - return ret; -#endif - - return 0; -} -#endif /* CONFIG_SPL_BUILD */ - -#if CONFIG_IS_ENABLED(OF_PLATDATA) -static int conv_of_platdata(struct udevice *dev) -{ - struct rk3288_sdram_params *plat = dev_get_platdata(dev); - struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat; - int ret; - - memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, - sizeof(plat->pctl_timing)); - memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, - sizeof(plat->phy_timing)); - memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); - /* Rk3288 supports dual-channel, set default channel num to 2 */ - plat->num_channels = 2; - ret = regmap_init_mem_platdata(dev, of_plat->reg, - ARRAY_SIZE(of_plat->reg) / 2, - &plat->map); - if (ret) - return ret; - - return 0; -} -#endif - -static int rk3288_dmc_probe(struct udevice *dev) -{ -#ifdef CONFIG_SPL_BUILD - struct rk3288_sdram_params *plat = dev_get_platdata(dev); - struct udevice *dev_clk; - struct regmap *map; - int ret; -#endif - struct dram_info *priv = dev_get_priv(dev); - - priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); -#ifdef CONFIG_SPL_BUILD -#if CONFIG_IS_ENABLED(OF_PLATDATA) - ret = conv_of_platdata(dev); - if (ret) - return ret; -#endif - map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC); - if (IS_ERR(map)) - return PTR_ERR(map); - priv->chan[0].msch = regmap_get_range(map, 0); - priv->chan[1].msch = (struct rk3288_msch *) - (regmap_get_range(map, 0) + 0x80); - - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); - - priv->chan[0].pctl = regmap_get_range(plat->map, 0); - priv->chan[0].publ = regmap_get_range(plat->map, 1); - priv->chan[1].pctl = regmap_get_range(plat->map, 2); - priv->chan[1].publ = regmap_get_range(plat->map, 3); - - ret = rockchip_get_clk(&dev_clk); - if (ret) - return ret; - priv->ddr_clk.id = CLK_DDR; - ret = clk_request(dev_clk, &priv->ddr_clk); - if (ret) - return ret; - - priv->cru = rockchip_get_cru(); - if (IS_ERR(priv->cru)) - return PTR_ERR(priv->cru); - ret = setup_sdram(dev); - if (ret) - return ret; -#else - priv->info.base = CONFIG_SYS_SDRAM_BASE; - priv->info.size = rockchip_sdram_size( - (phys_addr_t)&priv->pmu->sys_reg[2]); -#endif - - return 0; -} - -static int rk3288_dmc_get_info(struct udevice *dev, struct ram_info *info) -{ - struct dram_info *priv = dev_get_priv(dev); - - *info = priv->info; - - return 0; -} - -static struct ram_ops rk3288_dmc_ops = { - .get_info = rk3288_dmc_get_info, -}; - -static const struct udevice_id rk3288_dmc_ids[] = { - { .compatible = "rockchip,rk3288-dmc" }, - { } -}; - -U_BOOT_DRIVER(dmc_rk3288) = { - .name = "rockchip_rk3288_dmc", - .id = UCLASS_RAM, - .of_match = rk3288_dmc_ids, - .ops = &rk3288_dmc_ops, -#ifdef CONFIG_SPL_BUILD - .ofdata_to_platdata = rk3288_dmc_ofdata_to_platdata, -#endif - .probe = rk3288_dmc_probe, - .priv_auto_alloc_size = sizeof(struct dram_info), -#ifdef CONFIG_SPL_BUILD - .platdata_auto_alloc_size = sizeof(struct rk3288_sdram_params), -#endif -}; diff --git a/arch/arm/mach-rockchip/rk3328/Makefile b/arch/arm/mach-rockchip/rk3328/Makefile index 72873e2..bbab036 100644 --- a/arch/arm/mach-rockchip/rk3328/Makefile +++ b/arch/arm/mach-rockchip/rk3328/Makefile @@ -6,5 +6,4 @@ obj-y += clk_rk3328.o obj-y += rk3328.o -obj-y += sdram_rk3328.o obj-y += syscon_rk3328.o diff --git a/arch/arm/mach-rockchip/rk3328/sdram_rk3328.c b/arch/arm/mach-rockchip/rk3328/sdram_rk3328.c deleted file mode 100644 index 9637a35..0000000 --- a/arch/arm/mach-rockchip/rk3328/sdram_rk3328.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3328.h> -#include <asm/arch/sdram_common.h> - -DECLARE_GLOBAL_DATA_PTR; -struct dram_info { - struct ram_info info; - struct rk3328_grf_regs *grf; -}; - -static int rk3328_dmc_probe(struct udevice *dev) -{ - struct dram_info *priv = dev_get_priv(dev); - - priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); - debug("%s: grf=%p\n", __func__, priv->grf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; - priv->info.size = rockchip_sdram_size( - (phys_addr_t)&priv->grf->os_reg[2]); - - return 0; -} - -static int rk3328_dmc_get_info(struct udevice *dev, struct ram_info *info) -{ - struct dram_info *priv = dev_get_priv(dev); - - *info = priv->info; - - return 0; -} - -static struct ram_ops rk3328_dmc_ops = { - .get_info = rk3328_dmc_get_info, -}; - - -static const struct udevice_id rk3328_dmc_ids[] = { - { .compatible = "rockchip,rk3328-dmc" }, - { } -}; - -U_BOOT_DRIVER(dmc_rk3328) = { - .name = "rockchip_rk3328_dmc", - .id = UCLASS_RAM, - .of_match = rk3328_dmc_ids, - .ops = &rk3328_dmc_ops, - .probe = rk3328_dmc_probe, - .priv_auto_alloc_size = sizeof(struct dram_info), -}; diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c index cabf344..72d2c97 100644 --- a/arch/arm/mach-rockchip/rk3368-board-spl.c +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c @@ -38,13 +38,13 @@ void board_init_f(ulong dummy) /* Set up our preloader console */ ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); if (ret) { - error("%s: pinctrl init failed: %d\n", __func__, ret); + pr_err("%s: pinctrl init failed: %d\n", __func__, ret); hang(); } ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0); if (ret) { - error("%s: failed to set up console UART\n", __func__); + pr_err("%s: failed to set up console UART\n", __func__); hang(); } diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 3406156..9c20f56 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -1,10 +1,12 @@ /* * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <asm/arch/bootrom.h> #include <asm/arch/clock.h> #include <asm/arch/grf_rk3399.h> #include <asm/arch/hardware.h> @@ -19,9 +21,43 @@ DECLARE_GLOBAL_DATA_PTR; +void board_return_to_bootrom(void) +{ + back_to_bootrom(); +} + +static const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/sdhci@fe330000", + [BROM_BOOTSOURCE_SPINOR] = "/spi@ff1d0000", + [BROM_BOOTSOURCE_SD] = "/dwmmc@fe320000", +}; + +const char *board_spl_was_booted_from(void) +{ + u32 bootdevice_brom_id = readl(RK3399_BROM_BOOTSOURCE_ID_ADDR); + const char *bootdevice_ofpath = NULL; + + if (bootdevice_brom_id < ARRAY_SIZE(boot_devices)) + bootdevice_ofpath = boot_devices[bootdevice_brom_id]; + + if (bootdevice_ofpath) + debug("%s: brom_bootdevice_id %x maps to '%s'\n", + __func__, bootdevice_brom_id, bootdevice_ofpath); + else + debug("%s: failed to resolve brom_bootdevice_id %x\n", + __func__, bootdevice_brom_id); + + return bootdevice_ofpath; +} + u32 spl_boot_device(void) { - return BOOT_DEVICE_MMC1; + u32 boot_device = BOOT_DEVICE_MMC1; + + if (CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)) + return BOOT_DEVICE_BOOTROM; + + return boot_device; } u32 spl_boot_mode(const u32 boot_device) @@ -137,37 +173,6 @@ void board_init_f(ulong dummy) } } -void spl_board_init(void) -{ - struct udevice *pinctrl; - int ret; - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - goto err; - } - - preloader_console_init(); -#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) - back_to_bootrom(); -#endif - - return; -err: - printf("spl_board_init: Error %d\n", ret); - - /* No way to report error here */ - hang(); -} - #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/arch/arm/mach-rockchip/rk3399/Makefile b/arch/arm/mach-rockchip/rk3399/Makefile index 793ce31..98ebeac 100644 --- a/arch/arm/mach-rockchip/rk3399/Makefile +++ b/arch/arm/mach-rockchip/rk3399/Makefile @@ -6,5 +6,4 @@ obj-y += clk_rk3399.o obj-y += rk3399.o -obj-y += sdram_rk3399.o obj-y += syscon_rk3399.o diff --git a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c deleted file mode 100644 index 5ed4b03..0000000 --- a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c +++ /dev/null @@ -1,1238 +0,0 @@ -/* - * (C) Copyright 2016-2017 Rockchip Inc. - * - * SPDX-License-Identifier: GPL-2.0 - * - * Adapted from coreboot. - */ - -#include <common.h> -#include <clk.h> -#include <dm.h> -#include <dt-structs.h> -#include <ram.h> -#include <regmap.h> -#include <syscon.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/sdram_common.h> -#include <asm/arch/sdram_rk3399.h> -#include <asm/arch/cru_rk3399.h> -#include <asm/arch/grf_rk3399.h> -#include <asm/arch/hardware.h> -#include <linux/err.h> -#include <time.h> - -DECLARE_GLOBAL_DATA_PTR; -struct chan_info { - struct rk3399_ddr_pctl_regs *pctl; - struct rk3399_ddr_pi_regs *pi; - struct rk3399_ddr_publ_regs *publ; - struct rk3399_msch_regs *msch; -}; - -struct dram_info { -#ifdef CONFIG_SPL_BUILD - struct chan_info chan[2]; - struct clk ddr_clk; - struct rk3399_cru *cru; - struct rk3399_pmucru *pmucru; - struct rk3399_pmusgrf_regs *pmusgrf; - struct rk3399_ddr_cic_regs *cic; -#endif - struct ram_info info; - struct rk3399_pmugrf_regs *pmugrf; -}; - -#define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6)) -#define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7)) -#define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8)) - -#define PHY_DRV_ODT_Hi_Z 0x0 -#define PHY_DRV_ODT_240 0x1 -#define PHY_DRV_ODT_120 0x8 -#define PHY_DRV_ODT_80 0x9 -#define PHY_DRV_ODT_60 0xc -#define PHY_DRV_ODT_48 0xd -#define PHY_DRV_ODT_40 0xe -#define PHY_DRV_ODT_34_3 0xf - -#ifdef CONFIG_SPL_BUILD - -struct rockchip_dmc_plat { -#if CONFIG_IS_ENABLED(OF_PLATDATA) - struct dtd_rockchip_rk3399_dmc dtplat; -#else - struct rk3399_sdram_params sdram_params; -#endif - struct regmap *map; -}; - -static void copy_to_reg(u32 *dest, const u32 *src, u32 n) -{ - int i; - - for (i = 0; i < n / sizeof(u32); i++) { - writel(*src, dest); - src++; - dest++; - } -} - -static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs, - u32 freq) -{ - u32 *denali_phy = ddr_publ_regs->denali_phy; - - /* From IP spec, only freq small than 125 can enter dll bypass mode */ - if (freq <= 125) { - /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ - setbits_le32(&denali_phy[86], (0x3 << 2) << 8); - setbits_le32(&denali_phy[214], (0x3 << 2) << 8); - setbits_le32(&denali_phy[342], (0x3 << 2) << 8); - setbits_le32(&denali_phy[470], (0x3 << 2) << 8); - - /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ - setbits_le32(&denali_phy[547], (0x3 << 2) << 16); - setbits_le32(&denali_phy[675], (0x3 << 2) << 16); - setbits_le32(&denali_phy[803], (0x3 << 2) << 16); - } else { - /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ - clrbits_le32(&denali_phy[86], (0x3 << 2) << 8); - clrbits_le32(&denali_phy[214], (0x3 << 2) << 8); - clrbits_le32(&denali_phy[342], (0x3 << 2) << 8); - clrbits_le32(&denali_phy[470], (0x3 << 2) << 8); - - /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ - clrbits_le32(&denali_phy[547], (0x3 << 2) << 16); - clrbits_le32(&denali_phy[675], (0x3 << 2) << 16); - clrbits_le32(&denali_phy[803], (0x3 << 2) << 16); - } -} - -static void set_memory_map(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) -{ - const struct rk3399_sdram_channel *sdram_ch = - &sdram_params->ch[channel]; - u32 *denali_ctl = chan->pctl->denali_ctl; - u32 *denali_pi = chan->pi->denali_pi; - u32 cs_map; - u32 reduc; - u32 row; - - /* Get row number from ddrconfig setting */ - if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4) - row = 16; - else if (sdram_ch->ddrconfig == 3) - row = 14; - else - row = 15; - - cs_map = (sdram_ch->rank > 1) ? 3 : 1; - reduc = (sdram_ch->bw == 2) ? 0 : 1; - - /* Set the dram configuration to ctrl */ - clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); - clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), - ((3 - sdram_ch->bk) << 16) | - ((16 - row) << 24)); - - clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), - cs_map | (reduc << 16)); - - /* PI_199 PI_COL_DIFF:RW:0:4 */ - clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); - - /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ - clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), - ((3 - sdram_ch->bk) << 16) | - ((16 - row) << 24)); - /* PI_41 PI_CS_MAP:RW:24:4 */ - clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); - if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3)) - writel(0x2EC7FFFF, &denali_pi[34]); -} - -static void set_ds_odt(const struct chan_info *chan, - const struct rk3399_sdram_params *sdram_params) -{ - u32 *denali_phy = chan->publ->denali_phy; - - u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; - u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p; - u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; - u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n; - u32 reg_value; - - if (sdram_params->base.dramtype == LPDDR4) { - tsel_rd_select_p = PHY_DRV_ODT_Hi_Z; - tsel_wr_select_p = PHY_DRV_ODT_40; - ca_tsel_wr_select_p = PHY_DRV_ODT_40; - tsel_idle_select_p = PHY_DRV_ODT_Hi_Z; - - tsel_rd_select_n = PHY_DRV_ODT_240; - tsel_wr_select_n = PHY_DRV_ODT_40; - ca_tsel_wr_select_n = PHY_DRV_ODT_40; - tsel_idle_select_n = PHY_DRV_ODT_240; - } else if (sdram_params->base.dramtype == LPDDR3) { - tsel_rd_select_p = PHY_DRV_ODT_240; - tsel_wr_select_p = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_p = PHY_DRV_ODT_48; - tsel_idle_select_p = PHY_DRV_ODT_240; - - tsel_rd_select_n = PHY_DRV_ODT_Hi_Z; - tsel_wr_select_n = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_n = PHY_DRV_ODT_48; - tsel_idle_select_n = PHY_DRV_ODT_Hi_Z; - } else { - tsel_rd_select_p = PHY_DRV_ODT_240; - tsel_wr_select_p = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_p = PHY_DRV_ODT_34_3; - tsel_idle_select_p = PHY_DRV_ODT_240; - - tsel_rd_select_n = PHY_DRV_ODT_240; - tsel_wr_select_n = PHY_DRV_ODT_34_3; - ca_tsel_wr_select_n = PHY_DRV_ODT_34_3; - tsel_idle_select_n = PHY_DRV_ODT_240; - } - - if (sdram_params->base.odt == 1) - tsel_rd_en = 1; - else - tsel_rd_en = 0; - - tsel_wr_en = 0; - tsel_idle_en = 0; - - /* - * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0 - * sets termination values for read/idle cycles and drive strength - * for write cycles for DQ/DM - */ - reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | - (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) | - (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); - clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); - - /* - * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0 - * sets termination values for read/idle cycles and drive strength - * for write cycles for DQS - */ - clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value); - clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); - - /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ - reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4); - clrsetbits_le32(&denali_phy[544], 0xff, reg_value); - clrsetbits_le32(&denali_phy[672], 0xff, reg_value); - clrsetbits_le32(&denali_phy[800], 0xff, reg_value); - - /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ - clrsetbits_le32(&denali_phy[928], 0xff, reg_value); - - /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ - clrsetbits_le32(&denali_phy[937], 0xff, reg_value); - - /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ - clrsetbits_le32(&denali_phy[935], 0xff, reg_value); - - /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ - clrsetbits_le32(&denali_phy[939], 0xff, reg_value); - - /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ - clrsetbits_le32(&denali_phy[929], 0xff, reg_value); - - /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ - clrsetbits_le32(&denali_phy[924], 0xff, - tsel_wr_select_n | (tsel_wr_select_p << 4)); - clrsetbits_le32(&denali_phy[925], 0xff, - tsel_rd_select_n | (tsel_rd_select_p << 4)); - - /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */ - reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) - << 16; - clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value); - clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value); - clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value); - clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value); - - /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */ - reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) - << 24; - clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value); - clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value); - clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value); - clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value); - - /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */ - reg_value = tsel_wr_en << 8; - clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value); - clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value); - clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value); - - /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */ - reg_value = tsel_wr_en << 17; - clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value); - /* - * pad_rst/cke/cs/clk_term tsel 1bits - * DENALI_PHY_938/936/940/934 offset_17 - */ - clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value); - clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value); - clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value); - clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value); - - /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ - clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value); -} - -static int phy_io_config(const struct chan_info *chan, - const struct rk3399_sdram_params *sdram_params) -{ - u32 *denali_phy = chan->publ->denali_phy; - u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac; - u32 mode_sel; - u32 reg_value; - u32 drv_value, odt_value; - u32 speed; - - /* vref setting */ - if (sdram_params->base.dramtype == LPDDR4) { - /* LPDDR4 */ - vref_mode_dq = 0x6; - vref_value_dq = 0x1f; - vref_mode_ac = 0x6; - vref_value_ac = 0x1f; - } else if (sdram_params->base.dramtype == LPDDR3) { - if (sdram_params->base.odt == 1) { - vref_mode_dq = 0x5; /* LPDDR3 ODT */ - drv_value = (readl(&denali_phy[6]) >> 12) & 0xf; - odt_value = (readl(&denali_phy[6]) >> 4) & 0xf; - if (drv_value == PHY_DRV_ODT_48) { - switch (odt_value) { - case PHY_DRV_ODT_240: - vref_value_dq = 0x16; - break; - case PHY_DRV_ODT_120: - vref_value_dq = 0x26; - break; - case PHY_DRV_ODT_60: - vref_value_dq = 0x36; - break; - default: - debug("Invalid ODT value.\n"); - return -EINVAL; - } - } else if (drv_value == PHY_DRV_ODT_40) { - switch (odt_value) { - case PHY_DRV_ODT_240: - vref_value_dq = 0x19; - break; - case PHY_DRV_ODT_120: - vref_value_dq = 0x23; - break; - case PHY_DRV_ODT_60: - vref_value_dq = 0x31; - break; - default: - debug("Invalid ODT value.\n"); - return -EINVAL; - } - } else if (drv_value == PHY_DRV_ODT_34_3) { - switch (odt_value) { - case PHY_DRV_ODT_240: - vref_value_dq = 0x17; - break; - case PHY_DRV_ODT_120: - vref_value_dq = 0x20; - break; - case PHY_DRV_ODT_60: - vref_value_dq = 0x2e; - break; - default: - debug("Invalid ODT value.\n"); - return -EINVAL; - } - } else { - debug("Invalid DRV value.\n"); - return -EINVAL; - } - } else { - vref_mode_dq = 0x2; /* LPDDR3 */ - vref_value_dq = 0x1f; - } - vref_mode_ac = 0x2; - vref_value_ac = 0x1f; - } else if (sdram_params->base.dramtype == DDR3) { - /* DDR3L */ - vref_mode_dq = 0x1; - vref_value_dq = 0x1f; - vref_mode_ac = 0x1; - vref_value_ac = 0x1f; - } else { - debug("Unknown DRAM type.\n"); - return -EINVAL; - } - - reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq; - - /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */ - clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8); - /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */ - clrsetbits_le32(&denali_phy[914], 0xfff, reg_value); - /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */ - clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16); - /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */ - clrsetbits_le32(&denali_phy[915], 0xfff, reg_value); - - reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac; - - /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ - clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); - - if (sdram_params->base.dramtype == LPDDR4) - mode_sel = 0x6; - else if (sdram_params->base.dramtype == LPDDR3) - mode_sel = 0x0; - else if (sdram_params->base.dramtype == DDR3) - mode_sel = 0x1; - else - return -EINVAL; - - /* PHY_924 PHY_PAD_FDBK_DRIVE */ - clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15); - /* PHY_926 PHY_PAD_DATA_DRIVE */ - clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6); - /* PHY_927 PHY_PAD_DQS_DRIVE */ - clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6); - /* PHY_928 PHY_PAD_ADDR_DRIVE */ - clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14); - /* PHY_929 PHY_PAD_CLK_DRIVE */ - clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14); - /* PHY_935 PHY_PAD_CKE_DRIVE */ - clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14); - /* PHY_937 PHY_PAD_RST_DRIVE */ - clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14); - /* PHY_939 PHY_PAD_CS_DRIVE */ - clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); - - - /* speed setting */ - if (sdram_params->base.ddr_freq < 400) - speed = 0x0; - else if (sdram_params->base.ddr_freq < 800) - speed = 0x1; - else if (sdram_params->base.ddr_freq < 1200) - speed = 0x2; - else - speed = 0x3; - - /* PHY_924 PHY_PAD_FDBK_DRIVE */ - clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); - /* PHY_926 PHY_PAD_DATA_DRIVE */ - clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); - /* PHY_927 PHY_PAD_DQS_DRIVE */ - clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); - /* PHY_928 PHY_PAD_ADDR_DRIVE */ - clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); - /* PHY_929 PHY_PAD_CLK_DRIVE */ - clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); - /* PHY_935 PHY_PAD_CKE_DRIVE */ - clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); - /* PHY_937 PHY_PAD_RST_DRIVE */ - clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); - /* PHY_939 PHY_PAD_CS_DRIVE */ - clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); - - return 0; -} - -static int pctl_cfg(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) -{ - u32 *denali_ctl = chan->pctl->denali_ctl; - u32 *denali_pi = chan->pi->denali_pi; - u32 *denali_phy = chan->publ->denali_phy; - const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl; - const u32 *params_phy = sdram_params->phy_regs.denali_phy; - u32 tmp, tmp1, tmp2; - u32 pwrup_srefresh_exit; - int ret; - const ulong timeout_ms = 200; - - /* - * work around controller bug: - * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed - */ - copy_to_reg(&denali_ctl[1], ¶ms_ctl[1], - sizeof(struct rk3399_ddr_pctl_regs) - 4); - writel(params_ctl[0], &denali_ctl[0]); - copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0], - sizeof(struct rk3399_ddr_pi_regs)); - /* rank count need to set for init */ - set_memory_map(chan, channel, sdram_params); - - writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]); - writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]); - writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]); - - pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; - clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); - - /* PHY_DLL_RST_EN */ - clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24); - - setbits_le32(&denali_pi[0], START); - setbits_le32(&denali_ctl[0], START); - - /* Wating for phy DLL lock */ - while (1) { - tmp = readl(&denali_phy[920]); - tmp1 = readl(&denali_phy[921]); - tmp2 = readl(&denali_phy[922]); - if ((((tmp >> 16) & 0x1) == 0x1) && - (((tmp1 >> 16) & 0x1) == 0x1) && - (((tmp1 >> 0) & 0x1) == 0x1) && - (((tmp2 >> 0) & 0x1) == 0x1)) - break; - } - - copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4); - copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4); - copy_to_reg(&denali_phy[128], ¶ms_phy[128], (218 - 128 + 1) * 4); - copy_to_reg(&denali_phy[256], ¶ms_phy[256], (346 - 256 + 1) * 4); - copy_to_reg(&denali_phy[384], ¶ms_phy[384], (474 - 384 + 1) * 4); - copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4); - copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4); - copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4); - set_ds_odt(chan, sdram_params); - - /* - * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8 - * dqs_tsel_wr_end[7:4] add Half cycle - */ - tmp = (readl(&denali_phy[84]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8); - tmp = (readl(&denali_phy[212]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8); - tmp = (readl(&denali_phy[340]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8); - tmp = (readl(&denali_phy[468]) >> 8) & 0xff; - clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8); - - /* - * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8 - * dq_tsel_wr_end[7:4] add Half cycle - */ - tmp = (readl(&denali_phy[83]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16); - tmp = (readl(&denali_phy[211]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16); - tmp = (readl(&denali_phy[339]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16); - tmp = (readl(&denali_phy[467]) >> 16) & 0xff; - clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); - - ret = phy_io_config(chan, sdram_params); - if (ret) - return ret; - - /* PHY_DLL_RST_EN */ - clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); - - /* Wating for PHY and DRAM init complete */ - tmp = get_timer(0); - do { - if (get_timer(tmp) > timeout_ms) { - error("DRAM (%s): phy failed to lock within %ld ms\n", - __func__, timeout_ms); - return -ETIME; - } - } while (!(readl(&denali_ctl[203]) & (1 << 3))); - debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp)); - - clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, - pwrup_srefresh_exit); - return 0; -} - -static void select_per_cs_training_index(const struct chan_info *chan, - u32 rank) -{ - u32 *denali_phy = chan->publ->denali_phy; - - /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */ - if ((readl(&denali_phy[84])>>16) & 1) { - /* - * PHY_8/136/264/392 - * phy_per_cs_training_index_X 1bit offset_24 - */ - clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24); - clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24); - clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24); - clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24); - } -} - -static void override_write_leveling_value(const struct chan_info *chan) -{ - u32 *denali_ctl = chan->pctl->denali_ctl; - u32 *denali_phy = chan->publ->denali_phy; - u32 byte; - - /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ - setbits_le32(&denali_phy[896], 1); - - /* - * PHY_8/136/264/392 - * phy_per_cs_training_multicast_en_X 1bit offset_16 - */ - clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16); - clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16); - clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16); - clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16); - - for (byte = 0; byte < 4; byte++) - clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16, - 0x200 << 16); - - /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ - clrbits_le32(&denali_phy[896], 1); - - /* CTL_200 ctrlupd_req 1bit offset_8 */ - clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); -} - -static int data_training_ca(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) -{ - u32 *denali_pi = chan->pi->denali_pi; - u32 *denali_phy = chan->publ->denali_phy; - u32 i, tmp; - u32 obs_0, obs_1, obs_2, obs_err = 0; - u32 rank = sdram_params->ch[channel].rank; - - for (i = 0; i < rank; i++) { - select_per_cs_training_index(chan, i); - /* PI_100 PI_CALVL_EN:RW:8:2 */ - clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); - /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ - clrsetbits_le32(&denali_pi[92], - (0x1 << 16) | (0x3 << 24), - (0x1 << 16) | (i << 24)); - - /* Waiting for training complete */ - while (1) { - /* PI_174 PI_INT_STATUS:RD:8:18 */ - tmp = readl(&denali_pi[174]) >> 8; - /* - * check status obs - * PHY_532/660/789 phy_adr_calvl_obs1_:0:32 - */ - obs_0 = readl(&denali_phy[532]); - obs_1 = readl(&denali_phy[660]); - obs_2 = readl(&denali_phy[788]); - if (((obs_0 >> 30) & 0x3) || - ((obs_1 >> 30) & 0x3) || - ((obs_2 >> 30) & 0x3)) - obs_err = 1; - if ((((tmp >> 11) & 0x1) == 0x1) && - (((tmp >> 13) & 0x1) == 0x1) && - (((tmp >> 5) & 0x1) == 0x0) && - (obs_err == 0)) - break; - else if ((((tmp >> 5) & 0x1) == 0x1) || - (obs_err == 1)) - return -EIO; - } - /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ - writel(0x00003f7c, (&denali_pi[175])); - } - clrbits_le32(&denali_pi[100], 0x3 << 8); - - return 0; -} - -static int data_training_wl(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) -{ - u32 *denali_pi = chan->pi->denali_pi; - u32 *denali_phy = chan->publ->denali_phy; - u32 i, tmp; - u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; - u32 rank = sdram_params->ch[channel].rank; - - for (i = 0; i < rank; i++) { - select_per_cs_training_index(chan, i); - /* PI_60 PI_WRLVL_EN:RW:8:2 */ - clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); - /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ - clrsetbits_le32(&denali_pi[59], - (0x1 << 8) | (0x3 << 16), - (0x1 << 8) | (i << 16)); - - /* Waiting for training complete */ - while (1) { - /* PI_174 PI_INT_STATUS:RD:8:18 */ - tmp = readl(&denali_pi[174]) >> 8; - - /* - * check status obs, if error maybe can not - * get leveling done PHY_40/168/296/424 - * phy_wrlvl_status_obs_X:0:13 - */ - obs_0 = readl(&denali_phy[40]); - obs_1 = readl(&denali_phy[168]); - obs_2 = readl(&denali_phy[296]); - obs_3 = readl(&denali_phy[424]); - if (((obs_0 >> 12) & 0x1) || - ((obs_1 >> 12) & 0x1) || - ((obs_2 >> 12) & 0x1) || - ((obs_3 >> 12) & 0x1)) - obs_err = 1; - if ((((tmp >> 10) & 0x1) == 0x1) && - (((tmp >> 13) & 0x1) == 0x1) && - (((tmp >> 4) & 0x1) == 0x0) && - (obs_err == 0)) - break; - else if ((((tmp >> 4) & 0x1) == 0x1) || - (obs_err == 1)) - return -EIO; - } - /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ - writel(0x00003f7c, (&denali_pi[175])); - } - - override_write_leveling_value(chan); - clrbits_le32(&denali_pi[60], 0x3 << 8); - - return 0; -} - -static int data_training_rg(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) -{ - u32 *denali_pi = chan->pi->denali_pi; - u32 *denali_phy = chan->publ->denali_phy; - u32 i, tmp; - u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; - u32 rank = sdram_params->ch[channel].rank; - - for (i = 0; i < rank; i++) { - select_per_cs_training_index(chan, i); - /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ - clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24); - /* - * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 - * PI_RDLVL_CS:RW:24:2 - */ - clrsetbits_le32(&denali_pi[74], - (0x1 << 16) | (0x3 << 24), - (0x1 << 16) | (i << 24)); - - /* Waiting for training complete */ - while (1) { - /* PI_174 PI_INT_STATUS:RD:8:18 */ - tmp = readl(&denali_pi[174]) >> 8; - - /* - * check status obs - * PHY_43/171/299/427 - * PHY_GTLVL_STATUS_OBS_x:16:8 - */ - obs_0 = readl(&denali_phy[43]); - obs_1 = readl(&denali_phy[171]); - obs_2 = readl(&denali_phy[299]); - obs_3 = readl(&denali_phy[427]); - if (((obs_0 >> (16 + 6)) & 0x3) || - ((obs_1 >> (16 + 6)) & 0x3) || - ((obs_2 >> (16 + 6)) & 0x3) || - ((obs_3 >> (16 + 6)) & 0x3)) - obs_err = 1; - if ((((tmp >> 9) & 0x1) == 0x1) && - (((tmp >> 13) & 0x1) == 0x1) && - (((tmp >> 3) & 0x1) == 0x0) && - (obs_err == 0)) - break; - else if ((((tmp >> 3) & 0x1) == 0x1) || - (obs_err == 1)) - return -EIO; - } - /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ - writel(0x00003f7c, (&denali_pi[175])); - } - clrbits_le32(&denali_pi[80], 0x3 << 24); - - return 0; -} - -static int data_training_rl(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) -{ - u32 *denali_pi = chan->pi->denali_pi; - u32 i, tmp; - u32 rank = sdram_params->ch[channel].rank; - - for (i = 0; i < rank; i++) { - select_per_cs_training_index(chan, i); - /* PI_80 PI_RDLVL_EN:RW:16:2 */ - clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16); - /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ - clrsetbits_le32(&denali_pi[74], - (0x1 << 8) | (0x3 << 24), - (0x1 << 8) | (i << 24)); - - /* Waiting for training complete */ - while (1) { - /* PI_174 PI_INT_STATUS:RD:8:18 */ - tmp = readl(&denali_pi[174]) >> 8; - - /* - * make sure status obs not report error bit - * PHY_46/174/302/430 - * phy_rdlvl_status_obs_X:16:8 - */ - if ((((tmp >> 8) & 0x1) == 0x1) && - (((tmp >> 13) & 0x1) == 0x1) && - (((tmp >> 2) & 0x1) == 0x0)) - break; - else if (((tmp >> 2) & 0x1) == 0x1) - return -EIO; - } - /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ - writel(0x00003f7c, (&denali_pi[175])); - } - clrbits_le32(&denali_pi[80], 0x3 << 16); - - return 0; -} - -static int data_training_wdql(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params) -{ - u32 *denali_pi = chan->pi->denali_pi; - u32 i, tmp; - u32 rank = sdram_params->ch[channel].rank; - - for (i = 0; i < rank; i++) { - select_per_cs_training_index(chan, i); - /* - * disable PI_WDQLVL_VREF_EN before wdq leveling? - * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 - */ - clrbits_le32(&denali_pi[181], 0x1 << 8); - /* PI_124 PI_WDQLVL_EN:RW:16:2 */ - clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16); - /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ - clrsetbits_le32(&denali_pi[121], - (0x1 << 8) | (0x3 << 16), - (0x1 << 8) | (i << 16)); - - /* Waiting for training complete */ - while (1) { - /* PI_174 PI_INT_STATUS:RD:8:18 */ - tmp = readl(&denali_pi[174]) >> 8; - if ((((tmp >> 12) & 0x1) == 0x1) && - (((tmp >> 13) & 0x1) == 0x1) && - (((tmp >> 6) & 0x1) == 0x0)) - break; - else if (((tmp >> 6) & 0x1) == 0x1) - return -EIO; - } - /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ - writel(0x00003f7c, (&denali_pi[175])); - } - clrbits_le32(&denali_pi[124], 0x3 << 16); - - return 0; -} - -static int data_training(const struct chan_info *chan, u32 channel, - const struct rk3399_sdram_params *sdram_params, - u32 training_flag) -{ - u32 *denali_phy = chan->publ->denali_phy; - - /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ - setbits_le32(&denali_phy[927], (1 << 22)); - - if (training_flag == PI_FULL_TRAINING) { - if (sdram_params->base.dramtype == LPDDR4) { - training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | - PI_READ_GATE_TRAINING | - PI_READ_LEVELING | PI_WDQ_LEVELING; - } else if (sdram_params->base.dramtype == LPDDR3) { - training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | - PI_READ_GATE_TRAINING; - } else if (sdram_params->base.dramtype == DDR3) { - training_flag = PI_WRITE_LEVELING | - PI_READ_GATE_TRAINING | - PI_READ_LEVELING; - } - } - - /* ca training(LPDDR4,LPDDR3 support) */ - if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) - data_training_ca(chan, channel, sdram_params); - - /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ - if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) - data_training_wl(chan, channel, sdram_params); - - /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ - if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) - data_training_rg(chan, channel, sdram_params); - - /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ - if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) - data_training_rl(chan, channel, sdram_params); - - /* wdq leveling(LPDDR4 support) */ - if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) - data_training_wdql(chan, channel, sdram_params); - - /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ - clrbits_le32(&denali_phy[927], (1 << 22)); - - return 0; -} - -static void set_ddrconfig(const struct chan_info *chan, - const struct rk3399_sdram_params *sdram_params, - unsigned char channel, u32 ddrconfig) -{ - /* only need to set ddrconfig */ - struct rk3399_msch_regs *ddr_msch_regs = chan->msch; - unsigned int cs0_cap = 0; - unsigned int cs1_cap = 0; - - cs0_cap = (1 << (sdram_params->ch[channel].cs0_row - + sdram_params->ch[channel].col - + sdram_params->ch[channel].bk - + sdram_params->ch[channel].bw - 20)); - if (sdram_params->ch[channel].rank > 1) - cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row - - sdram_params->ch[channel].cs1_row); - if (sdram_params->ch[channel].row_3_4) { - cs0_cap = cs0_cap * 3 / 4; - cs1_cap = cs1_cap * 3 / 4; - } - - writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf); - writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8), - &ddr_msch_regs->ddrsize); -} - -static void dram_all_config(struct dram_info *dram, - const struct rk3399_sdram_params *sdram_params) -{ - u32 sys_reg = 0; - unsigned int channel, idx; - - sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; - sys_reg |= (sdram_params->base.num_channels - 1) - << SYS_REG_NUM_CH_SHIFT; - for (channel = 0, idx = 0; - (idx < sdram_params->base.num_channels) && (channel < 2); - channel++) { - const struct rk3399_sdram_channel *info = - &sdram_params->ch[channel]; - struct rk3399_msch_regs *ddr_msch_regs; - const struct rk3399_msch_timings *noc_timing; - - if (sdram_params->ch[channel].col == 0) - continue; - idx++; - sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel); - sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel); - sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel); - sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel); - sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel); - sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel); - sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel); - sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel); - sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel); - - ddr_msch_regs = dram->chan[channel].msch; - noc_timing = &sdram_params->ch[channel].noc_timings; - writel(noc_timing->ddrtiminga0, - &ddr_msch_regs->ddrtiminga0); - writel(noc_timing->ddrtimingb0, - &ddr_msch_regs->ddrtimingb0); - writel(noc_timing->ddrtimingc0, - &ddr_msch_regs->ddrtimingc0); - writel(noc_timing->devtodev0, - &ddr_msch_regs->devtodev0); - writel(noc_timing->ddrmode, - &ddr_msch_regs->ddrmode); - - /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ - if (sdram_params->ch[channel].rank == 1) - setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], - 1 << 17); - } - - writel(sys_reg, &dram->pmugrf->os_reg2); - rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, - sdram_params->base.stride << 10); - - /* reboot hold register set */ - writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) | - PRESET_GPIO1_HOLD(1), - &dram->pmucru->pmucru_rstnhold_con[1]); - clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3); -} - -static int switch_to_phy_index1(struct dram_info *dram, - const struct rk3399_sdram_params *sdram_params) -{ - u32 channel; - u32 *denali_phy; - u32 ch_count = sdram_params->base.num_channels; - int ret; - int i = 0; - - writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1, - 1 << 4 | 1 << 2 | 1), - &dram->cic->cic_ctrl0); - while (!(readl(&dram->cic->cic_status0) & (1 << 2))) { - mdelay(10); - i++; - if (i > 10) { - debug("index1 frequency change overtime\n"); - return -ETIME; - } - } - - i = 0; - writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0); - while (!(readl(&dram->cic->cic_status0) & (1 << 0))) { - mdelay(10); - if (i > 10) { - debug("index1 frequency done overtime\n"); - return -ETIME; - } - } - - for (channel = 0; channel < ch_count; channel++) { - denali_phy = dram->chan[channel].publ->denali_phy; - clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); - ret = data_training(&dram->chan[channel], channel, - sdram_params, PI_FULL_TRAINING); - if (ret) { - debug("index1 training failed\n"); - return ret; - } - } - - return 0; -} - -static int sdram_init(struct dram_info *dram, - const struct rk3399_sdram_params *sdram_params) -{ - unsigned char dramtype = sdram_params->base.dramtype; - unsigned int ddr_freq = sdram_params->base.ddr_freq; - int channel; - - debug("Starting SDRAM initialization...\n"); - - if ((dramtype == DDR3 && ddr_freq > 933) || - (dramtype == LPDDR3 && ddr_freq > 933) || - (dramtype == LPDDR4 && ddr_freq > 800)) { - debug("SDRAM frequency is to high!"); - return -E2BIG; - } - - for (channel = 0; channel < 2; channel++) { - const struct chan_info *chan = &dram->chan[channel]; - struct rk3399_ddr_publ_regs *publ = chan->publ; - - phy_dll_bypass_set(publ, ddr_freq); - - if (channel >= sdram_params->base.num_channels) - continue; - - if (pctl_cfg(chan, channel, sdram_params) != 0) { - printf("pctl_cfg fail, reset\n"); - return -EIO; - } - - /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ - if (dramtype == LPDDR3) - udelay(10); - - if (data_training(chan, channel, - sdram_params, PI_FULL_TRAINING)) { - printf("SDRAM initialization failed, reset\n"); - return -EIO; - } - - set_ddrconfig(chan, sdram_params, channel, - sdram_params->ch[channel].ddrconfig); - } - dram_all_config(dram, sdram_params); - switch_to_phy_index1(dram, sdram_params); - - debug("Finish SDRAM initialization...\n"); - return 0; -} - -static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev) -{ -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rockchip_dmc_plat *plat = dev_get_platdata(dev); - int ret; - - ret = dev_read_u32_array(dev, "rockchip,sdram-params", - (u32 *)&plat->sdram_params, - sizeof(plat->sdram_params) / sizeof(u32)); - if (ret) { - printf("%s: Cannot read rockchip,sdram-params %d\n", - __func__, ret); - return ret; - } - ret = regmap_init_mem(dev, &plat->map); - if (ret) - printf("%s: regmap failed %d\n", __func__, ret); - -#endif - return 0; -} - -#if CONFIG_IS_ENABLED(OF_PLATDATA) -static int conv_of_platdata(struct udevice *dev) -{ - struct rockchip_dmc_plat *plat = dev_get_platdata(dev); - struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; - int ret; - - ret = regmap_init_mem_platdata(dev, dtplat->reg, - ARRAY_SIZE(dtplat->reg) / 2, - &plat->map); - if (ret) - return ret; - - return 0; -} -#endif - -static int rk3399_dmc_init(struct udevice *dev) -{ - struct dram_info *priv = dev_get_priv(dev); - struct rockchip_dmc_plat *plat = dev_get_platdata(dev); - int ret; -#if !CONFIG_IS_ENABLED(OF_PLATDATA) - struct rk3399_sdram_params *params = &plat->sdram_params; -#else - struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; - struct rk3399_sdram_params *params = - (void *)dtplat->rockchip_sdram_params; - - ret = conv_of_platdata(dev); - if (ret) - return ret; -#endif - - priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); - priv->pmucru = rockchip_get_pmucru(); - priv->cru = rockchip_get_cru(); - priv->chan[0].pctl = regmap_get_range(plat->map, 0); - priv->chan[0].pi = regmap_get_range(plat->map, 1); - priv->chan[0].publ = regmap_get_range(plat->map, 2); - priv->chan[0].msch = regmap_get_range(plat->map, 3); - priv->chan[1].pctl = regmap_get_range(plat->map, 4); - priv->chan[1].pi = regmap_get_range(plat->map, 5); - priv->chan[1].publ = regmap_get_range(plat->map, 6); - priv->chan[1].msch = regmap_get_range(plat->map, 7); - - debug("con reg %p %p %p %p %p %p %p %p\n", - priv->chan[0].pctl, priv->chan[0].pi, - priv->chan[0].publ, priv->chan[0].msch, - priv->chan[1].pctl, priv->chan[1].pi, - priv->chan[1].publ, priv->chan[1].msch); - debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru, - priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru); -#if CONFIG_IS_ENABLED(OF_PLATDATA) - ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk); -#else - ret = clk_get_by_index(dev, 0, &priv->ddr_clk); -#endif - if (ret) { - printf("%s clk get failed %d\n", __func__, ret); - return ret; - } - ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz); - if (ret < 0) { - printf("%s clk set failed %d\n", __func__, ret); - return ret; - } - ret = sdram_init(priv, params); - if (ret < 0) { - printf("%s DRAM init failed%d\n", __func__, ret); - return ret; - } - - return 0; -} -#endif - -static int rk3399_dmc_probe(struct udevice *dev) -{ -#ifdef CONFIG_SPL_BUILD - if (rk3399_dmc_init(dev)) - return 0; -#else - struct dram_info *priv = dev_get_priv(dev); - - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; - priv->info.size = rockchip_sdram_size( - (phys_addr_t)&priv->pmugrf->os_reg2); -#endif - return 0; -} - -static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info) -{ - struct dram_info *priv = dev_get_priv(dev); - - *info = priv->info; - - return 0; -} - -static struct ram_ops rk3399_dmc_ops = { - .get_info = rk3399_dmc_get_info, -}; - - -static const struct udevice_id rk3399_dmc_ids[] = { - { .compatible = "rockchip,rk3399-dmc" }, - { } -}; - -U_BOOT_DRIVER(dmc_rk3399) = { - .name = "rockchip_rk3399_dmc", - .id = UCLASS_RAM, - .of_match = rk3399_dmc_ids, - .ops = &rk3399_dmc_ops, -#ifdef CONFIG_SPL_BUILD - .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata, -#endif - .probe = rk3399_dmc_probe, - .priv_auto_alloc_size = sizeof(struct dram_info), -#ifdef CONFIG_SPL_BUILD - .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat), -#endif -}; diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 4f78c72..843998d 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -10,6 +10,25 @@ #include <spl.h> #if CONFIG_IS_ENABLED(OF_CONTROL) +/** + * spl_node_to_boot_device() - maps from a DT-node to a SPL boot device + * @node: of_offset of the node + * + * The SPL framework uses BOOT_DEVICE_... constants to identify its boot + * sources. These may take on a device-specific meaning, depending on + * what nodes are enabled in a DTS (e.g. BOOT_DEVICE_MMC1 may refer to + * different controllers/block-devices, depending on which SD/MMC controllers + * are enabled in any given DTS). This function maps from a DT-node back + * onto a BOOT_DEVICE_... constant, considering the currently active devices. + * + * Returns + * -ENOENT, if no device matching the node could be found + * -ENOSYS, if the device matching the node can not be mapped onto a + * SPL boot device (e.g. the third MMC device) + * -1, for unspecified failures + * a positive integer (from the BOOT_DEVICE_... family) on succes. + */ + static int spl_node_to_boot_device(int node) { struct udevice *parent; @@ -57,6 +76,24 @@ static int spl_node_to_boot_device(int node) return -1; } +/** + * board_spl_was_booted_from() - retrieves the of-path the SPL was loaded from + * + * To support a 'same-as-spl' specification in the search-order for the next + * stage, we need a SoC- or board-specific way to handshake with what 'came + * before us' (either a BROM or TPL stage) and map the info retrieved onto + * a OF path. + * + * Returns + * NULL, on failure or if the device could not be identified + * a of_path (a string), on success + */ +__weak const char *board_spl_was_booted_from(void) +{ + debug("%s: no support for 'same-as-spl' for this board\n", __func__); + return NULL; +} + void board_boot_order(u32 *spl_boot_list) { const void *blob = gd->fdt_blob; @@ -78,8 +115,17 @@ void board_boot_order(u32 *spl_boot_list) (conf = fdt_stringlist_get(blob, chosen_node, "u-boot,spl-boot-order", elem, NULL)); elem++) { + const char *alias; + + /* Handle the case of 'same device the SPL was loaded from' */ + if (strncmp(conf, "same-as-spl", 11) == 0) { + conf = board_spl_was_booted_from(); + if (!conf) + continue; + } + /* First check if the list element is an alias */ - const char *alias = fdt_get_alias(blob, conf); + alias = fdt_get_alias(blob, conf); if (alias) conf = alias; diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 2f1da74..91ddb79 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -144,7 +144,7 @@ static const struct { const u16 pn; const char *name; const char *var; -} const socfpga_fpga_model[] = { +} socfpga_fpga_model[] = { /* Cyclone V E */ { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" }, { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" }, diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index 66f1ec2..ae16897 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -174,7 +174,7 @@ void socfpga_emac_manage_reset(ulong emacbase, u32 state) emacmask = ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK; break; default: - error("emac base address unexpected! %lx", emacbase); + pr_err("emac base address unexpected! %lx", emacbase); hang(); break; } diff --git a/arch/arm/mach-stm32/stm32f7/timer.c b/arch/arm/mach-stm32/stm32f7/timer.c index c15f8bb..b04c101 100644 --- a/arch/arm/mach-stm32/stm32f7/timer.c +++ b/arch/arm/mach-stm32/stm32f7/timer.c @@ -26,7 +26,7 @@ int timer_init(void) /* Stop the timer */ writel(readl(&gpt1_regs_ptr->cr1) & ~GPT_CR1_CEN, &gpt1_regs_ptr->cr1); - writel((CONFIG_SYS_CLK_FREQ/CONFIG_SYS_HZ_CLOCK) - 1, + writel((CONFIG_SYS_CLK_FREQ / 2 / CONFIG_SYS_HZ_CLOCK) - 1, &gpt1_regs_ptr->psc); /* Configure timer for auto-reload */ diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 65b1ebd..0c60ee0 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -14,9 +14,7 @@ #include <mmc.h> #include <i2c.h> #include <serial.h> -#ifdef CONFIG_SPL_BUILD #include <spl.h> -#endif #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/clock.h> @@ -212,11 +210,12 @@ void s_init(void) #ifdef CONFIG_SPL_BUILD DECLARE_GLOBAL_DATA_PTR; +#endif /* The sunxi internal brom will try to loader external bootloader * from mmc0, nand flash, mmc2. */ -u32 spl_boot_device(void) +uint32_t sunxi_get_boot_device(void) { int boot_source; @@ -255,6 +254,12 @@ u32 spl_boot_device(void) return -1; /* Never reached */ } +#ifdef CONFIG_SPL_BUILD +u32 spl_boot_device(void) +{ + return sunxi_get_boot_device(); +} + /* No confirmation data available in SPL yet. Hardcode bootmode */ u32 spl_boot_mode(const u32 boot_device) { diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index 9bf0b56..2f1cad1 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -18,12 +18,18 @@ #include <asm/io.h> #include <errno.h> -#define SUNXI_USB_PMU_IRQ_ENABLE 0x800 -#ifdef CONFIG_MACH_SUN8I_A33 -#define SUNXI_USB_CSR 0x410 -#else +#if defined(CONFIG_MACH_SUN4I) || \ + defined(CONFIG_MACH_SUN5I) || \ + defined(CONFIG_MACH_SUN6I) || \ + defined(CONFIG_MACH_SUN7I) || \ + defined(CONFIG_MACH_SUN8I_A23) || \ + defined(CONFIG_MACH_SUN9I) #define SUNXI_USB_CSR 0x404 +#else +#define SUNXI_USB_CSR 0x410 #endif + +#define SUNXI_USB_PMU_IRQ_ENABLE 0x800 #define SUNXI_USB_PASSBY_EN 1 #define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10) diff --git a/arch/arm/mach-tegra/ivc.c b/arch/arm/mach-tegra/ivc.c index cf6626f..dec7d90 100644 --- a/arch/arm/mach-tegra/ivc.c +++ b/arch/arm/mach-tegra/ivc.c @@ -493,7 +493,7 @@ static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes, (TEGRA_IVC_ALIGN - 1)); if ((uint64_t)nframes * (uint64_t)frame_size >= 0x100000000) { - error("tegra_ivc: nframes * frame_size overflows\n"); + pr_err("tegra_ivc: nframes * frame_size overflows\n"); return -EINVAL; } @@ -503,12 +503,12 @@ static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes, */ if ((qbase1 & (TEGRA_IVC_ALIGN - 1)) || (qbase2 & (TEGRA_IVC_ALIGN - 1))) { - error("tegra_ivc: channel start not aligned\n"); + pr_err("tegra_ivc: channel start not aligned\n"); return -EINVAL; } if (frame_size & (TEGRA_IVC_ALIGN - 1)) { - error("tegra_ivc: frame size not adequately aligned\n"); + pr_err("tegra_ivc: frame size not adequately aligned\n"); return -EINVAL; } @@ -521,7 +521,7 @@ static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes, } if (ret) { - error("tegra_ivc: queue regions overlap\n"); + pr_err("tegra_ivc: queue regions overlap\n"); return ret; } diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c b/arch/arm/mach-tegra/tegra124/xusb-padctl.c index d326a6a..bfc0ab8 100644 --- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c @@ -137,7 +137,7 @@ static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) u32 value; if (padctl->enable == 0) { - error("unbalanced enable/disable"); + pr_err("unbalanced enable/disable"); return 0; } diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c index 966cf9f..5224ef6 100644 --- a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c +++ b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c @@ -45,12 +45,12 @@ int dram_init(void) node = fdt_path_offset(nvtboot_blob, "/memory"); if (node < 0) { - error("Can't find /memory node in nvtboot DTB"); + pr_err("Can't find /memory node in nvtboot DTB"); hang(); } prop = fdt_getprop(nvtboot_blob, node, "reg", &len); if (!prop) { - error("Can't find /memory/reg property in nvtboot DTB"); + pr_err("Can't find /memory/reg property in nvtboot DTB"); hang(); } diff --git a/arch/arm/mach-tegra/tegra20/clock.c b/arch/arm/mach-tegra/tegra20/clock.c index ec04cf5..81fb1d8 100644 --- a/arch/arm/mach-tegra/tegra20/clock.c +++ b/arch/arm/mach-tegra/tegra20/clock.c @@ -667,7 +667,7 @@ static int tegra_plle_train(void) } while (--timeout); if (timeout == 0) { - error("timeout waiting for PLLE to become ready"); + pr_err("timeout waiting for PLLE to become ready"); return -ETIMEDOUT; } @@ -697,7 +697,7 @@ int tegra_plle_enable(void) if ((value & PLLE_MISC_PLL_READY) == 0) { err = tegra_plle_train(); if (err < 0) { - error("failed to train PLLE: %d", err); + pr_err("failed to train PLLE: %d", err); return err; } } @@ -726,7 +726,7 @@ int tegra_plle_enable(void) } while (--timeout); if (timeout == 0) { - error("timeout waiting for PLLE to lock"); + pr_err("timeout waiting for PLLE to lock"); return -ETIMEDOUT; } diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c index bf85e07..a3e3e37 100644 --- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c @@ -125,7 +125,7 @@ static int tegra_xusb_padctl_disable(struct tegra_xusb_padctl *padctl) u32 value; if (padctl->enable == 0) { - error("unbalanced enable/disable"); + pr_err("unbalanced enable/disable"); return 0; } diff --git a/arch/arm/mach-tegra/tegra30/clock.c b/arch/arm/mach-tegra/tegra30/clock.c index 4fd8b8a..282f34f 100644 --- a/arch/arm/mach-tegra/tegra30/clock.c +++ b/arch/arm/mach-tegra/tegra30/clock.c @@ -696,7 +696,7 @@ static int tegra_plle_train(void) } while (--timeout); if (timeout == 0) { - error("timeout waiting for PLLE to become ready"); + pr_err("timeout waiting for PLLE to become ready"); return -ETIMEDOUT; } @@ -726,7 +726,7 @@ int tegra_plle_enable(void) if ((value & PLLE_MISC_PLL_READY) == 0) { err = tegra_plle_train(); if (err < 0) { - error("failed to train PLLE: %d", err); + pr_err("failed to train PLLE: %d", err); return err; } } @@ -772,7 +772,7 @@ int tegra_plle_enable(void) } while (--timeout); if (timeout == 0) { - error("timeout waiting for PLLE to lock"); + pr_err("timeout waiting for PLLE to lock"); return -ETIMEDOUT; } diff --git a/arch/arm/mach-tegra/xusb-padctl-common.c b/arch/arm/mach-tegra/xusb-padctl-common.c index abc18c0..c8a468a 100644 --- a/arch/arm/mach-tegra/xusb-padctl-common.c +++ b/arch/arm/mach-tegra/xusb-padctl-common.c @@ -84,7 +84,7 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl, len = ofnode_read_string_count(node, "nvidia,lanes"); if (len < 0) { - error("failed to parse \"nvidia,lanes\" property"); + pr_err("failed to parse \"nvidia,lanes\" property"); return -EINVAL; } @@ -94,7 +94,7 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl, ret = ofnode_read_string_index(node, "nvidia,lanes", i, &group->pins[i]); if (ret) { - error("failed to read string from \"nvidia,lanes\" property"); + pr_err("failed to read string from \"nvidia,lanes\" property"); return -EINVAL; } } @@ -104,7 +104,7 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl, ret = ofnode_read_string_index(node, "nvidia,function", 0, &group->func); if (ret) { - error("failed to parse \"nvidia,func\" property"); + pr_err("failed to parse \"nvidia,func\" property"); return -EINVAL; } @@ -157,14 +157,14 @@ tegra_xusb_padctl_group_apply(struct tegra_xusb_padctl *padctl, lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]); if (!lane) { - error("no lane for pin %s", group->pins[i]); + pr_err("no lane for pin %s", group->pins[i]); continue; } func = tegra_xusb_padctl_lane_find_function(padctl, lane, group->func); if (func < 0) { - error("function %s invalid for lane %s: %d", + pr_err("function %s invalid for lane %s: %d", group->func, lane->name, func); continue; } @@ -206,7 +206,7 @@ tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl, err = tegra_xusb_padctl_group_apply(padctl, group); if (err < 0) { - error("failed to apply group %s: %d", + pr_err("failed to apply group %s: %d", group->name, err); continue; } @@ -232,7 +232,7 @@ tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl, err = tegra_xusb_padctl_group_parse_dt(padctl, group, subnode); if (err < 0) { - error("failed to parse group %s", group->name); + pr_err("failed to parse group %s", group->name); return err; } @@ -250,7 +250,7 @@ static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, err = ofnode_read_resource(node, 0, &padctl->regs); if (err < 0) { - error("registers not found"); + pr_err("registers not found"); return err; } @@ -261,7 +261,7 @@ static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, err = tegra_xusb_padctl_config_parse_dt(padctl, config, subnode); if (err < 0) { - error("failed to parse entry %s: %d", + pr_err("failed to parse entry %s: %d", config->name, err); continue; } @@ -289,7 +289,7 @@ int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count, err = tegra_xusb_padctl_parse_dt(&padctl, nodes[i]); if (err < 0) { - error("failed to parse DT: %d", err); + pr_err("failed to parse DT: %d", err); continue; } @@ -298,7 +298,7 @@ int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count, err = tegra_xusb_padctl_config_apply(&padctl, &padctl.config); if (err < 0) { - error("failed to apply pinmux: %d", err); + pr_err("failed to apply pinmux: %d", err); continue; } diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 32d3593..2213685 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -15,9 +15,6 @@ #include "sg-regs.h" #include "soc-info.h" -#define pr_warn(fmt, args...) printf(fmt, ##args) -#define pr_err(fmt, args...) printf(fmt, ##args) - DECLARE_GLOBAL_DATA_PTR; struct uniphier_memif_data { diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index 29f638d..da20935 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -104,9 +104,4 @@ int uniphier_have_internal_stm(void); int uniphier_boot_from_backend(void); int uniphier_pin_init(const char *pinconfig_name); -#undef pr_warn -#define pr_warn(fmt, args...) printf(fmt, ##args) -#undef pr_err -#define pr_err(fmt, args...) printf(fmt, ##args) - #endif /* __MACH_INIT_H */ |