16 files changed, 20 insertions, 20 deletions
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
index bee9318..085649e 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -46,7 +46,7 @@ void reset_cpu(ulong addr)
 int arch_cpu_init(void)
 {
 	/*
-	 * It might be necessary to flush data cache, if U-boot is loaded
+	 * It might be necessary to flush data cache, if U-Boot is loaded
 	 * from kickstart bootloader, e.g. from S1L loader
 	 */
 	flush_dcache_all();
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S
index 4b8053e..b21abc3 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S
@@ -41,5 +41,5 @@ lowlevel_init:
 	orr	r0, #0x00000004
 	str	r0, [r1]
 
-	/* Return to U-boot via saved link register */
+	/* Return to U-Boot via saved link register */
 	mov	pc, lr
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 31d1c9e..b7563ed 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -37,7 +37,7 @@ _monitor_vectors:
 
 /*
  * secure monitor handler
- * U-boot calls this "software interrupt" in start.S
+ * U-Boot calls this "software interrupt" in start.S
  * This is executed on a "smc" instruction, we use a "smc #0" to switch
  * to non-secure state.
  * r0, r1, r2: passed to the callee
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 4cd84b0..3d19bbf 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -1,6 +1,6 @@
 if ARM64
 
 config ARMV8_MULTIENTRY
-        boolean "Enable multiple CPUs to enter into U-boot"
+        boolean "Enable multiple CPUs to enter into U-Boot"
 
 endif
diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
index 469bd05..f62916d 100644
--- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
@@ -59,7 +59,7 @@
 	status = "okay";
 };
 
-/* for U-boot only */
+/* for U-Boot only */
 / {
 	soc {
 		u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
index e0a972f..dca408b 100644
--- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
@@ -61,7 +61,7 @@
 	status = "okay";
 };
 
-/* for U-boot only */
+/* for U-Boot only */
 / {
 	soc {
 		u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
index 02e74a7..202a642 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
@@ -66,7 +66,7 @@
 	status = "okay";
 };
 
-/* for U-boot only */
+/* for U-Boot only */
 / {
 	soc {
 		u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
index d46e827..02a3362 100644
--- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
+++ b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
@@ -47,7 +47,7 @@
 	status = "okay";
 };
 
-/* for U-boot only */
+/* for U-Boot only */
 / {
 	soc {
 		u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
index 1f3aee9..ff17945 100644
--- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts
@@ -68,7 +68,7 @@
 	status = "okay";
 };
 
-/* for U-boot only */
+/* for U-Boot only */
 &serial0 {
        u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
index b58bf07..b5b6f65 100644
--- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
@@ -63,7 +63,7 @@
 	status = "okay";
 };
 
-/* for U-boot only */
+/* for U-Boot only */
 / {
 	soc {
 		u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts
index a49215e..c6c133a 100644
--- a/arch/arm/dts/uniphier-proxstream2-gentil.dts
+++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts
@@ -49,7 +49,7 @@
 	status = "okay";
 };
 
-/* for U-boot only */
+/* for U-Boot only */
 / {
 	soc {
 		u-boot,dm-pre-reloc;
diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts
index 63bd363..3703ad3 100644
--- a/arch/arm/dts/uniphier-proxstream2-vodka.dts
+++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts
@@ -45,7 +45,7 @@
 	status = "okay";
 };
 
-/* for U-boot only */
+/* for U-Boot only */
 / {
 	soc {
 		u-boot,dm-pre-reloc;
diff --git a/arch/arm/mach-exynos/include/mach/spl.h b/arch/arm/mach-exynos/include/mach/spl.h
index 0c480ac..a5d13fa 100644
--- a/arch/arm/mach-exynos/include/mach/spl.h
+++ b/arch/arm/mach-exynos/include/mach/spl.h
@@ -42,10 +42,10 @@ struct spl_machine_param {
 	u32		mem_iv_size;	/* Memory channel interleaving size */
 	enum ddr_mode	mem_type;	/* Type of on-board memory */
 	/*
-	 * U-boot size - The iROM mmc copy function used by the SPL takes a
-	 * block count paramter to describe the u-boot size unlike the spi
-	 * boot copy function which just uses the u-boot size directly. Align
-	 * the u-boot size to block size (512 bytes) when populating the SPL
+	 * U-Boot size - The iROM mmc copy function used by the SPL takes a
+	 * block count paramter to describe the U-Boot size unlike the spi
+	 * boot copy function which just uses the U-Boot size directly. Align
+	 * the U-Boot size to block size (512 bytes) when populating the SPL
 	 * table only for mmc boot.
 	 */
 	u32		uboot_size;
diff --git a/arch/arm/mach-exynos/sec_boot.S b/arch/arm/mach-exynos/sec_boot.S
index dfc3455..5dc216d 100644
--- a/arch/arm/mach-exynos/sec_boot.S
+++ b/arch/arm/mach-exynos/sec_boot.S
@@ -30,10 +30,10 @@ relocate_wait_code:
  * because that comes out to be the last 4KB of the iRAM
  * (Base Address - 0x02020000, Limit Address - 0x020740000).
  *
- * U-boot and kernel are aware of this code and flags by the simple
+ * U-Boot and kernel are aware of this code and flags by the simple
  * fact that we are implementing a workaround in the last 4KB
  * of the iRAM and we have already defined these flag and address
- * values in both kernel and U-boot for our use.
+ * values in both kernel and U-Boot for our use.
  */
 code_base:
 	b	 1f
diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c
index c7f943e..7df0102 100644
--- a/arch/arm/mach-exynos/spl_boot.c
+++ b/arch/arm/mach-exynos/spl_boot.c
@@ -177,7 +177,7 @@ static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
 #endif
 
 /*
-* Copy U-boot from mmc to RAM:
+* Copy U-Boot from mmc to RAM:
 * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
 * Pointer to API (Data transfer from mmc to ram)
 */
diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S
index 51a8b3c..3f38f36 100644
--- a/arch/arm/mach-orion5x/lowlevel_init.S
+++ b/arch/arm/mach-orion5x/lowlevel_init.S
@@ -283,5 +283,5 @@ lowlevel_init:
 
 #endif /* CONFIG_SPL_BUILD */
 
-	/* Return to U-boot via saved link register */
+	/* Return to U-Boot via saved link register */
 	mov	pc, lr