diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/Kconfig | 2 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/ddr.c | 11 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/boot-common.c | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-stm32f4/stm32.h | 10 |
4 files changed, 22 insertions, 2 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7383975..75d6bbc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -697,6 +697,8 @@ config ARCH_UNIPHIER config TARGET_STM32F429_DISCOVERY bool "Support STM32F429 Discovery" select CPU_V7M + select DM + select DM_SERIAL config ARCH_ROCKCHIP bool "Support Rockchip SoCs" diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index b3fb0c4..888cf1f 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -164,6 +164,13 @@ void config_sdram(const struct emif_regs *regs, int nr) writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); + + /* Trigger initialization */ + writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); + /* Wait 1ms because of L3 timeout error */ + udelay(1000); + + /* Write proper sdram_ref_cref_ctrl value */ writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); } @@ -292,7 +299,9 @@ void config_ddr_phy(const struct emif_regs *regs, int nr) EMIF_REG_INITREF_DIS_MASK); #endif if (regs->zq_config) - writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl); + /* Set time between rising edge of DDR_RESET to rising + * edge of DDR_CKE to > 500us per memory spec. */ + writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1); diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 8e5d5c9..0456263 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -208,6 +208,7 @@ int board_mmc_init(bd_t *bis) break; case BOOT_DEVICE_MMC2: case BOOT_DEVICE_MMC2_2: + omap_mmc_init(0, 0, 0, -1, -1); omap_mmc_init(1, 0, 0, -1, -1); break; } diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h index 7ca6dc3..6b64d03 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32.h @@ -3,7 +3,7 @@ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com * * (C) Copyright 2015 - * Kamil Lulko, <rev13@wp.pl> + * Kamil Lulko, <kamil.lulko@gmail.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -106,6 +106,14 @@ struct stm32_flash_regs { #define STM32_FLASH_CR_SNB_OFFSET 3 #define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET) +/* + * Peripheral base addresses + */ +#define STM32_USART1_BASE (STM32_APB2PERIPH_BASE + 0x1000) +#define STM32_USART2_BASE (STM32_APB1PERIPH_BASE + 0x4400) +#define STM32_USART3_BASE (STM32_APB1PERIPH_BASE + 0x4800) +#define STM32_USART6_BASE (STM32_APB2PERIPH_BASE + 0x1400) + enum clock { CLOCK_CORE, CLOCK_AHB, |