diff options
Diffstat (limited to 'arch/powerpc/cpu/mpc8xxx')
-rw-r--r-- | arch/powerpc/cpu/mpc8xxx/cpu.c | 3 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 15 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 2 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 1 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/interactive.c | 4 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c | 4 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/main.c | 65 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc8xxx/ddr/options.c | 2 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc8xxx/fdt.c | 22 | ||||
-rw-r--r-- | arch/powerpc/cpu/mpc8xxx/law.c | 6 |
10 files changed, 87 insertions, 37 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 7369582..c67be4e 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -79,6 +79,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(BSC9131, 9131, 1), CPU_TYPE_ENTRY(BSC9132, 9132, 2), CPU_TYPE_ENTRY(BSC9232, 9232, 2), + CPU_TYPE_ENTRY(C291, C291, 1), + CPU_TYPE_ENTRY(C292, C292, 1), + CPU_TYPE_ENTRY(C293, C293, 1), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index ff5812d..242eb47 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -364,7 +364,7 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, ddr->timing_cfg_3 = (0 | ((ext_pretoact & 0x1) << 28) - | ((ext_acttopre & 0x2) << 24) + | ((ext_acttopre & 0x3) << 24) | ((ext_acttorw & 0x1) << 22) | ((ext_refrec & 0x1F) << 16) | ((ext_caslat & 0x3) << 12) @@ -681,6 +681,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, unsigned int odt_cfg = 0; /* ODT configuration */ unsigned int num_pr; /* Number of posted refreshes */ unsigned int slow = 0; /* DDR will be run less than 1250 */ + unsigned int x4_en = 0; /* x4 DRAM enable */ unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */ unsigned int ap_en; /* Address Parity Enable */ unsigned int d_init; /* DRAM data initialization */ @@ -725,6 +726,8 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, ap_en = 0; } + x4_en = popts->x4_en ? 1 : 0; + #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) /* Use the DDR controller to auto initialize memory. */ d_init = popts->ECC_init_using_memctl; @@ -747,6 +750,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, | ((odt_cfg & 0x3) << 21) | ((num_pr & 0xf) << 12) | ((slow & 1) << 11) + | (x4_en << 10) | (qd_en << 9) | (unq_mrs_en << 8) | ((obc_cfg & 0x1) << 6) @@ -1585,8 +1589,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, | ((ea & 0xFFF) << 0) /* ending address MSB */ ); } else { - debug("FSLDDR: setting bnds to 0 for inactive CS\n"); - ddr->cs[i].bnds = 0; + /* setting bnds to 0xffffffff for inactive CS */ + ddr->cs[i].bnds = 0xffffffff; } debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds); @@ -1638,5 +1642,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_sdram_rcw(ddr, popts, common_dimm); +#ifdef CONFIG_SYS_FSL_DDR_EMU + /* disble DDR training for emulator */ + ddr->debug[2] = 0x00000400; + ddr->debug[4] = 0xff800000; +#endif return check_fsl_memctl_config_regs(ddr); } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index 4dd55fc..c173a5a 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -96,7 +96,7 @@ unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); /* processor specific function */ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num); + unsigned int ctrl_num, int step); /* board specific function */ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index 3e7c269..b67158c 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -129,6 +129,7 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, pdimm->ec_sdram_width = 0; pdimm->data_width = pdimm->primary_sdram_width + pdimm->ec_sdram_width; + pdimm->device_width = 1 << ((spd->organization & 0x7) + 2); /* These are the types defined by the JEDEC DDR3 SPD spec */ pdimm->mirrored_dimm = 0; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c index 1ed6c77..260fce5 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c @@ -205,6 +205,7 @@ static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo, DIMM_PARM(primary_sdram_width), DIMM_PARM(ec_sdram_width), DIMM_PARM(registered_dimm), + DIMM_PARM(device_width), DIMM_PARM(n_row_addr), DIMM_PARM(n_col_addr), @@ -263,6 +264,7 @@ static void print_dimm_parameters(const dimm_params_t *pdimm) DIMM_PARM(primary_sdram_width), DIMM_PARM(ec_sdram_width), DIMM_PARM(registered_dimm), + DIMM_PARM(device_width), DIMM_PARM(n_row_addr), DIMM_PARM(n_col_addr), @@ -443,6 +445,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, CTRL_OPTIONS(twoT_en), CTRL_OPTIONS(threeT_en), CTRL_OPTIONS(ap_en), + CTRL_OPTIONS(x4_en), CTRL_OPTIONS(bstopre), CTRL_OPTIONS(wrlvl_override), CTRL_OPTIONS(wrlvl_sample), @@ -687,6 +690,7 @@ static void print_memctl_options(const memctl_options_t *popts) CTRL_OPTIONS(threeT_en), CTRL_OPTIONS(registered_dimm_en), CTRL_OPTIONS(ap_en), + CTRL_OPTIONS(x4_en), CTRL_OPTIONS(bstopre), CTRL_OPTIONS(wrlvl_override), CTRL_OPTIONS(wrlvl_sample), diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c index e958e13..56128a7 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c @@ -218,12 +218,16 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, if (dimm_params[i].n_ranks) { if (dimm_params[i].registered_dimm) { temp1 = 1; +#ifndef CONFIG_SPL_BUILD printf("Detected RDIMM %s\n", dimm_params[i].mpart); +#endif } else { temp2 = 1; +#ifndef CONFIG_SPL_BUILD printf("Detected UDIMM %s\n", dimm_params[i].mpart); +#endif } } } diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index 7a8636d..842bf19 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -25,10 +25,6 @@ void fsl_ddr_set_lawbar( unsigned int ctrl_num); void fsl_ddr_set_intl3r(const unsigned int granule_size); -/* processor specific function */ -extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, - unsigned int ctrl_num); - #if defined(SPD_EEPROM_ADDRESS) || \ defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) @@ -365,9 +361,11 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, { unsigned int i, j; unsigned long long total_mem = 0; + int assert_reset; fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg; common_timing_params_t *timing_params = pinfo->common_timing_params; + assert_reset = board_need_mem_reset(); /* data bus width capacity adjust shift amount */ unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS]; @@ -462,7 +460,20 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, timing_params[i].all_DIMMs_registered, &pinfo->memctl_opts[i], pinfo->dimm_params[i], i); + /* + * For RDIMMs, JEDEC spec requires clocks to be stable + * before reset signal is deasserted. For the boards + * using fixed parameters, this function should be + * be called from board init file. + */ + if (timing_params[i].all_DIMMs_registered) + assert_reset = 1; } + if (assert_reset) { + debug("Asserting mem reset\n"); + board_assert_mem_reset(); + } + case STEP_ASSIGN_ADDRESSES: /* STEP 5: Assign addresses to chip selects */ check_interleaving_options(pinfo); @@ -504,7 +515,13 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, fsl_ddr_cfg_regs_t *reg = &ddr_reg[i]; if (reg->cs[j].config & 0x80000000) { unsigned int end; - end = reg->cs[j].bnds & 0xFFF; + /* + * 0xfffffff is a special value we put + * for unused bnds + */ + if (reg->cs[j].bnds == 0xffffffff) + continue; + end = reg->cs[j].bnds & 0xffff; if (end > max_end) { max_end = end; } @@ -531,6 +548,7 @@ phys_size_t fsl_ddr_sdram(void) unsigned int law_memctl = LAW_TRGT_IF_DDR_1; unsigned long long total_memory; fsl_ddr_info_t info; + int deassert_reset; /* Reset info structure. */ memset(&info, 0, sizeof(fsl_ddr_info_t)); @@ -559,7 +577,21 @@ phys_size_t fsl_ddr_sdram(void) } } - /* Program configuration registers. */ + /* + * Program configuration registers. + * JEDEC specs requires clocks to be stable before deasserting reset + * for RDIMMs. Clocks start after chip select is enabled and clock + * control register is set. During step 1, all controllers have their + * registers set but not enabled. Step 2 proceeds after deasserting + * reset through board FPGA or GPIO. + * For non-registered DIMMs, initialization can go through but it is + * also OK to follow the same flow. + */ + deassert_reset = board_need_mem_reset(); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + if (info.common_timing_params[i].all_DIMMs_registered) + deassert_reset = 1; + } for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { debug("Programming controller %u\n", i); if (info.common_timing_params[i].ndimms_present == 0) { @@ -567,8 +599,22 @@ phys_size_t fsl_ddr_sdram(void) "skipping programming\n", i); continue; } - - fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i); + /* + * The following call with step = 1 returns before enabling + * the controller. It has to finish with step = 2 later. + */ + fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i, + deassert_reset ? 1 : 0); + } + if (deassert_reset) { + /* Use board FPGA or GPIO to deassert reset signal */ + debug("Deasserting mem reset\n"); + board_deassert_mem_reset(); + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + /* Call with step = 2 to continue initialization */ + fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), + i, 2); + } } /* program LAWs */ @@ -637,7 +683,8 @@ phys_size_t fsl_ddr_sdram(void) #if !defined(CONFIG_PHYS_64BIT) /* Check for 4G or more. Bad. */ if (total_memory >= (1ull << 32)) { - printf("Detected %lld MB of memory\n", total_memory >> 20); + puts("Detected "); + print_size(total_memory, " of memory\n"); printf(" This U-Boot only supports < 4G of DDR\n"); printf(" You could rebuild it with CONFIG_PHYS_64BIT\n"); printf(" "); /* re-align to match init_func_ram print */ diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c index 26369e0..30cdca4 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c @@ -700,6 +700,8 @@ unsigned int populate_memctl_options(int all_DIMMs_registered, } #endif + popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0; + /* Choose burst length. */ #if defined(CONFIG_FSL_DDR3) #if defined(CONFIG_E500MC) diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 89966e0..eb7cbbc 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -121,11 +121,8 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) { const char *modes[] = { "host", "peripheral", "otg" }; const char *phys[] = { "ulpi", "utmi" }; - const char *mode = NULL; - const char *phy_type = NULL; const char *dr_mode_type = NULL; const char *dr_phy_type = NULL; - char usb1_defined = 0; int usb_mode_off = -1; int usb_phy_off = -1; char str[5]; @@ -159,12 +156,6 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) dr_mode_type = modes[mode_idx]; dr_phy_type = phys[phy_idx]; - /* use usb_dr_mode and usb_phy_type if - usb1_defined = 0; these variables are to - be deprecated */ - if (!strcmp(str, "usb1")) - usb1_defined = 1; - if (mode_idx < 0 && phy_idx < 0) { printf("WARNING: invalid phy or mode\n"); return; @@ -183,19 +174,6 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) if (usb_phy_off < 0) return; } - - if (!usb1_defined) { - int usb_off = -1; - mode = getenv("usb_dr_mode"); - phy_type = getenv("usb_phy_type"); - if (mode || phy_type) { - printf("WARNING: usb_dr_mode and usb_phy_type " - "are to be deprecated soon. Use " - "hwconfig to set these values instead!!\n"); - fdt_fixup_usb_mode_phy_type(blob, mode, - phy_type, usb_off); - } - } } #endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */ diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index 89a561e..a401083 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -76,7 +76,8 @@ void disable_law(u8 idx) return; } -#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_NAND_SPL) && \ + (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL)) static int get_law_entry(u8 i, struct law_entry *e) { u32 lawar; @@ -106,7 +107,8 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) return idx; } -#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_NAND_SPL) && \ + (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL)) int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) { u32 idx; |