diff options
Diffstat (limited to 'arch/powerpc/include/asm')
| -rw-r--r-- | arch/powerpc/include/asm/fsl_ddr_dimm_params.h | 48 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/fsl_ddr_sdram.h | 28 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/immap_512x.h | 4 |
3 files changed, 40 insertions, 40 deletions
diff --git a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h index bd312ad..2cad6e2 100644 --- a/arch/powerpc/include/asm/fsl_ddr_dimm_params.h +++ b/arch/powerpc/include/asm/fsl_ddr_dimm_params.h @@ -45,48 +45,48 @@ typedef struct dimm_params_s { unsigned int mtb_ps; /* medium timebase ps, only for ddr3 */ unsigned int ftb_10th_ps; /* fine timebase, in 1/10 ps, only for ddr3 */ - unsigned int tAA_ps; /* minimum CAS latency time, only for ddr3 */ - unsigned int tFAW_ps; /* four active window delay, only for ddr3 */ + unsigned int taa_ps; /* minimum CAS latency time, only for ddr3 */ + unsigned int tfaw_ps; /* four active window delay, only for ddr3 */ /* * SDRAM clock periods * The range for these are 1000-10000 so a short should be sufficient */ - unsigned int tCKmin_X_ps; - unsigned int tCKmin_X_minus_1_ps; - unsigned int tCKmin_X_minus_2_ps; - unsigned int tCKmax_ps; + unsigned int tckmin_x_ps; + unsigned int tckmin_x_minus_1_ps; + unsigned int tckmin_x_minus_2_ps; + unsigned int tckmax_ps; /* SPD-defined CAS latencies */ - unsigned int caslat_X; - unsigned int caslat_X_minus_1; - unsigned int caslat_X_minus_2; + unsigned int caslat_x; + unsigned int caslat_x_minus_1; + unsigned int caslat_x_minus_2; unsigned int caslat_lowest_derated; /* Derated CAS latency */ /* basic timing parameters */ - unsigned int tRCD_ps; - unsigned int tRP_ps; - unsigned int tRAS_ps; + unsigned int trcd_ps; + unsigned int trp_ps; + unsigned int tras_ps; - unsigned int tWR_ps; /* maximum = 63750 ps */ - unsigned int tWTR_ps; /* maximum = 63750 ps */ - unsigned int tRFC_ps; /* max = 255 ns + 256 ns + .75 ns + unsigned int twr_ps; /* maximum = 63750 ps */ + unsigned int twtr_ps; /* maximum = 63750 ps */ + unsigned int trfc_ps; /* max = 255 ns + 256 ns + .75 ns = 511750 ps */ - unsigned int tRRD_ps; /* maximum = 63750 ps */ - unsigned int tRC_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ + unsigned int trrd_ps; /* maximum = 63750 ps */ + unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ unsigned int refresh_rate_ps; /* DDR3 doesn't need these as below */ - unsigned int tIS_ps; /* byte 32, spd->ca_setup */ - unsigned int tIH_ps; /* byte 33, spd->ca_hold */ - unsigned int tDS_ps; /* byte 34, spd->data_setup */ - unsigned int tDH_ps; /* byte 35, spd->data_hold */ - unsigned int tRTP_ps; /* byte 38, spd->trtp */ - unsigned int tDQSQ_max_ps; /* byte 44, spd->tdqsq */ - unsigned int tQHS_ps; /* byte 45, spd->tqhs */ + unsigned int tis_ps; /* byte 32, spd->ca_setup */ + unsigned int tih_ps; /* byte 33, spd->ca_hold */ + unsigned int tds_ps; /* byte 34, spd->data_setup */ + unsigned int tdh_ps; /* byte 35, spd->data_hold */ + unsigned int trtp_ps; /* byte 38, spd->trtp */ + unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ + unsigned int tqhs_ps; /* byte 45, spd->tqhs */ /* DDR3 RDIMM */ unsigned char rcw[16]; /* Register Control Word 0-15 */ diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index f4eec82..2c3c514 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -219,13 +219,13 @@ typedef struct fsl_ddr_cfg_regs_s { } fsl_ddr_cfg_regs_t; typedef struct memctl_options_partial_s { - unsigned int all_DIMMs_ECC_capable; - unsigned int all_DIMMs_tCKmax_ps; - unsigned int all_DIMMs_burst_lengths_bitmask; - unsigned int all_DIMMs_registered; - unsigned int all_DIMMs_unbuffered; + unsigned int all_dimms_ecc_capable; + unsigned int all_dimms_tckmax_ps; + unsigned int all_dimms_burst_lengths_bitmask; + unsigned int all_dimms_registered; + unsigned int all_dimms_unbuffered; /* unsigned int lowest_common_SPD_caslat; */ - unsigned int all_DIMMs_minimum_tRCD_ps; + unsigned int all_dimms_minimum_trcd_ps; } memctl_options_partial_t; #define DDR_DATA_BUS_WIDTH_64 0 @@ -261,10 +261,10 @@ typedef struct memctl_options_s { unsigned int addr_hash; /* Operational mode parameters */ - unsigned int ECC_mode; /* Use ECC? */ + unsigned int ecc_mode; /* Use ECC? */ /* Initialize ECC using memory controller? */ - unsigned int ECC_init_using_memctl; - unsigned int DQS_config; /* Use DQS? maybe only with DDR2? */ + unsigned int ecc_init_using_memctl; + unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ /* SREN - self-refresh during sleep */ unsigned int self_refresh_in_sleep; unsigned int dynamic_power; /* DYN_PWR */ @@ -272,7 +272,7 @@ typedef struct memctl_options_s { unsigned int data_bus_width; unsigned int burst_length; /* BL4, OTF and BL8 */ /* On-The-Fly Burst Chop enable */ - unsigned int OTF_burst_chop_en; + unsigned int otf_burst_chop_en; /* mirrior DIMMs for DDR3 */ unsigned int mirrored_dimm; unsigned int quad_rank_present; @@ -297,11 +297,11 @@ typedef struct memctl_options_s { unsigned int wrlvl_ctl_3; unsigned int half_strength_driver_enable; - unsigned int twoT_en; - unsigned int threeT_en; + unsigned int twot_en; + unsigned int threet_en; unsigned int bstopre; - unsigned int tCKE_clock_pulse_width_ps; /* tCKE */ - unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */ + unsigned int tcke_clock_pulse_width_ps; /* tCKE */ + unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */ /* Rtt impedance */ unsigned int rtt_override; /* rtt_override enable */ diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h index 01c9eff..814a535 100644 --- a/arch/powerpc/include/asm/immap_512x.h +++ b/arch/powerpc/include/asm/immap_512x.h @@ -279,8 +279,8 @@ typedef struct ddr512x { u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */ u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */ u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */ - u32 DQS_config_offset_count; /* DQS Config Offset Count */ - u32 DQS_config_offset_time; /* DQS Config Offset Time */ + u32 dqs_config_offset_count; /* DQS Config Offset Count */ + u32 dqs_config_offset_time; /* DQS Config Offset Time */ u32 DQS_delay_status; /* DQS Delay Status */ u32 res0[0xF]; u32 prioman_config1; /* Priority Manager Configuration */ |