diff options
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 82 | ||||
-rw-r--r-- | arch/powerpc/include/asm/fsl_law.h | 2 | ||||
-rw-r--r-- | arch/powerpc/include/asm/fsl_secure_boot.h | 10 | ||||
-rw-r--r-- | arch/powerpc/include/asm/fsl_serdes.h | 8 | ||||
-rw-r--r-- | arch/powerpc/include/asm/global_data.h | 6 | ||||
-rw-r--r-- | arch/powerpc/include/asm/immap_512x.h | 2 | ||||
-rw-r--r-- | arch/powerpc/include/asm/immap_8220.h | 246 | ||||
-rw-r--r-- | arch/powerpc/include/asm/immap_85xx.h | 95 | ||||
-rw-r--r-- | arch/powerpc/include/asm/processor.h | 28 | ||||
-rw-r--r-- | arch/powerpc/include/asm/u-boot.h | 8 |
10 files changed, 164 insertions, 323 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7267611..1009a31 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -512,23 +512,34 @@ #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" -#elif defined(CONFIG_PPC_T4240) +#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#ifdef CONFIG_PPC_T4240 #define CONFIG_MAX_CPUS 12 +#define CONFIG_SYS_NUM_FM1_DTSEC 8 +#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CONFIG_SYS_NUM_FM2_DTSEC 8 +#define CONFIG_SYS_NUM_FM2_10GEC 2 +#define CONFIG_NUM_DDR_CONTROLLERS 3 +#else +#define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_NUM_FM1_DTSEC 7 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_SYS_NUM_FM2_DTSEC 7 +#define CONFIG_SYS_NUM_FM2_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SRDS_3 #define CONFIG_SYS_FSL_SRDS_4 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 2 -#define CONFIG_SYS_NUM_FM1_DTSEC 8 -#define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_NUM_FM2_DTSEC 8 -#define CONFIG_SYS_NUM_FM2_10GEC 2 -#define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 @@ -537,26 +548,23 @@ #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_ERRATUM_A004468 #define CONFIG_SYS_FSL_ERRATUM_A_004934 #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_PCI_VER_3_X -#elif defined(CONFIG_PPC_B4420) +#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) +#define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ -#define CONFIG_MAX_CPUS 2 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 4 -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 @@ -567,30 +575,50 @@ #define CONFIG_SYS_FSL_ERRATUM_A005871 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 -#elif defined(CONFIG_PPC_B4860) -#define CONFIG_SYS_PPC64 /* 64-bit core */ +#ifdef CONFIG_PPC_B4860 +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 +#define CONFIG_SYS_NUM_FM1_DTSEC 6 +#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#else +#define CONFIG_MAX_CPUS 2 +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 +#define CONFIG_SYS_NUM_FM1_DTSEC 4 +#define CONFIG_SYS_NUM_FM1_10GEC 0 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#endif + +#elif defined(CONFIG_PPC_T1040) +#define CONFIG_E5500 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ #define CONFIG_MAX_CPUS 4 -#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 -#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 5 +#define CONFIG_SYS_FSL_NUM_LAWS 16 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 6 -#define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FMAN_V3 -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 -#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE -#define CONFIG_SYS_FSL_ERRATUM_A_004934 -#define CONFIG_SYS_FSL_ERRATUM_A005871 +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 #else @@ -601,4 +629,10 @@ #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." #endif +#ifdef CONFIG_E6500 +#define CONFIG_SYS_FSL_THREADS_PER_CORE 2 +#else +#define CONFIG_SYS_FSL_THREADS_PER_CORE 1 +#endif + #endif /* _ASM_MPC85xx_CONFIG_H_ */ diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index f9cec8e..90b264d 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -70,6 +70,8 @@ enum law_trgt_if { LAW_TRGT_IF_DCSR = 0x1d, LAW_TRGT_IF_LBC = 0x1f, LAW_TRGT_IF_QMAN = 0x3c, + + LAW_TRGT_IF_MAPLE = 0x50, }; #define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1 #define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index d1c1967..2bc6ed1 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -23,16 +23,6 @@ #ifndef __FSL_SECURE_BOOT_H #define __FSL_SECURE_BOOT_H -/* Starting TLB number for the TLB entried for 3.5 G space created by ISBC */ -#if defined(CONFIG_FSL_CORENET) -#define CONFIG_SYS_ISBC_START_TLB 3 -#else -#define CONFIG_SYS_ISBC_START_TLB 0 -#endif - -/* Number fo TLB's created by ISBC */ -#define CONFIG_SYS_ISBC_NUM_TLBS 5 - #if defined(CONFIG_FSL_CORENET) #define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000 #else diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 6cd7379..ccb91fb 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -80,6 +80,14 @@ enum srds_prtcl { XFI_FM2_MAC9, XFI_FM2_MAC10, INTERLAKEN, + SGMII_SW1_DTSEC1, /* SW indicates on L2 switch */ + SGMII_SW1_DTSEC2, + SGMII_SW1_DTSEC3, + SGMII_SW1_DTSEC4, + SGMII_SW1_DTSEC5, + SGMII_SW1_DTSEC6, + QSGMII_SW1_A, /* SW indicates on L2 swtich */ + QSGMII_SW1_B, }; enum srds { diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index d5db854..c02447f 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -104,12 +104,6 @@ struct arch_global_data { u32 ips_clk; u32 csb_clk; #endif /* CONFIG_MPC512X */ -#if defined(CONFIG_MPC8220) - unsigned long inp_clk; - unsigned long vco_clk; - unsigned long pev_clk; - unsigned long flb_clk; -#endif unsigned long reset_status; /* reset status register at boot */ #if defined(CONFIG_MPC83xx) unsigned long arbiter_event_attributes; diff --git a/arch/powerpc/include/asm/immap_512x.h b/arch/powerpc/include/asm/immap_512x.h index d96e536..8248219 100644 --- a/arch/powerpc/include/asm/immap_512x.h +++ b/arch/powerpc/include/asm/immap_512x.h @@ -1272,4 +1272,6 @@ static inline u32 get_pata_base (void) #define CONFIG_SYS_MPC512x_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET) +#define IIM_BASE_ADDR (CONFIG_SYS_IMMR + offsetof(immap_t, iim)) + #endif /* __IMMAP_512x__ */ diff --git a/arch/powerpc/include/asm/immap_8220.h b/arch/powerpc/include/asm/immap_8220.h deleted file mode 100644 index f9595f4..0000000 --- a/arch/powerpc/include/asm/immap_8220.h +++ /dev/null @@ -1,246 +0,0 @@ -/* - * MPC8220 Internal Memory Map - * Copyright (c) 2004 TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * The Internal Memory Map of the 8220. - * - */ -#ifndef __IMMAP_MPC8220__ -#define __IMMAP_MPC8220__ - -/* - * System configuration registers. - */ -typedef struct sys_conf { - u16 mbar; /* 0x00 */ - u16 res1; - - u16 res2; /* 0x04 */ - u16 sdramds; - - u32 res3[6]; /* 0x08 */ - - u32 cscfg[6]; /* 0x20 */ - - u32 res4[2]; /* 0x38 */ - - u8 res5[3]; /* 0x40 */ - u8 rstctrl; - - u8 res6[3]; /* 0x44 */ - u8 rststat; - - u32 res7[2]; /* 0x48 */ - - u32 jtagid; /* 0x50 */ -} sysconf8220_t; - - -/* - * Memory controller registers. - */ -typedef struct mem_ctlr { - ushort mode; /* 0x100 */ - ushort res1; - u32 ctrl; /* 0x104 */ - u32 cfg1; /* 0x108 */ - u32 cfg2; /* 0x10c */ -} memctl8220_t; - -/* - * XLB Arbitration registers - */ -typedef struct xlb_arb -{ - uint res1[16]; /* 0x200 */ - uint config; /* 0x240 */ - uint version; /* 0x244 */ - uint status; /* 0x248 */ - uint intEnable; /* 0x24c */ - uint addrCap; /* 0x250 */ - uint busSigCap; /* 0x254 */ - uint addrTenTimeOut; /* 0x258 */ - uint dataTenTimeOut; /* 0x25c */ - uint busActTimeOut; /* 0x260 */ - uint mastPriEn; /* 0x264 */ - uint mastPriority; /* 0x268 */ - uint baseAddr; /* 0x26c */ -} xlbarb8220_t; - -/* - * Flexbus registers - */ -typedef struct flexbus -{ - ushort csar0; /* 0x00 */ - ushort res1; - uint csmr0; /* 0x04 */ - uint cscr0; /* 0x08 */ - - ushort csar1; /* 0x0c */ - ushort res2; - uint csmr1; /* 0x10 */ - uint cscr1; /* 0x14 */ - - ushort csar2; /* 0x18 */ - ushort res3; - uint csmr2; /* 0x1c */ - uint cscr2; /* 0x20 */ - - ushort csar3; /* 0x24 */ - ushort res4; - uint csmr3; /* 0x28 */ - uint cscr3; /* 0x2c */ - - ushort csar4; /* 0x30 */ - ushort res5; - uint csmr4; /* 0x34 */ - uint cscr4; /* 0x38 */ - - ushort csar5; /* 0x3c */ - ushort res6; - uint csmr5; /* 0x40 */ - uint cscr5; /* 0x44 */ -} flexbus8220_t; - -/* - * GPIO registers - */ -typedef struct gpio -{ - u32 out; /* 0x00 */ - u32 obs; /* 0x04 */ - u32 obc; /* 0x08 */ - u32 obt; /* 0x0c */ - u32 en; /* 0x10 */ - u32 ebs; /* 0x14 */ - u32 ebc; /* 0x18 */ - u32 ebt; /* 0x1c */ - u32 mc; /* 0x20 */ - u32 st; /* 0x24 */ - u32 intr; /* 0x28 */ -} gpio8220_t; - -/* - * General Purpose Timer registers - */ -typedef struct gptimer -{ - u8 OCPW; - u8 OctIct; - u8 Control; - u8 Mode; - - u16 Prescl; /* Prescale */ - u16 Count; /* Count */ - - u16 PwmWid; /* PWM Width */ - u8 PwmOp; /* Output Polarity */ - u8 PwmLd; /* Immediate Update */ - - u16 Capture; /* Capture internal counter */ - u8 OvfPin; /* Ovf and Pin */ - u8 Int; /* Interrupts */ -} gptmr8220_t; - -/* - * PSC registers - */ -typedef struct psc -{ - u32 mr1_2; /* 0x00 Mode reg 1 & 2 */ - u32 sr_csr; /* 0x04 Status/Clock Select reg */ - u32 cr; /* 0x08 Command reg */ - u8 xmitbuf[4]; /* 0x0c Receive/Transmit Buffer */ - u32 ipcr_acr; /* 0x10 Input Port Change/Auxiliary Control reg */ - u32 isr_imr; /* 0x14 Interrupt Status/Mask reg */ - u32 ctur; /* 0x18 Counter Timer Upper reg */ - u32 ctlr; /* 0x1c Counter Timer Lower reg */ - u32 rsvd1[4]; /* 0x20 ... 0x2c */ - u32 ivr; /* 0x30 Interrupt Vector reg */ - u32 ipr; /* 0x34 Input Port reg */ - u32 opsetr; /* 0x38 Output Port Set reg */ - u32 opresetr; /* 0x3c Output Port Reset reg */ - u32 sicr; /* 0x40 PSC/IrDA control reg */ - u32 ircr1; /* 0x44 IrDA control reg 1*/ - u32 ircr2; /* 0x48 IrDA control reg 2*/ - u32 irsdr; /* 0x4c IrDA SIR Divide reg */ - u32 irmdr; /* 0x50 IrDA MIR Divide reg */ - u32 irfdr; /* 0x54 PSC IrDA FIR Divide reg */ - u32 rfnum; /* 0x58 RX-FIFO counter */ - u32 txnum; /* 0x5c TX-FIFO counter */ - u32 rfdata; /* 0x60 RX-FIFO data */ - u32 rfstat; /* 0x64 RX-FIFO status */ - u32 rfcntl; /* 0x68 RX-FIFO control */ - u32 rfalarm; /* 0x6c RX-FIFO alarm */ - u32 rfrptr; /* 0x70 RX-FIFO read pointer */ - u32 rfwptr; /* 0x74 RX-FIFO write pointer */ - u32 rflfrptr; /* 0x78 RX-FIFO last read frame pointer */ - u32 rflfwptr; /* 0x7c RX-FIFO last write frame pointer */ - - u32 tfdata; /* 0x80 TX-FIFO data */ - u32 tfstat; /* 0x84 TX-FIFO status */ - u32 tfcntl; /* 0x88 TX-FIFO control */ - u32 tfalarm; /* 0x8c TX-FIFO alarm */ - u32 tfrptr; /* 0x90 TX-FIFO read pointer */ - u32 tfwptr; /* 0x94 TX-FIFO write pointer */ - u32 tflfrptr; /* 0x98 TX-FIFO last read frame pointer */ - u32 tflfwptr; /* 0x9c TX-FIFO last write frame pointer */ -} psc8220_t; - -/* - * Interrupt Controller registers - */ -typedef struct interrupt_controller { -} intctl8220_t; - - -/* Fast controllers -*/ - -/* - * I2C registers - */ -typedef struct i2c -{ - u8 adr; /* 0x00 */ - u8 res1[3]; - u8 fdr; /* 0x04 */ - u8 res2[3]; - u8 cr; /* 0x08 */ - u8 res3[3]; - u8 sr; /* 0x0C */ - u8 res4[3]; - u8 dr; /* 0x10 */ - u8 res5[3]; - u32 reserved0; /* 0x14 */ - u32 reserved1; /* 0x18 */ - u32 reserved2; /* 0x1c */ - u8 icr; /* 0x20 */ - u8 res6[3]; -} i2c8220_t; - -/* - * Port Configuration Registers - */ -typedef struct pcfg -{ - uint pcfg0; /* 0x00 */ - uint pcfg1; /* 0x04 */ - uint pcfg2; /* 0x08 */ - uint pcfg3; /* 0x0c */ -} pcfg8220_t; - -/* ...and the whole thing wrapped up.... -*/ -typedef struct immap { - sysconf8220_t im_sysconf; /* System Configuration */ - memctl8220_t im_memctl; /* Memory Controller */ - xlbarb8220_t im_xlbarb; /* XLB Arbitration */ - psc8220_t im_psc; /* PSC controller */ - flexbus8220_t im_fb; /* FlexBus Controller */ - i2c8220_t im_i2c; /* I2C control/status */ - pcfg8220_t im_pcfg; /* Port configuration */ -} immap_t; - -#endif /* __IMMAP_MPC8220__ */ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index baaa9fe..4052037 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1676,18 +1676,17 @@ typedef struct cpc_corenet { /* Global Utilities Block */ #ifdef CONFIG_FSL_CORENET typedef struct ccsr_gur { - u32 porsr1; /* POR status */ - u8 res1[28]; + u32 porsr1; /* POR status 1 */ + u32 porsr2; /* POR status 2 */ + u8 res_008[0x20-0x8]; u32 gpporcr1; /* General-purpose POR configuration */ - u8 res2[12]; - u32 gpiocr; /* GPIO control */ - u8 res3[12]; - u32 gpoutdr; /* General-purpose output data */ - u8 res4[12]; - u32 gpindr; /* General-purpose input data */ - u8 res5[12]; - u32 alt_pmuxcr; /* Alt function signal multiplex control */ - u8 res6[12]; + u32 gpporcr2; /* General-purpose POR configuration 2 */ + u32 dcfg_fusesr; /* Fuse status register */ +#define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25 +#define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F +#define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20 +#define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F + u8 res_02c[0x70-0x2c]; u32 devdisr; /* Device disable control */ u32 devdisr2; /* Device disable control 2 */ u32 devdisr3; /* Device disable control 3 */ @@ -1831,7 +1830,7 @@ typedef struct ccsr_gur { #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#if defined(CONFIG_PPC_T4240) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1845,6 +1844,11 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 +#elif defined(CONFIG_PPC_T1040) +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 #endif #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000 @@ -1899,7 +1903,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_T4240) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 @@ -1992,6 +1996,7 @@ typedef struct ccsr_gur { #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ +#define TP_INIT_PER_CLUSTER 4 #define FSL_CORENET_DCSR_SZ_MASK 0x00000003 #define FSL_CORENET_DCSR_SZ_4M 0x0 @@ -2004,22 +2009,13 @@ typedef struct ccsr_gur { #define rmuliodnr rio1maintliodnr typedef struct ccsr_clk { - u32 clkc0csr; /* 0x000 Core 0 Clock control/status */ - u8 res1[0x1c]; - u32 clkc1csr; /* 0x020 Core 1 Clock control/status */ - u8 res2[0x1c]; - u32 clkc2csr; /* 0x040 Core 2 Clock control/status */ - u8 res3[0x1c]; - u32 clkc3csr; /* 0x060 Core 3 Clock control/status */ - u8 res4[0x1c]; - u32 clkc4csr; /* 0x080 Core 4 Clock control/status */ - u8 res5[0x1c]; - u32 clkc5csr; /* 0x0a0 Core 5 Clock control/status */ - u8 res6[0x1c]; - u32 clkc6csr; /* 0x0c0 Core 6 Clock control/status */ - u8 res7[0x1c]; - u32 clkc7csr; /* 0x0e0 Core 7 Clock control/status */ - u8 res8[0x71c]; + struct { + u32 clkcncsr; /* core cluster n clock control status */ + u8 res_004[0x0c]; + u32 clkcgnhwacsr;/* clock generator n hardware accelerator */ + u8 res_014[0x0c]; + } clkcsr[8]; + u8 res_100[0x700]; /* 0x100 */ u32 pllc1gsr; /* 0x800 Cluster PLL 1 General Status */ u8 res10[0x1c]; u32 pllc2gsr; /* 0x820 Cluster PLL 2 General Status */ @@ -2829,12 +2825,53 @@ typedef struct ccsr_pme { u8 res4[0x400]; } ccsr_pme_t; +#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE +struct ccsr_usb_port_ctrl { + u32 ctrl; + u32 drvvbuscfg; + u32 pwrfltcfg; + u32 sts; + u8 res_14[0xc]; + u32 bistcfg; + u32 biststs; + u32 abistcfg; + u32 abiststs; + u8 res_30[0x10]; + u32 xcvrprg; + u32 anaprg; + u32 anadrv; + u32 anasts; +}; + +typedef struct ccsr_usb_phy { + u32 id; + struct ccsr_usb_port_ctrl port1; + u8 res_50[0xc]; + u32 tvr; + u32 pllprg[4]; + u8 res_70[0x4]; + u32 anaccfg; + u32 dbg; + u8 res_7c[0x4]; + struct ccsr_usb_port_ctrl port2; + u8 res_dc[0x334]; +} ccsr_usb_phy_t; + +#define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0) +#define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1) +#define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1) +#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0) +#define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1) +#define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16) +#define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21) +#else typedef struct ccsr_usb_phy { u8 res0[0x18]; u32 usb_enable_override; u8 res[0xe4]; } ccsr_usb_phy_t; #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 +#endif #ifdef CONFIG_SYS_FSL_RAID_ENGINE struct ccsr_raide { diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 8c91f08..56b22d8 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -507,6 +507,15 @@ #define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */ #define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */ #define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */ + +/* e6500 */ +#define L2CSR0_L2REP_SPLRUAGE 0x00000000 /* L2REP Streaming PLRU with Aging */ +#define L2CSR0_L2REP_FIFO 0x00001000 /* L2REP FIFO */ +#define L2CSR0_L2REP_SPLRU 0x00002000 /* L2REP Streaming PLRU */ +#define L2CSR0_L2REP_PLRU 0x00003000 /* L2REP PLRU */ + +#define L2CSR0_L2REP_MODE L2CSR0_L2REP_SPLRUAGE + #define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */ #define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */ #define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ @@ -575,6 +584,16 @@ #define SPRN_MSSSR0 0x3f7 #endif +#define SPRN_HDBCR0 0x3d0 +#define SPRN_HDBCR1 0x3d1 +#define SPRN_HDBCR2 0x3d2 +#define SPRN_HDBCR3 0x3d3 +#define SPRN_HDBCR4 0x3d4 +#define SPRN_HDBCR5 0x3d5 +#define SPRN_HDBCR6 0x3d6 +#define SPRN_HDBCR7 0x277 +#define SPRN_HDBCR8 0x278 + /* Short-hand versions for a number of the above SPRNs */ #define CTR SPRN_CTR /* Counter Register */ @@ -1099,6 +1118,7 @@ #define SVR_P5040 0x820400 #define SVR_T4240 0x824000 #define SVR_T4120 0x824001 +#define SVR_T4160 0x824100 #define SVR_B4860 0X868000 #define SVR_G4860 0x868001 #define SVR_G4060 0x868003 @@ -1106,6 +1126,12 @@ #define SVR_G4440 0x868101 #define SVR_B4420 0x868102 #define SVR_B4220 0x868103 +#define SVR_T1040 0x852000 +#define SVR_T1041 0x852001 +#define SVR_T1042 0x852002 +#define SVR_T1020 0x852100 +#define SVR_T1021 0x852101 +#define SVR_T1022 0x852102 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 @@ -1174,6 +1200,8 @@ struct cpu_type { struct cpu_type *identify_cpu(u32 ver); int fixup_cpu(void); +int fsl_qoriq_core_to_cluster(unsigned int core); + #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define CPU_TYPE_ENTRY(n, v, nc) \ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \ diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index cf972d2..93496a0 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -59,14 +59,6 @@ typedef struct bd_info { #if defined(CONFIG_MPC83xx) unsigned long bi_immrbar; #endif -#if defined(CONFIG_MPC8220) - unsigned long bi_mbar_base; /* base of internal registers */ - unsigned long bi_inpfreq; /* Input Freq, In MHz */ - unsigned long bi_pcifreq; /* PCI Freq, in MHz */ - unsigned long bi_pevfreq; /* PEV Freq, in MHz */ - unsigned long bi_flbfreq; /* Flexbus Freq, in MHz */ - unsigned long bi_vcofreq; /* VCO Freq, in MHz */ -#endif unsigned long bi_bootflags; /* boot / reboot flag (Unused) */ unsigned long bi_ip_addr; /* IP Address */ unsigned char bi_enetaddr[6]; /* OLD: see README.enetaddr */ |