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-rw-r--r--arch/x86/include/asm/arch-ivybridge/mrccache.h51
-rw-r--r--arch/x86/include/asm/arch-queensbay/tnc.h5
-rw-r--r--arch/x86/include/asm/e820.h3
-rw-r--r--arch/x86/include/asm/mrccache.h107
-rw-r--r--arch/x86/include/asm/smbios.h236
-rw-r--r--arch/x86/include/asm/zimage.h3
6 files changed, 351 insertions, 54 deletions
diff --git a/arch/x86/include/asm/arch-ivybridge/mrccache.h b/arch/x86/include/asm/arch-ivybridge/mrccache.h
deleted file mode 100644
index 1d50ebb..0000000
--- a/arch/x86/include/asm/arch-ivybridge/mrccache.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2014 Google, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_MRCCACHE_H
-#define _ASM_ARCH_MRCCACHE_H
-
-#define MRC_DATA_ALIGN 0x1000
-#define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | ('C' << 16) | \
- ('D'<<24))
-
-__packed struct mrc_data_container {
- u32 signature; /* "MRCD" */
- u32 data_size; /* Size of the 'data' field */
- u32 checksum; /* IP style checksum */
- u32 reserved; /* For header alignment */
- u8 data[0]; /* Variable size, platform/run time dependent */
-};
-
-struct fmap_entry;
-struct udevice;
-
-/**
- * mrccache_find_current() - find the latest MRC cache record
- *
- * This searches the MRC cache region looking for the latest record to use
- * for setting up SDRAM
- *
- * @entry: Information about the position and size of the MRC cache
- * @return pointer to latest record, or NULL if none
- */
-struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry);
-
-/**
- * mrccache_update() - update the MRC cache with a new record
- *
- * This writes a new record to the end of the MRC cache. If the new record is
- * the same as the latest record then the write is skipped
- *
- * @sf: SPI flash to write to
- * @entry: Position and size of MRC cache in SPI flash
- * @cur: Record to write
- * @return 0 if updated, -EEXIST if the record is the same as the latest
- * record, other error if SPI write failed
- */
-int mrccache_update(struct udevice *sf, struct fmap_entry *entry,
- struct mrc_data_container *cur);
-
-#endif
diff --git a/arch/x86/include/asm/arch-queensbay/tnc.h b/arch/x86/include/asm/arch-queensbay/tnc.h
index ad9a6c4..2365394 100644
--- a/arch/x86/include/asm/arch-queensbay/tnc.h
+++ b/arch/x86/include/asm/arch-queensbay/tnc.h
@@ -7,6 +7,11 @@
#ifndef _X86_ARCH_TNC_H_
#define _X86_ARCH_TNC_H_
+/* IGD Control Register */
+#define IGD_GC 0x50
+#define VGA_DISABLE 0x00020000
+#define GMS_MASK 0x00700000
+
/* Memory BAR Enable */
#define MEM_BAR_EN 0x00000001
diff --git a/arch/x86/include/asm/e820.h b/arch/x86/include/asm/e820.h
index 21bc633..351f021 100644
--- a/arch/x86/include/asm/e820.h
+++ b/arch/x86/include/asm/e820.h
@@ -23,4 +23,7 @@ struct e820entry {
#endif /* __ASSEMBLY__ */
+/* Implementation defined function to install an e820 map */
+unsigned install_e820_map(unsigned max_entries, struct e820entry *);
+
#endif /* _ASM_X86_E820_H */
diff --git a/arch/x86/include/asm/mrccache.h b/arch/x86/include/asm/mrccache.h
new file mode 100644
index 0000000..e35b5ed
--- /dev/null
+++ b/arch/x86/include/asm/mrccache.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ * Copyright (C) 2015 Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_MRCCACHE_H
+#define _ASM_MRCCACHE_H
+
+#define MRC_DATA_ALIGN 0x1000
+#define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | \
+ ('C' << 16) | ('D'<<24))
+
+#define MRC_DATA_HEADER_SIZE 32
+
+struct __packed mrc_data_container {
+ u32 signature; /* "MRCD" */
+ u32 data_size; /* Size of the 'data' field */
+ u32 checksum; /* IP style checksum */
+ u32 reserved; /* For header alignment */
+ u8 data[0]; /* Variable size, platform/run time dependent */
+};
+
+struct mrc_region {
+ u32 base;
+ u32 offset;
+ u32 length;
+};
+
+struct udevice;
+
+/**
+ * mrccache_find_current() - find the latest MRC cache record
+ *
+ * This searches the MRC cache region looking for the latest record to use
+ * for setting up SDRAM
+ *
+ * @entry: Position and size of MRC cache in SPI flash
+ * @return pointer to latest record, or NULL if none
+ */
+struct mrc_data_container *mrccache_find_current(struct mrc_region *entry);
+
+/**
+ * mrccache_update() - update the MRC cache with a new record
+ *
+ * This writes a new record to the end of the MRC cache region. If the new
+ * record is the same as the latest record then the write is skipped
+ *
+ * @sf: SPI flash to write to
+ * @entry: Position and size of MRC cache in SPI flash
+ * @cur: Record to write
+ * @return 0 if updated, -EEXIST if the record is the same as the latest
+ * record, -EINVAL if the record is not valid, other error if SPI write failed
+ */
+int mrccache_update(struct udevice *sf, struct mrc_region *entry,
+ struct mrc_data_container *cur);
+
+/**
+ * mrccache_reserve() - reserve MRC data on the stack
+ *
+ * This copies MRC data pointed by gd->arch.mrc_output to a new place on the
+ * stack with length gd->arch.mrc_output_len, and updates gd->arch.mrc_output
+ * to point to the new place once the migration is done.
+ *
+ * This routine should be called by reserve_arch() before U-Boot is relocated
+ * when MRC cache is enabled.
+ *
+ * @return 0 always
+ */
+int mrccache_reserve(void);
+
+/**
+ * mrccache_get_region() - get MRC region on the SPI flash
+ *
+ * This gets MRC region whose offset and size are described in the device tree
+ * as a subnode to the SPI flash. If a non-NULL device pointer is supplied,
+ * this also probes the SPI flash device and returns its device pointer for
+ * the caller to use later.
+ *
+ * Be careful when calling this routine with a non-NULL device pointer:
+ * - driver model initialization must be complete
+ * - calling in the pre-relocation phase may bring some side effects during
+ * the SPI flash device probe (eg: for SPI controllers on a PCI bus, it
+ * triggers PCI bus enumeration during which insufficient memory issue
+ * might be exposed and it causes subsequent SPI flash probe fails).
+ *
+ * @devp: Returns pointer to the SPI flash device
+ * @entry: Position and size of MRC cache in SPI flash
+ * @return 0 if success, -ENOENT if SPI flash node does not exist in the
+ * device tree, -EPERM if MRC region subnode does not exist in the device
+ * tree, -EINVAL if MRC region properties format is incorrect, other error
+ * if SPI flash probe failed.
+ */
+int mrccache_get_region(struct udevice **devp, struct mrc_region *entry);
+
+/**
+ * mrccache_save() - save MRC data to the SPI flash
+ *
+ * This saves MRC data stored previously by gd->arch.mrc_output to a proper
+ * place within the MRC region on the SPI flash.
+ *
+ * @return 0 if saved to SPI flash successfully, other error if failed
+ */
+int mrccache_save(void);
+
+#endif /* _ASM_MRCCACHE_H */
diff --git a/arch/x86/include/asm/smbios.h b/arch/x86/include/asm/smbios.h
new file mode 100644
index 0000000..623a703
--- /dev/null
+++ b/arch/x86/include/asm/smbios.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Adapted from coreboot src/include/smbios.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _SMBIOS_H_
+#define _SMBIOS_H_
+
+/* SMBIOS spec version implemented */
+#define SMBIOS_MAJOR_VER 3
+#define SMBIOS_MINOR_VER 0
+
+/* SMBIOS structure types */
+enum {
+ SMBIOS_BIOS_INFORMATION = 0,
+ SMBIOS_SYSTEM_INFORMATION = 1,
+ SMBIOS_BOARD_INFORMATION = 2,
+ SMBIOS_SYSTEM_ENCLOSURE = 3,
+ SMBIOS_PROCESSOR_INFORMATION = 4,
+ SMBIOS_CACHE_INFORMATION = 7,
+ SMBIOS_SYSTEM_SLOTS = 9,
+ SMBIOS_PHYS_MEMORY_ARRAY = 16,
+ SMBIOS_MEMORY_DEVICE = 17,
+ SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS = 19,
+ SMBIOS_SYSTEM_BOOT_INFORMATION = 32,
+ SMBIOS_END_OF_TABLE = 127
+};
+
+#define SMBIOS_INTERMEDIATE_OFFSET 16
+#define SMBIOS_STRUCT_EOS_BYTES 2
+
+struct __packed smbios_entry {
+ u8 anchor[4];
+ u8 checksum;
+ u8 length;
+ u8 major_ver;
+ u8 minor_ver;
+ u16 max_struct_size;
+ u8 entry_point_rev;
+ u8 formatted_area[5];
+ u8 intermediate_anchor[5];
+ u8 intermediate_checksum;
+ u16 struct_table_length;
+ u32 struct_table_address;
+ u16 struct_count;
+ u8 bcd_rev;
+};
+
+/* BIOS characteristics */
+#define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7)
+#define BIOS_CHARACTERISTICS_UPGRADEABLE (1 << 11)
+#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT (1 << 16)
+
+#define BIOS_CHARACTERISTICS_EXT1_ACPI (1 << 0)
+#define BIOS_CHARACTERISTICS_EXT2_TARGET (1 << 2)
+
+struct __packed smbios_type0 {
+ u8 type;
+ u8 length;
+ u16 handle;
+ u8 vendor;
+ u8 bios_ver;
+ u16 bios_start_segment;
+ u8 bios_release_date;
+ u8 bios_rom_size;
+ u64 bios_characteristics;
+ u8 bios_characteristics_ext1;
+ u8 bios_characteristics_ext2;
+ u8 bios_major_release;
+ u8 bios_minor_release;
+ u8 ec_major_release;
+ u8 ec_minor_release;
+ char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+struct __packed smbios_type1 {
+ u8 type;
+ u8 length;
+ u16 handle;
+ u8 manufacturer;
+ u8 product_name;
+ u8 version;
+ u8 serial_number;
+ u8 uuid[16];
+ u8 wakeup_type;
+ u8 sku_number;
+ u8 family;
+ char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+#define SMBIOS_BOARD_FEATURE_HOSTING (1 << 0)
+#define SMBIOS_BOARD_MOTHERBOARD 10
+
+struct __packed smbios_type2 {
+ u8 type;
+ u8 length;
+ u16 handle;
+ u8 manufacturer;
+ u8 product_name;
+ u8 version;
+ u8 serial_number;
+ u8 asset_tag_number;
+ u8 feature_flags;
+ u8 chassis_location;
+ u16 chassis_handle;
+ u8 board_type;
+ char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+#define SMBIOS_ENCLOSURE_DESKTOP 3
+#define SMBIOS_STATE_SAFE 3
+#define SMBIOS_SECURITY_NONE 3
+
+struct __packed smbios_type3 {
+ u8 type;
+ u8 length;
+ u16 handle;
+ u8 manufacturer;
+ u8 chassis_type;
+ u8 version;
+ u8 serial_number;
+ u8 asset_tag_number;
+ u8 bootup_state;
+ u8 power_supply_state;
+ u8 thermal_state;
+ u8 security_status;
+ u32 oem_defined;
+ u8 height;
+ u8 number_of_power_cords;
+ u8 element_count;
+ u8 element_record_length;
+ char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+#define SMBIOS_PROCESSOR_TYPE_CENTRAL 3
+#define SMBIOS_PROCESSOR_STATUS_ENABLED 1
+#define SMBIOS_PROCESSOR_UPGRADE_NONE 6
+
+struct __packed smbios_type4 {
+ u8 type;
+ u8 length;
+ u16 handle;
+ u8 socket_designation;
+ u8 processor_type;
+ u8 processor_family;
+ u8 processor_manufacturer;
+ u32 processor_id[2];
+ u8 processor_version;
+ u8 voltage;
+ u16 external_clock;
+ u16 max_speed;
+ u16 current_speed;
+ u8 status;
+ u8 processor_upgrade;
+ u16 l1_cache_handle;
+ u16 l2_cache_handle;
+ u16 l3_cache_handle;
+ u8 serial_number;
+ u8 asset_tag;
+ u8 part_number;
+ u8 core_count;
+ u8 core_enabled;
+ u8 thread_count;
+ u16 processor_characteristics;
+ u16 processor_family2;
+ u16 core_count2;
+ u16 core_enabled2;
+ u16 thread_count2;
+ char eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+struct __packed smbios_type32 {
+ u8 type;
+ u8 length;
+ u16 handle;
+ u8 reserved[6];
+ u8 boot_status;
+ u8 eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+struct __packed smbios_type127 {
+ u8 type;
+ u8 length;
+ u16 handle;
+ u8 eos[SMBIOS_STRUCT_EOS_BYTES];
+};
+
+struct __packed smbios_header {
+ u8 type;
+ u8 length;
+ u16 handle;
+};
+
+/**
+ * fill_smbios_header() - Fill the header of an SMBIOS table
+ *
+ * This fills the header of an SMBIOS table structure.
+ *
+ * @table: start address of the structure
+ * @type: the type of structure
+ * @length: the length of the formatted area of the structure
+ * @handle: the structure's handle, a unique 16-bit number
+ */
+static inline void fill_smbios_header(void *table, int type,
+ int length, int handle)
+{
+ struct smbios_header *header = table;
+
+ header->type = type;
+ header->length = length - SMBIOS_STRUCT_EOS_BYTES;
+ header->handle = handle;
+}
+
+/**
+ * Function prototype to write a specific type of SMBIOS structure
+ *
+ * @addr: start address to write the structure
+ * @handle: the structure's handle, a unique 16-bit number
+ * @return: size of the structure
+ */
+typedef int (*smbios_write_type)(u32 *addr, int handle);
+
+/**
+ * write_smbios_table() - Write SMBIOS table
+ *
+ * This writes SMBIOS table at a given address.
+ *
+ * @addr: start address to write SMBIOS table
+ * @return: end address of SMBIOS table
+ */
+u32 write_smbios_table(u32 addr);
+
+#endif /* _SMBIOS_H_ */
diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h
index bf351ed..94fa2a7 100644
--- a/arch/x86/include/asm/zimage.h
+++ b/arch/x86/include/asm/zimage.h
@@ -31,9 +31,6 @@
#define BZIMAGE_LOAD_ADDR 0x100000
#define ZIMAGE_LOAD_ADDR 0x10000
-/* Implementation defined function to install an e820 map. */
-unsigned install_e820_map(unsigned max_entries, struct e820entry *);
-
struct boot_params *load_zimage(char *image, unsigned long kernel_size,
ulong *load_addressp);
int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,