diff options
Diffstat (limited to 'arch')
87 files changed, 2264 insertions, 586 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 2ca5305..1102346 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -70,6 +70,12 @@ config SANDBOX select HAVE_GENERIC_BOARD select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL + select DM + select DM_SPI_FLASH + select DM_SERIAL + select DM_I2C + select DM_SPI + select DM_GPIO config SH bool "SuperH architecture" @@ -84,6 +90,9 @@ config X86 select HAVE_GENERIC_BOARD select SYS_GENERIC_BOARD select SUPPORT_OF_CONTROL + select DM + select DM_SERIAL + select DM_GPIO endchoice diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7ed0e20..3702bb0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -235,6 +235,8 @@ config TARGET_SPEAR600 config TARGET_STV0991 bool "Support stv0991" select CPU_V7 + select DM + select DM_SERIAL config TARGET_X600 bool "Support x600" @@ -293,6 +295,9 @@ config TARGET_MX35PDK config ARCH_BCM283X bool "Broadcom BCM283X family" + select DM + select DM_SERIAL + select DM_GPIO config TARGET_INTEGRATORAP_CM946ES bool "Support integratorap_cm946es" @@ -330,21 +335,33 @@ config TARGET_CM_T335 bool "Support cm_t335" select CPU_V7 select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO config TARGET_PEPPER bool "Support pepper" select CPU_V7 select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO config TARGET_AM335X_IGEP0033 bool "Support am335x_igep0033" select CPU_V7 select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO config TARGET_PCM051 bool "Support pcm051" select CPU_V7 select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO config TARGET_DRACO bool "Support draco" @@ -370,11 +387,17 @@ config TARGET_PENGWYN bool "Support pengwyn" select CPU_V7 select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO config TARGET_AM335X_EVM bool "Support am335x_evm" select CPU_V7 select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO config TARGET_AM43XX_EVM bool "Support am43xx_evm" @@ -385,6 +408,8 @@ config TARGET_BAV335X bool "Support bav335x" select CPU_V7 select SUPPORT_SPL + select DM + select DM_SERIAL help The BAV335x OEM Network Processor integrates all the functions of an embedded network computer in a small, easy to use SODIMM module which @@ -419,10 +444,18 @@ config TARGET_BCMNSP config ARCH_EXYNOS bool "Samsung EXYNOS" select CPU_V7 + select DM + select DM_SPI_FLASH + select DM_SERIAL + select DM_SPI + select DM_GPIO config ARCH_S5PC1XX bool "Samsung S5PC1XX" select CPU_V7 + select DM + select DM_SERIAL + select DM_GPIO config ARCH_HIGHBANK bool "Calxeda Highbank" @@ -517,11 +550,15 @@ config TARGET_MX6QARM2 config TARGET_MX6QSABREAUTO bool "Support mx6qsabreauto" select CPU_V7 + select DM + select DM_THERMAL config TARGET_MX6SABRESD bool "Support mx6sabresd" select CPU_V7 select SUPPORT_SPL + select DM + select DM_THERMAL config TARGET_MX6SLEVK bool "Support mx6slevk" @@ -531,6 +568,8 @@ config TARGET_MX6SXSABRESD bool "Support mx6sxsabresd" select CPU_V7 select SUPPORT_SPL + select DM + select DM_THERMAL config TARGET_GW_VENTANA bool "Support gw_ventana" @@ -591,16 +630,25 @@ config TARGET_CM_FX6 bool "Support cm_fx6" select CPU_V7 select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO config TARGET_SOCFPGA_ARRIA5 bool "Support socfpga_arria5" select CPU_V7 select SUPPORT_SPL + select DM + select DM_SPI_FLASH + select DM_SPI config TARGET_SOCFPGA_CYCLONE5 bool "Support socfpga_cyclone5" select CPU_V7 select SUPPORT_SPL + select DM + select DM_SPI_FLASH + select DM_SPI config ARCH_SUNXI bool "Support sunxi (Allwinner) SoCs" @@ -621,6 +669,7 @@ config ZYNQ bool "Xilinx Zynq Platform" select CPU_V7 select SUPPORT_SPL + select DM config TARGET_XILINX_ZYNQMP bool "Support Xilinx ZynqMP Platform" @@ -632,6 +681,12 @@ config TEGRA select SPL select OF_CONTROL select CPU_V7 + select DM + select DM_SPI_FLASH + select DM_SERIAL + select DM_I2C + select DM_SPI + select DM_GPIO config TARGET_VEXPRESS64_AEMV8A bool "Support vexpress_aemv8a" @@ -726,6 +781,9 @@ config ARCH_UNIPHIER select SUPPORT_SPL select SPL select OF_CONTROL + select DM + select DM_SERIAL + select DM_I2C endchoice diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c index 697e094..1ce9db7 100644 --- a/arch/arm/cpu/arm926ejs/spear/cpu.c +++ b/arch/arm/cpu/arm926ejs/spear/cpu.c @@ -32,7 +32,7 @@ int arch_cpu_init(void) periph_clk_cfg |= CONFIG_SPEAR_UART48M; writel(periph_clk_cfg, &misc_p->periph_clk_cfg); #endif -#if defined(CONFIG_DESIGNWARE_ETH) +#if defined(CONFIG_ETH_DESIGNWARE) periph1_clken |= MISC_ETHENB; #endif #if defined(CONFIG_DW_UDC) diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index bd7540a..f6084ac 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -65,19 +65,7 @@ endchoice config SYS_SOC default "exynos" -config DM - default y - -config DM_SERIAL - default y - -config DM_SPI - default y - -config DM_SPI_FLASH - default y - -config DM_GPIO +config DM_USB default y source "board/samsung/smdkv310/Kconfig" diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 17500f2..f2f6897 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -159,6 +159,6 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) #ifdef CONFIG_SCSI_AHCI_PLAT void arch_preboot_os(void) { - ahci_reset(DWC_AHSATA_BASE); + ahci_reset((void __iomem *)DWC_AHSATA_BASE); } #endif diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c index d18bc50..2c2d1bc 100644 --- a/arch/arm/cpu/armv7/omap-common/sata.c +++ b/arch/arm/cpu/armv7/omap-common/sata.c @@ -69,7 +69,7 @@ int init_sata(int dev) val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO; writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG); - ret = ahci_init(DWC_AHSATA_BASE); + ret = ahci_init((void __iomem *)DWC_AHSATA_BASE); return ret; } @@ -88,6 +88,6 @@ void scsi_init(void) void scsi_bus_reset(void) { - ahci_reset(DWC_AHSATA_BASE); - ahci_init(DWC_AHSATA_BASE); + ahci_reset((void __iomem *)DWC_AHSATA_BASE); + ahci_init((void __iomem *)DWC_AHSATA_BASE); } diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 1f96498..cc82c50 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -17,6 +17,9 @@ config TARGET_OMAP3_SDP3430 config TARGET_OMAP3_BEAGLE bool "TI OMAP3 BeagleBoard" select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO config TARGET_CM_T35 bool "CompuLab CM-T3530 and CM-T3730 boards" @@ -28,6 +31,9 @@ config TARGET_CM_T3517 config TARGET_DEVKIT8000 bool "TimLL OMAP3 Devkit8000" select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO config TARGET_OMAP3_EVM bool "TI OMAP3 EVM" @@ -44,13 +50,22 @@ config TARGET_OMAP3_EVM_QUICK_NAND config TARGET_OMAP3_IGEP00X0 bool "IGEP" select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO config TARGET_OMAP3_OVERO bool "OMAP35xx Gumstix Overo" select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO config TARGET_OMAP3_ZOOM1 bool "TI Zoom1" + select DM + select DM_SERIAL + select DM_GPIO config TARGET_AM3517_CRANE bool "am3517_crane" @@ -94,18 +109,12 @@ config TARGET_TWISTER config TARGET_OMAP3_CAIRO bool "QUIPOS CAIRO" select SUPPORT_SPL + select DM + select DM_SERIAL + select DM_GPIO endchoice -config DM - default y - -config DM_GPIO - default y if DM - -config DM_SERIAL - default y if DM - config SYS_SOC default "omap3" diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig index 2b333a3..57dccec 100644 --- a/arch/arm/cpu/armv7/rmobile/Kconfig +++ b/arch/arm/cpu/armv7/rmobile/Kconfig @@ -8,24 +8,36 @@ config TARGET_ARMADILLO_800EVA config TARGET_GOSE bool "Gose board" + select DM + select DM_SERIAL config TARGET_KOELSCH bool "Koelsch board" + select DM + select DM_SERIAL config TARGET_LAGER bool "Lager board" + select DM + select DM_SERIAL config TARGET_KZM9G bool "KZM9D board" config TARGET_ALT bool "Alt board" + select DM + select DM_SERIAL config TARGET_SILK bool "Silk board" + select DM + select DM_SERIAL config TARGET_PORTER bool "Porter board" + select DM + select DM_SERIAL endchoice diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c index 7873c38..0f8b4d0 100644 --- a/arch/arm/cpu/armv7/socfpga/misc.c +++ b/arch/arm/cpu/armv7/socfpga/misc.c @@ -49,7 +49,7 @@ void enable_caches(void) /* * DesignWare Ethernet initialization */ -#ifdef CONFIG_DESIGNWARE_ETH +#ifdef CONFIG_ETH_DESIGNWARE int cpu_eth_init(bd_t *bis) { #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f897e6d..09708d9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -54,6 +54,9 @@ dtb-$(CONFIG_SOCFPGA) += \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_socrates.dtb +dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \ + ls1021a-twr.dtb + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts index 7d8be69..e89a94f 100644 --- a/arch/arm/dts/exynos5250-snow.dts +++ b/arch/arm/dts/exynos5250-snow.dts @@ -40,9 +40,9 @@ }; i2c4: i2c@12ca0000 { - cros-ec@1e { + cros_ec: cros-ec@1e { reg = <0x1e>; - compatible = "google,cros-ec"; + compatible = "google,cros-ec-i2c"; i2c-max-frequency = <100000>; u-boot,i2c-offset-len = <0>; ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>; @@ -65,9 +65,10 @@ spi@131b0000 { spi-max-frequency = <1000000>; spi-deactivate-delay = <100>; - cros_ec: cros-ec@0 { - reg = <0>; - compatible = "google,cros-ec"; + + embedded-controller { + compatible = "google,cros-ec-i2c"; + reg = <0x1e>; spi-max-frequency = <5000000>; ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>; optimise-flash-write; @@ -133,6 +134,7 @@ ehci@12110000 { samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; }; xhci@12000000 { diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index 3ad4728..7d8fa28 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -104,12 +104,12 @@ spi@12d40000 { /* spi2 */ spi-max-frequency = <4000000>; spi-deactivate-delay = <200>; + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; reg = <0>; - compatible = "google,cros-ec"; spi-half-duplex; spi-max-timeout-ms = <1100>; - spi-frame-header = <0xec>; ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>; /* diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts index 494f764..8c1f616 100644 --- a/arch/arm/dts/exynos5800-peach-pi.dts +++ b/arch/arm/dts/exynos5800-peach-pi.dts @@ -97,11 +97,10 @@ spi-max-frequency = <4000000>; spi-deactivate-delay = <200>; cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; reg = <0>; - compatible = "google,cros-ec"; spi-half-duplex; spi-max-timeout-ms = <1100>; - spi-frame-header = <0xec>; ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>; /* diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts new file mode 100644 index 0000000..8367811 --- /dev/null +++ b/arch/arm/dts/ls1021a-qds.dts @@ -0,0 +1,216 @@ +/* + * Freescale ls1021a QDS board device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "LS1021A QDS Board"; + + aliases { + enet0_rgmii_phy = &rgmii_phy1; + enet1_rgmii_phy = &rgmii_phy2; + enet2_rgmii_phy = &rgmii_phy3; + enet0_sgmii_phy = &sgmii_phy1c; + enet1_sgmii_phy = &sgmii_phy1d; + spi0 = &qspi; + spi1 = &dspi0; + }; +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + dspiflash: at45db021d@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: s25fl128s@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; + + pca9547: mux@77 { + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + ds3232: rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + ina220@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + eeprom@56 { + compatible = "atmel,24c512"; + reg = <0x56>; + }; + + eeprom@57 { + compatible = "atmel,24c512"; + reg = <0x57>; + }; + + adt7461a@4c { + compatible = "adi,adt7461a"; + reg = <0x4c>; + }; + }; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x60000000 0x08000000 + 0x2 0x0 0x7e800000 0x00010000 + 0x3 0x0 0x7fb00000 0x00000100>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + fpga: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + reg = <0x3 0x0 0x0000100>; + bank-width = <1>; + device-width = <1>; + ranges = <0 3 0 0x100>; + + mdio-mux-emi1 { + compatible = "mdio-mux-mmioreg"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1[2:0] */ + + /* Onboard PHYs */ + ls1021amdio0: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + + ls1021amdio1: mdio@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + ls1021amdio2: mdio@40 { + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + }; + + ls1021amdio3: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + sgmii_phy1c: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + + ls1021amdio4: mdio@80 { + reg = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + sgmii_phy1d: ethernet-phy@1d { + reg = <0x1d>; + }; + }; + }; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + tbi0: tbi-phy@8 { + reg = <0x8>; + device_type = "tbi-phy"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/ls1021a-twr.dts b/arch/arm/dts/ls1021a-twr.dts new file mode 100644 index 0000000..0e61c07 --- /dev/null +++ b/arch/arm/dts/ls1021a-twr.dts @@ -0,0 +1,87 @@ +/* + * Freescale ls1021a TWR board device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "LS1021A TWR Board"; + + aliases { + enet2_rgmii_phy = &rgmii_phy1; + enet0_sgmii_phy = &sgmii_phy2; + enet1_sgmii_phy = &sgmii_phy0; + spi0 = &qspi; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + qflash0: n25q128a13@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR Flash on board */ + ranges = <0x0 0x0 0x60000000 0x08000000>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + sgmii_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + sgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + tbi1: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi new file mode 100644 index 0000000..7fadd7c --- /dev/null +++ b/arch/arm/dts/ls1021a.dtsi @@ -0,0 +1,381 @@ +/* + * Freescale ls1021a SOC common device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "fsl,ls1021a"; + interrupt-parent = <&gic>; + + aliases { + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + serial4 = &lpuart4; + serial5 = &lpuart5; + sysclk = &sysclk; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@f00 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf00>; + clocks = <&cluster1_clk>; + }; + + cpu@f01 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf01>; + clocks = <&cluster1_clk>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + interrupt-parent = <&gic>; + ranges; + + gic: interrupt-controller@1400000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x1401000 0x1000>, + <0x1402000 0x1000>, + <0x1404000 0x2000>, + <0x1406000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + + }; + + ifc: ifc@1530000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x1530000 0x10000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + }; + + dcfg: dcfg@1ee0000 { + compatible = "fsl,ls1021a-dcfg", "syscon"; + reg = <0x1ee0000 0x10000>; + big-endian; + }; + + esdhc: esdhc@1560000 { + compatible = "fsl,esdhc"; + reg = <0x1560000 0x10000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + big-endian; + bus-width = <4>; + status = "disabled"; + }; + + scfg: scfg@1570000 { + compatible = "fsl,ls1021a-scfg", "syscon"; + reg = <0x1570000 0x10000>; + big-endian; + }; + + clockgen: clocking@1ee1000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1ee1000 0x10000>; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "sysclk"; + }; + + cga_pll1: pll@800 { + compatible = "fsl,qoriq-core-pll-2.0"; + #clock-cells = <1>; + reg = <0x800 0x10>; + clocks = <&sysclk>; + clock-output-names = "cga-pll1", "cga-pll1-div2", + "cga-pll1-div4"; + }; + + platform_clk: pll@c00 { + compatible = "fsl,qoriq-core-pll-2.0"; + #clock-cells = <1>; + reg = <0xc00 0x10>; + clocks = <&sysclk>; + clock-output-names = "platform-clk", "platform-clk-div2"; + }; + + cluster1_clk: clk0c0@0 { + compatible = "fsl,qoriq-core-mux-2.0"; + #clock-cells = <0>; + reg = <0x0 0x10>; + clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4"; + clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>; + clock-output-names = "cluster1-clk"; + }; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2100000 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&platform_clk 1>; + num-cs = <6>; + big-endian; + status = "disabled"; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2110000 0x10000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&platform_clk 1>; + num-cs = <6>; + big-endian; + status = "disabled"; + }; + + qspi: quadspi@1550000 { + compatible = "fsl,vf610-qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1550000 0x10000>, + <0x40000000 0x4000000>; + num-cs = <2>; + big-endian; + status = "disabled"; + }; + + i2c0: i2c@2180000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2180000 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + i2c1: i2c@2190000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2190000 0x10000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + i2c2: i2c@21a0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x21a0000 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + uart0: serial@21c0500 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x21c0500 0x100>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + uart1: serial@21c0600 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x21c0600 0x100>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + uart2: serial@21d0500 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x21d0500 0x100>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + uart3: serial@21d0600 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x21d0600 0x100>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + lpuart0: serial@2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x2950000 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysclk>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart1: serial@2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x2960000 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x2970000 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart3: serial@2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x2980000 0x1000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x2990000 0x1000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x29a0000 0x1000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + wdog0: watchdog@2ad0000 { + compatible = "fsl,imx21-wdt"; + reg = <0x2ad0000 0x10000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "wdog-en"; + big-endian; + }; + + sai1: sai@2b50000 { + compatible = "fsl,vf610-sai"; + reg = <0x2b50000 0x10000>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "sai"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 47>, + <&edma0 1 46>; + big-endian; + status = "disabled"; + }; + + sai2: sai@2b60000 { + compatible = "fsl,vf610-sai"; + reg = <0x2b60000 0x10000>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "sai"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 45>, + <&edma0 1 44>; + big-endian; + status = "disabled"; + }; + + edma0: edma@2c00000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x2c00000 0x10000>, + <0x2c10000 0x10000>, + <0x2c20000 0x10000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + big-endian; + clock-names = "dmamux0", "dmamux1"; + clocks = <&platform_clk 1>, + <&platform_clk 1>; + }; + + mdio0: mdio@2d24000 { + compatible = "gianfar"; + device_type = "mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2d24000 0x4000>; + }; + + usb@8600000 { + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; + reg = <0x8600000 0x1000>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + phy_type = "ulpi"; + }; + + usb3@3100000 { + compatible = "snps,dwc3"; + reg = <0x3100000 0x10000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + }; + }; +}; diff --git a/arch/arm/dts/skeleton64.dtsi b/arch/arm/dts/skeleton64.dtsi new file mode 100644 index 0000000..b5d7f36 --- /dev/null +++ b/arch/arm/dts/skeleton64.dtsi @@ -0,0 +1,13 @@ +/* + * Skeleton device tree in the 64 bits version; the bare minimum + * needed to boot; just include and add a compatible value. The + * bootloader will typically populate the memory node. + */ + +/ { + #address-cells = <2>; + #size-cells = <2>; + chosen { }; + aliases { }; + memory { device_type = "memory"; reg = <0 0 0 0>; }; +}; diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts index c1f35a0..9367193 100644 --- a/arch/arm/dts/tegra124-nyan-big.dts +++ b/arch/arm/dts/tegra124-nyan-big.dts @@ -230,6 +230,7 @@ usb@7d000000 { /* Rear external USB port. */ status = "okay"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; }; usb-phy@7d000000 { @@ -246,6 +247,7 @@ usb@7d008000 { /* Left external USB port. */ status = "okay"; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; }; usb-phy@7d008000 { diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index f606255..37ea6e9 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -644,7 +644,7 @@ void board_init_r(gd_t *id, ulong dest_addr) #endif #if defined(CONFIG_CMD_NET) puts("Net: "); - eth_initialize(gd->bd); + eth_initialize(); #if defined(CONFIG_RESET_PHY_R) debug("Reset Ethernet PHY\n"); reset_phy(); diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 2d6b676..b1bff8c 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -18,6 +18,7 @@ #include <u-boot/zlib.h> #include <asm/byteorder.h> #include <libfdt.h> +#include <mapmem.h> #include <fdt_support.h> #include <asm/bootm.h> #include <asm/secure.h> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 30c4e17..b660a5b 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -30,6 +30,9 @@ config TARGET_TNY_A9260 config TARGET_SNAPPER9260 bool "Support snapper9260" select CPU_ARM926EJS + select DM + select DM_SERIAL + select DM_GPIO config TARGET_AFEB9260 bool "Support afeb9260" diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig index 0c04c30..c740180 100644 --- a/arch/arm/mach-bcm283x/Kconfig +++ b/arch/arm/mach-bcm283x/Kconfig @@ -14,15 +14,6 @@ config TARGET_RPI_2 endchoice -config DM - default y - -config DM_SERIAL - default y - -config DM_GPIO - default y - config PHYS_TO_BUS default y diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index e18bdfc..e699d61 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -49,7 +49,7 @@ int dvevm_read_mac_address(uint8_t *buf) goto i2cerr; /* Check that MAC address is valid. */ - if (!is_valid_ether_addr(buf)) + if (!is_valid_ethaddr(buf)) goto err; return 1; /* Found */ diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index fce1c1d..8bab594 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -23,27 +23,9 @@ config SYS_MALLOC_F_LEN config USE_PRIVATE_LIBGCC default y -config DM - default y - config SPL_DM default y -config DM_SERIAL - default y - -config DM_SPI - default y - -config DM_SPI_FLASH - default y - -config DM_I2C - default y - -config DM_GPIO - default y - source "arch/arm/mach-tegra/tegra20/Kconfig" source "arch/arm/mach-tegra/tegra30/Kconfig" source "arch/arm/mach-tegra/tegra114/Kconfig" diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index 99aa96e..aacfcbf 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -244,7 +244,7 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) #endif #if defined(CONFIG_CMD_NET) puts("Net: "); - eth_initialize(gd->bd); + eth_initialize(); #endif #ifdef CONFIG_GENERIC_ATMEL_MCI diff --git a/arch/mips/mach-au1x00/au1x00_eth.c b/arch/mips/mach-au1x00/au1x00_eth.c index 39c5b6b..d6ebe07 100644 --- a/arch/mips/mach-au1x00/au1x00_eth.c +++ b/arch/mips/mach-au1x00/au1x00_eth.c @@ -187,13 +187,14 @@ static int au1x00_recv(struct eth_device* dev){ if(status&RX_ERROR){ printf("Rx error 0x%x\n", status); - } - else{ + } else { /* Pass the packet up to the protocol layers. */ - NetReceive(NetRxPackets[next_rx], length - 4); + net_process_received_packet(net_rx_packets[next_rx], + length - 4); } - fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE; + fifo_rx[next_rx].addr = + (virt_to_phys(net_rx_packets[next_rx])) | RX_DMA_ENABLE; next_rx++; if(next_rx>=NO_OF_FIFOS){ @@ -234,11 +235,12 @@ static int au1x00_init(struct eth_device* dev, bd_t * bd){ for(i=0;i<NO_OF_FIFOS;i++){ fifo_tx[i].len = 0; fifo_tx[i].addr = virt_to_phys(&txbuf[0]); - fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE; + fifo_rx[i].addr = (virt_to_phys(net_rx_packets[i])) | + RX_DMA_ENABLE; } /* Put mac addr in little endian */ -#define ea eth_get_dev()->enetaddr +#define ea eth_get_ethaddr() *mac_addr_high = (ea[5] << 8) | (ea[4] ) ; *mac_addr_low = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | (ea[0] ) ; diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c index 4c06a48..24a09bc 100644 --- a/arch/nds32/lib/board.c +++ b/arch/nds32/lib/board.c @@ -383,7 +383,7 @@ void board_init_r(gd_t *id, ulong dest_addr) #if defined(CONFIG_CMD_NET) puts("Net: "); - eth_initialize(gd->bd); + eth_initialize(); #if defined(CONFIG_RESET_PHY_R) debug("Reset Ethernet PHY\n"); reset_phy(); diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c index 2346685..c26cc8f 100644 --- a/arch/openrisc/lib/board.c +++ b/arch/openrisc/lib/board.c @@ -128,7 +128,7 @@ void board_init(void) #if defined(CONFIG_CMD_NET) puts("NET: "); - eth_initialize(bd); + eth_initialize(); #endif /* main_loop */ diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c index f9f15b5..30ea3de 100644 --- a/arch/powerpc/cpu/mpc8260/ether_fcc.c +++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c @@ -183,7 +183,7 @@ static int fec_recv(struct eth_device* dev) } else { /* Pass the packet up to the protocol layers. */ - NetReceive(NetRxPackets[rxIdx], length - 4); + net_process_received_packet(net_rx_packets[rxIdx], length - 4); } @@ -243,7 +243,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) { rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; rtx.rxbd[i].cbd_datlen = 0; - rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; + rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i]; } rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; @@ -299,7 +299,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) * it unique by setting a few bits in the upper byte of the * non-static part of the address. */ -#define ea eth_get_dev()->enetaddr +#define ea eth_get_ethaddr() pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; @@ -637,7 +637,7 @@ eth_loopback_test (void) puts ("FCC Ethernet External loopback test\n"); - eth_getenv_enetaddr("ethaddr", NetOurEther); + eth_getenv_enetaddr("ethaddr", net_ethaddr); /* * global initialisations for all FCC channels @@ -720,8 +720,8 @@ eth_loopback_test (void) bdp->cbd_sc = BD_ENET_TX_READY | BD_ENET_TX_PAD | \ BD_ENET_TX_LAST | BD_ENET_TX_TC; - memset ((void *)bp, patbytes[i], ELBT_BUFSZ); - NetSetEther (bp, NetBcastAddr, 0x8000); + memset((void *)bp, patbytes[i], ELBT_BUFSZ); + net_set_ether(bp, net_bcast_ethaddr, 0x8000); } ecp->txbd[ELBT_NTXBD - 1].cbd_sc |= BD_ENET_TX_WRAP; @@ -799,11 +799,9 @@ eth_loopback_test (void) * So, far we have only been given one Ethernet address. We use * the same address for all channels */ -#define ea NetOurEther - fpp->fen_paddrh = (ea[5] << 8) + ea[4]; - fpp->fen_paddrm = (ea[3] << 8) + ea[2]; - fpp->fen_paddrl = (ea[1] << 8) + ea[0]; -#undef ea + fpp->fen_paddrh = (net_ethaddr[5] << 8) + net_ethaddr[4]; + fpp->fen_paddrm = (net_ethaddr[3] << 8) + net_ethaddr[2]; + fpp->fen_paddrl = (net_ethaddr[1] << 8) + net_ethaddr[0]; fpp->fen_minflr = PKT_MINBUF_SIZE; /* min frame len register */ /* @@ -1016,7 +1014,7 @@ eth_loopback_test (void) &ecp->rxbufs[i][0]; ours = memcmp (ehp->et_src, \ - NetOurEther, 6); + net_ethaddr, 6); prot = swap16 (ehp->et_protlen); tb = prot & 0x8000; diff --git a/arch/powerpc/cpu/mpc8260/ether_scc.c b/arch/powerpc/cpu/mpc8260/ether_scc.c index c988def..5ba8bed 100644 --- a/arch/powerpc/cpu/mpc8260/ether_scc.c +++ b/arch/powerpc/cpu/mpc8260/ether_scc.c @@ -146,7 +146,7 @@ static int sec_rx(struct eth_device *dev) else { /* Pass the packet up to the protocol layers. */ - NetReceive(NetRxPackets[rxIdx], length - 4); + net_process_received_packet(net_rx_packets[rxIdx], length - 4); } @@ -263,7 +263,7 @@ static int sec_init(struct eth_device *dev, bd_t *bis) { rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; + rtx->rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i]; } rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 4d6cb09..88a3bd6 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -49,6 +49,7 @@ config TARGET_MPC837XERDB config TARGET_IDS8313 bool "Support ids8313" + select DM config TARGET_KM8360 bool "Support km8360" diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/arch/powerpc/cpu/mpc85xx/ether_fcc.c index 166dc9e..14358ae 100644 --- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c +++ b/arch/powerpc/cpu/mpc85xx/ether_fcc.c @@ -186,7 +186,7 @@ static int fec_recv(struct eth_device* dev) } else { /* Pass the packet up to the protocol layers. */ - NetReceive(NetRxPackets[rxIdx], length - 4); + net_process_received_packet(net_rx_packets[rxIdx], length - 4); } @@ -263,7 +263,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) { rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; rtx.rxbd[i].cbd_datlen = 0; - rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i]; + rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i]; } rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; @@ -338,7 +338,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis) * it unique by setting a few bits in the upper byte of the * non-static part of the address. */ -#define ea eth_get_dev()->enetaddr +#define ea eth_get_ethaddr() pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4]; pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2]; pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0]; diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index 22b8ec7..2e19603 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -247,21 +247,21 @@ static int fec_recv (struct eth_device *dev) rtx->rxbd[rxIdx].cbd_sc); #endif } else { - uchar *rx = NetRxPackets[rxIdx]; + uchar *rx = net_rx_packets[rxIdx]; length -= 4; #if defined(CONFIG_CMD_CDP) - if ((rx[0] & 1) != 0 - && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0 - && !is_cdp_packet((uchar *)rx)) + if ((rx[0] & 1) != 0 && + memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 && + !is_cdp_packet((uchar *)rx)) rx = NULL; #endif /* * Pass the packet up to the protocol layers. */ if (rx != NULL) - NetReceive (rx, length); + net_process_received_packet(rx, length); } /* Give the buffer back to the FEC. */ @@ -576,7 +576,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd) for (i = 0; i < PKTBUFSRX; i++) { rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; + rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; } rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c index 251966b..5498440 100644 --- a/arch/powerpc/cpu/mpc8xx/scc.c +++ b/arch/powerpc/cpu/mpc8xx/scc.c @@ -159,7 +159,8 @@ static int scc_recv (struct eth_device *dev) #endif } else { /* Pass the packet up to the protocol layers. */ - NetReceive (NetRxPackets[rxIdx], length - 4); + net_process_received_packet(net_rx_packets[rxIdx], + length - 4); } @@ -280,7 +281,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis) for (i = 0; i < PKTBUFSRX; i++) { rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; + rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; } rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; @@ -339,7 +340,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis) pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ -#define ea eth_get_dev()->enetaddr +#define ea eth_get_ethaddr() pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 9e52d3f..89cb3e9 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -43,6 +43,8 @@ config TARGET_BUBINGA config TARGET_CANYONLANDS bool "Support canyonlands" + select DM + select DM_SERIAL config TARGET_EBONY bool "Support ebony" diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 91645d3..5ea29cc 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -890,7 +890,7 @@ void board_init_r(gd_t *id, ulong dest_addr) #if defined(CONFIG_CMD_NET) WATCHDOG_RESET(); puts("Net: "); - eth_initialize(bd); + eth_initialize(); #endif #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 2098b9c..8aac96f 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -10,28 +10,26 @@ config SYS_BOARD config SYS_CONFIG_NAME default "sandbox" -config DM - default y - -config DM_GPIO - default y - -config DM_SERIAL +config DM_TEST default y -config DM_CROS_EC - default y +config PCI + bool "PCI support" + help + Enable support for PCI (Peripheral Interconnect Bus), a type of bus + used on some devices to allow the CPU to communicate with its + peripherals. -config DM_SPI +config NET default y -config DM_SPI_FLASH +config NETDEVICES default y -config DM_I2C +config DM_ETH default y -config DM_TEST +config ETH_SANDBOX_RAW default y endmenu diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index 7d4410c..1b42fee 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -8,6 +8,7 @@ # obj-y := cpu.o os.o start.o state.o +obj-$(CONFIG_ETH_SANDBOX_RAW) += eth-raw-os.o obj-$(CONFIG_SANDBOX_SDL) += sdl.o # os.c is build in the system environment, so needs standard includes @@ -20,3 +21,12 @@ $(obj)/os.o: $(src)/os.c FORCE $(call if_changed_dep,cc_os.o) $(obj)/sdl.o: $(src)/sdl.c FORCE $(call if_changed_dep,cc_os.o) + +# eth-raw-os.c is built in the system env, so needs standard includes +# CFLAGS_REMOVE_eth-raw-os.o cannot be used to drop header include path +quiet_cmd_cc_eth-raw-os.o = CC $(quiet_modtag) $@ +cmd_cc_eth-raw-os.o = $(CC) $(filter-out -nostdinc, \ + $(patsubst -I%,-idirafter%,$(c_flags))) -c -o $@ $< + +$(obj)/eth-raw-os.o: $(src)/eth-raw-os.c FORCE + $(call if_changed_dep,cc_eth-raw-os.o) diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 1aa397c..f0dafed 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -2,7 +2,7 @@ * Copyright (c) 2011 The Chromium OS Authors. * SPDX-License-Identifier: GPL-2.0+ */ - +#define DEBUG #include <common.h> #include <dm/root.h> #include <os.h> @@ -10,6 +10,15 @@ DECLARE_GLOBAL_DATA_PTR; +/* Enable access to PCI memory with map_sysmem() */ +static bool enable_pci_map; + +#ifdef CONFIG_PCI +/* Last device that was mapped into memory, and length of mapping */ +static struct udevice *map_dev; +unsigned long map_len; +#endif + void reset_cpu(ulong ignored) { if (state_uninit()) @@ -40,26 +49,44 @@ unsigned long __attribute__((no_instrument_function)) timer_get_us(void) return os_get_nsec() / 1000; } -int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) +int cleanup_before_linux(void) +{ + return 0; +} + +void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { - if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) { - bootstage_mark(BOOTSTAGE_ID_RUN_OS); - printf("## Transferring control to Linux (at address %08lx)...\n", - images->ep); - reset_cpu(0); +#ifdef CONFIG_PCI + unsigned long plen = len; + void *ptr; + + map_dev = NULL; + if (enable_pci_map && !pci_map_physmem(paddr, &len, &map_dev, &ptr)) { + if (plen != len) { + printf("%s: Warning: partial map at %x, wanted %lx, got %lx\n", + __func__, paddr, len, plen); + } + map_len = len; + return ptr; } +#endif - return 0; + return (void *)(gd->arch.ram_buf + paddr); } -int cleanup_before_linux(void) +void unmap_physmem(const void *vaddr, unsigned long flags) { - return 0; +#ifdef CONFIG_PCI + if (map_dev) { + pci_unmap_physmem(vaddr, map_len, map_dev); + map_dev = NULL; + } +#endif } -void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +void sandbox_set_enable_pci_map(int enable) { - return (void *)(gd->arch.ram_buf + paddr); + enable_pci_map = enable; } phys_addr_t map_to_sysmem(const void *ptr) diff --git a/arch/sandbox/cpu/eth-raw-os.c b/arch/sandbox/cpu/eth-raw-os.c new file mode 100644 index 0000000..b76a731 --- /dev/null +++ b/arch/sandbox/cpu/eth-raw-os.c @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2015 National Instruments + * + * (C) Copyright 2015 + * Joe Hershberger <joe.hershberger@ni.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <asm/eth-raw-os.h> +#include <errno.h> +#include <fcntl.h> +#include <net/if.h> +#include <netinet/in.h> +#include <netinet/ip.h> +#include <netinet/udp.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <sys/types.h> +#include <sys/ioctl.h> +#include <sys/socket.h> +#include <unistd.h> + +#include <arpa/inet.h> +#include <linux/if_ether.h> +#include <linux/if_packet.h> + +static int _raw_packet_start(const char *ifname, unsigned char *ethmac, + struct eth_sandbox_raw_priv *priv) +{ + struct sockaddr_ll *device; + struct packet_mreq mr; + int ret; + int flags; + + /* Prepare device struct */ + priv->device = malloc(sizeof(struct sockaddr_ll)); + if (priv->device == NULL) + return -ENOMEM; + device = priv->device; + memset(device, 0, sizeof(struct sockaddr_ll)); + device->sll_ifindex = if_nametoindex(ifname); + device->sll_family = AF_PACKET; + memcpy(device->sll_addr, ethmac, 6); + device->sll_halen = htons(6); + + /* Open socket */ + priv->sd = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL)); + if (priv->sd < 0) { + printf("Failed to open socket: %d %s\n", errno, + strerror(errno)); + return -errno; + } + /* Bind to the specified interface */ + ret = setsockopt(priv->sd, SOL_SOCKET, SO_BINDTODEVICE, ifname, + strlen(ifname) + 1); + if (ret < 0) { + printf("Failed to bind to '%s': %d %s\n", ifname, errno, + strerror(errno)); + return -errno; + } + + /* Make the socket non-blocking */ + flags = fcntl(priv->sd, F_GETFL, 0); + fcntl(priv->sd, F_SETFL, flags | O_NONBLOCK); + + /* Enable promiscuous mode to receive responses meant for us */ + mr.mr_ifindex = device->sll_ifindex; + mr.mr_type = PACKET_MR_PROMISC; + ret = setsockopt(priv->sd, SOL_PACKET, PACKET_ADD_MEMBERSHIP, + &mr, sizeof(mr)); + if (ret < 0) { + struct ifreq ifr; + + printf("Failed to set promiscuous mode: %d %s\n" + "Falling back to the old \"flags\" way...\n", + errno, strerror(errno)); + strncpy(ifr.ifr_name, ifname, IFNAMSIZ); + if (ioctl(priv->sd, SIOCGIFFLAGS, &ifr) < 0) { + printf("Failed to read flags: %d %s\n", errno, + strerror(errno)); + return -errno; + } + ifr.ifr_flags |= IFF_PROMISC; + if (ioctl(priv->sd, SIOCSIFFLAGS, &ifr) < 0) { + printf("Failed to write flags: %d %s\n", errno, + strerror(errno)); + return -errno; + } + } + return 0; +} + +static int _local_inet_start(struct eth_sandbox_raw_priv *priv) +{ + struct sockaddr_in *device; + int ret; + int flags; + int one = 1; + + /* Prepare device struct */ + priv->device = malloc(sizeof(struct sockaddr_in)); + if (priv->device == NULL) + return -ENOMEM; + device = priv->device; + memset(device, 0, sizeof(struct sockaddr_in)); + device->sin_family = AF_INET; + device->sin_addr.s_addr = htonl(INADDR_LOOPBACK); + + /** + * Open socket + * Since we specify UDP here, any incoming ICMP packets will + * not be received, so things like ping will not work on this + * localhost interface. + */ + priv->sd = socket(AF_INET, SOCK_RAW, IPPROTO_UDP); + if (priv->sd < 0) { + printf("Failed to open socket: %d %s\n", errno, + strerror(errno)); + return -errno; + } + + /* Make the socket non-blocking */ + flags = fcntl(priv->sd, F_GETFL, 0); + fcntl(priv->sd, F_SETFL, flags | O_NONBLOCK); + + /* Include the UDP/IP headers on send and receive */ + ret = setsockopt(priv->sd, IPPROTO_IP, IP_HDRINCL, &one, + sizeof(one)); + if (ret < 0) { + printf("Failed to set header include option: %d %s\n", errno, + strerror(errno)); + return -errno; + } + priv->local_bind_sd = -1; + priv->local_bind_udp_port = 0; + return 0; +} + +int sandbox_eth_raw_os_start(const char *ifname, unsigned char *ethmac, + struct eth_sandbox_raw_priv *priv) +{ + if (priv->local) + return _local_inet_start(priv); + else + return _raw_packet_start(ifname, ethmac, priv); +} + +int sandbox_eth_raw_os_send(void *packet, int length, + struct eth_sandbox_raw_priv *priv) +{ + int retval; + struct udphdr *udph = packet + sizeof(struct iphdr); + + if (!priv->sd || !priv->device) + return -EINVAL; + + /* + * This block of code came about when testing tftp on the localhost + * interface. When using the RAW AF_INET API, the network stack is still + * in play responding to incoming traffic based on open "ports". Since + * it is raw (at the IP layer, no Ethernet) the network stack tells the + * TFTP server that the port it responded to is closed. This causes the + * TFTP transfer to be aborted. This block of code inspects the outgoing + * packet as formulated by the u-boot network stack to determine the + * source port (that the TFTP server will send packets back to) and + * opens a typical UDP socket on that port, thus preventing the network + * stack from sending that ICMP message claiming that the port has no + * bound socket. + */ + if (priv->local && (priv->local_bind_sd == -1 || + priv->local_bind_udp_port != udph->source)) { + struct iphdr *iph = packet; + struct sockaddr_in addr; + + if (priv->local_bind_sd != -1) + close(priv->local_bind_sd); + + /* A normal UDP socket is required to bind */ + priv->local_bind_sd = socket(AF_INET, SOCK_DGRAM, 0); + if (priv->local_bind_sd < 0) { + printf("Failed to open bind sd: %d %s\n", errno, + strerror(errno)); + return -errno; + } + priv->local_bind_udp_port = udph->source; + + /** + * Bind the UDP port that we intend to use as our source port + * so that the kernel will not send an ICMP port unreachable + * message to the server + */ + addr.sin_family = AF_INET; + addr.sin_port = udph->source; + addr.sin_addr.s_addr = iph->saddr; + retval = bind(priv->local_bind_sd, &addr, sizeof(addr)); + if (retval < 0) + printf("Failed to bind: %d %s\n", errno, + strerror(errno)); + } + + retval = sendto(priv->sd, packet, length, 0, + (struct sockaddr *)priv->device, + sizeof(struct sockaddr_ll)); + if (retval < 0) { + printf("Failed to send packet: %d %s\n", errno, + strerror(errno)); + return -errno; + } + return retval; +} + +int sandbox_eth_raw_os_recv(void *packet, int *length, + const struct eth_sandbox_raw_priv *priv) +{ + int retval; + int saddr_size; + + if (!priv->sd || !priv->device) + return -EINVAL; + saddr_size = sizeof(struct sockaddr); + retval = recvfrom(priv->sd, packet, 1536, 0, + (struct sockaddr *)priv->device, + (socklen_t *)&saddr_size); + *length = 0; + if (retval >= 0) { + *length = retval; + return 0; + } + /* The socket is non-blocking, so expect EAGAIN when there is no data */ + if (errno == EAGAIN) + return 0; + return -errno; +} + +void sandbox_eth_raw_os_stop(struct eth_sandbox_raw_priv *priv) +{ + free(priv->device); + priv->device = NULL; + close(priv->sd); + priv->sd = -1; + if (priv->local) { + if (priv->local_bind_sd != -1) + close(priv->local_bind_sd); + priv->local_bind_sd = -1; + priv->local_bind_udp_port = 0; + } +} diff --git a/arch/sandbox/dts/cros-ec-keyboard.dtsi b/arch/sandbox/dts/cros-ec-keyboard.dtsi new file mode 100644 index 0000000..9c7fb0a --- /dev/null +++ b/arch/sandbox/dts/cros-ec-keyboard.dtsi @@ -0,0 +1,105 @@ +/* + * Keyboard dts fragment for devices that use cros-ec-keyboard + * + * Copyright (c) 2014 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include <dt-bindings/input/input.h> + +&cros_ec { + keyboard-controller { + compatible = "google,cros-ec-keyb"; + keypad,num-rows = <8>; + keypad,num-columns = <13>; + google,needs-ghost-filter; + + linux,keymap = < + MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) + MATRIX_KEY(0x00, 0x02, KEY_F1) + MATRIX_KEY(0x00, 0x03, KEY_B) + MATRIX_KEY(0x00, 0x04, KEY_F10) + MATRIX_KEY(0x00, 0x06, KEY_N) + MATRIX_KEY(0x00, 0x08, KEY_EQUAL) + MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) + + MATRIX_KEY(0x01, 0x01, KEY_ESC) + MATRIX_KEY(0x01, 0x02, KEY_F4) + MATRIX_KEY(0x01, 0x03, KEY_G) + MATRIX_KEY(0x01, 0x04, KEY_F7) + MATRIX_KEY(0x01, 0x06, KEY_H) + MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) + MATRIX_KEY(0x01, 0x09, KEY_F9) + MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) + + MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL) + MATRIX_KEY(0x02, 0x01, KEY_TAB) + MATRIX_KEY(0x02, 0x02, KEY_F3) + MATRIX_KEY(0x02, 0x03, KEY_T) + MATRIX_KEY(0x02, 0x04, KEY_F6) + MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE) + MATRIX_KEY(0x02, 0x06, KEY_Y) + MATRIX_KEY(0x02, 0x07, KEY_102ND) + MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE) + MATRIX_KEY(0x02, 0x09, KEY_F8) + + MATRIX_KEY(0x03, 0x01, KEY_GRAVE) + MATRIX_KEY(0x03, 0x02, KEY_F2) + MATRIX_KEY(0x03, 0x03, KEY_5) + MATRIX_KEY(0x03, 0x04, KEY_F5) + MATRIX_KEY(0x03, 0x06, KEY_6) + MATRIX_KEY(0x03, 0x08, KEY_MINUS) + MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH) + + MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) + MATRIX_KEY(0x04, 0x01, KEY_A) + MATRIX_KEY(0x04, 0x02, KEY_D) + MATRIX_KEY(0x04, 0x03, KEY_F) + MATRIX_KEY(0x04, 0x04, KEY_S) + MATRIX_KEY(0x04, 0x05, KEY_K) + MATRIX_KEY(0x04, 0x06, KEY_J) + MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON) + MATRIX_KEY(0x04, 0x09, KEY_L) + MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH) + MATRIX_KEY(0x04, 0x0b, KEY_ENTER) + + MATRIX_KEY(0x05, 0x01, KEY_Z) + MATRIX_KEY(0x05, 0x02, KEY_C) + MATRIX_KEY(0x05, 0x03, KEY_V) + MATRIX_KEY(0x05, 0x04, KEY_X) + MATRIX_KEY(0x05, 0x05, KEY_COMMA) + MATRIX_KEY(0x05, 0x06, KEY_M) + MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT) + MATRIX_KEY(0x05, 0x08, KEY_SLASH) + MATRIX_KEY(0x05, 0x09, KEY_DOT) + MATRIX_KEY(0x05, 0x0b, KEY_SPACE) + + MATRIX_KEY(0x06, 0x01, KEY_1) + MATRIX_KEY(0x06, 0x02, KEY_3) + MATRIX_KEY(0x06, 0x03, KEY_4) + MATRIX_KEY(0x06, 0x04, KEY_2) + MATRIX_KEY(0x06, 0x05, KEY_8) + MATRIX_KEY(0x06, 0x06, KEY_7) + MATRIX_KEY(0x06, 0x08, KEY_0) + MATRIX_KEY(0x06, 0x09, KEY_9) + MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT) + MATRIX_KEY(0x06, 0x0b, KEY_DOWN) + MATRIX_KEY(0x06, 0x0c, KEY_RIGHT) + + MATRIX_KEY(0x07, 0x01, KEY_Q) + MATRIX_KEY(0x07, 0x02, KEY_E) + MATRIX_KEY(0x07, 0x03, KEY_R) + MATRIX_KEY(0x07, 0x04, KEY_W) + MATRIX_KEY(0x07, 0x05, KEY_I) + MATRIX_KEY(0x07, 0x06, KEY_U) + MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT) + MATRIX_KEY(0x07, 0x08, KEY_P) + MATRIX_KEY(0x07, 0x09, KEY_O) + MATRIX_KEY(0x07, 0x0b, KEY_UP) + MATRIX_KEY(0x07, 0x0c, KEY_LEFT) + >; + }; +}; diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 9ce31bf..efa2097 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -1,8 +1,15 @@ /dts-v1/; +#define USB_CLASS_HUB 9 + / { #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + + aliases { + eth5 = "/eth@90000000"; + pci0 = &pci; + }; chosen { stdout-path = "/serial"; @@ -32,36 +39,31 @@ sides = <6>; }; - host@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "sandbox,host-emulation"; - cros-ec@0 { - reg = <0>; - compatible = "google,cros-ec"; + cros_ec: cros-ec@0 { + reg = <0 0>; + compatible = "google,cros-ec-sandbox"; - /* - * This describes the flash memory within the EC. Note - * that the STM32L flash erases to 0, not 0xff. - */ + /* + * This describes the flash memory within the EC. Note + * that the STM32L flash erases to 0, not 0xff. + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0>; #address-cells = <1>; #size-cells = <1>; - flash@8000000 { - reg = <0x08000000 0x20000>; - erase-value = <0>; - #address-cells = <1>; - #size-cells = <1>; - /* Information for sandbox */ - ro { - reg = <0 0xf000>; - }; - wp-ro { - reg = <0xf000 0x1000>; - }; - rw { - reg = <0x10000 0x10000>; - }; + /* Information for sandbox */ + ro { + reg = <0 0xf000>; + }; + wp-ro { + reg = <0xf000 0x1000>; + }; + rw { + reg = <0x10000 0x10000>; }; }; }; @@ -72,59 +74,6 @@ yres = <600>; }; - cros-ec-keyb { - compatible = "google,cros-ec-keyb"; - keypad,num-rows = <8>; - keypad,num-columns = <13>; - google,ghost-filter; - /* - * Keymap entries take the form of 0xRRCCKKKK where - * RR=Row CC=Column KKKK=Key Code - * The values below are for a US keyboard layout and - * are taken from the Linux driver. Note that the - * 102ND key is not used for US keyboards. - */ - linux,keymap = < - /* CAPSLCK F1 B F10 */ - 0x0001003a 0x0002003b 0x00030030 0x00040044 - /* N = R_ALT ESC */ - 0x00060031 0x0008000d 0x000a0064 0x01010001 - /* F4 G F7 H */ - 0x0102003e 0x01030022 0x01040041 0x01060023 - /* ' F9 BKSPACE L_CTRL */ - 0x01080028 0x01090043 0x010b000e 0x0200001d - /* TAB F3 T F6 */ - 0x0201000f 0x0202003d 0x02030014 0x02040040 - /* ] Y 102ND [ */ - 0x0205001b 0x02060015 0x02070056 0x0208001a - /* F8 GRAVE F2 5 */ - 0x02090042 0x03010029 0x0302003c 0x03030006 - /* F5 6 - \ */ - 0x0304003f 0x03060007 0x0308000c 0x030b002b - /* R_CTRL A D F */ - 0x04000061 0x0401001e 0x04020020 0x04030021 - /* S K J ; */ - 0x0404001f 0x04050025 0x04060024 0x04080027 - /* L ENTER Z C */ - 0x04090026 0x040b001c 0x0501002c 0x0502002e - /* V X , M */ - 0x0503002f 0x0504002d 0x05050033 0x05060032 - /* L_SHIFT / . SPACE */ - 0x0507002a 0x05080035 0x05090034 0x050B0039 - /* 1 3 4 2 */ - 0x06010002 0x06020004 0x06030005 0x06040003 - /* 8 7 0 9 */ - 0x06050009 0x06060008 0x0608000b 0x0609000a - /* L_ALT DOWN RIGHT Q */ - 0x060a0038 0x060b006c 0x060c006a 0x07010010 - /* E R W I */ - 0x07020012 0x07030013 0x07040011 0x07050017 - /* U R_SHIFT P O */ - 0x07060016 0x07070036 0x07080019 0x07090018 - /* UP LEFT */ - 0x070b0067 0x070c0069>; - }; - gpio_a: gpios@0 { gpio-controller; compatible = "sandbox,gpio"; @@ -144,7 +93,7 @@ i2c@0 { #address-cells = <1>; #size-cells = <0>; - reg = <0>; + reg = <0 0>; compatible = "sandbox,i2c"; clock-frequency = <400000>; eeprom@2c { @@ -161,10 +110,10 @@ spi@0 { #address-cells = <1>; #size-cells = <0>; - reg = <0>; + reg = <0 0>; compatible = "sandbox,spi"; cs-gpios = <0>, <&gpio_a 0>; - flash@0 { + firmware_storage_spi: flash@0 { reg = <0>; compatible = "spansion,m25p16", "sandbox,spi-flash"; spi-max-frequency = <40000000>; @@ -172,13 +121,77 @@ }; }; - cros-ec@0 { - compatible = "google,cros-ec"; - #address-cells = <1>; - #size-cells = <1>; - firmware_storage_spi: flash@0 { - reg = <0 0x400000>; + pci: pci-controller { + compatible = "sandbox,pci"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000 + 0x01000000 0 0x20000000 0x20000000 0 0x2000>; + pci@1f,0 { + compatible = "pci-generic"; + reg = <0xf800 0 0 0 0>; + emul@1f,0 { + compatible = "sandbox,swap-case"; + }; + }; + }; + + eth@10002000 { + compatible = "sandbox,eth"; + reg = <0x10002000 0x1000>; + fake-host-hwaddr = [00 00 66 44 22 00]; + }; + + eth@80000000 { + compatible = "sandbox,eth-raw"; + reg = <0x80000000 0x1000>; + host-raw-interface = "eth0"; + }; + + eth@90000000 { + compatible = "sandbox,eth-raw"; + reg = <0x90000000 0x1000>; + host-raw-interface = "lo"; + }; + + usb@0 { + compatible = "sandbox,usb"; + status = "disabled"; + hub { + compatible = "sandbox,usb-hub"; + #address-cells = <1>; + #size-cells = <0>; + flash-stick { + reg = <0>; + compatible = "sandbox,usb-flash"; + }; }; }; + usb@1 { + compatible = "sandbox,usb"; + hub { + compatible = "usb-hub"; + usb,device-class = <USB_CLASS_HUB>; + hub-emul { + compatible = "sandbox,usb-hub"; + #address-cells = <1>; + #size-cells = <0>; + flash-stick { + reg = <0>; + compatible = "sandbox,usb-flash"; + sandbox,filepath = "flash.bin"; + }; + }; + }; + }; + + usb@2 { + compatible = "sandbox,usb"; + status = "disabled"; + }; + }; + +#include "cros-ec-keyboard.dtsi" diff --git a/arch/sandbox/include/asm/eth-raw-os.h b/arch/sandbox/include/asm/eth-raw-os.h new file mode 100644 index 0000000..ed4b2e2 --- /dev/null +++ b/arch/sandbox/include/asm/eth-raw-os.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2015 National Instruments + * + * (C) Copyright 2015 + * Joe Hershberger <joe.hershberger@ni.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ETH_RAW_OS_H +#define __ETH_RAW_OS_H + +/** + * struct eth_sandbox_raw_priv - raw socket session + * + * sd: socket descriptor - the open socket during a session + * device: struct sockaddr_ll - the host interface packets move to/from + * local: 1 or 0 to select the local interface ('lo') or not + * local_bindsd: socket descriptor to prevent the kernel from sending + * a message to the server claiming the port is + * unreachable + * local_bind_udp_port: The UDP port number that we bound to + */ +struct eth_sandbox_raw_priv { + int sd; + void *device; + int local; + int local_bind_sd; + unsigned short local_bind_udp_port; +}; + +int sandbox_eth_raw_os_start(const char *ifname, unsigned char *ethmac, + struct eth_sandbox_raw_priv *priv); +int sandbox_eth_raw_os_send(void *packet, int length, + struct eth_sandbox_raw_priv *priv); +int sandbox_eth_raw_os_recv(void *packet, int *length, + const struct eth_sandbox_raw_priv *priv); +void sandbox_eth_raw_os_stop(struct eth_sandbox_raw_priv *priv); + +#endif /* __ETH_RAW_OS_H */ diff --git a/arch/sandbox/include/asm/eth.h b/arch/sandbox/include/asm/eth.h new file mode 100644 index 0000000..4b79ede --- /dev/null +++ b/arch/sandbox/include/asm/eth.h @@ -0,0 +1,15 @@ +/* + * Copyright (c) 2015 National Instruments + * + * (C) Copyright 2015 + * Joe Hershberger <joe.hershberger@ni.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ETH_H +#define __ETH_H + +void sandbox_eth_disable_response(int index, bool disable); + +#endif /* __ETH_H */ diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h index 895fcb8..5b87fde 100644 --- a/arch/sandbox/include/asm/io.h +++ b/arch/sandbox/include/asm/io.h @@ -22,10 +22,7 @@ void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags); /* * Take down a mapping set up by map_physmem(). */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} +void unmap_physmem(const void *vaddr, unsigned long flags); /* For sandbox, we want addresses to point into our RAM buffer */ static inline void *map_sysmem(phys_addr_t paddr, unsigned long len) @@ -33,8 +30,10 @@ static inline void *map_sysmem(phys_addr_t paddr, unsigned long len) return map_physmem(paddr, len, MAP_WRBACK); } +/* Remove a previous mapping */ static inline void unmap_sysmem(const void *vaddr) { + unmap_physmem(vaddr, MAP_WRBACK); } /* Map from a pointer to our RAM buffer */ @@ -48,6 +47,15 @@ phys_addr_t map_to_sysmem(const void *ptr); #define writew(v, addr) #define writel(v, addr) +/* I/O access functions */ +int inl(unsigned int addr); +int inw(unsigned int addr); +int inb(unsigned int addr); + +void outl(unsigned int value, unsigned int addr); +void outw(unsigned int value, unsigned int addr); +void outb(unsigned int value, unsigned int addr); + #include <iotrace.h> #endif diff --git a/arch/sandbox/include/asm/processor.h b/arch/sandbox/include/asm/processor.h new file mode 100644 index 0000000..3c1794e --- /dev/null +++ b/arch/sandbox/include/asm/processor.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_PROCESSOR_H +#define _ASM_PROCESSOR_H + +/* This file is required for PCI */ + +#endif diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h index 25a0c85..8e490e9 100644 --- a/arch/sandbox/include/asm/test.h +++ b/arch/sandbox/include/asm/test.h @@ -10,7 +10,12 @@ #define __ASM_TEST_H /* The sandbox driver always permits an I2C device with this address */ -#define SANDBOX_I2C_TEST_ADDR 0x59 +#define SANDBOX_I2C_TEST_ADDR 0x59 + +#define SANDBOX_PCI_VENDOR_ID 0x1234 +#define SANDBOX_PCI_DEVICE_ID 0x5678 +#define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM +#define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL enum sandbox_i2c_eeprom_test_mode { SIE_TEST_MODE_NONE, diff --git a/arch/sandbox/include/asm/u-boot-sandbox.h b/arch/sandbox/include/asm/u-boot-sandbox.h index 770ab5c..d5b9361 100644 --- a/arch/sandbox/include/asm/u-boot-sandbox.h +++ b/arch/sandbox/include/asm/u-boot-sandbox.h @@ -27,4 +27,52 @@ int cleanup_before_linux(void); /* drivers/video/sandbox_sdl.c */ int sandbox_lcd_sdl_early_init(void); +/** + * pci_map_physmem() - map a PCI device into memory + * + * This is used on sandbox to map a device into memory so that it can be + * used with normal memory access. After this call, some part of the device's + * internal structure becomes visible. + * + * This function is normally called from sandbox's map_sysmem() automatically. + * + * @paddr: Physical memory address, normally corresponding to a PCI BAR + * @lenp: On entry, the size of the area to map, On exit it is updated + * to the size actually mapped, which may be less if the device + * has less space + * @devp: Returns the device which mapped into this space + * @ptrp: Returns a pointer to the mapped address. The device's space + * can be accessed as @lenp bytes starting here + * @return 0 if OK, -ve on error + */ +int pci_map_physmem(phys_addr_t paddr, unsigned long *lenp, + struct udevice **devp, void **ptrp); + +/** + * pci_unmap_physmem() - undo a memory mapping + * + * This must be called after pci_map_physmem() to undo the mapping. + * + * @paddr: Physical memory address, as passed to pci_map_physmem() + * @len: Size of area mapped, as returned by pci_map_physmem() + * @dev: Device to unmap, as returned by pci_map_physmem() + * @return 0 if OK, -ve on error + */ +int pci_unmap_physmem(const void *addr, unsigned long len, + struct udevice *dev); + +/** + * sandbox_set_enable_pci_map() - Enable / disable PCI address mapping + * + * Since address mapping involves calling every driver, provide a way to + * enable and disable this. It can be handled automatically by the emulator + * uclass, which knows if any emulators are currently active. + * + * If this is disabled, pci_map_physmem() will not be called from + * map_sysmem(). + * + * @enable: 0 to disable, 1 to enable + */ +void sandbox_set_enable_pci_map(int enable); + #endif /* _U_BOOT_SANDBOX_H_ */ diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile index 4c1a38d..96761e2 100644 --- a/arch/sandbox/lib/Makefile +++ b/arch/sandbox/lib/Makefile @@ -7,5 +7,6 @@ # SPDX-License-Identifier: GPL-2.0+ # - obj-y += interrupts.o +obj-$(CONFIG_PCI) += pci_io.o +obj-$(CONFIG_CMD_BOOTM) += bootm.o diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c new file mode 100644 index 0000000..d49c927 --- /dev/null +++ b/arch/sandbox/lib/bootm.c @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * Copyright (c) 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk> + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define LINUX_ARM_ZIMAGE_MAGIC 0x016f2818 + +struct arm_z_header { + uint32_t code[9]; + uint32_t zi_magic; + uint32_t zi_start; + uint32_t zi_end; +} __attribute__ ((__packed__)); + +int bootz_setup(ulong image, ulong *start, ulong *end) +{ + uint8_t *zimage = map_sysmem(image, 0); + struct arm_z_header *arm_hdr = (struct arm_z_header *)zimage; + int ret = 0; + + if (memcmp(zimage + 0x202, "HdrS", 4) == 0) { + uint8_t setup_sects = *(zimage + 0x1f1); + uint32_t syssize = + le32_to_cpu(*(uint32_t *)(zimage + 0x1f4)); + + *start = 0; + *end = (setup_sects + 1) * 512 + syssize * 16; + + printf("setting up X86 zImage [ %ld - %ld ]\n", + *start, *end); + } else if (le32_to_cpu(arm_hdr->zi_magic) == LINUX_ARM_ZIMAGE_MAGIC) { + *start = le32_to_cpu(arm_hdr->zi_start); + *end = le32_to_cpu(arm_hdr->zi_end); + + printf("setting up ARM zImage [ %ld - %ld ]\n", + *start, *end); + } else { + printf("Unrecognized zImage\n"); + ret = 1; + } + + unmap_sysmem((void *)image); + + return ret; +} + +int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) +{ + if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) { + bootstage_mark(BOOTSTAGE_ID_RUN_OS); + printf("## Transferring control to Linux (at address %08lx)...\n", + images->ep); + reset_cpu(0); + } + + return 0; +} diff --git a/arch/sandbox/lib/pci_io.c b/arch/sandbox/lib/pci_io.c new file mode 100644 index 0000000..0de124f --- /dev/null +++ b/arch/sandbox/lib/pci_io.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2014 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * IO space access commands. + */ + +#include <common.h> +#include <command.h> +#include <dm.h> +#include <asm/io.h> + +int pci_map_physmem(phys_addr_t paddr, unsigned long *lenp, + struct udevice **devp, void **ptrp) +{ + struct udevice *dev; + int ret; + + *ptrp = 0; + for (uclass_first_device(UCLASS_PCI_EMUL, &dev); + dev; + uclass_next_device(&dev)) { + struct dm_pci_emul_ops *ops = pci_get_emul_ops(dev); + + if (!ops || !ops->map_physmem) + continue; + ret = (ops->map_physmem)(dev, paddr, lenp, ptrp); + if (ret) + continue; + *devp = dev; + return 0; + } + + debug("%s: failed: addr=%x\n", __func__, paddr); + return -ENOSYS; +} + +int pci_unmap_physmem(const void *vaddr, unsigned long len, + struct udevice *dev) +{ + struct dm_pci_emul_ops *ops = pci_get_emul_ops(dev); + + if (!ops || !ops->unmap_physmem) + return -ENOSYS; + return (ops->unmap_physmem)(dev, vaddr, len); +} + +static int pci_io_read(unsigned int addr, ulong *valuep, pci_size_t size) +{ + struct udevice *dev; + int ret; + + *valuep = pci_get_ff(size); + for (uclass_first_device(UCLASS_PCI_EMUL, &dev); + dev; + uclass_next_device(&dev)) { + struct dm_pci_emul_ops *ops = pci_get_emul_ops(dev); + + if (ops && ops->read_io) { + ret = (ops->read_io)(dev, addr, valuep, size); + if (!ret) + return 0; + } + } + + debug("%s: failed: addr=%x\n", __func__, addr); + return -ENOSYS; +} + +static int pci_io_write(unsigned int addr, ulong value, pci_size_t size) +{ + struct udevice *dev; + int ret; + + for (uclass_first_device(UCLASS_PCI_EMUL, &dev); + dev; + uclass_next_device(&dev)) { + struct dm_pci_emul_ops *ops = pci_get_emul_ops(dev); + + if (ops && ops->write_io) { + ret = (ops->write_io)(dev, addr, value, size); + if (!ret) + return 0; + } + } + + debug("%s: failed: addr=%x, value=%lx\n", __func__, addr, value); + return -ENOSYS; +} + +int inl(unsigned int addr) +{ + unsigned long value; + int ret; + + ret = pci_io_read(addr, &value, PCI_SIZE_32); + + return ret ? 0 : value; +} + +int inw(unsigned int addr) +{ + unsigned long value; + int ret; + + ret = pci_io_read(addr, &value, PCI_SIZE_16); + + return ret ? 0 : value; +} + +int inb(unsigned int addr) +{ + unsigned long value; + int ret; + + ret = pci_io_read(addr, &value, PCI_SIZE_8); + + return ret ? 0 : value; +} + +void outl(unsigned int value, unsigned int addr) +{ + pci_io_write(addr, value, PCI_SIZE_32); +} + +void outw(unsigned int value, unsigned int addr) +{ + pci_io_write(addr, value, PCI_SIZE_16); +} + +void outb(unsigned int value, unsigned int addr) +{ + pci_io_write(addr, value, PCI_SIZE_8); +} diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 1eb7afb..6dad3c7 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -178,7 +178,7 @@ void sh_generic_init(void) #endif #if defined(CONFIG_CMD_NET) puts("Net: "); - eth_initialize(gd->bd); + eth_initialize(); #endif /* CONFIG_CMD_NET */ while (1) { diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c index b311a94..d2ac6bc 100644 --- a/arch/sparc/lib/board.c +++ b/arch/sparc/lib/board.c @@ -351,7 +351,7 @@ void board_init_f(ulong bootflag) #if defined(CONFIG_CMD_NET) WATCHDOG_RESET(); puts("Net: "); - eth_initialize(bd); + eth_initialize(); #endif #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index da27115..3f1401a 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -7,6 +7,9 @@ config SYS_ARCH config USE_PRIVATE_LIBGCC default y +config SYS_VSNPRINTF + default y + choice prompt "Target select" @@ -32,6 +35,20 @@ config TARGET_CHROMEBOOK_LINK and it provides a 2560x1700 high resolution touch-enabled LCD display. +config TARGET_CHROMEBOX_PANTHER + bool "Support Chromebox panther (not available)" + select n + help + Note: At present this must be used with Coreboot. See README.x86 + for instructions. + + This is the Asus Chromebox CN60 released in 2014. It uses an Intel + Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a + Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also + includes a USB SD reader, four USB3 ports, display port and HDMI + video output and a 16GB SATA solid state drive. There is no Chrome + OS EC on this model. + config TARGET_CROWNBAY bool "Support Intel Crown Bay CRB" help @@ -67,13 +84,10 @@ config TARGET_GALILEO endchoice -config DM - default y - -config DM_GPIO +config DM_SPI default y -config DM_SERIAL +config DM_SPI_FLASH default y config SYS_MALLOC_F_LEN @@ -432,6 +446,8 @@ source "board/coreboot/coreboot/Kconfig" source "board/google/chromebook_link/Kconfig" +source "board/google/chromebox_panther/Kconfig" + source "board/intel/crownbay/Kconfig" source "board/intel/minnowmax/Kconfig" @@ -452,4 +468,13 @@ config PCIE_ECAM_BASE assigned to PCI devices - i.e. the memory and prefetch regions, as passed to pci_set_region(). +config BOOTSTAGE + default y + +config BOOTSTAGE_REPORT + default y + +config CMD_BOOTSTAGE + default y + endmenu diff --git a/arch/x86/cpu/baytrail/early_uart.c b/arch/x86/cpu/baytrail/early_uart.c index 4199210..b64a3a9 100644 --- a/arch/x86/cpu/baytrail/early_uart.c +++ b/arch/x86/cpu/baytrail/early_uart.c @@ -50,7 +50,7 @@ static void score_select_func(int pad, int func) writel(reg, pconf0_addr); } -static void pci_write_config32(int dev, unsigned int where, u32 value) +static void x86_pci_write_config32(int dev, unsigned int where, u32 value) { unsigned long addr; @@ -62,7 +62,8 @@ static void pci_write_config32(int dev, unsigned int where, u32 value) int setup_early_uart(void) { /* Enable the legacy UART hardware. */ - pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, 1); + x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, + 1); /* * Set up the pads to the UART function. This allows the signals to diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c index c9983f1..fa415dd 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/coreboot/pci.c @@ -10,58 +10,27 @@ */ #include <common.h> +#include <dm.h> +#include <errno.h> #include <pci.h> +#include <asm/io.h> #include <asm/pci.h> DECLARE_GLOBAL_DATA_PTR; -static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *table) -{ - u8 secondary; - hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary); - hose->last_busno = max(hose->last_busno, (int)secondary); - pci_hose_scan_bus(hose, secondary); -} - -static struct pci_config_table pci_coreboot_config_table[] = { - /* vendor, device, class, bus, dev, func */ - { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge }, - {} +static const struct dm_pci_ops pci_x86_ops = { + .read_config = pci_x86_read_config, + .write_config = pci_x86_write_config, }; -void board_pci_setup_hose(struct pci_controller *hose) -{ - hose->config_table = pci_coreboot_config_table; - hose->first_busno = 0; - hose->last_busno = 0; - - /* PCI memory space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - - pci_set_region(hose->regions + 2, - CONFIG_PCI_PREF_BUS, - CONFIG_PCI_PREF_PHYS, - CONFIG_PCI_PREF_SIZE, - PCI_REGION_PREFETCH); - - pci_set_region(hose->regions + 3, - 0, - 0, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); +static const struct udevice_id pci_x86_ids[] = { + { .compatible = "pci-x86" }, + { } +}; - hose->region_count = 4; -} +U_BOOT_DRIVER(pci_x86_drv) = { + .name = "pci_x86", + .id = UCLASS_PCI, + .of_match = pci_x86_ids, + .ops = &pci_x86_ops, +}; diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index e98a230..9c3ab81 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -90,7 +90,8 @@ int dram_init(void) struct memrange *memrange = &lib_sysinfo.memrange[i]; unsigned long long end = memrange->base + memrange->size; - if (memrange->type == CB_MEM_RAM && end > ram_size) + if (memrange->type == CB_MEM_RAM && end > ram_size && + memrange->base < (1ULL << 32)) ram_size = end; } gd->ram_size = ram_size; @@ -108,7 +109,8 @@ void dram_init_banksize(void) for (i = 0, j = 0; i < lib_sysinfo.n_memranges; i++) { struct memrange *memrange = &lib_sysinfo.memrange[i]; - if (memrange->type == CB_MEM_RAM) { + if (memrange->type == CB_MEM_RAM && + memrange->base < (1ULL << 32)) { gd->bd->bi_dram[j].start = memrange->base; gd->bd->bi_dram[j].size = memrange->size; j++; diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index ed7905c..a9ca50b 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -163,7 +163,7 @@ void setup_gdt(gd_t *id, u64 *gdt_addr) int __weak x86_cleanup_before_linux(void) { #ifdef CONFIG_BOOTSTAGE_STASH - bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH, + bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR, CONFIG_BOOTSTAGE_STASH_SIZE); #endif diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index 65a17d3..ca8cccf 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <fdtdec.h> #include <malloc.h> @@ -22,36 +23,36 @@ void bd82x6x_pci_init(pci_dev_t dev) debug("bd82x6x PCI init.\n"); /* Enable Bus Master */ - reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 = x86_pci_read_config16(dev, PCI_COMMAND); reg16 |= PCI_COMMAND_MASTER; - pci_write_config16(dev, PCI_COMMAND, reg16); + x86_pci_write_config16(dev, PCI_COMMAND, reg16); /* This device has no interrupt */ - pci_write_config8(dev, INTR, 0xff); + x86_pci_write_config8(dev, INTR, 0xff); /* disable parity error response and SERR */ - reg16 = pci_read_config16(dev, BCTRL); + reg16 = x86_pci_read_config16(dev, BCTRL); reg16 &= ~(1 << 0); reg16 &= ~(1 << 1); - pci_write_config16(dev, BCTRL, reg16); + x86_pci_write_config16(dev, BCTRL, reg16); /* Master Latency Count must be set to 0x04! */ - reg8 = pci_read_config8(dev, SMLT); + reg8 = x86_pci_read_config8(dev, SMLT); reg8 &= 0x07; reg8 |= (0x04 << 3); - pci_write_config8(dev, SMLT, reg8); + x86_pci_write_config8(dev, SMLT, reg8); /* Will this improve throughput of bus masters? */ - pci_write_config8(dev, PCI_MIN_GNT, 0x06); + x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06); /* Clear errors in status registers */ - reg16 = pci_read_config16(dev, PSTS); + reg16 = x86_pci_read_config16(dev, PSTS); /* reg16 |= 0xf900; */ - pci_write_config16(dev, PSTS, reg16); + x86_pci_write_config16(dev, PSTS, reg16); - reg16 = pci_read_config16(dev, SECSTS); + reg16 = x86_pci_read_config16(dev, SECSTS); /* reg16 |= 0xf900; */ - pci_write_config16(dev, SECSTS, reg16); + x86_pci_write_config16(dev, SECSTS, reg16); } #define PCI_BRIDGE_UPDATE_COMMAND @@ -59,7 +60,7 @@ void bd82x6x_pci_dev_enable_resources(pci_dev_t dev) { uint16_t command; - command = pci_read_config16(dev, PCI_COMMAND); + command = x86_pci_read_config16(dev, PCI_COMMAND); command |= PCI_COMMAND_IO; #ifdef PCI_BRIDGE_UPDATE_COMMAND /* @@ -67,7 +68,7 @@ void bd82x6x_pci_dev_enable_resources(pci_dev_t dev) * ROM and APICs to become invisible. */ debug("%x cmd <- %02x\n", dev, command); - pci_write_config16(dev, PCI_COMMAND, command); + x86_pci_write_config16(dev, PCI_COMMAND, command); #else printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command); #endif @@ -77,16 +78,16 @@ void bd82x6x_pci_bus_enable_resources(pci_dev_t dev) { uint16_t ctrl; - ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + ctrl = x86_pci_read_config16(dev, PCI_BRIDGE_CONTROL); ctrl |= PCI_COMMAND_IO; ctrl |= PCI_BRIDGE_CTL_VGA; debug("%x bridge ctrl <- %04x\n", dev, ctrl); - pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); + x86_pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl); bd82x6x_pci_dev_enable_resources(dev); } -int bd82x6x_init_pci_devices(void) +static int bd82x6x_probe(struct udevice *dev) { const void *blob = gd->fdt_blob; struct pci_controller *hose; @@ -144,3 +145,15 @@ int bd82x6x_init(void) return 0; } + +static const struct udevice_id bd82x6x_ids[] = { + { .compatible = "intel,bd82x6x" }, + { } +}; + +U_BOOT_DRIVER(bd82x6x_drv) = { + .name = "bd82x6x", + .id = UCLASS_PCH, + .of_match = bd82x6x_ids, + .probe = bd82x6x_probe, +}; diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index e925310..37f3731 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -12,6 +12,7 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <fdtdec.h> #include <asm/cpu.h> @@ -116,23 +117,32 @@ static void set_spi_speed(void) int arch_cpu_init(void) { + post_code(POST_CPU_INIT); + timer_set_base(rdtsc()); + + return x86_cpu_init_f(); +} + +int arch_cpu_init_dm(void) +{ const void *blob = gd->fdt_blob; struct pci_controller *hose; + struct udevice *bus; int node; int ret; - post_code(POST_CPU_INIT); - timer_set_base(rdtsc()); - - ret = x86_cpu_init_f(); + post_code(0x70); + ret = uclass_get_device(UCLASS_PCI, 0, &bus); + post_code(0x71); if (ret) return ret; + post_code(0x72); + hose = dev_get_uclass_priv(bus); - ret = pci_early_init_hose(&hose); - if (ret) - return ret; + /* TODO(sjg@chromium.org): Get rid of gd->hose */ + gd->hose = hose; - node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC); + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); if (node < 0) return -ENOENT; ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV); @@ -167,21 +177,21 @@ static int enable_smbus(void) dev = PCI_BDF(0x0, 0x1f, 0x3); /* Check to make sure we've got the right device. */ - value = pci_read_config16(dev, 0x0); + value = x86_pci_read_config16(dev, 0x0); if (value != 0x8086) { printf("SMBus controller not found\n"); return -ENOSYS; } /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + x86_pci_write_config32(dev, SMB_BASE, + SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); + x86_pci_write_config8(dev, HOSTC, HST_EN); /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + x86_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); /* Disable interrupt generation. */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); @@ -214,25 +224,25 @@ static void enable_usb_bar(void) u32 cmd; /* USB Controller 1 */ - pci_write_config32(usb0, PCI_BASE_ADDRESS_0, - PCH_EHCI0_TEMP_BAR0); - cmd = pci_read_config32(usb0, PCI_COMMAND); + x86_pci_write_config32(usb0, PCI_BASE_ADDRESS_0, + PCH_EHCI0_TEMP_BAR0); + cmd = x86_pci_read_config32(usb0, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb0, PCI_COMMAND, cmd); + x86_pci_write_config32(usb0, PCI_COMMAND, cmd); /* USB Controller 1 */ - pci_write_config32(usb1, PCI_BASE_ADDRESS_0, - PCH_EHCI1_TEMP_BAR0); - cmd = pci_read_config32(usb1, PCI_COMMAND); + x86_pci_write_config32(usb1, PCI_BASE_ADDRESS_0, + PCH_EHCI1_TEMP_BAR0); + cmd = x86_pci_read_config32(usb1, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb1, PCI_COMMAND, cmd); + x86_pci_write_config32(usb1, PCI_COMMAND, cmd); /* USB3 Controller */ - pci_write_config32(usb3, PCI_BASE_ADDRESS_0, - PCH_XHCI_TEMP_BAR0); - cmd = pci_read_config32(usb3, PCI_COMMAND); + x86_pci_write_config32(usb3, PCI_BASE_ADDRESS_0, + PCH_XHCI_TEMP_BAR0); + cmd = x86_pci_read_config32(usb3, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb3, PCI_COMMAND, cmd); + x86_pci_write_config32(usb3, PCI_COMMAND, cmd); } static int report_bist_failure(void) @@ -320,8 +330,8 @@ int print_cpuinfo(void) gd->arch.pei_boot_mode = boot_mode; /* TODO: Move this to the board or driver */ - pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10); + x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10); /* Print processor name */ name = cpu_get_name(processor_name); diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c index eb8f613..9ca008e 100644 --- a/arch/x86/cpu/ivybridge/early_init.c +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -17,10 +17,10 @@ static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev) { /* Setting up Southbridge. In the northbridge code. */ debug("Setting up static southbridge registers\n"); - pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); + x86_pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); - pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */ + x86_pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1); + x86_pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */ debug("Disabling watchdog reboot\n"); setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ @@ -28,25 +28,27 @@ static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev) /* Set up all hardcoded northbridge BARs */ debug("Setting up static registers\n"); - pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(pch_dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + x86_pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1); + x86_pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); + x86_pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1); + x86_pci_write_config32(pch_dev, MCHBAR + 4, + (0LL + DEFAULT_MCHBAR) >> 32); /* 64MB - busses 0-63 */ - pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); - pci_write_config32(pch_dev, PCIEXBAR + 4, - (0LL + DEFAULT_PCIEXBAR) >> 32); - pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1); - pci_write_config32(pch_dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); + x86_pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5); + x86_pci_write_config32(pch_dev, PCIEXBAR + 4, + (0LL + DEFAULT_PCIEXBAR) >> 32); + x86_pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1); + x86_pci_write_config32(pch_dev, DMIBAR + 4, + (0LL + DEFAULT_DMIBAR) >> 32); /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(pch_dev, PAM0, 0x30); - pci_write_config8(pch_dev, PAM1, 0x33); - pci_write_config8(pch_dev, PAM2, 0x33); - pci_write_config8(pch_dev, PAM3, 0x33); - pci_write_config8(pch_dev, PAM4, 0x33); - pci_write_config8(pch_dev, PAM5, 0x33); - pci_write_config8(pch_dev, PAM6, 0x33); + x86_pci_write_config8(pch_dev, PAM0, 0x30); + x86_pci_write_config8(pch_dev, PAM1, 0x33); + x86_pci_write_config8(pch_dev, PAM2, 0x33); + x86_pci_write_config8(pch_dev, PAM3, 0x33); + x86_pci_write_config8(pch_dev, PAM4, 0x33); + x86_pci_write_config8(pch_dev, PAM5, 0x33); + x86_pci_write_config8(pch_dev, PAM6, 0x33); } static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev) @@ -55,7 +57,7 @@ static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev) u16 reg16; u8 reg8; - reg16 = pci_read_config16(video_dev, PCI_DEVICE_ID); + reg16 = x86_pci_read_config16(video_dev, PCI_DEVICE_ID); switch (reg16) { case 0x0102: /* GT1 Desktop */ case 0x0106: /* GT1 Mobile */ @@ -75,7 +77,7 @@ static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev) debug("Initialising Graphics\n"); /* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */ - reg16 = pci_read_config16(pch_dev, GGC); + reg16 = x86_pci_read_config16(pch_dev, GGC); reg16 &= ~0x00f8; reg16 |= 1 << 3; /* Program GTT memory by setting GGC[9:8] = 2MB */ @@ -83,13 +85,13 @@ static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev) reg16 |= 2 << 8; /* Enable VGA decode */ reg16 &= ~0x0002; - pci_write_config16(pch_dev, GGC, reg16); + x86_pci_write_config16(pch_dev, GGC, reg16); /* Enable 256MB aperture */ - reg8 = pci_read_config8(video_dev, MSAC); + reg8 = x86_pci_read_config8(video_dev, MSAC); reg8 &= ~0x06; reg8 |= 0x02; - pci_write_config8(video_dev, MSAC, reg8); + x86_pci_write_config8(video_dev, MSAC, reg8); /* Erratum workarounds */ reg32 = readl(MCHBAR_REG(0x5f00)); @@ -124,22 +126,22 @@ void sandybridge_early_init(int chipset_type) u8 reg8; /* Device ID Override Enable should be done very early */ - capid0_a = pci_read_config32(pch_dev, 0xe4); + capid0_a = x86_pci_read_config32(pch_dev, 0xe4); if (capid0_a & (1 << 10)) { - reg8 = pci_read_config8(pch_dev, 0xf3); + reg8 = x86_pci_read_config8(pch_dev, 0xf3); reg8 &= ~7; /* Clear 2:0 */ if (chipset_type == SANDYBRIDGE_MOBILE) reg8 |= 1; /* Set bit 0 */ - pci_write_config8(pch_dev, 0xf3, reg8); + x86_pci_write_config8(pch_dev, 0xf3, reg8); } /* Setup all BARs required for early PCIe and raminit */ sandybridge_setup_bars(pch_dev, lpc_dev); /* Device Enable */ - pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD); + x86_pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD); sandybridge_setup_graphics(pch_dev, video_dev); } diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c index b24dea1..356bbb4 100644 --- a/arch/x86/cpu/ivybridge/early_me.c +++ b/arch/x86/cpu/ivybridge/early_me.c @@ -29,7 +29,7 @@ static inline void pci_read_dword_ptr(void *ptr, int offset) { u32 dword; - dword = pci_read_config32(PCH_ME_DEV, offset); + dword = x86_pci_read_config32(PCH_ME_DEV, offset); memcpy(ptr, &dword, sizeof(dword)); } @@ -37,7 +37,7 @@ static inline void pci_write_dword_ptr(void *ptr, int offset) { u32 dword = 0; memcpy(&dword, ptr, sizeof(dword)); - pci_write_config32(PCH_ME_DEV, offset, dword); + x86_pci_write_config32(PCH_ME_DEV, offset, dword); } void intel_early_me_status(void) @@ -101,7 +101,7 @@ static inline void set_global_reset(int enable) { u32 etr3; - etr3 = pci_read_config32(PCH_LPC_DEV, ETR3); + etr3 = x86_pci_read_config32(PCH_LPC_DEV, ETR3); /* Clear CF9 Without Resume Well Reset Enable */ etr3 &= ~ETR3_CWORWRE; @@ -112,7 +112,7 @@ static inline void set_global_reset(int enable) else etr3 &= ~ETR3_CF9GR; - pci_write_config32(PCH_LPC_DEV, ETR3, etr3); + x86_pci_write_config32(PCH_LPC_DEV, ETR3, etr3); } int intel_early_me_init_done(u8 status) @@ -127,8 +127,8 @@ int intel_early_me_init_done(u8 status) }; /* MEBASE from MESEG_BASE[35:20] */ - mebase_l = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L); - mebase_h = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H); + mebase_l = x86_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L); + mebase_h = x86_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H); mebase_h &= 0xf; did.uma_base = (mebase_l >> 20) | (mebase_h << 12); diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c index 821ea25..ea169b0 100644 --- a/arch/x86/cpu/ivybridge/gma.c +++ b/arch/x86/cpu/ivybridge/gma.c @@ -741,9 +741,9 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, int ret; /* IGD needs to be Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 = x86_pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); + x86_pci_write_config32(dev, PCI_COMMAND, reg32); /* Use write-combining for the graphics memory, 256MB */ base = pci_read_bar32(hose, dev, 2); diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 43fdd31..bc1a0f0 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <fdtdec.h> #include <rtc.h> @@ -29,7 +30,7 @@ static int pch_enable_apic(pci_dev_t dev) int i; /* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */ - pci_write_config8(dev, ACPI_CNTL, 0x80); + x86_pci_write_config8(dev, ACPI_CNTL, 0x80); writel(0, IO_APIC_INDEX); writel(1 << 25, IO_APIC_DATA); @@ -72,9 +73,9 @@ static void pch_enable_serial_irqs(pci_dev_t dev) /* Set packet length and toggle silent mode bit for one frame. */ value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0); #ifdef CONFIG_SERIRQ_CONTINUOUS_MODE - pci_write_config8(dev, SERIRQ_CNTL, value); + x86_pci_write_config8(dev, SERIRQ_CNTL, value); #else - pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6)); + x86_pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6)); #endif } @@ -86,15 +87,15 @@ static int pch_pirq_init(const void *blob, int node, pci_dev_t dev) sizeof(route))) return -EINVAL; ptr = route; - pci_write_config8(dev, PIRQA_ROUT, *ptr++); - pci_write_config8(dev, PIRQB_ROUT, *ptr++); - pci_write_config8(dev, PIRQC_ROUT, *ptr++); - pci_write_config8(dev, PIRQD_ROUT, *ptr++); + x86_pci_write_config8(dev, PIRQA_ROUT, *ptr++); + x86_pci_write_config8(dev, PIRQB_ROUT, *ptr++); + x86_pci_write_config8(dev, PIRQC_ROUT, *ptr++); + x86_pci_write_config8(dev, PIRQD_ROUT, *ptr++); - pci_write_config8(dev, PIRQE_ROUT, *ptr++); - pci_write_config8(dev, PIRQF_ROUT, *ptr++); - pci_write_config8(dev, PIRQG_ROUT, *ptr++); - pci_write_config8(dev, PIRQH_ROUT, *ptr++); + x86_pci_write_config8(dev, PIRQE_ROUT, *ptr++); + x86_pci_write_config8(dev, PIRQF_ROUT, *ptr++); + x86_pci_write_config8(dev, PIRQG_ROUT, *ptr++); + x86_pci_write_config8(dev, PIRQH_ROUT, *ptr++); /* * TODO(sjg@chromium.org): U-Boot does not set up the interrupts @@ -116,7 +117,7 @@ static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev) for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++) reg |= route[gpi] << (gpi * 2); - pci_write_config32(dev, 0xb8, reg); + x86_pci_write_config32(dev, 0xb8, reg); return 0; } @@ -141,7 +142,7 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev) */ pwr_on = MAINBOARD_POWER_ON; - reg16 = pci_read_config16(dev, GEN_PMCON_3); + reg16 = x86_pci_read_config16(dev, GEN_PMCON_3); reg16 &= 0xfffe; switch (pwr_on) { case MAINBOARD_POWER_OFF: @@ -168,7 +169,7 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev) reg16 |= (1 << 12); /* Disable SLP stretch after SUS well */ - pci_write_config16(dev, GEN_PMCON_3, reg16); + x86_pci_write_config16(dev, GEN_PMCON_3, reg16); debug("Set power %s after power failure.\n", state); /* Set up NMI on errors. */ @@ -192,21 +193,21 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev) outb(reg8, 0x70); /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ - reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 = x86_pci_read_config16(dev, GEN_PMCON_1); reg16 &= ~(3 << 0); /* SMI# rate 1 minute */ reg16 &= ~(1 << 10); /* Disable BIOS_PCI_EXP_EN for native PME */ #if DEBUG_PERIODIC_SMIS /* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */ reg16 |= (3 << 0); /* Periodic SMI every 8s */ #endif - pci_write_config16(dev, GEN_PMCON_1, reg16); + x86_pci_write_config16(dev, GEN_PMCON_1, reg16); /* Set the board's GPI routing. */ ret = pch_gpi_routing(blob, node, dev); if (ret) return ret; - pmbase = pci_read_config16(dev, 0x40) & 0xfffe; + pmbase = x86_pci_read_config16(dev, 0x40) & 0xfffe; writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node, "intel,gpe0-enable", 0)); @@ -231,11 +232,11 @@ static void pch_rtc_init(pci_dev_t dev) int rtc_failed; u8 reg8; - reg8 = pci_read_config8(dev, GEN_PMCON_3); + reg8 = x86_pci_read_config8(dev, GEN_PMCON_3); rtc_failed = reg8 & RTC_BATTERY_DEAD; if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; - pci_write_config8(dev, GEN_PMCON_3, reg8); + x86_pci_write_config8(dev, GEN_PMCON_3, reg8); } debug("rtc_failed = 0x%x\n", rtc_failed); @@ -258,7 +259,7 @@ static void pch_rtc_init(pci_dev_t dev) static void cpt_pm_init(pci_dev_t dev) { debug("CougarPoint PM init\n"); - pci_write_config8(dev, 0xa9, 0x47); + x86_pci_write_config8(dev, 0xa9, 0x47); setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0)); setbits_le32(RCB_REG(0x228c), 1 << 0); @@ -302,7 +303,7 @@ static void cpt_pm_init(pci_dev_t dev) static void ppt_pm_init(pci_dev_t dev) { debug("PantherPoint PM init\n"); - pci_write_config8(dev, 0xa9, 0x47); + x86_pci_write_config8(dev, 0xa9, 0x47); setbits_le32(RCB_REG(0x2238), 1 << 0); setbits_le32(RCB_REG(0x228c), 1 << 0); setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14)); @@ -356,9 +357,9 @@ static void enable_clock_gating(pci_dev_t dev) setbits_le32(RCB_REG(0x2234), 0xf); - reg16 = pci_read_config16(dev, GEN_PMCON_1); + reg16 = x86_pci_read_config16(dev, GEN_PMCON_1); reg16 |= (1 << 2) | (1 << 11); - pci_write_config16(dev, GEN_PMCON_1, reg16); + x86_pci_write_config16(dev, GEN_PMCON_1, reg16); pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); @@ -412,15 +413,15 @@ static void pch_lock_smm(pci_dev_t dev) #if TEST_SMM_FLASH_LOCKDOWN /* Now try this: */ debug("Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", (reg8 & 1) ? "rw" : "ro"); reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); + x86_pci_write_config8(dev, 0xdc, reg8); reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); + x86_pci_write_config8(dev, 0xdc, reg8); debug("ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", (reg8 & 1) ? "rw" : "ro"); @@ -428,9 +429,9 @@ static void pch_lock_smm(pci_dev_t dev) writeb(0, 0xfff00000); debug("Testing:\n"); reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); + x86_pci_write_config8(dev, 0xdc, reg8); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off", (reg8 & 1) ? "rw" : "ro"); debug("Done.\n"); @@ -443,9 +444,9 @@ static void pch_disable_smm_only_flashing(pci_dev_t dev) u8 reg8; debug("Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + x86_pci_write_config8(dev, 0xdc, reg8); } static void pch_fixups(pci_dev_t dev) @@ -453,9 +454,9 @@ static void pch_fixups(pci_dev_t dev) u8 gen_pmcon_2; /* Indicate DRAM init done for MRC S3 to know it can resume */ - gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); + gen_pmcon_2 = x86_pci_read_config8(dev, GEN_PMCON_2); gen_pmcon_2 |= (1 << 7); - pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); + x86_pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2); /* Enable DMI ASPM in the PCH */ clrbits_le32(RCB_REG(0x2304), 1 << 10); @@ -478,10 +479,10 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev) return -EINVAL; /* Set COM1/COM2 decode range */ - pci_write_config16(dev, LPC_IO_DEC, 0x0010); + x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010); /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */ - pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN | + x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN | GAMEL_LPC_EN | COMA_LPC_EN); /* Write all registers but use 0 if we run out of data */ @@ -491,7 +492,7 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev) if (i < count) reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16); - pci_write_config32(dev, LPC_GENX_DEC(i), reg); + x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg); } return 0; @@ -509,12 +510,12 @@ int lpc_init(struct pci_controller *hose, pci_dev_t dev) pci_write_bar32(hose, dev, 3, 0x800); pci_write_bar32(hose, dev, 4, 0x900); - node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC); + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); if (node < 0) return -ENOENT; /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + x86_pci_write_config16(dev, PCI_COMMAND, 0x000f); /* IO APIC initialization. */ pch_enable_apic(dev); @@ -567,3 +568,14 @@ void lpc_enable(pci_dev_t dev) writew(0x0010, RCB_REG(DISPBDF)); setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); } + +static const struct udevice_id bd82x6x_lpc_ids[] = { + { .compatible = "intel,bd82x6x-lpc" }, + { } +}; + +U_BOOT_DRIVER(bd82x6x_lpc_drv) = { + .name = "lpc", + .id = UCLASS_LPC, + .of_match = bd82x6x_lpc_ids, +}; diff --git a/arch/x86/cpu/ivybridge/mrccache.c b/arch/x86/cpu/ivybridge/mrccache.c index 0f1a64b..9205494 100644 --- a/arch/x86/cpu/ivybridge/mrccache.c +++ b/arch/x86/cpu/ivybridge/mrccache.c @@ -105,7 +105,7 @@ static struct mrc_data_container *find_next_mrc_cache(struct fmap_entry *entry, return cache; } -int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry, +int mrccache_update(struct udevice *sf, struct fmap_entry *entry, struct mrc_data_container *cur) { struct mrc_data_container *cache; @@ -135,7 +135,7 @@ int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry, debug("Erasing the MRC cache region of %x bytes at %x\n", entry->length, entry->offset); - ret = spi_flash_erase(sf, entry->offset, entry->length); + ret = spi_flash_erase_dm(sf, entry->offset, entry->length); if (ret) { debug("Failed to erase flash region\n"); return ret; @@ -146,7 +146,8 @@ int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry, /* Write the data out */ offset = (ulong)cache - base_addr + entry->offset; debug("Write MRC cache update to flash at %lx\n", offset); - ret = spi_flash_write(sf, offset, cur->data_size + sizeof(*cur), cur); + ret = spi_flash_write_dm(sf, offset, cur->data_size + sizeof(*cur), + cur); if (ret) { debug("Failed to write to SPI flash\n"); return ret; diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index c50b5de..e95e60e 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -30,7 +30,7 @@ int bridge_silicon_revision(void) result = cpuid(1); stepping = result.eax & 0xf; dev = PCI_BDF(0, 0, 0); - bridge_id = pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0; + bridge_id = x86_pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0; bridge_revision_id = bridge_id | stepping; } @@ -55,7 +55,7 @@ static int get_pcie_bar(u32 *base, u32 *len) *base = 0; *len = 0; - pciexbar_reg = pci_read_config32(dev, PCIEXBAR); + pciexbar_reg = x86_pci_read_config32(dev, PCIEXBAR); if (!(pciexbar_reg & (1 << 0))) return 0; @@ -170,7 +170,7 @@ void northbridge_init(pci_dev_t dev) void northbridge_enable(pci_dev_t dev) { #if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev, SKPAD)) { + switch (x86_pci_read_config32(dev, SKPAD)) { case 0xcafebabe: debug("Normal boot.\n"); apci_set_slp_type(0); diff --git a/arch/x86/cpu/ivybridge/pch.c b/arch/x86/cpu/ivybridge/pch.c index fa04d48..bbab646 100644 --- a/arch/x86/cpu/ivybridge/pch.c +++ b/arch/x86/cpu/ivybridge/pch.c @@ -21,7 +21,7 @@ int pch_silicon_revision(void) dev = PCH_LPC_DEV; if (pch_revision_id < 0) - pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID); + pch_revision_id = x86_pci_read_config8(dev, PCI_REVISION_ID); return pch_revision_id; } @@ -32,7 +32,7 @@ int pch_silicon_type(void) dev = PCH_LPC_DEV; if (pch_type < 0) - pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1); + pch_type = x86_pci_read_config8(dev, PCI_DEVICE_ID + 1); return pch_type; } diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c index 452d1c3..5e90f30 100644 --- a/arch/x86/cpu/ivybridge/pci.c +++ b/arch/x86/cpu/ivybridge/pci.c @@ -10,69 +10,30 @@ */ #include <common.h> +#include <dm.h> #include <pci.h> #include <asm/pci.h> +#include <asm/post.h> #include <asm/arch/bd82x6x.h> #include <asm/arch/pch.h> -static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *table) -{ - u8 secondary; - - hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary); - if (secondary != 0) - pci_hose_scan_bus(hose, secondary); -} - -static struct pci_config_table pci_ivybridge_config_table[] = { - /* vendor, device, class, bus, dev, func */ - { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge }, - {} -}; - -void board_pci_setup_hose(struct pci_controller *hose) -{ - hose->config_table = pci_ivybridge_config_table; - hose->first_busno = 0; - hose->last_busno = 0; - - /* PCI memory space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - - pci_set_region(hose->regions + 2, - CONFIG_PCI_PREF_BUS, - CONFIG_PCI_PREF_PHYS, - CONFIG_PCI_PREF_SIZE, - PCI_REGION_PREFETCH); - - hose->region_count = 3; -} - -int board_pci_pre_scan(struct pci_controller *hose) +static int pci_ivybridge_probe(struct udevice *bus) { + struct pci_controller *hose = dev_get_uclass_priv(bus); pci_dev_t dev; u16 reg16; + if (!(gd->flags & GD_FLG_RELOC)) + return 0; + post_code(0x50); bd82x6x_init(); + post_code(0x51); reg16 = 0xff; dev = PCH_DEV; - reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 = x86_pci_read_config16(dev, PCI_COMMAND); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + x86_pci_write_config16(dev, PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. @@ -82,19 +43,25 @@ int board_pci_pre_scan(struct pci_controller *hose) pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); pci_write_bar32(hose, dev, 0, 0xf0000000); + post_code(0x52); return 0; } -int board_pci_post_scan(struct pci_controller *hose) -{ - int ret; +static const struct dm_pci_ops pci_ivybridge_ops = { + .read_config = pci_x86_read_config, + .write_config = pci_x86_write_config, +}; - ret = bd82x6x_init_pci_devices(); - if (ret) { - printf("bd82x6x_init_pci_devices() failed: %d\n", ret); - return ret; - } +static const struct udevice_id pci_ivybridge_ids[] = { + { .compatible = "intel,pci-ivybridge" }, + { } +}; - return 0; -} +U_BOOT_DRIVER(pci_ivybridge_drv) = { + .name = "pci_ivybridge", + .id = UCLASS_PCI, + .of_match = pci_ivybridge_ids, + .ops = &pci_ivybridge_ops, + .probe = pci_ivybridge_probe, +}; diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/ivybridge/report_platform.c index 69e31b3..4493870 100644 --- a/arch/x86/cpu/ivybridge/report_platform.c +++ b/arch/x86/cpu/ivybridge/report_platform.c @@ -70,14 +70,14 @@ static void report_pch_info(void) u16 dev_id; uint8_t rev_id; - dev_id = pci_read_config16(PCH_LPC_DEV, 2); + dev_id = x86_pci_read_config16(PCH_LPC_DEV, 2); for (i = 0; i < ARRAY_SIZE(pch_table); i++) { if (pch_table[i].dev_id == dev_id) { pch_type = pch_table[i].dev_name; break; } } - rev_id = pci_read_config8(PCH_LPC_DEV, 8); + rev_id = x86_pci_read_config8(PCH_LPC_DEV, 8); debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id, rev_id); } diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c index bbcd47d..e7bf03c 100644 --- a/arch/x86/cpu/ivybridge/sata.c +++ b/arch/x86/cpu/ivybridge/sata.c @@ -14,14 +14,14 @@ static inline u32 sir_read(pci_dev_t dev, int idx) { - pci_write_config32(dev, SATA_SIRI, idx); - return pci_read_config32(dev, SATA_SIRD); + x86_pci_write_config32(dev, SATA_SIRI, idx); + return x86_pci_read_config32(dev, SATA_SIRD); } static inline void sir_write(pci_dev_t dev, int idx, u32 value) { - pci_write_config32(dev, SATA_SIRI, idx); - pci_write_config32(dev, SATA_SIRD, value); + x86_pci_write_config32(dev, SATA_SIRI, idx); + x86_pci_write_config32(dev, SATA_SIRD, value); } static void common_sata_init(pci_dev_t dev, unsigned int port_map) @@ -31,17 +31,17 @@ static void common_sata_init(pci_dev_t dev, unsigned int port_map) /* Set IDE I/O Configuration */ reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); + x86_pci_write_config32(dev, IDE_CONFIG, reg32); /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); + reg16 = x86_pci_read_config16(dev, 0x92); reg16 &= ~0x3f; reg16 |= port_map; - pci_write_config16(dev, 0x92, reg16); + x86_pci_write_config16(dev, 0x92, reg16); /* SATA Initialization register */ port_map &= 0xff; - pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183); + x86_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183); } void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node) @@ -60,7 +60,7 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node) "sata_interface_speed_support", 0); /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, 0x0007); + x86_pci_write_config16(dev, PCI_COMMAND, 0x0007); mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); if (!mode || !strcmp(mode, "ahci")) { @@ -69,18 +69,18 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node) debug("SATA: Controller in AHCI mode\n"); /* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0x0a); + x86_pci_write_config8(dev, INTR_LN, 0x0a); /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); + x86_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0); + x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001); common_sata_init(dev, 0x8000 | port_map); @@ -115,22 +115,22 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node) /* No AHCI: clear AHCI base */ pci_write_bar32(hose, dev, 5, 0x00000000); /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 = x86_pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + x86_pci_write_config16(dev, PCI_COMMAND, reg16); - pci_write_config8(dev, 0x09, 0x80); + x86_pci_write_config8(dev, 0x09, 0x80); /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); + x86_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); + x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); common_sata_init(dev, port_map); } else { @@ -140,31 +140,32 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node) pci_write_bar32(hose, dev, 5, 0x00000000); /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 = x86_pci_read_config16(dev, PCI_COMMAND); reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); + x86_pci_write_config16(dev, PCI_COMMAND, reg16); /* * Native mode capable on both primary and secondary (0xa) * OR'ed with enabled (0x50) = 0xf */ - pci_write_config8(dev, 0x09, 0x8f); + x86_pci_write_config8(dev, 0x09, 0x8f); /* Set Interrupt Line */ /* Interrupt Pin is set by D31IP.PIP */ - pci_write_config8(dev, INTR_LN, 0xff); + x86_pci_write_config8(dev, INTR_LN, 0xff); /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | + x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_PPE0 | IDE_IE0 | IDE_TIME0); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | + x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | IDE_SITRE | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); + x86_pci_write_config16(dev, IDE_SDMA_CNT, + IDE_SSDE0 | IDE_PSDE0); + x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); common_sata_init(dev, port_map); } @@ -221,5 +222,5 @@ void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node) port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); map |= (port_map ^ 0x3f) << 8; - pci_write_config16(dev, 0x90, map); + x86_pci_write_config16(dev, 0x90, map); } diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 766b385..9a6da37 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -89,11 +89,12 @@ void dram_init_banksize(void) } } -static int get_mrc_entry(struct spi_flash **sfp, struct fmap_entry *entry) +static int get_mrc_entry(struct udevice **devp, struct fmap_entry *entry) { const void *blob = gd->fdt_blob; int node, spi_node, mrc_node; int upto; + int ret; /* Find the flash chip within the SPI controller node */ upto = 0; @@ -112,10 +113,13 @@ static int get_mrc_entry(struct spi_flash **sfp, struct fmap_entry *entry) if (fdtdec_read_fmap_entry(blob, mrc_node, "rm-mrc-cache", entry)) return -EINVAL; - if (sfp) { - *sfp = spi_flash_probe_fdt(blob, node, spi_node); - if (!*sfp) - return -EBADF; + if (devp) { + debug("getting sf\n"); + ret = uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, + devp); + debug("ret = %d\n", ret); + if (ret) + return ret; } return 0; @@ -246,7 +250,7 @@ static int sdram_save_mrc_data(void) { struct mrc_data_container *data; struct fmap_entry entry; - struct spi_flash *sf; + struct udevice *sf; int ret; if (!gd->arch.mrc_output_len) @@ -266,7 +270,6 @@ static int sdram_save_mrc_data(void) free(data); err_data: - spi_flash_free(sf); err_entry: if (ret) debug("%s: Failed: %d\n", __func__, ret); @@ -444,7 +447,7 @@ int sdram_initialise(struct pei_data *pei_data) * Send ME init done for SandyBridge here. This is done inside the * SystemAgent binary on IvyBridge */ - done = pci_read_config32(PCH_DEV, PCI_DEVICE_ID); + done = x86_pci_read_config32(PCH_DEV, PCI_DEVICE_ID); done &= BASE_REV_MASK; if (BASE_REV_SNB == done) intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); @@ -615,24 +618,24 @@ static int sdram_find(pci_dev_t dev) */ /* Top of Upper Usable DRAM, including remap */ - touud = pci_read_config32(dev, TOUUD+4); + touud = x86_pci_read_config32(dev, TOUUD+4); touud <<= 32; - touud |= pci_read_config32(dev, TOUUD); + touud |= x86_pci_read_config32(dev, TOUUD); /* Top of Lower Usable DRAM */ - tolud = pci_read_config32(dev, TOLUD); + tolud = x86_pci_read_config32(dev, TOLUD); /* Top of Memory - does not account for any UMA */ - tom = pci_read_config32(dev, 0xa4); + tom = x86_pci_read_config32(dev, 0xa4); tom <<= 32; - tom |= pci_read_config32(dev, 0xa0); + tom |= x86_pci_read_config32(dev, 0xa0); debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom); /* ME UMA needs excluding if total memory <4GB */ - me_base = pci_read_config32(dev, 0x74); + me_base = x86_pci_read_config32(dev, 0x74); me_base <<= 32; - me_base |= pci_read_config32(dev, 0x70); + me_base |= x86_pci_read_config32(dev, 0x70); debug("MEBASE %llx\n", me_base); @@ -650,7 +653,7 @@ static int sdram_find(pci_dev_t dev) } /* Graphics memory comes next */ - ggc = pci_read_config16(dev, GGC); + ggc = x86_pci_read_config16(dev, GGC); if (!(ggc & 2)) { debug("IGD decoded, subtracting "); @@ -670,7 +673,7 @@ static int sdram_find(pci_dev_t dev) } /* Calculate TSEG size from its base which must be below GTT */ - tseg_base = pci_read_config32(dev, 0xb8); + tseg_base = x86_pci_read_config32(dev, 0xb8); uma_size = (uma_memory_base - tseg_base) >> 10; tomk -= uma_size; uma_memory_base = tomk * 1024ULL; diff --git a/arch/x86/cpu/ivybridge/usb_ehci.c b/arch/x86/cpu/ivybridge/usb_ehci.c index 291c971..da11aee 100644 --- a/arch/x86/cpu/ivybridge/usb_ehci.c +++ b/arch/x86/cpu/ivybridge/usb_ehci.c @@ -20,10 +20,10 @@ void bd82x6x_usb_ehci_init(pci_dev_t dev) writel(reg32, RCB_REG(0x35b0)); debug("EHCI: Setting up controller.. "); - reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 = x86_pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER; /* reg32 |= PCI_COMMAND_SERR; */ - pci_write_config32(dev, PCI_COMMAND, reg32); + x86_pci_write_config32(dev, PCI_COMMAND, reg32); debug("done.\n"); } diff --git a/arch/x86/cpu/ivybridge/usb_xhci.c b/arch/x86/cpu/ivybridge/usb_xhci.c index 4a32a7e..f77b804 100644 --- a/arch/x86/cpu/ivybridge/usb_xhci.c +++ b/arch/x86/cpu/ivybridge/usb_xhci.c @@ -16,17 +16,17 @@ void bd82x6x_usb_xhci_init(pci_dev_t dev) debug("XHCI: Setting up controller.. "); /* lock overcurrent map */ - reg32 = pci_read_config32(dev, 0x44); + reg32 = x86_pci_read_config32(dev, 0x44); reg32 |= 1; - pci_write_config32(dev, 0x44, reg32); + x86_pci_write_config32(dev, 0x44, reg32); /* Enable clock gating */ - reg32 = pci_read_config32(dev, 0x40); + reg32 = x86_pci_read_config32(dev, 0x40); reg32 &= ~((1 << 20) | (1 << 21)); reg32 |= (1 << 19) | (1 << 18) | (1 << 17); reg32 |= (1 << 10) | (1 << 9) | (1 << 8); reg32 |= (1 << 31); /* lock */ - pci_write_config32(dev, 0x40, reg32); + x86_pci_write_config32(dev, 0x40, reg32); debug("done.\n"); } diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c index ab1aaaa..e23b233 100644 --- a/arch/x86/cpu/pci.c +++ b/arch/x86/cpu/pci.c @@ -10,9 +10,11 @@ */ #include <common.h> +#include <dm.h> #include <errno.h> #include <malloc.h> #include <pci.h> +#include <asm/io.h> #include <asm/pci.h> DECLARE_GLOBAL_DATA_PTR; @@ -70,7 +72,7 @@ static struct pci_controller *get_hose(void) return pci_bus_to_hose(0); } -unsigned int pci_read_config8(pci_dev_t dev, unsigned where) +unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where) { uint8_t value; @@ -79,7 +81,7 @@ unsigned int pci_read_config8(pci_dev_t dev, unsigned where) return value; } -unsigned int pci_read_config16(pci_dev_t dev, unsigned where) +unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where) { uint16_t value; @@ -88,7 +90,7 @@ unsigned int pci_read_config16(pci_dev_t dev, unsigned where) return value; } -unsigned int pci_read_config32(pci_dev_t dev, unsigned where) +unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where) { uint32_t value; @@ -97,17 +99,55 @@ unsigned int pci_read_config32(pci_dev_t dev, unsigned where) return value; } -void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value) +void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value) { pci_hose_write_config_byte(get_hose(), dev, where, value); } -void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value) +void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value) { pci_hose_write_config_word(get_hose(), dev, where, value); } -void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value) +void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value) { pci_hose_write_config_dword(get_hose(), dev, where, value); } + +int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, + ulong *valuep, enum pci_size_t size) +{ + outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR); + switch (size) { + case PCI_SIZE_8: + *valuep = inb(PCI_REG_DATA + (offset & 3)); + break; + case PCI_SIZE_16: + *valuep = inw(PCI_REG_DATA + (offset & 2)); + break; + case PCI_SIZE_32: + *valuep = inl(PCI_REG_DATA); + break; + } + + return 0; +} + +int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, + ulong value, enum pci_size_t size) +{ + outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR); + switch (size) { + case PCI_SIZE_8: + outb(value, PCI_REG_DATA + (offset & 3)); + break; + case PCI_SIZE_16: + outw(value, PCI_REG_DATA + (offset & 2)); + break; + case PCI_SIZE_32: + outl(value, PCI_REG_DATA); + break; + } + + return 0; +} diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 25edcf7..e4b19c2 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -30,9 +30,9 @@ static void unprotect_spi_flash(void) { u32 bc; - bc = pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8); + bc = x86_pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8); bc |= 0x1; /* unprotect the flash */ - pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc); + x86_pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc); } static void quark_setup_bars(void) diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c index 30ab725..b7236e7 100644 --- a/arch/x86/cpu/queensbay/tnc.c +++ b/arch/x86/cpu/queensbay/tnc.c @@ -16,9 +16,9 @@ static void unprotect_spi_flash(void) { u32 bc; - bc = pci_read_config32(PCH_LPC_DEV, 0xd8); + bc = x86_pci_read_config32(PCH_LPC_DEV, 0xd8); bc |= 0x1; /* unprotect the flash */ - pci_write_config32(PCH_LPC_DEV, 0xd8, bc); + x86_pci_write_config32(PCH_LPC_DEV, 0xd8, bc); } int arch_cpu_init(void) diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 7a66133..431bbd8 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -1,4 +1,5 @@ dtb-y += chromebook_link.dtb \ + chromebox_panther.dtb \ crownbay.dtb \ galileo.dtb \ minnowmax.dtb diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 45ada61..b450c3c 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -8,7 +8,7 @@ compatible = "google,link", "intel,celeron-ivybridge"; aliases { - spi0 = "/spi"; + spi0 = "/pci/pch/spi"; }; config { @@ -151,27 +151,14 @@ }; }; - spi { - #address-cells = <1>; - #size-cells = <0>; - compatible = "intel,ich-spi"; - spi-flash@0 { - #size-cells = <1>; - #address-cells = <1>; - reg = <0>; - compatible = "winbond,w25q64", "spi-flash"; - memory-map = <0xff800000 0x00800000>; - rw-mrc-cache { - label = "rw-mrc-cache"; - /* Alignment: 4k (for updating) */ - reg = <0x003e0000 0x00010000>; - type = "wiped"; - wipe-value = [ff]; - }; - }; - }; - pci { + compatible = "intel,pci-ivybridge", "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000 + 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000 + 0x01000000 0x0 0x1000 0x1000 0 0xefff>; sata { compatible = "intel,pantherpoint-ahci"; intel,sata-mode = "ahci"; @@ -192,8 +179,10 @@ intel,pch-backlight = <0x04000000>; }; - lpc { - compatible = "intel,lpc"; + pch { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,bd82x6x"; + u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; gen-dec = <0x800 0xfc 0x900 0xfc>; @@ -204,17 +193,44 @@ 1 0 0 0 0 0 0 0>; /* Enable EC SMI source */ intel,alt-gp-smi-enable = <0x0100>; + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + #size-cells = <1>; + #address-cells = <1>; + reg = <0>; + compatible = "winbond,w25q64", + "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x003e0000 0x00010000>; + type = "wiped"; + wipe-value = [ff]; + }; + }; + }; - cros-ec@200 { - compatible = "google,cros-ec"; - reg = <0x204 1 0x200 1 0x880 0x80>; - - /* Describes the flash memory within the EC */ + lpc { + compatible = "intel,bd82x6x-lpc"; #address-cells = <1>; - #size-cells = <1>; - flash@8000000 { - reg = <0x08000000 0x20000>; - erase-value = <0xff>; + #size-cells = <0>; + cros-ec@200 { + compatible = "google,cros-ec"; + reg = <0x204 1 0x200 1 0x880 0x80>; + + /* + * Describes the flash memory within + * the EC + */ + #address-cells = <1>; + #size-cells = <1>; + flash@8000000 { + reg = <0x08000000 0x20000>; + erase-value = <0xff>; + }; }; }; }; diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts new file mode 100644 index 0000000..4eccefd --- /dev/null +++ b/arch/x86/dts/chromebox_panther.dts @@ -0,0 +1,64 @@ +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" + +/ { + model = "Google Panther"; + compatible = "google,panther", "intel,haswell"; + + aliases { + spi0 = "/spi"; + }; + + config { + silent-console = <0>; + no-keyboard; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x10>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x30 0x10>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x10>; + bank-name = "C"; + }; + + chosen { + stdout-path = "/serial"; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + #size-cells = <1>; + #address-cells = <1>; + reg = <0>; + compatible = "winbond,w25q64", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + /* Alignment: 4k (for updating) */ + reg = <0x003e0000 0x00010000>; + type = "wiped"; + wipe-value = [ff]; + }; + }; + }; + +}; diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h index e1d9a9b..5ae32f7 100644 --- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h +++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h @@ -12,7 +12,6 @@ void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node); void bd82x6x_pci_init(pci_dev_t dev); void bd82x6x_usb_ehci_init(pci_dev_t dev); void bd82x6x_usb_xhci_init(pci_dev_t dev); -int bd82x6x_init_pci_devices(void); int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, const void *blob, int node); int bd82x6x_init(void); diff --git a/arch/x86/include/asm/arch-ivybridge/mrccache.h b/arch/x86/include/asm/arch-ivybridge/mrccache.h index 968b2ef..1d50ebb 100644 --- a/arch/x86/include/asm/arch-ivybridge/mrccache.h +++ b/arch/x86/include/asm/arch-ivybridge/mrccache.h @@ -20,7 +20,7 @@ __packed struct mrc_data_container { }; struct fmap_entry; -struct spi_flash; +struct udevice; /** * mrccache_find_current() - find the latest MRC cache record @@ -45,7 +45,7 @@ struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry); * @return 0 if updated, -EEXIST if the record is the same as the latest * record, other error if SPI write failed */ -int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry, +int mrccache_update(struct udevice *sf, struct fmap_entry *entry, struct mrc_data_container *cur); #endif diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index a153dd1..a1969ed 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -8,6 +8,8 @@ #ifndef _PCI_I386_H_ #define _PCI_I386_H_ +#include <pci.h> + /* bus mapping constants (used for PCI core initialization) */ #define PCI_REG_ADDR 0xcf8 #define PCI_REG_DATA 0xcfc @@ -48,13 +50,19 @@ int board_pci_post_scan(struct pci_controller *hose); * Simple PCI access routines - these work from either the early PCI hose * or the 'real' one, created after U-Boot has memory available */ -unsigned int pci_read_config8(pci_dev_t dev, unsigned where); -unsigned int pci_read_config16(pci_dev_t dev, unsigned where); -unsigned int pci_read_config32(pci_dev_t dev, unsigned where); +unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where); +unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where); +unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where); + +void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value); +void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value); +void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value); + +int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset, + ulong *valuep, enum pci_size_t size); -void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value); -void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value); -void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value); +int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, + ulong value, enum pci_size_t size); #endif /* __ASSEMBLY__ */ diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index c17f7f0..6c571dd 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -14,10 +14,14 @@ obj-$(CONFIG_HAVE_FSP) += cmd_hob.o obj-y += gcc.o obj-y += init_helpers.o obj-y += interrupts.o +obj-y += lpc-uclass.o obj-y += cmd_mtrr.o obj-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o +ifndef CONFIG_DM_PCI obj-$(CONFIG_PCI) += pci_type1.o +endif +obj-y += pch-uclass.o obj-y += relocate.o obj-y += physmem.o obj-$(CONFIG_X86_RAMTEST) += ramtest.o diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c index b0e2ecb..290990a 100644 --- a/arch/x86/lib/bios_interrupts.c +++ b/arch/x86/lib/bios_interrupts.c @@ -172,28 +172,28 @@ int int1a_handler(void) } switch (func) { case 0xb108: /* Read Config Byte */ - byte = pci_read_config8(dev, reg); + byte = x86_pci_read_config8(dev, reg); M.x86.R_ECX = byte; break; case 0xb109: /* Read Config Word */ - word = pci_read_config16(dev, reg); + word = x86_pci_read_config16(dev, reg); M.x86.R_ECX = word; break; case 0xb10a: /* Read Config Dword */ - dword = pci_read_config32(dev, reg); + dword = x86_pci_read_config32(dev, reg); M.x86.R_ECX = dword; break; case 0xb10b: /* Write Config Byte */ byte = M.x86.R_ECX; - pci_write_config8(dev, reg, byte); + x86_pci_write_config8(dev, reg, byte); break; case 0xb10c: /* Write Config Word */ word = M.x86.R_ECX; - pci_write_config16(dev, reg, word); + x86_pci_write_config16(dev, reg, word); break; case 0xb10d: /* Write Config Dword */ dword = M.x86.R_ECX; - pci_write_config32(dev, reg, dword); + x86_pci_write_config32(dev, reg, dword); break; } diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 5097ca2..4fd47fc 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -89,11 +89,3 @@ int init_bd_struct_r(void) return 0; } - -int init_func_spi(void) -{ - puts("SPI: "); - spi_init(); - puts("ready\n"); - return 0; -} diff --git a/arch/x86/lib/lpc-uclass.c b/arch/x86/lib/lpc-uclass.c new file mode 100644 index 0000000..6aeb4d4 --- /dev/null +++ b/arch/x86/lib/lpc-uclass.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <dm/root.h> + +static int lpc_uclass_post_bind(struct udevice *bus) +{ + /* + * Scan the device tree for devices + * + * Before relocation, only bind devices marked for pre-relocation + * use. + */ + return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset, + gd->flags & GD_FLG_RELOC ? false : true); +} + +UCLASS_DRIVER(lpc) = { + .id = UCLASS_LPC, + .name = "lpc", + .post_bind = lpc_uclass_post_bind, +}; diff --git a/arch/x86/lib/pch-uclass.c b/arch/x86/lib/pch-uclass.c new file mode 100644 index 0000000..d1082e1 --- /dev/null +++ b/arch/x86/lib/pch-uclass.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <dm/root.h> + +static int pch_uclass_post_bind(struct udevice *bus) +{ + /* + * Scan the device tree for devices + * + * Before relocation, only bind devices marked for pre-relocation + * use. + */ + return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset, + gd->flags & GD_FLG_RELOC ? false : true); +} + +UCLASS_DRIVER(pch) = { + .id = UCLASS_PCH, + .name = "pch", + .post_bind = pch_uclass_post_bind, +}; |