diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/dts/Makefile | 24 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-common32.dtsi | 8 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-ld11-ref.dts (renamed from arch/arm/dts/uniphier-ph1-ld11-ref.dts) | 9 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-ld11.dtsi (renamed from arch/arm/dts/uniphier-ph1-ld11.dtsi) | 16 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-ld20-ref.dts (renamed from arch/arm/dts/uniphier-ph1-ld20-ref.dts) | 11 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-ld20.dtsi (renamed from arch/arm/dts/uniphier-ph1-ld20.dtsi) | 9 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-ld4-ref.dts (renamed from arch/arm/dts/uniphier-ph1-ld4-ref.dts) | 11 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-ld4.dtsi (renamed from arch/arm/dts/uniphier-ph1-ld4.dtsi) | 24 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-ld6b-ref.dts (renamed from arch/arm/dts/uniphier-ph1-ld6b-ref.dts) | 11 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-ld6b.dtsi | 32 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-ph1-ld6b.dtsi | 31 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-pro4-ace.dts (renamed from arch/arm/dts/uniphier-ph1-pro4-ace.dts) | 15 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-pro4-ref.dts (renamed from arch/arm/dts/uniphier-ph1-pro4-ref.dts) | 11 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-pro4-sanji.dts (renamed from arch/arm/dts/uniphier-ph1-pro4-sanji.dts) | 15 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-pro4.dtsi (renamed from arch/arm/dts/uniphier-ph1-pro4.dtsi) | 23 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-pro5-4kbox.dts (renamed from arch/arm/dts/uniphier-ph1-pro5-4kbox.dts) | 11 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-pro5.dtsi (renamed from arch/arm/dts/uniphier-ph1-pro5.dtsi) | 14 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-pxs2-gentil.dts (renamed from arch/arm/dts/uniphier-proxstream2-gentil.dts) | 16 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-pxs2-vodka.dts (renamed from arch/arm/dts/uniphier-proxstream2-vodka.dts) | 11 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-pxs2.dtsi (renamed from arch/arm/dts/uniphier-proxstream2.dtsi) | 16 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-sld3-ref.dts (renamed from arch/arm/dts/uniphier-ph1-sld3-ref.dts) | 11 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-sld3.dtsi (renamed from arch/arm/dts/uniphier-ph1-sld3.dtsi) | 48 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-sld8-ref.dts (renamed from arch/arm/dts/uniphier-ph1-sld8-ref.dts) | 11 | ||||
-rw-r--r-- | arch/arm/dts/uniphier-sld8.dtsi (renamed from arch/arm/dts/uniphier-ph1-sld8.dtsi) | 24 | ||||
-rw-r--r-- | arch/arm/mach-uniphier/boards.c | 26 |
25 files changed, 274 insertions, 164 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8458f6b..8dbaea0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -79,18 +79,18 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-xp-theadorable.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ - uniphier-ph1-ld11-ref.dtb \ - uniphier-ph1-ld20-ref.dtb \ - uniphier-ph1-ld4-ref.dtb \ - uniphier-ph1-ld6b-ref.dtb \ - uniphier-ph1-pro4-ace.dtb \ - uniphier-ph1-pro4-ref.dtb \ - uniphier-ph1-pro4-sanji.dtb \ - uniphier-ph1-pro5-4kbox.dtb \ - uniphier-ph1-sld3-ref.dtb \ - uniphier-ph1-sld8-ref.dtb \ - uniphier-proxstream2-gentil.dtb \ - uniphier-proxstream2-vodka.dtb + uniphier-ld11-ref.dtb \ + uniphier-ld20-ref.dtb \ + uniphier-ld4-ref.dtb \ + uniphier-ld6b-ref.dtb \ + uniphier-pro4-ace.dtb \ + uniphier-pro4-ref.dtb \ + uniphier-pro4-sanji.dtb \ + uniphier-pro5-4kbox.dtb \ + uniphier-pxs2-gentil.dtb \ + uniphier-pxs2-vodka.dtb \ + uniphier-sld3-ref.dtb \ + uniphier-sld8-ref.dtb dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zc706.dtb \ zynq-zed.dtb \ diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi index e441033..f87e320 100644 --- a/arch/arm/dts/uniphier-common32.dtsi +++ b/arch/arm/dts/uniphier-common32.dtsi @@ -1,7 +1,8 @@ /* * Device Tree Source commonly used by UniPhier ARM SoCs * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ @@ -9,6 +10,11 @@ /include/ "skeleton.dtsi" / { + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { refclk: ref { #clock-cells = <0>; diff --git a/arch/arm/dts/uniphier-ph1-ld11-ref.dts b/arch/arm/dts/uniphier-ld11-ref.dts index ca31026..ea11198 100644 --- a/arch/arm/dts/uniphier-ph1-ld11-ref.dts +++ b/arch/arm/dts/uniphier-ld11-ref.dts @@ -1,5 +1,5 @@ /* - * Device Tree Source for UniPhier PH1-LD11 Reference Board + * Device Tree Source for UniPhier LD11 Reference Board * * Copyright (C) 2016 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> @@ -8,12 +8,13 @@ */ /dts-v1/; -/include/ "uniphier-ph1-ld11.dtsi" +/include/ "uniphier-ld11.dtsi" +/include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { - model = "UniPhier PH1-LD11 Reference Board"; - compatible = "socionext,ph1-ld11-ref", "socionext,ph1-ld11"; + model = "UniPhier LD11 Reference Board"; + compatible = "socionext,uniphier-ld11-ref", "socionext,uniphier-ld11"; aliases { serial0 = &serial0; diff --git a/arch/arm/dts/uniphier-ph1-ld11.dtsi b/arch/arm/dts/uniphier-ld11.dtsi index 0bdbbdd..a95cb6e 100644 --- a/arch/arm/dts/uniphier-ph1-ld11.dtsi +++ b/arch/arm/dts/uniphier-ld11.dtsi @@ -1,5 +1,5 @@ /* - * Device Tree Source for UniPhier PH1-LD11 SoC + * Device Tree Source for UniPhier LD11 SoC * * Copyright (C) 2016 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> @@ -10,7 +10,7 @@ /memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ / { - compatible = "socionext,ph1-ld11"; + compatible = "socionext,uniphier-ld11"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; @@ -230,7 +230,9 @@ interrupts = <0 243 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 3>, <&mio_clk 6>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; }; usb1: usb@5a810100 { @@ -240,7 +242,9 @@ interrupts = <0 244 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 4>, <&mio_clk 6>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; }; usb2: usb@5a820100 { @@ -250,7 +254,9 @@ interrupts = <0 245 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 5>, <&mio_clk 6>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; }; mioctrl@5b3e0000 { diff --git a/arch/arm/dts/uniphier-ph1-ld20-ref.dts b/arch/arm/dts/uniphier-ld20-ref.dts index e4e8d76..044e000 100644 --- a/arch/arm/dts/uniphier-ph1-ld20-ref.dts +++ b/arch/arm/dts/uniphier-ld20-ref.dts @@ -1,19 +1,20 @@ /* - * Device Tree Source for UniPhier PH1-LD20 Reference Board + * Device Tree Source for UniPhier LD20 Reference Board * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; -/include/ "uniphier-ph1-ld20.dtsi" +/include/ "uniphier-ld20.dtsi" /include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { - model = "UniPhier PH1-LD20 Reference Board"; - compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20"; + model = "UniPhier LD20 Reference Board"; + compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20"; aliases { serial0 = &serial0; diff --git a/arch/arm/dts/uniphier-ph1-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi index 7f97f88..29a84ae 100644 --- a/arch/arm/dts/uniphier-ph1-ld20.dtsi +++ b/arch/arm/dts/uniphier-ld20.dtsi @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-LD20 SoC + * Device Tree Source for UniPhier LD20 SoC * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ @@ -9,7 +10,7 @@ /memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */ / { - compatible = "socionext,ph1-ld20"; + compatible = "socionext,uniphier-ld20"; #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&gic>; @@ -271,6 +272,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sd>; clocks = <&mio_clk 0>; + reset-names = "host"; + resets = <&mio_rst 0>; bus-width = <4>; }; diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ld4-ref.dts index 36de7e3..0f4bd9b 100644 --- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts +++ b/arch/arm/dts/uniphier-ld4-ref.dts @@ -1,19 +1,20 @@ /* - * Device Tree Source for UniPhier PH1-LD4 Reference Board + * Device Tree Source for UniPhier LD4 Reference Board * - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; -/include/ "uniphier-ph1-ld4.dtsi" +/include/ "uniphier-ld4.dtsi" /include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { - model = "UniPhier PH1-LD4 Reference Board"; - compatible = "socionext,ph1-ld4-ref", "socionext,ph1-ld4"; + model = "UniPhier LD4 Reference Board"; + compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4"; memory { device_type = "memory"; diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ld4.dtsi index e4884b9..9f555df 100644 --- a/arch/arm/dts/uniphier-ph1-ld4.dtsi +++ b/arch/arm/dts/uniphier-ld4.dtsi @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-LD4 SoC + * Device Tree Source for UniPhier LD4 SoC * - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ @@ -9,7 +10,7 @@ /include/ "uniphier-common32.dtsi" / { - compatible = "socionext,ph1-ld4"; + compatible = "socionext,uniphier-ld4"; cpus { #address-cells = <1>; @@ -19,6 +20,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; @@ -223,6 +225,8 @@ pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; clocks = <&mio_clk 0>; + reset-names = "host", "bridge"; + resets = <&mio_rst 0>, <&mio_rst 3>; bus-width = <4>; }; @@ -235,6 +239,8 @@ pinctrl-0 = <&pinctrl_emmc>; pinctrl-1 = <&pinctrl_emmc_1v8>; clocks = <&mio_clk 1>; + reset-names = "host", "bridge", "hw-reset"; + resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; bus-width = <8>; non-removable; }; @@ -246,7 +252,9 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 3>, <&mio_clk 6>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; }; usb1: usb@5a810100 { @@ -256,7 +264,9 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 4>, <&mio_clk 6>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; }; usb2: usb@5a820100 { @@ -266,7 +276,9 @@ interrupts = <0 82 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 5>, <&mio_clk 6>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; }; aidet@61830000 { diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ld6b-ref.dts index e29a6ea..4da3c63 100644 --- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts +++ b/arch/arm/dts/uniphier-ld6b-ref.dts @@ -1,19 +1,20 @@ /* - * Device Tree Source for UniPhier PH1-LD6b Reference Board + * Device Tree Source for UniPhier LD6b Reference Board * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; -/include/ "uniphier-ph1-ld6b.dtsi" +/include/ "uniphier-ld6b.dtsi" /include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { - model = "UniPhier PH1-LD6b Reference Board"; - compatible = "socionext,ph1-ld6b-ref", "socionext,ph1-ld6b"; + model = "UniPhier LD6b Reference Board"; + compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b"; memory { device_type = "memory"; diff --git a/arch/arm/dts/uniphier-ld6b.dtsi b/arch/arm/dts/uniphier-ld6b.dtsi new file mode 100644 index 0000000..9870047 --- /dev/null +++ b/arch/arm/dts/uniphier-ld6b.dtsi @@ -0,0 +1,32 @@ +/* + * Device Tree Source for UniPhier LD6b SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/* + * LD6b consists of two silicon dies: D-chip and A-chip. + * The D-chip (digital chip) is the same as the PXs2 die. + * Reuse the PXs2 device tree with some properties overridden. + */ +/include/ "uniphier-pxs2.dtsi" + +/ { + compatible = "socionext,uniphier-ld6b"; +}; + +/* UART3 unavailable: the pads are not wired to the package balls */ +&serial3 { + status = "disabled"; +}; + +/* + * LD6b and PXs2 have completely different packages, + * which makes the pinctrl driver unshareable. + */ +&pinctrl { + compatible = "socionext,uniphier-ld6b-pinctrl"; +}; diff --git a/arch/arm/dts/uniphier-ph1-ld6b.dtsi b/arch/arm/dts/uniphier-ph1-ld6b.dtsi deleted file mode 100644 index e8110ee..0000000 --- a/arch/arm/dts/uniphier-ph1-ld6b.dtsi +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD6b SoC - * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ X11 - */ - -/* - * PH1-LD6b consists of two silicon dies: D-chip and A-chip. - * The D-chip (digital chip) is the same as the ProXstream2 die. - * Reuse the ProXstream2 device tree with some properties overridden. - */ -/include/ "uniphier-proxstream2.dtsi" - -/ { - compatible = "socionext,ph1-ld6b"; -}; - -/* UART3 unavailable: the pads are not wired to the package balls */ -&serial3 { - status = "disabled"; -}; - -/* - * PH1-LD6b and ProXstream2 have completely different packages, - * which makes the pinctrl driver unshareable. - */ -&pinctrl { - compatible = "socionext,uniphier-ld6b-pinctrl"; -}; diff --git a/arch/arm/dts/uniphier-ph1-pro4-ace.dts b/arch/arm/dts/uniphier-pro4-ace.dts index d8740cc..f70bc82 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-ace.dts +++ b/arch/arm/dts/uniphier-pro4-ace.dts @@ -1,17 +1,18 @@ /* - * Device Tree Source for UniPhier PH1-Pro4 Ace Board + * Device Tree Source for UniPhier Pro4 Ace Board * - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; -/include/ "uniphier-ph1-pro4.dtsi" +/include/ "uniphier-pro4.dtsi" / { - model = "UniPhier PH1-Pro4 Ace Board"; - compatible = "socionext,ph1-pro4-ace", "socionext,ph1-pro4"; + model = "UniPhier Pro4 Ace Board"; + compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4"; memory { device_type = "memory"; @@ -50,8 +51,8 @@ &i2c0 { status = "okay"; - eeprom { - compatible = "24c64", "i2c-eeprom"; + eeprom@54 { + compatible = "st,24c64", "i2c-eeprom"; reg = <0x54>; u-boot,i2c-offset-len = <2>; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-pro4-ref.dts index 4a2de08..2d49b3e 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts +++ b/arch/arm/dts/uniphier-pro4-ref.dts @@ -1,19 +1,20 @@ /* - * Device Tree Source for UniPhier PH1-Pro4 Reference Board + * Device Tree Source for UniPhier Pro4 Reference Board * - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; -/include/ "uniphier-ph1-pro4.dtsi" +/include/ "uniphier-pro4.dtsi" /include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { - model = "UniPhier PH1-Pro4 Reference Board"; - compatible = "socionext,ph1-pro4-ref", "socionext,ph1-pro4"; + model = "UniPhier Pro4 Reference Board"; + compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4"; memory { device_type = "memory"; diff --git a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts b/arch/arm/dts/uniphier-pro4-sanji.dts index 3f178d2..d43f725 100644 --- a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts +++ b/arch/arm/dts/uniphier-pro4-sanji.dts @@ -1,17 +1,18 @@ /* - * Device Tree Source for UniPhier PH1-Pro4 Sanji Board + * Device Tree Source for UniPhier Pro4 Sanji Board * - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; -/include/ "uniphier-ph1-pro4.dtsi" +/include/ "uniphier-pro4.dtsi" / { - model = "UniPhier PH1-Pro4 Sanji Board"; - compatible = "socionext,ph1-pro4-sanji", "socionext,ph1-pro4"; + model = "UniPhier Pro4 Sanji Board"; + compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4"; memory { device_type = "memory"; @@ -45,8 +46,8 @@ &i2c0 { status = "okay"; - eeprom { - compatible = "24c64", "i2c-eeprom"; + eeprom@54 { + compatible = "st,24c64", "i2c-eeprom"; reg = <0x54>; u-boot,i2c-offset-len = <2>; }; diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi index 192ce84..aa80ea4 100644 --- a/arch/arm/dts/uniphier-ph1-pro4.dtsi +++ b/arch/arm/dts/uniphier-pro4.dtsi @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-Pro4 SoC + * Device Tree Source for UniPhier Pro4 SoC * - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ @@ -9,17 +10,17 @@ /include/ "uniphier-common32.dtsi" / { - compatible = "socionext,ph1-pro4"; + compatible = "socionext,uniphier-pro4"; cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -27,6 +28,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; @@ -352,6 +354,8 @@ pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; clocks = <&mio_clk 0>; + reset-names = "host", "bridge"; + resets = <&mio_rst 0>, <&mio_rst 3>; bus-width = <4>; }; @@ -364,6 +368,8 @@ pinctrl-0 = <&pinctrl_emmc>; pinctrl-1 = <&pinctrl_emmc_1v8>; clocks = <&mio_clk 1>; + reset-names = "host", "bridge", "hw-reset"; + resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; bus-width = <8>; non-removable; }; @@ -377,6 +383,7 @@ pinctrl-0 = <&pinctrl_sd1>; pinctrl-1 = <&pinctrl_sd1_1v8>; clocks = <&mio_clk 2>; + resets = <&mio_rst 2>, <&mio_rst 5>; bus-width = <4>; }; @@ -387,7 +394,9 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 3>, <&mio_clk 6>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; }; usb3: usb@5a810100 { @@ -397,7 +406,9 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb3>; - clocks = <&mio_clk 4>, <&mio_clk 6>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; }; aidet@5fc20000 { diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-pro5-4kbox.dts index 682b795..ffc21a7 100644 --- a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts +++ b/arch/arm/dts/uniphier-pro5-4kbox.dts @@ -1,17 +1,18 @@ /* - * Device Tree Source for UniPhier PH1-Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0) + * Device Tree Source for UniPhier Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0) * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; -/include/ "uniphier-ph1-pro5.dtsi" +/include/ "uniphier-pro5.dtsi" / { - model = "UniPhier PH1-Pro5 4KBOX Board"; - compatible = "socionext,ph1-pro5-4kbox", "socionext,ph1-pro5"; + model = "UniPhier Pro5 4KBOX Board"; + compatible = "socionext,uniphier-pro5-4kbox", "socionext,uniphier-pro5"; memory { device_type = "memory"; diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi index 22a70b1..97edc89 100644 --- a/arch/arm/dts/uniphier-ph1-pro5.dtsi +++ b/arch/arm/dts/uniphier-pro5.dtsi @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-Pro5 SoC + * Device Tree Source for UniPhier Pro5 SoC * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ @@ -9,17 +10,17 @@ /include/ "uniphier-common32.dtsi" / { - compatible = "socionext,ph1-pro5"; + compatible = "socionext,uniphier-pro5"; cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -27,6 +28,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; @@ -362,6 +364,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; clocks = <&mio_clk 1>; + reset-names = "host", "hw-reset"; + resets = <&mio_rst 1>, <&mio_rst 6>; bus-width = <8>; non-removable; }; @@ -375,6 +379,8 @@ pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; clocks = <&mio_clk 0>; + reset-names = "host"; + resets = <&mio_rst 0>; bus-width = <4>; }; diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-pxs2-gentil.dts index 7233dc6..a98e758 100644 --- a/arch/arm/dts/uniphier-proxstream2-gentil.dts +++ b/arch/arm/dts/uniphier-pxs2-gentil.dts @@ -1,17 +1,19 @@ /* - * Device Tree Source for UniPhier ProXstream2 Gentil Board + * Device Tree Source for UniPhier PXs2 Gentil Board * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; -/include/ "uniphier-proxstream2.dtsi" +/include/ "uniphier-pxs2.dtsi" / { - model = "UniPhier ProXstream2 Gentil Board"; - compatible = "socionext,proxstream2-gentil", "socionext,proxstream2"; + model = "UniPhier PXs2 Gentil Board"; + compatible = "socionext,uniphier-pxs2-gentil", + "socionext,uniphier-pxs2"; memory { device_type = "memory"; @@ -41,8 +43,8 @@ &i2c0 { status = "okay"; - eeprom { - compatible = "24c64", "i2c-eeprom"; + eeprom@54 { + compatible = "st,24c64", "i2c-eeprom"; reg = <0x54>; u-boot,i2c-offset-len = <2>; }; diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-pxs2-vodka.dts index 30ea270..78a52a8 100644 --- a/arch/arm/dts/uniphier-proxstream2-vodka.dts +++ b/arch/arm/dts/uniphier-pxs2-vodka.dts @@ -1,17 +1,18 @@ /* - * Device Tree Source for UniPhier ProXstream2 Vodka Board + * Device Tree Source for UniPhier PXs2 Vodka Board * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ /dts-v1/; -/include/ "uniphier-proxstream2.dtsi" +/include/ "uniphier-pxs2.dtsi" / { - model = "UniPhier ProXstream2 Vodka Board"; - compatible = "socionext,proxstream2-vodka", "socionext,proxstream2"; + model = "UniPhier PXs2 Vodka Board"; + compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2"; memory { device_type = "memory"; diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi index 609cbaa..b64107b 100644 --- a/arch/arm/dts/uniphier-proxstream2.dtsi +++ b/arch/arm/dts/uniphier-pxs2.dtsi @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier ProXstream2 SoC + * Device Tree Source for UniPhier PXs2 SoC * - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ @@ -9,17 +10,17 @@ /include/ "uniphier-common32.dtsi" / { - compatible = "socionext,proxstream2"; + compatible = "socionext,uniphier-pxs2"; cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -27,6 +28,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -34,6 +36,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -41,6 +44,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; @@ -361,6 +365,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_emmc>; clocks = <&mio_clk 1>; + reset-names = "host", "hw-reset"; + resets = <&mio_rst 1>, <&mio_rst 6>; bus-width = <8>; non-removable; }; @@ -374,6 +380,8 @@ pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; clocks = <&mio_clk 0>; + reset-names = "host"; + resets = <&mio_rst 0>; bus-width = <4>; }; diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-sld3-ref.dts index 116e571..f35500d 100644 --- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts +++ b/arch/arm/dts/uniphier-sld3-ref.dts @@ -1,19 +1,20 @@ /* - * Device Tree Source for UniPhier PH1-sLD3 Reference Board + * Device Tree Source for UniPhier sLD3 Reference Board * - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; -/include/ "uniphier-ph1-sld3.dtsi" +/include/ "uniphier-sld3.dtsi" /include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { - model = "UniPhier PH1-sLD3 Reference Board"; - compatible = "socionext,ph1-sld3-ref", "socionext,ph1-sld3"; + model = "UniPhier sLD3 Reference Board"; + compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3"; memory { device_type = "memory"; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-sld3.dtsi index a554b08..f5c5487 100644 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/dts/uniphier-sld3.dtsi @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-sLD3 SoC + * Device Tree Source for UniPhier sLD3 SoC * - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ @@ -9,26 +10,34 @@ /include/ "skeleton.dtsi" / { - compatible = "socionext,ph1-sld3"; + compatible = "socionext,uniphier-sld3"; cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; + next-level-cache = <&l2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + enable-method = "psci"; + next-level-cache = <&l2>; }; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { refclk: ref { #clock-cells = <0>; @@ -79,6 +88,18 @@ <0x20000100 0x100>; }; + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(512 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + serial0: serial@54006800 { compatible = "socionext,uniphier-uart"; status = "disabled"; @@ -280,6 +301,7 @@ system_bus: system-bus@58c00000 { compatible = "socionext,uniphier-system-bus"; + status = "disabled"; reg = <0x58c00000 0x400>; #address-cells = <2>; #size-cells = <1>; @@ -317,6 +339,7 @@ pinctrl-0 = <&pinctrl_emmc>; pinctrl-1 = <&pinctrl_emmc_1v8>; clocks = <&mio_clk 1>; + resets = <&mio_rst 1>, <&mio_rst 4>; bus-width = <8>; non-removable; }; @@ -330,6 +353,7 @@ pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; clocks = <&mio_clk 0>; + resets = <&mio_rst 0>, <&mio_rst 3>; bus-width = <4>; }; @@ -340,7 +364,9 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 3>, <&mio_clk 6>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; }; usb1: usb@5a810100 { @@ -350,7 +376,9 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 4>, <&mio_clk 6>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; }; usb2: usb@5a820100 { @@ -360,7 +388,9 @@ interrupts = <0 82 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 5>, <&mio_clk 6>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; }; usb3: usb@5a830100 { @@ -370,7 +400,9 @@ interrupts = <0 83 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb3>; - clocks = <&mio_clk 7>, <&mio_clk 6>; + clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>, + <&mio_rst 15>; }; soc-glue@5f800000 { diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-sld8-ref.dts index 9af012c..6c0544b 100644 --- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts +++ b/arch/arm/dts/uniphier-sld8-ref.dts @@ -1,19 +1,20 @@ /* - * Device Tree Source for UniPhier PH1-sLD8 Reference Board + * Device Tree Source for UniPhier sLD8 Reference Board * - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ /dts-v1/; -/include/ "uniphier-ph1-sld8.dtsi" +/include/ "uniphier-sld8.dtsi" /include/ "uniphier-ref-daughter.dtsi" /include/ "uniphier-support-card.dtsi" / { - model = "UniPhier PH1-sLD8 Reference Board"; - compatible = "socionext,ph1-sld8-ref", "socionext,ph1-sld8"; + model = "UniPhier sLD8 Reference Board"; + compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8"; memory { device_type = "memory"; diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-sld8.dtsi index 1ecce50..b8f6d67 100644 --- a/arch/arm/dts/uniphier-ph1-sld8.dtsi +++ b/arch/arm/dts/uniphier-sld8.dtsi @@ -1,7 +1,8 @@ /* - * Device Tree Source for UniPhier PH1-sLD8 SoC + * Device Tree Source for UniPhier sLD8 SoC * - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ X11 */ @@ -9,7 +10,7 @@ /include/ "uniphier-common32.dtsi" / { - compatible = "socionext,ph1-sld8"; + compatible = "socionext,uniphier-sld8"; cpus { #address-cells = <1>; @@ -19,6 +20,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; @@ -223,6 +225,8 @@ pinctrl-0 = <&pinctrl_sd>; pinctrl-1 = <&pinctrl_sd_1v8>; clocks = <&mio_clk 0>; + reset-names = "host", "bridge"; + resets = <&mio_rst 0>, <&mio_rst 3>; bus-width = <4>; }; @@ -235,6 +239,8 @@ pinctrl-0 = <&pinctrl_emmc>; pinctrl-1 = <&pinctrl_emmc_1v8>; clocks = <&mio_clk 1>; + reset-names = "host", "bridge", "hw-reset"; + resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; bus-width = <8>; non-removable; }; @@ -246,7 +252,9 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; - clocks = <&mio_clk 3>, <&mio_clk 6>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, + <&mio_rst 12>; }; usb1: usb@5a810100 { @@ -256,7 +264,9 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; - clocks = <&mio_clk 4>, <&mio_clk 6>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, + <&mio_rst 13>; }; usb2: usb@5a820100 { @@ -266,7 +276,9 @@ interrupts = <0 82 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; - clocks = <&mio_clk 5>, <&mio_clk 6>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, + <&mio_rst 14>; }; aidet@61830000 { diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index 79b1d20..0596451 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -250,35 +250,35 @@ struct uniphier_board_id { static const struct uniphier_board_id uniphier_boards[] = { #if defined(CONFIG_ARCH_UNIPHIER_SLD3) - { "socionext,ph1-sld3", &uniphier_sld3_data, }, + { "socionext,uniphier-sld3", &uniphier_sld3_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) - { "socionext,ph1-ld4", &uniphier_ld4_data, }, + { "socionext,uniphier-ld4", &uniphier_ld4_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO4) - { "socionext,ph1-pro4-ace", &uniphier_pro4_2g_data, }, - { "socionext,ph1-pro4-sanji", &uniphier_pro4_2g_data, }, - { "socionext,ph1-pro4", &uniphier_pro4_data, }, + { "socionext,uniphier-pro4-ace", &uniphier_pro4_2g_data, }, + { "socionext,uniphier-pro4-sanji", &uniphier_pro4_2g_data, }, + { "socionext,uniphier-pro4", &uniphier_pro4_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_SLD8) - { "socionext,ph1-sld8", &uniphier_sld8_data, }, + { "socionext,uniphier-sld8", &uniphier_sld8_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO5) - { "socionext,ph1-pro5", &uniphier_pro5_data, }, + { "socionext,uniphier-pro5", &uniphier_pro5_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_PXS2) - { "socionext,proxstream2", &uniphier_pxs2_data, }, + { "socionext,uniphier-pxs2", &uniphier_pxs2_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD6B) - { "socionext,ph1-ld6b", &uniphier_ld6b_data, }, + { "socionext,uniphier-ld6b", &uniphier_ld6b_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD11) - { "socionext,ph1-ld11", &uniphier_ld11_data, }, + { "socionext,uniphier-ld11", &uniphier_ld11_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) - { "socionext,ph1-ld21", &uniphier_ld21_data, }, - { "socionext,ph1-ld20-ref", &uniphier_ld20_ref_data, }, - { "socionext,ph1-ld20", &uniphier_ld20_data, }, + { "socionext,uniphier-ld21", &uniphier_ld21_data, }, + { "socionext,uniphier-ld20-ref", &uniphier_ld20_ref_data, }, + { "socionext,uniphier-ld20", &uniphier_ld20_data, }, #endif }; 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