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-rw-r--r--arch/arm/Kconfig9
-rw-r--r--arch/arm/cpu/armv7/ls102xa/Makefile1
-rw-r--r--arch/arm/cpu/armv7/ls102xa/cpu.c3
-rw-r--r--arch/arm/cpu/armv7/ls102xa/fdt.c2
-rw-r--r--arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c42
-rw-r--r--arch/arm/cpu/armv8/Makefile2
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/Makefile30
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/README.lsch210
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 (renamed from arch/arm/cpu/armv8/fsl-lsch3/README)2
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c (renamed from arch/arm/cpu/armv8/fsl-lsch3/cpu.c)273
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.h (renamed from arch/arm/cpu/armv8/fsl-lsch3/cpu.h)2
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fdt.c (renamed from arch/arm/cpu/armv8/fsl-lsch3/fdt.c)25
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c117
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c180
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c (renamed from arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c)8
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c (renamed from arch/arm/cpu/armv8/fsl-lsch3/speed.c)12
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S (renamed from arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S)14
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c86
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c (renamed from arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c)3
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/mp.c (renamed from arch/arm/cpu/armv8/fsl-lsch3/mp.c)30
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/soc.c (renamed from arch/arm/cpu/armv8/fsl-lsch3/soc.c)42
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/spl.c79
-rw-r--r--arch/arm/cpu/armv8/fsl-lsch3/Makefile13
-rw-r--r--arch/arm/cpu/armv8/fsl-lsch3/speed.h7
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/clock.h (renamed from arch/arm/include/asm/arch-fsl-lsch3/clock.h)8
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/config.h143
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/cpu.h229
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/fdt.h (renamed from arch/arm/include/asm/arch-fsl-lsch3/fdt.h)4
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h157
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h555
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h (renamed from arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h)119
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h55
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h (renamed from arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h)0
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/mmu.h10
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/mp.h (renamed from arch/arm/cpu/armv8/fsl-lsch3/mp.h)10
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/ns_access.h158
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/soc.h53
-rw-r--r--arch/arm/include/asm/arch-fsl-layerscape/speed.h10
-rw-r--r--arch/arm/include/asm/arch-fsl-lsch3/config.h185
-rw-r--r--arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h67
-rw-r--r--arch/arm/include/asm/arch-fsl-lsch3/gpio.h9
-rw-r--r--arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h13
-rw-r--r--arch/arm/include/asm/arch-fsl-lsch3/soc.h28
-rw-r--r--arch/arm/include/asm/arch-ls102xa/config.h15
-rw-r--r--arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h25
-rw-r--r--arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h11
-rw-r--r--arch/arm/include/asm/arch-ls102xa/ns_access.h103
-rw-r--r--arch/arm/include/asm/armv8/mmu.h1
-rw-r--r--arch/arm/include/asm/config.h7
-rw-r--r--arch/arm/include/asm/io.h4
-rw-r--r--arch/arm/include/asm/types.h10
-rw-r--r--arch/powerpc/include/asm/fsl_dtsec.h231
-rw-r--r--arch/powerpc/include/asm/fsl_fman.h463
-rw-r--r--arch/powerpc/include/asm/fsl_tgec.h202
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h2
55 files changed, 2362 insertions, 1517 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2632099..3992f69 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -627,6 +627,14 @@ config TARGET_LS1021ATWR
select CPU_V7
select SUPPORT_SPL
+config TARGET_LS1043ARDB
+ bool "Support ls1043ardb"
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select SUPPORT_SPL
+ help
+ Support for Freescale LS1043ARDB platform.
+
config TARGET_H2200
bool "Support h2200"
select CPU_PXA
@@ -743,6 +751,7 @@ source "board/freescale/ls2085aqds/Kconfig"
source "board/freescale/ls2085ardb/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
+source "board/freescale/ls1043ardb/Kconfig"
source "board/freescale/mx23evk/Kconfig"
source "board/freescale/mx25pdk/Kconfig"
source "board/freescale/mx28evk/Kconfig"
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile
index 2d55782..2311468 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -9,6 +9,7 @@ obj-y += clock.o
obj-y += timer.o
obj-y += fsl_epu.o
+obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index e2eb5f3..df2e1b7 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -301,6 +301,7 @@ int arch_cpu_init(void)
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *rcpm2_base =
(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+ struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
u32 state;
/*
@@ -328,6 +329,8 @@ int arch_cpu_init(void)
*/
fsl_epu_clean(epu_base);
+ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
+
return 0;
}
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index e01d911..856abed 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -171,7 +171,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
"clock-frequency", busclk / 2, 1);
-#ifdef CONFIG_QSPI_BOOT
+#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
CONFIG_SYS_IFC_ADDR);
fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
new file mode 100644
index 0000000..deeb674
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/immap_ls102xa.h>
+#include <ahci.h>
+#include <scsi.h>
+
+/* port register default value */
+#define AHCI_PORT_PHY_1_CFG 0xa003fffe
+#define AHCI_PORT_PHY_2_CFG 0x28183411
+#define AHCI_PORT_PHY_3_CFG 0x0e081004
+#define AHCI_PORT_PHY_4_CFG 0x00480811
+#define AHCI_PORT_PHY_5_CFG 0x192c96a4
+#define AHCI_PORT_TRANS_CFG 0x08000025
+
+#define SATA_ECC_REG_ADDR 0x20220520
+#define SATA_ECC_DISABLE 0x00020000
+
+int ls1021a_sata_init(void)
+{
+ struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
+ out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE);
+#endif
+
+ out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
+ out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG);
+ out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG);
+ out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG);
+ out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG);
+ out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
+
+ ahci_init((void __iomem *)AHCI_BASE_ADDR);
+ scsi_scan(0);
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index adb11b3..48c041b 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -15,6 +15,6 @@ obj-y += cache.o
obj-y += tlb.o
obj-y += transition.o
-obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
+obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
new file mode 100644
index 0000000..6fa08c8
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -0,0 +1,30 @@
+#
+# Copyright 2014-2015, Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += lowlevel.o
+obj-y += soc.o
+obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SPL) += spl.o
+
+ifneq ($(CONFIG_FSL_LSCH3),)
+obj-y += fsl_lsch3_speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o
+else
+ifneq ($(CONFIG_FSL_LSCH2),)
+obj-y += fsl_lsch2_speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
+endif
+endif
+
+ifneq ($(CONFIG_LS2085A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
+else
+ifneq ($(CONFIG_LS1043A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+endif
+endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2 b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
new file mode 100644
index 0000000..a6ef830
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch2
@@ -0,0 +1,10 @@
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+Freescale LayerScape with Chassis Generation 2
+
+This architecture supports Freescale ARMv8 SoCs with Chassis generation 2,
+for example LS1043A.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
index 08da7e4..03e18f6 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
@@ -1,5 +1,5 @@
#
-# Copyright 2014 Freescale Semiconductor
+# Copyright 2014-2015 Freescale Semiconductor
#
# SPDX-License-Identifier: GPL-2.0+
#
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index eb1213e..0cb0afa 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -10,34 +10,28 @@
#include <asm/system.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
-#include <asm/arch-fsl-lsch3/soc.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/speed.h>
+#ifdef CONFIG_MP
+#include <asm/arch/mp.h>
+#endif
+#include <fm_eth.h>
#include <fsl_debug_server.h>
#include <fsl-mc/fsl_mc.h>
-#include <asm/arch/fsl_serdes.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
-#include "cpu.h"
-#include "mp.h"
-#include "speed.h"
DECLARE_GLOBAL_DATA_PTR;
-static struct cpu_type cpu_type_list[] = {
-#ifdef CONFIG_LS2085A
- CPU_TYPE_ENTRY(LS2085, LS2085, 8),
- CPU_TYPE_ENTRY(LS2080, LS2080, 8),
- CPU_TYPE_ENTRY(LS2045, LS2045, 4),
-#endif
-};
-
void cpu_name(char *name)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
unsigned int i, svr, ver;
- svr = in_le32(&gur->svr);
+ svr = gur_in32(&gur->svr);
ver = SVR_SOC_VER(svr);
for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
@@ -54,146 +48,6 @@ void cpu_name(char *name)
}
#ifndef CONFIG_SYS_DCACHE_OFF
-
-#define SECTION_SHIFT_L0 39UL
-#define SECTION_SHIFT_L1 30UL
-#define SECTION_SHIFT_L2 21UL
-#define BLOCK_SIZE_L0 0x8000000000
-#define BLOCK_SIZE_L1 0x40000000
-#define BLOCK_SIZE_L2 0x200000
-
-#define NUM_OF_ENTRY 512
-
-#define TCR_EL2_PS_40BIT (2 << 16)
-#define LSCH3_VA_BITS (40)
-#define LSCH3_TCR (TCR_TG0_4K | \
- TCR_EL2_PS_40BIT | \
- TCR_SHARED_NON | \
- TCR_ORGN_NC | \
- TCR_IRGN_NC | \
- TCR_T0SZ(LSCH3_VA_BITS))
-#define LSCH3_TCR_FINAL (TCR_TG0_4K | \
- TCR_EL2_PS_40BIT | \
- TCR_SHARED_OUTER | \
- TCR_ORGN_WBWA | \
- TCR_IRGN_WBWA | \
- TCR_T0SZ(LSCH3_VA_BITS))
-
-#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
-#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
-#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
-#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
-#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
-#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
-#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
-#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
-#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
-#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
-#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
-#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
-#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
-#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
-#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
-#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
-#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
-#define CONFIG_SYS_FSL_NI_BASE 0x810000000
-#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
-#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
-#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
-#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
-#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
-#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
-#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
-#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
-#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
-#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
-#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
-#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
-#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
-#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
-#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
-
-struct sys_mmu_table {
- u64 virt_addr;
- u64 phys_addr;
- u64 size;
- u64 memory_type;
- u64 share;
-};
-
-static const struct sys_mmu_table lsch3_early_mmu_table[] = {
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
- CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
- /* For IFC Region #1, only the first 4MB is cache-enabled */
- { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
- CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
- CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
- CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
- MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
- CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
-};
-
-static const struct sys_mmu_table lsch3_final_mmu_table[] = {
- { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
- CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
- CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
- { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
- CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
- CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
- CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
- CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- /* For QBMAN portal, only the first 64MB is cache-enabled */
- { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
- CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
- CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
- CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
- MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
- CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
- CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
- CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-#ifdef CONFIG_LS2085A
- { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
- CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-#endif
- { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
- CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
- CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
- CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
- { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
-};
-
-struct table_info {
- u64 *ptr;
- u64 table_base;
- u64 entry_size;
-};
-
/*
* Set the block entries according to the information of the table.
*/
@@ -311,6 +165,7 @@ static inline void early_mmu_setup(void)
u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000);
+
struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
/* Invalidate all table entries */
@@ -320,19 +175,23 @@ static inline void early_mmu_setup(void)
set_pgtable_table(level0_table, 0, level1_table0);
set_pgtable_table(level0_table, 1, level1_table1);
set_pgtable_table(level1_table0, 0, level2_table0);
+
+#ifdef CONFIG_FSL_LSCH3
set_pgtable_table(level1_table0,
CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1,
level2_table1);
-
+#elif defined(CONFIG_FSL_LSCH2)
+ set_pgtable_table(level1_table0, 1, level2_table1);
+#endif
/* Find the table and fill in the block entries */
- for (i = 0; i < ARRAY_SIZE(lsch3_early_mmu_table); i++) {
- if (find_table(&lsch3_early_mmu_table[i],
+ for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) {
+ if (find_table(&early_mmu_table[i],
&table, level0_table) == 0) {
/*
* If find_table() returns error, it cannot be dealt
* with here. Breakpoint can be added for debugging.
*/
- set_block_entry(&lsch3_early_mmu_table[i], &table);
+ set_block_entry(&early_mmu_table[i], &table);
/*
* If set_block_entry() returns error, it cannot be
* dealt with here too.
@@ -341,7 +200,9 @@ static inline void early_mmu_setup(void)
}
el = current_el();
- set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR, MEMORY_ATTRIBUTES);
+
+ set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR,
+ MEMORY_ATTRIBUTES);
set_sctlr(get_sctlr() | CR_M);
}
@@ -353,7 +214,12 @@ static inline void early_mmu_setup(void)
* Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB.
* Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB.
* Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB.
+ *
+ * For LSCH3:
* Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB.
+ * For LSCH2:
+ * Level 2 table 1 contains 512 entries for each 2MB from 1GB to 2GB.
+ * Level 2 table 2 contains 512 entries for each 2MB from 20GB to 21GB.
*/
static inline void final_mmu_setup(void)
{
@@ -362,7 +228,12 @@ static inline void final_mmu_setup(void)
u64 *level1_table0 = (u64 *)(gd->arch.tlb_addr + 0x1000);
u64 *level1_table1 = (u64 *)(gd->arch.tlb_addr + 0x2000);
u64 *level2_table0 = (u64 *)(gd->arch.tlb_addr + 0x3000);
+#ifdef CONFIG_FSL_LSCH3
+ u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+#elif defined(CONFIG_FSL_LSCH2)
u64 *level2_table1 = (u64 *)(gd->arch.tlb_addr + 0x4000);
+ u64 *level2_table2 = (u64 *)(gd->arch.tlb_addr + 0x5000);
+#endif
struct table_info table = {level0_table, 0, BLOCK_SIZE_L0};
/* Invalidate all table entries */
@@ -372,23 +243,30 @@ static inline void final_mmu_setup(void)
set_pgtable_table(level0_table, 0, level1_table0);
set_pgtable_table(level0_table, 1, level1_table1);
set_pgtable_table(level1_table0, 0, level2_table0);
+#ifdef CONFIG_FSL_LSCH3
set_pgtable_table(level1_table0,
CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
level2_table1);
+#elif defined(CONFIG_FSL_LSCH2)
+ set_pgtable_table(level1_table0, 1, level2_table1);
+ set_pgtable_table(level1_table0,
+ CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1,
+ level2_table2);
+#endif
/* Find the table and fill in the block entries */
- for (i = 0; i < ARRAY_SIZE(lsch3_final_mmu_table); i++) {
- if (find_table(&lsch3_final_mmu_table[i],
+ for (i = 0; i < ARRAY_SIZE(final_mmu_table); i++) {
+ if (find_table(&final_mmu_table[i],
&table, level0_table) == 0) {
- if (set_block_entry(&lsch3_final_mmu_table[i],
+ if (set_block_entry(&final_mmu_table[i],
&table) != 0) {
printf("MMU error: could not set block entry for %p\n",
- &lsch3_final_mmu_table[i]);
+ &final_mmu_table[i]);
}
} else {
printf("MMU error: could not find the table for %p\n",
- &lsch3_final_mmu_table[i]);
+ &final_mmu_table[i]);
}
}
@@ -396,9 +274,13 @@ static inline void final_mmu_setup(void)
flush_dcache_range(gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
+#ifdef CONFIG_SYS_DPAA_FMAN
+ flush_dcache_all();
+#endif
/* point TTBR to the new table */
el = current_el();
- set_ttbr_tcr_mair(el, (u64)level0_table, LSCH3_TCR_FINAL,
+
+ set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL,
MEMORY_ATTRIBUTES);
/*
* MMU is already enabled, just need to invalidate TLB to load the
@@ -434,8 +316,9 @@ static inline u32 initiator_type(u32 cluster, int init_id)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
- u32 type = in_le32(&gur->tp_ityp[idx]);
+ u32 type = 0;
+ type = gur_in32(&gur->tp_ityp[idx]);
if (type & TP_ITYP_AV)
return type;
@@ -450,7 +333,8 @@ u32 cpu_mask(void)
do {
int j;
- cluster = in_le32(&gur->tp_cluster[i].lower);
+
+ cluster = gur_in32(&gur->tp_cluster[i].lower);
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
type = initiator_type(cluster, j);
if (type) {
@@ -460,7 +344,7 @@ u32 cpu_mask(void)
}
}
i++;
- } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+ } while ((cluster & TP_CLUSTER_EOC) == 0x0);
return mask;
}
@@ -482,7 +366,8 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
do {
int j;
- cluster = in_le32(&gur->tp_cluster[i].lower);
+
+ cluster = gur_in32(&gur->tp_cluster[i].lower);
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
if (initiator_type(cluster, j)) {
if (count == core)
@@ -491,7 +376,7 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
}
}
i++;
- } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+ } while ((cluster & TP_CLUSTER_EOC) == 0x0);
return -1; /* cannot identify the cluster */
}
@@ -505,7 +390,8 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
do {
int j;
- cluster = in_le32(&gur->tp_cluster[i].lower);
+
+ cluster = gur_in32(&gur->tp_cluster[i].lower);
for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
type = initiator_type(cluster, j);
if (type) {
@@ -515,7 +401,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
}
}
i++;
- } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
+ } while ((cluster & TP_CLUSTER_EOC) == 0x0);
return -1; /* cannot identify the cluster */
}
@@ -527,15 +413,13 @@ int print_cpuinfo(void)
struct sys_info sysinfo;
char buf[32];
unsigned int i, core;
- u32 type;
+ u32 type, rcw;
puts("SoC: ");
cpu_name(buf);
- printf(" %s (0x%x)\n", buf, in_le32(&gur->svr));
-
+ printf(" %s (0x%x)\n", buf, gur_in32(&gur->svr));
memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
-
get_sys_info(&sysinfo);
puts("Clock Configuration:");
for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
@@ -551,18 +435,23 @@ int print_cpuinfo(void)
printf("\n Bus: %-4s MHz ",
strmhz(buf, sysinfo.freq_systembus));
printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
+#ifdef CONFIG_SYS_DPAA_FMAN
+ printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
+#endif
+#ifdef CONFIG_FSL_LSCH3
printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
+#endif
puts("\n");
- /* Display the RCW, so that no one gets confused as to what RCW
+ /*
+ * Display the RCW, so that no one gets confused as to what RCW
* we're actually using for this boot.
*/
puts("Reset Configuration Word (RCW):");
for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
- u32 rcw = in_le32(&gur->rcwsr[i]);
-
+ rcw = gur_in32(&gur->rcwsr[i]);
if ((i % 4) == 0)
- printf("\n %02x:", i * 4);
+ printf("\n %08x:", i * 4);
printf(" %08x", rcw);
}
puts("\n");
@@ -585,27 +474,37 @@ int cpu_eth_init(bd_t *bis)
#ifdef CONFIG_FSL_MC_ENET
error = fsl_mc_ldpaa_init(bis);
#endif
+#ifdef CONFIG_FMAN_ENET
+ fm_standard_init(bis);
+#endif
return error;
}
int arch_early_init_r(void)
{
- int rv;
- rv = fsl_lsch3_wake_seconday_cores();
+#ifdef CONFIG_MP
+ int rv = 1;
+ rv = fsl_layerscape_wake_seconday_cores();
if (rv)
printf("Did not wake secondary cores\n");
+#endif
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#endif
+#ifdef CONFIG_FMAN_ENET
+ fman_enet_init();
+#endif
return 0;
}
int timer_init(void)
{
u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+#ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+#endif
#ifdef COUNTER_FREQUENCY_REAL
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
@@ -613,10 +512,12 @@ int timer_init(void)
asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
#endif
+#ifdef CONFIG_FSL_LSCH3
/* Enable timebase for all clusters.
* It is safe to do so even some clusters are not enabled.
*/
out_le32(cltbenr, 0xf);
+#endif
/* Enable clock for timer
* This is a global setting.
@@ -632,7 +533,7 @@ void reset_cpu(ulong addr)
u32 val;
/* Raise RESET_REQ_B */
- val = in_le32(rstcr);
+ val = scfg_in32(rstcr);
val |= 0x02;
- out_le32(rstcr, val);
+ scfg_out32(rstcr, val);
}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
index 2e3312b..8072f3c 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.h
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2014, Freescale Semiconductor
+ * Copyright 2014-2015, Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 567c419..47599c1 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -7,11 +7,22 @@
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
-#include <asm/arch-fsl-lsch3/fdt.h>
+#include <phy.h>
+#ifdef CONFIG_FSL_LSCH3
+#include <asm/arch/fdt.h>
+#endif
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
-#include "mp.h"
+#ifdef CONFIG_MP
+#include <asm/arch/mp.h>
+#endif
+
+int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
+{
+ return fdt_setprop_string(blob, offset, "phy-connection-type",
+ phy_string_for_interface(phyc));
+}
#ifdef CONFIG_MP
void ft_fixup_cpu(void *blob)
@@ -33,8 +44,8 @@ void ft_fixup_cpu(void *blob)
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
- core_id = of_read_number(reg, addr_cells);
if (reg) {
+ core_id = of_read_number(reg, addr_cells);
if (core_id == 0 || (is_core_online(core_id))) {
val = spin_tbl_addr;
val += id_to_core(core_id) *
@@ -150,6 +161,7 @@ void append_mmu_masters(void *blob, const char *smmu_path,
* for all DPAA2 devices.
*
*/
+#ifdef CONFIG_FSL_LSCH3
static void fdt_fixup_smmu(void *blob)
{
int nodeoffset;
@@ -165,6 +177,7 @@ static void fdt_fixup_smmu(void *blob)
fdt_fixup_smmu_pcie(blob);
#endif
}
+#endif
void ft_cpu_setup(void *blob, bd_t *bd)
{
@@ -181,9 +194,11 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ft_pci_setup(blob, bd);
#endif
-#if defined(CONFIG_FSL_ESDHC)
+#ifdef CONFIG_FSL_ESDHC
fdt_fixup_esdhc(blob, bd);
#endif
+#ifdef CONFIG_FSL_LSCH3
fdt_fixup_smmu(blob);
+#endif
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
new file mode 100644
index 0000000..f7178d1
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+ int ret = 0;
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ ret |= serdes1_prtcl_map[device];
+#endif
+
+ return !!ret;
+}
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 cfg = gur_in32(&gur->rcwsr[4]);
+ int i;
+
+ switch (sd) {
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ case FSL_SRDS_1:
+ cfg &= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ break;
+#endif
+ default:
+ printf("invalid SerDes%d\n", sd);
+ break;
+ }
+
+ /* Is serdes enabled at all? */
+ if (unlikely(cfg == 0))
+ return -ENODEV;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (serdes_get_prtcl(sd, cfg, i) == device)
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+int get_serdes_protocol(void)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 cfg = gur_in32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ return cfg;
+}
+
+const char *serdes_clock_to_string(u32 clock)
+{
+ switch (clock) {
+ case SRDS_PLLCR0_RFCK_SEL_100:
+ return "100";
+ case SRDS_PLLCR0_RFCK_SEL_125:
+ return "125";
+ case SRDS_PLLCR0_RFCK_SEL_156_25:
+ return "156.25";
+ default:
+ return "100";
+ }
+}
+
+void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
+ u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 cfg;
+ int lane;
+
+ memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
+
+ cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask;
+ cfg >>= sd_prctl_shift;
+ printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
+
+ if (!is_serdes_prtcl_valid(sd, cfg))
+ printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
+
+ for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
+
+ if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
+ debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
+ else
+ serdes_prtcl_map[lane_prtcl] = 1;
+ }
+}
+
+void fsl_serdes_init(void)
+{
+#ifdef CONFIG_SYS_FSL_SRDS_1
+ serdes_init(FSL_SRDS_1,
+ CONFIG_SYS_FSL_SERDES_ADDR,
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
+ serdes1_prtcl_map);
+#endif
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
new file mode 100644
index 0000000..6f6a588
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/soc.h>
+#include <fsl_ifc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
+#endif
+
+void get_sys_info(struct sys_info *sys_info)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+ struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
+ u32 ccr;
+#endif
+#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
+ u32 rcw_tmp;
+#endif
+ struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
+ unsigned int cpu;
+ const u8 core_cplx_pll[8] = {
+ [0] = 0, /* CC1 PPL / 1 */
+ [1] = 0, /* CC1 PPL / 2 */
+ [4] = 1, /* CC2 PPL / 1 */
+ [5] = 1, /* CC2 PPL / 2 */
+ };
+
+ const u8 core_cplx_pll_div[8] = {
+ [0] = 1, /* CC1 PPL / 1 */
+ [1] = 2, /* CC1 PPL / 2 */
+ [4] = 1, /* CC2 PPL / 1 */
+ [5] = 2, /* CC2 PPL / 2 */
+ };
+
+ uint i;
+ uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+
+ sys_info->freq_systembus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+ sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#else
+ sys_info->freq_ddrbus = sysclk;
+#endif
+
+ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+ FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+ sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
+ FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
+ FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+
+ for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
+ ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
+ if (ratio[i] > 4)
+ freq_c_pll[i] = sysclk * ratio[i];
+ else
+ freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
+ }
+
+ for (cpu = 0; cpu < CONFIG_MAX_CPUS; cpu++) {
+ u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
+ & 0xf;
+ u32 cplx_pll = core_cplx_pll[c_pll_sel];
+
+ sys_info->freq_processor[cpu] =
+ freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
+ }
+
+#define HWA_CGA_M1_CLK_SEL 0xe0000000
+#define HWA_CGA_M1_CLK_SHIFT 29
+#ifdef CONFIG_SYS_DPAA_FMAN
+ rcw_tmp = in_be32(&gur->rcwsr[7]);
+ switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
+ case 2:
+ sys_info->freq_fman[0] = freq_c_pll[0] / 2;
+ break;
+ case 3:
+ sys_info->freq_fman[0] = freq_c_pll[0] / 3;
+ break;
+ case 6:
+ sys_info->freq_fman[0] = freq_c_pll[1] / 2;
+ break;
+ case 7:
+ sys_info->freq_fman[0] = freq_c_pll[1] / 3;
+ break;
+ default:
+ printf("Error: Unknown FMan1 clock select!\n");
+ break;
+ }
+#endif
+
+#define HWA_CGA_M2_CLK_SEL 0x00000007
+#define HWA_CGA_M2_CLK_SHIFT 0
+#ifdef CONFIG_FSL_ESDHC
+ rcw_tmp = in_be32(&gur->rcwsr[15]);
+ rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT;
+ sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp;
+#endif
+
+#if defined(CONFIG_FSL_IFC)
+ ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
+ ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
+
+ sys_info->freq_localbus = sys_info->freq_systembus / ccr;
+#endif
+}
+
+int get_clocks(void)
+{
+ struct sys_info sys_info;
+
+ get_sys_info(&sys_info);
+ gd->cpu_clk = sys_info.freq_processor[0];
+ gd->bus_clk = sys_info.freq_systembus;
+ gd->mem_clk = sys_info.freq_ddrbus;
+
+#ifdef CONFIG_FSL_ESDHC
+ gd->arch.sdhc_clk = sys_info.freq_sdhc;
+#endif
+
+ if (gd->cpu_clk != 0)
+ return 0;
+ else
+ return 1;
+}
+
+ulong get_bus_freq(ulong dummy)
+{
+ return gd->bus_clk;
+}
+
+ulong get_ddr_freq(ulong dummy)
+{
+ return gd->mem_clk;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+int get_sdhc_freq(ulong dummy)
+{
+ return gd->arch.sdhc_clk;
+}
+#endif
+
+int get_serial_clock(void)
+{
+ return gd->bus_clk;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_I2C_CLK:
+ return get_bus_freq(0);
+#if defined(CONFIG_FSL_ESDHC)
+ case MXC_ESDHC_CLK:
+ return get_sdhc_freq(0);
+#endif
+ case MXC_DSPI_CLK:
+ return get_bus_freq(0);
+ case MXC_UART_CLK:
+ return get_bus_freq(0);
+ default:
+ printf("Unsupported clock\n");
+ }
+ return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index ae08343..2ab8da6 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -8,7 +8,7 @@
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/fsl_serdes.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <asm/arch/soc.h>
#include <fsl-mc/ldpaa_wriop.h>
#ifdef CONFIG_SYS_FSL_SRDS_1
@@ -35,7 +35,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- u32 cfg = in_le32(&gur->rcwsr[28]);
+ u32 cfg = gur_in32(&gur->rcwsr[28]);
int i;
switch (sd) {
@@ -76,7 +76,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
- cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask;
+ cfg = gur_in32(&gur->rcwsr[28]) & sd_prctl_mask;
cfg >>= sd_prctl_shift;
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index d9f137c..4054c3c 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2014, Freescale Semiconductor, Inc.
+ * Copyright 2014-2015, Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
@@ -11,8 +11,8 @@
#include <fsl_ifc.h>
#include <asm/processor.h>
#include <asm/io.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
#include <asm/arch/clock.h>
+#include <asm/arch/soc.h>
#include "cpu.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -83,15 +83,15 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_ddrbus2 = sysclk;
#endif
- sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
+ sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
/* Platform clock is half of platform PLL */
sys_info->freq_systembus /= 2;
- sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
+ sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
- sys_info->freq_ddrbus2 *= (in_le32(&gur->rcwsr[0]) >>
+ sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
@@ -118,7 +118,7 @@ void get_sys_info(struct sys_info *sys_info)
}
#if defined(CONFIG_FSL_IFC)
- ccr = in_le32(&ifc_regs.gregs->ifc_ccr);
+ ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
sys_info->freq_localbus = sys_info->freq_systembus / ccr;
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 6b19d36..41e1704 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2014 Freescale Semiconductor
+ * (C) Copyright 2014-2015 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*
@@ -10,11 +10,14 @@
#include <linux/linkage.h>
#include <asm/gic.h>
#include <asm/macro.h>
-#include "mp.h"
+#ifdef CONFIG_MP
+#include <asm/arch/mp.h>
+#endif
ENTRY(lowlevel_init)
mov x29, lr /* Save LR */
+#ifdef CONFIG_FSL_LSCH3
/* Add fully-coherent masters to DVM domain */
ldr x0, =CCI_MN_BASE
ldr x1, =CCI_MN_RNF_NODEID_LIST
@@ -81,6 +84,7 @@ ENTRY(lowlevel_init)
ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
ldr x1, =0x00FF000C
bl ccn504_set_qos
+#endif
/* Set the SMMU page size in the sACR register */
ldr x1, =SMMU_BASE
@@ -106,10 +110,12 @@ ENTRY(lowlevel_init)
branch_if_master x0, x1, 2f
+#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
ldr x0, =secondary_boot_func
blr x0
-2:
+#endif
+2:
#ifdef CONFIG_FSL_TZPC_BP147
/* Set Non Secure access for all devices protected via TZPC */
ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
@@ -245,6 +251,7 @@ ENTRY(__asm_flush_l3_cache)
ret
ENDPROC(__asm_flush_l3_cache)
+#ifdef CONFIG_MP
/* Keep literals not used by the secondary boot code outside it */
.ltorg
@@ -353,3 +360,4 @@ __real_cntfrq:
/* Secondary Boot Code ends here */
__secondary_boot_code_size:
.quad .-secondary_boot_code
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c
new file mode 100644
index 0000000..e54d389
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/immap_lsch2.h>
+
+struct serdes_config {
+ u32 protocol;
+ u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {0x1555, {XFI_FM1_MAC9, PCIE1, PCIE2, PCIE3} },
+ {0x2555, {SGMII_2500_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
+ {0x4555, {QSGMII_FM1_A, PCIE1, PCIE2, PCIE3} },
+ {0x4558, {QSGMII_FM1_A, PCIE1, PCIE2, SATA1} },
+ {0x1355, {XFI_FM1_MAC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+ {0x2355, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+ {0x3335, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
+ PCIE3} },
+ {0x3355, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, PCIE3} },
+ {0x3358, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, PCIE2, SATA1} },
+ {0x3555, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, PCIE3} },
+ {0x3558, {SGMII_FM1_DTSEC9, PCIE1, PCIE2, SATA1} },
+ {0x7000, {PCIE1, PCIE1, PCIE1, PCIE1} },
+ {0x9998, {PCIE1, PCIE2, PCIE3, SATA1} },
+ {0x6058, {PCIE1, PCIE1, PCIE2, SATA1} },
+ {0x1455, {XFI_FM1_MAC9, QSGMII_FM1_A, PCIE2, PCIE3} },
+ {0x2455, {SGMII_2500_FM1_DTSEC9, QSGMII_FM1_A, PCIE2, PCIE3} },
+ {0x2255, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC2, PCIE2, PCIE3} },
+ {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6} },
+ {}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+ serdes1_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == cfg)
+ return ptr->lanes[lane];
+ ptr++;
+ }
+
+ return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+ int i;
+ struct serdes_config *ptr;
+
+ if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+ return 0;
+
+ ptr = serdes_cfg_tbl[serdes];
+ while (ptr->protocol) {
+ if (ptr->protocol == prtcl)
+ break;
+ ptr++;
+ }
+
+ if (!ptr->protocol)
+ return 0;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (ptr->lanes[i] != NONE)
+ return 1;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c
index 0b79a50..ea3114c 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls2085a_serdes.c
@@ -1,12 +1,11 @@
/*
- * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/fsl_serdes.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
struct serdes_config {
u8 protocol;
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index da7853a..0d600db 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -7,9 +7,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/arch-fsl-lsch3/immap_lsch3.h>
-#include "mp.h"
+#include <asm/arch/mp.h>
+#include <asm/arch/soc.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -23,10 +22,14 @@ phys_addr_t determine_mp_bootpg(void)
return (phys_addr_t)&secondary_boot_code;
}
-int fsl_lsch3_wake_seconday_cores(void)
+int fsl_layerscape_wake_seconday_cores(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_LSCH3
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+#elif defined(CONFIG_FSL_LSCH2)
+ struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
+#endif
u32 cores, cpu_up_mask = 1;
int i, timeout = 10;
u64 *table = get_spin_tbl_addr();
@@ -48,13 +51,24 @@ int fsl_lsch3_wake_seconday_cores(void)
(CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
printf("Waking secondary cores to start from %lx\n", gd->relocaddr);
- out_le32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
- out_le32(&gur->bootlocptrl, (u32)gd->relocaddr);
- out_le32(&gur->scratchrw[6], 1);
+
+#ifdef CONFIG_FSL_LSCH3
+ gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
+ gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
+ gur_out32(&gur->scratchrw[6], 1);
asm volatile("dsb st" : : : "memory");
rst->brrl = cores;
asm volatile("dsb st" : : : "memory");
+#elif defined(CONFIG_FSL_LSCH2)
+ scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
+ scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
+ asm volatile("dsb st" : : : "memory");
+ gur_out32(&gur->brrl, cores);
+ asm volatile("dsb st" : : : "memory");
+ /* Bootup online cores */
+ scfg_out32(&scfg->corebcr, cores);
+#endif
/* This is needed as a precautionary measure.
* If some code before this has accidentally released the secondary
* cores then the pre-bootloader code will trap them in a "wfe" unless
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 2538001..637853d 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -1,19 +1,18 @@
/*
- * Copyright 2015 Freescale Semiconductor
+ * Copyright 2014-2015 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <fsl_ifc.h>
-#include <nand.h>
-#include <spl.h>
-#include <asm/arch-fsl-lsch3/soc.h>
+#include <asm/arch/soc.h>
#include <asm/io.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_LS2085A
static void erratum_a008751(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
@@ -78,30 +77,27 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
}
-#ifdef CONFIG_SPL_BUILD
-void board_init_f(ulong dummy)
+#elif defined(CONFIG_LS1043A)
+void fsl_lsch2_early_init_f(void)
{
- /* Clear global data */
- memset((void *)gd, 0, sizeof(gd_t));
+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
- arch_cpu_init();
- board_early_init_f();
- timer_init();
- env_init();
- gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
-
- serial_init();
- console_init_f();
- dram_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
+#ifdef CONFIG_FSL_IFC
+ init_early_memctl_regs(); /* tighten IFC timing */
+#endif
- board_init_r(NULL, 0);
+ /*
+ * Enable snoop requests and DVM message requests for
+ * Slave insterface S4 (A53 core cluster)
+ */
+ out_le32(&cci->slave[4].snoop_ctrl,
+ CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
}
+#endif
-u32 spl_boot_device(void)
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
{
- return BOOT_DEVICE_NAND;
+ return 0;
}
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
new file mode 100644
index 0000000..ba551aa
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <fsl_ifc.h>
+#include <fsl_csu.h>
+#include <i2c.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ return BOOT_DEVICE_MMC1;
+#endif
+#ifdef CONFIG_SPL_NAND_SUPPORT
+ return BOOT_DEVICE_NAND;
+#endif
+ return 0;
+}
+
+u32 spl_boot_mode(void)
+{
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_MMC1:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+ return MMCSD_MODE_FAT;
+#else
+ return MMCSD_MODE_RAW;
+#endif
+ case BOOT_DEVICE_NAND:
+ return 0;
+ default:
+ puts("spl: error: unsupported device\n");
+ hang();
+ }
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ /* Set global data pointer */
+ gd = &gdata;
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+#ifdef CONFIG_LS2085A
+ arch_cpu_init();
+#endif
+#ifdef CONFIG_FSL_IFC
+ init_early_memctl_regs();
+#endif
+ board_early_init_f();
+ timer_init();
+#ifdef CONFIG_LS2085A
+ env_init();
+#endif
+ get_clocks();
+
+ preloader_console_init();
+
+#ifdef CONFIG_SPL_I2C_SUPPORT
+ i2c_init_all();
+#endif
+ dram_init();
+
+ /* Clear the BSS */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+ enable_layerscape_ns_access();
+#endif
+ board_init_r(NULL, 0);
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
deleted file mode 100644
index 9f7815b..0000000
--- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright 2014, Freescale Semiconductor
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += cpu.o
-obj-y += lowlevel.o
-obj-y += soc.o
-obj-y += speed.o
-obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o
-obj-$(CONFIG_MP) += mp.o
-obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.h b/arch/arm/cpu/armv8/fsl-lsch3/speed.h
deleted file mode 100644
index 15af5b9..0000000
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Copyright 2014, Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-void get_sys_info(struct sys_info *sys_info);
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/clock.h b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
index 62bc53c..6935913 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/clock.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/clock.h
@@ -1,12 +1,12 @@
/*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
*/
-#ifndef __ASM_ARCH_FSL_LSCH3_CLOCK_H_
-#define __ASM_ARCH_FSL_LSCH3_CLOCK_H_
+#ifndef __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
+#define __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_
#include <common.h>
@@ -21,4 +21,4 @@ enum mxc_clock {
unsigned int mxc_get_clock(enum mxc_clock clk);
-#endif /* __ASM_ARCH_FSL_LSCH3_CLOCK_H_ */
+#endif /* __ASM_ARCH_FSL_LAYERSCAPE_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
new file mode 100644
index 0000000..87bb937
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
+
+#include <fsl_ddrc_version.h>
+
+#ifdef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDRC_GEN4
+#else
+#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
+#endif
+#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
+
+#if defined(CONFIG_LS2085A)
+#define CONFIG_MAX_CPUS 16
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
+#define CONFIG_NUM_DDR_CONTROLLERS 3
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
+#define SRDS_MAX_LANES 8
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
+#define CONFIG_SYS_PAGE_SIZE 0x10000
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#ifndef L1_CACHE_BYTES
+#define L1_CACHE_SHIFT 6
+#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
+#endif
+
+#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
+
+/* DDR */
+#define CONFIG_SYS_FSL_DDR_LE
+#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_IFC_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0x06000000
+#define GICR_BASE 0x06100000
+
+/* SMMU Defintions */
+#define SMMU_BASE 0x05000000 /* GR0 Base */
+
+/* Cache Coherent Interconnect */
+#define CCI_MN_BASE 0x04000000
+#define CCI_MN_RNF_NODEID_LIST 0x180
+#define CCI_MN_DVM_DOMAIN_CTL 0x200
+#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
+
+#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
+#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
+#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
+#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
+#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
+#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
+
+#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
+#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
+#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
+
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE 0x02200000
+#define TZPCR0SIZE_BASE (TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
+
+#define CONFIG_SYS_FSL_ERRATUM_A008336
+#define CONFIG_SYS_FSL_ERRATUM_A008511
+#define CONFIG_SYS_FSL_ERRATUM_A008514
+#define CONFIG_SYS_FSL_ERRATUM_A008585
+#define CONFIG_SYS_FSL_ERRATUM_A008751
+#elif defined(CONFIG_LS1043A)
+#define CONFIG_MAX_CPUS 4
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 7
+#define CONFIG_SYS_NUM_FM1_10GEC 1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000
+#define CONFIG_SYS_FSL_SEC_COMPAT 5
+#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */
+#define CONFIG_SYS_FSL_DDR_BE
+#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
+#define CONFIG_SYS_FSL_CCSR_SCFG_BE
+#define CONFIG_SYS_FSL_IFC_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+
+#define QE_MURAM_SIZE 0x6000UL
+#define MAX_QE_RISC 1
+#define QE_NUM_OF_SNUM 28
+
+#define SRDS_MAX_LANES 4
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
+
+#define CONFIG_SYS_FSL_SFP_VER_3_2
+#define CONFIG_SYS_FSL_SNVS_LE
+#define CONFIG_SYS_FSL_SEC_LE
+#define CONFIG_SYS_FSL_SFP_BE
+#define CONFIG_SYS_FSL_SRK_LE
+#define CONFIG_KEY_REVOCATION
+
+/* SMMU Defintions */
+#define SMMU_BASE 0x09000000
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE 0x01401000
+#define GICC_BASE 0x01402000
+
+#else
+#error SoC not defined
+#endif
+
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
new file mode 100644
index 0000000..2903996
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -0,0 +1,229 @@
+/*
+ * Copyright 2014-2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_LAYERSCAPE_CPU_H
+#define _FSL_LAYERSCAPE_CPU_H
+
+static struct cpu_type cpu_type_list[] = {
+ CPU_TYPE_ENTRY(LS2085, LS2085, 8),
+ CPU_TYPE_ENTRY(LS2080, LS2080, 8),
+ CPU_TYPE_ENTRY(LS2045, LS2045, 4),
+ CPU_TYPE_ENTRY(LS1043, LS1043, 4),
+};
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+
+#define SECTION_SHIFT_L0 39UL
+#define SECTION_SHIFT_L1 30UL
+#define SECTION_SHIFT_L2 21UL
+#define BLOCK_SIZE_L0 0x8000000000
+#define BLOCK_SIZE_L1 0x40000000
+#define BLOCK_SIZE_L2 0x200000
+#define NUM_OF_ENTRY 512
+#define TCR_EL2_PS_40BIT (2 << 16)
+
+#define LAYERSCAPE_VA_BITS (40)
+#define LAYERSCAPE_TCR (TCR_TG0_4K | \
+ TCR_EL2_PS_40BIT | \
+ TCR_SHARED_NON | \
+ TCR_ORGN_NC | \
+ TCR_IRGN_NC | \
+ TCR_T0SZ(LAYERSCAPE_VA_BITS))
+#define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \
+ TCR_EL2_PS_40BIT | \
+ TCR_SHARED_OUTER | \
+ TCR_ORGN_WBWA | \
+ TCR_IRGN_WBWA | \
+ TCR_T0SZ(LAYERSCAPE_VA_BITS))
+
+#ifdef CONFIG_FSL_LSCH3
+#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
+#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
+#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
+#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
+#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
+#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
+#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
+#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
+#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
+#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
+#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
+#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
+#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
+#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
+#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
+#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
+#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
+#define CONFIG_SYS_FSL_NI_BASE 0x810000000
+#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
+#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
+#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
+#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
+#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
+#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
+#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
+#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
+#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
+#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
+#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
+#elif defined(CONFIG_FSL_LSCH2)
+#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
+#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
+#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
+#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
+#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
+#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
+#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
+#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
+#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
+#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
+#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
+#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
+#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
+#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
+#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
+#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
+#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
+#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
+#endif
+
+struct sys_mmu_table {
+ u64 virt_addr;
+ u64 phys_addr;
+ u64 size;
+ u64 memory_type;
+ u64 share;
+};
+
+struct table_info {
+ u64 *ptr;
+ u64 table_base;
+ u64 entry_size;
+};
+
+static const struct sys_mmu_table early_mmu_table[] = {
+#ifdef CONFIG_FSL_LSCH3
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+ /* For IFC Region #1, only the first 4MB is cache-enabled */
+ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
+ CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+ CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
+ CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
+ MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
+ CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+#elif defined(CONFIG_FSL_LSCH2)
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+ CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+#endif
+};
+
+static const struct sys_mmu_table final_mmu_table[] = {
+#ifdef CONFIG_FSL_LSCH3
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+ { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
+ CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+ CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
+ CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
+ CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ /* For QBMAN portal, only the first 64MB is cache-enabled */
+ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+ CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
+ MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+ CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
+ CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
+ CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+#ifdef CONFIG_LS2085A
+ { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
+ CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+#endif
+ { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
+ CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
+ CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
+ CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+#elif defined(CONFIG_FSL_LSCH2)
+ { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
+ CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+ CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+ CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
+ PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
+ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+ CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+ { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+ CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
+ CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
+ CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
+ CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+#endif
+};
+#endif
+
+int fsl_qoriq_core_to_cluster(unsigned int core);
+u32 cpu_mask(void);
+#endif /* _FSL_LAYERSCAPE_CPU_H */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fdt.h b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
index 21d20fb..4da73ab 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/fdt.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
@@ -4,7 +4,11 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_
+
void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt);
void append_mmu_masters(void *blob, const char *smmu_path,
const char *master_name, u32 *stream_ids, int count);
void fdt_fixup_smmu_pcie(void *blob);
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
new file mode 100644
index 0000000..e1043b5
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_SERDES_H__
+#define __FSL_SERDES_H__
+
+#include <config.h>
+
+#if defined(CONFIG_LS2085A)
+enum srds_prtcl {
+ NONE = 0,
+ PCIE1,
+ PCIE2,
+ PCIE3,
+ PCIE4,
+ SATA1,
+ SATA2,
+ XAUI1,
+ XAUI2,
+ XFI1,
+ XFI2,
+ XFI3,
+ XFI4,
+ XFI5,
+ XFI6,
+ XFI7,
+ XFI8,
+ SGMII1,
+ SGMII2,
+ SGMII3,
+ SGMII4,
+ SGMII5,
+ SGMII6,
+ SGMII7,
+ SGMII8,
+ SGMII9,
+ SGMII10,
+ SGMII11,
+ SGMII12,
+ SGMII13,
+ SGMII14,
+ SGMII15,
+ SGMII16,
+ QSGMII_A, /* A indicates MACs 1-4 */
+ QSGMII_B, /* B indicates MACs 5-8 */
+ QSGMII_C, /* C indicates MACs 9-12 */
+ QSGMII_D, /* D indicates MACs 12-16 */
+ SERDES_PRCTL_COUNT
+};
+
+enum srds {
+ FSL_SRDS_1 = 0,
+ FSL_SRDS_2 = 1,
+};
+#elif defined(CONFIG_LS1043A)
+enum srds_prtcl {
+ NONE = 0,
+ PCIE1,
+ PCIE2,
+ PCIE3,
+ PCIE4,
+ SATA1,
+ SATA2,
+ SRIO1,
+ SRIO2,
+ SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3,
+ SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5,
+ SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC10,
+ SGMII_FM2_DTSEC1,
+ SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3,
+ SGMII_FM2_DTSEC4,
+ SGMII_FM2_DTSEC5,
+ SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC10,
+ SGMII_TSEC1,
+ SGMII_TSEC2,
+ SGMII_TSEC3,
+ SGMII_TSEC4,
+ XAUI_FM1,
+ XAUI_FM2,
+ AURORA,
+ CPRI1,
+ CPRI2,
+ CPRI3,
+ CPRI4,
+ CPRI5,
+ CPRI6,
+ CPRI7,
+ CPRI8,
+ XAUI_FM1_MAC9,
+ XAUI_FM1_MAC10,
+ XAUI_FM2_MAC9,
+ XAUI_FM2_MAC10,
+ HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC10,
+ HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC10,
+ QSGMII_FM1_A, /* A indicates MACs 1,2,5,6 */
+ QSGMII_FM1_B, /* B indicates MACs 5,6,9,10 */
+ QSGMII_FM2_A,
+ QSGMII_FM2_B,
+ XFI_FM1_MAC1,
+ XFI_FM1_MAC2,
+ XFI_FM1_MAC9,
+ XFI_FM1_MAC10,
+ XFI_FM2_MAC9,
+ XFI_FM2_MAC10,
+ INTERLAKEN,
+ QSGMII_SW1_A, /* Indicates ports on L2 Switch */
+ QSGMII_SW1_B,
+ SGMII_2500_FM1_DTSEC1,
+ SGMII_2500_FM1_DTSEC2,
+ SGMII_2500_FM1_DTSEC3,
+ SGMII_2500_FM1_DTSEC4,
+ SGMII_2500_FM1_DTSEC5,
+ SGMII_2500_FM1_DTSEC6,
+ SGMII_2500_FM1_DTSEC9,
+ SGMII_2500_FM1_DTSEC10,
+ SGMII_2500_FM2_DTSEC1,
+ SGMII_2500_FM2_DTSEC2,
+ SGMII_2500_FM2_DTSEC3,
+ SGMII_2500_FM2_DTSEC4,
+ SGMII_2500_FM2_DTSEC5,
+ SGMII_2500_FM2_DTSEC6,
+ SGMII_2500_FM2_DTSEC9,
+ SGMII_2500_FM2_DTSEC10,
+ SERDES_PRCTL_COUNT
+};
+
+enum srds {
+ FSL_SRDS_1 = 0,
+};
+
+#endif
+
+int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+
+#ifdef CONFIG_LS1043A
+const char *serdes_clock_to_string(u32 clock);
+int get_serdes_protocol(void);
+#endif
+
+#endif /* __FSL_SERDES_H__ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
new file mode 100644
index 0000000..d941437
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -0,0 +1,555 @@
+/*
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_FSL_LSCH2_IMMAP_H__
+#define __ARCH_FSL_LSCH2_IMMAP_H__
+
+#include <fsl_immap.h>
+
+#define CONFIG_SYS_IMMR 0x01000000
+#define CONFIG_SYS_DCSRBAR 0x20000000
+#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
+
+#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000)
+#define CONFIG_SYS_GIC400_ADDR (CONFIG_SYS_IMMR + 0x00400000)
+#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
+#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
+#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
+#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
+#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
+#define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000)
+#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
+#define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
+#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
+#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
+#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
+#define CONFIG_SYS_SNVS_ADDR (CONFIG_SYS_IMMR + 0xe90000)
+#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
+
+#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
+
+#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
+#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
+#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x011a0000)
+#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x011b0000)
+
+#define WDOG1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01ad0000)
+
+#define QSPI0_BASE_ADDR (CONFIG_SYS_IMMR + 0x00550000)
+#define DSPI1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01100000)
+
+#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
+
+#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
+
+#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
+
+/* TZ Address Space Controller Definitions */
+#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
+#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
+#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
+#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
+#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
+#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
+#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
+#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
+#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
+#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
+#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
+#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
+#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
+
+#define TP_ITYP_AV 0x00000001 /* Initiator available */
+#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
+#define TP_ITYP_TYPE_ARM 0x0
+#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
+#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
+#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
+#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
+#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
+#define TY_ITYP_VER_A7 0x1
+#define TY_ITYP_VER_A53 0x2
+#define TY_ITYP_VER_A57 0x3
+
+#define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */
+#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
+#define TP_INIT_PER_CLUSTER 4
+
+/*
+ * Define default values for some CCSR macros to make header files cleaner*
+ *
+ * To completely disable CCSR relocation in a board header file, define
+ * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
+ * to a value that is the same as CONFIG_SYS_CCSRBAR.
+ */
+
+#ifdef CONFIG_SYS_CCSRBAR_PHYS
+#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
+CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
+#endif
+
+#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR
+#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
+#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
+#endif
+
+#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
+#endif
+
+#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
+ CONFIG_SYS_CCSRBAR_PHYS_LOW)
+
+struct sys_info {
+ unsigned long freq_processor[CONFIG_MAX_CPUS];
+ unsigned long freq_systembus;
+ unsigned long freq_ddrbus;
+ unsigned long freq_localbus;
+ unsigned long freq_sdhc;
+#ifdef CONFIG_SYS_DPAA_FMAN
+ unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
+#endif
+ unsigned long freq_qman;
+};
+
+#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0xa88000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0xa89000
+#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0xa8a000
+#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0xa8b000
+#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0xa8c000
+#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0xa8d000
+
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
+#define CONFIG_SYS_FSL_FM1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
+#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+
+/* Device Configuration and Pin Control */
+struct ccsr_gur {
+ u32 porsr1; /* POR status 1 */
+#define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000
+ u32 porsr2; /* POR status 2 */
+ u8 res_008[0x20-0x8];
+ u32 gpporcr1; /* General-purpose POR configuration */
+ u32 gpporcr2;
+#define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT 25
+#define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK 0x1F
+#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT 20
+#define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK 0x1F
+ u32 dcfg_fusesr; /* Fuse status register */
+ u8 res_02c[0x70-0x2c];
+ u32 devdisr; /* Device disable control */
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_1 0x80000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_2 0x40000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_3 0x20000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_4 0x10000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_5 0x08000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_6 0x04000000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_9 0x00800000
+#define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_1 0x00800000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_2 0x00400000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_3 0x80000000
+#define FSL_CHASSIS2_DEVDISR2_10GEC1_4 0x40000000
+ u32 devdisr2; /* Device disable control 2 */
+ u32 devdisr3; /* Device disable control 3 */
+ u32 devdisr4; /* Device disable control 4 */
+ u32 devdisr5; /* Device disable control 5 */
+ u32 devdisr6; /* Device disable control 6 */
+ u32 devdisr7; /* Device disable control 7 */
+ u8 res_08c[0x94-0x8c];
+ u32 coredisru; /* uppper portion for support of 64 cores */
+ u32 coredisrl; /* lower portion for support of 64 cores */
+ u8 res_09c[0xa0-0x9c];
+ u32 pvr; /* Processor version */
+ u32 svr; /* System version */
+ u32 mvr; /* Manufacturing version */
+ u8 res_0ac[0xb0-0xac];
+ u32 rstcr; /* Reset control */
+ u32 rstrqpblsr; /* Reset request preboot loader status */
+ u8 res_0b8[0xc0-0xb8];
+ u32 rstrqmr1; /* Reset request mask */
+ u8 res_0c4[0xc8-0xc4];
+ u32 rstrqsr1; /* Reset request status */
+ u8 res_0cc[0xd4-0xcc];
+ u32 rstrqwdtmrl; /* Reset request WDT mask */
+ u8 res_0d8[0xdc-0xd8];
+ u32 rstrqwdtsrl; /* Reset request WDT status */
+ u8 res_0e0[0xe4-0xe0];
+ u32 brrl; /* Boot release */
+ u8 res_0e8[0x100-0xe8];
+ u32 rcwsr[16]; /* Reset control word status */
+#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT 25
+#define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK 0x1f
+#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT 16
+#define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f
+#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000
+#define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16
+ u8 res_140[0x200-0x140];
+ u32 scratchrw[4]; /* Scratch Read/Write */
+ u8 res_210[0x300-0x210];
+ u32 scratchw1r[4]; /* Scratch Read (Write once) */
+ u8 res_310[0x400-0x310];
+ u32 crstsr[12];
+ u8 res_430[0x500-0x430];
+
+ /* PCI Express n Logical I/O Device Number register */
+ u32 dcfg_ccsr_pex1liodnr;
+ u32 dcfg_ccsr_pex2liodnr;
+ u32 dcfg_ccsr_pex3liodnr;
+ u32 dcfg_ccsr_pex4liodnr;
+ /* RIO n Logical I/O Device Number register */
+ u32 dcfg_ccsr_rio1liodnr;
+ u32 dcfg_ccsr_rio2liodnr;
+ u32 dcfg_ccsr_rio3liodnr;
+ u32 dcfg_ccsr_rio4liodnr;
+ /* USB Logical I/O Device Number register */
+ u32 dcfg_ccsr_usb1liodnr;
+ u32 dcfg_ccsr_usb2liodnr;
+ u32 dcfg_ccsr_usb3liodnr;
+ u32 dcfg_ccsr_usb4liodnr;
+ /* SD/MMC Logical I/O Device Number register */
+ u32 dcfg_ccsr_sdmmc1liodnr;
+ u32 dcfg_ccsr_sdmmc2liodnr;
+ u32 dcfg_ccsr_sdmmc3liodnr;
+ u32 dcfg_ccsr_sdmmc4liodnr;
+ /* RIO Message Unit Logical I/O Device Number register */
+ u32 dcfg_ccsr_riomaintliodnr;
+
+ u8 res_544[0x550-0x544];
+ u32 sataliodnr[4];
+ u8 res_560[0x570-0x560];
+
+ u32 dcfg_ccsr_misc1liodnr;
+ u32 dcfg_ccsr_misc2liodnr;
+ u32 dcfg_ccsr_misc3liodnr;
+ u32 dcfg_ccsr_misc4liodnr;
+ u32 dcfg_ccsr_dma1liodnr;
+ u32 dcfg_ccsr_dma2liodnr;
+ u32 dcfg_ccsr_dma3liodnr;
+ u32 dcfg_ccsr_dma4liodnr;
+ u32 dcfg_ccsr_spare1liodnr;
+ u32 dcfg_ccsr_spare2liodnr;
+ u32 dcfg_ccsr_spare3liodnr;
+ u32 dcfg_ccsr_spare4liodnr;
+ u8 res_5a0[0x600-0x5a0];
+ u32 dcfg_ccsr_pblsr;
+
+ u32 pamubypenr;
+ u32 dmacr1;
+
+ u8 res_60c[0x610-0x60c];
+ u32 dcfg_ccsr_gensr1;
+ u32 dcfg_ccsr_gensr2;
+ u32 dcfg_ccsr_gensr3;
+ u32 dcfg_ccsr_gensr4;
+ u32 dcfg_ccsr_gencr1;
+ u32 dcfg_ccsr_gencr2;
+ u32 dcfg_ccsr_gencr3;
+ u32 dcfg_ccsr_gencr4;
+ u32 dcfg_ccsr_gencr5;
+ u32 dcfg_ccsr_gencr6;
+ u32 dcfg_ccsr_gencr7;
+ u8 res_63c[0x658-0x63c];
+ u32 dcfg_ccsr_cgensr1;
+ u32 dcfg_ccsr_cgensr0;
+ u8 res_660[0x678-0x660];
+ u32 dcfg_ccsr_cgencr1;
+
+ u32 dcfg_ccsr_cgencr0;
+ u8 res_680[0x700-0x680];
+ u32 dcfg_ccsr_sriopstecr;
+ u32 dcfg_ccsr_dcsrcr;
+
+ u8 res_708[0x740-0x708]; /* add more registers when needed */
+ u32 tp_ityp[64]; /* Topology Initiator Type Register */
+ struct {
+ u32 upper;
+ u32 lower;
+ } tp_cluster[16];
+ u8 res_8c0[0xa00-0x8c0]; /* add more registers when needed */
+ u32 dcfg_ccsr_qmbm_warmrst;
+ u8 res_a04[0xa20-0xa04]; /* add more registers when needed */
+ u32 dcfg_ccsr_reserved0;
+ u32 dcfg_ccsr_reserved1;
+};
+
+#define SCFG_QSPI_CLKSEL 0x40100000
+#define SCFG_USBDRVVBUS_SELCR_USB1 0x00000000
+#define SCFG_USBDRVVBUS_SELCR_USB2 0x00000001
+#define SCFG_USBDRVVBUS_SELCR_USB3 0x00000002
+#define SCFG_USBPWRFAULT_INACTIVE 0x00000000
+#define SCFG_USBPWRFAULT_SHARED 0x00000001
+#define SCFG_USBPWRFAULT_DEDICATED 0x00000002
+#define SCFG_USBPWRFAULT_USB3_SHIFT 4
+#define SCFG_USBPWRFAULT_USB2_SHIFT 2
+#define SCFG_USBPWRFAULT_USB1_SHIFT 0
+
+#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
+#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
+
+/* Supplemental Configuration Unit */
+struct ccsr_scfg {
+ u8 res_000[0x100-0x000];
+ u32 usb2_icid;
+ u32 usb3_icid;
+ u8 res_108[0x114-0x108];
+ u32 dma_icid;
+ u32 sata_icid;
+ u32 usb1_icid;
+ u32 qe_icid;
+ u32 sdhc_icid;
+ u32 edma_icid;
+ u32 etr_icid;
+ u32 core_sft_rst[4];
+ u8 res_140[0x158-0x140];
+ u32 altcbar;
+ u32 qspi_cfg;
+ u8 res_160[0x180-0x160];
+ u32 dmamcr;
+ u8 res_184[0x18c-0x184];
+ u32 debug_icid;
+ u8 res_190[0x1a4-0x190];
+ u32 snpcnfgcr;
+ u8 res_1a8[0x1ac-0x1a8];
+ u32 intpcr;
+ u8 res_1b0[0x204-0x1b0];
+ u32 coresrencr;
+ u8 res_208[0x220-0x208];
+ u32 rvbar0_0;
+ u32 rvbar0_1;
+ u32 rvbar1_0;
+ u32 rvbar1_1;
+ u32 rvbar2_0;
+ u32 rvbar2_1;
+ u32 rvbar3_0;
+ u32 rvbar3_1;
+ u32 lpmcsr;
+ u8 res_244[0x400-0x244];
+ u32 qspidqscr;
+ u32 ecgtxcmcr;
+ u32 sdhciovselcr;
+ u32 rcwpmuxcr0;
+ u32 usbdrvvbus_selcr;
+ u32 usbpwrfault_selcr;
+ u32 usb_refclk_selcr1;
+ u32 usb_refclk_selcr2;
+ u32 usb_refclk_selcr3;
+ u8 res_424[0x600-0x424];
+ u32 scratchrw[4];
+ u8 res_610[0x680-0x610];
+ u32 corebcr;
+ u8 res_684[0x1000-0x684];
+ u32 pex1msiir;
+ u32 pex1msir;
+ u8 res_1008[0x2000-0x1008];
+ u32 pex2;
+ u32 pex2msir;
+ u8 res_2008[0x3000-0x2008];
+ u32 pex3msiir;
+ u32 pex3msir;
+};
+
+/* Clocking */
+struct ccsr_clk {
+ struct {
+ u32 clkcncsr; /* core cluster n clock control status */
+ u8 res_004[0x0c];
+ u32 clkcghwacsr; /* Clock generator n hardware accelerator */
+ u8 res_014[0x0c];
+ } clkcsr[4];
+ u8 res_040[0x780]; /* 0x100 */
+ struct {
+ u32 pllcngsr;
+ u8 res_804[0x1c];
+ } pllcgsr[2];
+ u8 res_840[0x1c0];
+ u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
+ u8 res_a04[0x1fc];
+ u32 pllpgsr; /* 0xc00 Platform PLL General Status */
+ u8 res_c04[0x1c];
+ u32 plldgsr; /* 0xc20 DDR PLL General Status */
+ u8 res_c24[0x3dc];
+};
+
+/* System Counter */
+struct sctr_regs {
+ u32 cntcr;
+ u32 cntsr;
+ u32 cntcv1;
+ u32 cntcv2;
+ u32 resv1[4];
+ u32 cntfid0;
+ u32 cntfid1;
+ u32 resv2[1002];
+ u32 counterid[12];
+};
+
+#define SRDS_MAX_LANES 4
+struct ccsr_serdes {
+ struct {
+ u32 rstctl; /* Reset Control Register */
+#define SRDS_RSTCTL_RST 0x80000000
+#define SRDS_RSTCTL_RSTDONE 0x40000000
+#define SRDS_RSTCTL_RSTERR 0x20000000
+#define SRDS_RSTCTL_SWRST 0x10000000
+#define SRDS_RSTCTL_SDEN 0x00000020
+#define SRDS_RSTCTL_SDRST_B 0x00000040
+#define SRDS_RSTCTL_PLLRST_B 0x00000080
+ u32 pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_POFF 0x80000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
+#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
+#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
+#define SRDS_PLLCR0_PLL_LCK 0x00800000
+#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
+#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
+#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
+#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
+#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
+ u32 pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
+ u32 res_0c; /* 0x00c */
+ u32 pllcr3;
+ u32 pllcr4;
+ u8 res_18[0x20-0x18];
+ } bank[2];
+ u8 res_40[0x90-0x40];
+ u32 srdstcalcr; /* 0x90 TX Calibration Control */
+ u8 res_94[0xa0-0x94];
+ u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
+ u8 res_a4[0xb0-0xa4];
+ u32 srdsgr0; /* 0xb0 General Register 0 */
+ u8 res_b4[0xe0-0xb4];
+ u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
+ u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
+ u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
+ u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
+ u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
+ u8 res_f4[0x100-0xf4];
+ struct {
+ u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
+ u8 res_104[0x120-0x104];
+ } srdslnpssr[4];
+ u8 res_180[0x300-0x180];
+ u32 srdspexeqcr;
+ u32 srdspexeqpcr[11];
+ u8 res_330[0x400-0x330];
+ u32 srdspexapcr;
+ u8 res_404[0x440-0x404];
+ u32 srdspexbpcr;
+ u8 res_444[0x800-0x444];
+ struct {
+ u32 gcr0; /* 0x800 General Control Register 0 */
+ u32 gcr1; /* 0x804 General Control Register 1 */
+ u32 gcr2; /* 0x808 General Control Register 2 */
+ u32 sscr0;
+ u32 recr0; /* 0x810 Receive Equalization Control */
+ u32 recr1;
+ u32 tecr0; /* 0x818 Transmit Equalization Control */
+ u32 sscr1;
+ u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
+ u8 res_824[0x83c-0x824];
+ u32 tcsr3;
+ } lane[4]; /* Lane A, B, C, D, E, F, G, H */
+ u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
+};
+
+#define CCI400_CTRLORD_TERM_BARRIER 0x00000008
+#define CCI400_CTRLORD_EN_BARRIER 0
+#define CCI400_SHAORD_NON_SHAREABLE 0x00000002
+#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002
+#define CCI400_SNOOP_REQ_EN 0x00000001
+
+/* CCI-400 registers */
+struct ccsr_cci400 {
+ u32 ctrl_ord; /* Control Override */
+ u32 spec_ctrl; /* Speculation Control */
+ u32 secure_access; /* Secure Access */
+ u32 status; /* Status */
+ u32 impr_err; /* Imprecise Error */
+ u8 res_14[0x100 - 0x14];
+ u32 pmcr; /* Performance Monitor Control */
+ u8 res_104[0xfd0 - 0x104];
+ u32 pid[8]; /* Peripheral ID */
+ u32 cid[4]; /* Component ID */
+ struct {
+ u32 snoop_ctrl; /* Snoop Control */
+ u32 sha_ord; /* Shareable Override */
+ u8 res_1008[0x1100 - 0x1008];
+ u32 rc_qos_ord; /* read channel QoS Value Override */
+ u32 wc_qos_ord; /* read channel QoS Value Override */
+ u8 res_1108[0x110c - 0x1108];
+ u32 qos_ctrl; /* QoS Control */
+ u32 max_ot; /* Max OT */
+ u8 res_1114[0x1130 - 0x1114];
+ u32 target_lat; /* Target Latency */
+ u32 latency_regu; /* Latency Regulation */
+ u32 qos_range; /* QoS Range */
+ u8 res_113c[0x2000 - 0x113c];
+ } slave[5]; /* Slave Interface */
+ u8 res_6000[0x9004 - 0x6000];
+ u32 cycle_counter; /* Cycle counter */
+ u32 count_ctrl; /* Count Control */
+ u32 overflow_status; /* Overflow Flag Status */
+ u8 res_9010[0xa000 - 0x9010];
+ struct {
+ u32 event_select; /* Event Select */
+ u32 event_count; /* Event Count */
+ u32 counter_ctrl; /* Counter Control */
+ u32 overflow_status; /* Overflow Flag Status */
+ u8 res_a010[0xb000 - 0xa010];
+ } pcounter[4]; /* Performance Counter */
+ u8 res_e004[0x10000 - 0xe004];
+};
+
+/* MMU 500 */
+#define SMMU_SCR0 (SMMU_BASE + 0x0)
+#define SMMU_SCR1 (SMMU_BASE + 0x4)
+#define SMMU_SCR2 (SMMU_BASE + 0x8)
+#define SMMU_SACR (SMMU_BASE + 0x10)
+#define SMMU_IDR0 (SMMU_BASE + 0x20)
+#define SMMU_IDR1 (SMMU_BASE + 0x24)
+
+#define SMMU_NSCR0 (SMMU_BASE + 0x400)
+#define SMMU_NSCR2 (SMMU_BASE + 0x408)
+#define SMMU_NSACR (SMMU_BASE + 0x410)
+
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SCR0_USFCFG_MASK 0x00000400
+
+#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index d6bee60..6a70d44 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -6,9 +6,109 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __ARCH_FSL_LSCH3_IMMAP_H
+#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
#define __ARCH_FSL_LSCH3_IMMAP_H_
+#define CONFIG_SYS_IMMR 0x01000000
+#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
+#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
+#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
+#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
+#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
+#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
+#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
+#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
+#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
+#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
+#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
+ 0x18A0)
+
+#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
+#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
+
+/* SP (Cortex-A5) related */
+#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
+ (CONFIG_SYS_FSL_SP_ADDR + 0x0008)
+#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
+ (CONFIG_SYS_FSL_SP_ADDR + 0x1000)
+
+#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
+#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
+
+#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
+#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
+#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
+#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
+
+#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
+
+/* TZ Address Space Controller Definitions */
+#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
+#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
+#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
+#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
+#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
+#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
+#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
+#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
+#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
+#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
+#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
+#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
+#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
+
+/* PCIe */
+#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
+#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
+#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
+
+/* Device Configuration */
+#define DCFG_BASE 0x01e00000
+#define DCFG_PORSR1 0x000
+#define DCFG_PORSR1_RCW_SRC 0xff800000
+#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
+#define DCFG_RCWSR13 0x130
+#define DCFG_RCWSR13_DSPI (0 << 8)
+
+#define DCFG_DCSR_BASE 0X700100000ULL
+#define DCFG_DCSR_PORCR1 0x000
+
+/* Supplemental Configuration */
+#define SCFG_BASE 0x01fc0000
+#define SCFG_USB3PRM1CR 0x000
+
+#define TP_ITYP_AV 0x00000001 /* Initiator available */
+#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
+#define TP_ITYP_TYPE_ARM 0x0
+#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
+#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
+#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
+#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
+#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
+#define TY_ITYP_VER_A7 0x1
+#define TY_ITYP_VER_A53 0x2
+#define TY_ITYP_VER_A57 0x3
+
+#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
+#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
+#define TP_INIT_PER_CLUSTER 4
/* This is chassis generation 3 */
struct sys_info {
@@ -109,21 +209,6 @@ struct ccsr_gur {
u8 res_858[0x1000-0x858];
};
-#define TP_ITYP_AV 0x00000001 /* Initiator available */
-#define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
-#define TP_ITYP_TYPE_ARM 0x0
-#define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
-#define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
-#define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
-#define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
-#define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
-#define TY_ITYP_VER_A7 0x1
-#define TY_ITYP_VER_A53 0x2
-#define TY_ITYP_VER_A57 0x3
-
-#define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
-#define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
-#define TP_INIT_PER_CLUSTER 4
struct ccsr_clk_cluster_group {
struct {
@@ -180,4 +265,4 @@ struct ccsr_reset {
u32 ip_rev1; /* 0xbf8 */
u32 ip_rev2; /* 0xbfc */
};
-#endif /* __ARCH_FSL_LSCH3_IMMAP_H */
+#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
new file mode 100644
index 0000000..57e417b
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/imx-regs.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
+#define __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__
+
+#define I2C_QUIRK_REG /* enable 8-bit driver */
+
+#ifdef CONFIG_FSL_LPUART
+#ifdef CONFIG_LPUART_32B_REG
+struct lpuart_fsl {
+ u32 baud;
+ u32 stat;
+ u32 ctrl;
+ u32 data;
+ u32 match;
+ u32 modir;
+ u32 fifo;
+ u32 water;
+};
+#else
+struct lpuart_fsl {
+ u8 ubdh;
+ u8 ubdl;
+ u8 uc1;
+ u8 uc2;
+ u8 us1;
+ u8 us2;
+ u8 uc3;
+ u8 ud;
+ u8 uma1;
+ u8 uma2;
+ u8 uc4;
+ u8 uc5;
+ u8 ued;
+ u8 umodem;
+ u8 uir;
+ u8 reserved;
+ u8 upfifo;
+ u8 ucfifo;
+ u8 usfifo;
+ u8 utwfifo;
+ u8 utcfifo;
+ u8 urwfifo;
+ u8 urcfifo;
+ u8 rsvd[28];
+};
+#endif
+#endif /* CONFIG_FSL_LPUART */
+
+#endif /* __ASM_ARCH_FSL_LAYERSCAPE_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h b/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h
index 5c94530..5c94530 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ls2085a_stream_id.h
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mmu.h b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h
new file mode 100644
index 0000000..d54eacd
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mmu.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2015, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_
+#include <asm/arch-armv8/mmu.h>
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_MMU_H_ */
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
index c985d6a..e46e076 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h
@@ -1,11 +1,11 @@
/*
- * Copyright 2014, Freescale Semiconductor
+ * Copyright 2014-2015, Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _FSL_CH3_MP_H
-#define _FSL_CH3_MP_H
+#ifndef _FSL_LAYERSCAPE_MP_H
+#define _FSL_LAYERSCAPE_MP_H
/*
* Each spin table element is defined as
@@ -29,10 +29,10 @@ extern u64 __spin_table[];
extern u64 __real_cntfrq;
extern u64 *secondary_boot_code;
extern size_t __secondary_boot_code_size;
-int fsl_lsch3_wake_seconday_cores(void);
+int fsl_layerscape_wake_seconday_cores(void);
void *get_spin_tbl_addr(void);
phys_addr_t determine_mp_bootpg(void);
void secondary_boot_func(void);
int is_core_online(u64 cpu_id);
#endif
-#endif /* _FSL_CH3_MP_H */
+#endif /* _FSL_LAYERSCAPE_MP_H */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
new file mode 100644
index 0000000..a3ccdb0
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_NS_ACCESS_H_
+#define __FSL_NS_ACCESS_H_
+
+enum csu_cslx_ind {
+ CSU_CSLX_PCIE2_IO = 0,
+ CSU_CSLX_PCIE1_IO,
+ CSU_CSLX_MG2TPR_IP,
+ CSU_CSLX_IFC_MEM,
+ CSU_CSLX_OCRAM,
+ CSU_CSLX_GIC,
+ CSU_CSLX_PCIE1,
+ CSU_CSLX_OCRAM2,
+ CSU_CSLX_QSPI_MEM,
+ CSU_CSLX_PCIE2,
+ CSU_CSLX_SATA,
+ CSU_CSLX_USB1,
+ CSU_CSLX_QM_BM_SWPORTAL,
+ CSU_CSLX_PCIE3 = 16,
+ CSU_CSLX_PCIE3_IO,
+ CSU_CSLX_USB3 = 20,
+ CSU_CSLX_USB2,
+ CSU_CSLX_SERDES = 32,
+ CSU_CSLX_QDMA,
+ CSU_CSLX_LPUART2,
+ CSU_CSLX_LPUART1,
+ CSU_CSLX_LPUART4,
+ CSU_CSLX_LPUART3,
+ CSU_CSLX_LPUART6,
+ CSU_CSLX_LPUART5,
+ CSU_CSLX_DSPI1 = 41,
+ CSU_CSLX_QSPI,
+ CSU_CSLX_ESDHC,
+ CSU_CSLX_IFC = 45,
+ CSU_CSLX_I2C1,
+ CSU_CSLX_I2C3 = 48,
+ CSU_CSLX_I2C2,
+ CSU_CSLX_DUART2 = 50,
+ CSU_CSLX_DUART1,
+ CSU_CSLX_WDT2,
+ CSU_CSLX_WDT1,
+ CSU_CSLX_EDMA,
+ CSU_CSLX_SYS_CNT,
+ CSU_CSLX_DMA_MUX2,
+ CSU_CSLX_DMA_MUX1,
+ CSU_CSLX_DDR,
+ CSU_CSLX_QUICC,
+ CSU_CSLX_DCFG_CCU_RCPM = 60,
+ CSU_CSLX_SECURE_BOOTROM,
+ CSU_CSLX_SFP,
+ CSU_CSLX_TMU,
+ CSU_CSLX_SECURE_MONITOR,
+ CSU_CSLX_SCFG,
+ CSU_CSLX_FM = 66,
+ CSU_CSLX_SEC5_5,
+ CSU_CSLX_BM,
+ CSU_CSLX_QM,
+ CSU_CSLX_GPIO2 = 70,
+ CSU_CSLX_GPIO1,
+ CSU_CSLX_GPIO4,
+ CSU_CSLX_GPIO3,
+ CSU_CSLX_PLATFORM_CONT,
+ CSU_CSLX_CSU,
+ CSU_CSLX_IIC4 = 77,
+ CSU_CSLX_WDT4,
+ CSU_CSLX_WDT3,
+ CSU_CSLX_WDT5 = 81,
+ CSU_CSLX_FTM2 = 86,
+ CSU_CSLX_FTM1,
+ CSU_CSLX_FTM4,
+ CSU_CSLX_FTM3,
+ CSU_CSLX_FTM6 = 90,
+ CSU_CSLX_FTM5,
+ CSU_CSLX_FTM8,
+ CSU_CSLX_FTM7,
+ CSU_CSLX_DSCR = 121,
+};
+
+static struct csu_ns_dev ns_dev[] = {
+ {CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
+ {CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
+ {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
+ {CSU_CSLX_IFC_MEM, CSU_ALL_RW},
+ {CSU_CSLX_OCRAM, CSU_ALL_RW},
+ {CSU_CSLX_GIC, CSU_ALL_RW},
+ {CSU_CSLX_PCIE1, CSU_ALL_RW},
+ {CSU_CSLX_OCRAM2, CSU_ALL_RW},
+ {CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
+ {CSU_CSLX_PCIE2, CSU_ALL_RW},
+ {CSU_CSLX_SATA, CSU_ALL_RW},
+ {CSU_CSLX_USB1, CSU_ALL_RW},
+ {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
+ {CSU_CSLX_PCIE3, CSU_ALL_RW},
+ {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
+ {CSU_CSLX_USB3, CSU_ALL_RW},
+ {CSU_CSLX_USB2, CSU_ALL_RW},
+ {CSU_CSLX_SERDES, CSU_ALL_RW},
+ {CSU_CSLX_QDMA, CSU_ALL_RW},
+ {CSU_CSLX_LPUART2, CSU_ALL_RW},
+ {CSU_CSLX_LPUART1, CSU_ALL_RW},
+ {CSU_CSLX_LPUART4, CSU_ALL_RW},
+ {CSU_CSLX_LPUART3, CSU_ALL_RW},
+ {CSU_CSLX_LPUART6, CSU_ALL_RW},
+ {CSU_CSLX_LPUART5, CSU_ALL_RW},
+ {CSU_CSLX_DSPI1, CSU_ALL_RW},
+ {CSU_CSLX_QSPI, CSU_ALL_RW},
+ {CSU_CSLX_ESDHC, CSU_ALL_RW},
+ {CSU_CSLX_IFC, CSU_ALL_RW},
+ {CSU_CSLX_I2C1, CSU_ALL_RW},
+ {CSU_CSLX_I2C3, CSU_ALL_RW},
+ {CSU_CSLX_I2C2, CSU_ALL_RW},
+ {CSU_CSLX_DUART2, CSU_ALL_RW},
+ {CSU_CSLX_DUART1, CSU_ALL_RW},
+ {CSU_CSLX_WDT2, CSU_ALL_RW},
+ {CSU_CSLX_WDT1, CSU_ALL_RW},
+ {CSU_CSLX_EDMA, CSU_ALL_RW},
+ {CSU_CSLX_SYS_CNT, CSU_ALL_RW},
+ {CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
+ {CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
+ {CSU_CSLX_DDR, CSU_ALL_RW},
+ {CSU_CSLX_QUICC, CSU_ALL_RW},
+ {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
+ {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
+ {CSU_CSLX_SFP, CSU_ALL_RW},
+ {CSU_CSLX_TMU, CSU_ALL_RW},
+ {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
+ {CSU_CSLX_SCFG, CSU_ALL_RW},
+ {CSU_CSLX_FM, CSU_ALL_RW},
+ {CSU_CSLX_SEC5_5, CSU_ALL_RW},
+ {CSU_CSLX_BM, CSU_ALL_RW},
+ {CSU_CSLX_QM, CSU_ALL_RW},
+ {CSU_CSLX_GPIO2, CSU_ALL_RW},
+ {CSU_CSLX_GPIO1, CSU_ALL_RW},
+ {CSU_CSLX_GPIO4, CSU_ALL_RW},
+ {CSU_CSLX_GPIO3, CSU_ALL_RW},
+ {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
+ {CSU_CSLX_CSU, CSU_ALL_RW},
+ {CSU_CSLX_IIC4, CSU_ALL_RW},
+ {CSU_CSLX_WDT4, CSU_ALL_RW},
+ {CSU_CSLX_WDT3, CSU_ALL_RW},
+ {CSU_CSLX_WDT5, CSU_ALL_RW},
+ {CSU_CSLX_FTM2, CSU_ALL_RW},
+ {CSU_CSLX_FTM1, CSU_ALL_RW},
+ {CSU_CSLX_FTM4, CSU_ALL_RW},
+ {CSU_CSLX_FTM3, CSU_ALL_RW},
+ {CSU_CSLX_FTM6, CSU_ALL_RW},
+ {CSU_CSLX_FTM5, CSU_ALL_RW},
+ {CSU_CSLX_FTM8, CSU_ALL_RW},
+ {CSU_CSLX_FTM7, CSU_ALL_RW},
+ {CSU_CSLX_DSCR, CSU_ALL_RW},
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
new file mode 100644
index 0000000..5ed456e
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
+#define _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_
+
+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE
+#define gur_in32(a) in_le32(a)
+#define gur_out32(a, v) out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)
+#define gur_in32(a) in_be32(a)
+#define gur_out32(a, v) out_be32(a, v)
+#endif
+
+#ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define scfg_in32(a) in_le32(a)
+#define scfg_out32(a, v) out_le32(a, v)
+#elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)
+#define scfg_in32(a) in_be32(a)
+#define scfg_out32(a, v) out_be32(a, v)
+#endif
+
+struct cpu_type {
+ char name[15];
+ u32 soc_ver;
+ u32 num_cores;
+};
+
+#define CPU_TYPE_ENTRY(n, v, nc) \
+ { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
+
+#define SVR_WO_E 0xFFFFFE
+#define SVR_LS1043 0x879204
+#define SVR_LS2045 0x870120
+#define SVR_LS2080 0x870110
+#define SVR_LS2085 0x870100
+
+#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
+#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
+#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
+#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
+
+#ifdef CONFIG_FSL_LSCH3
+void fsl_lsch3_early_init_f(void);
+#elif defined(CONFIG_FSL_LSCH2)
+void fsl_lsch2_early_init_f(void);
+#endif
+
+void cpu_name(char *name);
+#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/speed.h b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
new file mode 100644
index 0000000..de795f6
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/speed.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2014-2015, Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _FSL_LAYERSCAPE_SPEED_H
+#define _FSL_LAYERSCAPE_SPEED_H
+void get_sys_info(struct sys_info *sys_info);
+#endif /* _FSL_LAYERSCAPE_SPEED_H */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
deleted file mode 100644
index 96d6c98..0000000
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Copyright 2014, Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_
-#define _ASM_ARMV8_FSL_LSCH3_CONFIG_
-
-#include <fsl_ddrc_version.h>
-
-#define CONFIG_SYS_PAGE_SIZE 0x10000
-#define CONFIG_SYS_CACHELINE_SIZE 64
-
-#ifndef L1_CACHE_BYTES
-#define L1_CACHE_SHIFT 6
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-#endif
-
-#define CONFIG_MP
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
-/* Link Definitions */
-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
-
-#define CONFIG_SYS_IMMR 0x01000000
-#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
-#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
-#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
-#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
-#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
-#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
-#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
-#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
-#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
-#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
-#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
-#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
- 0x18A0)
-
-#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
-#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
-
-/* SP (Cortex-A5) related */
-#define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
- (CONFIG_SYS_FSL_SP_ADDR + 0x0008)
-#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
- (CONFIG_SYS_FSL_SP_ADDR + 0x1000)
-
-#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
-
-#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
-#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
-#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
-#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
-
-#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
-
-/* TZ Protection Controller Definitions */
-#define TZPC_BASE 0x02200000
-#define TZPCR0SIZE_BASE (TZPC_BASE)
-#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
-#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
-#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
-#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
-#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
-#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
-#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
-#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
-#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
-
-/* TZ Address Space Controller Definitions */
-#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
-#define TZASC2_BASE 0x01110000 /* as per CCSR map. */
-#define TZASC3_BASE 0x01120000 /* as per CCSR map. */
-#define TZASC4_BASE 0x01130000 /* as per CCSR map. */
-#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
-#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
-#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
-#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
-#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
-#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
-#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
-#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
-#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
-
-/* Generic Interrupt Controller Definitions */
-#define GICD_BASE 0x06000000
-#define GICR_BASE 0x06100000
-
-/* SMMU Defintions */
-#define SMMU_BASE 0x05000000 /* GR0 Base */
-
-/* DDR */
-#define CONFIG_SYS_FSL_DDR_LE
-#define CONFIG_VERY_BIG_RAM
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#else
-#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
-#endif
-#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
-#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
-#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
-
-#define CONFIG_SYS_FSL_ESDHC_LE
-/* IFC */
-#define CONFIG_SYS_FSL_IFC_LE
-#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
-
-/* PCIe */
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
-#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
-#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
-#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
-#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
-#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
-#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
-#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
-
-/* Cache Coherent Interconnect */
-#define CCI_MN_BASE 0x04000000
-#define CCI_MN_RNF_NODEID_LIST 0x180
-#define CCI_MN_DVM_DOMAIN_CTL 0x200
-#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
-
-#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
-#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
-#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
-#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
-#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
-#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
-
-#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
-#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
-#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
-
-/* Device Configuration */
-#define DCFG_BASE 0x01e00000
-#define DCFG_PORSR1 0x000
-#define DCFG_PORSR1_RCW_SRC 0xff800000
-#define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
-#define DCFG_RCWSR13 0x130
-#define DCFG_RCWSR13_DSPI (0 << 8)
-
-#define DCFG_DCSR_BASE 0X700100000ULL
-#define DCFG_DCSR_PORCR1 0x000
-
-/* Supplemental Configuration */
-#define SCFG_BASE 0x01fc0000
-#define SCFG_USB3PRM1CR 0x000
-
-#ifdef CONFIG_LS2085A
-#define CONFIG_MAX_CPUS 16
-#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_NUM_DDR_CONTROLLERS 3
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
-#define CONFIG_SYS_FSL_SRDS_1
-#define CONFIG_SYS_FSL_SRDS_2
-#else
-#error SoC not defined
-#endif
-
-#ifdef CONFIG_LS2085A
-#define CONFIG_SYS_FSL_ERRATUM_A008336
-#define CONFIG_SYS_FSL_ERRATUM_A008511
-#define CONFIG_SYS_FSL_ERRATUM_A008514
-#define CONFIG_SYS_FSL_ERRATUM_A008585
-#define CONFIG_SYS_FSL_ERRATUM_A008751
-#endif
-
-#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
deleted file mode 100644
index 2810f3f..0000000
--- a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __FSL_SERDES_H
-#define __FSL_SERDES_H
-
-#include <config.h>
-
-#define SRDS_MAX_LANES 8
-
-enum srds_prtcl {
- NONE = 0,
- PCIE1,
- PCIE2,
- PCIE3,
- PCIE4,
- SATA1,
- SATA2,
- XAUI1,
- XAUI2,
- XFI1,
- XFI2,
- XFI3,
- XFI4,
- XFI5,
- XFI6,
- XFI7,
- XFI8,
- SGMII1,
- SGMII2,
- SGMII3,
- SGMII4,
- SGMII5,
- SGMII6,
- SGMII7,
- SGMII8,
- SGMII9,
- SGMII10,
- SGMII11,
- SGMII12,
- SGMII13,
- SGMII14,
- SGMII15,
- SGMII16,
- QSGMII_A, /* A indicates MACs 1-4 */
- QSGMII_B, /* B indicates MACs 5-8 */
- QSGMII_C, /* C indicates MACs 9-12 */
- QSGMII_D, /* D indicates MACs 12-16 */
- SERDES_PRCTL_COUNT
-};
-
-enum srds {
- FSL_SRDS_1 = 0,
- FSL_SRDS_2 = 1,
-};
-
-int is_serdes_configured(enum srds_prtcl device);
-void fsl_serdes_init(void);
-
-int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
-enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
-int is_serdes_prtcl_valid(int serdes, u32 prtcl);
-
-#endif /* __FSL_SERDES_H */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/gpio.h b/arch/arm/include/asm/arch-fsl-lsch3/gpio.h
deleted file mode 100644
index f23a78c..0000000
--- a/arch/arm/include/asm/arch-fsl-lsch3/gpio.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright 2014, Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARMV8_FSL_LSCH3_GPIO_H_
-#define _ASM_ARMV8_FSL_LSCH3_GPIO_H_
-#endif /* _ASM_ARMV8_FSL_LSCH3_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h b/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h
deleted file mode 100644
index 8f00535..0000000
--- a/arch/arm/include/asm/arch-fsl-lsch3/imx-regs.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- */
-
-#ifndef __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
-#define __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_
-
-#define I2C_QUIRK_REG /* enable 8-bit driver */
-
-#endif /* __ASM_ARCH_FSL_LSCH3_IMX_REGS_H_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
deleted file mode 100644
index 9a29272..0000000
--- a/arch/arm/include/asm/arch-fsl-lsch3/soc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright 2015 Freescale Semiconductor
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-struct cpu_type {
- char name[15];
- u32 soc_ver;
- u32 num_cores;
-};
-
-#define CPU_TYPE_ENTRY(n, v, nc) \
- { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
-
-#define SVR_WO_E 0xFFFFFE
-#define SVR_LS2045 0x870120
-#define SVR_LS2080 0x870110
-#define SVR_LS2085 0x870100
-
-#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
-#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
-#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
-#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
-
-void fsl_lsch3_early_init_f(void);
-void cpu_name(char *name);
-
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index bcaf7bf..f066480 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -79,6 +79,21 @@
#define CONFIG_SYS_PCIE2_PHYS_ADDR (CONFIG_SYS_PCIE2_PHYS_BASE + \
CONFIG_SYS_PCIE2_VIRT_ADDR)
+/* SATA */
+#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
+#define CONFIG_SYS_SCSI_MAX_LUN 1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_FSL_ERRATUM_A008407
+
#ifdef CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_VERY_BIG_RAM
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 60aa0d3..09ed980 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -144,6 +144,7 @@ struct ccsr_gur {
};
#define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00
+#define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
#define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
#define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
@@ -397,4 +398,28 @@ struct ccsr_cci400 {
u8 res_e004[0x10000 - 0xe004];
};
+/* AHCI (sata) register map */
+struct ccsr_ahci {
+ u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
+ u32 pcfg; /* port config */
+ u32 ppcfg; /* port phy1 config */
+ u32 pp2c; /* port phy2 config */
+ u32 pp3c; /* port phy3 config */
+ u32 pp4c; /* port phy4 config */
+ u32 pp5c; /* port phy5 config */
+ u32 paxic; /* port AXI config */
+ u32 axicc; /* AXI cache control */
+ u32 axipc; /* AXI PROT control */
+ u32 ptc; /* port Trans Config */
+ u32 pts; /* port Trans Status */
+ u32 plc; /* port link config */
+ u32 plc1; /* port link config1 */
+ u32 plc2; /* port link config2 */
+ u32 pls; /* port link status */
+ u32 pls1; /* port link status1 */
+ u32 pcmdc; /* port CMD config */
+ u32 ppcs; /* port phy control status */
+ u32 pberr; /* port 0/1 BIST error */
+ u32 cmds; /* port 0/1 CMD status error */
+};
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
new file mode 100644
index 0000000..d097a6a
--- /dev/null
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __FSL_SATA_H_
+#define __FSL_SATA_H_
+
+int ls1021a_sata_init(void);
+#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h
index b53f699..a921fb6 100644
--- a/arch/arm/include/asm/arch-ls102xa/ns_access.h
+++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h
@@ -7,22 +7,6 @@
#ifndef __FSL_NS_ACCESS_H_
#define __FSL_NS_ACCESS_H_
-enum csu_cslx_access {
- CSU_NS_SUP_R = 0x08,
- CSU_NS_SUP_W = 0x80,
- CSU_NS_SUP_RW = 0x88,
- CSU_NS_USER_R = 0x04,
- CSU_NS_USER_W = 0x40,
- CSU_NS_USER_RW = 0x44,
- CSU_S_SUP_R = 0x02,
- CSU_S_SUP_W = 0x20,
- CSU_S_SUP_RW = 0x22,
- CSU_S_USER_R = 0x01,
- CSU_S_USER_W = 0x10,
- CSU_S_USER_RW = 0x11,
- CSU_ALL_RW = 0xff,
-};
-
enum csu_cslx_ind {
CSU_CSLX_PCIE2_IO = 0,
CSU_CSLX_PCIE1_IO,
@@ -108,11 +92,88 @@ enum csu_cslx_ind {
CSU_CSLX_MAX,
};
-struct csu_ns_dev {
- unsigned long ind;
- uint32_t val;
+static struct csu_ns_dev ns_dev[] = {
+ { CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
+ { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
+ { CSU_CSLX_IFC_MEM, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM, CSU_ALL_RW },
+ { CSU_CSLX_GIC, CSU_ALL_RW },
+ { CSU_CSLX_PCIE1, CSU_ALL_RW },
+ { CSU_CSLX_OCRAM2, CSU_ALL_RW },
+ { CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
+ { CSU_CSLX_PCIE2, CSU_ALL_RW },
+ { CSU_CSLX_SATA, CSU_ALL_RW },
+ { CSU_CSLX_USB3, CSU_ALL_RW },
+ { CSU_CSLX_SERDES, CSU_ALL_RW },
+ { CSU_CSLX_QDMA, CSU_ALL_RW },
+ { CSU_CSLX_LPUART2, CSU_ALL_RW },
+ { CSU_CSLX_LPUART1, CSU_ALL_RW },
+ { CSU_CSLX_LPUART4, CSU_ALL_RW },
+ { CSU_CSLX_LPUART3, CSU_ALL_RW },
+ { CSU_CSLX_LPUART6, CSU_ALL_RW },
+ { CSU_CSLX_LPUART5, CSU_ALL_RW },
+ { CSU_CSLX_DSPI2, CSU_ALL_RW },
+ { CSU_CSLX_DSPI1, CSU_ALL_RW },
+ { CSU_CSLX_QSPI, CSU_ALL_RW },
+ { CSU_CSLX_ESDHC, CSU_ALL_RW },
+ { CSU_CSLX_2D_ACE, CSU_ALL_RW },
+ { CSU_CSLX_IFC, CSU_ALL_RW },
+ { CSU_CSLX_I2C1, CSU_ALL_RW },
+ { CSU_CSLX_USB2, CSU_ALL_RW },
+ { CSU_CSLX_I2C3, CSU_ALL_RW },
+ { CSU_CSLX_I2C2, CSU_ALL_RW },
+ { CSU_CSLX_DUART2, CSU_ALL_RW },
+ { CSU_CSLX_DUART1, CSU_ALL_RW },
+ { CSU_CSLX_WDT2, CSU_ALL_RW },
+ { CSU_CSLX_WDT1, CSU_ALL_RW },
+ { CSU_CSLX_EDMA, CSU_ALL_RW },
+ { CSU_CSLX_SYS_CNT, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
+ { CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
+ { CSU_CSLX_DDR, CSU_ALL_RW },
+ { CSU_CSLX_QUICC, CSU_ALL_RW },
+ { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
+ { CSU_CSLX_SFP, CSU_ALL_RW },
+ { CSU_CSLX_TMU, CSU_ALL_RW },
+ { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED0, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC1, CSU_ALL_RW },
+ { CSU_CSLX_SEC5_5, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC3, CSU_ALL_RW },
+ { CSU_CSLX_ETSEC2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO2, CSU_ALL_RW },
+ { CSU_CSLX_GPIO1, CSU_ALL_RW },
+ { CSU_CSLX_GPIO4, CSU_ALL_RW },
+ { CSU_CSLX_GPIO3, CSU_ALL_RW },
+ { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
+ { CSU_CSLX_CSU, CSU_ALL_RW },
+ { CSU_CSLX_ASRC, CSU_ALL_RW },
+ { CSU_CSLX_SPDIF, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
+ { CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
+ { CSU_CSLX_SAI2, CSU_ALL_RW },
+ { CSU_CSLX_SAI1, CSU_ALL_RW },
+ { CSU_CSLX_SAI4, CSU_ALL_RW },
+ { CSU_CSLX_SAI3, CSU_ALL_RW },
+ { CSU_CSLX_FTM2, CSU_ALL_RW },
+ { CSU_CSLX_FTM1, CSU_ALL_RW },
+ { CSU_CSLX_FTM4, CSU_ALL_RW },
+ { CSU_CSLX_FTM3, CSU_ALL_RW },
+ { CSU_CSLX_FTM6, CSU_ALL_RW },
+ { CSU_CSLX_FTM5, CSU_ALL_RW },
+ { CSU_CSLX_FTM8, CSU_ALL_RW },
+ { CSU_CSLX_FTM7, CSU_ALL_RW },
+ { CSU_CSLX_COP_DCSR, CSU_ALL_RW },
+ { CSU_CSLX_EPU, CSU_ALL_RW },
+ { CSU_CSLX_GDI, CSU_ALL_RW },
+ { CSU_CSLX_DDI, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED1, CSU_ALL_RW },
+ { CSU_CSLX_USB3_PHY, CSU_ALL_RW },
+ { CSU_CSLX_RESERVED2, CSU_ALL_RW },
};
-void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num);
-
#endif
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 587ee39..d8d9af4 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -65,6 +65,7 @@
/*
* Section
*/
+#define PMD_SECT_NS (1 << 5)
#define PMD_SECT_NON_SHARE (0 << 8)
#define PMD_SECT_OUTER_SHARE (2 << 8)
#define PMD_SECT_INNER_SHARE (3 << 8)
diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index 22fff02..435fc45 100644
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -15,14 +15,11 @@
#define CONFIG_STATIC_RELA
#endif
-#ifdef CONFIG_FSL_LSCH3
-#include <asm/arch-fsl-lsch3/config.h>
-#endif
-
#if defined(CONFIG_LS102XA) || \
defined(CONFIG_CPU_PXA27X) || \
defined(CONFIG_CPU_MONAHANS) || \
- defined(CONFIG_CPU_PXA25X)
+ defined(CONFIG_CPU_PXA25X) || \
+ defined(CONFIG_FSL_LAYERSCAPE)
#include <asm/arch/config.h>
#endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index bfbe0a0..75773bd 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -46,7 +46,7 @@ static inline void sync(void)
static inline void *
map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
{
- return (void *)paddr;
+ return (void *)((unsigned long)paddr);
}
/*
@@ -59,7 +59,7 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags)
static inline phys_addr_t virt_to_phys(void * vaddr)
{
- return (phys_addr_t)(vaddr);
+ return (phys_addr_t)((unsigned long)vaddr);
}
/*
diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h
index ee77c41..388058e 100644
--- a/arch/arm/include/asm/types.h
+++ b/arch/arm/include/asm/types.h
@@ -45,12 +45,16 @@ typedef unsigned long long u64;
#define BITS_PER_LONG 32
#endif /* CONFIG_ARM64 */
-/* Dma addresses are 32-bits wide. */
-
+#ifdef CONFIG_PHYS_64BIT
+typedef unsigned long long dma_addr_t;
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
+#else
+/* DMA addresses are 32-bits wide */
typedef u32 dma_addr_t;
-
typedef unsigned long phys_addr_t;
typedef unsigned long phys_size_t;
+#endif
#endif /* __KERNEL__ */
diff --git a/arch/powerpc/include/asm/fsl_dtsec.h b/arch/powerpc/include/asm/fsl_dtsec.h
deleted file mode 100644
index 41b8398..0000000
--- a/arch/powerpc/include/asm/fsl_dtsec.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __DTSEC_H__
-#define __DTSEC_H__
-
-#include <asm/types.h>
-
-struct dtsec {
- u32 tsec_id; /* controller ID and version */
- u32 tsec_id2; /* controller ID and configuration */
- u32 ievent; /* interrupt event */
- u32 imask; /* interrupt mask */
- u32 res0;
- u32 ecntrl; /* ethernet control and configuration */
- u32 ptv; /* pause time value */
- u32 tbipa; /* TBI PHY address */
- u32 res1[8];
- u32 tctrl; /* Transmit control register */
- u32 res2[3];
- u32 rctrl; /* Receive control register */
- u32 res3[11];
- u32 igaddr[8]; /* Individual group address */
- u32 gaddr[8]; /* group address */
- u32 res4[16];
- u32 maccfg1; /* MAC configuration register 1 */
- u32 maccfg2; /* MAC configuration register 2 */
- u32 ipgifg; /* inter-packet/inter-frame gap */
- u32 hafdup; /* half-duplex control */
- u32 maxfrm; /* Maximum frame size */
- u32 res5[3];
- u32 miimcfg; /* MII management configuration */
- u32 miimcom; /* MII management command */
- u32 miimadd; /* MII management address */
- u32 miimcon; /* MII management control */
- u32 miimstat; /* MII management status */
- u32 miimind; /* MII management indicator */
- u32 res6;
- u32 ifstat; /* Interface status */
- u32 macstnaddr1; /* MAC station address 1 */
- u32 macstnaddr2; /* MAC station address 2 */
- u32 res7[46];
- /* transmit and receive counter */
- u32 tr64; /* Tx and Rx 64 bytes frame */
- u32 tr127; /* Tx and Rx 65 to 127 bytes frame */
- u32 tr255; /* Tx and Rx 128 to 255 bytes frame */
- u32 tr511; /* Tx and Rx 256 to 511 bytes frame */
- u32 tr1k; /* Tx and Rx 512 to 1023 bytes frame */
- u32 trmax; /* Tx and Rx 1024 to 1518 bytes frame */
- u32 trmgv; /* Tx and Rx 1519 to 1522 good VLAN frame */
- /* receive counters */
- u32 rbyt; /* Receive byte counter */
- u32 rpkt; /* Receive packet counter */
- u32 rfcs; /* Receive FCS error */
- u32 rmca; /* Receive multicast packet */
- u32 rbca; /* Receive broadcast packet */
- u32 rxcf; /* Receive control frame */
- u32 rxpf; /* Receive pause frame */
- u32 rxuo; /* Receive unknown OP code */
- u32 raln; /* Receive alignment error */
- u32 rflr; /* Receive frame length error */
- u32 rcde; /* Receive code error */
- u32 rcse; /* Receive carrier sense error */
- u32 rund; /* Receive undersize packet */
- u32 rovr; /* Receive oversize packet */
- u32 rfrg; /* Receive fragments counter */
- u32 rjbr; /* Receive jabber counter */
- u32 rdrp; /* Receive drop counter */
- /* transmit counters */
- u32 tbyt; /* Transmit byte counter */
- u32 tpkt; /* Transmit packet */
- u32 tmca; /* Transmit multicast packet */
- u32 tbca; /* Transmit broadcast packet */
- u32 txpf; /* Transmit pause control frame */
- u32 tdfr; /* Transmit deferral packet */
- u32 tedf; /* Transmit excessive deferral pkt */
- u32 tscl; /* Transmit single collision pkt */
- u32 tmcl; /* Transmit multiple collision pkt */
- u32 tlcl; /* Transmit late collision pkt */
- u32 txcl; /* Transmit excessive collision */
- u32 tncl; /* Transmit total collision */
- u32 res8;
- u32 tdrp; /* Transmit drop frame */
- u32 tjbr; /* Transmit jabber frame */
- u32 tfcs; /* Transmit FCS error */
- u32 txcf; /* Transmit control frame */
- u32 tovr; /* Transmit oversize frame */
- u32 tund; /* Transmit undersize frame */
- u32 tfrg; /* Transmit fragments frame */
- /* counter controls */
- u32 car1; /* carry register 1 */
- u32 car2; /* carry register 2 */
- u32 cam1; /* carry register 1 mask */
- u32 cam2; /* carry register 2 mask */
- u32 res9[80];
-};
-
-
-/* TBI register addresses */
-#define TBI_CR 0x00
-#define TBI_SR 0x01
-#define TBI_ANA 0x04
-#define TBI_ANLPBPA 0x05
-#define TBI_ANEX 0x06
-#define TBI_TBICON 0x11
-
-/* TBI MDIO register bit fields*/
-#define TBICON_CLK_SELECT 0x0020
-#define TBIANA_ASYMMETRIC_PAUSE 0x0100
-#define TBIANA_SYMMETRIC_PAUSE 0x0080
-#define TBIANA_HALF_DUPLEX 0x0040
-#define TBIANA_FULL_DUPLEX 0x0020
-#define TBICR_PHY_RESET 0x8000
-#define TBICR_ANEG_ENABLE 0x1000
-#define TBICR_RESTART_ANEG 0x0200
-#define TBICR_FULL_DUPLEX 0x0100
-#define TBICR_SPEED1_SET 0x0040
-
-/* IEVENT - interrupt events register */
-#define IEVENT_BABR 0x80000000 /* Babbling receive error */
-#define IEVENT_RXC 0x40000000 /* pause control frame received */
-#define IEVENT_MSRO 0x04000000 /* MIB counter overflow */
-#define IEVENT_GTSC 0x02000000 /* Graceful transmit stop complete */
-#define IEVENT_BABT 0x01000000 /* Babbling transmit error */
-#define IEVENT_TXC 0x00800000 /* control frame transmitted */
-#define IEVENT_TXE 0x00400000 /* Transmit channel error */
-#define IEVENT_LC 0x00040000 /* Late collision occurred */
-#define IEVENT_CRL 0x00020000 /* Collision retry exceed limit */
-#define IEVENT_XFUN 0x00010000 /* Transmit FIFO underrun */
-#define IEVENT_ABRT 0x00008000 /* Transmit packet abort */
-#define IEVENT_MMRD 0x00000400 /* MII management read complete */
-#define IEVENT_MMWR 0x00000200 /* MII management write complete */
-#define IEVENT_GRSC 0x00000100 /* Graceful stop complete */
-#define IEVENT_TDPE 0x00000002 /* Internal data parity error on Tx */
-#define IEVENT_RDPE 0x00000001 /* Internal data parity error on Rx */
-
-#define IEVENT_CLEAR_ALL 0xffffffff
-
-/* IMASK - interrupt mask register */
-#define IMASK_BREN 0x80000000 /* Babbling receive enable */
-#define IMASK_RXCEN 0x40000000 /* receive control enable */
-#define IMASK_MSROEN 0x04000000 /* MIB counter overflow enable */
-#define IMASK_GTSCEN 0x02000000 /* Graceful Tx stop complete enable */
-#define IMASK_BTEN 0x01000000 /* Babbling transmit error enable */
-#define IMASK_TXCEN 0x00800000 /* control frame transmitted enable */
-#define IMASK_TXEEN 0x00400000 /* Transmit channel error enable */
-#define IMASK_LCEN 0x00040000 /* Late collision interrupt enable */
-#define IMASK_CRLEN 0x00020000 /* Collision retry exceed limit */
-#define IMASK_XFUNEN 0x00010000 /* Transmit FIFO underrun enable */
-#define IMASK_ABRTEN 0x00008000 /* Transmit packet abort enable */
-#define IMASK_MMRDEN 0x00000400 /* MII management read complete enable */
-#define IMASK_MMWREN 0x00000200 /* MII management write complete enable */
-#define IMASK_GRSCEN 0x00000100 /* Graceful stop complete interrupt enable */
-#define IMASK_TDPEEN 0x00000002 /* Internal data parity error on Tx enable */
-#define IMASK_RDPEEN 0x00000001 /* Internal data parity error on Rx enable */
-
-#define IMASK_MASK_ALL 0x00000000
-
-/* ECNTRL - ethernet control register */
-#define ECNTRL_CFG_RO 0x80000000 /* GMIIM, RPM, R100M, SGMIIM bits are RO */
-#define ECNTRL_CLRCNT 0x00004000 /* clear all statistics */
-#define ECNTRL_AUTOZ 0x00002000 /* auto zero MIB counter */
-#define ECNTRL_STEN 0x00001000 /* enable internal counters to update */
-#define ECNTRL_GMIIM 0x00000040 /* 1- GMII or RGMII interface mode */
-#define ECNTRL_TBIM 0x00000020 /* 1- Ten-bit interface mode */
-#define ECNTRL_RPM 0x00000010 /* 1- RGMII reduced-pin mode */
-#define ECNTRL_R100M 0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps
- 0- RGMII 10 Mbps, SGMII 10 Mbps */
-#define ECNTRL_SGMIIM 0x00000002 /* 1- SGMII interface mode */
-#define ECNTRL_TBIM 0x00000020 /* 1- TBI Interface mode (for SGMII) */
-
-#define ECNTRL_DEFAULT (ECNTRL_TBIM | ECNTRL_R100M | ECNTRL_SGMIIM)
-
-/* TCTRL - Transmit control register */
-#define TCTRL_THDF 0x00000800 /* Transmit half-duplex flow control */
-#define TCTRL_TTSE 0x00000040 /* Transmit time-stamp enable */
-#define TCTRL_GTS 0x00000020 /* Graceful transmit stop */
-#define TCTRL_RFC_PAUSE 0x00000010 /* Receive flow control pause frame */
-
-/* RCTRL - Receive control register */
-#define RCTRL_PAL_MASK 0x001f0000 /* packet alignment padding length */
-#define RCTRL_PAL_SHIFT 16
-#define RCTRL_CFA 0x00008000 /* control frame accept enable */
-#define RCTRL_GHTX 0x00000800 /* group address hash table extend */
-#define RCTRL_RTSE 0x00000040 /* receive 1588 time-stamp enable */
-#define RCTRL_GRS 0x00000020 /* graceful receive stop */
-#define RCTRL_BC_REJ 0x00000010 /* broadcast frame reject */
-#define RCTRL_BC_MPROM 0x00000008 /* all multicast/broadcast frames received */
-#define RCTRL_RSF 0x00000004 /* receive short frame(17~63 bytes) enable */
-#define RCTRL_EMEN 0x00000002 /* Exact match MAC address enable */
-#define RCTRL_UPROM 0x00000001 /* all unicast frame received */
-
-/* MACCFG1 - MAC configuration 1 register */
-#define MACCFG1_SOFT_RST 0x80000000 /* place the MAC in reset */
-#define MACCFG1_RST_RXMAC 0x00080000 /* reset receive MAC control block */
-#define MACCFG1_RST_TXMAC 0x00040000 /* reet transmit MAC control block */
-#define MACCFG1_RST_RXFUN 0x00020000 /* reset receive function block */
-#define MACCFG1_RST_TXFUN 0x00010000 /* reset transmit function block */
-#define MACCFG1_LOOPBACK 0x00000100 /* MAC loopback */
-#define MACCFG1_RX_FLOW 0x00000020 /* Receive flow */
-#define MACCFG1_TX_FLOW 0x00000010 /* Transmit flow */
-#define MACCFG1_SYNC_RXEN 0x00000008 /* Frame reception enabled */
-#define MACCFG1_RX_EN 0x00000004 /* Rx enable */
-#define MACCFG1_SYNC_TXEN 0x00000002 /* Frame transmission is enabled */
-#define MACCFG1_TX_EN 0x00000001 /* Tx enable */
-#define MACCFG1_RXTX_EN (MACCFG1_RX_EN | MACCFG1_TX_EN)
-
-/* MACCFG2 - MAC configuration 2 register */
-#define MACCFG2_PRE_LEN_MASK 0x0000f000 /* preamble length */
-#define MACCFG2_PRE_LEN(x) ((x << 12) & MACCFG2_PRE_LEN_MASK)
-#define MACCFG2_IF_MODE_MASK 0x00000300
-#define MACCFG2_IF_MODE_NIBBLE 0x00000100 /* MII, 10/100 Mbps MII/RMII */
-#define MACCFG2_IF_MODE_BYTE 0x00000200 /* GMII/TBI, 1000 GMII/TBI */
-#define MACCFG2_PRE_RX_EN 0x00000080 /* receive preamble enable */
-#define MACCFG2_PRE_TX_EN 0x00000040 /* tx preable enable */
-#define MACCFG2_HUGE_FRAME 0x00000020 /* >= max frame len enable */
-#define MACCFG2_LEN_CHECK 0x00000010 /* MAC check frame's length Rx */
-#define MACCFG2_MAG_EN 0x00000008 /* magic packet enable */
-#define MACCFG2_PAD_CRC 0x00000004 /* pad and append CRC */
-#define MACCFG2_CRC_EN 0x00000002 /* MAC appends a CRC on all frames */
-#define MACCFG2_FULL_DUPLEX 0x00000001 /* Full deplex mode */
-
-struct fsl_enet_mac;
-
-void init_dtsec(struct fsl_enet_mac *mac, void *base, void *phyregs,
- int max_rx_len);
-
-#endif
diff --git a/arch/powerpc/include/asm/fsl_fman.h b/arch/powerpc/include/asm/fsl_fman.h
deleted file mode 100644
index 4d04415..0000000
--- a/arch/powerpc/include/asm/fsl_fman.h
+++ /dev/null
@@ -1,463 +0,0 @@
-/*
- * MPC85xx Internal Memory Map
- *
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __FSL_FMAN_H__
-#define __FSL_FMAN_H__
-
-#include <asm/types.h>
-
-typedef struct fm_bmi_common {
- u32 fmbm_init; /* BMI initialization */
- u32 fmbm_cfg1; /* BMI configuration1 */
- u32 fmbm_cfg2; /* BMI configuration2 */
- u32 res0[0x5];
- u32 fmbm_ievr; /* interrupt event register */
- u32 fmbm_ier; /* interrupt enable register */
- u32 fmbm_ifr; /* interrupt force register */
- u32 res1[0x5];
- u32 fmbm_arb[0x8]; /* BMI arbitration */
- u32 res2[0x28];
- u32 fmbm_gde; /* global debug enable */
- u32 fmbm_pp[0x3f]; /* BMI port parameters */
- u32 res3;
- u32 fmbm_pfs[0x3f]; /* BMI port FIFO size */
- u32 res4;
- u32 fmbm_ppid[0x3f];/* port partition ID */
-} fm_bmi_common_t;
-
-typedef struct fm_qmi_common {
- u32 fmqm_gc; /* general configuration register */
- u32 res0;
- u32 fmqm_eie; /* error interrupt event register */
- u32 fmqm_eien; /* error interrupt enable register */
- u32 fmqm_eif; /* error interrupt force register */
- u32 fmqm_ie; /* interrupt event register */
- u32 fmqm_ien; /* interrupt enable register */
- u32 fmqm_if; /* interrupt force register */
- u32 fmqm_gs; /* global status register */
- u32 fmqm_ts; /* task status register */
- u32 fmqm_etfc; /* enqueue total frame counter */
- u32 fmqm_dtfc; /* dequeue total frame counter */
- u32 fmqm_dc0; /* dequeue counter 0 */
- u32 fmqm_dc1; /* dequeue counter 1 */
- u32 fmqm_dc2; /* dequeue counter 2 */
- u32 fmqm_dc3; /* dequeue counter 3 */
- u32 fmqm_dfnoc; /* dequeue FQID not override counter */
- u32 fmqm_dfcc; /* dequeue FQID from context counter */
- u32 fmqm_dffc; /* dequeue FQID from FD counter */
- u32 fmqm_dcc; /* dequeue confirm counter */
- u32 res1[0xc];
- u32 fmqm_dtrc; /* debug trap configuration register */
- u32 fmqm_efddd; /* enqueue frame descriptor dynamic debug */
- u32 res3[0x2];
- u32 res4[0xdc]; /* missing debug regs */
-} fm_qmi_common_t;
-
-typedef struct fm_bmi {
- u8 res[1024];
-} fm_bmi_t;
-
-typedef struct fm_qmi {
- u8 res[1024];
-} fm_qmi_t;
-
-struct fm_bmi_rx_port {
- u32 fmbm_rcfg; /* Rx configuration */
- u32 fmbm_rst; /* Rx status */
- u32 fmbm_rda; /* Rx DMA attributes */
- u32 fmbm_rfp; /* Rx FIFO parameters */
- u32 fmbm_rfed; /* Rx frame end data */
- u32 fmbm_ricp; /* Rx internal context parameters */
- u32 fmbm_rim; /* Rx internal margins */
- u32 fmbm_rebm; /* Rx external buffer margins */
- u32 fmbm_rfne; /* Rx frame next engine */
- u32 fmbm_rfca; /* Rx frame command attributes */
- u32 fmbm_rfpne; /* Rx frame parser next engine */
- u32 fmbm_rpso; /* Rx parse start offset */
- u32 fmbm_rpp; /* Rx policer profile */
- u32 fmbm_rccb; /* Rx coarse classification base */
- u32 res1[0x2];
- u32 fmbm_rprai[0x8]; /* Rx parse results array Initialization */
- u32 fmbm_rfqid; /* Rx frame queue ID */
- u32 fmbm_refqid; /* Rx error frame queue ID */
- u32 fmbm_rfsdm; /* Rx frame status discard mask */
- u32 fmbm_rfsem; /* Rx frame status error mask */
- u32 fmbm_rfene; /* Rx frame enqueue next engine */
- u32 res2[0x23];
- u32 fmbm_ebmpi[0x8]; /* buffer manager pool information */
- u32 fmbm_acnt[0x8]; /* allocate counter */
- u32 res3[0x8];
- u32 fmbm_cgm[0x8]; /* congestion group map */
- u32 fmbm_mpd; /* BMan pool depletion */
- u32 res4[0x1F];
- u32 fmbm_rstc; /* Rx statistics counters */
- u32 fmbm_rfrc; /* Rx frame counters */
- u32 fmbm_rfbc; /* Rx bad frames counter */
- u32 fmbm_rlfc; /* Rx large frames counter */
- u32 fmbm_rffc; /* Rx filter frames counter */
- u32 fmbm_rfdc; /* Rx frame discard counter */
- u32 fmbm_rfldec; /* Rx frames list DMA error counter */
- u32 fmbm_rodc; /* Rx out of buffers discard counter */
- u32 fmbm_rbdc; /* Rx buffers deallocate counter */
- u32 res5[0x17];
- u32 fmbm_rpc; /* Rx performance counters */
- u32 fmbm_rpcp; /* Rx performance count parameters */
- u32 fmbm_rccn; /* Rx cycle counter */
- u32 fmbm_rtuc; /* Rx tasks utilization counter */
- u32 fmbm_rrquc; /* Rx receive queue utilization counter */
- u32 fmbm_rduc; /* Rx DMA utilization counter */
- u32 fmbm_rfuc; /* Rx FIFO utilization counter */
- u32 fmbm_rpac; /* Rx pause activation counter */
- u32 res6[0x18];
- u32 fmbm_rdbg; /* Rx debug configuration */
-};
-
-/* FMBM_RCFG - Rx configuration */
-#define FMBM_RCFG_EN 0x80000000 /* port is enabled to receive data */
-#define FMBM_RCFG_FDOVR 0x02000000 /* frame discard override */
-#define FMBM_RCFG_IM 0x01000000 /* independent mode */
-
-/* FMBM_RST - Rx status */
-#define FMBM_RST_BSY 0x80000000 /* Rx port is busy */
-
-/* FMBM_RFCA - Rx frame command attributes */
-#define FMBM_RFCA_ORDER 0x80000000
-#define FMBM_RFCA_MR_MASK 0x003f0000
-#define FMBM_RFCA_MR(x) ((x << 16) & FMBM_RFCA_MR_MASK)
-
-/* FMBM_RSTC - Rx statistics */
-#define FMBM_RSTC_EN 0x80000000 /* statistics counters enable */
-
-struct fm_bmi_tx_port {
- u32 fmbm_tcfg; /* Tx configuration */
- u32 fmbm_tst; /* Tx status */
- u32 fmbm_tda; /* Tx DMA attributes */
- u32 fmbm_tfp; /* Tx FIFO parameters */
- u32 fmbm_tfed; /* Tx frame end data */
- u32 fmbm_ticp; /* Tx internal context parameters */
- u32 fmbm_tfne; /* Tx frame next engine */
- u32 fmbm_tfca; /* Tx frame command attributes */
- u32 fmbm_tcfqid;/* Tx confirmation frame queue ID */
- u32 fmbm_tfeqid;/* Tx error frame queue ID */
- u32 fmbm_tfene; /* Tx frame enqueue next engine */
- u32 fmbm_trlmts;/* Tx rate limiter scale */
- u32 fmbm_trlmt; /* Tx rate limiter */
- u32 res0[0x73];
- u32 fmbm_tstc; /* Tx statistics counters */
- u32 fmbm_tfrc; /* Tx frame counter */
- u32 fmbm_tfdc; /* Tx frames discard counter */
- u32 fmbm_tfledc;/* Tx frame length error discard counter */
- u32 fmbm_tfufdc;/* Tx frame unsupported format discard counter */
- u32 fmbm_tbdc; /* Tx buffers deallocate counter */
- u32 res1[0x1a];
- u32 fmbm_tpc; /* Tx performance counters */
- u32 fmbm_tpcp; /* Tx performance count parameters */
- u32 fmbm_tccn; /* Tx cycle counter */
- u32 fmbm_ttuc; /* Tx tasks utilization counter */
- u32 fmbm_ttcquc;/* Tx transmit confirm queue utilization counter */
- u32 fmbm_tduc; /* Tx DMA utilization counter */
- u32 fmbm_tfuc; /* Tx FIFO utilization counter */
- u32 res2[0x19];
- u32 fmbm_tdcfg; /* Tx debug configuration */
-};
-
-/* FMBM_TCFG - Tx configuration */
-#define FMBM_TCFG_EN 0x80000000 /* port is enabled to transmit data */
-#define FMBM_TCFG_IM 0x01000000 /* independent mode enable */
-
-/* FMBM_TST - Tx status */
-#define FMBM_TST_BSY 0x80000000 /* Tx port is busy */
-
-/* FMBM_TFCA - Tx frame command attributes */
-#define FMBM_TFCA_ORDER 0x80000000
-#define FMBM_TFCA_MR_MASK 0x003f0000
-#define FMBM_TFCA_MR(x) ((x << 16) & FMBM_TFCA_MR_MASK)
-
-/* FMBM_TSTC - Tx statistics counters */
-#define FMBM_TSTC_EN 0x80000000
-
-/* FMBM_INIT - BMI initialization register */
-#define FMBM_INIT_START 0x80000000 /* init internal buffers */
-
-/* FMBM_CFG1 - BMI configuration 1 */
-#define FMBM_CFG1_FBPS_MASK 0x03ff0000 /* Free buffer pool size */
-#define FMBM_CFG1_FBPS_SHIFT 16
-#define FMBM_CFG1_FBPO_MASK 0x000003ff /* Free buffer pool offset */
-
-/* FMBM_IEVR - interrupt event */
-#define FMBM_IEVR_PEC 0x80000000 /* pipeline table ECC err detected */
-#define FMBM_IEVR_LEC 0x40000000 /* linked list RAM ECC error */
-#define FMBM_IEVR_SEC 0x20000000 /* statistics count RAM ECC error */
-#define FMBM_IEVR_CLEAR_ALL (FMBM_IEVR_PEC | FMBM_IEVR_LEC | FMBM_IEVR_SEC)
-
-/* FMBM_IER - interrupt enable */
-#define FMBM_IER_PECE 0x80000000 /* PEC interrupt enable */
-#define FMBM_IER_LECE 0x40000000 /* LEC interrupt enable */
-#define FMBM_IER_SECE 0x20000000 /* SEC interrupt enable */
-
-#define FMBM_IER_DISABLE_ALL 0x00000000
-
-/* FMBM_PP - BMI Port Parameters */
-#define FMBM_PP_MXT_MASK 0x3f000000 /* Max # tasks */
-#define FMBM_PP_MXT(x) (((x-1) << 24) & FMBM_PP_MXT_MASK)
-#define FMBM_PP_MXD_MASK 0x00000f00 /* Max DMA */
-#define FMBM_PP_MXD(x) (((x-1) << 8) & FMBM_PP_MXD_MASK)
-
-/* FMBM_PFS - BMI Port FIFO Size */
-#define FMBM_PFS_IFSZ_MASK 0x000003ff /* Internal Fifo Size */
-#define FMBM_PFS_IFSZ(x) (x & FMBM_PFS_IFSZ_MASK)
-
-/* FMQM_GC - global configuration */
-#define FMQM_GC_ENQ_EN 0x80000000 /* enqueue enable */
-#define FMQM_GC_DEQ_EN 0x40000000 /* dequeue enable */
-#define FMQM_GC_STEN 0x10000000 /* enable global stat counters */
-#define FMQM_GC_ENQ_THR_MASK 0x00003f00 /* max number of enqueue Tnum */
-#define FMQM_GC_ENQ(x) ((x << 8) & FMQM_GC_ENQ_THR_MAS)
-#define FMQM_GC_DEQ_THR_MASK 0x0000003f /* max number of dequeue Tnum */
-#define FMQM_GC_DEQ(x) (x & FMQM_GC_DEQ_THR_MASK)
-
-/* FMQM_EIE - error interrupt event register */
-#define FMQM_EIE_DEE 0x80000000 /* double-bit ECC error */
-#define FMQM_EIE_DFUPE 0x40000000 /* dequeue from unknown PortID */
-#define FMQM_EIE_CLEAR_ALL (FMQM_EIE_DEE | FMQM_EIE_DFUPE)
-
-/* FMQM_EIEN - error interrupt enable register */
-#define FMQM_EIEN_DEEN 0x80000000 /* double-bit ECC error */
-#define FMQM_EIEN_DFUPEN 0x40000000 /* dequeue from unknown PortID */
-#define FMQM_EIEN_DISABLE_ALL 0x00000000
-
-/* FMQM_IE - interrupt event register */
-#define FMQM_IE_SEE 0x80000000 /* single-bit ECC error detected */
-#define FMQM_IE_CLEAR_ALL FMQM_IE_SEE
-
-/* FMQM_IEN - interrupt enable register */
-#define FMQM_IEN_SEE 0x80000000 /* single-bit ECC err IRQ enable */
-#define FMQM_IEN_DISABLE_ALL 0x00000000
-
-/* NIA - next invoked action */
-#define NIA_ENG_RISC 0x00000000
-#define NIA_ENG_MASK 0x007c0000
-
-/* action code */
-#define NIA_RISC_AC_CC 0x00000006
-#define NIA_RISC_AC_IM_TX 0x00000008 /* independent mode Tx */
-#define NIA_RISC_AC_IM_RX 0x0000000a /* independent mode Rx */
-#define NIA_RISC_AC_HC 0x0000000c
-
-typedef struct fm_parser {
- u8 res[1024];
-} fm_parser_t;
-
-typedef struct fm_policer {
- u8 res[4*1024];
-} fm_policer_t;
-
-typedef struct fm_keygen {
- u8 res[4*1024];
-} fm_keygen_t;
-
-typedef struct fm_dma {
- u32 fmdmsr; /* status register */
- u32 fmdmmr; /* mode register */
- u32 fmdmtr; /* bus threshold register */
- u32 fmdmhy; /* bus hysteresis register */
- u32 fmdmsetr; /* SOS emergency threshold register */
- u32 fmdmtah; /* transfer bus address high register */
- u32 fmdmtal; /* transfer bus address low register */
- u32 fmdmtcid; /* transfer bus communication ID register */
- u32 fmdmra; /* DMA bus internal ram address register */
- u32 fmdmrd; /* DMA bus internal ram data register */
- u32 res0[0xb];
- u32 fmdmdcr; /* debug counter */
- u32 fmdmemsr; /* emrgency smoother register */
- u32 res1;
- u32 fmdmplr[32]; /* FM DMA PID-LIODN # register */
- u32 res[0x3c8];
-} fm_dma_t;
-
-/* FMDMSR - Fman DMA status register */
-#define FMDMSR_CMDQNE 0x10000000 /* command queue not empty */
-#define FMDMSR_BER 0x08000000 /* bus err event occurred on bus */
-#define FMDMSR_RDB_ECC 0x04000000 /* read buffer ECC error */
-#define FMDMSR_WRB_SECC 0x02000000 /* write buf ECC err sys side */
-#define FMDMSR_WRB_FECC 0x01000000 /* write buf ECC err Fman side */
-#define FMDMSR_DPEXT_SECC 0x00800000 /* DP external ECC err sys side */
-#define FMDMSR_DPEXT_FECC 0x00400000 /* DP external ECC err Fman side */
-#define FMDMSR_DPDAT_SECC 0x00200000 /* DP data ECC err on sys side */
-#define FMDMSR_DPDAT_FECC 0x00100000 /* DP data ECC err on Fman side */
-#define FMDMSR_SPDAT_FECC 0x00080000 /* SP data ECC error Fman side */
-
-#define FMDMSR_CLEAR_ALL (FMDMSR_BER | FMDMSR_RDB_ECC \
- | FMDMSR_WRB_SECC | FMDMSR_WRB_FECC \
- | FMDMSR_DPEXT_SECC | FMDMSR_DPEXT_FECC \
- | FMDMSR_DPDAT_SECC | FMDMSR_DPDAT_FECC \
- | FMDMSR_SPDAT_FECC)
-
-/* FMDMMR - FMan DMA mode register */
-#define FMDMMR_SBER 0x10000000 /* stop the DMA if a bus error */
-
-typedef struct fm_fpm {
- u32 fpmtnc; /* TNUM control */
- u32 fpmprc; /* Port_ID control */
- u32 res0;
- u32 fpmflc; /* flush control */
- u32 fpmdis1; /* dispatch thresholds1 */
- u32 fpmdis2; /* dispatch thresholds2 */
- u32 fmepi; /* error pending interrupts */
- u32 fmrie; /* rams interrupt enable */
- u32 fpmfcevent[0x4];/* FMan controller event 0-3 */
- u32 res1[0x4];
- u32 fpmfcmask[0x4]; /* FMan controller mask 0-3 */
- u32 res2[0x4];
- u32 fpmtsc1; /* timestamp control1 */
- u32 fpmtsc2; /* timestamp control2 */
- u32 fpmtsp; /* time stamp */
- u32 fpmtsf; /* time stamp fraction */
- u32 fpmrcr; /* rams control and event */
- u32 res3[0x3];
- u32 fpmdrd[0x4]; /* data_ram data 0-3 */
- u32 res4[0xc];
- u32 fpmdra; /* data ram access */
- u32 fm_ip_rev_1; /* IP block revision 1 */
- u32 fm_ip_rev_2; /* IP block revision 2 */
- u32 fmrstc; /* reset command */
- u32 fmcld; /* classifier debug control */
- u32 fmnpi; /* normal pending interrupts */
- u32 res5;
- u32 fmfpee; /* event and enable */
- u32 fpmcev[0x4]; /* CPU event 0-3 */
- u32 res6[0x4];
- u32 fmfp_ps[0x40]; /* port status */
- u32 res7[0x260];
- u32 fpmts[0x80]; /* task status */
- u32 res8[0xa0];
-} fm_fpm_t;
-
-/* FMFP_PRC - FPM Port_ID Control Register */
-#define FMFPPRC_PORTID_MASK 0x3f000000
-#define FMFPPRC_PORTID_SHIFT 24
-#define FMFPPRC_ORA_SHIFT 16
-#define FMFPPRC_RISC1 0x00000001
-#define FMFPPRC_RISC2 0x00000002
-#define FMFPPRC_RISC_ALL (FMFPPRC_RISC1 | FMFPPRC_RSIC2)
-
-/* FPM Flush Control Register */
-#define FMFP_FLC_DISP_LIM_NONE 0x00000000 /* no dispatch limitation */
-
-/* FMFP_EE - FPM event and enable register */
-#define FMFPEE_DECC 0x80000000 /* double ECC err on FPM ram */
-#define FMFPEE_STL 0x40000000 /* stall of task ... */
-#define FMFPEE_SECC 0x20000000 /* single ECC error */
-#define FMFPEE_RFM 0x00010000 /* release FMan */
-#define FMFPEE_DECC_EN 0x00008000 /* double ECC interrupt enable */
-#define FMFPEE_STL_EN 0x00004000 /* stall of task interrupt enable */
-#define FMFPEE_SECC_EN 0x00002000 /* single ECC err interrupt enable */
-#define FMFPEE_EHM 0x00000008 /* external halt enable */
-#define FMFPEE_UEC 0x00000004 /* FMan is not halted */
-#define FMFPEE_CER 0x00000002 /* only errornous task stalled */
-#define FMFPEE_DER 0x00000001 /* DMA error is just reported */
-
-#define FMFPEE_CLEAR_EVENT (FMFPEE_DECC | FMFPEE_STL | FMFPEE_SECC | \
- FMFPEE_EHM | FMFPEE_UEC | FMFPEE_CER | \
- FMFPEE_DER | FMFPEE_RFM)
-
-/* FMFP_RCR - FMan Rams Control and Event */
-#define FMFP_RCR_MDEC 0x00008000 /* double ECC error in muram */
-#define FMFP_RCR_IDEC 0x00004000 /* double ECC error in iram */
-
-typedef struct fm_imem {
- u32 iadd; /* instruction address register */
- u32 idata; /* instruction data register */
- u32 itcfg; /* timing config register */
- u32 iready; /* ready register */
- u8 res[0xff0];
-} fm_imem_t;
-#define IRAM_IADD_AIE 0x80000000 /* address auto increase enable */
-#define IRAM_READY 0x80000000 /* ready to use */
-
-typedef struct fm_soft_parser {
- u8 res[4*1024];
-} fm_soft_parser_t;
-
-typedef struct fm_dtesc {
- u8 res[4*1024];
-} fm_dtsec_t;
-
-typedef struct fm_mdio {
- u8 res0[0x120];
- u32 miimcfg; /* MII management configuration reg */
- u32 miimcom; /* MII management command reg */
- u32 miimadd; /* MII management address reg */
- u32 miimcon; /* MII management control reg */
- u32 miimstat; /* MII management status reg */
- u32 miimind; /* MII management indication reg */
- u8 res1[0x1000 - 0x138];
-} fm_mdio_t;
-
-typedef struct fm_10gec {
- u8 res[4*1024];
-} fm_10gec_t;
-
-typedef struct fm_10gec_mdio {
- u8 res[4*1024];
-} fm_10gec_mdio_t;
-
-typedef struct fm_memac {
- u8 res[4*1024];
-} fm_memac_t;
-
-typedef struct fm_memac_mdio {
- u8 res[4*1024];
-} fm_memac_mdio_t;
-
-typedef struct fm_1588 {
- u8 res[4*1024];
-} fm_1588_t;
-
-typedef struct ccsr_fman {
- u8 muram[0x80000];
- fm_bmi_common_t fm_bmi_common;
- fm_qmi_common_t fm_qmi_common;
- u8 res0[2048];
- struct {
- fm_bmi_t fm_bmi;
- fm_qmi_t fm_qmi;
- fm_parser_t fm_parser;
- u8 res[1024];
- } port[63];
- fm_policer_t fm_policer;
- fm_keygen_t fm_keygen;
- fm_dma_t fm_dma;
- fm_fpm_t fm_fpm;
- fm_imem_t fm_imem;
- u8 res1[8*1024];
- fm_soft_parser_t fm_soft_parser;
- u8 res2[96*1024];
-#ifdef CONFIG_SYS_FMAN_V3
- struct {
- fm_memac_t fm_memac;
- fm_memac_mdio_t fm_memac_mdio;
- } memac[10];
- u8 res4[32*1024];
- fm_memac_mdio_t fm_dedicated_mdio[2];
-#else
- struct {
- fm_dtsec_t fm_dtesc;
- fm_mdio_t fm_mdio;
- } mac_1g[8]; /* support up to 8 1g controllers */
- struct {
- fm_10gec_t fm_10gec;
- fm_10gec_mdio_t fm_10gec_mdio;
- } mac_10g[1];
- u8 res4[48*1024];
-#endif
- fm_1588_t fm_1588;
- u8 res5[4*1024];
-} ccsr_fman_t;
-
-#endif /*__FSL_FMAN_H__*/
diff --git a/arch/powerpc/include/asm/fsl_tgec.h b/arch/powerpc/include/asm/fsl_tgec.h
deleted file mode 100644
index 92fb777..0000000
--- a/arch/powerpc/include/asm/fsl_tgec.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- * Dave Liu <daveliu@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __TGEC_H__
-#define __TGEC_H__
-
-#include <phy.h>
-
-struct tgec {
- /* 10GEC general control and status registers */
- u32 tgec_id; /* Controller ID register */
- u32 res0;
- u32 command_config; /* Control and configuration register */
- u32 mac_addr_0; /* Lower 32 bits of 48-bit MAC address */
- u32 mac_addr_1; /* Upper 16 bits of 48-bit MAC address */
- u32 maxfrm; /* Maximum frame length register */
- u32 pause_quant; /* Pause quanta register */
- u32 res1[4];
- u32 hashtable_ctrl; /* Hash table control register */
- u32 res2[4];
- u32 status; /* MAC status register */
- u32 tx_ipg_length; /* Transmitter inter-packet-gap register */
- u32 mac_addr_2; /* Lower 32 bits of the 2nd 48-bit MAC addr */
- u32 mac_addr_3; /* Upper 16 bits of the 2nd 48-bit MAC addr */
- u32 res3[4];
- u32 imask; /* Interrupt mask register */
- u32 ievent; /* Interrupt event register */
- u32 res4[6];
- /* 10GEC statistics counter registers */
- u32 tx_frame_u; /* Tx frame counter upper */
- u32 tx_frame_l; /* Tx frame counter lower */
- u32 rx_frame_u; /* Rx frame counter upper */
- u32 rx_frame_l; /* Rx frame counter lower */
- u32 rx_frame_crc_err_u; /* Rx frame check sequence error upper */
- u32 rx_frame_crc_err_l; /* Rx frame check sequence error lower */
- u32 rx_align_err_u; /* Rx alignment error upper */
- u32 rx_align_err_l; /* Rx alignment error lower */
- u32 tx_pause_frame_u; /* Tx valid pause frame upper */
- u32 tx_pause_frame_l; /* Tx valid pause frame lower */
- u32 rx_pause_frame_u; /* Rx valid pause frame upper */
- u32 rx_pause_frame_l; /* Rx valid pause frame upper */
- u32 rx_long_err_u; /* Rx too long frame error upper */
- u32 rx_long_err_l; /* Rx too long frame error lower */
- u32 rx_frame_err_u; /* Rx frame length error upper */
- u32 rx_frame_err_l; /* Rx frame length error lower */
- u32 tx_vlan_u; /* Tx VLAN frame upper */
- u32 tx_vlan_l; /* Tx VLAN frame lower */
- u32 rx_vlan_u; /* Rx VLAN frame upper */
- u32 rx_vlan_l; /* Rx VLAN frame lower */
- u32 tx_oct_u; /* Tx octets upper */
- u32 tx_oct_l; /* Tx octets lower */
- u32 rx_oct_u; /* Rx octets upper */
- u32 rx_oct_l; /* Rx octets lower */
- u32 rx_uni_u; /* Rx unicast frame upper */
- u32 rx_uni_l; /* Rx unicast frame lower */
- u32 rx_multi_u; /* Rx multicast frame upper */
- u32 rx_multi_l; /* Rx multicast frame lower */
- u32 rx_brd_u; /* Rx broadcast frame upper */
- u32 rx_brd_l; /* Rx broadcast frame lower */
- u32 tx_frame_err_u; /* Tx frame error upper */
- u32 tx_frame_err_l; /* Tx frame error lower */
- u32 tx_uni_u; /* Tx unicast frame upper */
- u32 tx_uni_l; /* Tx unicast frame lower */
- u32 tx_multi_u; /* Tx multicast frame upper */
- u32 tx_multi_l; /* Tx multicast frame lower */
- u32 tx_brd_u; /* Tx broadcast frame upper */
- u32 tx_brd_l; /* Tx broadcast frame lower */
- u32 rx_drop_u; /* Rx dropped packets upper */
- u32 rx_drop_l; /* Rx dropped packets lower */
- u32 rx_eoct_u; /* Rx ethernet octets upper */
- u32 rx_eoct_l; /* Rx ethernet octets lower */
- u32 rx_pkt_u; /* Rx packets upper */
- u32 rx_pkt_l; /* Rx packets lower */
- u32 tx_undsz_u; /* Undersized packet upper */
- u32 tx_undsz_l; /* Undersized packet lower */
- u32 rx_64_u; /* Rx 64 oct packet upper */
- u32 rx_64_l; /* Rx 64 oct packet lower */
- u32 rx_127_u; /* Rx 65 to 127 oct packet upper */
- u32 rx_127_l; /* Rx 65 to 127 oct packet lower */
- u32 rx_255_u; /* Rx 128 to 255 oct packet upper */
- u32 rx_255_l; /* Rx 128 to 255 oct packet lower */
- u32 rx_511_u; /* Rx 256 to 511 oct packet upper */
- u32 rx_511_l; /* Rx 256 to 511 oct packet lower */
- u32 rx_1023_u; /* Rx 512 to 1023 oct packet upper */
- u32 rx_1023_l; /* Rx 512 to 1023 oct packet lower */
- u32 rx_1518_u; /* Rx 1024 to 1518 oct packet upper */
- u32 rx_1518_l; /* Rx 1024 to 1518 oct packet lower */
- u32 rx_1519_u; /* Rx 1519 to max oct packet upper */
- u32 rx_1519_l; /* Rx 1519 to max oct packet lower */
- u32 tx_oversz_u; /* oversized packet upper */
- u32 tx_oversz_l; /* oversized packet lower */
- u32 tx_jabber_u; /* Jabber packet upper */
- u32 tx_jabber_l; /* Jabber packet lower */
- u32 tx_frag_u; /* Fragment packet upper */
- u32 tx_frag_l; /* Fragment packet lower */
- u32 rx_err_u; /* Rx frame error upper */
- u32 rx_err_l; /* Rx frame error lower */
- u32 res5[0x39a];
-};
-
-/* EC10G_ID - 10-gigabit ethernet MAC controller ID */
-#define EC10G_ID_VER_MASK 0x0000ff00
-#define EC10G_ID_VER_SHIFT 8
-#define EC10G_ID_REV_MASK 0x000000ff
-
-/* COMMAND_CONFIG - command and configuration register */
-#define TGEC_CMD_CFG_EN_TIMESTAMP 0x00100000 /* enable IEEE1588 */
-#define TGEC_CMD_CFG_TX_ADDR_INS_SEL 0x00080000 /* Tx mac addr w/ second */
-#define TGEC_CMD_CFG_NO_LEN_CHK 0x00020000 /* payload len chk disable */
-#define TGEC_CMD_CFG_SEND_IDLE 0x00010000 /* send XGMII idle seqs */
-#define TGEC_CMD_CFG_RX_ER_DISC 0x00004000 /* Rx err frm discard enb */
-#define TGEC_CMD_CFG_CMD_FRM_EN 0x00002000 /* CMD frame RX enable */
-#define TGEC_CMD_CFG_STAT_CLR 0x00001000 /* clear stats */
-#define TGEC_CMD_CFG_TX_ADDR_INS 0x00000200 /* overwrite src MAC addr */
-#define TGEC_CMD_CFG_PAUSE_IGNORE 0x00000100 /* ignore pause frames */
-#define TGEC_CMD_CFG_PAUSE_FWD 0x00000080 /* fwd pause frames */
-#define TGEC_CMD_CFG_CRC_FWD 0x00000040 /* fwd Rx CRC frames */
-#define TGEC_CMD_CFG_PAD_EN 0x00000020 /* MAC remove Rx padding */
-#define TGEC_CMD_CFG_PROM_EN 0x00000010 /* promiscuous mode enable */
-#define TGEC_CMD_CFG_WAN_MODE 0x00000008 /* WAN mode enable */
-#define TGEC_CMD_CFG_RX_EN 0x00000002 /* MAC Rx path enable */
-#define TGEC_CMD_CFG_TX_EN 0x00000001 /* MAC Tx path enable */
-#define TGEC_CMD_CFG_RXTX_EN (TGEC_CMD_CFG_RX_EN | TGEC_CMD_CFG_TX_EN)
-
-/* HASHTABLE_CTRL - Hashtable control register */
-#define HASHTABLE_CTRL_MCAST_EN 0x00000200 /* enable mulitcast Rx hash */
-#define HASHTABLE_CTRL_ADDR_MASK 0x000001ff
-
-/* TX_IPG_LENGTH - Transmit inter-packet gap length register */
-#define TX_IPG_LENGTH_IPG_LEN_MASK 0x000003ff
-
-/* IMASK - interrupt mask register */
-#define IMASK_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event mask */
-#define IMASK_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion mask */
-#define IMASK_REM_FAULT 0x00004000 /* remote fault mask */
-#define IMASK_LOC_FAULT 0x00002000 /* local fault mask */
-#define IMASK_TX_ECC_ER 0x00001000 /* Tx frame ECC error mask */
-#define IMASK_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow mask */
-#define IMASK_TX_ER 0x00000200 /* Tx frame error mask */
-#define IMASK_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow mask */
-#define IMASK_RX_ECC_ER 0x00000080 /* Rx frame ECC error mask */
-#define IMASK_RX_JAB_FRM 0x00000040 /* Rx jabber frame mask */
-#define IMASK_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame mask */
-#define IMASK_RX_RUNT_FRM 0x00000010 /* Rx runt frame mask */
-#define IMASK_RX_FRAG_FRM 0x00000008 /* Rx fragment frame mask */
-#define IMASK_RX_LEN_ER 0x00000004 /* Rx payload length error mask */
-#define IMASK_RX_CRC_ER 0x00000002 /* Rx CRC error mask */
-#define IMASK_RX_ALIGN_ER 0x00000001 /* Rx alignment error mask */
-
-#define IMASK_MASK_ALL 0x00000000
-
-/* IEVENT - interrupt event register */
-#define IEVENT_MDIO_SCAN_EVENT 0x00010000 /* MDIO scan event */
-#define IEVENT_MDIO_CMD_CMPL 0x00008000 /* MDIO cmd completion */
-#define IEVENT_REM_FAULT 0x00004000 /* remote fault */
-#define IEVENT_LOC_FAULT 0x00002000 /* local fault */
-#define IEVENT_TX_ECC_ER 0x00001000 /* Tx frame ECC error */
-#define IEVENT_TX_FIFO_UNFL 0x00000800 /* Tx FIFO underflow */
-#define IEVENT_TX_ER 0x00000200 /* Tx frame error */
-#define IEVENT_RX_FIFO_OVFL 0x00000100 /* Rx FIFO overflow */
-#define IEVENT_RX_ECC_ER 0x00000080 /* Rx frame ECC error */
-#define IEVENT_RX_JAB_FRM 0x00000040 /* Rx jabber frame */
-#define IEVENT_RX_OVRSZ_FRM 0x00000020 /* Rx oversized frame */
-#define IEVENT_RX_RUNT_FRM 0x00000010 /* Rx runt frame */
-#define IEVENT_RX_FRAG_FRM 0x00000008 /* Rx fragment frame */
-#define IEVENT_RX_LEN_ER 0x00000004 /* Rx payload length error */
-#define IEVENT_RX_CRC_ER 0x00000002 /* Rx CRC error */
-#define IEVENT_RX_ALIGN_ER 0x00000001 /* Rx alignment error */
-
-#define IEVENT_CLEAR_ALL 0xffffffff
-
-struct tgec_mdio_controller {
- u32 res0[0xc];
- u32 mdio_stat; /* MDIO configuration and status */
- u32 mdio_ctl; /* MDIO control */
- u32 mdio_data; /* MDIO data */
- u32 mdio_addr; /* MDIO address */
-};
-
-#define MDIO_STAT_CLKDIV(x) (((x>>1) & 0xff) << 8)
-#define MDIO_STAT_BSY (1 << 0)
-#define MDIO_STAT_RD_ER (1 << 1)
-#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
-#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
-#define MDIO_CTL_PRE_DIS (1 << 10)
-#define MDIO_CTL_SCAN_EN (1 << 11)
-#define MDIO_CTL_POST_INC (1 << 14)
-#define MDIO_CTL_READ (1 << 15)
-
-#define MDIO_DATA(x) (x & 0xffff)
-#define MDIO_DATA_BSY (1 << 31)
-
-struct fsl_enet_mac;
-
-void init_tgec(struct fsl_enet_mac *mac, void *base, void *phyregs,
- int max_rx_len);
-
-#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 0c9d85e..101b8db 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -19,7 +19,7 @@
#include <fsl_sec.h>
#include <fsl_sfp.h>
#include <asm/fsl_lbc.h>
-#include <asm/fsl_fman.h>
+#include <fsl_fman.h>
#include <fsl_immap.h>
typedef struct ccsr_local {