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-rw-r--r--arch/arm/config.mk3
-rw-r--r--arch/arm/cpu/armv8/Kconfig41
-rw-r--r--arch/arm/cpu/armv8/Makefile1
-rw-r--r--arch/arm/cpu/armv8/cpu-dt.c11
-rw-r--r--arch/arm/cpu/armv8/cpu.c22
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/Kconfig21
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/Makefile1
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/cpu.c3
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/fdt.c3
-rw-r--r--arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S20
-rw-r--r--arch/arm/cpu/armv8/psci.S286
-rw-r--r--arch/arm/cpu/armv8/sec_firmware.c2
-rw-r--r--arch/arm/cpu/armv8/sec_firmware_asm.S2
-rw-r--r--arch/arm/cpu/armv8/u-boot.lds57
-rw-r--r--arch/arm/dts/fsl-ls1043a-qds.dtsi12
-rw-r--r--arch/arm/dts/fsl-ls1043a-rdb.dts8
-rw-r--r--arch/arm/include/asm/armv8/sec_firmware.h2
-rw-r--r--arch/arm/include/asm/macro.h8
-rw-r--r--arch/arm/include/asm/psci.h15
-rw-r--r--arch/arm/include/asm/secure.h2
-rw-r--r--arch/arm/include/asm/system.h11
-rw-r--r--arch/arm/lib/bootm-fdt.c3
-rw-r--r--arch/arm/lib/bootm.c3
-rw-r--r--arch/arm/lib/psci-dt.c5
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h5
25 files changed, 525 insertions, 22 deletions
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index 008da39..3a81f13 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -121,7 +121,8 @@ endif
# limit ourselves to the sections we want in the .bin.
ifdef CONFIG_ARM64
-OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn
+OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .data \
+ -j .u_boot_list -j .rela.dyn
else
OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \
-j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 965a8d1..22dce88 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -40,4 +40,45 @@ config PSCI_RESET
Select Y here to make use of PSCI calls for system reset
+config ARMV8_PSCI
+ bool "Enable PSCI support" if EXPERT
+ default n
+ help
+ PSCI is Power State Coordination Interface defined by ARM.
+ The PSCI in U-boot provides a general framework and each platform
+ can implement their own specific PSCI functions.
+ Say Y here to enable PSCI support on ARMv8 platform.
+
+config ARMV8_PSCI_NR_CPUS
+ int "Maximum supported CPUs for PSCI"
+ depends on ARMV8_PSCI
+ default 4
+ help
+ The maximum number of CPUs supported in the PSCI firmware.
+ It is no problem to set a larger value than the number of CPUs in
+ the actual hardware implementation.
+
+config ARMV8_PSCI_CPUS_PER_CLUSTER
+ int "Number of CPUs per cluster"
+ depends on ARMV8_PSCI
+ default 0
+ help
+ The number of CPUs per cluster, suppose each cluster has same number
+ of CPU cores, platforms with asymmetric clusters don't apply here.
+ A value 0 or no definition of it works for single cluster system.
+ System with multi-cluster should difine their own exact value.
+
+if SYS_HAS_ARMV8_SECURE_BASE
+
+config ARMV8_SECURE_BASE
+ hex "Secure address for PSCI image"
+ depends on ARMV8_PSCI
+ help
+ Address for placing the PSCI text, data and stack sections.
+ If not defined, the PSCI sections are placed together with the u-boot
+ but platform can choose to place PSCI code image separately in other
+ places such as some secure RAM built-in SOC etc.
+
+endif
+
endif
diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile
index dea1465..28ba786 100644
--- a/arch/arm/cpu/armv8/Makefile
+++ b/arch/arm/cpu/armv8/Makefile
@@ -25,3 +25,4 @@ obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/
obj-$(CONFIG_S32V234) += s32v234/
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
+obj-$(CONFIG_ARMV8_PSCI) += psci.o
diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c
index 9ffb49c..3a5afe8 100644
--- a/arch/arm/cpu/armv8/cpu-dt.c
+++ b/arch/arm/cpu/armv8/cpu-dt.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <asm/psci.h>
+#include <asm/system.h>
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#include <asm/armv8/sec_firmware.h>
#endif
@@ -13,7 +14,8 @@
int psci_update_dt(void *fdt)
{
#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_FSL_PPA_ARMV8_PSCI)
+
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
/*
* If the PSCI in SEC Firmware didn't work, avoid to update the
@@ -25,6 +27,13 @@ int psci_update_dt(void *fdt)
return 0;
#endif
fdt_psci(fdt);
+
+#if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_ARMV8_SECURE_BASE)
+ /* secure code lives in RAM, keep it alive */
+ fdt_add_mem_rsv(fdt, (unsigned long)__secure_start,
+ __secure_end - __secure_start);
+#endif
+
#endif
#endif
return 0;
diff --git a/arch/arm/cpu/armv8/cpu.c b/arch/arm/cpu/armv8/cpu.c
index e06c3cc..5dcb5e2 100644
--- a/arch/arm/cpu/armv8/cpu.c
+++ b/arch/arm/cpu/armv8/cpu.c
@@ -14,6 +14,7 @@
#include <common.h>
#include <command.h>
#include <asm/system.h>
+#include <asm/secure.h>
#include <linux/compiler.h>
int cleanup_before_linux(void)
@@ -41,3 +42,24 @@ int cleanup_before_linux(void)
return 0;
}
+
+#ifdef CONFIG_ARMV8_PSCI
+static void relocate_secure_section(void)
+{
+#ifdef CONFIG_ARMV8_SECURE_BASE
+ size_t sz = __secure_end - __secure_start;
+
+ memcpy((void *)CONFIG_ARMV8_SECURE_BASE, __secure_start, sz);
+ flush_dcache_range(CONFIG_ARMV8_SECURE_BASE,
+ CONFIG_ARMV8_SECURE_BASE + sz + 1);
+ invalidate_icache_all();
+#endif
+}
+
+void armv8_setup_psci(void)
+{
+ relocate_secure_section();
+ secure_ram_addr(psci_setup_vectors)();
+ secure_ram_addr(psci_arch_init)();
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 6772584..cc0dc88 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -44,6 +44,27 @@ config FSL_LSCH3
menu "Layerscape architecture"
depends on FSL_LSCH2 || FSL_LSCH3
+menu "Layerscape PPA"
+config FSL_LS_PPA
+ bool "FSL Layerscape PPA firmware support"
+ depends on !ARMV8_PSCI
+ depends on ARCH_LS1043A || ARCH_LS1046A
+ select FSL_PPA_ARMV8_PSCI
+ help
+ The FSL Primary Protected Application (PPA) is a software component
+ which is loaded during boot stage, and then remains resident in RAM
+ and runs in the TrustZone after boot.
+ Say y to enable it.
+
+config FSL_PPA_ARMV8_PSCI
+ bool "PSCI implementation in PPA firmware"
+ depends on FSL_LS_PPA
+ help
+ This config enables the ARMv8 PSCI implementation in PPA firmware.
+ This is a private PSCI implementation and different from those
+ implemented under the common ARMv8 PSCI framework.
+endmenu
+
config SYS_FSL_MMDC
bool
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 51c1cee..423b4b3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -28,6 +28,7 @@ endif
ifneq ($(CONFIG_LS1043A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
+obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
endif
ifneq ($(CONFIG_ARCH_LS1012A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index ffbbd72..467d9af 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -410,7 +410,8 @@ int arch_early_init_r(void)
erratum_a009942_check_cpo();
#endif
#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
+ defined(CONFIG_FSL_PPA_ARMV8_PSCI)
/* Check the psci version to determine if the psci is supported */
psci_ver = sec_firmware_support_psci_version();
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 0dae5fa..c10ccf9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -42,7 +42,8 @@ void ft_fixup_cpu(void *blob)
int addr_cells;
u64 val, core_id;
size_t *boot_code_size = &(__secondary_boot_code_size);
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
+ defined(CONFIG_FSL_PPA_ARMV8_PSCI)
int node;
u32 psci_ver;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
new file mode 100644
index 0000000..86045ac
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043a_psci.S
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/psci.h>
+
+ .pushsection ._secure.text, "ax"
+
+.globl psci_version
+psci_version:
+ ldr w0, =0x00010000 /* PSCI v1.0 */
+ ret
+
+ .popsection
diff --git a/arch/arm/cpu/armv8/psci.S b/arch/arm/cpu/armv8/psci.S
new file mode 100644
index 0000000..43d5d6b
--- /dev/null
+++ b/arch/arm/cpu/armv8/psci.S
@@ -0,0 +1,286 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Author: Hongbo Zhang <hongbo.zhang@nxp.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ * This file implements LS102X platform PSCI SYSTEM-SUSPEND function
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/psci.h>
+
+/* Default PSCI function, return -1, Not Implemented */
+#define PSCI_DEFAULT(__fn) \
+ ENTRY(__fn); \
+ mov w0, #ARM_PSCI_RET_NI; \
+ ret; \
+ ENDPROC(__fn); \
+ .weak __fn
+
+/* PSCI function and ID table definition*/
+#define PSCI_TABLE(__id, __fn) \
+ .word __id; \
+ .word __fn
+
+.pushsection ._secure.text, "ax"
+
+/* 32 bits PSCI default functions */
+PSCI_DEFAULT(psci_version)
+PSCI_DEFAULT(psci_cpu_suspend)
+PSCI_DEFAULT(psci_cpu_off)
+PSCI_DEFAULT(psci_cpu_on)
+PSCI_DEFAULT(psci_affinity_info)
+PSCI_DEFAULT(psci_migrate)
+PSCI_DEFAULT(psci_migrate_info_type)
+PSCI_DEFAULT(psci_migrate_info_up_cpu)
+PSCI_DEFAULT(psci_system_off)
+PSCI_DEFAULT(psci_system_reset)
+PSCI_DEFAULT(psci_features)
+PSCI_DEFAULT(psci_cpu_freeze)
+PSCI_DEFAULT(psci_cpu_default_suspend)
+PSCI_DEFAULT(psci_node_hw_state)
+PSCI_DEFAULT(psci_system_suspend)
+PSCI_DEFAULT(psci_set_suspend_mode)
+PSCI_DEFAULT(psi_stat_residency)
+PSCI_DEFAULT(psci_stat_count)
+
+.align 3
+_psci_32_table:
+PSCI_TABLE(ARM_PSCI_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_PSCI_VERSION, psci_version)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_SUSPEND, psci_cpu_suspend)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_OFF, psci_cpu_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_CPU_ON, psci_cpu_on)
+PSCI_TABLE(ARM_PSCI_0_2_FN_AFFINITY_INFO, psci_affinity_info)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE, psci_migrate)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE, psci_migrate_info_type)
+PSCI_TABLE(ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_OFF, psci_system_off)
+PSCI_TABLE(ARM_PSCI_0_2_FN_SYSTEM_RESET, psci_system_reset)
+PSCI_TABLE(ARM_PSCI_1_0_FN_PSCI_FEATURES, psci_features)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_FREEZE, psci_cpu_freeze)
+PSCI_TABLE(ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_NODE_HW_STATE, psci_node_hw_state)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SYSTEM_SUSPEND, psci_system_suspend)
+PSCI_TABLE(ARM_PSCI_1_0_FN_SET_SUSPEND_MODE, psci_set_suspend_mode)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_RESIDENCY, psi_stat_residency)
+PSCI_TABLE(ARM_PSCI_1_0_FN_STAT_COUNT, psci_stat_count)
+PSCI_TABLE(0, 0)
+
+/* 64 bits PSCI default functions */
+PSCI_DEFAULT(psci_cpu_suspend_64)
+PSCI_DEFAULT(psci_cpu_on_64)
+PSCI_DEFAULT(psci_affinity_info_64)
+PSCI_DEFAULT(psci_migrate_64)
+PSCI_DEFAULT(psci_migrate_info_up_cpu_64)
+PSCI_DEFAULT(psci_cpu_default_suspend_64)
+PSCI_DEFAULT(psci_node_hw_state_64)
+PSCI_DEFAULT(psci_system_suspend_64)
+PSCI_DEFAULT(psci_stat_residency_64)
+PSCI_DEFAULT(psci_stat_count_64)
+
+.align 3
+_psci_64_table:
+PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_SUSPEND, psci_cpu_suspend_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_CPU_ON, psci_cpu_on_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_AFFINITY_INFO, psci_affinity_info_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE, psci_migrate_64)
+PSCI_TABLE(ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU, psci_migrate_info_up_cpu_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND, psci_cpu_default_suspend_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_NODE_HW_STATE, psci_node_hw_state_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND, psci_system_suspend_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_RESIDENCY, psci_stat_residency_64)
+PSCI_TABLE(ARM_PSCI_1_0_FN64_STAT_COUNT, psci_stat_count_64)
+PSCI_TABLE(0, 0)
+
+.macro psci_enter
+ /* PSCI call is Fast Call(atomic), so mask DAIF */
+ mrs x15, DAIF
+ stp x15, xzr, [sp, #-16]!
+ ldr x15, =0x3C0
+ msr DAIF, x15
+ /* SMC convention, x18 ~ x30 should be saved by callee */
+ stp x29, x30, [sp, #-16]!
+ stp x27, x28, [sp, #-16]!
+ stp x25, x26, [sp, #-16]!
+ stp x23, x24, [sp, #-16]!
+ stp x21, x22, [sp, #-16]!
+ stp x19, x20, [sp, #-16]!
+ mrs x15, elr_el3
+ stp x18, x15, [sp, #-16]!
+.endm
+
+.macro psci_return
+ /* restore registers */
+ ldp x18, x15, [sp], #16
+ msr elr_el3, x15
+ ldp x19, x20, [sp], #16
+ ldp x21, x22, [sp], #16
+ ldp x23, x24, [sp], #16
+ ldp x25, x26, [sp], #16
+ ldp x27, x28, [sp], #16
+ ldp x29, x30, [sp], #16
+ /* restore DAIF */
+ ldp x15, xzr, [sp], #16
+ msr DAIF, x15
+ eret
+.endm
+
+/* Caller must put PSCI function-ID table base in x9 */
+handle_psci:
+ psci_enter
+1: ldr x10, [x9] /* Load PSCI function table */
+ ubfx x11, x10, #32, #32
+ ubfx x10, x10, #0, #32
+ cbz x10, 3f /* If reach the end, bail out */
+ cmp x10, x0
+ b.eq 2f /* PSCI function found */
+ add x9, x9, #8 /* If not match, try next entry */
+ b 1b
+
+2: blr x11 /* Call PSCI function */
+ psci_return
+
+3: mov x0, #ARM_PSCI_RET_NI
+ psci_return
+
+unknown_smc_id:
+ ldr x0, =0xFFFFFFFF
+ eret
+
+handle_smc32:
+ /* SMC function ID 0x84000000-0x8400001F: 32 bits PSCI */
+ ldr w9, =0x8400001F
+ cmp w0, w9
+ b.gt unknown_smc_id
+ ldr w9, =0x84000000
+ cmp w0, w9
+ b.lt unknown_smc_id
+
+ adr x9, _psci_32_table
+ b handle_psci
+
+handle_smc64:
+ /* check SMC32 or SMC64 calls */
+ ubfx x9, x0, #30, #1
+ cbz x9, handle_smc32
+
+ /* SMC function ID 0xC4000000-0xC400001F: 64 bits PSCI */
+ ldr x9, =0xC400001F
+ cmp x0, x9
+ b.gt unknown_smc_id
+ ldr x9, =0xC4000000
+ cmp x0, x9
+ b.lt unknown_smc_id
+
+ adr x9, _psci_64_table
+ b handle_psci
+
+/*
+ * Get CPU ID from MPIDR, suppose every cluster has same number of CPU cores,
+ * Platform with asymmetric clusters should implement their own interface.
+ * In case this function being called by other platform's C code, the ARM
+ * Architecture Procedure Call Standard is considered, e.g. register X0 is
+ * used for the return value, while in this PSCI environment, X0 usually holds
+ * the SMC function identifier, so X0 should be saved by caller function.
+ */
+ENTRY(psci_get_cpu_id)
+#ifdef CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
+ mrs x9, MPIDR_EL1
+ ubfx x9, x9, #8, #8
+ ldr x10, =CONFIG_ARMV8_PSCI_CPUS_PER_CLUSTER
+ mul x9, x10, x9
+#else
+ mov x9, xzr
+#endif
+ mrs x10, MPIDR_EL1
+ ubfx x10, x10, #0, #8
+ add x0, x10, x9
+ ret
+ENDPROC(psci_get_cpu_id)
+.weak psci_get_cpu_id
+
+/* CPU ID input in x0, stack top output in x0*/
+LENTRY(psci_get_cpu_stack_top)
+ adr x9, __secure_stack_end
+ lsl x0, x0, #ARM_PSCI_STACK_SHIFT
+ sub x0, x9, x0
+ ret
+ENDPROC(psci_get_cpu_stack_top)
+
+unhandled_exception:
+ b unhandled_exception /* simply dead loop */
+
+handle_sync:
+ mov x15, x30
+ mov x14, x0
+
+ bl psci_get_cpu_id
+ bl psci_get_cpu_stack_top
+ mov x9, #1
+ msr spsel, x9
+ mov sp, x0
+
+ mov x0, x14
+ mov x30, x15
+
+ mrs x9, esr_el3
+ ubfx x9, x9, #26, #6
+ cmp x9, #0x13
+ b.eq handle_smc32
+ cmp x9, #0x17
+ b.eq handle_smc64
+
+ b unhandled_exception
+
+ .align 11
+ .globl el3_exception_vectors
+el3_exception_vectors:
+ b unhandled_exception /* Sync, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* IRQ, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* FIQ, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* SError, Current EL using SP0 */
+ .align 7
+ b unhandled_exception /* Sync, Current EL using SPx */
+ .align 7
+ b unhandled_exception /* IRQ, Current EL using SPx */
+ .align 7
+ b unhandled_exception /* FIQ, Current EL using SPx */
+ .align 7
+ b unhandled_exception /* SError, Current EL using SPx */
+ .align 7
+ b handle_sync /* Sync, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* IRQ, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* FIQ, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* SError, Lower EL using AArch64 */
+ .align 7
+ b unhandled_exception /* Sync, Lower EL using AArch32 */
+ .align 7
+ b unhandled_exception /* IRQ, Lower EL using AArch32 */
+ .align 7
+ b unhandled_exception /* FIQ, Lower EL using AArch32 */
+ .align 7
+ b unhandled_exception /* SError, Lower EL using AArch32 */
+
+ENTRY(psci_setup_vectors)
+ adr x0, el3_exception_vectors
+ msr vbar_el3, x0
+ ret
+ENDPROC(psci_setup_vectors)
+
+ENTRY(psci_arch_init)
+ ret
+ENDPROC(psci_arch_init)
+.weak psci_arch_init
+
+.popsection
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c
index 2ddd67e..0b973f0 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -209,7 +209,7 @@ __weak bool sec_firmware_is_valid(const void *sec_firmware_img)
return true;
}
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
/*
* The PSCI_VERSION function is added from PSCI v0.2. When the PSCI
* v0.1 received this function, the NOT_SUPPORTED (0xffff_ffff) error
diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S
index 1b39f1d..903195d 100644
--- a/arch/arm/cpu/armv8/sec_firmware_asm.S
+++ b/arch/arm/cpu/armv8/sec_firmware_asm.S
@@ -41,7 +41,7 @@ WEAK(_sec_firmware_entry)
ret
ENDPROC(_sec_firmware_entry)
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
ENTRY(_sec_firmware_support_psci_version)
mov x0, 0x84000000
mov x1, 0x0
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index fd15ad5..22195b8 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -8,11 +8,17 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include <config.h>
+#include <asm/psci.h>
+
OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
OUTPUT_ARCH(aarch64)
ENTRY(_start)
SECTIONS
{
+#ifdef CONFIG_ARMV8_SECURE_BASE
+ /DISCARD/ : { *(.rela._secure*) }
+#endif
. = 0x00000000;
. = ALIGN(8);
@@ -23,6 +29,57 @@ SECTIONS
*(.text*)
}
+#ifdef CONFIG_ARMV8_PSCI
+ .__secure_start :
+#ifndef CONFIG_ARMV8_SECURE_BASE
+ ALIGN(CONSTANT(COMMONPAGESIZE))
+#endif
+ {
+ KEEP(*(.__secure_start))
+ }
+
+#ifndef CONFIG_ARMV8_SECURE_BASE
+#define CONFIG_ARMV8_SECURE_BASE
+#define __ARMV8_PSCI_STACK_IN_RAM
+#endif
+ .secure_text CONFIG_ARMV8_SECURE_BASE :
+ AT(ADDR(.__secure_start) + SIZEOF(.__secure_start))
+ {
+ *(._secure.text)
+ }
+
+ .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))
+ {
+ *(._secure.data)
+ }
+
+ .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),
+ CONSTANT(COMMONPAGESIZE)) (NOLOAD) :
+#ifdef __ARMV8_PSCI_STACK_IN_RAM
+ AT(ADDR(.secure_stack))
+#else
+ AT(LOADADDR(.secure_data) + SIZEOF(.secure_data))
+#endif
+ {
+ KEEP(*(.__secure_stack_start))
+
+ . = . + CONFIG_ARMV8_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;
+
+ . = ALIGN(CONSTANT(COMMONPAGESIZE));
+
+ KEEP(*(.__secure_stack_end))
+ }
+
+#ifndef __ARMV8_PSCI_STACK_IN_RAM
+ . = LOADADDR(.secure_stack);
+#endif
+
+ .__secure_end : AT(ADDR(.__secure_end)) {
+ KEEP(*(.__secure_end))
+ LONG(0x1d1071c); /* Must output something to reset LMA */
+ }
+#endif
+
. = ALIGN(8);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi
index 2e9f1f9..2101172 100644
--- a/arch/arm/dts/fsl-ls1043a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -135,8 +135,8 @@
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
ranges = <0x0 0x0 0x0 0x60000000 0x08000000
- 0x2 0x0 0x0 0x7e800000 0x00010000
- 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+ 0x1 0x0 0x0 0x7e800000 0x00010000
+ 0x2 0x0 0x0 0x7fb00000 0x00000100>;
status = "okay";
nor@0,0 {
@@ -148,21 +148,21 @@
device-width = <1>;
};
- nand@2,0 {
+ nand@1,0 {
compatible = "fsl,ifc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1 0x0 0x10000>;
};
- fpga: board-control@3,0 {
+ fpga: board-control@2,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
- reg = <0x3 0x0 0x0000100>;
+ reg = <0x2 0x0 0x0000100>;
bank-width = <1>;
device-width = <1>;
- ranges = <0 3 0 0x100>;
+ ranges = <0 2 0 0x100>;
};
};
diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts
index 16c5c89..f271e71 100644
--- a/arch/arm/dts/fsl-ls1043a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1043a-rdb.dts
@@ -47,12 +47,12 @@
compatible = "adi,adt7461a";
reg = <0x4c>;
};
- eeprom@56 {
+ eeprom@52 {
compatible = "at24,24c512";
reg = <0x52>;
};
- eeprom@57 {
+ eeprom@53 {
compatible = "at24,24c512";
reg = <0x53>;
};
@@ -69,8 +69,8 @@
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
ranges = <0x0 0x0 0x0 0x60000000 0x08000000
- 0x2 0x0 0x0 0x7e800000 0x00010000
- 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+ 0x1 0x0 0x0 0x7e800000 0x00010000
+ 0x2 0x0 0x0 0x7fb00000 0x00000100>;
nor@0,0 {
compatible = "cfi-flash";
diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h
index eb68185..a4e144b 100644
--- a/arch/arm/include/asm/armv8/sec_firmware.h
+++ b/arch/arm/include/asm/armv8/sec_firmware.h
@@ -14,7 +14,7 @@
int sec_firmware_init(const void *, u32 *, u32 *);
int _sec_firmware_entry(const void *, u32 *, u32 *);
bool sec_firmware_is_valid(const void *);
-#ifdef CONFIG_ARMV8_PSCI
+#ifdef CONFIG_FSL_PPA_ARMV8_PSCI
unsigned int sec_firmware_support_psci_version(void);
unsigned int _sec_firmware_support_psci_version(void);
#endif
diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 2553e3e..e1916f7 100644
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -182,11 +182,17 @@ lr .req x30
/*
* The next lower exception level is AArch64, 64bit EL2 | HCE |
- * SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1.
+ * RES1 (Bits[5:4]) | Non-secure EL0/EL1.
+ * and the SMD depends on requirements.
*/
+#ifdef CONFIG_ARMV8_PSCI
+ ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
+ SCR_EL3_RES1 | SCR_EL3_NS_EN)
+#else
ldr \tmp, =(SCR_EL3_RW_AARCH64 | SCR_EL3_HCE_EN |\
SCR_EL3_SMD_DIS | SCR_EL3_RES1 |\
SCR_EL3_NS_EN)
+#endif
msr scr_el3, \tmp
/* Return to the EL2_SP2 mode from EL3 */
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index 9f1f779..ac8b00d 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -45,6 +45,9 @@
#define ARM_PSCI_0_2_FN_BASE 0x84000000
#define ARM_PSCI_0_2_FN(n) (ARM_PSCI_0_2_FN_BASE + (n))
+#define ARM_PSCI_0_2_FN64_BASE 0xC4000000
+#define ARM_PSCI_0_2_FN64(n) (ARM_PSCI_0_2_FN64_BASE + (n))
+
#define ARM_PSCI_0_2_FN_PSCI_VERSION ARM_PSCI_0_2_FN(0)
#define ARM_PSCI_0_2_FN_CPU_SUSPEND ARM_PSCI_0_2_FN(1)
#define ARM_PSCI_0_2_FN_CPU_OFF ARM_PSCI_0_2_FN(2)
@@ -56,6 +59,12 @@
#define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8)
#define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9)
+#define ARM_PSCI_0_2_FN64_CPU_SUSPEND ARM_PSCI_0_2_FN64(1)
+#define ARM_PSCI_0_2_FN64_CPU_ON ARM_PSCI_0_2_FN64(3)
+#define ARM_PSCI_0_2_FN64_AFFINITY_INFO ARM_PSCI_0_2_FN64(4)
+#define ARM_PSCI_0_2_FN64_MIGRATE ARM_PSCI_0_2_FN64(5)
+#define ARM_PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU ARM_PSCI_0_2_FN64(7)
+
/* PSCI 1.0 interface */
#define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10)
#define ARM_PSCI_1_0_FN_CPU_FREEZE ARM_PSCI_0_2_FN(11)
@@ -66,6 +75,12 @@
#define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16)
#define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17)
+#define ARM_PSCI_1_0_FN64_CPU_DEFAULT_SUSPEND ARM_PSCI_0_2_FN64(12)
+#define ARM_PSCI_1_0_FN64_NODE_HW_STATE ARM_PSCI_0_2_FN64(13)
+#define ARM_PSCI_1_0_FN64_SYSTEM_SUSPEND ARM_PSCI_0_2_FN64(14)
+#define ARM_PSCI_1_0_FN64_STAT_RESIDENCY ARM_PSCI_0_2_FN64(16)
+#define ARM_PSCI_1_0_FN64_STAT_COUNT ARM_PSCI_0_2_FN64(17)
+
/* 1KB stack per core */
#define ARM_PSCI_STACK_SHIFT 10
#define ARM_PSCI_STACK_SIZE (1 << ARM_PSCI_STACK_SHIFT)
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index 5a403bc..d23044a 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -6,7 +6,7 @@
#define __secure __attribute__ ((section ("._secure.text")))
#define __secure_data __attribute__ ((section ("._secure.data")))
-#ifdef CONFIG_ARMV7_SECURE_BASE
+#if defined(CONFIG_ARMV7_SECURE_BASE) || defined(CONFIG_ARMV8_SECURE_BASE)
/*
* Warning, horror ahead.
*
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 01efc43..dc4c991 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -237,6 +237,17 @@ void smc_call(struct pt_regs *args);
void __noreturn psci_system_reset(void);
void __noreturn psci_system_off(void);
+#ifdef CONFIG_ARMV8_PSCI
+extern char __secure_start[];
+extern char __secure_end[];
+extern char __secure_stack_start[];
+extern char __secure_stack_end[];
+
+void armv8_setup_psci(void);
+void psci_setup_vectors(void);
+void psci_arch_init(void);
+#endif
+
#endif /* __ASSEMBLY__ */
#else /* CONFIG_ARM64 */
diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c
index 4481f9e..e261d4f 100644
--- a/arch/arm/lib/bootm-fdt.c
+++ b/arch/arm/lib/bootm-fdt.c
@@ -52,7 +52,8 @@ int arch_fixup_fdt(void *blob)
return ret;
#endif
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI)
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI) || \
+ defined(CONFIG_FSL_PPA_ARMV8_PSCI)
ret = psci_update_dt(blob);
if (ret)
return ret;
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 4eee13a..43cc83e 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -316,6 +316,9 @@ static void boot_jump_linux(bootm_headers_t *images, int flag)
announce_and_cleanup(fake);
if (!fake) {
+#ifdef CONFIG_ARMV8_PSCI
+ armv8_setup_psci();
+#endif
do_nonsec_virt_switch();
update_os_arch_secondary_cores(images->os.arch);
diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c
index baf6d70..45af037 100644
--- a/arch/arm/lib/psci-dt.c
+++ b/arch/arm/lib/psci-dt.c
@@ -16,7 +16,8 @@
int fdt_psci(void *fdt)
{
-#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI)
+#if defined(CONFIG_ARMV7_PSCI) || defined(CONFIG_ARMV8_PSCI) || \
+ defined(CONFIG_FSL_PPA_ARMV8_PSCI)
int nodeoff;
unsigned int psci_ver = 0;
int tmp;
@@ -65,7 +66,7 @@ int fdt_psci(void *fdt)
init_psci_node:
#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
psci_ver = sec_firmware_support_psci_version();
-#elif defined(CONFIG_ARMV7_PSCI_1_0)
+#elif defined(CONFIG_ARMV7_PSCI_1_0) || defined(CONFIG_ARMV8_PSCI)
psci_ver = ARM_PSCI_VER_1_0;
#endif
switch (psci_ver) {
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 603d6ae..8cfc612 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -517,6 +517,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_FSL_ERRATUM_A007798
+#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_PCI_VER_3_X
@@ -557,6 +558,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A006384
#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_FSL_ERRATUM_A004477
+#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_SFP_VER_3_0
#ifdef CONFIG_ARCH_B4860
@@ -626,6 +628,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ERRATUM_A008378
#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009942
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023) ||\
defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
@@ -668,6 +671,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ERRATUM_A008378
#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_ERRATUM_A009942
#elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
#define CONFIG_E6500
@@ -717,6 +721,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A009942
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define CONFIG_SYS_FSL_SFP_VER_3_0