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-rw-r--r--arch/arm/Kconfig163
-rw-r--r--arch/arm/Makefile6
-rw-r--r--arch/arm/cpu/arm926ejs/lpc32xx/clk.c10
-rw-r--r--arch/arm/cpu/arm926ejs/lpc32xx/devices.c3
-rw-r--r--arch/arm/cpu/arm926ejs/spear/cpu.c34
-rw-r--r--arch/arm/cpu/armv7/Makefile4
-rw-r--r--arch/arm/cpu/armv7/ls102xa/cpu.c15
-rw-r--r--arch/arm/cpu/armv7/mx6/Kconfig30
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c2
-rw-r--r--arch/arm/cpu/armv7/mx6/ddr.c4
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c198
-rw-r--r--arch/arm/cpu/armv7/mx7/Kconfig26
-rw-r--r--arch/arm/cpu/armv7/mx7/Makefile8
-rw-r--r--arch/arm/cpu/armv7/mx7/clock.c1127
-rw-r--r--arch/arm/cpu/armv7/mx7/clock_slice.c757
-rw-r--r--arch/arm/cpu/armv7/mx7/soc.c267
-rw-r--r--arch/arm/cpu/armv7/nonsec_virt.S14
-rw-r--r--arch/arm/cpu/armv7/omap-common/emif-common.c6
-rw-r--r--arch/arm/cpu/armv7/omap3/Kconfig12
-rw-r--r--arch/arm/cpu/armv7/rmobile/Kconfig8
-rw-r--r--arch/arm/cpu/armv7/sunxi/board.c8
-rw-r--r--arch/arm/cpu/armv7/u8500/Makefile9
-rw-r--r--arch/arm/cpu/armv7/u8500/clock.c74
-rw-r--r--arch/arm/cpu/armv7/u8500/cpu.c176
-rw-r--r--arch/arm/cpu/armv7/u8500/lowlevel.S21
-rw-r--r--arch/arm/cpu/armv7/u8500/prcmu.c214
-rw-r--r--arch/arm/cpu/armv7/u8500/timer.c135
-rw-r--r--arch/arm/cpu/armv8/start.S2
-rw-r--r--arch/arm/dts/Makefile17
-rw-r--r--arch/arm/dts/exynos4210-trats.dts4
-rw-r--r--arch/arm/dts/ls1021a-twr.dts16
-rw-r--r--arch/arm/dts/sun4i-a10-inet1.dts226
-rw-r--r--arch/arm/dts/sun4i-a10-inet9f-rev03.dts219
-rw-r--r--arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts209
-rw-r--r--arch/arm/dts/sun5i-a10s-wobo-i5.dts224
-rw-r--r--arch/arm/dts/sun5i-a10s.dtsi11
-rw-r--r--arch/arm/dts/sun5i-a13-q8-tablet.dts60
-rw-r--r--arch/arm/dts/sun5i-q8-common.dtsi170
-rw-r--r--arch/arm/dts/sun8i-a23-q8-tablet.dts65
-rw-r--r--arch/arm/dts/sun8i-a33-q8-tablet.dts65
-rw-r--r--arch/arm/dts/sun8i-q8-common.dtsi84
-rw-r--r--arch/arm/dts/sunxi-q8-common.dtsi77
-rw-r--r--arch/arm/dts/tegra20.dtsi57
-rw-r--r--arch/arm/dts/tegra210-p2371-2180.dts60
-rw-r--r--arch/arm/dts/uniphier-ph1-ld4-ref.dts16
-rw-r--r--arch/arm/dts/uniphier-ph1-ld6b-ref.dts17
-rw-r--r--arch/arm/dts/uniphier-ph1-pro4-ref.dts16
-rw-r--r--arch/arm/dts/uniphier-ph1-pro5-4kbox.dts64
-rw-r--r--arch/arm/dts/uniphier-ph1-sld8-ref.dts16
-rw-r--r--arch/arm/dts/uniphier-pinctrl.dtsi38
-rw-r--r--arch/arm/dts/uniphier-proxstream2-gentil.dts62
-rw-r--r--arch/arm/dts/uniphier-proxstream2-vodka.dts62
-rw-r--r--arch/arm/imx-common/Makefile10
-rw-r--r--arch/arm/imx-common/cache.c103
-rw-r--r--arch/arm/imx-common/cpu.c33
-rw-r--r--arch/arm/imx-common/ddrmc-vf610.c193
-rw-r--r--arch/arm/imx-common/init.c118
-rw-r--r--arch/arm/imx-common/iomux-v3.c6
-rw-r--r--arch/arm/imx-common/syscounter.c126
-rw-r--r--arch/arm/include/asm/arch-am33xx/cpu.h1
-rw-r--r--arch/arm/include/asm/arch-hi6220/gpio.h2
-rw-r--r--arch/arm/include/asm/arch-hi6220/hi6220.h3
-rw-r--r--arch/arm/include/asm/arch-imx/cpu.h4
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/clk.h3
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/emc.h2
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/gpio_grp.h4
-rw-r--r--arch/arm/include/asm/arch-mx6/imx-regs.h4
-rw-r--r--arch/arm/include/asm/arch-mx7/clock.h348
-rw-r--r--arch/arm/include/asm/arch-mx7/clock_slice.h116
-rw-r--r--arch/arm/include/asm/arch-mx7/crm_regs.h2813
-rw-r--r--arch/arm/include/asm/arch-mx7/imx-regs.h1307
-rw-r--r--arch/arm/include/asm/arch-mx7/sys_proto.h9
-rw-r--r--arch/arm/include/asm/arch-omap5/cpu.h2
-rw-r--r--arch/arm/include/asm/arch-rmobile/rcar-base.h3
-rw-r--r--arch/arm/include/asm/arch-spear/spr_misc.h1
-rw-r--r--arch/arm/include/asm/arch-sunxi/spl.h54
-rw-r--r--arch/arm/include/asm/arch-tegra/clock.h7
-rw-r--r--arch/arm/include/asm/arch-tegra/dc.h2
-rw-r--r--arch/arm/include/asm/arch-tegra/gpio.h9
-rw-r--r--arch/arm/include/asm/arch-tegra114/clock-tables.h1
-rw-r--r--arch/arm/include/asm/arch-tegra114/clock.h3
-rw-r--r--arch/arm/include/asm/arch-tegra124/clock-tables.h1
-rw-r--r--arch/arm/include/asm/arch-tegra124/clock.h3
-rw-r--r--arch/arm/include/asm/arch-tegra20/clock-tables.h1
-rw-r--r--arch/arm/include/asm/arch-tegra210/clock-tables.h1
-rw-r--r--arch/arm/include/asm/arch-tegra30/clock-tables.h1
-rw-r--r--arch/arm/include/asm/arch-u8500/clock.h53
-rw-r--r--arch/arm/include/asm/arch-u8500/db8500_gpio.h42
-rw-r--r--arch/arm/include/asm/arch-u8500/db8500_pincfg.h170
-rw-r--r--arch/arm/include/asm/arch-u8500/gpio.h231
-rw-r--r--arch/arm/include/asm/arch-u8500/hardware.h94
-rw-r--r--arch/arm/include/asm/arch-u8500/prcmu.h64
-rw-r--r--arch/arm/include/asm/arch-u8500/sys_proto.h12
-rw-r--r--arch/arm/include/asm/arch-u8500/u8500.h31
-rw-r--r--arch/arm/include/asm/arch-vf610/ddrmc-vf610.h40
-rw-r--r--arch/arm/include/asm/arch-vf610/imx-regs.h6
-rw-r--r--arch/arm/include/asm/imx-common/boot_mode.h21
-rw-r--r--arch/arm/include/asm/imx-common/sys_proto.h7
-rw-r--r--arch/arm/include/asm/imx-common/syscounter.h29
-rw-r--r--arch/arm/include/asm/mach-types.h76
-rw-r--r--arch/arm/include/asm/u-boot.h19
-rw-r--r--arch/arm/lib/Makefile3
-rw-r--r--arch/arm/lib/board.c687
-rw-r--r--arch/arm/mach-at91/Kconfig30
-rw-r--r--arch/arm/mach-davinci/Kconfig45
-rw-r--r--arch/arm/mach-davinci/cpu.c2
-rw-r--r--arch/arm/mach-exynos/clock.c10
-rw-r--r--arch/arm/mach-keystone/include/mach/clock_defs.h2
-rw-r--r--arch/arm/mach-keystone/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-kirkwood/Kconfig20
-rw-r--r--arch/arm/mach-mvebu/cpu.c36
-rw-r--r--arch/arm/mach-mvebu/include/mach/soc.h2
-rw-r--r--arch/arm/mach-mvebu/timer.c2
-rw-r--r--arch/arm/mach-nomadik/Kconfig17
-rw-r--r--arch/arm/mach-nomadik/Makefile9
-rw-r--r--arch/arm/mach-nomadik/gpio.c83
-rw-r--r--arch/arm/mach-nomadik/include/mach/gpio.h26
-rw-r--r--arch/arm/mach-nomadik/include/mach/mtu.h50
-rw-r--r--arch/arm/mach-nomadik/reset.S14
-rw-r--r--arch/arm/mach-nomadik/timer.c71
-rw-r--r--arch/arm/mach-rockchip/board-spl.c7
-rw-r--r--arch/arm/mach-socfpga/Kconfig4
-rw-r--r--arch/arm/mach-tegra/clock.c21
-rw-r--r--arch/arm/mach-tegra/tegra114/clock.c9
-rw-r--r--arch/arm/mach-tegra/tegra124/clock.c9
-rw-r--r--arch/arm/mach-tegra/tegra210/Kconfig9
-rw-r--r--arch/arm/mach-tegra/tegra210/clock.c21
-rw-r--r--arch/arm/mach-uniphier/Kconfig95
-rw-r--r--arch/arm/mach-uniphier/Makefile21
-rw-r--r--arch/arm/mach-uniphier/bcu/Makefile3
-rw-r--r--arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c (renamed from arch/arm/mach-uniphier/ph1-ld4/bcu_init.c)8
-rw-r--r--arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c (renamed from arch/arm/mach-uniphier/ph1-sld3/bcu_init.c)8
-rw-r--r--arch/arm/mach-uniphier/board_common.c23
-rw-r--r--arch/arm/mach-uniphier/board_early_init_f.c73
-rw-r--r--arch/arm/mach-uniphier/board_early_init_r.c7
-rw-r--r--arch/arm/mach-uniphier/boards.c130
-rw-r--r--arch/arm/mach-uniphier/boot-mode/Makefile9
-rw-r--r--arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c (renamed from arch/arm/mach-uniphier/ph1-pro4/boot-mode.c)21
-rw-r--r--arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c75
-rw-r--r--arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c (renamed from arch/arm/mach-uniphier/ph1-sld3/boot-mode.c)23
-rw-r--r--arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c75
-rw-r--r--arch/arm/mach-uniphier/boot-mode/boot-mode.c45
-rw-r--r--arch/arm/mach-uniphier/clk/Makefile7
-rw-r--r--arch/arm/mach-uniphier/clk/clk-ph1-ld4.c (renamed from arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c)3
-rw-r--r--arch/arm/mach-uniphier/clk/clk-ph1-pro4.c (renamed from arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c)3
-rw-r--r--arch/arm/mach-uniphier/clk/clk-ph1-pro5.c44
-rw-r--r--arch/arm/mach-uniphier/clk/clk-proxstream2.c50
-rw-r--r--arch/arm/mach-uniphier/cmd_pinmon.c43
-rw-r--r--arch/arm/mach-uniphier/ddrphy/Makefile3
-rw-r--r--arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c (renamed from arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c)4
-rw-r--r--arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c (renamed from arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c)4
-rw-r--r--arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c (renamed from arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c)4
-rw-r--r--arch/arm/mach-uniphier/ddrphy/ddrphy-training.c (renamed from arch/arm/mach-uniphier/ddrphy_training.c)0
-rw-r--r--arch/arm/mach-uniphier/debug_ll.S185
-rw-r--r--arch/arm/mach-uniphier/dram_init.c51
-rw-r--r--arch/arm/mach-uniphier/early-clk/Makefile7
-rw-r--r--arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c (renamed from arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c)5
-rw-r--r--arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c39
-rw-r--r--arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c44
-rw-r--r--arch/arm/mach-uniphier/early-pinctrl/Makefile1
-rw-r--r--arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c26
-rw-r--r--arch/arm/mach-uniphier/include/mach/board.h42
-rw-r--r--arch/arm/mach-uniphier/include/mach/boot-device.h15
-rw-r--r--arch/arm/mach-uniphier/include/mach/ddrphy-regs.h7
-rw-r--r--arch/arm/mach-uniphier/include/mach/debug-uart.S23
-rw-r--r--arch/arm/mach-uniphier/include/mach/init.h99
-rw-r--r--arch/arm/mach-uniphier/include/mach/led.h100
-rw-r--r--arch/arm/mach-uniphier/include/mach/micro-support-card.h39
-rw-r--r--arch/arm/mach-uniphier/include/mach/platdevice.h24
-rw-r--r--arch/arm/mach-uniphier/include/mach/sc-regs.h25
-rw-r--r--arch/arm/mach-uniphier/include/mach/sg-regs.h50
-rw-r--r--arch/arm/mach-uniphier/include/mach/soc_info.h63
-rw-r--r--arch/arm/mach-uniphier/init/Makefile9
-rw-r--r--arch/arm/mach-uniphier/init/init-ph1-ld4.c60
-rw-r--r--arch/arm/mach-uniphier/init/init-ph1-pro4.c58
-rw-r--r--arch/arm/mach-uniphier/init/init-ph1-pro5.c42
-rw-r--r--arch/arm/mach-uniphier/init/init-ph1-sld3.c53
-rw-r--r--arch/arm/mach-uniphier/init/init-ph1-sld8.c60
-rw-r--r--arch/arm/mach-uniphier/init/init-proxstream2.c41
-rw-r--r--arch/arm/mach-uniphier/init/init.c58
-rw-r--r--arch/arm/mach-uniphier/init_page_table.S6
-rw-r--r--arch/arm/mach-uniphier/lowlevel_init.S3
-rw-r--r--arch/arm/mach-uniphier/memconf.c103
-rw-r--r--arch/arm/mach-uniphier/memconf/Makefile4
-rw-r--r--arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c59
-rw-r--r--arch/arm/mach-uniphier/memconf/memconf-proxstream2.c64
-rw-r--r--arch/arm/mach-uniphier/memconf/memconf.c104
-rw-r--r--arch/arm/mach-uniphier/micro-support-card.c (renamed from arch/arm/mach-uniphier/support_card.c)169
-rw-r--r--arch/arm/mach-uniphier/ph1-ld4/Makefile15
-rw-r--r--arch/arm/mach-uniphier/ph1-ld4/boot-mode.c1
-rw-r--r--arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c1
-rw-r--r--arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c27
-rw-r--r--arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S29
-rw-r--r--arch/arm/mach-uniphier/ph1-ld4/pinctrl.c48
-rw-r--r--arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c1
-rw-r--r--arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c49
-rw-r--r--arch/arm/mach-uniphier/ph1-ld4/sg_init.c18
-rw-r--r--arch/arm/mach-uniphier/ph1-pro4/Makefile15
-rw-r--r--arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c26
-rw-r--r--arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S39
-rw-r--r--arch/arm/mach-uniphier/ph1-pro4/pinctrl.c49
-rw-r--r--arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c42
-rw-r--r--arch/arm/mach-uniphier/ph1-pro4/sg_init.c18
-rw-r--r--arch/arm/mach-uniphier/ph1-sld3/Makefile15
-rw-r--r--arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c1
-rw-r--r--arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c1
-rw-r--r--arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c23
-rw-r--r--arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S33
-rw-r--r--arch/arm/mach-uniphier/ph1-sld3/memconf.c52
-rw-r--r--arch/arm/mach-uniphier/ph1-sld3/pinctrl.c24
-rw-r--r--arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c37
-rw-r--r--arch/arm/mach-uniphier/ph1-sld3/sg_init.c9
-rw-r--r--arch/arm/mach-uniphier/ph1-sld3/umc_init.c15
-rw-r--r--arch/arm/mach-uniphier/ph1-sld8/Makefile1
-rw-r--r--arch/arm/mach-uniphier/ph1-sld8/bcu_init.c1
-rw-r--r--arch/arm/mach-uniphier/ph1-sld8/boot-mode.c1
-rw-r--r--arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c1
-rw-r--r--arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c1
-rw-r--r--arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c27
-rw-r--r--arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S29
-rw-r--r--arch/arm/mach-uniphier/ph1-sld8/pinctrl.c51
-rw-r--r--arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c1
-rw-r--r--arch/arm/mach-uniphier/ph1-sld8/sbc_init.c1
-rw-r--r--arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c57
-rw-r--r--arch/arm/mach-uniphier/ph1-sld8/sg_init.c1
-rw-r--r--arch/arm/mach-uniphier/pinctrl/Makefile7
-rw-r--r--arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c49
-rw-r--r--arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c45
-rw-r--r--arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c50
-rw-r--r--arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c43
-rw-r--r--arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c25
-rw-r--r--arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c43
-rw-r--r--arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c45
-rw-r--r--arch/arm/mach-uniphier/pll/Makefile8
-rw-r--r--arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c (renamed from arch/arm/mach-uniphier/ph1-ld4/pll_init.c)34
-rw-r--r--arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c (renamed from arch/arm/mach-uniphier/ph1-pro4/pll_init.c)36
-rw-r--r--arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c (renamed from arch/arm/mach-uniphier/ph1-sld3/pll_init.c)5
-rw-r--r--arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c (renamed from arch/arm/mach-uniphier/ph1-sld8/pll_init.c)5
-rw-r--r--arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c (renamed from arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c)6
-rw-r--r--arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c (renamed from arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c)5
-rw-r--r--arch/arm/mach-uniphier/print_misc_info.c2
-rw-r--r--arch/arm/mach-uniphier/sbc/Makefile7
-rw-r--r--arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c (renamed from arch/arm/mach-uniphier/ph1-ld4/sbc_init.c)17
-rw-r--r--arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c (renamed from arch/arm/mach-uniphier/ph1-pro4/sbc_init.c)17
-rw-r--r--arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c (renamed from arch/arm/mach-uniphier/ph1-sld3/sbc_init.c)19
-rw-r--r--arch/arm/mach-uniphier/sbc/sbc-proxstream2.c48
-rw-r--r--arch/arm/mach-uniphier/soc_info.c61
-rw-r--r--arch/arm/mach-uniphier/spl.c76
-rw-r--r--arch/arm/mach-uniphier/umc/Makefile3
-rw-r--r--arch/arm/mach-uniphier/umc/umc-ph1-ld4.c (renamed from arch/arm/mach-uniphier/ph1-ld4/umc_init.c)30
-rw-r--r--arch/arm/mach-uniphier/umc/umc-ph1-pro4.c (renamed from arch/arm/mach-uniphier/ph1-pro4/umc_init.c)36
-rw-r--r--arch/arm/mach-uniphier/umc/umc-ph1-sld8.c (renamed from arch/arm/mach-uniphier/ph1-sld8/umc_init.c)30
-rw-r--r--arch/arm/mach-versatile/Kconfig15
-rw-r--r--arch/arm/mach-zynq/include/mach/gpio.h2
-rw-r--r--arch/powerpc/cpu/ppc4xx/Kconfig4
-rw-r--r--arch/powerpc/include/asm/global_data.h6
-rw-r--r--arch/sandbox/dts/sandbox.dts4
-rw-r--r--arch/x86/cpu/quark/dram.c10
-rw-r--r--arch/x86/cpu/quark/quark.c249
-rw-r--r--arch/x86/dts/galileo.dts12
-rw-r--r--arch/x86/include/asm/arch-quark/msg_port.h31
-rw-r--r--arch/x86/include/asm/arch-quark/quark.h81
-rw-r--r--arch/x86/lib/fsp/fsp_dram.c3
263 files changed, 12323 insertions, 4693 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8085a24..7981355 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -70,7 +70,7 @@ config SYS_L2CACHE_OFF
choice
prompt "Target select"
- default ARCH_VERSATILE
+ default TARGET_HIKEY
config ARCH_AT91
bool "Atmel AT91"
@@ -79,10 +79,6 @@ config TARGET_EDB93XX
bool "Support edb93xx"
select CPU_ARM920T
-config TARGET_SCB9328
- bool "Support scb9328"
- select CPU_ARM920T
-
config TARGET_VCMA9
bool "Support VCMA9"
select CPU_ARM920T
@@ -138,11 +134,6 @@ config TARGET_MX25PDK
bool "Support mx25pdk"
select CPU_ARM926EJS
-config TARGET_TX25
- bool "Support tx25"
- select CPU_ARM926EJS
- select SUPPORT_SPL
-
config TARGET_ZMX25
bool "Support zmx25"
select CPU_ARM926EJS
@@ -152,14 +143,6 @@ config TARGET_APF27
select CPU_ARM926EJS
select SUPPORT_SPL
-config TARGET_IMX27LITE
- bool "Support imx27lite"
- select CPU_ARM926EJS
-
-config TARGET_MAGNESIUM
- bool "Support magnesium"
- select CPU_ARM926EJS
-
config TARGET_APX4DEVKIT
bool "Support apx4devkit"
select CPU_ARM926EJS
@@ -205,10 +188,6 @@ config TARGET_SC_SPS_1
select CPU_ARM926EJS
select SUPPORT_SPL
-config ARCH_NOMADIK
- bool "ST-Ericsson Nomadik"
- select CPU_ARM926EJS
-
config ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
@@ -243,18 +222,10 @@ config TARGET_X600
select CPU_ARM926EJS
select SUPPORT_SPL
-config ARCH_VERSATILE
- bool "ARM Ltd. Versatile family"
- select CPU_ARM926EJS
-
config TARGET_IMX31_PHYCORE
bool "Support imx31_phycore"
select CPU_ARM1136
-config TARGET_QONG
- bool "Support qong"
- select CPU_ARM1136
-
config TARGET_MX31ADS
bool "Support mx31ads"
select CPU_ARM1136
@@ -264,14 +235,6 @@ config TARGET_MX31PDK
select CPU_ARM1136
select SUPPORT_SPL
-config TARGET_TT01
- bool "Support tt01"
- select CPU_ARM1136
-
-config TARGET_IMX31_LITEKIT
- bool "Support imx31_litekit"
- select CPU_ARM1136
-
config TARGET_WOODBURN
bool "Support woodburn"
select CPU_ARM1136
@@ -400,6 +363,13 @@ config TARGET_AM335X_EVM
select DM_SERIAL
select DM_GPIO
+config TARGET_AM335X_SL50
+ bool "Support am335x_sl50"
+ select CPU_V7
+ select SUPPORT_SPL
+ select DM
+ select DM_SERIAL
+
config TARGET_AM43XX_EVM
bool "Support am43xx_evm"
select CPU_V7
@@ -472,6 +442,10 @@ config ARCH_KEYSTONE
select CPU_V7
select SUPPORT_SPL
+config ARCH_MX7
+ bool "Freescale MX7"
+ select CPU_V7
+
config ARCH_MX6
bool "Freescale MX6"
select CPU_V7
@@ -485,10 +459,6 @@ config TARGET_M53EVK
select CPU_V7
select SUPPORT_SPL
-config TARGET_IMA3_MX53
- bool "Support ima3-mx53"
- select CPU_V7
-
config TARGET_MX51EVK
bool "Support mx51evk"
select CPU_V7
@@ -509,14 +479,6 @@ config TARGET_MX53SMD
bool "Support mx53smd"
select CPU_V7
-config TARGET_MX51_EFIKAMX
- bool "Support mx51_efikamx"
- select CPU_V7
-
-config TARGET_VISION2
- bool "Support vision2"
- select CPU_V7
-
config OMAP34XX
bool "OMAP34XX SoC"
select CPU_V7
@@ -564,18 +526,10 @@ config ARCH_SUNXI
select USB_STORAGE
select USB_KEYBOARD
-config TARGET_SNOWBALL
- bool "Support snowball"
- select CPU_V7
-
config TARGET_TS4800
bool "Support TS4800"
select CPU_V7
-config TARGET_U8500_HREF
- bool "Support u8500_href"
- select CPU_V7
-
config TARGET_VF610TWR
bool "Support vf610twr"
select CPU_V7
@@ -584,6 +538,10 @@ config TARGET_COLIBRI_VF
bool "Support Colibri VF50/61"
select CPU_V7
+config TARGET_PCM052
+ bool "Support pcm-052"
+ select CPU_V7
+
config ARCH_ZYNQ
bool "Xilinx Zynq Platform"
select CPU_V7
@@ -609,6 +567,15 @@ config TARGET_VEXPRESS64_BASE_FVP
select ARM64
select SEMIHOSTING
+config TARGET_VEXPRESS64_BASE_FVP_DRAM
+ bool "Support Versatile Express ARMv8a FVP BASE model booting from DRAM"
+ select ARM64
+ help
+ This target is derived from TARGET_VEXPRESS64_BASE_FVP and over-rides
+ the default config to allow the user to load the images directly into
+ DRAM using model parameters rather than by using semi-hosting to load
+ the files from the host filesystem.
+
config TARGET_VEXPRESS64_JUNO
bool "Support Versatile Express Juno Development Platform"
select ARM64
@@ -648,6 +615,9 @@ config TARGET_LS2085ARDB
config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
+ select DM
+ select DM_GPIO
+ select DM_SERIAL
help
Support for HiKey 96boards platform. It features a HI6220
SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
@@ -656,66 +626,19 @@ config TARGET_LS1021AQDS
bool "Support ls1021aqds"
select CPU_V7
select SUPPORT_SPL
-
config TARGET_LS1021ATWR
bool "Support ls1021atwr"
select CPU_V7
select SUPPORT_SPL
-config TARGET_BALLOON3
- bool "Support balloon3"
- select CPU_PXA
-
config TARGET_H2200
bool "Support h2200"
select CPU_PXA
-config TARGET_PALMLD
- bool "Support palmld"
- select CPU_PXA
-
-config TARGET_PALMTC
- bool "Support palmtc"
- select CPU_PXA
-
-config TARGET_PALMTREO680
- bool "Support palmtreo680"
- select CPU_PXA
- select SUPPORT_SPL
-
-config TARGET_PXA255_IDP
- bool "Support pxa255_idp"
- select CPU_PXA
-
-config TARGET_TRIZEPSIV
- bool "Support trizepsiv"
- select CPU_PXA
-
-config TARGET_VPAC270
- bool "Support vpac270"
- select CPU_PXA
- select SUPPORT_SPL
-
-config TARGET_XAENIAX
- bool "Support xaeniax"
- select CPU_PXA
-
-config TARGET_ZIPITZ2
- bool "Support zipitz2"
- select CPU_PXA
-
-config TARGET_LP8X4X
- bool "Support lp8x4x"
- select CPU_PXA
-
config TARGET_COLIBRI_PXA270
bool "Support colibri_pxa270"
select CPU_PXA
-config TARGET_JORNADA
- bool "Support jornada"
- select CPU_SA1100
-
config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
select CPU_V7
@@ -761,12 +684,12 @@ source "arch/arm/mach-keystone/Kconfig"
source "arch/arm/mach-kirkwood/Kconfig"
+source "arch/arm/cpu/armv7/mx7/Kconfig"
+
source "arch/arm/cpu/armv7/mx6/Kconfig"
source "arch/arm/cpu/armv7/mx5/Kconfig"
-source "arch/arm/mach-nomadik/Kconfig"
-
source "arch/arm/cpu/armv7/omap3/Kconfig"
source "arch/arm/cpu/armv7/omap4/Kconfig"
@@ -787,8 +710,6 @@ source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/mach-uniphier/Kconfig"
-source "arch/arm/mach-versatile/Kconfig"
-
source "arch/arm/mach-zynq/Kconfig"
source "arch/arm/cpu/armv7/Kconfig"
@@ -809,7 +730,6 @@ source "board/Marvell/gplugd/Kconfig"
source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
-source "board/balloon3/Kconfig"
source "board/bluegiga/apx4devkit/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcmcygnus/Kconfig"
@@ -818,10 +738,8 @@ source "board/cirrus/edb93xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_t43/Kconfig"
source "board/creative/xfi3/Kconfig"
-source "board/davedenx/qong/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
-source "board/esg/ima3-mx53/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls2085aqds/Kconfig"
source "board/freescale/ls2085ardb/Kconfig"
@@ -839,30 +757,19 @@ source "board/freescale/mx53evk/Kconfig"
source "board/freescale/mx53loco/Kconfig"
source "board/freescale/mx53smd/Kconfig"
source "board/freescale/vf610twr/Kconfig"
-source "board/genesi/mx51_efikamx/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/h2200/Kconfig"
-source "board/hale/tt01/Kconfig"
source "board/hisilicon/hikey/Kconfig"
-source "board/icpdas/lp8x4x/Kconfig"
source "board/imx31_phycore/Kconfig"
source "board/isee/igep0033/Kconfig"
-source "board/jornada/Kconfig"
-source "board/karo/tx25/Kconfig"
-source "board/logicpd/imx27lite/Kconfig"
-source "board/logicpd/imx31_litekit/Kconfig"
source "board/maxbcm/Kconfig"
source "board/mpl/vcma9/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig"
-source "board/palmld/Kconfig"
-source "board/palmtc/Kconfig"
-source "board/palmtreo680/Kconfig"
source "board/phytec/pcm051/Kconfig"
+source "board/phytec/pcm052/Kconfig"
source "board/ppcag/bg0900/Kconfig"
-source "board/pxa255_idp/Kconfig"
source "board/samsung/smdk2410/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
-source "board/scb9328/Kconfig"
source "board/schulercontrol/sc_sps_1/Kconfig"
source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"
@@ -873,12 +780,11 @@ source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"
source "board/spear/spear600/Kconfig"
source "board/spear/x600/Kconfig"
-source "board/st-ericsson/snowball/Kconfig"
-source "board/st-ericsson/u8500/Kconfig"
source "board/st/stm32f429-discovery/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/sunxi/Kconfig"
source "board/syteco/zmx25/Kconfig"
+source "board/tcl/sl50/Kconfig"
source "board/ti/am335x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/birdland/bav335x/Kconfig"
@@ -887,15 +793,10 @@ source "board/ti/ti816x/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/toradex/colibri_vf/Kconfig"
-source "board/trizepsiv/Kconfig"
source "board/technologic/ts4800/Kconfig"
-source "board/ttcontrol/vision2/Kconfig"
-source "board/vpac270/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
-source "board/xaeniax/Kconfig"
-source "board/zipitz2/Kconfig"
source "arch/arm/Kconfig.debug"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 1eca815..58f9bbb 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -51,14 +51,12 @@ machine-$(CONFIG_ARCH_KEYSTONE) += keystone
machine-$(CONFIG_KIRKWOOD) += kirkwood
machine-$(CONFIG_ARMADA_XP) += mvebu
# TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
-machine-$(CONFIG_ARCH_NOMADIK) += nomadik
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_TEGRA) += tegra
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
-machine-$(CONFIG_ARCH_VERSATILE) += versatile
machine-$(CONFIG_ARCH_ZYNQ) += zynq
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
@@ -80,11 +78,11 @@ libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y)
-ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35))
libs-y += arch/arm/imx-common/
endif
else
-ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610))
+ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx7 mx31 mx35 mxs vf610))
libs-y += arch/arm/imx-common/
endif
endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
index 1ef8a36..f5e2103 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
@@ -54,12 +54,12 @@ unsigned int get_hclk_pll_rate(void)
if (fref > 27000000ULL || fref < 1000000ULL)
return 0;
- fout = fref * m_div;
- if (val & CLK_HCLK_PLL_FEEDBACK) {
- fcco = fout;
+ fcco = fref * m_div;
+ fout = fcco;
+ if (val & CLK_HCLK_PLL_FEEDBACK)
+ fcco *= p_div;
+ else
do_div(fout, p_div);
- } else
- fcco = fout * p_div;
if (fcco > 320000000ULL || fcco < 156000000ULL)
return 0;
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index d9fa280..b1c3f8f 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -44,8 +44,7 @@ void lpc32xx_uart_init(unsigned int uart_id)
void lpc32xx_dma_init(void)
{
/* Enable DMA interface */
- writel(DMA_CLK_ENABLE, &clk->dmaclk_ctrl);
-
+ writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl);
}
void lpc32xx_mac_init(void)
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
index e39cdba..be0d14f 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -83,3 +83,37 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_ECC_BCH)
+static int do_switch_ecc(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ if (argc != 2)
+ goto usage;
+
+ if (strncmp(argv[1], "hw", 2) == 0) {
+ /* 1-bit HW ECC */
+ printf("Switching to 1-bit HW ECC\n");
+ fsmc_nand_switch_ecc(1);
+ } else if (strncmp(argv[1], "bch4", 2) == 0) {
+ /* 4-bit SW ECC BCH4 */
+ printf("Switching to 4-bit SW ECC (BCH4)\n");
+ fsmc_nand_switch_ecc(4);
+ } else {
+ goto usage;
+ }
+
+ return 0;
+
+usage:
+ printf("Usage: nandecc %s\n", cmdtp->usage);
+ return 1;
+}
+
+U_BOOT_CMD(
+ nandecc, 2, 0, do_switch_ecc,
+ "switch NAND ECC calculation algorithm",
+ "hw|bch4 - Switch between NAND hardware 1-bit HW and"
+ " 4-bit SW BCH\n"
+);
+#endif
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 6769d8f..c8d1422 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -12,7 +12,7 @@ obj-y += cache_v7.o
obj-y += cpu.o cp15.o
obj-y += syslib.o
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),)
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif
@@ -44,6 +44,7 @@ obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
obj-$(if $(filter mx5,$(SOC)),y) += mx5/
obj-$(CONFIG_MX6) += mx6/
+obj-$(CONFIG_MX7) += mx7/
obj-$(CONFIG_OMAP34XX) += omap3/
obj-$(CONFIG_OMAP44XX) += omap4/
obj-$(CONFIG_OMAP54XX) += omap5/
@@ -51,5 +52,4 @@ obj-$(CONFIG_RMOBILE) += rmobile/
obj-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
-obj-$(CONFIG_U8500) += u8500/
obj-$(CONFIG_VF610) += vf610/
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 8dd95d9..e2eb5f3 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -13,6 +13,8 @@
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
+#include <config.h>
+#include <fsl_wdog.h>
#include "fsl_epu.h"
@@ -354,3 +356,16 @@ void smp_kick_all_cpus(void)
asm volatile("sev");
}
#endif
+
+void reset_cpu(ulong addr)
+{
+ struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+ clrbits_be16(&wdog->wcr, WCR_SRS);
+
+ while (1) {
+ /*
+ * Let the watchdog trigger
+ */
+ }
+}
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 8b0120f..0b02e9e 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -35,19 +35,15 @@ choice
config TARGET_ARISTAINETOS
bool "aristainetos"
- select CPU_V7
config TARGET_ARISTAINETOS2
bool "aristainetos2"
- select CPU_V7
config TARGET_ARISTAINETOS2B
bool "Support aristainetos2-revB"
- select CPU_V7
config TARGET_CGTQMX6EVAL
bool "cgtqmx6eval"
- select CPU_V7
config TARGET_CM_FX6
bool "CM-FX6"
@@ -58,77 +54,70 @@ config TARGET_CM_FX6
config TARGET_EMBESTMX6BOARDS
bool "embestmx6boards"
- select CPU_V7
config TARGET_GW_VENTANA
bool "gw_ventana"
- select CPU_V7
select SUPPORT_SPL
config TARGET_KOSAGI_NOVENA
bool "Kosagi Novena"
- select CPU_V7
select SUPPORT_SPL
config TARGET_MX6CUBOXI
bool "Solid-run mx6 boards"
- select CPU_V7
select SUPPORT_SPL
config TARGET_MX6QARM2
bool "mx6qarm2"
- select CPU_V7
config TARGET_MX6QSABREAUTO
bool "mx6qsabreauto"
- select CPU_V7
select DM
select DM_THERMAL
config TARGET_MX6SABRESD
bool "mx6sabresd"
- select CPU_V7
select SUPPORT_SPL
select DM
select DM_THERMAL
config TARGET_MX6SLEVK
bool "mx6slevk"
- select CPU_V7
select SUPPORT_SPL
config TARGET_MX6SXSABRESD
bool "mx6sxsabresd"
- select CPU_V7
select SUPPORT_SPL
select DM
select DM_THERMAL
+config TARGET_MX6UL_9X9_EVK
+ bool "mx6ul_9x9_evk"
+ select MX6UL
+ select DM
+ select DM_THERMAL
+ select SUPPORT_SPL
+
config TARGET_MX6UL_14X14_EVK
bool "mx6ul_14x14_evk"
select MX6UL
- select CPU_V7
select DM
select DM_THERMAL
select SUPPORT_SPL
config TARGET_NITROGEN6X
bool "nitrogen6x"
- select CPU_V7
config TARGET_OT1200
bool "Bachmann OT1200"
- select CPU_V7
select SUPPORT_SPL
config TARGET_PLATINUM_PICON
bool "platinum-picon"
- select CPU_V7
select SUPPORT_SPL
config TARGET_PLATINUM_TITANIUM
bool "platinum-titanium"
- select CPU_V7
select SUPPORT_SPL
config TARGET_SECOMX6
@@ -136,28 +125,23 @@ config TARGET_SECOMX6
config TARGET_TBS2910
bool "TBS2910 Matrix ARM mini PC"
- select CPU_V7
config TARGET_TITANIUM
bool "titanium"
- select CPU_V7
config TARGET_TQMA6
bool "TQ Systems TQMa6 board"
config TARGET_UDOO
bool "udoo"
- select CPU_V7
select SUPPORT_SPL
config TARGET_WANDBOARD
bool "wandboard"
- select CPU_V7
select SUPPORT_SPL
config TARGET_WARP
bool "WaRP"
- select CPU_V7
endchoice
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ba6cc75..11efd12 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -535,6 +535,8 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
if (freq < ENET_25MHZ || freq > ENET_125MHZ)
return -EINVAL;
+ reg = readl(&anatop->pll_enet);
+
if (fec_id == 0) {
reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index cf5587b..6b039e4 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -702,8 +702,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
txs = DIV_ROUND_UP(170000, clkper) - 1;
break;
case 4: /* 4Gb per chip */
- trfc = DIV_ROUND_UP(300000, clkper) - 1;
- txs = DIV_ROUND_UP(310000, clkper) - 1;
+ trfc = DIV_ROUND_UP(260000, clkper) - 1;
+ txs = DIV_ROUND_UP(270000, clkper) - 1;
break;
case 8: /* 8Gb per chip */
trfc = DIV_ROUND_UP(350000, clkper) - 1;
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 8ad8da8..282302b 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -8,9 +8,6 @@
*/
#include <common.h>
-#include <asm/armv7.h>
-#include <asm/bootm.h>
-#include <asm/pl310.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
@@ -38,7 +35,7 @@ struct scu_regs {
u32 fpga_rev;
};
-#if defined(CONFIG_IMX6_THERMAL)
+#if defined(CONFIG_IMX_THERMAL)
static const struct imx_thermal_plat imx6_thermal_plat = {
.regs = (void *)ANATOP_BASE_ADDR,
.fuse_bank = 1,
@@ -186,65 +183,6 @@ u32 __weak get_board_rev(void)
}
#endif
-void init_aips(void)
-{
- struct aipstz_regs *aips1, *aips2;
-#ifdef CONFIG_MX6SX
- struct aipstz_regs *aips3;
-#endif
-
- aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
- aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
-#ifdef CONFIG_MX6SX
- aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
-#endif
-
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- writel(0x77777777, &aips1->mprot0);
- writel(0x77777777, &aips1->mprot1);
- writel(0x77777777, &aips2->mprot0);
- writel(0x77777777, &aips2->mprot1);
-
- /*
- * Set all OPACRx to be non-bufferable, not require
- * supervisor privilege level for access,allow for
- * write access and untrusted master access.
- */
- writel(0x00000000, &aips1->opacr0);
- writel(0x00000000, &aips1->opacr1);
- writel(0x00000000, &aips1->opacr2);
- writel(0x00000000, &aips1->opacr3);
- writel(0x00000000, &aips1->opacr4);
- writel(0x00000000, &aips2->opacr0);
- writel(0x00000000, &aips2->opacr1);
- writel(0x00000000, &aips2->opacr2);
- writel(0x00000000, &aips2->opacr3);
- writel(0x00000000, &aips2->opacr4);
-
-#ifdef CONFIG_MX6SX
- /*
- * Set all MPROTx to be non-bufferable, trusted for R/W,
- * not forced to user-mode.
- */
- writel(0x77777777, &aips3->mprot0);
- writel(0x77777777, &aips3->mprot1);
-
- /*
- * Set all OPACRx to be non-bufferable, not require
- * supervisor privilege level for access,allow for
- * write access and untrusted master access.
- */
- writel(0x00000000, &aips3->opacr0);
- writel(0x00000000, &aips3->opacr1);
- writel(0x00000000, &aips3->opacr2);
- writel(0x00000000, &aips3->opacr3);
- writel(0x00000000, &aips3->opacr4);
-#endif
-}
-
static void clear_ldo_ramp(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
@@ -312,20 +250,6 @@ static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
return 0;
}
-static void imx_set_wdog_powerdown(bool enable)
-{
- struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
- struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
- struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
-
- if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
- writew(enable, &wdog3->wmcr);
-
- /* Write to the PDE (Power Down Enable) bit */
- writew(enable, &wdog1->wmcr);
- writew(enable, &wdog2->wmcr);
-}
-
static void set_ahb_rate(u32 val)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -378,22 +302,6 @@ static void set_preclk_from_osc(void)
}
#endif
-#define SRC_SCR_WARM_RESET_ENABLE 0
-
-static void init_src(void)
-{
- struct src *src_regs = (struct src *)SRC_BASE_ADDR;
- u32 val;
-
- /*
- * force warm reset sources to generate cold reset
- * for a more reliable restart
- */
- val = readl(&src_regs->scr);
- val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
- writel(val, &src_regs->scr);
-}
-
int arch_cpu_init(void)
{
init_aips();
@@ -440,31 +348,6 @@ int board_postclk_init(void)
return 0;
}
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
- enum dcache_option option = DCACHE_WRITETHROUGH;
-#else
- enum dcache_option option = DCACHE_WRITEBACK;
-#endif
-
- /* Avoid random hang when download by usb */
- invalidate_dcache_all();
-
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-
- /* Enable caching on OCRAM and ROM */
- mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
- ROMCP_ARB_END_ADDR,
- option);
- mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
- IRAM_SIZE,
- option);
-}
-#endif
-
#if defined(CONFIG_FEC_MXC)
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
@@ -486,18 +369,6 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
}
#endif
-void boot_mode_apply(unsigned cfg_val)
-{
- unsigned reg;
- struct src *psrc = (struct src *)SRC_BASE_ADDR;
- writel(cfg_val, &psrc->gpr9);
- reg = readl(&psrc->gpr10);
- if (cfg_val)
- reg |= 1 << 28;
- else
- reg &= ~(1 << 28);
- writel(reg, &psrc->gpr10);
-}
/*
* cfg_val will be used for
* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
@@ -605,70 +476,3 @@ void imx_setup_hdmi(void)
writel(reg, &mxc_ccm->chsccdr);
}
#endif
-
-#ifndef CONFIG_SYS_L2CACHE_OFF
-#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
-void v7_outer_cache_enable(void)
-{
- struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
- unsigned int val;
-
-
- /*
- * Set bit 22 in the auxiliary control register. If this bit
- * is cleared, PL310 treats Normal Shared Non-cacheable
- * accesses as Cacheable no-allocate.
- */
- setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
-
-#if defined CONFIG_MX6SL
- struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
- val = readl(&iomux->gpr[11]);
- if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
- /* L2 cache configured as OCRAM, reset it */
- val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
- writel(val, &iomux->gpr[11]);
- }
-#endif
-
- /* Must disable the L2 before changing the latency parameters */
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
- writel(0x132, &pl310->pl310_tag_latency_ctrl);
- writel(0x132, &pl310->pl310_data_latency_ctrl);
-
- val = readl(&pl310->pl310_prefetch_ctrl);
-
- /* Turn on the L2 I/D prefetch */
- val |= 0x30000000;
-
- /*
- * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
- * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
- * But according to ARM PL310 errata: 752271
- * ID: 752271: Double linefill feature can cause data corruption
- * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
- * Workaround: The only workaround to this erratum is to disable the
- * double linefill feature. This is the default behavior.
- */
-
-#ifndef CONFIG_MX6Q
- val |= 0x40800000;
-#endif
- writel(val, &pl310->pl310_prefetch_ctrl);
-
- val = readl(&pl310->pl310_power_ctrl);
- val |= L2X0_DYNAMIC_CLK_GATING_EN;
- val |= L2X0_STNDBY_MODE_EN;
- writel(val, &pl310->pl310_power_ctrl);
-
- setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
-
-void v7_outer_cache_disable(void)
-{
- struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
-
- clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
-#endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig
new file mode 100644
index 0000000..ea19e5c
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx7/Kconfig
@@ -0,0 +1,26 @@
+if ARCH_MX7
+
+config MX7
+ bool
+ default y
+
+config MX7D
+ bool
+
+choice
+ prompt "MX7 board select"
+ optional
+
+config TARGET_MX7DSABRESD
+ bool "mx7dsabresd"
+ select DM
+ select DM_THERMAL
+
+endchoice
+
+config SYS_SOC
+ default "mx7"
+
+source "board/freescale/mx7dsabresd/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/armv7/mx7/Makefile b/arch/arm/cpu/armv7/mx7/Makefile
new file mode 100644
index 0000000..e6ecef0
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx7/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2015 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+#
+
+obj-y := soc.o clock.o clock_slice.o
diff --git a/arch/arm/cpu/armv7/mx7/clock.c b/arch/arm/cpu/armv7/mx7/clock.c
new file mode 100644
index 0000000..77db6e8
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx7/clock.c
@@ -0,0 +1,1127 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ * Peng Fan <Peng.Fan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
+ ANATOP_BASE_ADDR;
+struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#else
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+#endif
+ return 0;
+}
+
+u32 get_ahb_clk(void)
+{
+ return get_root_clk(AHB_CLK_ROOT);
+}
+
+static u32 get_ipg_clk(void)
+{
+ /*
+ * The AHB and IPG are fixed at 2:1 ratio, and synchronized to
+ * each other.
+ */
+ return get_ahb_clk() / 2;
+}
+
+u32 imx_get_uartclk(void)
+{
+ return get_root_clk(UART1_CLK_ROOT);
+}
+
+u32 imx_get_fecclk(void)
+{
+ return get_root_clk(ENET_AXI_CLK_ROOT);
+}
+
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable)
+{
+ clock_enable(CCGR_OCOTP, enable);
+}
+
+void enable_thermal_clk(void)
+{
+ enable_ocotp_clk(1);
+}
+#endif
+
+void enable_usboh3_clk(unsigned char enable)
+{
+ u32 target;
+
+ if (enable) {
+ /* disable the clock gate first */
+ clock_enable(CCGR_USB_HSIC, 0);
+
+ /* 120Mhz */
+ target = CLK_ROOT_ON |
+ USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(USB_HSIC_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_USB_CTRL, 1);
+ clock_enable(CCGR_USB_HSIC, 1);
+ clock_enable(CCGR_USB_PHY1, 1);
+ clock_enable(CCGR_USB_PHY2, 1);
+ } else {
+ clock_enable(CCGR_USB_CTRL, 0);
+ clock_enable(CCGR_USB_HSIC, 0);
+ clock_enable(CCGR_USB_PHY1, 0);
+ clock_enable(CCGR_USB_PHY2, 0);
+ }
+}
+
+static u32 decode_pll(enum pll_clocks pll, u32 infreq)
+{
+ u32 reg, div_sel;
+ u32 num, denom;
+
+ /*
+ * Alought there are four choices for the bypass src,
+ * we choose OSC_24M which is the default set in ROM.
+ */
+ switch (pll) {
+ case PLL_CORE:
+ reg = readl(&ccm_anatop->pll_arm);
+
+ if (reg & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
+ return 0;
+
+ if (reg & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
+ return MXC_HCLK;
+
+ div_sel = (reg & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
+ CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT;
+
+ return (infreq * div_sel) / 2;
+
+ case PLL_SYS:
+ reg = readl(&ccm_anatop->pll_480);
+
+ if (reg & CCM_ANALOG_PLL_480_POWERDOWN_MASK)
+ return 0;
+
+ if (reg & CCM_ANALOG_PLL_480_BYPASS_MASK)
+ return MXC_HCLK;
+
+ if (((reg & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) >>
+ CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT) == 0)
+ return 480000000u;
+ else
+ return 528000000u;
+
+ case PLL_ENET:
+ reg = readl(&ccm_anatop->pll_enet);
+
+ if (reg & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
+ return 0;
+
+ if (reg & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
+ return MXC_HCLK;
+
+ return 1000000000u;
+
+ case PLL_DDR:
+ reg = readl(&ccm_anatop->pll_ddr);
+
+ if (reg & CCM_ANALOG_PLL_DDR_POWERDOWN_MASK)
+ return 0;
+
+ num = ccm_anatop->pll_ddr_num;
+ denom = ccm_anatop->pll_ddr_denom;
+
+ if (reg & CCM_ANALOG_PLL_DDR_BYPASS_MASK)
+ return MXC_HCLK;
+
+ div_sel = (reg & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK) >>
+ CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT;
+
+ return infreq * (div_sel + num / denom);
+
+ case PLL_USB:
+ return 480000000u;
+
+ default:
+ printf("Unsupported pll clocks %d\n", pll);
+ break;
+ }
+
+ return 0;
+}
+
+static u32 mxc_get_pll_sys_derive(int derive)
+{
+ u32 freq, div, frac;
+ u32 reg;
+
+ div = 1;
+ reg = readl(&ccm_anatop->pll_480);
+ freq = decode_pll(PLL_SYS, MXC_HCLK);
+
+ switch (derive) {
+ case PLL_SYS_MAIN_480M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK)
+ return 0;
+ else
+ return freq;
+ case PLL_SYS_MAIN_240M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK)
+ return 0;
+ else
+ return freq / 2;
+ case PLL_SYS_MAIN_120M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK)
+ return 0;
+ else
+ return freq / 4;
+ case PLL_SYS_PFD0_392M_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD0_196M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK)
+ return 0;
+ reg = readl(&ccm_anatop->pfd_480a);
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT;
+ div = 2;
+ break;
+ case PLL_SYS_PFD1_332M_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD1_166M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK)
+ return 0;
+ reg = readl(&ccm_anatop->pfd_480a);
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT;
+ div = 2;
+ break;
+ case PLL_SYS_PFD2_270M_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD2_135M_CLK:
+ if (reg & CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK)
+ return 0;
+ reg = readl(&ccm_anatop->pfd_480a);
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT;
+ div = 2;
+ break;
+ case PLL_SYS_PFD3_CLK:
+ reg = readl(&ccm_anatop->pfd_480a);
+ if (reg & CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD4_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD5_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD6_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT;
+ break;
+ case PLL_SYS_PFD7_CLK:
+ reg = readl(&ccm_anatop->pfd_480b);
+ if (reg & CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK)
+ return 0;
+ frac = (reg & CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK) >>
+ CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT;
+ break;
+ default:
+ printf("Error derived pll_sys clock %d\n", derive);
+ return 0;
+ }
+
+ return ((freq / frac) * 18) / div;
+}
+
+static u32 mxc_get_pll_enet_derive(int derive)
+{
+ u32 freq, reg;
+
+ freq = decode_pll(PLL_ENET, MXC_HCLK);
+ reg = readl(&ccm_anatop->pll_enet);
+
+ switch (derive) {
+ case PLL_ENET_MAIN_500M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK)
+ return freq / 2;
+ break;
+ case PLL_ENET_MAIN_250M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK)
+ return freq / 4;
+ break;
+ case PLL_ENET_MAIN_125M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK)
+ return freq / 8;
+ break;
+ case PLL_ENET_MAIN_100M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK)
+ return freq / 10;
+ break;
+ case PLL_ENET_MAIN_50M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK)
+ return freq / 20;
+ break;
+ case PLL_ENET_MAIN_40M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK)
+ return freq / 25;
+ break;
+ case PLL_ENET_MAIN_25M_CLK:
+ if (reg & CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK)
+ return freq / 40;
+ break;
+ default:
+ printf("Error derived pll_enet clock %d\n", derive);
+ break;
+ }
+
+ return 0;
+}
+
+static u32 mxc_get_pll_ddr_derive(int derive)
+{
+ u32 freq, reg;
+
+ freq = decode_pll(PLL_DDR, MXC_HCLK);
+ reg = readl(&ccm_anatop->pll_ddr);
+
+ switch (derive) {
+ case PLL_DRAM_MAIN_1066M_CLK:
+ return freq;
+ case PLL_DRAM_MAIN_533M_CLK:
+ if (reg & CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK)
+ return freq / 2;
+ break;
+ default:
+ printf("Error derived pll_ddr clock %d\n", derive);
+ break;
+ }
+
+ return 0;
+}
+
+static u32 mxc_get_pll_derive(enum pll_clocks pll, int derive)
+{
+ switch (pll) {
+ case PLL_SYS:
+ return mxc_get_pll_sys_derive(derive);
+ case PLL_ENET:
+ return mxc_get_pll_enet_derive(derive);
+ case PLL_DDR:
+ return mxc_get_pll_ddr_derive(derive);
+ default:
+ printf("Error pll.\n");
+ return 0;
+ }
+}
+
+static u32 get_root_src_clk(enum clk_root_src root_src)
+{
+ switch (root_src) {
+ case OSC_24M_CLK:
+ return 24000000u;
+ case PLL_ARM_MAIN_800M_CLK:
+ return decode_pll(PLL_CORE, MXC_HCLK);
+
+ case PLL_SYS_MAIN_480M_CLK:
+ case PLL_SYS_MAIN_240M_CLK:
+ case PLL_SYS_MAIN_120M_CLK:
+ case PLL_SYS_PFD0_392M_CLK:
+ case PLL_SYS_PFD0_196M_CLK:
+ case PLL_SYS_PFD1_332M_CLK:
+ case PLL_SYS_PFD1_166M_CLK:
+ case PLL_SYS_PFD2_270M_CLK:
+ case PLL_SYS_PFD2_135M_CLK:
+ case PLL_SYS_PFD3_CLK:
+ case PLL_SYS_PFD4_CLK:
+ case PLL_SYS_PFD5_CLK:
+ case PLL_SYS_PFD6_CLK:
+ case PLL_SYS_PFD7_CLK:
+ return mxc_get_pll_derive(PLL_SYS, root_src);
+
+ case PLL_ENET_MAIN_500M_CLK:
+ case PLL_ENET_MAIN_250M_CLK:
+ case PLL_ENET_MAIN_125M_CLK:
+ case PLL_ENET_MAIN_100M_CLK:
+ case PLL_ENET_MAIN_50M_CLK:
+ case PLL_ENET_MAIN_40M_CLK:
+ case PLL_ENET_MAIN_25M_CLK:
+ return mxc_get_pll_derive(PLL_ENET, root_src);
+
+ case PLL_DRAM_MAIN_1066M_CLK:
+ case PLL_DRAM_MAIN_533M_CLK:
+ return mxc_get_pll_derive(PLL_DDR, root_src);
+
+ case PLL_AUDIO_MAIN_CLK:
+ return decode_pll(PLL_AUDIO, MXC_HCLK);
+ case PLL_VIDEO_MAIN_CLK:
+ return decode_pll(PLL_VIDEO, MXC_HCLK);
+
+ case PLL_USB_MAIN_480M_CLK:
+ return decode_pll(PLL_USB, MXC_HCLK);
+
+ case REF_1M_CLK:
+ return 1000000;
+ case OSC_32K_CLK:
+ return MXC_CLK32;
+
+ case EXT_CLK_1:
+ case EXT_CLK_2:
+ case EXT_CLK_3:
+ case EXT_CLK_4:
+ printf("No EXT CLK supported??\n");
+ break;
+ };
+
+ return 0;
+}
+
+u32 get_root_clk(enum clk_root_index clock_id)
+{
+ enum clk_root_src root_src;
+ u32 post_podf, pre_podf, auto_podf, root_src_clk;
+ int auto_en;
+
+ if (clock_root_enabled(clock_id) <= 0)
+ return 0;
+
+ if (clock_get_prediv(clock_id, &pre_podf) < 0)
+ return 0;
+
+ if (clock_get_postdiv(clock_id, &post_podf) < 0)
+ return 0;
+
+ if (clock_get_autopostdiv(clock_id, &auto_podf, &auto_en) < 0)
+ return 0;
+
+ if (auto_en == 0)
+ auto_podf = 0;
+
+ if (clock_get_src(clock_id, &root_src) < 0)
+ return 0;
+
+ root_src_clk = get_root_src_clk(root_src);
+
+ /*
+ * bypass clk is ignored.
+ */
+
+ return root_src_clk / (post_podf + 1) / (pre_podf + 1) /
+ (auto_podf + 1);
+}
+
+static u32 get_ddrc_clk(void)
+{
+ u32 reg, freq;
+ enum root_post_div post_div;
+
+ reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root);
+ if (reg & CLK_ROOT_MUX_MASK)
+ /* DRAM_ALT_CLK_ROOT */
+ freq = get_root_clk(DRAM_ALT_CLK_ROOT);
+ else
+ /* PLL_DRAM_MAIN_1066M_CLK */
+ freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK);
+
+ post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK;
+
+ return freq / (post_div + 1) / 2;
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+ switch (clk) {
+ case MXC_ARM_CLK:
+ return get_root_clk(ARM_A7_CLK_ROOT);
+ case MXC_AXI_CLK:
+ return get_root_clk(MAIN_AXI_CLK_ROOT);
+ case MXC_AHB_CLK:
+ return get_root_clk(AHB_CLK_ROOT);
+ case MXC_IPG_CLK:
+ return get_ipg_clk();
+ case MXC_I2C_CLK:
+ return get_root_clk(I2C1_CLK_ROOT);
+ case MXC_UART_CLK:
+ return get_root_clk(UART1_CLK_ROOT);
+ case MXC_CSPI_CLK:
+ return get_root_clk(ECSPI1_CLK_ROOT);
+ case MXC_DDR_CLK:
+ return get_ddrc_clk();
+ case MXC_ESDHC_CLK:
+ return get_root_clk(USDHC1_CLK_ROOT);
+ case MXC_ESDHC2_CLK:
+ return get_root_clk(USDHC2_CLK_ROOT);
+ case MXC_ESDHC3_CLK:
+ return get_root_clk(USDHC3_CLK_ROOT);
+ default:
+ printf("Unsupported mxc_clock %d\n", clk);
+ break;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_SYS_I2C_MXC
+/* i2c_num can be 0 - 3 */
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
+{
+ u32 target;
+
+ if (i2c_num >= 4)
+ return -EINVAL;
+
+ if (enable) {
+ clock_enable(CCGR_I2C1 + i2c_num, 0);
+
+ /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */
+
+ target = CLK_ROOT_ON |
+ I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(I2C1_CLK_ROOT + i2c_num, target);
+
+ clock_enable(CCGR_I2C1 + i2c_num, 1);
+ } else {
+ clock_enable(CCGR_I2C1 + i2c_num, 0);
+ }
+
+ return 0;
+}
+#endif
+
+static void init_clk_esdhc(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_USDHC1, 0);
+ clock_enable(CCGR_USDHC2, 0);
+ clock_enable(CCGR_USDHC3, 0);
+
+ /* 196: 392/2 */
+ target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(USDHC1_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(USDHC2_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(USDHC3_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_USDHC1, 1);
+ clock_enable(CCGR_USDHC2, 1);
+ clock_enable(CCGR_USDHC3, 1);
+}
+
+static void init_clk_uart(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_UART1, 0);
+ clock_enable(CCGR_UART2, 0);
+ clock_enable(CCGR_UART3, 0);
+ clock_enable(CCGR_UART4, 0);
+ clock_enable(CCGR_UART5, 0);
+ clock_enable(CCGR_UART6, 0);
+ clock_enable(CCGR_UART7, 0);
+
+ /* 24Mhz */
+ target = CLK_ROOT_ON | UART1_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART1_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART2_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART2_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART3_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART3_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART4_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART4_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART5_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART5_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART6_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART6_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | UART7_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(UART7_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_UART1, 1);
+ clock_enable(CCGR_UART2, 1);
+ clock_enable(CCGR_UART3, 1);
+ clock_enable(CCGR_UART4, 1);
+ clock_enable(CCGR_UART5, 1);
+ clock_enable(CCGR_UART6, 1);
+ clock_enable(CCGR_UART7, 1);
+}
+
+static void init_clk_weim(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_WEIM, 0);
+
+ /* 120Mhz */
+ target = CLK_ROOT_ON | EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(EIM_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_WEIM, 1);
+}
+
+static void init_clk_ecspi(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_ECSPI1, 0);
+ clock_enable(CCGR_ECSPI2, 0);
+ clock_enable(CCGR_ECSPI3, 0);
+ clock_enable(CCGR_ECSPI4, 0);
+
+ /* 60Mhz: 240/4 */
+ target = CLK_ROOT_ON | ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI1_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI2_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI3_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ECSPI4_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_ECSPI1, 1);
+ clock_enable(CCGR_ECSPI2, 1);
+ clock_enable(CCGR_ECSPI3, 1);
+ clock_enable(CCGR_ECSPI4, 1);
+}
+
+static void init_clk_wdog(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_WDOG1, 0);
+ clock_enable(CCGR_WDOG2, 0);
+ clock_enable(CCGR_WDOG3, 0);
+ clock_enable(CCGR_WDOG4, 0);
+
+ /* 24Mhz */
+ target = CLK_ROOT_ON | WDOG_CLK_ROOT_FROM_OSC_24M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(WDOG_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_WDOG1, 1);
+ clock_enable(CCGR_WDOG2, 1);
+ clock_enable(CCGR_WDOG3, 1);
+ clock_enable(CCGR_WDOG4, 1);
+}
+
+#ifdef CONFIG_MXC_EPDC
+static void init_clk_epdc(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_EPDC, 0);
+
+ /* 24Mhz */
+ target = CLK_ROOT_ON | EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV12);
+ clock_set_target_val(EPDC_PIXEL_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_EPDC, 1);
+}
+#endif
+
+static int enable_pll_enet(void)
+{
+ u32 reg;
+ s32 timeout = 100000;
+
+ reg = readl(&ccm_anatop->pll_enet);
+ /* If pll_enet powered up, no need to set it again */
+ if (reg & ANADIG_PLL_ENET_PWDN_MASK) {
+ reg &= ~ANADIG_PLL_ENET_PWDN_MASK;
+ writel(reg, &ccm_anatop->pll_enet);
+
+ while (timeout--) {
+ if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK)
+ break;
+ }
+
+ if (timeout <= 0) {
+ /* If timeout, we set pwdn for pll_enet. */
+ reg |= ANADIG_PLL_ENET_PWDN_MASK;
+ return -ETIME;
+ }
+ }
+
+ /* Clear bypass */
+ writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr);
+
+ writel((CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK
+ | CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK),
+ &ccm_anatop->pll_enet_set);
+
+ return 0;
+}
+static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
+ u32 post_div)
+{
+ u32 reg = 0;
+ ulong start;
+
+ debug("pll5 div = %d, num = %d, denom = %d\n",
+ pll_div, pll_num, pll_denom);
+
+ /* Power up PLL5 video and disable its output */
+ writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK |
+ CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK,
+ &ccm_anatop->pll_video_clr);
+
+ /* Set div, num and denom */
+ switch (post_div) {
+ case 1:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x1) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 2:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 3:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x1),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 4:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x0) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x3),
+ &ccm_anatop->pll_video_set);
+ break;
+ case 0:
+ default:
+ writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) |
+ CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(0x2) |
+ CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(0x0),
+ &ccm_anatop->pll_video_set);
+ break;
+ }
+
+ writel(CCM_ANALOG_PLL_VIDEO_NUM_A(pll_num),
+ &ccm_anatop->pll_video_num);
+
+ writel(CCM_ANALOG_PLL_VIDEO_DENOM_B(pll_denom),
+ &ccm_anatop->pll_video_denom);
+
+ /* Wait PLL5 lock */
+ start = get_timer(0); /* Get current timestamp */
+
+ do {
+ reg = readl(&ccm_anatop->pll_video);
+ if (reg & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) {
+ /* Enable PLL out */
+ writel(CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK,
+ &ccm_anatop->pll_video_set);
+ return 0;
+ }
+ } while (get_timer(0) < (start + 10)); /* Wait 10ms */
+
+ printf("Lock PLL5 timeout\n");
+
+ return 1;
+}
+
+int set_clk_qspi(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_QSPI, 0);
+
+ /* 49M: 392/2/4 */
+ target = CLK_ROOT_ON | QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(QSPI_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_QSPI, 1);
+
+ return 0;
+}
+
+int set_clk_nand(void)
+{
+ u32 target;
+
+ /* disable the clock gate first */
+ clock_enable(CCGR_RAWNAND, 0);
+
+ enable_pll_enet();
+ /* 100: 500/5 */
+ target = CLK_ROOT_ON | NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV5);
+ clock_set_target_val(NAND_CLK_ROOT, target);
+
+ /* enable the clock gate */
+ clock_enable(CCGR_RAWNAND, 1);
+
+ return 0;
+}
+
+void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq)
+{
+ u32 hck = MXC_HCLK/1000;
+ u32 min = hck * 27;
+ u32 max = hck * 54;
+ u32 temp, best = 0;
+ u32 i, j, pred = 1, postd = 1;
+ u32 pll_div, pll_num, pll_denom, post_div = 0;
+ u32 target;
+
+ debug("mxs_set_lcdclk, freq = %d\n", freq);
+
+ clock_enable(CCGR_LCDIF, 0);
+
+ temp = (freq * 8 * 8);
+ if (temp < min) {
+ for (i = 1; i <= 4; i++) {
+ if ((temp * (1 << i)) > min) {
+ post_div = i;
+ freq = (freq * (1 << i));
+ break;
+ }
+ }
+
+ if (5 == i) {
+ printf("Fail to set rate to %dkhz", freq);
+ return;
+ }
+ }
+
+ for (i = 1; i <= 8; i++) {
+ for (j = 1; j <= 8; j++) {
+ temp = freq * i * j;
+ if (temp > max || temp < min)
+ continue;
+
+ if (best == 0 || temp < best) {
+ best = temp;
+ pred = i;
+ postd = j;
+ }
+ }
+ }
+
+ if (best == 0) {
+ printf("Fail to set rate to %dkhz", freq);
+ return;
+ }
+
+ debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
+
+ pll_div = best / hck;
+ pll_denom = 1000000;
+ pll_num = (best - hck * pll_div) * pll_denom / hck;
+
+ if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
+ return;
+
+ target = CLK_ROOT_ON | LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK |
+ CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1));
+ clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, target);
+
+ clock_enable(CCGR_LCDIF, 1);
+}
+
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type)
+{
+ u32 target;
+ int ret;
+ u32 enet1_ref, enet2_ref;
+
+ /* disable the clock first */
+ clock_enable(CCGR_ENET1, 0);
+ clock_enable(CCGR_ENET2, 0);
+
+ switch (type) {
+ case ENET_125MHz:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+ enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
+ break;
+ case ENET_50MHz:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+ enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
+ break;
+ case ENET_25MHz:
+ enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+ enet2_ref = ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ ret = enable_pll_enet();
+ if (ret != 0)
+ return ret;
+
+ /* set enet axi clock 196M: 392/2 */
+ target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2);
+ clock_set_target_val(ENET_AXI_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | enet1_ref |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET1_REF_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ENET1_TIME_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | enet2_ref |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET2_REF_CLK_ROOT, target);
+
+ target = CLK_ROOT_ON | ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
+ clock_set_target_val(ENET2_TIME_CLK_ROOT, target);
+
+#ifdef CONFIG_FEC_MXC_25M_REF_CLK
+ target = CLK_ROOT_ON |
+ ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK |
+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
+ CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
+ clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target);
+#endif
+ /* enable clock */
+ clock_enable(CCGR_ENET1, 1);
+ clock_enable(CCGR_ENET2, 1);
+
+ return 0;
+}
+#endif
+
+/* Configure PLL/PFD freq */
+void clock_init(void)
+{
+/* Rom has enabled PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
+ * In u-boot, we have to:
+ * 1. Configure PFD3- PFD7 for freq we needed in u-boot
+ * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate
+ * interface. The clocks for these peripherals are enabled after this intialization.
+ * 3. Other peripherals with set clock rate interface does not be set in this function.
+ */
+ u32 reg;
+
+ /*
+ * Configure PFD4 to 392M
+ * 480M * 18 / 0x16 = 392M
+ */
+ reg = readl(&ccm_anatop->pfd_480b);
+
+ reg &= ~(ANATOP_PFD480B_PFD4_FRAC_MASK |
+ CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK);
+ reg |= ANATOP_PFD480B_PFD4_FRAC_392M_VAL;
+
+ writel(reg, &ccm_anatop->pfd_480b);
+
+ init_clk_esdhc();
+ init_clk_uart();
+ init_clk_weim();
+ init_clk_ecspi();
+ init_clk_wdog();
+#ifdef CONFIG_MXC_EPDC
+ init_clk_epdc();
+#endif
+
+ enable_usboh3_clk(1);
+
+ clock_enable(CCGR_SNVS, 1);
+
+#ifdef CONFIG_NAND_MXS
+ clock_enable(CCGR_RAWNAND, 1);
+#endif
+}
+
+#ifdef CONFIG_SECURE_BOOT
+void hab_caam_clock_enable(unsigned char enable)
+{
+ if (enable)
+ clock_enable(CCGR_CAAM, 1);
+ else
+ clock_enable(CCGR_CAAM, 0);
+}
+#endif
+
+#ifdef CONFIG_MXC_EPDC
+void epdc_clock_enable(void)
+{
+ clock_enable(CCGR_EPDC, 1);
+}
+void epdc_clock_disable(void)
+{
+ clock_enable(CCGR_EPDC, 0);
+}
+#endif
+
+/*
+ * Dump some core clockes.
+ */
+int do_mx7_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u32 freq;
+ freq = decode_pll(PLL_CORE, MXC_HCLK);
+ printf("PLL_CORE %8d MHz\n", freq / 1000000);
+ freq = decode_pll(PLL_SYS, MXC_HCLK);
+ printf("PLL_SYS %8d MHz\n", freq / 1000000);
+ freq = decode_pll(PLL_ENET, MXC_HCLK);
+ printf("PLL_NET %8d MHz\n", freq / 1000000);
+
+ printf("\n");
+
+ printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
+ printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
+#ifdef CONFIG_MXC_SPI
+ printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
+ printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
+ printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
+ printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
+ printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
+ printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
+ printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clocks, CONFIG_SYS_MAXARGS, 1, do_mx7_showclocks,
+ "display clocks",
+ ""
+);
diff --git a/arch/arm/cpu/armv7/mx7/clock_slice.c b/arch/arm/cpu/armv7/mx7/clock_slice.c
new file mode 100644
index 0000000..ad5d504
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx7/clock_slice.c
@@ -0,0 +1,757 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ * Peng Fan <Peng.Fan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <div64.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+static struct clk_root_map root_array[] = {
+ {ARM_A7_CLK_ROOT, CCM_CORE_CHANNEL,
+ {OSC_24M_CLK, PLL_ARM_MAIN_800M_CLK, PLL_ENET_MAIN_500M_CLK,
+ PLL_DRAM_MAIN_1066M_CLK, PLL_SYS_MAIN_480M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ARM_M4_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_250M_CLK,
+ PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ARM_M0_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_125M_CLK,
+ PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {MAIN_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD5_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {DISP_AXI_CLK_ROOT, CCM_BUS_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK,
+ PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {ENET_AXI_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK}
+ },
+ {NAND_USDHC_BUS_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_PFD6_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK}
+ },
+ {AHB_CLK_ROOT, CCM_AHB_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
+ PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {DRAM_PHYM_CLK_ROOT, CCM_DRAM_PHYM_CHANNEL,
+ {PLL_DRAM_MAIN_1066M_CLK, DRAM_PHYM_ALT_CLK_ROOT}
+ },
+ {DRAM_CLK_ROOT, CCM_DRAM_CHANNEL,
+ {PLL_DRAM_MAIN_1066M_CLK, DRAM_ALT_CLK_ROOT}
+ },
+ {DRAM_PHYM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD7_CLK,
+ PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {DRAM_ALT_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_MAIN_480M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_ENET_MAIN_250M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_AUDIO_MAIN_CLK, PLL_SYS_PFD2_270M_CLK}
+ },
+ {USB_HSIC_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_USB_MAIN_480M_CLK,
+ PLL_SYS_PFD3_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD5_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {PCIE_CTRL_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_250M_CLK, PLL_SYS_MAIN_240M_CLK,
+ PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_SYS_PFD6_CLK}
+ },
+ {PCIE_PHY_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_ENET_MAIN_500M_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+ EXT_CLK_4, PLL_SYS_PFD0_392M_CLK}
+ },
+ {EPDC_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD1_332M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD6_CLK,
+ PLL_SYS_PFD7_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {LCDIF_PIXEL_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_DRAM_MAIN_533M_CLK,
+ EXT_CLK_3, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {MIPI_DSI_EXTSER_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD5_CLK, PLL_SYS_PFD3_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
+ },
+ {MIPI_CSI_WARP_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD3_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD0_196M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_AUDIO_MAIN_CLK}
+ },
+ {MIPI_DPHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_PFD5_CLK, REF_1M_CLK, EXT_CLK_2,
+ PLL_VIDEO_MAIN_CLK, EXT_CLK_3}
+ },
+ {SAI1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
+ },
+ {SAI2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_2}
+ },
+ {SAI3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
+ },
+ {SPDIF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_125M_CLK, EXT_CLK_3}
+ },
+ {ENET1_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
+ },
+ {ENET1_TIME_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+ EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
+ },
+ {ENET2_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_ENET_MAIN_25M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, EXT_CLK_4}
+ },
+ {ENET2_TIME_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_AUDIO_MAIN_CLK,
+ EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+ EXT_CLK_4, PLL_VIDEO_MAIN_CLK}
+ },
+ {ENET_PHY_REF_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_25M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_SYS_PFD3_CLK}
+ },
+ {EIM_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_SYS_PFD3_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {NAND_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_PFD0_392M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {QSPI_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD4_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD3_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {USDHC1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {USDHC2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {USDHC3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD4_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD6_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {CAN1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
+ EXT_CLK_1, EXT_CLK_4}
+ },
+ {CAN2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_SYS_MAIN_480M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_USB_MAIN_480M_CLK,
+ EXT_CLK_1, EXT_CLK_3}
+ },
+ {I2C1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {I2C2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {I2C3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {I2C4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_120M_CLK, PLL_ENET_MAIN_50M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_PFD2_135M_CLK}
+ },
+ {UART1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART5_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART6_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_3, PLL_USB_MAIN_480M_CLK}
+ },
+ {UART7_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_480M_CLK, EXT_CLK_2,
+ EXT_CLK_4, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {ECSPI4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_ENET_MAIN_40M_CLK,
+ PLL_SYS_MAIN_120M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_PFD4_CLK,
+ PLL_ENET_MAIN_250M_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {PWM1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {PWM2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_1,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {PWM3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {PWM4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_2,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {FLEXTIMER1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {FLEXTIMER2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_AUDIO_MAIN_CLK, EXT_CLK_3,
+ REF_1M_CLK, PLL_VIDEO_MAIN_CLK}
+ },
+ {SIM1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {SIM2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_USB_MAIN_480M_CLK, PLL_VIDEO_MAIN_CLK,
+ PLL_ENET_MAIN_125M_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {GPT1_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_1}
+ },
+ {GPT2_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_2}
+ },
+ {GPT3_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_3}
+ },
+ {GPT4_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_100M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_ENET_MAIN_40M_CLK, PLL_VIDEO_MAIN_CLK, REF_1M_CLK,
+ PLL_AUDIO_MAIN_CLK, EXT_CLK_4}
+ },
+ {TRACE_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
+ EXT_CLK_1, EXT_CLK_3}
+ },
+ {WDOG_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK,
+ REF_1M_CLK, PLL_SYS_PFD1_166M_CLK}
+ },
+ {CSI_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {AUDIO_MCLK_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_SYS_MAIN_120M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, PLL_USB_MAIN_480M_CLK}
+ },
+ {WRCLK_CLK_ROOT, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_ENET_MAIN_40M_CLK, PLL_DRAM_MAIN_533M_CLK,
+ PLL_USB_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD2_270M_CLK,
+ PLL_ENET_MAIN_500M_CLK, PLL_SYS_PFD7_CLK}
+ },
+ {IPP_DO_CLKO1, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_480M_CLK, PLL_SYS_MAIN_240M_CLK,
+ PLL_SYS_PFD0_196M_CLK, PLL_SYS_PFD3_CLK, PLL_ENET_MAIN_500M_CLK,
+ PLL_DRAM_MAIN_533M_CLK, REF_1M_CLK}
+ },
+ {IPP_DO_CLKO2, CCM_IP_CHANNEL,
+ {OSC_24M_CLK, PLL_SYS_MAIN_240M_CLK, PLL_SYS_PFD0_392M_CLK,
+ PLL_SYS_PFD1_166M_CLK, PLL_SYS_PFD4_CLK, PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK, OSC_32K_CLK}
+ },
+};
+
+/* select which entry of root_array */
+static int select(enum clk_root_index clock_id)
+{
+ int i, size;
+ struct clk_root_map *p = root_array;
+
+ size = ARRAY_SIZE(root_array);
+
+ for (i = 0; i < size; i++, p++) {
+ if (clock_id == p->entry)
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+static int src_supported(int entry, enum clk_root_src clock_src)
+{
+ int i, size;
+ struct clk_root_map *p = &root_array[entry];
+
+ if ((p->type == CCM_DRAM_PHYM_CHANNEL) || (p->type == CCM_DRAM_CHANNEL))
+ size = 2;
+ else
+ size = 8;
+
+ for (i = 0; i < size; i++) {
+ if (p->src_mux[i] == clock_src)
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+/* Set src for clock root slice. */
+int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src)
+{
+ int root_entry, src_entry;
+ u32 reg;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ src_entry = src_supported(root_entry, clock_src);
+ if (src_entry < 0)
+ return -EINVAL;
+
+ reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ reg &= ~CLK_ROOT_MUX_MASK;
+ reg |= src_entry << CLK_ROOT_MUX_SHIFT;
+ __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+/* Get src of a clock root slice. */
+int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ val &= CLK_ROOT_MUX_MASK;
+ val >>= CLK_ROOT_MUX_SHIFT;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+ *p_clock_src = p->src_mux[val];
+
+ return 0;
+}
+
+int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div)
+{
+ int root_entry;
+ struct clk_root_map *p;
+ u32 reg;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type == CCM_CORE_CHANNEL) ||
+ (p->type == CCM_DRAM_PHYM_CHANNEL) ||
+ (p->type == CCM_DRAM_CHANNEL)) {
+ if (pre_div != CLK_ROOT_PRE_DIV1) {
+ printf("Error pre div!\n");
+ return -EINVAL;
+ }
+ }
+
+ reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ reg &= ~CLK_ROOT_PRE_DIV_MASK;
+ reg |= pre_div << CLK_ROOT_PRE_DIV_SHIFT;
+ __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type == CCM_CORE_CHANNEL) ||
+ (p->type == CCM_DRAM_PHYM_CHANNEL) ||
+ (p->type == CCM_DRAM_CHANNEL)) {
+ *pre_div = 0;
+ return 0;
+ }
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ val &= CLK_ROOT_PRE_DIV_MASK;
+ val >>= CLK_ROOT_PRE_DIV_SHIFT;
+
+ *pre_div = val;
+
+ return 0;
+}
+
+int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div)
+{
+ u32 reg;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ if (clock_id == DRAM_PHYM_CLK_ROOT) {
+ if (div != CLK_ROOT_POST_DIV1) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+ }
+
+ /* Only 3 bit post div. */
+ if ((clock_id == DRAM_CLK_ROOT) && (div > CLK_ROOT_POST_DIV7)) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+
+ reg = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ reg &= ~CLK_ROOT_POST_DIV_MASK;
+ reg |= div << CLK_ROOT_POST_DIV_SHIFT;
+ __raw_writel(reg, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div)
+{
+ u32 val;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ if (clock_id == DRAM_PHYM_CLK_ROOT) {
+ *div = 0;
+ return 0;
+ }
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ if (clock_id == DRAM_CLK_ROOT)
+ val &= DRAM_CLK_ROOT_POST_DIV_MASK;
+ else
+ val &= CLK_ROOT_POST_DIV_MASK;
+ val >>= CLK_ROOT_POST_DIV_SHIFT;
+
+ *div = val;
+
+ return 0;
+}
+
+int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
+ int auto_en)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
+ printf("Auto postdiv not supported.!\n");
+ return -EINVAL;
+ }
+
+ /*
+ * Each time only one filed can be changed, no use target_root_set.
+ */
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ val &= ~CLK_ROOT_AUTO_DIV_MASK;
+ val |= (div << CLK_ROOT_AUTO_DIV_SHIFT);
+
+ if (auto_en)
+ val |= CLK_ROOT_AUTO_EN;
+ else
+ val &= ~CLK_ROOT_AUTO_EN;
+
+ __raw_writel(val, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
+ int *auto_en)
+{
+ u32 val;
+ int root_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ /*
+ * Only bus/ahb channel supports auto div.
+ * If unsupported, just set auto_en and div with 0.
+ */
+ if ((p->type != CCM_BUS_CHANNEL) && (p->type != CCM_AHB_CHANNEL)) {
+ *auto_en = 0;
+ *div = 0;
+ return 0;
+ }
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+ if ((val & CLK_ROOT_AUTO_EN_MASK) == 0)
+ *auto_en = 0;
+ else
+ *auto_en = 1;
+
+ val &= CLK_ROOT_AUTO_DIV_MASK;
+ val >>= CLK_ROOT_AUTO_DIV_SHIFT;
+
+ *div = val;
+
+ return 0;
+}
+
+int clock_get_target_val(enum clk_root_index clock_id, u32 *val)
+{
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ *val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_set_target_val(enum clk_root_index clock_id, u32 val)
+{
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ __raw_writel(val, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+/* Auto_div and auto_en is ignored, they are rarely used. */
+int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
+ enum root_post_div post_div, enum clk_root_src clock_src)
+{
+ u32 val;
+ int root_entry, src_entry;
+ struct clk_root_map *p;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ root_entry = select(clock_id);
+ if (root_entry < 0)
+ return -EINVAL;
+
+ p = &root_array[root_entry];
+
+ if ((p->type == CCM_CORE_CHANNEL) ||
+ (p->type == CCM_DRAM_PHYM_CHANNEL) ||
+ (p->type == CCM_DRAM_CHANNEL)) {
+ if (pre_div != CLK_ROOT_PRE_DIV1) {
+ printf("Error pre div!\n");
+ return -EINVAL;
+ }
+ }
+
+ /* Only 3 bit post div. */
+ if (p->type == CCM_DRAM_CHANNEL) {
+ if (post_div > CLK_ROOT_POST_DIV7) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+ }
+
+ if (p->type == CCM_DRAM_PHYM_CHANNEL) {
+ if (post_div != CLK_ROOT_POST_DIV1) {
+ printf("Error post div!\n");
+ return -EINVAL;
+ }
+ }
+
+ src_entry = src_supported(root_entry, clock_src);
+ if (src_entry < 0)
+ return -EINVAL;
+
+ val = CLK_ROOT_ON | pre_div << CLK_ROOT_PRE_DIV_SHIFT |
+ post_div << CLK_ROOT_POST_DIV_SHIFT |
+ src_entry << CLK_ROOT_MUX_SHIFT;
+
+ __raw_writel(val, &imx_ccm->root[clock_id].target_root);
+
+ return 0;
+}
+
+int clock_root_enabled(enum clk_root_index clock_id)
+{
+ u32 val;
+
+ if (clock_id >= CLK_ROOT_MAX)
+ return -EINVAL;
+
+ /*
+ * No enable bit for DRAM controller and PHY. Just return enabled.
+ */
+ if ((clock_id == DRAM_PHYM_CLK_ROOT) || (clock_id == DRAM_CLK_ROOT))
+ return 1;
+
+ val = __raw_readl(&imx_ccm->root[clock_id].target_root);
+
+ return (val & CLK_ROOT_ENABLE_MASK) ? 1 : 0;
+}
+
+/* CCGR gate operation */
+int clock_enable(enum clk_ccgr_index index, bool enable)
+{
+ if (index >= CCGR_MAX)
+ return -EINVAL;
+
+ if (enable)
+ __raw_writel(CCM_CLK_ON_MSK,
+ &imx_ccm->ccgr_array[index].ccgr_set);
+ else
+ __raw_writel(CCM_CLK_ON_MSK,
+ &imx_ccm->ccgr_array[index].ccgr_clr);
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c
new file mode 100644
index 0000000..2ed05ea
--- /dev/null
+++ b/arch/arm/cpu/armv7/mx7/soc.c
@@ -0,0 +1,267 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/dma.h>
+#include <asm/arch/crm_regs.h>
+#include <dm.h>
+#include <imx_thermal.h>
+
+#if defined(CONFIG_IMX_THERMAL)
+static const struct imx_thermal_plat imx7_thermal_plat = {
+ .regs = (void *)ANATOP_BASE_ADDR,
+ .fuse_bank = 3,
+ .fuse_word = 3,
+};
+
+U_BOOT_DEVICE(imx7_thermal) = {
+ .name = "imx_thermal",
+ .platdata = &imx7_thermal_plat,
+};
+#endif
+
+/*
+ * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_SPEED_SHIFT 8
+#define OCOTP_TESTER3_SPEED_800MHZ 0
+#define OCOTP_TESTER3_SPEED_850MHZ 1
+#define OCOTP_TESTER3_SPEED_1GHZ 2
+
+u32 get_cpu_speed_grade_hz(void)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ uint32_t val;
+
+ val = readl(&fuse->tester3);
+ val >>= OCOTP_TESTER3_SPEED_SHIFT;
+ val &= 0x3;
+
+ switch(val) {
+ case OCOTP_TESTER3_SPEED_800MHZ:
+ return 792000000;
+ case OCOTP_TESTER3_SPEED_850MHZ:
+ return 852000000;
+ case OCOTP_TESTER3_SPEED_1GHZ:
+ return 996000000;
+ }
+ return 0;
+}
+
+/*
+ * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
+ * defines a 2-bit SPEED_GRADING
+ */
+#define OCOTP_TESTER3_TEMP_SHIFT 6
+
+u32 get_cpu_temp_grade(int *minc, int *maxc)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[1];
+ struct fuse_bank1_regs *fuse =
+ (struct fuse_bank1_regs *)bank->fuse_regs;
+ uint32_t val;
+
+ val = readl(&fuse->tester3);
+ val >>= OCOTP_TESTER3_TEMP_SHIFT;
+ val &= 0x3;
+
+ if (minc && maxc) {
+ if (val == TEMP_AUTOMOTIVE) {
+ *minc = -40;
+ *maxc = 125;
+ } else if (val == TEMP_INDUSTRIAL) {
+ *minc = -40;
+ *maxc = 105;
+ } else if (val == TEMP_EXTCOMMERCIAL) {
+ *minc = -20;
+ *maxc = 105;
+ } else {
+ *minc = 0;
+ *maxc = 95;
+ }
+ }
+ return val;
+}
+
+u32 get_cpu_rev(void)
+{
+ struct mxc_ccm_anatop_reg *ccm_anatop = (struct mxc_ccm_anatop_reg *)
+ ANATOP_BASE_ADDR;
+ u32 reg = readl(&ccm_anatop->digprog);
+ u32 type = (reg >> 16) & 0xff;
+
+ reg &= 0xff;
+ return (type << 12) | reg;
+}
+
+#ifdef CONFIG_REVISION_TAG
+u32 __weak get_board_rev(void)
+{
+ return get_cpu_rev();
+}
+#endif
+
+int arch_cpu_init(void)
+{
+ init_aips();
+
+ /* Disable PDE bit of WMCR register */
+ imx_set_wdog_powerdown(false);
+
+#ifdef CONFIG_APBH_DMA
+ /* Start APBH DMA */
+ mxs_dma_init();
+#endif
+
+ return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[0];
+ struct fuse_bank0_regs *fuse =
+ (struct fuse_bank0_regs *)bank->fuse_regs;
+
+ serialnr->low = fuse->tester0;
+ serialnr->high = fuse->tester1;
+}
+#endif
+
+#if defined(CONFIG_FEC_MXC)
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[9];
+ struct fuse_bank9_regs *fuse =
+ (struct fuse_bank9_regs *)bank->fuse_regs;
+
+ if (0 == dev_id) {
+ u32 value = readl(&fuse->mac_addr1);
+ mac[0] = (value >> 8);
+ mac[1] = value;
+
+ value = readl(&fuse->mac_addr0);
+ mac[2] = value >> 24;
+ mac[3] = value >> 16;
+ mac[4] = value >> 8;
+ mac[5] = value;
+ } else {
+ u32 value = readl(&fuse->mac_addr2);
+ mac[0] = value >> 24;
+ mac[1] = value >> 16;
+ mac[2] = value >> 8;
+ mac[3] = value;
+
+ value = readl(&fuse->mac_addr1);
+ mac[4] = value >> 24;
+ mac[5] = value >> 16;
+ }
+}
+#endif
+
+void set_wdog_reset(struct wdog_regs *wdog)
+{
+ u32 reg = readw(&wdog->wcr);
+ /*
+ * Output WDOG_B signal to reset external pmic or POR_B decided by
+ * the board desgin. Without external reset, the peripherals/DDR/
+ * PMIC are not reset, that may cause system working abnormal.
+ */
+ reg = readw(&wdog->wcr);
+ reg |= 1 << 3;
+ /*
+ * WDZST bit is write-once only bit. Align this bit in kernel,
+ * otherwise kernel code will have no chance to set this bit.
+ */
+ reg |= 1 << 0;
+ writew(reg, &wdog->wcr);
+}
+
+/*
+ * cfg_val will be used for
+ * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
+ * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
+ * to SBMR1, which will determine the boot device.
+ */
+const struct boot_mode soc_boot_modes[] = {
+ {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)},
+ {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)},
+ {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)},
+ {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)},
+
+ {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)},
+ {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)},
+ /* 4 bit bus width */
+ {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
+ {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)},
+ {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)},
+ {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)},
+ {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)},
+ {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)},
+ {NULL, 0},
+};
+
+enum boot_device get_boot_device(void)
+{
+ struct bootrom_sw_info **p =
+ (struct bootrom_sw_info **)ROM_SW_INFO_ADDR;
+
+ enum boot_device boot_dev = SD1_BOOT;
+ u8 boot_type = (*p)->boot_dev_type;
+ u8 boot_instance = (*p)->boot_dev_instance;
+
+ switch (boot_type) {
+ case BOOT_TYPE_SD:
+ boot_dev = boot_instance + SD1_BOOT;
+ break;
+ case BOOT_TYPE_MMC:
+ boot_dev = boot_instance + MMC1_BOOT;
+ break;
+ case BOOT_TYPE_NAND:
+ boot_dev = NAND_BOOT;
+ break;
+ case BOOT_TYPE_QSPI:
+ boot_dev = QSPI_BOOT;
+ break;
+ case BOOT_TYPE_WEIM:
+ boot_dev = WEIM_NOR_BOOT;
+ break;
+ case BOOT_TYPE_SPINOR:
+ boot_dev = SPI_NOR_BOOT;
+ break;
+ default:
+ break;
+ }
+
+ return boot_dev;
+}
+
+void s_init(void)
+{
+#if !defined CONFIG_SPL_BUILD
+ /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
+ asm volatile(
+ "mrc p15, 0, r0, c1, c0, 1\n"
+ "orr r0, r0, #1 << 6\n"
+ "mcr p15, 0, r0, c1, c0, 1\n");
+#endif
+ /* clock configuration. */
+ clock_init();
+
+ return;
+}
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 30d81db..31d1c9e 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -53,6 +53,20 @@ _secure_monitor:
bl psci_arch_init
#endif
+#ifdef CONFIG_ARM_ERRATA_773022
+ mrc p15, 0, r5, c1, c0, 1
+ orr r5, r5, #(1 << 1)
+ mcr p15, 0, r5, c1, c0, 1
+ isb
+#endif
+
+#ifdef CONFIG_ARM_ERRATA_774769
+ mrc p15, 0, r5, c1, c0, 1
+ orr r5, r5, #(1 << 25)
+ mcr p15, 0, r5, c1, c0, 1
+ isb
+#endif
+
mrc p15, 0, r5, c1, c1, 0 @ read SCR
bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
orr r5, r5, #0x31 @ enable NS, AW, FW bits
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index f5b22f6..bf7bf26 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -294,8 +294,8 @@ static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
/* Disable refreshed before leveling */
- clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT,
- EMIF_REG_INITREF_DIS_SHIFT);
+ clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
+ EMIF_REG_INITREF_DIS_MASK);
/* Start Full leveling */
writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
@@ -309,7 +309,7 @@ static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
}
/* Enable refreshes after leveling */
- clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT);
+ clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
debug("HW leveling success\n");
/*
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index cda38e1..4fa72f7 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -12,9 +12,6 @@ config TARGET_MT_VENTOUX
bool "TeeJet Mt.Ventoux"
select SUPPORT_SPL
-config TARGET_OMAP3_SDP3430
- bool "TI OMAP3430 SDP"
-
config TARGET_OMAP3_BEAGLE
bool "TI OMAP3 BeagleBoard"
select SUPPORT_SPL
@@ -79,9 +76,6 @@ config TARGET_ECO5PK
bool "ECO5PK"
select SUPPORT_SPL
-config TARGET_DIG297
- bool "DIG297"
-
config TARGET_TRICORDER
bool "Tricorder"
select SUPPORT_SPL
@@ -96,9 +90,6 @@ config TARGET_OMAP3_LOGIC
select DM_SERIAL
select DM_GPIO
-config TARGET_OMAP3_MVBLX
- bool "OMAP3 MVBLX"
-
config TARGET_NOKIA_RX51
bool "Nokia RX51"
@@ -131,7 +122,6 @@ config SYS_SOC
source "board/logicpd/am3517evm/Kconfig"
source "board/teejet/mt_ventoux/Kconfig"
-source "board/ti/sdp3430/Kconfig"
source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
source "board/compulab/cm_t3517/Kconfig"
@@ -143,11 +133,9 @@ source "board/logicpd/zoom1/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/pandora/Kconfig"
source "board/8dtech/eco5pk/Kconfig"
-source "board/comelit/dig297/Kconfig"
source "board/corscience/tricorder/Kconfig"
source "board/htkw/mcx/Kconfig"
source "board/logicpd/omap3som/Kconfig"
-source "board/matrix_vision/mvblx/Kconfig"
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
source "board/technexion/twister/Kconfig"
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig
index ef56286..85c06eb 100644
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ b/arch/arm/cpu/armv7/rmobile/Kconfig
@@ -40,6 +40,11 @@ config TARGET_PORTER
select DM
select DM_SERIAL
+config TARGET_STOUT
+ bool "Stout board"
+ select DM
+ select DM_SERIAL
+
endchoice
config SYS_SOC
@@ -47,7 +52,7 @@ config SYS_SOC
config RMOBILE_EXTRAM_BOOT
bool "Enable boot from RAM"
- depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK
+ depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT
default n
choice
@@ -80,5 +85,6 @@ source "board/kmc/kzm9g/Kconfig"
source "board/renesas/alt/Kconfig"
source "board/renesas/silk/Kconfig"
source "board/renesas/porter/Kconfig"
+source "board/renesas/stout/Kconfig"
endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index b40198b..d11365b 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -21,6 +21,7 @@
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
+#include <asm/arch/spl.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
#include <asm/arch/tzpc.h>
@@ -152,7 +153,7 @@ u32 spl_boot_device(void)
* binary over USB. If it is found, it determines where SPL was
* read from.
*/
- if (readl(4) != 0x4E4F4765 || readl(8) != 0x3054422E) /* eGON.BT0 */
+ if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
return BOOT_DEVICE_BOARD;
/* The BROM will try to boot from mmc0 first, so try that first. */
@@ -198,11 +199,6 @@ void board_init_f(ulong dummy)
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
sunxi_board_init();
-
- /* Clear the BSS. */
- memset(__bss_start, 0, __bss_end - __bss_start);
-
- board_init_r(NULL, 0);
}
#endif
diff --git a/arch/arm/cpu/armv7/u8500/Makefile b/arch/arm/cpu/armv7/u8500/Makefile
deleted file mode 100644
index fad9d4a..0000000
--- a/arch/arm/cpu/armv7/u8500/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := timer.o clock.o prcmu.o cpu.o
-obj-y += lowlevel.o
diff --git a/arch/arm/cpu/armv7/u8500/clock.c b/arch/arm/cpu/armv7/u8500/clock.c
deleted file mode 100644
index 1e3b3d5..0000000
--- a/arch/arm/cpu/armv7/u8500/clock.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * (C) Copyright 2009 ST-Ericsson
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-struct clkrst {
- unsigned int pcken;
- unsigned int pckdis;
- unsigned int kcken;
- unsigned int kckdis;
-};
-
-static unsigned int clkrst_base[] = {
- U8500_CLKRST1_BASE,
- U8500_CLKRST2_BASE,
- U8500_CLKRST3_BASE,
- 0,
- U8500_CLKRST5_BASE,
- U8500_CLKRST6_BASE,
- U8500_CLKRST7_BASE, /* ED only */
-};
-
-/* Turn on peripheral clock at PRCC level */
-void u8500_clock_enable(int periph, int cluster, int kern)
-{
- struct clkrst *clkrst = (struct clkrst *) clkrst_base[periph - 1];
-
- if (kern != -1)
- writel(1 << kern, &clkrst->kcken);
-
- if (cluster != -1)
- writel(1 << cluster, &clkrst->pcken);
-}
-
-void db8500_clocks_init(void)
-{
- /*
- * Enable all clocks. This is u-boot, we can enable it all. There is no
- * powersave in u-boot.
- */
-
- u8500_clock_enable(1, 9, -1); /* GPIO0 */
- u8500_clock_enable(2, 11, -1);/* GPIO1 */
- u8500_clock_enable(3, 8, -1); /* GPIO2 */
- u8500_clock_enable(5, 1, -1); /* GPIO3 */
- u8500_clock_enable(3, 6, 6); /* UART2 */
- u8500_clock_enable(3, 3, 3); /* I2C0 */
- u8500_clock_enable(1, 5, 5); /* SDI0 */
- u8500_clock_enable(2, 4, 2); /* SDI4 */
- u8500_clock_enable(6, 6, -1); /* MTU0 */
- u8500_clock_enable(3, 4, 4); /* SDI2 */
-
- /*
- * Enabling clocks for all devices which are AMBA devices in the
- * kernel. Otherwise they will not get probe()'d because the
- * peripheral ID register will not be powered.
- */
-
- /* XXX: some of these differ between ED/V1 */
-
- u8500_clock_enable(1, 1, 1); /* UART1 */
- u8500_clock_enable(1, 0, 0); /* UART0 */
- u8500_clock_enable(3, 2, 2); /* SSP1 */
- u8500_clock_enable(3, 1, 1); /* SSP0 */
- u8500_clock_enable(2, 8, -1); /* SPI0 */
- u8500_clock_enable(2, 5, 3); /* MSP2 */
-}
diff --git a/arch/arm/cpu/armv7/u8500/cpu.c b/arch/arm/cpu/armv7/u8500/cpu.c
deleted file mode 100644
index d8634be..0000000
--- a/arch/arm/cpu/armv7/u8500/cpu.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * Copyright (C) 2012 Linaro Limited
- * Mathieu Poirier <mathieu.poirier@linaro.org>
- *
- * Based on original code from Joakim Axelsson at ST-Ericsson
- * (C) Copyright 2010 ST-Ericsson
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/prcmu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-
-#include <asm/arch/hardware.h>
-
-#define CPUID_DB8500V1 0x411fc091
-#define CPUID_DB8500V2 0x412fc091
-#define ASICID_DB8500V11 0x008500A1
-
-#define CACHE_CONTR_BASE 0xA0412000
-/* Cache controller register offsets
- * as found in ARM's technical reference manual
- */
-#define CACHE_INVAL_BY_WAY (CACHE_CONTR_BASE + 0x77C)
-#define CACHE_LOCKDOWN_BY_D (CACHE_CONTR_BASE + 0X900)
-#define CACHE_LOCKDOWN_BY_I (CACHE_CONTR_BASE + 0X904)
-
-static unsigned int read_asicid(void);
-
-static inline unsigned int read_cpuid(void)
-{
- unsigned int val;
-
- /* Main ID register (MIDR) */
- asm("mrc p15, 0, %0, c0, c0, 0"
- : "=r" (val)
- :
- : "cc");
-
- return val;
-}
-
-static int cpu_is_u8500v11(void)
-{
- return read_asicid() == ASICID_DB8500V11;
-}
-
-static int cpu_is_u8500v2(void)
-{
- return read_cpuid() == CPUID_DB8500V2;
-}
-
-static unsigned int read_asicid(void)
-{
- unsigned int *address;
-
- if (cpu_is_u8500v2())
- address = (void *) U8500_ASIC_ID_LOC_V2;
- else
- address = (void *) U8500_ASIC_ID_LOC_ED_V1;
-
- return readl(address);
-}
-
-void cpu_cache_initialization(void)
-{
- unsigned int value;
- /* invalidate all cache entries */
- writel(0xFFFF, CACHE_INVAL_BY_WAY);
-
- /* ways are set to '0' when they are totally
- * cleaned and invalidated
- */
- do {
- value = readl(CACHE_INVAL_BY_WAY);
- } while (value & 0xFF);
-
- /* Invalidate register 9 D and I lockdown */
- writel(0xFF, CACHE_LOCKDOWN_BY_D);
- writel(0xFF, CACHE_LOCKDOWN_BY_I);
-}
-
-#ifdef CONFIG_ARCH_CPU_INIT
-/*
- * SOC specific cpu init
- */
-int arch_cpu_init(void)
-{
- db8500_prcmu_init();
- db8500_clocks_init();
-
- return 0;
-}
-#endif /* CONFIG_ARCH_CPU_INIT */
-
-#ifdef CONFIG_MMC
-
-int u8500_mmc_power_init(void)
-{
- int ret;
- int enable, voltage;
- int ab8500_revision;
-
- if (!cpu_is_u8500v11() && !cpu_is_u8500v2())
- return 0;
-
- /* Get AB8500 revision */
- ret = ab8500_read(AB8500_MISC, AB8500_REV_REG);
- if (ret < 0)
- goto out;
-
- ab8500_revision = ret;
-
- /*
- * On v1.1 HREF boards (HREF+), Vaux3 needs to be enabled for the SD
- * card to work. This is done by enabling the regulators in the AB8500
- * via PRCMU I2C transactions.
- *
- * This code is derived from the handling of AB8500_LDO_VAUX3 in
- * ab8500_ldo_enable() and ab8500_ldo_disable() in Linux.
- *
- * Turn off and delay is required to have it work across soft reboots.
- */
-
- /* Turn off (read-modify-write) */
- ret = ab8500_read(AB8500_REGU_CTRL2,
- AB8500_REGU_VRF1VAUX3_REGU_REG);
- if (ret < 0)
- goto out;
-
- enable = ret;
-
- /* Turn off */
- ret = ab8500_write(AB8500_REGU_CTRL2,
- AB8500_REGU_VRF1VAUX3_REGU_REG,
- enable & ~LDO_VAUX3_ENABLE_MASK);
- if (ret < 0)
- goto out;
-
- udelay(10 * 1000);
-
- /* Set the voltage to 2.91 V or 2.9 V without overriding VRF1 value */
- ret = ab8500_read(AB8500_REGU_CTRL2,
- AB8500_REGU_VRF1VAUX3_SEL_REG);
- if (ret < 0)
- goto out;
-
- voltage = ret;
-
- if (ab8500_revision < 0x20) {
- voltage &= ~LDO_VAUX3_SEL_MASK;
- voltage |= LDO_VAUX3_SEL_2V9;
- } else {
- voltage &= ~LDO_VAUX3_V2_SEL_MASK;
- voltage |= LDO_VAUX3_V2_SEL_2V91;
- }
-
- ret = ab8500_write(AB8500_REGU_CTRL2,
- AB8500_REGU_VRF1VAUX3_SEL_REG, voltage);
- if (ret < 0)
- goto out;
-
- /* Turn on the supply */
- enable &= ~LDO_VAUX3_ENABLE_MASK;
- enable |= LDO_VAUX3_ENABLE_VAL;
-
- ret = ab8500_write(AB8500_REGU_CTRL2,
- AB8500_REGU_VRF1VAUX3_REGU_REG, enable);
-
-out:
- return ret;
-}
-#endif /* CONFIG_MMC */
diff --git a/arch/arm/cpu/armv7/u8500/lowlevel.S b/arch/arm/cpu/armv7/u8500/lowlevel.S
deleted file mode 100644
index d3e3920..0000000
--- a/arch/arm/cpu/armv7/u8500/lowlevel.S
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * (C) Copyright 2011 ST-Ericsson
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-
-ENTRY(lowlevel_init)
- mov pc, lr
-ENDPROC(lowlevel_init)
-
- .align 5
-ENTRY(reset_cpu)
- ldr r0, =CFG_PRCMU_BASE
- ldr r1, =0x1
- str r1, [r0, #0x228]
-_loop_forever:
- b _loop_forever
-ENDPROC(reset_cpu)
diff --git a/arch/arm/cpu/armv7/u8500/prcmu.c b/arch/arm/cpu/armv7/u8500/prcmu.c
deleted file mode 100644
index 26ffdc2..0000000
--- a/arch/arm/cpu/armv7/u8500/prcmu.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * Copyright (C) 2009 ST-Ericsson SA
- *
- * Adapted from the Linux version:
- * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * NOTE: This currently does not support the I2C workaround access method.
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/arch/prcmu.h>
-
-/* CPU mailbox registers */
-#define PRCMU_I2C_WRITE(slave) \
- (((slave) << 1) | I2CWRITE | (1 << 6))
-#define PRCMU_I2C_READ(slave) \
- (((slave) << 1) | I2CREAD | (1 << 6))
-
-#define I2C_MBOX_BIT (1 << 5)
-
-static int prcmu_is_ready(void)
-{
- int ready = readb(PRCM_XP70_CUR_PWR_STATE) == AP_EXECUTE;
- if (!ready)
- printf("PRCMU firmware not ready\n");
- return ready;
-}
-
-static int wait_for_i2c_mbx_rdy(void)
-{
- int timeout = 10000;
-
- if (readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) {
- printf("prcmu: warning i2c mailbox was not acked\n");
- /* clear mailbox 5 ack irq */
- writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
- }
-
- /* check any already on-going transaction */
- while ((readl(PRCM_MBOX_CPU_VAL) & I2C_MBOX_BIT) && timeout)
- timeout--;
-
- if (timeout == 0)
- return -1;
-
- return 0;
-}
-
-static int wait_for_i2c_req_done(void)
-{
- int timeout = 10000;
-
- /* Set an interrupt to XP70 */
- writel(I2C_MBOX_BIT, PRCM_MBOX_CPU_SET);
-
- /* wait for mailbox 5 (i2c) ack */
- while (!(readl(PRCM_ARM_IT1_VAL) & I2C_MBOX_BIT) && timeout)
- timeout--;
-
- if (timeout == 0)
- return -1;
-
- return 0;
-}
-
-/**
- * prcmu_i2c_read - PRCMU - 4500 communication using PRCMU I2C
- * @reg: - db8500 register bank to be accessed
- * @slave: - db8500 register to be accessed
- * Returns: ACK_MB5 value containing the status
- */
-int prcmu_i2c_read(u8 reg, u16 slave)
-{
- uint8_t i2c_status;
- uint8_t i2c_val;
- int ret;
-
- if (!prcmu_is_ready())
- return -1;
-
- debug("\nprcmu_4500_i2c_read:bank=%x;reg=%x;\n",
- reg, slave);
-
- ret = wait_for_i2c_mbx_rdy();
- if (ret) {
- printf("prcmu_i2c_read: mailbox became not ready\n");
- return ret;
- }
-
- /* prepare the data for mailbox 5 */
- writeb(PRCMU_I2C_READ(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
- writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
- writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
- writeb(0, PRCM_REQ_MB5_I2CVAL);
-
- ret = wait_for_i2c_req_done();
- if (ret) {
- printf("prcmu_i2c_read: mailbox request timed out\n");
- return ret;
- }
-
- /* retrieve values */
- debug("ack-mb5:transfer status = %x\n",
- readb(PRCM_ACK_MB5_STATUS));
- debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
- debug("ack-mb5:slave_add = %x\n",
- readb(PRCM_ACK_MB5_SLAVE));
- debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
-
- i2c_status = readb(PRCM_ACK_MB5_STATUS);
- i2c_val = readb(PRCM_ACK_MB5_VAL);
- /* clear mailbox 5 ack irq */
- writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
-
- if (i2c_status == I2C_RD_OK)
- return i2c_val;
-
- printf("prcmu_i2c_read:read return status= %d\n", i2c_status);
- return -1;
-}
-
-/**
- * prcmu_i2c_write - PRCMU-db8500 communication using PRCMU I2C
- * @reg: - db8500 register bank to be accessed
- * @slave: - db800 register to be written to
- * @reg_data: - the data to write
- * Returns: ACK_MB5 value containing the status
- */
-int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data)
-{
- uint8_t i2c_status;
- int ret;
-
- if (!prcmu_is_ready())
- return -1;
-
- debug("\nprcmu_4500_i2c_write:bank=%x;reg=%x;\n",
- reg, slave);
-
- ret = wait_for_i2c_mbx_rdy();
- if (ret) {
- printf("prcmu_i2c_write: mailbox became not ready\n");
- return ret;
- }
-
- /* prepare the data for mailbox 5 */
- writeb(PRCMU_I2C_WRITE(reg), PRCM_REQ_MB5_I2COPTYPE_REG);
- writeb((1 << 3) | 0x0, PRCM_REQ_MB5_BIT_FIELDS);
- writeb(slave, PRCM_REQ_MB5_I2CSLAVE);
- writeb(reg_data, PRCM_REQ_MB5_I2CVAL);
-
- ret = wait_for_i2c_req_done();
- if (ret) {
- printf("prcmu_i2c_write: mailbox request timed out\n");
- return ret;
- }
-
- /* retrieve values */
- debug("ack-mb5:transfer status = %x\n",
- readb(PRCM_ACK_MB5_STATUS));
- debug("ack-mb5:reg bank = %x\n", readb(PRCM_ACK_MB5) >> 1);
- debug("ack-mb5:slave_add = %x\n",
- readb(PRCM_ACK_MB5_SLAVE));
- debug("ack-mb5:reg_val = %d\n", readb(PRCM_ACK_MB5_VAL));
-
- i2c_status = readb(PRCM_ACK_MB5_STATUS);
- debug("\ni2c_status = %x\n", i2c_status);
- /* clear mailbox 5 ack irq */
- writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
-
- if (i2c_status == I2C_WR_OK)
- return 0;
-
- printf("%s: i2c_status : 0x%x\n", __func__, i2c_status);
- return -1;
-}
-
-void u8500_prcmu_enable(u32 *reg)
-{
- writel(readl(reg) | (1 << 8), reg);
-}
-
-void db8500_prcmu_init(void)
-{
- /* Enable timers */
- writel(1 << 17, PRCM_TCR);
-
- u8500_prcmu_enable((u32 *)PRCM_PER1CLK_MGT_REG);
- u8500_prcmu_enable((u32 *)PRCM_PER2CLK_MGT_REG);
- u8500_prcmu_enable((u32 *)PRCM_PER3CLK_MGT_REG);
- /* PER4CLK does not exist */
- u8500_prcmu_enable((u32 *)PRCM_PER5CLK_MGT_REG);
- u8500_prcmu_enable((u32 *)PRCM_PER6CLK_MGT_REG);
- /* Only exists in ED but is always ok to write to */
- u8500_prcmu_enable((u32 *)PRCM_PER7CLK_MGT_REG);
-
- u8500_prcmu_enable((u32 *)PRCM_UARTCLK_MGT_REG);
- u8500_prcmu_enable((u32 *)PRCM_I2CCLK_MGT_REG);
-
- u8500_prcmu_enable((u32 *)PRCM_SDMMCCLK_MGT_REG);
-
- /* Clean up the mailbox interrupts after pre-u-boot code. */
- writel(I2C_MBOX_BIT, PRCM_ARM_IT1_CLEAR);
-}
diff --git a/arch/arm/cpu/armv7/u8500/timer.c b/arch/arm/cpu/armv7/u8500/timer.c
deleted file mode 100644
index 6b74e13..0000000
--- a/arch/arm/cpu/armv7/u8500/timer.c
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright (C) 2010 Linaro Limited
- * John Rigby <john.rigby@linaro.org>
- *
- * Based on original from Linux kernel source and
- * internal ST-Ericsson U-Boot source.
- * (C) Copyright 2009 Alessandro Rubini
- * (C) Copyright 2010 ST-Ericsson
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * The MTU device has some interrupt control registers
- * followed by 4 timers.
- */
-
-/* The timers */
-struct u8500_mtu_timer {
- u32 lr; /* Load value */
- u32 cv; /* Current value */
- u32 cr; /* Control reg */
- u32 bglr; /* ??? */
-};
-
-/* The MTU that contains the timers */
-struct u8500_mtu {
- u32 imsc; /* Interrupt mask set/clear */
- u32 ris; /* Raw interrupt status */
- u32 mis; /* Masked interrupt status */
- u32 icr; /* Interrupt clear register */
- struct u8500_mtu_timer pt[4];
-};
-
-/* bits for the control register */
-#define MTU_CR_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR */
-#define MTU_CR_32BITS 0x02
-
-#define MTU_CR_PRESCALE_1 0x00
-#define MTU_CR_PRESCALE_16 0x04
-#define MTU_CR_PRESCALE_256 0x08
-#define MTU_CR_PRESCALE_MASK 0x0c
-
-#define MTU_CR_PERIODIC 0x40 /* if 0 = free-running */
-#define MTU_CR_ENA 0x80
-
-/*
- * The MTU is clocked at 133 MHz by default. (V1 and later)
- */
-#define TIMER_CLOCK (133 * 1000 * 1000 / 16)
-#define COUNT_TO_USEC(x) ((x) * 16 / 133)
-#define USEC_TO_COUNT(x) ((x) * 133 / 16)
-#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
-#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
-#define TIMER_LOAD_VAL 0xffffffff
-
-/*
- * MTU timer to use (from 0 to 3).
- */
-#define MTU_TIMER 2
-
-static struct u8500_mtu_timer *timer_base =
- &((struct u8500_mtu *)U8500_MTU0_BASE_V1)->pt[MTU_TIMER];
-
-/* macro to read the 32 bit timer: since it decrements, we invert read value */
-#define READ_TIMER() (~readl(&timer_base->cv))
-
-/* Configure a free-running, auto-wrap counter with /16 prescaler */
-int timer_init(void)
-{
- writel(MTU_CR_ENA | MTU_CR_PRESCALE_16 | MTU_CR_32BITS,
- &timer_base->cr);
- return 0;
-}
-
-ulong get_timer_masked(void)
-{
- /* current tick value */
- ulong now = TICKS_TO_HZ(READ_TIMER());
-
- if (now >= gd->arch.lastinc) { /* normal (non rollover) */
- gd->arch.tbl += (now - gd->arch.lastinc);
- } else { /* rollover */
- gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) -
- gd->arch.lastinc) + now;
- }
- gd->arch.lastinc = now;
- return gd->arch.tbl;
-}
-
-/* Delay x useconds */
-void __udelay(ulong usec)
-{
- long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
- ulong now, last = READ_TIMER();
-
- while (tmo > 0) {
- now = READ_TIMER();
- if (now > last) /* normal (non rollover) */
- tmo -= now - last;
- else /* rollover */
- tmo -= TIMER_LOAD_VAL - last + now;
- last = now;
- }
-}
-
-ulong get_timer(ulong base)
-{
- return get_timer_masked() - base;
-}
-
-/*
- * Emulation of Power architecture long long timebase.
- *
- * TODO: Support gd->arch.tbu for real long long timebase.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * Emulation of Power architecture timebase.
- * NB: Low resolution compared to Power tbclk.
- */
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index e70bed4..da45d98 100644
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -54,8 +54,10 @@ reset:
orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
msr scr_el3, x0
msr cptr_el3, xzr /* Enable FP/SIMD */
+#ifdef COUNTER_FREQUENCY
ldr x0, =COUNTER_FREQUENCY
msr cntfrq_el0, x0 /* Initialize CNTFRQ */
+#endif
b 0f
2: msr vbar_el2, x0
mov x0, #0x33ff
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f2e18a5..65b4230 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -39,13 +39,17 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra124-venice2.dtb \
tegra210-e2220-1170.dtb \
tegra210-p2371-0000.dtb \
+ tegra210-p2371-2180.dtb \
tegra210-p2571.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-ld4-ref.dtb \
uniphier-ph1-ld6b-ref.dtb \
uniphier-ph1-pro4-ref.dtb \
+ uniphier-ph1-pro5-4kbox.dtb \
uniphier-ph1-sld3-ref.dtb \
- uniphier-ph1-sld8-ref.dtb
+ uniphier-ph1-sld8-ref.dtb \
+ uniphier-proxstream2-gentil.dtb \
+ uniphier-proxstream2-vodka.dtb
dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-zc706.dtb \
zynq-zed.dtb \
@@ -81,9 +85,11 @@ dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-gemei-g9.dtb \
sun4i-a10-hackberry.dtb \
sun4i-a10-hyundai-a7hd.dtb \
+ sun4i-a10-inet1.dtb \
sun4i-a10-inet-3f.dtb \
sun4i-a10-inet-3w.dtb \
sun4i-a10-inet97fv2.dtb \
+ sun4i-a10-inet9f-rev03.dtb \
sun4i-a10-itead-iteaduino-plus.dtb \
sun4i-a10-jesurun-q5.dtb \
sun4i-a10-marsboard.dtb \
@@ -91,13 +97,15 @@ dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-mk802.dtb \
sun4i-a10-mk802ii.dtb \
sun4i-a10-olinuxino-lime.dtb \
- sun4i-a10-pcduino.dtb
+ sun4i-a10-pcduino.dtb \
+ sun4i-a10-pov-protab2-ips9.dtb
dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a10s-auxtek-t003.dtb \
sun5i-a10s-auxtek-t004.dtb \
sun5i-a10s-mk802.dtb \
sun5i-a10s-olinuxino-micro.dtb \
sun5i-a10s-r7-tv-dongle.dtb \
+ sun5i-a10s-wobo-i5.dtb \
sun5i-a13-ampe-a76.dtb \
sun5i-a13-forfun-q88db.dtb \
sun5i-a13-hsg-h702.dtb \
@@ -105,6 +113,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \
sun5i-a13-inet-98v-rev2.dtb \
sun5i-a13-olinuxino.dtb \
sun5i-a13-olinuxino-micro.dtb \
+ sun5i-a13-q8-tablet.dtb \
sun5i-a13-tzx-q8-713b7.dtb \
sun5i-a13-utoo-p66.dtb
dtb-$(CONFIG_MACH_SUN6I) += \
@@ -144,11 +153,13 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \
sun8i-a23-evb.dtb \
sun8i-a23-gt90h-v4.dtb \
sun8i-a23-ippo-q8h-v5.dtb \
- sun8i-a23-ippo-q8h-v1.2.dtb
+ sun8i-a23-ippo-q8h-v1.2.dtb \
+ sun8i-a23-q8-tablet.dtb
dtb-$(CONFIG_MACH_SUN8I_A33) += \
sun8i-a33-et-q8-v1.6.dtb \
sun8i-a33-ga10h-v1.1.dtb \
sun8i-a33-ippo-q8h-v1.2.dtb \
+ sun8i-a33-q8-tablet.dtb \
sun8i-a33-sinlinx-sina33.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts
index 36d02df..f3fac80 100644
--- a/arch/arm/dts/exynos4210-trats.dts
+++ b/arch/arm/dts/exynos4210-trats.dts
@@ -117,4 +117,8 @@
sdhci@12540000 {
status = "disabled";
};
+
+ dwmmc@12550000 {
+ status = "disabled";
+ };
};
diff --git a/arch/arm/dts/ls1021a-twr.dts b/arch/arm/dts/ls1021a-twr.dts
index 0e61c07..6ccd332 100644
--- a/arch/arm/dts/ls1021a-twr.dts
+++ b/arch/arm/dts/ls1021a-twr.dts
@@ -17,6 +17,7 @@
enet0_sgmii_phy = &sgmii_phy2;
enet1_sgmii_phy = &sgmii_phy0;
spi0 = &qspi;
+ spi1 = &dspi1;
};
};
@@ -33,6 +34,21 @@
};
};
+&dspi1 {
+ bus-num = <0>;
+ status = "okay";
+
+ dspiflash: at26df081a@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-flash";
+ spi-max-frequency = <16000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
&i2c0 {
status = "okay";
};
diff --git a/arch/arm/dts/sun4i-a10-inet1.dts b/arch/arm/dts/sun4i-a10-inet1.dts
new file mode 100644
index 0000000..487ce63
--- /dev/null
+++ b/arch/arm/dts/sun4i-a10-inet1.dts
@@ -0,0 +1,226 @@
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "iNet-1";
+ compatible = "inet-tek,inet1", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+
+ /* Accelerometer */
+ bma250@18 {
+ compatible = "bosch,bma250";
+ reg = <0x18>;
+ interrupt-parent = <&pio>;
+ interrupts = <7 0 IRQ_TYPE_EDGE_RISING>; /* PH0 / EINT0 */
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <&reg_ldo2>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@1000 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <1000000>;
+ };
+
+ button@1200 {
+ label = "Home";
+ linux,code = <KEY_HOMEPAGE>;
+ channel = <0>;
+ voltage = <1200000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PH5";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ };
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-dll";
+};
+
+&reg_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+&reg_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+&reg_usb0_vbus {
+ status = "okay";
+};
+
+&reg_usb1_vbus {
+ status = "okay";
+};
+
+&reg_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ usb2_vbus-supply = <&reg_usb2_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun4i-a10-inet9f-rev03.dts b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts
new file mode 100644
index 0000000..8446465
--- /dev/null
+++ b/arch/arm/dts/sun4i-a10-inet9f-rev03.dts
@@ -0,0 +1,219 @@
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "iNet-9F Rev 03";
+ compatible = "inet-tek,inet9f-rev03", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <&reg_ldo2>;
+ status = "okay";
+
+ button@200 {
+ label = "Menu";
+ linux,code = <KEY_MENU>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@600 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <600000>;
+ };
+
+ button@800 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <800000>;
+ };
+
+ button@1000 {
+ label = "Home";
+ linux,code = <KEY_HOMEPAGE>;
+ channel = <0>;
+ voltage = <1000000>;
+ };
+
+ button@1200 {
+ label = "Esc";
+ linux,code = <KEY_ESC>;
+ channel = <0>;
+ voltage = <1200000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PH5";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ };
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-dll";
+};
+
+&reg_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+&reg_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+&reg_usb0_vbus {
+ status = "okay";
+};
+
+&reg_usb2_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ usb2_vbus-supply = <&reg_usb2_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts b/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts
new file mode 100644
index 0000000..223515e
--- /dev/null
+++ b/arch/arm/dts/sun4i-a10-pov-protab2-ips9.dts
@@ -0,0 +1,209 @@
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun4i-a10.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Point of View Protab2-IPS9";
+ compatible = "pov,protab2-ips9", "allwinner,sun4i-a10";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <&reg_ldo2>;
+ status = "okay";
+
+ button@400 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+
+ button@800 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <800000>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
+ cd-inverted;
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PH4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PH5";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ };
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-dll";
+};
+
+&reg_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+&reg_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+&reg_ldo3 {
+ /*
+ * We need to always power the camera sensor, otherwhise all access
+ * to i2c1 is blocked.
+ */
+ regulator-always-on;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vdd-csi";
+};
+
+&reg_usb0_vbus {
+ status = "okay";
+};
+
+&reg_usb1_vbus {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+ usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/dts/sun5i-a10s-wobo-i5.dts
new file mode 100644
index 0000000..9fea918
--- /dev/null
+++ b/arch/arm/dts/sun5i-a10s-wobo-i5.dts
@@ -0,0 +1,224 @@
+/*
+ * Copyright 2015 Jelle van der Waa <jelle@vdwaa.nl>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a10s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "A10s-Wobo i5";
+ compatible = "wobo,a10s-wobo-i5", "allwinner,sun5i-a10s";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins_wobo_i5>;
+
+ blue {
+ label = "a10s-wobo-i5:blue:usr";
+ gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ reg_emac_3v3: emac-3v3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_power_pin_wobo>;
+ regulator-name = "emac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pio 0 2 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_pins_b>;
+ phy = <&phy1>;
+ status = "okay";
+};
+
+&emac_sram {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&mdio {
+ phy-supply = <&reg_emac_3v3>;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_wobo_i5>;
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+ cd-inverted;
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ led_pins_wobo_i5: led_pins@0 {
+ allwinner,pins = "PB2";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_cd_pin_wobo_i5: mmc0_cd_pin@0 {
+ allwinner,pins = "PB3";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ emac_power_pin_wobo: emac_power_pin@0 {
+ allwinner,pins = "PA02";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1250000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-name = "vdd-int-dll";
+};
+
+&reg_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+&reg_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+&reg_ldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+&reg_usb1_vbus {
+ gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb1_vbus_pin_a {
+ allwinner,pins = "PG12";
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun5i-a10s.dtsi b/arch/arm/dts/sun5i-a10s.dtsi
index f11efb7..4173e1e 100644
--- a/arch/arm/dts/sun5i-a10s.dtsi
+++ b/arch/arm/dts/sun5i-a10s.dtsi
@@ -194,6 +194,17 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ emac_pins_b: emac0@1 {
+ allwinner,pins = "PD6", "PD7", "PD10",
+ "PD11", "PD12", "PD13", "PD14",
+ "PD15", "PD18", "PD19", "PD20",
+ "PD21", "PD22", "PD23", "PD24",
+ "PD25", "PD26", "PD27";
+ allwinner,function = "emac";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
mmc1_pins_a: mmc1@0 {
allwinner,pins = "PG3", "PG4", "PG5",
"PG6", "PG7", "PG8";
diff --git a/arch/arm/dts/sun5i-a13-q8-tablet.dts b/arch/arm/dts/sun5i-a13-q8-tablet.dts
new file mode 100644
index 0000000..72e93ac
--- /dev/null
+++ b/arch/arm/dts/sun5i-a13-q8-tablet.dts
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun5i-a13.dtsi"
+#include "sun5i-q8-common.dtsi"
+
+/ {
+ model = "Q8 A13 Tablet";
+ compatible = "allwinner,q8-a13", "allwinner,sun5i-a13";
+};
+
+&reg_ldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+&usbphy {
+ usb1_vbus-supply = <&reg_ldo3>;
+};
diff --git a/arch/arm/dts/sun5i-q8-common.dtsi b/arch/arm/dts/sun5i-q8-common.dtsi
new file mode 100644
index 0000000..0641d68
--- /dev/null
+++ b/arch/arm/dts/sun5i-q8-common.dtsi
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "sunxi-q8-common.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&reg_dcdc2>;
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&i2c0 {
+ axp209: pmic@34 {
+ reg = <0x34>;
+ interrupts = <0>;
+ };
+};
+
+&i2c1 {
+ pcf8563: rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+#include "axp209.dtsi"
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>;
+ vmmc-supply = <&reg_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
+ cd-inverted;
+ status = "okay";
+};
+
+&otg_sram {
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_q8: mmc0_cd_pin@0 {
+ allwinner,pins = "PG0";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
+ allwinner,pins = "PG1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
+ };
+
+ usb0_id_detect_pin: usb0_id_detect_pin@0 {
+ allwinner,pins = "PG2";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ usb0_vbus_pin_a: usb0_vbus_pin@0 {
+ allwinner,pins = "PG12";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&reg_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-name = "vdd-int-pll";
+};
+
+&reg_ldo1 {
+ regulator-name = "vdd-rtc";
+};
+
+&reg_ldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+};
+
+&reg_usb0_vbus {
+ gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_b>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
+ usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-a23-q8-tablet.dts b/arch/arm/dts/sun8i-a23-q8-tablet.dts
new file mode 100644
index 0000000..6062ea7
--- /dev/null
+++ b/arch/arm/dts/sun8i-a23-q8-tablet.dts
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a23.dtsi"
+#include "sun8i-q8-common.dtsi"
+
+/ {
+ model = "Q8 A23 Tablet";
+ compatible = "allwinner,q8-a23", "allwinner,sun8i-a23";
+};
+
+/*
+ * FIXME for now we only support host mode and rely on u-boot to have
+ * turned on Vbus which is controlled by the axp223 pmic on the board.
+ *
+ * Once we have axp223 support we should switch to fully supporting otg.
+ */
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-a33-q8-tablet.dts b/arch/arm/dts/sun8i-a33-q8-tablet.dts
new file mode 100644
index 0000000..44b3229
--- /dev/null
+++ b/arch/arm/dts/sun8i-a33-q8-tablet.dts
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+#include "sun8i-q8-common.dtsi"
+
+/ {
+ model = "Q8 A33 Tablet";
+ compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
+};
+
+/*
+ * FIXME for now we only support host mode and rely on u-boot to have
+ * turned on Vbus which is controlled by the axp223 pmic on the board.
+ *
+ * Once we have axp223 support we should switch to fully supporting otg.
+ */
+&usb_otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-q8-common.dtsi b/arch/arm/dts/sun8i-q8-common.dtsi
new file mode 100644
index 0000000..07cd268
--- /dev/null
+++ b/arch/arm/dts/sun8i-q8-common.dtsi
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "sunxi-q8-common.dtsi"
+
+/ {
+ aliases {
+ serial0 = &r_uart;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>;
+ vmmc-supply = <&reg_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+ cd-inverted;
+ status = "okay";
+};
+
+&pio {
+ bl_en_pin_q8: bl_en_pin@0 {
+ allwinner,pins = "PH6";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc0_cd_pin_q8: mmc0_cd_pin@0 {
+ allwinner,pins = "PB4";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+};
+
+&r_uart {
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_uart_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sunxi-q8-common.dtsi b/arch/arm/dts/sunxi-q8-common.dtsi
new file mode 100644
index 0000000..17b26ff
--- /dev/null
+++ b/arch/arm/dts/sunxi-q8-common.dtsi
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include "sunxi-common-regulators.dtsi"
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&lradc {
+ vref-supply = <&reg_vcc3v0>;
+ status = "okay";
+
+ button@200 {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ channel = <0>;
+ voltage = <200000>;
+ };
+
+ button@400 {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ channel = <0>;
+ voltage = <400000>;
+ };
+};
diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi
index b8c8a92..e68d7be 100644
--- a/arch/arm/dts/tegra20.dtsi
+++ b/arch/arm/dts/tegra20.dtsi
@@ -320,6 +320,63 @@
clocks = <&tegra_car 47>, <&tegra_car 124>;
};
+ spi@7000d400 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000d400 0x200>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA20_CLK_SBC1>;
+ resets = <&tegra_car 41>;
+ reset-names = "spi";
+ dmas = <&apbdma 15>, <&apbdma 15>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi@7000d600 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000d600 0x200>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA20_CLK_SBC2>;
+ resets = <&tegra_car 44>;
+ reset-names = "spi";
+ dmas = <&apbdma 16>, <&apbdma 16>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi@7000d800 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000d800 0x200>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA20_CLK_SBC3>;
+ resets = <&tegra_car 46>;
+ reset-names = "spi";
+ dmas = <&apbdma 17>, <&apbdma 17>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spi@7000da00 {
+ compatible = "nvidia,tegra20-slink";
+ reg = <0x7000da00 0x200>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&tegra_car TEGRA20_CLK_SBC4>;
+ resets = <&tegra_car 68>;
+ reset-names = "spi";
+ dmas = <&apbdma 18>, <&apbdma 18>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+
kbc@7000e200 {
compatible = "nvidia,tegra20-kbc";
reg = <0x7000e200 0x0078>;
diff --git a/arch/arm/dts/tegra210-p2371-2180.dts b/arch/arm/dts/tegra210-p2371-2180.dts
new file mode 100644
index 0000000..5d9adcf
--- /dev/null
+++ b/arch/arm/dts/tegra210-p2371-2180.dts
@@ -0,0 +1,60 @@
+/dts-v1/;
+
+#include "tegra210.dtsi"
+
+/ {
+ model = "NVIDIA P2371-2180";
+ compatible = "nvidia,p2371-2180", "nvidia,tegra210";
+
+ chosen {
+ stdout-path = &uarta;
+ };
+
+ aliases {
+ i2c0 = "/i2c@0,7000d000";
+ sdhci0 = "/sdhci@0,700b0600";
+ sdhci1 = "/sdhci@0,700b0000";
+ usb0 = "/usb@0,7d000000";
+ };
+
+ memory {
+ reg = <0x0 0x80000000 0x0 0xc0000000>;
+ };
+
+ sdhci@0,700b0000 {
+ status = "okay";
+ cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;
+ power-gpios = <&gpio TEGRA_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
+ wp-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ };
+
+ sdhci@0,700b0600 {
+ status = "okay";
+ bus-width = <8>;
+ };
+
+ i2c@0,7000d000 {
+ status = "okay";
+ clock-frequency = <400000>;
+ };
+
+ usb@0,7d000000 {
+ status = "okay";
+ dr_mode = "otg";
+ nvidia,vbus-gpio = <&gpio TEGRA_GPIO(CC, 4) GPIO_ACTIVE_HIGH>;
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clk32k_in: clock@0 {
+ compatible = "fixed-clock";
+ reg = <0>;
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+ };
+};
diff --git a/arch/arm/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
index 20f2e9a..9d697c1 100644
--- a/arch/arm/dts/uniphier-ph1-ld4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld4-ref.dts
@@ -61,6 +61,20 @@
};
/* for U-boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
&serial0 {
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
index 58dc20e..bd86f09 100644
--- a/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-ld6b-ref.dts
@@ -3,6 +3,7 @@
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
+ * SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
@@ -54,6 +55,20 @@
};
/* for U-boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
&serial0 {
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
index ec1117d..a825069 100644
--- a/arch/arm/dts/uniphier-ph1-pro4-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-pro4-ref.dts
@@ -68,6 +68,20 @@
};
/* for U-boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
&serial0 {
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
new file mode 100644
index 0000000..912bc27
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-pro5-4kbox.dts
@@ -0,0 +1,64 @@
+/*
+ * Device Tree Source for UniPhier PH1-Pro5 4KBOX Board (EVB-Pro5-4KBOX-M-V0)
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-pro5.dtsi"
+
+/ {
+ model = "UniPhier PH1-Pro5 4KBOX Board";
+ compatible = "socionext,ph1-pro5-4kbox", "socionext,ph1-pro5";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS1,115200";
+ stdout-path = &serial1;
+ };
+
+ aliases {
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial1 {
+ status = "okay";
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+/* for U-boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&serial1 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart1 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
index 6269f9a..2cfcaff 100644
--- a/arch/arm/dts/uniphier-ph1-sld8-ref.dts
+++ b/arch/arm/dts/uniphier-ph1-sld8-ref.dts
@@ -65,6 +65,20 @@
};
/* for U-boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
&serial0 {
- u-boot,dm-pre-reloc;
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+ u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/uniphier-pinctrl.dtsi b/arch/arm/dts/uniphier-pinctrl.dtsi
index f67445f..b584213 100644
--- a/arch/arm/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/dts/uniphier-pinctrl.dtsi
@@ -3,43 +3,7 @@
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * SPDX-License-Identifier: GPL-2.0+ X11
*/
&pinctrl {
diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts
new file mode 100644
index 0000000..81d2385
--- /dev/null
+++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts
@@ -0,0 +1,62 @@
+/*
+ * Device Tree Source for UniPhier ProXstream2 Gentil Board
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-proxstream2.dtsi"
+
+/ {
+ model = "UniPhier ProXstream2 Gentil Board";
+ compatible = "socionext,proxstream2-gentil", "socionext,proxstream2";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS2,115200";
+ stdout-path = &serial2;
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+/* for U-boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&serial2 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts
new file mode 100644
index 0000000..fba7b74
--- /dev/null
+++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts
@@ -0,0 +1,62 @@
+/*
+ * Device Tree Source for UniPhier ProXstream2 Vodka Board
+ *
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ "uniphier-proxstream2.dtsi"
+
+/ {
+ model = "UniPhier ProXstream2 Vodka Board";
+ compatible = "socionext,proxstream2-vodka", "socionext,proxstream2";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS2,115200";
+ stdout-path = &serial2;
+ };
+
+ aliases {
+ serial0 = &serial0;
+ serial1 = &serial1;
+ serial2 = &serial2;
+ i2c0 = &i2c0;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+};
+
+&serial2 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+/* for U-boot only */
+/ {
+ soc {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&serial2 {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index b9f1ca4..1698d06 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -7,7 +7,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 vf610))
obj-y = iomux-v3.o
endif
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
@@ -18,7 +18,13 @@ ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
obj-y += misc.o
obj-$(CONFIG_SPL_BUILD) += spl.o
endif
-ifeq ($(SOC),$(filter $(SOC),mx6))
+ifeq ($(SOC),$(filter $(SOC),mx7))
+obj-y += cpu.o
+obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
+obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o
+endif
+ifeq ($(SOC),$(filter $(SOC),mx6 mx7))
+obj-y += cache.o init.o
obj-$(CONFIG_CMD_SATA) += sata.o
obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif
diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c
new file mode 100644
index 0000000..54b021c
--- /dev/null
+++ b/arch/arm/imx-common/cache.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv7.h>
+#include <asm/pl310.h>
+#include <asm/io.h>
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+ enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+ /* Avoid random hang when download by usb */
+ invalidate_dcache_all();
+
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+
+ /* Enable caching on OCRAM and ROM */
+ mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
+ ROMCP_ARB_END_ADDR,
+ option);
+ mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
+ IRAM_SIZE,
+ option);
+}
+#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+#ifdef CONFIG_SYS_L2_PL310
+#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
+void v7_outer_cache_enable(void)
+{
+ struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+ unsigned int val;
+
+
+ /*
+ * Set bit 22 in the auxiliary control register. If this bit
+ * is cleared, PL310 treats Normal Shared Non-cacheable
+ * accesses as Cacheable no-allocate.
+ */
+ setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
+
+#if defined CONFIG_MX6SL
+ struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+ val = readl(&iomux->gpr[11]);
+ if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
+ /* L2 cache configured as OCRAM, reset it */
+ val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
+ writel(val, &iomux->gpr[11]);
+ }
+#endif
+
+ /* Must disable the L2 before changing the latency parameters */
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
+ writel(0x132, &pl310->pl310_tag_latency_ctrl);
+ writel(0x132, &pl310->pl310_data_latency_ctrl);
+
+ val = readl(&pl310->pl310_prefetch_ctrl);
+
+ /* Turn on the L2 I/D prefetch */
+ val |= 0x30000000;
+
+ /*
+ * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
+ * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
+ * But according to ARM PL310 errata: 752271
+ * ID: 752271: Double linefill feature can cause data corruption
+ * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
+ * Workaround: The only workaround to this erratum is to disable the
+ * double linefill feature. This is the default behavior.
+ */
+
+#ifndef CONFIG_MX6Q
+ val |= 0x40800000;
+#endif
+ writel(val, &pl310->pl310_prefetch_ctrl);
+
+ val = readl(&pl310->pl310_power_ctrl);
+ val |= L2X0_DYNAMIC_CLK_GATING_EN;
+ val |= L2X0_STNDBY_MODE_EN;
+ writel(val, &pl310->pl310_power_ctrl);
+
+ setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+
+void v7_outer_cache_disable(void)
+{
+ struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+
+ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+}
+#endif /* !CONFIG_SYS_L2_PL310 */
+#endif /* !CONFIG_SYS_L2CACHE_OFF */
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index e27546c..d3d1fc5 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -46,13 +46,28 @@ static char *get_reset_cause(void)
case 0x00008:
return "IPP USER";
case 0x00010:
+#ifdef CONFIG_MX7
+ return "WDOG1";
+#else
return "WDOG";
+#endif
case 0x00020:
return "JTAG HIGH-Z";
case 0x00040:
return "JTAG SW";
+ case 0x00080:
+ return "WDOG3";
+#ifdef CONFIG_MX7
+ case 0x00100:
+ return "WDOG4";
+ case 0x00200:
+ return "TEMPSENSE";
+#else
+ case 0x00100:
+ return "TEMPSENSE";
case 0x10000:
return "WARM BOOT";
+#endif
default:
return "unknown reset";
}
@@ -122,6 +137,8 @@ unsigned imx_ddr_size(void)
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
+ case MXC_CPU_MX7D:
+ return "7D"; /* Dual-core version of the mx7 */
case MXC_CPU_MX6QP:
return "6QP"; /* Quad-Plus version of the mx6 */
case MXC_CPU_MX6DP:
@@ -154,14 +171,12 @@ int print_cpuinfo(void)
u32 cpurev;
__maybe_unused u32 max_freq;
-#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
+ cpurev = get_cpu_rev();
+
+#if defined(CONFIG_IMX_THERMAL)
struct udevice *thermal_dev;
int cpu_tmp, minc, maxc, ret;
-#endif
-
- cpurev = get_cpu_rev();
-#if defined(CONFIG_MX6)
printf("CPU: Freescale i.MX%s rev%d.%d",
get_imx_type((cpurev & 0xFF000) >> 12),
(cpurev & 0x000F0) >> 4,
@@ -181,7 +196,7 @@ int print_cpuinfo(void)
mxc_get_clock(MXC_ARM_CLK) / 1000000);
#endif
-#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
+#if defined(CONFIG_IMX_THERMAL)
puts("CPU: ");
switch (get_cpu_temp_grade(&minc, &maxc)) {
case TEMP_AUTOMOTIVE:
@@ -205,9 +220,9 @@ int print_cpuinfo(void)
if (!ret)
printf(" at %dC\n", cpu_tmp);
else
- puts(" - invalid sensor data\n");
+ debug(" - invalid sensor data\n");
} else {
- puts(" - invalid sensor device\n");
+ debug(" - invalid sensor device\n");
}
#endif
@@ -238,6 +253,7 @@ int cpu_mmc_init(bd_t *bis)
}
#endif
+#ifndef CONFIG_MX7
u32 get_ahb_clk(void)
{
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -249,6 +265,7 @@ u32 get_ahb_clk(void)
return get_periph_clk() / (ahb_podf + 1);
}
+#endif
void arch_preboot_os(void)
{
diff --git a/arch/arm/imx-common/ddrmc-vf610.c b/arch/arm/imx-common/ddrmc-vf610.c
index e462631..daf3c7e 100644
--- a/arch/arm/imx-common/ddrmc-vf610.c
+++ b/arch/arm/imx-common/ddrmc-vf610.c
@@ -12,9 +12,9 @@
#include <asm/arch/iomux-vf610.h>
#include <asm/arch/ddrmc-vf610.h>
-void ddrmc_setup_iomux(void)
+void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
{
- static const iomux_v3_cfg_t ddr_pads[] = {
+ static const iomux_v3_cfg_t default_pads[] = {
VF610_PAD_DDR_A15__DDR_A_15,
VF610_PAD_DDR_A14__DDR_A_14,
VF610_PAD_DDR_A13__DDR_A_13,
@@ -65,76 +65,54 @@ void ddrmc_setup_iomux(void)
VF610_PAD_DDR_RESETB,
};
- imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
-}
+ if ((pads == NULL) || (pads_count == 0)) {
+ pads = default_pads;
+ pads_count = ARRAY_SIZE(default_pads);
+ }
-void ddrmc_phy_init(void)
-{
- struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+ imx_iomux_v3_setup_multiple_pads(pads, pads_count);
+}
- writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
- writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
- writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
+static struct ddrmc_phy_setting default_phy_settings[] = {
+ { DDRMC_PHY_DQ_TIMING, 0 },
+ { DDRMC_PHY_DQ_TIMING, 16 },
+ { DDRMC_PHY_DQ_TIMING, 32 },
- writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
- writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
+ { DDRMC_PHY_DQS_TIMING, 1 },
+ { DDRMC_PHY_DQS_TIMING, 17 },
- writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
- writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
- writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
+ { DDRMC_PHY_CTRL, 2 },
+ { DDRMC_PHY_CTRL, 18 },
+ { DDRMC_PHY_CTRL, 34 },
- writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
- writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
- writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
+ { DDRMC_PHY_MASTER_CTRL, 3 },
+ { DDRMC_PHY_MASTER_CTRL, 19 },
+ { DDRMC_PHY_MASTER_CTRL, 35 },
- writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
- writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
- writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
+ { DDRMC_PHY_SLAVE_CTRL, 4 },
+ { DDRMC_PHY_SLAVE_CTRL, 20 },
+ { DDRMC_PHY_SLAVE_CTRL, 36 },
/* LPDDR2 only parameter */
- writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
+ { DDRMC_PHY_OFF, 49 },
- writel(DDRMC_PHY50_DDR3_MODE |
- DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]);
+ { DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE, 50 },
/* Processor Pad ODT settings */
- writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
-}
-
-static void ddrmc_ctrl_lvl_init(struct ddrmc_lvl_info *lvl)
-{
- struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
- u32 cr102 = 0, cr105 = 0, cr106 = 0, cr110 = 0;
+ { DDRMC_PHY_PROC_PAD_ODT, 52 },
- if (lvl->wrlvl_reg_en) {
- writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
- writel(DDRMC_CR98_WRLVL_DL_0(lvl->wrlvl_dl_0), &ddrmr->cr[98]);
- writel(DDRMC_CR99_WRLVL_DL_1(lvl->wrlvl_dl_1), &ddrmr->cr[99]);
- }
-
- if (lvl->rdlvl_reg_en) {
- cr102 |= DDRMC_CR102_RDLVL_REG_EN;
- cr105 |= DDRMC_CR105_RDLVL_DL_0(lvl->rdlvl_dl_0);
- cr110 |= DDRMC_CR110_RDLVL_DL_1(lvl->rdlvl_dl_1);
- }
-
- if (lvl->rdlvl_gt_reg_en) {
- cr102 |= DDRMC_CR102_RDLVL_GT_REGEN;
- cr106 |= DDRMC_CR106_RDLVL_GTDL_0(lvl->rdlvl_gt_dl_0);
- cr110 |= DDRMC_CR110_RDLVL_GTDL_1(lvl->rdlvl_gt_dl_1);
- }
-
- writel(cr102, &ddrmr->cr[102]);
- writel(cr105, &ddrmr->cr[105]);
- writel(cr106, &ddrmr->cr[106]);
- writel(cr110, &ddrmr->cr[110]);
-}
+ /* end marker */
+ { 0, -1 }
+};
void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
- struct ddrmc_lvl_info *lvl,
- int col_diff, int row_diff)
+ struct ddrmc_cr_setting *board_cr_settings,
+ struct ddrmc_phy_setting *board_phy_settings,
+ int col_diff, int row_diff)
{
struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+ struct ddrmc_cr_setting *cr_setting;
+ struct ddrmc_phy_setting *phy_setting;
writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
@@ -144,7 +122,9 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
writel(DDRMC_CR12_WRLAT(timings->wrlat) |
DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
- DDRMC_CR13_TCCD(timings->tccd), &ddrmr->cr[13]);
+ DDRMC_CR13_TCCD(timings->tccd) |
+ DDRMC_CR13_TBST_INT_INTERVAL(timings->tbst_int_interval),
+ &ddrmr->cr[13]);
writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
DDRMC_CR14_TWTR(timings->twtr) |
DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
@@ -156,18 +136,19 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
- writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) |
- DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
+ writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) | DDRMC_CR21_CCMAP_EN |
+ DDRMC_CR21_TRAS_LOCKOUT(timings->tras_lockout),
+ &ddrmr->cr[21]);
writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
- writel(DDRMC_CR23_BSTLEN(3) |
+ writel(DDRMC_CR23_BSTLEN(timings->bstlen) |
DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
writel(DDRMC_CR26_TREF(timings->tref) |
DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
- writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]);
+ writel(DDRMC_CR28_TREF_INT(timings->tref_int), &ddrmr->cr[28]);
writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
@@ -177,7 +158,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
writel(DDRMC_CR34_CKSRX(timings->cksrx) |
DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
- writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]);
+ writel(DDRMC_CR38_FREQ_CHG_EN(timings->freq_chg_en), &ddrmr->cr[38]);
writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
@@ -191,13 +172,14 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
- writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
+ writel(DDRMC_CR72_ZQCS_ROTATE(timings->zqcs_rotate), &ddrmr->cr[72]);
writel(DDRMC_CR73_APREBIT(timings->aprebit) |
DDRMC_CR73_COL_DIFF(col_diff) |
DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
- DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
+ DDRMC_CR74_CMD_AGE_CNT(timings->cmd_age_cnt) |
+ DDRMC_CR74_AGE_CNT(timings->age_cnt),
&ddrmr->cr[74]);
writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
DDRMC_CR75_PLEN, &ddrmr->cr[75]);
@@ -205,13 +187,15 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
- writel(DDRMC_CR78_Q_FULLNESS(7) |
+ writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) |
DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
- writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
+ writel(DDRMC_CR87_ODT_RD_MAPCS0(timings->odt_rd_mapcs0) |
+ DDRMC_CR87_ODT_WR_MAPCS0(timings->odt_wr_mapcs0),
+ &ddrmr->cr[87]);
writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
@@ -219,58 +203,33 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
- if (lvl != NULL)
- ddrmc_ctrl_lvl_init(lvl);
-
- writel(DDRMC_CR117_AXI0_W_PRI(0) |
- DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]);
- writel(DDRMC_CR118_AXI1_W_PRI(1) |
- DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]);
-
- writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) |
- DDRMC_CR120_AXI0_PRI0_RPRI(2), &ddrmr->cr[120]);
- writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) |
- DDRMC_CR121_AXI0_PRI2_RPRI(2), &ddrmr->cr[121]);
- writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
- DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
- writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
- DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
- writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
-
- writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]);
- writel(DDRMC_CR132_WRLAT_ADJ(5) |
- DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]);
- writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
- writel(DDRMC_CR138_PHY_WRLV_MXDL(256) |
- DDRMC_CR138_PHYDRAM_CK_EN(1), &ddrmr->cr[138]);
- writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
- DDRMC_CR139_PHY_WRLV_DLL(3) |
- DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]);
- writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
- writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) |
- DDRMC_CR143_RDLV_MXDL(128), &ddrmr->cr[143]);
- writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
- DDRMC_CR144_PHY_RDLV_DLL(3) |
- DDRMC_CR144_PHY_RDLV_EN(3), &ddrmr->cr[144]);
- writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
- writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
- writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
- writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
- writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
- DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
-
- writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
- DDRMC_CR154_PAD_ZQ_MODE(1) |
- DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
- DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
- writel(DDRMC_CR155_PAD_ODT_BYTE1(2) |
- DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]);
- writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
- writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
- DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
-
- ddrmc_phy_init();
+ /* execute custom CR setting sequence (may be NULL) */
+ cr_setting = board_cr_settings;
+ if (cr_setting != NULL)
+ while (cr_setting->cr_rnum >= 0) {
+ writel(cr_setting->setting,
+ &ddrmr->cr[cr_setting->cr_rnum]);
+ cr_setting++;
+ }
+
+ /* perform default PHY settings (may be overriden by custom settings */
+ phy_setting = default_phy_settings;
+ while (phy_setting->phy_rnum >= 0) {
+ writel(phy_setting->setting,
+ &ddrmr->phy[phy_setting->phy_rnum]);
+ phy_setting++;
+ }
+
+ /* execute custom PHY setting sequence (may be NULL) */
+ phy_setting = board_phy_settings;
+ if (phy_setting != NULL)
+ while (phy_setting->phy_rnum >= 0) {
+ writel(phy_setting->setting,
+ &ddrmr->phy[phy_setting->phy_rnum]);
+ phy_setting++;
+ }
+ /* all inits done, start the DDR controller */
writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
while (!(readl(&ddrmr->cr[80]) && 0x100))
diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c
new file mode 100644
index 0000000..15dab1d
--- /dev/null
+++ b/arch/arm/imx-common/init.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/arch/crm_regs.h>
+
+void init_aips(void)
+{
+ struct aipstz_regs *aips1, *aips2, *aips3;
+
+ aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
+ aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
+ aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
+
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ writel(0x77777777, &aips1->mprot0);
+ writel(0x77777777, &aips1->mprot1);
+ writel(0x77777777, &aips2->mprot0);
+ writel(0x77777777, &aips2->mprot1);
+
+ /*
+ * Set all OPACRx to be non-bufferable, not require
+ * supervisor privilege level for access,allow for
+ * write access and untrusted master access.
+ */
+ writel(0x00000000, &aips1->opacr0);
+ writel(0x00000000, &aips1->opacr1);
+ writel(0x00000000, &aips1->opacr2);
+ writel(0x00000000, &aips1->opacr3);
+ writel(0x00000000, &aips1->opacr4);
+ writel(0x00000000, &aips2->opacr0);
+ writel(0x00000000, &aips2->opacr1);
+ writel(0x00000000, &aips2->opacr2);
+ writel(0x00000000, &aips2->opacr3);
+ writel(0x00000000, &aips2->opacr4);
+
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) {
+ /*
+ * Set all MPROTx to be non-bufferable, trusted for R/W,
+ * not forced to user-mode.
+ */
+ writel(0x77777777, &aips3->mprot0);
+ writel(0x77777777, &aips3->mprot1);
+
+ /*
+ * Set all OPACRx to be non-bufferable, not require
+ * supervisor privilege level for access,allow for
+ * write access and untrusted master access.
+ */
+ writel(0x00000000, &aips3->opacr0);
+ writel(0x00000000, &aips3->opacr1);
+ writel(0x00000000, &aips3->opacr2);
+ writel(0x00000000, &aips3->opacr3);
+ writel(0x00000000, &aips3->opacr4);
+ }
+}
+
+void imx_set_wdog_powerdown(bool enable)
+{
+ struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
+ struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+ struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
+#ifdef CONFIG_MX7D
+ struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
+#endif
+
+ /* Write to the PDE (Power Down Enable) bit */
+ writew(enable, &wdog1->wmcr);
+ writew(enable, &wdog2->wmcr);
+
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+ is_soc_type(MXC_SOC_MX7))
+ writew(enable, &wdog3->wmcr);
+#ifdef CONFIG_MX7D
+ writew(enable, &wdog4->wmcr);
+#endif
+}
+
+#define SRC_SCR_WARM_RESET_ENABLE 0
+
+void init_src(void)
+{
+ struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+ u32 val;
+
+ /*
+ * force warm reset sources to generate cold reset
+ * for a more reliable restart
+ */
+ val = readl(&src_regs->scr);
+ val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
+ writel(val, &src_regs->scr);
+}
+
+#ifdef CONFIG_CMD_BMODE
+void boot_mode_apply(unsigned cfg_val)
+{
+ unsigned reg;
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ writel(cfg_val, &psrc->gpr9);
+ reg = readl(&psrc->gpr10);
+ if (cfg_val)
+ reg |= 1 << 28;
+ else
+ reg &= ~(1 << 28);
+ writel(reg, &psrc->gpr10);
+}
+#endif
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index b4f481f..228d5f8 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -11,10 +11,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
-#if !defined(CONFIG_MX25) && !defined(CONFIG_VF610)
-#include <asm/arch/sys_proto.h>
-#endif
#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/sys_proto.h>
static void *base = (void *)IOMUXC_BASE_ADDR;
@@ -53,7 +51,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
}
#endif
- if (mux_ctrl_ofs)
+ if (is_soc_type(MXC_SOC_MX7) || mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
if (sel_input_ofs)
diff --git a/arch/arm/imx-common/syscounter.c b/arch/arm/imx-common/syscounter.c
new file mode 100644
index 0000000..e00fef2
--- /dev/null
+++ b/arch/arm/imx-common/syscounter.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * The file use ls102xa/timer.c as a reference.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/syscounter.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This function is intended for SHORT delays only.
+ * It will overflow at around 10 seconds @ 400MHz,
+ * or 20 seconds @ 200MHz.
+ */
+unsigned long usec2ticks(unsigned long usec)
+{
+ ulong ticks;
+
+ if (usec < 1000)
+ ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
+ else
+ ticks = ((usec / 10) * (get_tbclk() / 100000));
+
+ return ticks;
+}
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ unsigned long freq;
+
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+ tick *= CONFIG_SYS_HZ;
+ do_div(tick, freq);
+
+ return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long usec)
+{
+ unsigned long freq;
+
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+ usec = usec * freq + 999999;
+ do_div(usec, 1000000);
+
+ return usec;
+}
+
+int timer_init(void)
+{
+ struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
+ unsigned long val, freq;
+
+ freq = CONFIG_SC_TIMER_CLK;
+ asm("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
+
+ writel(freq, &sctr->cntfid0);
+
+ /* Enable system counter */
+ val = readl(&sctr->cntcr);
+ val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1);
+ val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG;
+ writel(val, &sctr->cntcr);
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ return 0;
+}
+
+unsigned long long get_ticks(void)
+{
+ unsigned long long now;
+
+ asm("mrrc p15, 0, %Q0, %R0, c14" : "=r" (now));
+
+ gd->arch.tbl = (unsigned long)(now & 0xffffffff);
+ gd->arch.tbu = (unsigned long)(now >> 32);
+
+ return now;
+}
+
+ulong get_timer_masked(void)
+{
+ return tick_to_time(get_ticks());
+}
+
+ulong get_timer(ulong base)
+{
+ return get_timer_masked() - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned long long tmp;
+ ulong tmo;
+
+ tmo = us_to_tick(usec);
+ tmp = get_ticks() + tmo; /* get current timestamp */
+
+ while (get_ticks() < tmp) /* loop till event */
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ unsigned long freq;
+
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (freq));
+
+ return freq;
+}
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 13a9cad..112ac5e 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -17,7 +17,6 @@
#include <asm/arch/hardware.h>
-#define BIT(x) (1 << x)
#define CL_BIT(x) (0 << x)
/* Timer register bits */
diff --git a/arch/arm/include/asm/arch-hi6220/gpio.h b/arch/arm/include/asm/arch-hi6220/gpio.h
index 98122a2..4fafaef 100644
--- a/arch/arm/include/asm/arch-hi6220/gpio.h
+++ b/arch/arm/include/asm/arch-hi6220/gpio.h
@@ -11,8 +11,6 @@
#define HI6220_GPIO_BASE(bank) (((bank < 4) ? 0xf8011000 : \
0xf7020000 - 0x4000) + (0x1000 * bank))
-#define BIT(x) (1 << (x))
-
#define HI6220_GPIO_PER_BANK 8
#define HI6220_GPIO_DIR 0x400
diff --git a/arch/arm/include/asm/arch-hi6220/hi6220.h b/arch/arm/include/asm/arch-hi6220/hi6220.h
index 4b987c2..3a12c75 100644
--- a/arch/arm/include/asm/arch-hi6220/hi6220.h
+++ b/arch/arm/include/asm/arch-hi6220/hi6220.h
@@ -13,6 +13,9 @@
#define HI6220_MMC0_BASE 0xF723D000
#define HI6220_MMC1_BASE 0xF723E000
+#define HI6220_UART0_BASE 0xF8015000
+#define HI6220_UART3_BASE 0xF7113000
+
#define HI6220_PMUSSI_BASE 0xF8000000
#define HI6220_PERI_BASE 0xF7030000
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 1c8d24e..7e681e9 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -21,8 +21,12 @@
#define MXC_CPU_MX6D 0x67
#define MXC_CPU_MX6DP 0x68
#define MXC_CPU_MX6QP 0x69
+#define MXC_CPU_MX7D 0x72
#define MXC_CPU_VF610 0xF6 /* dummy ID */
+#define MXC_SOC_MX6 0x60
+#define MXC_SOC_MX7 0x70
+
#define CS0_128 0
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h
index d21310e..303ff1c 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -158,9 +158,6 @@ struct clk_pm_regs {
#define CLK_NAND_SLC_SELECT (1 << 2)
#define CLK_NAND_MLC_INT (1 << 5)
-/* DMA Clock Control Register bits */
-#define DMA_CLK_ENABLE (1 << 0)
-
/* SSP Clock Control Register bits */
#define CLK_SSP0_ENABLE_CLOCK (1 << 0)
diff --git a/arch/arm/include/asm/arch-lpc32xx/emc.h b/arch/arm/include/asm/arch-lpc32xx/emc.h
index 1a2bab2..f70faf8 100644
--- a/arch/arm/include/asm/arch-lpc32xx/emc.h
+++ b/arch/arm/include/asm/arch-lpc32xx/emc.h
@@ -70,7 +70,7 @@ struct emc_regs {
/* Static Memory Delay Registers */
#define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F)
-#define EMC_STAT_WAITOEN(n) (((n) - 1) & 0x0F)
+#define EMC_STAT_WAITOEN(n) ((n) & 0x0F)
#define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F)
#define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F)
#define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F)
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
index c9cf9df..64acf15 100644
--- a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h
@@ -12,7 +12,7 @@
/*
* Macro to map the pin for the lpc32xx_gpio driver.
- * Note: - GPIOS are considered here as homogeneous and linear, from 0 to 127;
+ * Note: - GPIOS are considered here as homogeneous and linear from 0 to 159;
* mapping is done per register, as group of 32.
* (see drivers/gpio/lpc32xx_gpio.c for details).
* - macros can be use with the following pins:
@@ -26,9 +26,9 @@
#define LPC32XX_GPIO_P0_GRP 0
#define LPC32XX_GPIO_P1_GRP 32
#define LPC32XX_GPIO_P2_GRP 64
-#define LPC32XX_GPI_P3_GRP 96
#define LPC32XX_GPO_P3_GRP 96
#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25)
+#define LPC32XX_GPI_P3_GRP 128
/*
* A specific GPIO can be selected with this macro
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index a685ed2..74512ac 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -137,8 +137,10 @@
/* Defines for Blocks connected via AIPS (SkyBlue) */
#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
+#define ATZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
+#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
@@ -219,6 +221,8 @@
#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
+#define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000)
+#define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000)
#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
diff --git a/arch/arm/include/asm/arch-mx7/clock.h b/arch/arm/include/asm/arch-mx7/clock.h
new file mode 100644
index 0000000..688d236
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/clock.h
@@ -0,0 +1,348 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ * Peng Fan <Peng.Fan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_CLOCK_H
+#define _ASM_ARCH_CLOCK_H
+
+#include <common.h>
+#include <asm/arch/crm_regs.h>
+
+#ifdef CONFIG_SYS_MX7_HCLK
+#define MXC_HCLK CONFIG_SYS_MX7_HCLK
+#else
+#define MXC_HCLK 24000000
+#endif
+
+#ifdef CONFIG_SYS_MX7_CLK32
+#define MXC_CLK32 CONFIG_SYS_MX7_CLK32
+#else
+#define MXC_CLK32 32768
+#endif
+
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_AHB_CLK,
+ MXC_IPG_CLK,
+ MXC_UART_CLK,
+ MXC_CSPI_CLK,
+ MXC_AXI_CLK,
+ MXC_DDR_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_I2C_CLK,
+};
+
+/* PLL supported by i.mx7d */
+enum pll_clocks {
+ PLL_CORE, /* Core PLL */
+ PLL_SYS, /* System PLL*/
+ PLL_ENET, /* Enet PLL */
+ PLL_AUDIO, /* Audio PLL */
+ PLL_VIDEO, /* Video PLL*/
+ PLL_DDR, /* Dram PLL */
+ PLL_USB, /* USB PLL, fixed at 480MHZ */
+};
+
+/* clk src for clock root gen */
+enum clk_root_src {
+ OSC_24M_CLK,
+
+ PLL_ARM_MAIN_800M_CLK,
+
+ PLL_SYS_MAIN_480M_CLK,
+ PLL_SYS_MAIN_240M_CLK,
+ PLL_SYS_MAIN_120M_CLK,
+ PLL_SYS_PFD0_392M_CLK,
+ PLL_SYS_PFD0_196M_CLK,
+ PLL_SYS_PFD1_332M_CLK,
+ PLL_SYS_PFD1_166M_CLK,
+ PLL_SYS_PFD2_270M_CLK,
+ PLL_SYS_PFD2_135M_CLK,
+ PLL_SYS_PFD3_CLK,
+ PLL_SYS_PFD4_CLK,
+ PLL_SYS_PFD5_CLK,
+ PLL_SYS_PFD6_CLK,
+ PLL_SYS_PFD7_CLK,
+
+ PLL_ENET_MAIN_500M_CLK,
+ PLL_ENET_MAIN_250M_CLK,
+ PLL_ENET_MAIN_125M_CLK,
+ PLL_ENET_MAIN_100M_CLK,
+ PLL_ENET_MAIN_50M_CLK,
+ PLL_ENET_MAIN_40M_CLK,
+ PLL_ENET_MAIN_25M_CLK,
+
+ PLL_DRAM_MAIN_1066M_CLK,
+ PLL_DRAM_MAIN_533M_CLK,
+
+ PLL_AUDIO_MAIN_CLK,
+ PLL_VIDEO_MAIN_CLK,
+
+ PLL_USB_MAIN_480M_CLK, /* fixed at 480MHZ */
+
+ EXT_CLK_1,
+ EXT_CLK_2,
+ EXT_CLK_3,
+ EXT_CLK_4,
+
+ REF_1M_CLK,
+ OSC_32K_CLK,
+};
+
+/*
+ * Clock root index
+ */
+enum clk_root_index {
+ ARM_A7_CLK_ROOT = 0,
+ ARM_M4_CLK_ROOT = 1,
+ ARM_M0_CLK_ROOT = 2,
+ MAIN_AXI_CLK_ROOT = 16,
+ DISP_AXI_CLK_ROOT = 17,
+ ENET_AXI_CLK_ROOT = 18,
+ NAND_USDHC_BUS_CLK_ROOT = 19,
+ AHB_CLK_ROOT = 32,
+ DRAM_PHYM_CLK_ROOT = 48,
+ DRAM_CLK_ROOT = 49,
+ DRAM_PHYM_ALT_CLK_ROOT = 64,
+ DRAM_ALT_CLK_ROOT = 65,
+ USB_HSIC_CLK_ROOT = 66,
+ PCIE_CTRL_CLK_ROOT = 67,
+ PCIE_PHY_CLK_ROOT = 68,
+ EPDC_PIXEL_CLK_ROOT = 69,
+ LCDIF_PIXEL_CLK_ROOT = 70,
+ MIPI_DSI_EXTSER_CLK_ROOT = 71,
+ MIPI_CSI_WARP_CLK_ROOT = 72,
+ MIPI_DPHY_REF_CLK_ROOT = 73,
+ SAI1_CLK_ROOT = 74,
+ SAI2_CLK_ROOT = 75,
+ SAI3_CLK_ROOT = 76,
+ SPDIF_CLK_ROOT = 77,
+ ENET1_REF_CLK_ROOT = 78,
+ ENET1_TIME_CLK_ROOT = 79,
+ ENET2_REF_CLK_ROOT = 80,
+ ENET2_TIME_CLK_ROOT = 81,
+ ENET_PHY_REF_CLK_ROOT = 82,
+ EIM_CLK_ROOT = 83,
+ NAND_CLK_ROOT = 84,
+ QSPI_CLK_ROOT = 85,
+ USDHC1_CLK_ROOT = 86,
+ USDHC2_CLK_ROOT = 87,
+ USDHC3_CLK_ROOT = 88,
+ CAN1_CLK_ROOT = 89,
+ CAN2_CLK_ROOT = 90,
+ I2C1_CLK_ROOT = 91,
+ I2C2_CLK_ROOT = 92,
+ I2C3_CLK_ROOT = 93,
+ I2C4_CLK_ROOT = 94,
+ UART1_CLK_ROOT = 95,
+ UART2_CLK_ROOT = 96,
+ UART3_CLK_ROOT = 97,
+ UART4_CLK_ROOT = 98,
+ UART5_CLK_ROOT = 99,
+ UART6_CLK_ROOT = 100,
+ UART7_CLK_ROOT = 101,
+ ECSPI1_CLK_ROOT = 102,
+ ECSPI2_CLK_ROOT = 103,
+ ECSPI3_CLK_ROOT = 104,
+ ECSPI4_CLK_ROOT = 105,
+ PWM1_CLK_ROOT = 106,
+ PWM2_CLK_ROOT = 107,
+ PWM3_CLK_ROOT = 108,
+ PWM4_CLK_ROOT = 109,
+ FLEXTIMER1_CLK_ROOT = 110,
+ FLEXTIMER2_CLK_ROOT = 111,
+ SIM1_CLK_ROOT = 112,
+ SIM2_CLK_ROOT = 113,
+ GPT1_CLK_ROOT = 114,
+ GPT2_CLK_ROOT = 115,
+ GPT3_CLK_ROOT = 116,
+ GPT4_CLK_ROOT = 117,
+ TRACE_CLK_ROOT = 118,
+ WDOG_CLK_ROOT = 119,
+ CSI_MCLK_CLK_ROOT = 120,
+ AUDIO_MCLK_CLK_ROOT = 121,
+ WRCLK_CLK_ROOT = 122,
+ IPP_DO_CLKO1 = 123,
+ IPP_DO_CLKO2 = 124,
+
+ CLK_ROOT_MAX,
+};
+
+struct clk_root_setting {
+ enum clk_root_index root;
+ u32 setting;
+};
+
+/*
+ * CCGR mapping
+ */
+enum clk_ccgr_index {
+ CCGR_CPU = 0,
+ CCGR_M4 = 1,
+ CCGR_SIM_MAIN = 4,
+ CCGR_SIM_DISPLAY = 5,
+ CCGR_SIM_ENET = 6,
+ CCGR_SIM_M = 7,
+ CCGR_SIM_S = 8,
+ CCGR_SIM_WAKEUP = 9,
+ CCGR_IPMUX1 = 10,
+ CCGR_IPMUX2 = 11,
+ CCGR_IPMUX3 = 12,
+ CCGR_ROM = 16,
+ CCGR_OCRAM = 17,
+ CCGR_OCRAM_S = 18,
+ CCGR_DRAM = 19,
+ CCGR_RAWNAND = 20,
+ CCGR_QSPI = 21,
+ CCGR_WEIM = 22,
+ CCGR_ADC = 32,
+ CCGR_ANATOP = 33,
+ CCGR_SCTR = 34,
+ CCGR_OCOTP = 35,
+ CCGR_CAAM = 36,
+ CCGR_SNVS = 37,
+ CCGR_RDC = 38,
+ CCGR_MU = 39,
+ CCGR_HS = 40,
+ CCGR_DVFS = 41,
+ CCGR_QOS = 42,
+ CCGR_QOS_DISPMIX = 43,
+ CCGR_QOS_MEGAMIX = 44,
+ CCGR_CSU = 45,
+ CCGR_DBGMON = 46,
+ CCGR_DEBUG = 47,
+ CCGR_TRACE = 48,
+ CCGR_SEC_DEBUG = 49,
+ CCGR_SEMA1 = 64,
+ CCGR_SEMA2 = 65,
+ CCGR_PERFMON1 = 68,
+ CCGR_PERFMON2 = 69,
+ CCGR_SDMA = 72,
+ CCGR_CSI = 73,
+ CCGR_EPDC = 74,
+ CCGR_LCDIF = 75,
+ CCGR_PXP = 76,
+ CCGR_PCIE = 96,
+ CCGR_MIPI_CSI = 100,
+ CCGR_MIPI_DSI = 101,
+ CCGR_MIPI_MEM_PHY = 102,
+ CCGR_USB_CTRL = 104,
+ CCGR_USB_HSIC = 105,
+ CCGR_USB_PHY1 = 106,
+ CCGR_USB_PHY2 = 107,
+ CCGR_USDHC1 = 108,
+ CCGR_USDHC2 = 109,
+ CCGR_USDHC3 = 110,
+ CCGR_ENET1 = 112,
+ CCGR_ENET2 = 113,
+ CCGR_CAN1 = 116,
+ CCGR_CAN2 = 117,
+ CCGR_ECSPI1 = 120,
+ CCGR_ECSPI2 = 121,
+ CCGR_ECSPI3 = 122,
+ CCGR_ECSPI4 = 123,
+ CCGR_GPT1 = 124,
+ CCGR_GPT2 = 125,
+ CCGR_GPT3 = 126,
+ CCGR_GPT4 = 127,
+ CCGR_FTM1 = 128,
+ CCGR_FTM2 = 129,
+ CCGR_PWM1 = 132,
+ CCGR_PWM2 = 133,
+ CCGR_PWM3 = 134,
+ CCGR_PWM4 = 135,
+ CCGR_I2C1 = 136,
+ CCGR_I2C2 = 137,
+ CCGR_I2C3 = 138,
+ CCGR_I2C4 = 139,
+ CCGR_SAI1 = 140,
+ CCGR_SAI2 = 141,
+ CCGR_SAI3 = 142,
+ CCGR_SIM1 = 144,
+ CCGR_SIM2 = 145,
+ CCGR_UART1 = 148,
+ CCGR_UART2 = 149,
+ CCGR_UART3 = 150,
+ CCGR_UART4 = 151,
+ CCGR_UART5 = 152,
+ CCGR_UART6 = 153,
+ CCGR_UART7 = 154,
+ CCGR_WDOG1 = 156,
+ CCGR_WDOG2 = 157,
+ CCGR_WDOG3 = 158,
+ CCGR_WDOG4 = 159,
+ CCGR_GPIO1 = 160,
+ CCGR_GPIO2 = 161,
+ CCGR_GPIO3 = 162,
+ CCGR_GPIO4 = 163,
+ CCGR_GPIO5 = 164,
+ CCGR_GPIO6 = 165,
+ CCGR_GPIO7 = 166,
+ CCGR_IOMUX = 168,
+ CCGR_IOMUX_LPSR = 169,
+ CCGR_KPP = 170,
+
+ CCGR_SKIP,
+ CCGR_MAX,
+};
+
+/* Clock root channel */
+enum clk_root_type {
+ CCM_CORE_CHANNEL,
+ CCM_BUS_CHANNEL,
+ CCM_AHB_CHANNEL,
+ CCM_DRAM_PHYM_CHANNEL,
+ CCM_DRAM_CHANNEL,
+ CCM_IP_CHANNEL,
+};
+
+#include <asm/arch/clock_slice.h>
+
+/*
+ * entry: the clock root index
+ * type: ccm channel
+ * src_mux: each entry corresponding to the clock src, detailed info in CCM RM
+ */
+struct clk_root_map {
+ enum clk_root_index entry;
+ enum clk_root_type type;
+ uint8_t src_mux[8];
+};
+
+enum enet_freq {
+ ENET_25MHz,
+ ENET_50MHz,
+ ENET_125MHz,
+};
+
+u32 get_root_clk(enum clk_root_index clock_id);
+u32 mxc_get_clock(enum mxc_clock clk);
+u32 imx_get_uartclk(void);
+u32 imx_get_fecclk(void);
+void clock_init(void);
+#ifdef CONFIG_SYS_I2C_MXC
+int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
+#endif
+#ifdef CONFIG_FEC_MXC
+int set_clk_enet(enum enet_freq type);
+#endif
+int set_clk_qspi(void);
+int set_clk_nand(void);
+#ifdef CONFIG_MXC_OCOTP
+void enable_ocotp_clk(unsigned char enable);
+#endif
+void enable_usboh3_clk(unsigned char enable);
+#ifdef CONFIG_SECURE_BOOT
+void hab_caam_clock_enable(unsigned char enable);
+#endif
+void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq);
+void enable_thermal_clk(void);
+#endif
diff --git a/arch/arm/include/asm/arch-mx7/clock_slice.h b/arch/arm/include/asm/arch-mx7/clock_slice.h
new file mode 100644
index 0000000..6ede0cd
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/clock_slice.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ * Peng Fan <Peng.Fan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_CLOCK_SLICE_H
+#define _ASM_ARCH_CLOCK_SLICE_H
+
+enum root_pre_div {
+ CLK_ROOT_PRE_DIV1 = 0,
+ CLK_ROOT_PRE_DIV2,
+ CLK_ROOT_PRE_DIV3,
+ CLK_ROOT_PRE_DIV4,
+ CLK_ROOT_PRE_DIV5,
+ CLK_ROOT_PRE_DIV6,
+ CLK_ROOT_PRE_DIV7,
+ CLK_ROOT_PRE_DIV8,
+};
+
+enum root_post_div {
+ CLK_ROOT_POST_DIV1 = 0,
+ CLK_ROOT_POST_DIV2,
+ CLK_ROOT_POST_DIV3,
+ CLK_ROOT_POST_DIV4,
+ CLK_ROOT_POST_DIV5,
+ CLK_ROOT_POST_DIV6,
+ CLK_ROOT_POST_DIV7,
+ CLK_ROOT_POST_DIV8,
+ CLK_ROOT_POST_DIV9,
+ CLK_ROOT_POST_DIV10,
+ CLK_ROOT_POST_DIV11,
+ CLK_ROOT_POST_DIV12,
+ CLK_ROOT_POST_DIV13,
+ CLK_ROOT_POST_DIV14,
+ CLK_ROOT_POST_DIV15,
+ CLK_ROOT_POST_DIV16,
+ CLK_ROOT_POST_DIV17,
+ CLK_ROOT_POST_DIV18,
+ CLK_ROOT_POST_DIV19,
+ CLK_ROOT_POST_DIV20,
+ CLK_ROOT_POST_DIV21,
+ CLK_ROOT_POST_DIV22,
+ CLK_ROOT_POST_DIV23,
+ CLK_ROOT_POST_DIV24,
+ CLK_ROOT_POST_DIV25,
+ CLK_ROOT_POST_DIV26,
+ CLK_ROOT_POST_DIV27,
+ CLK_ROOT_POST_DIV28,
+ CLK_ROOT_POST_DIV29,
+ CLK_ROOT_POST_DIV30,
+ CLK_ROOT_POST_DIV31,
+ CLK_ROOT_POST_DIV32,
+ CLK_ROOT_POST_DIV33,
+ CLK_ROOT_POST_DIV34,
+ CLK_ROOT_POST_DIV35,
+ CLK_ROOT_POST_DIV36,
+ CLK_ROOT_POST_DIV37,
+ CLK_ROOT_POST_DIV38,
+ CLK_ROOT_POST_DIV39,
+ CLK_ROOT_POST_DIV40,
+ CLK_ROOT_POST_DIV41,
+ CLK_ROOT_POST_DIV42,
+ CLK_ROOT_POST_DIV43,
+ CLK_ROOT_POST_DIV44,
+ CLK_ROOT_POST_DIV45,
+ CLK_ROOT_POST_DIV46,
+ CLK_ROOT_POST_DIV47,
+ CLK_ROOT_POST_DIV48,
+ CLK_ROOT_POST_DIV49,
+ CLK_ROOT_POST_DIV50,
+ CLK_ROOT_POST_DIV51,
+ CLK_ROOT_POST_DIV52,
+ CLK_ROOT_POST_DIV53,
+ CLK_ROOT_POST_DIV54,
+ CLK_ROOT_POST_DIV55,
+ CLK_ROOT_POST_DIV56,
+ CLK_ROOT_POST_DIV57,
+ CLK_ROOT_POST_DIV58,
+ CLK_ROOT_POST_DIV59,
+ CLK_ROOT_POST_DIV60,
+ CLK_ROOT_POST_DIV61,
+ CLK_ROOT_POST_DIV62,
+ CLK_ROOT_POST_DIV63,
+ CLK_ROOT_POST_DIV64,
+};
+
+enum root_auto_div {
+ CLK_ROOT_AUTO_DIV1 = 0,
+ CLK_ROOT_AUTO_DIV2,
+ CLK_ROOT_AUTO_DIV4,
+ CLK_ROOT_AUTO_DIV8,
+ CLK_ROOT_AUTO_DIV16,
+};
+
+int clock_set_src(enum clk_root_index clock_id, enum clk_root_src clock_src);
+int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src);
+int clock_set_prediv(enum clk_root_index clock_id, enum root_pre_div pre_div);
+int clock_get_prediv(enum clk_root_index clock_id, enum root_pre_div *pre_div);
+int clock_set_postdiv(enum clk_root_index clock_id, enum root_post_div div);
+int clock_get_postdiv(enum clk_root_index clock_id, enum root_post_div *div);
+int clock_set_autopostdiv(enum clk_root_index clock_id, enum root_auto_div div,
+ int auto_en);
+int clock_get_autopostdiv(enum clk_root_index clock_id, enum root_auto_div *div,
+ int *auto_en);
+int clock_get_target_val(enum clk_root_index clock_id, u32 *val);
+int clock_set_target_val(enum clk_root_index clock_id, u32 val);
+int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
+ enum root_post_div post_div, enum clk_root_src clock_src);
+int clock_root_enabled(enum clk_root_index clock_id);
+
+int clock_enable(enum clk_ccgr_index index, bool enable);
+#endif
diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h
new file mode 100644
index 0000000..d65d4d9
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/crm_regs.h
@@ -0,0 +1,2813 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * Author:
+ * Peng Fan <Peng.Fan@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ARCH_ARM_MACH_MX7_CCM_REGS_H__
+#define __ARCH_ARM_MACH_MX7_CCM_REGS_H__
+
+#include <asm/arch/imx-regs.h>
+#include <asm/io.h>
+
+#define CCM_GPR0_OFFSET 0x0
+#define CCM_OBSERVE0_OFFSET 0x0400
+#define CCM_SCTRL0_OFFSET 0x0800
+#define CCM_CCGR0_OFFSET 0x4000
+#define CCM_ROOT0_TARGET_OFFSET 0x8000
+
+#ifndef __ASSEMBLY__
+
+struct mxc_ccm_ccgr {
+ uint32_t ccgr;
+ uint32_t ccgr_set;
+ uint32_t ccgr_clr;
+ uint32_t ccgr_tog;
+};
+
+struct mxc_ccm_root_slice {
+ uint32_t target_root;
+ uint32_t target_root_set;
+ uint32_t target_root_clr;
+ uint32_t target_root_tog;
+ uint32_t reserved_0[4];
+ uint32_t post;
+ uint32_t post_root_set;
+ uint32_t post_root_clr;
+ uint32_t post_root_tog;
+ uint32_t pre;
+ uint32_t pre_root_set;
+ uint32_t pre_root_clr;
+ uint32_t pre_root_tog;
+ uint32_t reserved_1[12];
+ uint32_t access_ctrl;
+ uint32_t access_ctrl_root_set;
+ uint32_t access_ctrl_root_clr;
+ uint32_t access_ctrl_root_tog;
+};
+
+/** CCM - Peripheral register structure */
+struct mxc_ccm_reg {
+ uint32_t gpr0;
+ uint32_t gpr0_set;
+ uint32_t gpr0_clr;
+ uint32_t gpr0_tog;
+ uint32_t reserved_0[4092];
+ struct mxc_ccm_ccgr ccgr_array[191]; /* offset 0x4000 */
+ uint32_t reserved_1[3332];
+ struct mxc_ccm_root_slice root[121]; /* offset 0x8000 */
+
+};
+
+struct mxc_ccm_anatop_reg {
+ uint32_t ctrl_24m; /* offset 0x0000 */
+ uint32_t ctrl_24m_set;
+ uint32_t ctrl_24m_clr;
+ uint32_t ctrl_24m_tog;
+ uint32_t rcosc_config0; /* offset 0x0010 */
+ uint32_t rcosc_config0_set;
+ uint32_t rcosc_config0_clr;
+ uint32_t rcosc_config0_tog;
+ uint32_t rcosc_config1; /* offset 0x0020 */
+ uint32_t rcosc_config1_set;
+ uint32_t rcosc_config1_clr;
+ uint32_t rcosc_config1_tog;
+ uint32_t rcosc_config2; /* offset 0x0030 */
+ uint32_t rcosc_config2_set;
+ uint32_t rcosc_config2_clr;
+ uint32_t rcosc_config2_tog;
+ uint8_t reserved_0[16];
+ uint32_t osc_32k; /* offset 0x0050 */
+ uint32_t osc_32k_set;
+ uint32_t osc_32k_clr;
+ uint32_t osc_32k_tog;
+ uint32_t pll_arm; /* offset 0x0060 */
+ uint32_t pll_arm_set;
+ uint32_t pll_arm_clr;
+ uint32_t pll_arm_tog;
+ uint32_t pll_ddr; /* offset 0x0070 */
+ uint32_t pll_ddr_set;
+ uint32_t pll_ddr_clr;
+ uint32_t pll_ddr_tog;
+ uint32_t pll_ddr_ss; /* offset 0x0080 */
+ uint8_t reserved_1[12];
+ uint32_t pll_ddr_num; /* offset 0x0090 */
+ uint8_t reserved_2[12];
+ uint32_t pll_ddr_denom; /* offset 0x00a0 */
+ uint8_t reserved_3[12];
+ uint32_t pll_480; /* offset 0x00b0 */
+ uint32_t pll_480_set;
+ uint32_t pll_480_clr;
+ uint32_t pll_480_tog;
+ uint32_t pfd_480a; /* offset 0x00c0 */
+ uint32_t pfd_480a_set;
+ uint32_t pfd_480a_clr;
+ uint32_t pfd_480a_tog;
+ uint32_t pfd_480b; /* offset 0x00d0 */
+ uint32_t pfd_480b_set;
+ uint32_t pfd_480b_clr;
+ uint32_t pfd_480b_tog;
+ uint32_t pll_enet; /* offset 0x00e0 */
+ uint32_t pll_enet_set;
+ uint32_t pll_enet_clr;
+ uint32_t pll_enet_tog;
+ uint32_t pll_audio; /* offset 0x00f0 */
+ uint32_t pll_audio_set;
+ uint32_t pll_audio_clr;
+ uint32_t pll_audio_tog;
+ uint32_t pll_audio_ss; /* offset 0x0100 */
+ uint8_t reserved_4[12];
+ uint32_t pll_audio_num; /* offset 0x0110 */
+ uint8_t reserved_5[12];
+ uint32_t pll_audio_denom; /* offset 0x0120 */
+ uint8_t reserved_6[12];
+ uint32_t pll_video; /* offset 0x0130 */
+ uint32_t pll_video_set;
+ uint32_t pll_video_clr;
+ uint32_t pll_video_tog;
+ uint32_t pll_video_ss; /* offset 0x0140 */
+ uint8_t reserved_7[12];
+ uint32_t pll_video_num; /* offset 0x0150 */
+ uint8_t reserved_8[12];
+ uint32_t pll_video_denom; /* offset 0x0160 */
+ uint8_t reserved_9[12];
+ uint32_t clk_misc0; /* offset 0x0170 */
+ uint32_t clk_misc0_set;
+ uint32_t clk_misc0_clr;
+ uint32_t clk_misc0_tog;
+ uint32_t clk_rsvd; /* offset 0x0180 */
+ uint8_t reserved_10[124];
+ uint32_t reg_1p0a; /* offset 0x0200 */
+ uint32_t reg_1p0a_set;
+ uint32_t reg_1p0a_clr;
+ uint32_t reg_1p0a_tog;
+ uint32_t reg_1p0d; /* offsest 0x0210 */
+ uint32_t reg_1p0d_set;
+ uint32_t reg_1p0d_clr;
+ uint32_t reg_1p0d_tog;
+ uint32_t reg_hsic_1p2; /* offset 0x0220 */
+ uint32_t reg_hsic_1p2_set;
+ uint32_t reg_hsic_1p2_clr;
+ uint32_t reg_hsic_1p2_tog;
+ uint32_t reg_lpsr_1p0; /* offset 0x0230 */
+ uint32_t reg_lpsr_1p0_set;
+ uint32_t reg_lpsr_1p0_clr;
+ uint32_t reg_lpsr_1p0_tog;
+ uint32_t reg_3p0; /* offset 0x0240 */
+ uint32_t reg_3p0_set;
+ uint32_t reg_3p0_clr;
+ uint32_t reg_3p0_tog;
+ uint32_t reg_snvs; /* offset 0x0250 */
+ uint32_t reg_snvs_set;
+ uint32_t reg_snvs_clr;
+ uint32_t reg_snvs_tog;
+ uint32_t analog_debug_misc0; /* offset 0x0260 */
+ uint32_t analog_debug_misc0_set;
+ uint32_t analog_debug_misc0_clr;
+ uint32_t analog_debug_misc0_tog;
+ uint32_t ref; /* offset 0x0270 */
+ uint32_t ref_set;
+ uint32_t ref_clr;
+ uint32_t ref_tog;
+ uint8_t reserved_11[128];
+ uint32_t tempsense0; /* offset 0x0300 */
+ uint32_t tempsense0_set;
+ uint32_t tempsense0_clr;
+ uint32_t tempsense0_tog;
+ uint32_t tempsense1; /* offset 0x0310 */
+ uint32_t tempsense1_set;
+ uint32_t tempsense1_clr;
+ uint32_t tempsense1_tog;
+ uint32_t tempsense_trim; /* offset 0x0320 */
+ uint32_t tempsense_trim_set;
+ uint32_t tempsense_trim_clr;
+ uint32_t tempsense_trim_tog;
+ uint32_t lowpwr_ctrl; /* offset 0x0330 */
+ uint32_t lowpwr_ctrl_set;
+ uint32_t lowpwr_ctrl_clr;
+ uint32_t lowpwr_ctrl_tog;
+ uint32_t snvs_tamper_offset_ctrl; /* offset 0x0340 */
+ uint32_t snvs_tamper_offset_ctrl_set;
+ uint32_t snvs_tamper_offset_ctrl_clr;
+ uint32_t snvs_tamper_offset_ctrl_tog;
+ uint32_t snvs_tamper_pull_ctrl; /* offset 0x0350 */
+ uint32_t snvs_tamper_pull_ctrl_set;
+ uint32_t snvs_tamper_pull_ctrl_clr;
+ uint32_t snvs_tamper_pull_ctrl_tog;
+ uint32_t snvs_test; /* offset 0x0360 */
+ uint32_t snvs_test_set;
+ uint32_t snvs_test_clr;
+ uint32_t snvs_test_tog;
+ uint32_t snvs_tamper_trim_ctrl; /* offset 0x0370 */
+ uint32_t snvs_tamper_trim_ctrl_set;
+ uint32_t snvs_tamper_trim_ctrl_ctrl;
+ uint32_t snvs_tamper_trim_ctrl_tog;
+ uint32_t snvs_misc_ctrl; /* offset 0x0380 */
+ uint32_t snvs_misc_ctrl_set;
+ uint32_t snvs_misc_ctrl_clr;
+ uint32_t snvs_misc_ctrl_tog;
+ uint8_t reserved_12[112];
+ uint32_t misc; /* offset 0x0400 */
+ uint8_t reserved_13[252];
+ uint32_t adc0; /* offset 0x0500 */
+ uint8_t reserved_14[12];
+ uint32_t adc1; /* offset 0x0510 */
+ uint8_t reserved_15[748];
+ uint32_t digprog; /* offset 0x0800 */
+};
+#endif
+
+#define ANADIG_CLK_MISC0_PFD_480_AUTOGATE_EN_MASK (0x01 << 17)
+
+#define ANADIG_PLL_LOCK 0x80000000
+
+#define ANADIG_PLL_ARM_PWDN_MASK (0x01 << 12)
+#define ANADIG_PLL_480_PWDN_MASK (0x01 << 12)
+#define ANADIG_PLL_DDR_PWDN_MASK (0x01 << 20)
+#define ANADIG_PLL_ENET_PWDN_MASK (0x01 << 5)
+#define ANADIG_PLL_VIDEO_PWDN_MASK (0x01 << 12)
+
+
+#define ANATOP_PFD480B_PFD4_FRAC_MASK 0x0000003f
+#define ANATOP_PFD480B_PFD4_FRAC_320M_VAL 0x0000001B
+#define ANATOP_PFD480B_PFD4_FRAC_392M_VAL 0x00000016
+#define ANATOP_PFD480B_PFD4_FRAC_432M_VAL 0x00000014
+
+/* PLL_ARM Bit Fields */
+#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7F
+#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_ARM_HALF_LF_MASK 0x80
+#define CCM_ANALOG_PLL_ARM_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_MASK 0x100
+#define CCM_ANALOG_PLL_ARM_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_ARM_HALF_CP_MASK 0x200
+#define CCM_ANALOG_PLL_ARM_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_MASK 0x400
+#define CCM_ANALOG_PLL_ARM_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_MASK 0x800
+#define CCM_ANALOG_PLL_ARM_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK 0x1000
+#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_MASK 0x2000
+#define CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK 0xC000
+#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_ARM_BYPASS_MASK 0x10000
+#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_ARM_LVDS_SEL_MASK 0x20000
+#define CCM_ANALOG_PLL_ARM_LVDS_SEL_SHIFT 17
+#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_MASK 0x40000
+#define CCM_ANALOG_PLL_ARM_LVDS_24MHZ_SEL_SHIFT 18
+#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK 0x80000
+#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT 19
+#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_MASK 0x100000
+#define CCM_ANALOG_PLL_ARM_PLL_ARM_OVERRIDE_SHIFT 20
+#define CCM_ANALOG_PLL_ARM_RSVD0_MASK 0x7FE00000
+#define CCM_ANALOG_PLL_ARM_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_ARM_LOCK_MASK 0x80000000
+#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT 31
+
+/* PLL_DDR Bit Fields */
+#define CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK 0x7F
+#define CCM_ANALOG_PLL_DDR_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_DDR_HALF_LF_MASK 0x80
+#define CCM_ANALOG_PLL_DDR_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_MASK 0x100
+#define CCM_ANALOG_PLL_DDR_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_DDR_HALF_CP_MASK 0x200
+#define CCM_ANALOG_PLL_DDR_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_MASK 0x400
+#define CCM_ANALOG_PLL_DDR_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_MASK 0x800
+#define CCM_ANALOG_PLL_DDR_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_MASK 0x1000
+#define CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT 12
+#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_MASK 0x2000
+#define CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_MASK 0xC000
+#define CCM_ANALOG_PLL_DDR_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_DDR_BYPASS_MASK 0x10000
+#define CCM_ANALOG_PLL_DDR_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_MASK 0x20000
+#define CCM_ANALOG_PLL_DDR_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_MASK 0x40000
+#define CCM_ANALOG_PLL_DDR_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_MASK 0x80000
+#define CCM_ANALOG_PLL_DDR_PLL_DDR_OVERRIDE_SHIFT 19
+#define CCM_ANALOG_PLL_DDR_POWERDOWN_MASK 0x100000
+#define CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT 20
+#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK 0x600000
+#define CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT 21
+#define CCM_ANALOG_PLL_DDR_RSVD1_MASK 0x7F800000
+#define CCM_ANALOG_PLL_DDR_RSVD1_SHIFT 23
+#define CCM_ANALOG_PLL_DDR_LOCK_MASK 0x80000000
+#define CCM_ANALOG_PLL_DDR_LOCK_SHIFT 31
+
+/* PLL_480 Bit Fields */
+#define CCM_ANALOG_PLL_480_DIV_SELECT_MASK 0x1
+#define CCM_ANALOG_PLL_480_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_480_RSVD0_MASK 0xE
+#define CCM_ANALOG_PLL_480_RSVD0_SHIFT 1
+#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_MASK 0x10
+#define CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT 4
+#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_MASK 0x20
+#define CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT 5
+#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_MASK 0x40
+#define CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT 6
+#define CCM_ANALOG_PLL_480_HALF_LF_MASK 0x80
+#define CCM_ANALOG_PLL_480_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_480_DOUBLE_LF_MASK 0x100
+#define CCM_ANALOG_PLL_480_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_480_HALF_CP_MASK 0x200
+#define CCM_ANALOG_PLL_480_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_480_DOUBLE_CP_MASK 0x400
+#define CCM_ANALOG_PLL_480_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_MASK 0x800
+#define CCM_ANALOG_PLL_480_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_480_POWERDOWN_MASK 0x1000
+#define CCM_ANALOG_PLL_480_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_480_ENABLE_CLK_MASK 0x2000
+#define CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_MASK 0xC000
+#define CCM_ANALOG_PLL_480_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_480_BYPASS_MASK 0x10000
+#define CCM_ANALOG_PLL_480_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_MASK 0x20000
+#define CCM_ANALOG_PLL_480_PLL_480_OVERRIDE_SHIFT 17
+#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_MASK 0x40000
+#define CCM_ANALOG_PLL_480_PFD0_OVERRIDE_SHIFT 18
+#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_MASK 0x80000
+#define CCM_ANALOG_PLL_480_PFD1_OVERRIDE_SHIFT 19
+#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_MASK 0x100000
+#define CCM_ANALOG_PLL_480_PFD2_OVERRIDE_SHIFT 20
+#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_MASK 0x200000
+#define CCM_ANALOG_PLL_480_PFD3_OVERRIDE_SHIFT 21
+#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_MASK 0x400000
+#define CCM_ANALOG_PLL_480_PFD4_OVERRIDE_SHIFT 22
+#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_MASK 0x800000
+#define CCM_ANALOG_PLL_480_PFD5_OVERRIDE_SHIFT 23
+#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_MASK 0x1000000
+#define CCM_ANALOG_PLL_480_PFD6_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_MASK 0x2000000
+#define CCM_ANALOG_PLL_480_PFD7_OVERRIDE_SHIFT 25
+#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_MASK 0x4000000
+#define CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT 26
+#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_MASK 0x8000000
+#define CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT 27
+#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_MASK 0x10000000
+#define CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT 28
+#define CCM_ANALOG_PLL_480_RSVD1_MASK 0x60000000
+#define CCM_ANALOG_PLL_480_RSVD1_SHIFT 29
+#define CCM_ANALOG_PLL_480_LOCK_MASK 0x80000000
+#define CCM_ANALOG_PLL_480_LOCK_SHIFT 31
+
+/* PFD_480A Bit Fields */
+#define CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK 0x3F
+#define CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT 0
+#define CCM_ANALOG_PFD_480A_PFD0_STABLE_MASK 0x40
+#define CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT 6
+#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_MASK 0x80
+#define CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT 7
+#define CCM_ANALOG_PFD_480A_PFD1_FRAC_MASK 0x3F00
+#define CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT 8
+#define CCM_ANALOG_PFD_480A_PFD1_STABLE_MASK 0x4000
+#define CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT 14
+#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_MASK 0x8000
+#define CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT 15
+#define CCM_ANALOG_PFD_480A_PFD2_FRAC_MASK 0x3F0000
+#define CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT 16
+#define CCM_ANALOG_PFD_480A_PFD2_STABLE_MASK 0x400000
+#define CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT 22
+#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_MASK 0x800000
+#define CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT 23
+#define CCM_ANALOG_PFD_480A_PFD3_FRAC_MASK 0x3F000000
+#define CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT 24
+#define CCM_ANALOG_PFD_480A_PFD3_STABLE_MASK 0x40000000
+#define CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT 30
+#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_MASK 0x80000000
+#define CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT 31
+/* PFD_480B Bit Fields */
+#define CCM_ANALOG_PFD_480B_PFD4_FRAC_MASK 0x3F
+#define CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT 0
+#define CCM_ANALOG_PFD_480B_PFD4_STABLE_MASK 0x40
+#define CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT 6
+#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_MASK 0x80
+#define CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT 7
+#define CCM_ANALOG_PFD_480B_PFD5_FRAC_MASK 0x3F00
+#define CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT 8
+#define CCM_ANALOG_PFD_480B_PFD5_STABLE_MASK 0x4000
+#define CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT 14
+#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_MASK 0x8000
+#define CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT 15
+#define CCM_ANALOG_PFD_480B_PFD6_FRAC_MASK 0x3F0000
+#define CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT 16
+#define CCM_ANALOG_PFD_480B_PFD6_STABLE_MASK 0x400000
+#define CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT 22
+#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_MASK 0x800000
+#define CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT 23
+#define CCM_ANALOG_PFD_480B_PFD7_FRAC_MASK 0x3F000000
+#define CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT 24
+#define CCM_ANALOG_PFD_480B_PFD7_STABLE_MASK 0x40000000
+#define CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT 30
+#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_MASK 0x80000000
+#define CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT 31
+
+/* PLL_ENET Bit Fields */
+#define CCM_ANALOG_PLL_ENET_HALF_LF_MASK 0x1
+#define CCM_ANALOG_PLL_ENET_HALF_LF_SHIFT 0
+#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_MASK 0x2
+#define CCM_ANALOG_PLL_ENET_DOUBLE_LF_SHIFT 1
+#define CCM_ANALOG_PLL_ENET_HALF_CP_MASK 0x4
+#define CCM_ANALOG_PLL_ENET_HALF_CP_SHIFT 2
+#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_MASK 0x8
+#define CCM_ANALOG_PLL_ENET_DOUBLE_CP_SHIFT 3
+#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_MASK 0x10
+#define CCM_ANALOG_PLL_ENET_HOLD_RING_OFF_SHIFT 4
+#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK 0x20
+#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT 5
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_MASK 0x40
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT 6
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_MASK 0x80
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT 7
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_MASK 0x100
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT 8
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_MASK 0x200
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT 9
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_MASK 0x400
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT 10
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_MASK 0x800
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT 11
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_MASK 0x1000
+#define CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT 12
+#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_MASK 0x2000
+#define CCM_ANALOG_PLL_ENET_PLL_ENET_OVERRIDE_SHIFT 13
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK 0xC000
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_ENET_BYPASS_MASK 0x10000
+#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_MASK 0x20000
+#define CCM_ANALOG_PLL_ENET_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK 0x40000
+#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_ENET_RSVD1_MASK 0x7FF80000
+#define CCM_ANALOG_PLL_ENET_RSVD1_SHIFT 19
+#define CCM_ANALOG_PLL_ENET_LOCK_MASK 0x80000000
+#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT 31
+
+/* PLL_AUDIO Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_AUDIO_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_AUDIO_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_AUDIO_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_AUDIO_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_AUDIO_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_AUDIO_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_AUDIO_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_AUDIO_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_AUDIO_PLL_AUDIO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_AUDIO_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_AUDIO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_RSVD1_MASK)
+#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT 31
+/* PLL_AUDIO_SET Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_AUDIO_SET_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_AUDIO_SET_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_AUDIO_SET_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_AUDIO_SET_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_AUDIO_SET_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_AUDIO_SET_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_AUDIO_SET_PLL_AUDIO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_AUDIO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_SET_RSVD1_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT 31
+/* PLL_AUDIO_CLR Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_AUDIO_CLR_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_AUDIO_CLR_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_AUDIO_CLR_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_PLL_AUDIO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_AUDIO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_CLR_RSVD1_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT 31
+/* PLL_AUDIO_TOG Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_AUDIO_TOG_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_AUDIO_TOG_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_AUDIO_TOG_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_PLL_AUDIO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_AUDIO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_AUDIO_TOG_RSVD1_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT 31
+/* PLL_AUDIO_SS Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK 0x7FFFu
+#define CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK 0x8000u
+#define CCM_ANALOG_PLL_AUDIO_SS_ENABLE_SHIFT 15
+#define CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK 0xFFFF0000u
+#define CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT 16
+#define CCM_ANALOG_PLL_AUDIO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_AUDIO_SS_STOP_MASK)
+/* PLL_AUDIO_NUM Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK 0x3FFFFFFFu
+#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
+#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK 0xC0000000u
+#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT 30
+#define CCM_ANALOG_PLL_AUDIO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_NUM_RSVD0_MASK)
+/* PLL_AUDIO_DENOM Bit Fields */
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK 0x3FFFFFFFu
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT 0
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
+#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK 0xC0000000u
+#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT 30
+#define CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_AUDIO_DENOM_RSVD0_MASK)
+/* PLL_VIDEO Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_VIDEO_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_VIDEO_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_VIDEO_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_VIDEO_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_VIDEO_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_VIDEO_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_VIDEO_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_VIDEO_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_VIDEO_PLL_VIDEO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_VIDEO_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_VIDEO_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_RSVD1_MASK)
+#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT 31
+/* PLL_VIDEO_SET Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_VIDEO_SET_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_VIDEO_SET_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_VIDEO_SET_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_VIDEO_SET_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_VIDEO_SET_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_VIDEO_SET_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_VIDEO_SET_PLL_VIDEO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_VIDEO_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SET_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_SET_RSVD1_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT 31
+/* PLL_VIDEO_CLR Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_VIDEO_CLR_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_VIDEO_CLR_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_VIDEO_CLR_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_PLL_VIDEO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_VIDEO_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_CLR_RSVD1_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT 31
+/* PLL_VIDEO_TOG Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK 0x7Fu
+#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_MASK 0x80u
+#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_LF_SHIFT 7
+#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_MASK 0x100u
+#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_LF_SHIFT 8
+#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_MASK 0x200u
+#define CCM_ANALOG_PLL_VIDEO_TOG_HALF_CP_SHIFT 9
+#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_MASK 0x400u
+#define CCM_ANALOG_PLL_VIDEO_TOG_DOUBLE_CP_SHIFT 10
+#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_MASK 0x800u
+#define CCM_ANALOG_PLL_VIDEO_TOG_HOLD_RING_OFF_SHIFT 11
+#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK 0x1000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT 12
+#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_MASK 0x2000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_CLK_SHIFT 13
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK 0xC000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT 14
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK 0x10000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT 16
+#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_MASK 0x20000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_DITHER_ENABLE_SHIFT 17
+#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK 0x40000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT 18
+#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK 0x180000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT 19
+#define CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_TEST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_MASK 0x200000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD0_SHIFT 21
+#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK 0xC00000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT 22
+#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SEL_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_MASK 0x1000000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_PLL_VIDEO_OVERRIDE_SHIFT 24
+#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK 0x7E000000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT 25
+#define CCM_ANALOG_PLL_VIDEO_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_SHIFT))&CCM_ANALOG_PLL_VIDEO_TOG_RSVD1_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK 0x80000000u
+#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT 31
+/* PLL_VIDEO_SS Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK 0x7FFFu
+#define CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_SS_STEP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STEP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK 0x8000u
+#define CCM_ANALOG_PLL_VIDEO_SS_ENABLE_SHIFT 15
+#define CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK 0xFFFF0000u
+#define CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT 16
+#define CCM_ANALOG_PLL_VIDEO_SS_STOP(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_SS_STOP_SHIFT))&CCM_ANALOG_PLL_VIDEO_SS_STOP_MASK)
+/* PLL_VIDEO_NUM Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK 0x3FFFFFFFu
+#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
+#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK 0xC0000000u
+#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT 30
+#define CCM_ANALOG_PLL_VIDEO_NUM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_NUM_RSVD0_MASK)
+/* PLL_VIDEO_DENOM Bit Fields */
+#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK 0x3FFFFFFFu
+#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT 0
+#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
+#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK 0xC0000000u
+#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT 30
+#define CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_SHIFT))&CCM_ANALOG_PLL_VIDEO_DENOM_RSVD0_MASK)
+/* CLK_MISC0 Bit Fields */
+#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK 0x1Fu
+#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT 0
+#define CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_MASK 0x20u
+#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_OBEN_SHIFT 5
+#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_MASK 0x40u
+#define CCM_ANALOG_CLK_MISC0_LVDSCLK1_IBEN_SHIFT 6
+#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_MASK 0x80u
+#define CCM_ANALOG_CLK_MISC0_ACLK2_PREDIV_SHIFT 7
+#define CCM_ANALOG_CLK_MISC0_RSVD0_MASK 0xFFFFFF00u
+#define CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT 8
+#define CCM_ANALOG_CLK_MISC0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_RSVD0_MASK)
+/* CLK_MISC0_SET Bit Fields */
+#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK 0x1Fu
+#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT 0
+#define CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_MASK 0x20u
+#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_OBEN_SHIFT 5
+#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_MASK 0x40u
+#define CCM_ANALOG_CLK_MISC0_SET_LVDSCLK1_IBEN_SHIFT 6
+#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_MASK 0x80u
+#define CCM_ANALOG_CLK_MISC0_SET_ACLK2_PREDIV_SHIFT 7
+#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK 0xFFFFFF00u
+#define CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT 8
+#define CCM_ANALOG_CLK_MISC0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_SET_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_SET_RSVD0_MASK)
+/* CLK_MISC0_CLR Bit Fields */
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK 0x1Fu
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT 0
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_MASK 0x20u
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_OBEN_SHIFT 5
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_MASK 0x40u
+#define CCM_ANALOG_CLK_MISC0_CLR_LVDSCLK1_IBEN_SHIFT 6
+#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_MASK 0x80u
+#define CCM_ANALOG_CLK_MISC0_CLR_ACLK2_PREDIV_SHIFT 7
+#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK 0xFFFFFF00u
+#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT 8
+#define CCM_ANALOG_CLK_MISC0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_CLR_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_CLR_RSVD0_MASK)
+/* CLK_MISC0_TOG Bit Fields */
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK 0x1Fu
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT 0
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_MASK 0x20u
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_OBEN_SHIFT 5
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_MASK 0x40u
+#define CCM_ANALOG_CLK_MISC0_TOG_LVDSCLK1_IBEN_SHIFT 6
+#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_MASK 0x80u
+#define CCM_ANALOG_CLK_MISC0_TOG_ACLK2_PREDIV_SHIFT 7
+#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK 0xFFFFFF00u
+#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT 8
+#define CCM_ANALOG_CLK_MISC0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<CCM_ANALOG_CLK_MISC0_TOG_RSVD0_SHIFT))&CCM_ANALOG_CLK_MISC0_TOG_RSVD0_MASK)
+
+/* REG_1P0A Bit Fields */
+#define PMU_REG_1P0A_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0A_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0A_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0A_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0A_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0A_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0A_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0A_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0A_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0A_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_BO_OFFSET_SHIFT))&PMU_REG_1P0A_BO_OFFSET_MASK)
+#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0A_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0A_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0A_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0A_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0A_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0A_RSVD0_SHIFT 13
+#define PMU_REG_1P0A_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD0_SHIFT))&PMU_REG_1P0A_RSVD0_MASK)
+#define PMU_REG_1P0A_BO_MASK 0x10000u
+#define PMU_REG_1P0A_BO_SHIFT 16
+#define PMU_REG_1P0A_OK_MASK 0x20000u
+#define PMU_REG_1P0A_OK_SHIFT 17
+#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0A_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0A_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0A_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0A_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0A_REG_TEST_SHIFT 20
+#define PMU_REG_1P0A_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_REG_TEST_SHIFT))&PMU_REG_1P0A_REG_TEST_MASK)
+#define PMU_REG_1P0A_RSVD1_MASK 0xFF000000u
+#define PMU_REG_1P0A_RSVD1_SHIFT 24
+#define PMU_REG_1P0A_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_RSVD1_SHIFT))&PMU_REG_1P0A_RSVD1_MASK)
+/* REG_1P0A_SET Bit Fields */
+#define PMU_REG_1P0A_SET_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0A_SET_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0A_SET_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0A_SET_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0A_SET_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0A_SET_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0A_SET_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0A_SET_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0A_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0A_SET_BO_OFFSET_MASK)
+#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0A_SET_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0A_SET_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0A_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_SET_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0A_SET_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0A_SET_RSVD0_SHIFT 13
+#define PMU_REG_1P0A_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD0_SHIFT))&PMU_REG_1P0A_SET_RSVD0_MASK)
+#define PMU_REG_1P0A_SET_BO_MASK 0x10000u
+#define PMU_REG_1P0A_SET_BO_SHIFT 16
+#define PMU_REG_1P0A_SET_OK_MASK 0x20000u
+#define PMU_REG_1P0A_SET_OK_SHIFT 17
+#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0A_SET_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0A_SET_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0A_SET_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0A_SET_REG_TEST_SHIFT 20
+#define PMU_REG_1P0A_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_REG_TEST_SHIFT))&PMU_REG_1P0A_SET_REG_TEST_MASK)
+#define PMU_REG_1P0A_SET_RSVD1_MASK 0xFF000000u
+#define PMU_REG_1P0A_SET_RSVD1_SHIFT 24
+#define PMU_REG_1P0A_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_SET_RSVD1_SHIFT))&PMU_REG_1P0A_SET_RSVD1_MASK)
+/* REG_1P0A_CLR Bit Fields */
+#define PMU_REG_1P0A_CLR_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0A_CLR_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0A_CLR_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0A_CLR_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0A_CLR_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0A_CLR_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0A_CLR_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0A_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0A_CLR_BO_OFFSET_MASK)
+#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0A_CLR_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0A_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_CLR_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0A_CLR_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0A_CLR_RSVD0_SHIFT 13
+#define PMU_REG_1P0A_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD0_SHIFT))&PMU_REG_1P0A_CLR_RSVD0_MASK)
+#define PMU_REG_1P0A_CLR_BO_MASK 0x10000u
+#define PMU_REG_1P0A_CLR_BO_SHIFT 16
+#define PMU_REG_1P0A_CLR_OK_MASK 0x20000u
+#define PMU_REG_1P0A_CLR_OK_SHIFT 17
+#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0A_CLR_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0A_CLR_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0A_CLR_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0A_CLR_REG_TEST_SHIFT 20
+#define PMU_REG_1P0A_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_REG_TEST_SHIFT))&PMU_REG_1P0A_CLR_REG_TEST_MASK)
+#define PMU_REG_1P0A_CLR_RSVD1_MASK 0xFF000000u
+#define PMU_REG_1P0A_CLR_RSVD1_SHIFT 24
+#define PMU_REG_1P0A_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_CLR_RSVD1_SHIFT))&PMU_REG_1P0A_CLR_RSVD1_MASK)
+/* REG_1P0A_TOG Bit Fields */
+#define PMU_REG_1P0A_TOG_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0A_TOG_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0A_TOG_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0A_TOG_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0A_TOG_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0A_TOG_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0A_TOG_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0A_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0A_TOG_BO_OFFSET_MASK)
+#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0A_TOG_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0A_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0A_TOG_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0A_TOG_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0A_TOG_RSVD0_SHIFT 13
+#define PMU_REG_1P0A_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD0_SHIFT))&PMU_REG_1P0A_TOG_RSVD0_MASK)
+#define PMU_REG_1P0A_TOG_BO_MASK 0x10000u
+#define PMU_REG_1P0A_TOG_BO_SHIFT 16
+#define PMU_REG_1P0A_TOG_OK_MASK 0x20000u
+#define PMU_REG_1P0A_TOG_OK_SHIFT 17
+#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0A_TOG_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0A_TOG_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0A_TOG_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0A_TOG_REG_TEST_SHIFT 20
+#define PMU_REG_1P0A_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_REG_TEST_SHIFT))&PMU_REG_1P0A_TOG_REG_TEST_MASK)
+#define PMU_REG_1P0A_TOG_RSVD1_MASK 0xFF000000u
+#define PMU_REG_1P0A_TOG_RSVD1_SHIFT 24
+#define PMU_REG_1P0A_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0A_TOG_RSVD1_SHIFT))&PMU_REG_1P0A_TOG_RSVD1_MASK)
+/* REG_1P0D Bit Fields */
+#define PMU_REG_1P0D_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0D_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0D_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0D_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0D_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0D_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0D_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0D_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0D_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0D_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0D_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_BO_OFFSET_SHIFT))&PMU_REG_1P0D_BO_OFFSET_MASK)
+#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0D_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0D_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0D_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0D_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0D_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0D_RSVD0_SHIFT 13
+#define PMU_REG_1P0D_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD0_SHIFT))&PMU_REG_1P0D_RSVD0_MASK)
+#define PMU_REG_1P0D_BO_MASK 0x10000u
+#define PMU_REG_1P0D_BO_SHIFT 16
+#define PMU_REG_1P0D_OK_MASK 0x20000u
+#define PMU_REG_1P0D_OK_SHIFT 17
+#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0D_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0D_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0D_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0D_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0D_REG_TEST_SHIFT 20
+#define PMU_REG_1P0D_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_REG_TEST_SHIFT))&PMU_REG_1P0D_REG_TEST_MASK)
+#define PMU_REG_1P0D_RSVD1_MASK 0x7F000000u
+#define PMU_REG_1P0D_RSVD1_SHIFT 24
+#define PMU_REG_1P0D_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_RSVD1_SHIFT))&PMU_REG_1P0D_RSVD1_MASK)
+#define PMU_REG_1P0D_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_1P0D_OVERRIDE_SHIFT 31
+/* REG_1P0D_SET Bit Fields */
+#define PMU_REG_1P0D_SET_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0D_SET_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0D_SET_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0D_SET_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0D_SET_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0D_SET_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0D_SET_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0D_SET_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0D_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_BO_OFFSET_SHIFT))&PMU_REG_1P0D_SET_BO_OFFSET_MASK)
+#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0D_SET_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0D_SET_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0D_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_SET_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0D_SET_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0D_SET_RSVD0_SHIFT 13
+#define PMU_REG_1P0D_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD0_SHIFT))&PMU_REG_1P0D_SET_RSVD0_MASK)
+#define PMU_REG_1P0D_SET_BO_MASK 0x10000u
+#define PMU_REG_1P0D_SET_BO_SHIFT 16
+#define PMU_REG_1P0D_SET_OK_MASK 0x20000u
+#define PMU_REG_1P0D_SET_OK_SHIFT 17
+#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0D_SET_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0D_SET_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0D_SET_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0D_SET_REG_TEST_SHIFT 20
+#define PMU_REG_1P0D_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_REG_TEST_SHIFT))&PMU_REG_1P0D_SET_REG_TEST_MASK)
+#define PMU_REG_1P0D_SET_RSVD1_MASK 0x7F000000u
+#define PMU_REG_1P0D_SET_RSVD1_SHIFT 24
+#define PMU_REG_1P0D_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_SET_RSVD1_SHIFT))&PMU_REG_1P0D_SET_RSVD1_MASK)
+#define PMU_REG_1P0D_SET_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_1P0D_SET_OVERRIDE_SHIFT 31
+/* REG_1P0D_CLR Bit Fields */
+#define PMU_REG_1P0D_CLR_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0D_CLR_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0D_CLR_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0D_CLR_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0D_CLR_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0D_CLR_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0D_CLR_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0D_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_BO_OFFSET_SHIFT))&PMU_REG_1P0D_CLR_BO_OFFSET_MASK)
+#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0D_CLR_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0D_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_CLR_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0D_CLR_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0D_CLR_RSVD0_SHIFT 13
+#define PMU_REG_1P0D_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD0_SHIFT))&PMU_REG_1P0D_CLR_RSVD0_MASK)
+#define PMU_REG_1P0D_CLR_BO_MASK 0x10000u
+#define PMU_REG_1P0D_CLR_BO_SHIFT 16
+#define PMU_REG_1P0D_CLR_OK_MASK 0x20000u
+#define PMU_REG_1P0D_CLR_OK_SHIFT 17
+#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0D_CLR_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0D_CLR_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0D_CLR_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0D_CLR_REG_TEST_SHIFT 20
+#define PMU_REG_1P0D_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_REG_TEST_SHIFT))&PMU_REG_1P0D_CLR_REG_TEST_MASK)
+#define PMU_REG_1P0D_CLR_RSVD1_MASK 0x7F000000u
+#define PMU_REG_1P0D_CLR_RSVD1_SHIFT 24
+#define PMU_REG_1P0D_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_CLR_RSVD1_SHIFT))&PMU_REG_1P0D_CLR_RSVD1_MASK)
+#define PMU_REG_1P0D_CLR_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_1P0D_CLR_OVERRIDE_SHIFT 31
+/* REG_1P0D_TOG Bit Fields */
+#define PMU_REG_1P0D_TOG_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_1P0D_TOG_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_1P0D_TOG_ENABLE_BO_MASK 0x2u
+#define PMU_REG_1P0D_TOG_ENABLE_BO_SHIFT 1
+#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_1P0D_TOG_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_1P0D_TOG_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_1P0D_TOG_BO_OFFSET_MASK 0x70u
+#define PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT 4
+#define PMU_REG_1P0D_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_BO_OFFSET_SHIFT))&PMU_REG_1P0D_TOG_BO_OFFSET_MASK)
+#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_1P0D_TOG_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_1P0D_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_1P0D_TOG_OUTPUT_TRG_MASK)
+#define PMU_REG_1P0D_TOG_RSVD0_MASK 0xE000u
+#define PMU_REG_1P0D_TOG_RSVD0_SHIFT 13
+#define PMU_REG_1P0D_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD0_SHIFT))&PMU_REG_1P0D_TOG_RSVD0_MASK)
+#define PMU_REG_1P0D_TOG_BO_MASK 0x10000u
+#define PMU_REG_1P0D_TOG_BO_SHIFT 16
+#define PMU_REG_1P0D_TOG_OK_MASK 0x20000u
+#define PMU_REG_1P0D_TOG_OK_SHIFT 17
+#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_1P0D_TOG_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_1P0D_TOG_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_1P0D_TOG_REG_TEST_MASK 0xF00000u
+#define PMU_REG_1P0D_TOG_REG_TEST_SHIFT 20
+#define PMU_REG_1P0D_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_REG_TEST_SHIFT))&PMU_REG_1P0D_TOG_REG_TEST_MASK)
+#define PMU_REG_1P0D_TOG_RSVD1_MASK 0x7F000000u
+#define PMU_REG_1P0D_TOG_RSVD1_SHIFT 24
+#define PMU_REG_1P0D_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_1P0D_TOG_RSVD1_SHIFT))&PMU_REG_1P0D_TOG_RSVD1_MASK)
+#define PMU_REG_1P0D_TOG_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_1P0D_TOG_OVERRIDE_SHIFT 31
+/* REG_HSIC_1P2 Bit Fields */
+#define PMU_REG_HSIC_1P2_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_HSIC_1P2_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_HSIC_1P2_ENABLE_BO_MASK 0x2u
+#define PMU_REG_HSIC_1P2_ENABLE_BO_SHIFT 1
+#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_HSIC_1P2_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_HSIC_1P2_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_HSIC_1P2_BO_OFFSET_MASK 0x70u
+#define PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT 4
+#define PMU_REG_HSIC_1P2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_BO_OFFSET_MASK)
+#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_HSIC_1P2_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_HSIC_1P2_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_OUTPUT_TRG_MASK)
+#define PMU_REG_HSIC_1P2_RSVD0_MASK 0xE000u
+#define PMU_REG_HSIC_1P2_RSVD0_SHIFT 13
+#define PMU_REG_HSIC_1P2_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_RSVD0_MASK)
+#define PMU_REG_HSIC_1P2_BO_MASK 0x10000u
+#define PMU_REG_HSIC_1P2_BO_SHIFT 16
+#define PMU_REG_HSIC_1P2_OK_MASK 0x20000u
+#define PMU_REG_HSIC_1P2_OK_SHIFT 17
+#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_HSIC_1P2_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_HSIC_1P2_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_HSIC_1P2_REG_TEST_MASK 0xF00000u
+#define PMU_REG_HSIC_1P2_REG_TEST_SHIFT 20
+#define PMU_REG_HSIC_1P2_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_REG_TEST_MASK)
+#define PMU_REG_HSIC_1P2_RSVD1_MASK 0x7F000000u
+#define PMU_REG_HSIC_1P2_RSVD1_SHIFT 24
+#define PMU_REG_HSIC_1P2_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_RSVD1_MASK)
+#define PMU_REG_HSIC_1P2_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_HSIC_1P2_OVERRIDE_SHIFT 31
+/* REG_HSIC_1P2_SET Bit Fields */
+#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_MASK 0x2u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_BO_SHIFT 1
+#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK 0x70u
+#define PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT 4
+#define PMU_REG_HSIC_1P2_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_SET_BO_OFFSET_MASK)
+#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_HSIC_1P2_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_SET_OUTPUT_TRG_MASK)
+#define PMU_REG_HSIC_1P2_SET_RSVD0_MASK 0xE000u
+#define PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT 13
+#define PMU_REG_HSIC_1P2_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD0_MASK)
+#define PMU_REG_HSIC_1P2_SET_BO_MASK 0x10000u
+#define PMU_REG_HSIC_1P2_SET_BO_SHIFT 16
+#define PMU_REG_HSIC_1P2_SET_OK_MASK 0x20000u
+#define PMU_REG_HSIC_1P2_SET_OK_SHIFT 17
+#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_HSIC_1P2_SET_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_HSIC_1P2_SET_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_HSIC_1P2_SET_REG_TEST_MASK 0xF00000u
+#define PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT 20
+#define PMU_REG_HSIC_1P2_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_SET_REG_TEST_MASK)
+#define PMU_REG_HSIC_1P2_SET_RSVD1_MASK 0x7F000000u
+#define PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT 24
+#define PMU_REG_HSIC_1P2_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_SET_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_SET_RSVD1_MASK)
+#define PMU_REG_HSIC_1P2_SET_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_HSIC_1P2_SET_OVERRIDE_SHIFT 31
+/* REG_HSIC_1P2_CLR Bit Fields */
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_MASK 0x2u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_BO_SHIFT 1
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK 0x70u
+#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT 4
+#define PMU_REG_HSIC_1P2_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_CLR_BO_OFFSET_MASK)
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_CLR_OUTPUT_TRG_MASK)
+#define PMU_REG_HSIC_1P2_CLR_RSVD0_MASK 0xE000u
+#define PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT 13
+#define PMU_REG_HSIC_1P2_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD0_MASK)
+#define PMU_REG_HSIC_1P2_CLR_BO_MASK 0x10000u
+#define PMU_REG_HSIC_1P2_CLR_BO_SHIFT 16
+#define PMU_REG_HSIC_1P2_CLR_OK_MASK 0x20000u
+#define PMU_REG_HSIC_1P2_CLR_OK_SHIFT 17
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_HSIC_1P2_CLR_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_HSIC_1P2_CLR_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK 0xF00000u
+#define PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT 20
+#define PMU_REG_HSIC_1P2_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_CLR_REG_TEST_MASK)
+#define PMU_REG_HSIC_1P2_CLR_RSVD1_MASK 0x7F000000u
+#define PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT 24
+#define PMU_REG_HSIC_1P2_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_CLR_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_CLR_RSVD1_MASK)
+#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_HSIC_1P2_CLR_OVERRIDE_SHIFT 31
+/* REG_HSIC_1P2_TOG Bit Fields */
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_MASK 0x2u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_BO_SHIFT 1
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK 0x70u
+#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT 4
+#define PMU_REG_HSIC_1P2_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_BO_OFFSET_SHIFT))&PMU_REG_HSIC_1P2_TOG_BO_OFFSET_MASK)
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_HSIC_1P2_TOG_OUTPUT_TRG_MASK)
+#define PMU_REG_HSIC_1P2_TOG_RSVD0_MASK 0xE000u
+#define PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT 13
+#define PMU_REG_HSIC_1P2_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD0_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD0_MASK)
+#define PMU_REG_HSIC_1P2_TOG_BO_MASK 0x10000u
+#define PMU_REG_HSIC_1P2_TOG_BO_SHIFT 16
+#define PMU_REG_HSIC_1P2_TOG_OK_MASK 0x20000u
+#define PMU_REG_HSIC_1P2_TOG_OK_SHIFT 17
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_HSIC_1P2_TOG_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_HSIC_1P2_TOG_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK 0xF00000u
+#define PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT 20
+#define PMU_REG_HSIC_1P2_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_REG_TEST_SHIFT))&PMU_REG_HSIC_1P2_TOG_REG_TEST_MASK)
+#define PMU_REG_HSIC_1P2_TOG_RSVD1_MASK 0x7F000000u
+#define PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT 24
+#define PMU_REG_HSIC_1P2_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_HSIC_1P2_TOG_RSVD1_SHIFT))&PMU_REG_HSIC_1P2_TOG_RSVD1_MASK)
+#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_MASK 0x80000000u
+#define PMU_REG_HSIC_1P2_TOG_OVERRIDE_SHIFT 31
+/* REG_LPSR_1P0 Bit Fields */
+#define PMU_REG_LPSR_1P0_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_LPSR_1P0_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_LPSR_1P0_ENABLE_BO_MASK 0x2u
+#define PMU_REG_LPSR_1P0_ENABLE_BO_SHIFT 1
+#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_LPSR_1P0_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_LPSR_1P0_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_LPSR_1P0_BO_OFFSET_MASK 0x70u
+#define PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT 4
+#define PMU_REG_LPSR_1P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_BO_OFFSET_MASK)
+#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_LPSR_1P0_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_LPSR_1P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_OUTPUT_TRG_MASK)
+#define PMU_REG_LPSR_1P0_RSVD0_MASK 0xE000u
+#define PMU_REG_LPSR_1P0_RSVD0_SHIFT 13
+#define PMU_REG_LPSR_1P0_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_RSVD0_MASK)
+#define PMU_REG_LPSR_1P0_BO_MASK 0x10000u
+#define PMU_REG_LPSR_1P0_BO_SHIFT 16
+#define PMU_REG_LPSR_1P0_OK_MASK 0x20000u
+#define PMU_REG_LPSR_1P0_OK_SHIFT 17
+#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_LPSR_1P0_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_LPSR_1P0_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_LPSR_1P0_REG_TEST_MASK 0xF00000u
+#define PMU_REG_LPSR_1P0_REG_TEST_SHIFT 20
+#define PMU_REG_LPSR_1P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_REG_TEST_MASK)
+#define PMU_REG_LPSR_1P0_RSVD1_MASK 0xFF000000u
+#define PMU_REG_LPSR_1P0_RSVD1_SHIFT 24
+#define PMU_REG_LPSR_1P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_RSVD1_MASK)
+/* REG_LPSR_1P0_SET Bit Fields */
+#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_MASK 0x2u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_BO_SHIFT 1
+#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK 0x70u
+#define PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT 4
+#define PMU_REG_LPSR_1P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_SET_BO_OFFSET_MASK)
+#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_LPSR_1P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_SET_OUTPUT_TRG_MASK)
+#define PMU_REG_LPSR_1P0_SET_RSVD0_MASK 0xE000u
+#define PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT 13
+#define PMU_REG_LPSR_1P0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD0_MASK)
+#define PMU_REG_LPSR_1P0_SET_BO_MASK 0x10000u
+#define PMU_REG_LPSR_1P0_SET_BO_SHIFT 16
+#define PMU_REG_LPSR_1P0_SET_OK_MASK 0x20000u
+#define PMU_REG_LPSR_1P0_SET_OK_SHIFT 17
+#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_LPSR_1P0_SET_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_LPSR_1P0_SET_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_LPSR_1P0_SET_REG_TEST_MASK 0xF00000u
+#define PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT 20
+#define PMU_REG_LPSR_1P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_SET_REG_TEST_MASK)
+#define PMU_REG_LPSR_1P0_SET_RSVD1_MASK 0xFF000000u
+#define PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT 24
+#define PMU_REG_LPSR_1P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_SET_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_SET_RSVD1_MASK)
+/* REG_LPSR_1P0_CLR Bit Fields */
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_MASK 0x2u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_BO_SHIFT 1
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK 0x70u
+#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT 4
+#define PMU_REG_LPSR_1P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_CLR_BO_OFFSET_MASK)
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_CLR_OUTPUT_TRG_MASK)
+#define PMU_REG_LPSR_1P0_CLR_RSVD0_MASK 0xE000u
+#define PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT 13
+#define PMU_REG_LPSR_1P0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD0_MASK)
+#define PMU_REG_LPSR_1P0_CLR_BO_MASK 0x10000u
+#define PMU_REG_LPSR_1P0_CLR_BO_SHIFT 16
+#define PMU_REG_LPSR_1P0_CLR_OK_MASK 0x20000u
+#define PMU_REG_LPSR_1P0_CLR_OK_SHIFT 17
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_LPSR_1P0_CLR_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_LPSR_1P0_CLR_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK 0xF00000u
+#define PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT 20
+#define PMU_REG_LPSR_1P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_CLR_REG_TEST_MASK)
+#define PMU_REG_LPSR_1P0_CLR_RSVD1_MASK 0xFF000000u
+#define PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT 24
+#define PMU_REG_LPSR_1P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_CLR_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_CLR_RSVD1_MASK)
+/* REG_LPSR_1P0_TOG Bit Fields */
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_MASK 0x2u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_BO_SHIFT 1
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_MASK 0x8u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_PULLDOWN_SHIFT 3
+#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK 0x70u
+#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT 4
+#define PMU_REG_LPSR_1P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_LPSR_1P0_TOG_BO_OFFSET_MASK)
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_MASK 0x80u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_PWRUPLOAD_SHIFT 7
+#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_LPSR_1P0_TOG_OUTPUT_TRG_MASK)
+#define PMU_REG_LPSR_1P0_TOG_RSVD0_MASK 0xE000u
+#define PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT 13
+#define PMU_REG_LPSR_1P0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD0_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD0_MASK)
+#define PMU_REG_LPSR_1P0_TOG_BO_MASK 0x10000u
+#define PMU_REG_LPSR_1P0_TOG_BO_SHIFT 16
+#define PMU_REG_LPSR_1P0_TOG_OK_MASK 0x20000u
+#define PMU_REG_LPSR_1P0_TOG_OK_SHIFT 17
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_MASK 0x40000u
+#define PMU_REG_LPSR_1P0_TOG_ENABLE_WEAK_LINREG_SHIFT 18
+#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_MASK 0x80000u
+#define PMU_REG_LPSR_1P0_TOG_SELREF_WEAK_LINREG_SHIFT 19
+#define PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK 0xF00000u
+#define PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT 20
+#define PMU_REG_LPSR_1P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_REG_TEST_SHIFT))&PMU_REG_LPSR_1P0_TOG_REG_TEST_MASK)
+#define PMU_REG_LPSR_1P0_TOG_RSVD1_MASK 0xFF000000u
+#define PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT 24
+#define PMU_REG_LPSR_1P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_LPSR_1P0_TOG_RSVD1_SHIFT))&PMU_REG_LPSR_1P0_TOG_RSVD1_MASK)
+/* REG_3P0 Bit Fields */
+#define PMU_REG_3P0_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_3P0_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_3P0_ENABLE_BO_MASK 0x2u
+#define PMU_REG_3P0_ENABLE_BO_SHIFT 1
+#define PMU_REG_3P0_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_3P0_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_3P0_RSVD0_MASK 0x8u
+#define PMU_REG_3P0_RSVD0_SHIFT 3
+#define PMU_REG_3P0_BO_OFFSET_MASK 0x70u
+#define PMU_REG_3P0_BO_OFFSET_SHIFT 4
+#define PMU_REG_3P0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_BO_OFFSET_SHIFT))&PMU_REG_3P0_BO_OFFSET_MASK)
+#define PMU_REG_3P0_VBUS_SEL_MASK 0x80u
+#define PMU_REG_3P0_VBUS_SEL_SHIFT 7
+#define PMU_REG_3P0_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_3P0_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_3P0_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_OUTPUT_TRG_MASK)
+#define PMU_REG_3P0_RSVD1_MASK 0xE000u
+#define PMU_REG_3P0_RSVD1_SHIFT 13
+#define PMU_REG_3P0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD1_SHIFT))&PMU_REG_3P0_RSVD1_MASK)
+#define PMU_REG_3P0_BO_VDD3P0_MASK 0x10000u
+#define PMU_REG_3P0_BO_VDD3P0_SHIFT 16
+#define PMU_REG_3P0_OK_VDD3P0_MASK 0x20000u
+#define PMU_REG_3P0_OK_VDD3P0_SHIFT 17
+#define PMU_REG_3P0_REG_TEST_MASK 0x3C0000u
+#define PMU_REG_3P0_REG_TEST_SHIFT 18
+#define PMU_REG_3P0_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_REG_TEST_SHIFT))&PMU_REG_3P0_REG_TEST_MASK)
+#define PMU_REG_3P0_RSVD2_MASK 0xFFC00000u
+#define PMU_REG_3P0_RSVD2_SHIFT 22
+#define PMU_REG_3P0_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_RSVD2_SHIFT))&PMU_REG_3P0_RSVD2_MASK)
+/* REG_3P0_SET Bit Fields */
+#define PMU_REG_3P0_SET_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_3P0_SET_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_3P0_SET_ENABLE_BO_MASK 0x2u
+#define PMU_REG_3P0_SET_ENABLE_BO_SHIFT 1
+#define PMU_REG_3P0_SET_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_3P0_SET_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_3P0_SET_RSVD0_MASK 0x8u
+#define PMU_REG_3P0_SET_RSVD0_SHIFT 3
+#define PMU_REG_3P0_SET_BO_OFFSET_MASK 0x70u
+#define PMU_REG_3P0_SET_BO_OFFSET_SHIFT 4
+#define PMU_REG_3P0_SET_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_BO_OFFSET_SHIFT))&PMU_REG_3P0_SET_BO_OFFSET_MASK)
+#define PMU_REG_3P0_SET_VBUS_SEL_MASK 0x80u
+#define PMU_REG_3P0_SET_VBUS_SEL_SHIFT 7
+#define PMU_REG_3P0_SET_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_3P0_SET_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_SET_OUTPUT_TRG_MASK)
+#define PMU_REG_3P0_SET_RSVD1_MASK 0xE000u
+#define PMU_REG_3P0_SET_RSVD1_SHIFT 13
+#define PMU_REG_3P0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD1_SHIFT))&PMU_REG_3P0_SET_RSVD1_MASK)
+#define PMU_REG_3P0_SET_BO_VDD3P0_MASK 0x10000u
+#define PMU_REG_3P0_SET_BO_VDD3P0_SHIFT 16
+#define PMU_REG_3P0_SET_OK_VDD3P0_MASK 0x20000u
+#define PMU_REG_3P0_SET_OK_VDD3P0_SHIFT 17
+#define PMU_REG_3P0_SET_REG_TEST_MASK 0x3C0000u
+#define PMU_REG_3P0_SET_REG_TEST_SHIFT 18
+#define PMU_REG_3P0_SET_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_REG_TEST_SHIFT))&PMU_REG_3P0_SET_REG_TEST_MASK)
+#define PMU_REG_3P0_SET_RSVD2_MASK 0xFFC00000u
+#define PMU_REG_3P0_SET_RSVD2_SHIFT 22
+#define PMU_REG_3P0_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_SET_RSVD2_SHIFT))&PMU_REG_3P0_SET_RSVD2_MASK)
+/* REG_3P0_CLR Bit Fields */
+#define PMU_REG_3P0_CLR_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_3P0_CLR_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_3P0_CLR_ENABLE_BO_MASK 0x2u
+#define PMU_REG_3P0_CLR_ENABLE_BO_SHIFT 1
+#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_3P0_CLR_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_3P0_CLR_RSVD0_MASK 0x8u
+#define PMU_REG_3P0_CLR_RSVD0_SHIFT 3
+#define PMU_REG_3P0_CLR_BO_OFFSET_MASK 0x70u
+#define PMU_REG_3P0_CLR_BO_OFFSET_SHIFT 4
+#define PMU_REG_3P0_CLR_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_BO_OFFSET_SHIFT))&PMU_REG_3P0_CLR_BO_OFFSET_MASK)
+#define PMU_REG_3P0_CLR_VBUS_SEL_MASK 0x80u
+#define PMU_REG_3P0_CLR_VBUS_SEL_SHIFT 7
+#define PMU_REG_3P0_CLR_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_3P0_CLR_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_CLR_OUTPUT_TRG_MASK)
+#define PMU_REG_3P0_CLR_RSVD1_MASK 0xE000u
+#define PMU_REG_3P0_CLR_RSVD1_SHIFT 13
+#define PMU_REG_3P0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD1_SHIFT))&PMU_REG_3P0_CLR_RSVD1_MASK)
+#define PMU_REG_3P0_CLR_BO_VDD3P0_MASK 0x10000u
+#define PMU_REG_3P0_CLR_BO_VDD3P0_SHIFT 16
+#define PMU_REG_3P0_CLR_OK_VDD3P0_MASK 0x20000u
+#define PMU_REG_3P0_CLR_OK_VDD3P0_SHIFT 17
+#define PMU_REG_3P0_CLR_REG_TEST_MASK 0x3C0000u
+#define PMU_REG_3P0_CLR_REG_TEST_SHIFT 18
+#define PMU_REG_3P0_CLR_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_REG_TEST_SHIFT))&PMU_REG_3P0_CLR_REG_TEST_MASK)
+#define PMU_REG_3P0_CLR_RSVD2_MASK 0xFFC00000u
+#define PMU_REG_3P0_CLR_RSVD2_SHIFT 22
+#define PMU_REG_3P0_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_CLR_RSVD2_SHIFT))&PMU_REG_3P0_CLR_RSVD2_MASK)
+/* REG_3P0_TOG Bit Fields */
+#define PMU_REG_3P0_TOG_ENABLE_LINREG_MASK 0x1u
+#define PMU_REG_3P0_TOG_ENABLE_LINREG_SHIFT 0
+#define PMU_REG_3P0_TOG_ENABLE_BO_MASK 0x2u
+#define PMU_REG_3P0_TOG_ENABLE_BO_SHIFT 1
+#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_MASK 0x4u
+#define PMU_REG_3P0_TOG_ENABLE_ILIMIT_SHIFT 2
+#define PMU_REG_3P0_TOG_RSVD0_MASK 0x8u
+#define PMU_REG_3P0_TOG_RSVD0_SHIFT 3
+#define PMU_REG_3P0_TOG_BO_OFFSET_MASK 0x70u
+#define PMU_REG_3P0_TOG_BO_OFFSET_SHIFT 4
+#define PMU_REG_3P0_TOG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_BO_OFFSET_SHIFT))&PMU_REG_3P0_TOG_BO_OFFSET_MASK)
+#define PMU_REG_3P0_TOG_VBUS_SEL_MASK 0x80u
+#define PMU_REG_3P0_TOG_VBUS_SEL_SHIFT 7
+#define PMU_REG_3P0_TOG_OUTPUT_TRG_MASK 0x1F00u
+#define PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT 8
+#define PMU_REG_3P0_TOG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_OUTPUT_TRG_SHIFT))&PMU_REG_3P0_TOG_OUTPUT_TRG_MASK)
+#define PMU_REG_3P0_TOG_RSVD1_MASK 0xE000u
+#define PMU_REG_3P0_TOG_RSVD1_SHIFT 13
+#define PMU_REG_3P0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD1_SHIFT))&PMU_REG_3P0_TOG_RSVD1_MASK)
+#define PMU_REG_3P0_TOG_BO_VDD3P0_MASK 0x10000u
+#define PMU_REG_3P0_TOG_BO_VDD3P0_SHIFT 16
+#define PMU_REG_3P0_TOG_OK_VDD3P0_MASK 0x20000u
+#define PMU_REG_3P0_TOG_OK_VDD3P0_SHIFT 17
+#define PMU_REG_3P0_TOG_REG_TEST_MASK 0x3C0000u
+#define PMU_REG_3P0_TOG_REG_TEST_SHIFT 18
+#define PMU_REG_3P0_TOG_REG_TEST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_REG_TEST_SHIFT))&PMU_REG_3P0_TOG_REG_TEST_MASK)
+#define PMU_REG_3P0_TOG_RSVD2_MASK 0xFFC00000u
+#define PMU_REG_3P0_TOG_RSVD2_SHIFT 22
+#define PMU_REG_3P0_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<PMU_REG_3P0_TOG_RSVD2_SHIFT))&PMU_REG_3P0_TOG_RSVD2_MASK)
+/* REF Bit Fields */
+#define PMU_REF_REFTOP_PWD_MASK 0x1u
+#define PMU_REF_REFTOP_PWD_SHIFT 0
+#define PMU_REF_REFTOP_PWDVBGUP_MASK 0x2u
+#define PMU_REF_REFTOP_PWDVBGUP_SHIFT 1
+#define PMU_REF_REFTOP_LOWPOWER_MASK 0x4u
+#define PMU_REF_REFTOP_LOWPOWER_SHIFT 2
+#define PMU_REF_REFTOP_SELFBIASOFF_MASK 0x8u
+#define PMU_REF_REFTOP_SELFBIASOFF_SHIFT 3
+#define PMU_REF_REFTOP_VBGADJ_MASK 0x70u
+#define PMU_REF_REFTOP_VBGADJ_SHIFT 4
+#define PMU_REF_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_VBGADJ_SHIFT))&PMU_REF_REFTOP_VBGADJ_MASK)
+#define PMU_REF_REFTOP_VBGUP_MASK 0x80u
+#define PMU_REF_REFTOP_VBGUP_SHIFT 7
+#define PMU_REF_REFTOP_BIAS_TST_MASK 0x300u
+#define PMU_REF_REFTOP_BIAS_TST_SHIFT 8
+#define PMU_REF_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_REFTOP_BIAS_TST_SHIFT))&PMU_REF_REFTOP_BIAS_TST_MASK)
+#define PMU_REF_LPBG_SEL_MASK 0x400u
+#define PMU_REF_LPBG_SEL_SHIFT 10
+#define PMU_REF_LPBG_TEST_MASK 0x800u
+#define PMU_REF_LPBG_TEST_SHIFT 11
+#define PMU_REF_REFTOP_IBIAS_OFF_MASK 0x1000u
+#define PMU_REF_REFTOP_IBIAS_OFF_SHIFT 12
+#define PMU_REF_REFTOP_LINREGREF_EN_MASK 0x2000u
+#define PMU_REF_REFTOP_LINREGREF_EN_SHIFT 13
+#define PMU_REF_RSVD1_MASK 0xFFFFC000u
+#define PMU_REF_RSVD1_SHIFT 14
+#define PMU_REF_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_RSVD1_SHIFT))&PMU_REF_RSVD1_MASK)
+/* REF_SET Bit Fields */
+#define PMU_REF_SET_REFTOP_PWD_MASK 0x1u
+#define PMU_REF_SET_REFTOP_PWD_SHIFT 0
+#define PMU_REF_SET_REFTOP_PWDVBGUP_MASK 0x2u
+#define PMU_REF_SET_REFTOP_PWDVBGUP_SHIFT 1
+#define PMU_REF_SET_REFTOP_LOWPOWER_MASK 0x4u
+#define PMU_REF_SET_REFTOP_LOWPOWER_SHIFT 2
+#define PMU_REF_SET_REFTOP_SELFBIASOFF_MASK 0x8u
+#define PMU_REF_SET_REFTOP_SELFBIASOFF_SHIFT 3
+#define PMU_REF_SET_REFTOP_VBGADJ_MASK 0x70u
+#define PMU_REF_SET_REFTOP_VBGADJ_SHIFT 4
+#define PMU_REF_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_VBGADJ_SHIFT))&PMU_REF_SET_REFTOP_VBGADJ_MASK)
+#define PMU_REF_SET_REFTOP_VBGUP_MASK 0x80u
+#define PMU_REF_SET_REFTOP_VBGUP_SHIFT 7
+#define PMU_REF_SET_REFTOP_BIAS_TST_MASK 0x300u
+#define PMU_REF_SET_REFTOP_BIAS_TST_SHIFT 8
+#define PMU_REF_SET_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_REFTOP_BIAS_TST_SHIFT))&PMU_REF_SET_REFTOP_BIAS_TST_MASK)
+#define PMU_REF_SET_LPBG_SEL_MASK 0x400u
+#define PMU_REF_SET_LPBG_SEL_SHIFT 10
+#define PMU_REF_SET_LPBG_TEST_MASK 0x800u
+#define PMU_REF_SET_LPBG_TEST_SHIFT 11
+#define PMU_REF_SET_REFTOP_IBIAS_OFF_MASK 0x1000u
+#define PMU_REF_SET_REFTOP_IBIAS_OFF_SHIFT 12
+#define PMU_REF_SET_REFTOP_LINREGREF_EN_MASK 0x2000u
+#define PMU_REF_SET_REFTOP_LINREGREF_EN_SHIFT 13
+#define PMU_REF_SET_RSVD1_MASK 0xFFFFC000u
+#define PMU_REF_SET_RSVD1_SHIFT 14
+#define PMU_REF_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_SET_RSVD1_SHIFT))&PMU_REF_SET_RSVD1_MASK)
+/* REF_CLR Bit Fields */
+#define PMU_REF_CLR_REFTOP_PWD_MASK 0x1u
+#define PMU_REF_CLR_REFTOP_PWD_SHIFT 0
+#define PMU_REF_CLR_REFTOP_PWDVBGUP_MASK 0x2u
+#define PMU_REF_CLR_REFTOP_PWDVBGUP_SHIFT 1
+#define PMU_REF_CLR_REFTOP_LOWPOWER_MASK 0x4u
+#define PMU_REF_CLR_REFTOP_LOWPOWER_SHIFT 2
+#define PMU_REF_CLR_REFTOP_SELFBIASOFF_MASK 0x8u
+#define PMU_REF_CLR_REFTOP_SELFBIASOFF_SHIFT 3
+#define PMU_REF_CLR_REFTOP_VBGADJ_MASK 0x70u
+#define PMU_REF_CLR_REFTOP_VBGADJ_SHIFT 4
+#define PMU_REF_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_VBGADJ_SHIFT))&PMU_REF_CLR_REFTOP_VBGADJ_MASK)
+#define PMU_REF_CLR_REFTOP_VBGUP_MASK 0x80u
+#define PMU_REF_CLR_REFTOP_VBGUP_SHIFT 7
+#define PMU_REF_CLR_REFTOP_BIAS_TST_MASK 0x300u
+#define PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT 8
+#define PMU_REF_CLR_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_REFTOP_BIAS_TST_SHIFT))&PMU_REF_CLR_REFTOP_BIAS_TST_MASK)
+#define PMU_REF_CLR_LPBG_SEL_MASK 0x400u
+#define PMU_REF_CLR_LPBG_SEL_SHIFT 10
+#define PMU_REF_CLR_LPBG_TEST_MASK 0x800u
+#define PMU_REF_CLR_LPBG_TEST_SHIFT 11
+#define PMU_REF_CLR_REFTOP_IBIAS_OFF_MASK 0x1000u
+#define PMU_REF_CLR_REFTOP_IBIAS_OFF_SHIFT 12
+#define PMU_REF_CLR_REFTOP_LINREGREF_EN_MASK 0x2000u
+#define PMU_REF_CLR_REFTOP_LINREGREF_EN_SHIFT 13
+#define PMU_REF_CLR_RSVD1_MASK 0xFFFFC000u
+#define PMU_REF_CLR_RSVD1_SHIFT 14
+#define PMU_REF_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_CLR_RSVD1_SHIFT))&PMU_REF_CLR_RSVD1_MASK)
+/* REF_TOG Bit Fields */
+#define PMU_REF_TOG_REFTOP_PWD_MASK 0x1u
+#define PMU_REF_TOG_REFTOP_PWD_SHIFT 0
+#define PMU_REF_TOG_REFTOP_PWDVBGUP_MASK 0x2u
+#define PMU_REF_TOG_REFTOP_PWDVBGUP_SHIFT 1
+#define PMU_REF_TOG_REFTOP_LOWPOWER_MASK 0x4u
+#define PMU_REF_TOG_REFTOP_LOWPOWER_SHIFT 2
+#define PMU_REF_TOG_REFTOP_SELFBIASOFF_MASK 0x8u
+#define PMU_REF_TOG_REFTOP_SELFBIASOFF_SHIFT 3
+#define PMU_REF_TOG_REFTOP_VBGADJ_MASK 0x70u
+#define PMU_REF_TOG_REFTOP_VBGADJ_SHIFT 4
+#define PMU_REF_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_VBGADJ_SHIFT))&PMU_REF_TOG_REFTOP_VBGADJ_MASK)
+#define PMU_REF_TOG_REFTOP_VBGUP_MASK 0x80u
+#define PMU_REF_TOG_REFTOP_VBGUP_SHIFT 7
+#define PMU_REF_TOG_REFTOP_BIAS_TST_MASK 0x300u
+#define PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT 8
+#define PMU_REF_TOG_REFTOP_BIAS_TST(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_REFTOP_BIAS_TST_SHIFT))&PMU_REF_TOG_REFTOP_BIAS_TST_MASK)
+#define PMU_REF_TOG_LPBG_SEL_MASK 0x400u
+#define PMU_REF_TOG_LPBG_SEL_SHIFT 10
+#define PMU_REF_TOG_LPBG_TEST_MASK 0x800u
+#define PMU_REF_TOG_LPBG_TEST_SHIFT 11
+#define PMU_REF_TOG_REFTOP_IBIAS_OFF_MASK 0x1000u
+#define PMU_REF_TOG_REFTOP_IBIAS_OFF_SHIFT 12
+#define PMU_REF_TOG_REFTOP_LINREGREF_EN_MASK 0x2000u
+#define PMU_REF_TOG_REFTOP_LINREGREF_EN_SHIFT 13
+#define PMU_REF_TOG_RSVD1_MASK 0xFFFFC000u
+#define PMU_REF_TOG_RSVD1_SHIFT 14
+#define PMU_REF_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<PMU_REF_TOG_RSVD1_SHIFT))&PMU_REF_TOG_RSVD1_MASK)
+/* LOWPWR_CTRL Bit Fields */
+#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK 0x3u
+#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT 0
+#define PMU_LOWPWR_CTRL_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_STOP_MODE_CONFIG_MASK)
+#define PMU_LOWPWR_CTRL_RSVD0_MASK 0xFCu
+#define PMU_LOWPWR_CTRL_RSVD0_SHIFT 2
+#define PMU_LOWPWR_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_RSVD0_MASK)
+#define PMU_LOWPWR_CTRL_L1_PWRGATE_MASK 0x100u
+#define PMU_LOWPWR_CTRL_L1_PWRGATE_SHIFT 8
+#define PMU_LOWPWR_CTRL_L2_PWRGATE_MASK 0x200u
+#define PMU_LOWPWR_CTRL_L2_PWRGATE_SHIFT 9
+#define PMU_LOWPWR_CTRL_CPU_PWRGATE_MASK 0x400u
+#define PMU_LOWPWR_CTRL_CPU_PWRGATE_SHIFT 10
+#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_MASK 0x800u
+#define PMU_LOWPWR_CTRL_DISPLAY_PWRGATE_SHIFT 11
+#define PMU_LOWPWR_CTRL_MIX_PWRGATE_MASK 0x1000u
+#define PMU_LOWPWR_CTRL_MIX_PWRGATE_SHIFT 12
+#define PMU_LOWPWR_CTRL_GPU_PWRGATE_MASK 0x2000u
+#define PMU_LOWPWR_CTRL_GPU_PWRGATE_SHIFT 13
+#define PMU_LOWPWR_CTRL_CONTROL0_MASK 0xFFC000u
+#define PMU_LOWPWR_CTRL_CONTROL0_SHIFT 14
+#define PMU_LOWPWR_CTRL_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CONTROL0_MASK)
+#define PMU_LOWPWR_CTRL_CONTROL1_MASK 0xFF000000u
+#define PMU_LOWPWR_CTRL_CONTROL1_SHIFT 24
+#define PMU_LOWPWR_CTRL_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CONTROL1_MASK)
+/* LOWPWR_CTRL_SET Bit Fields */
+#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK 0x3u
+#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT 0
+#define PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_SET_STOP_MODE_CONFIG_MASK)
+#define PMU_LOWPWR_CTRL_SET_RSVD0_MASK 0xFCu
+#define PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT 2
+#define PMU_LOWPWR_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_SET_RSVD0_MASK)
+#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_MASK 0x100u
+#define PMU_LOWPWR_CTRL_SET_L1_PWRGATE_SHIFT 8
+#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_MASK 0x200u
+#define PMU_LOWPWR_CTRL_SET_L2_PWRGATE_SHIFT 9
+#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_MASK 0x400u
+#define PMU_LOWPWR_CTRL_SET_CPU_PWRGATE_SHIFT 10
+#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_MASK 0x800u
+#define PMU_LOWPWR_CTRL_SET_DISPLAY_PWRGATE_SHIFT 11
+#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_MASK 0x1000u
+#define PMU_LOWPWR_CTRL_SET_MIX_PWRGATE_SHIFT 12
+#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_MASK 0x2000u
+#define PMU_LOWPWR_CTRL_SET_GPU_PWRGATE_SHIFT 13
+#define PMU_LOWPWR_CTRL_SET_CONTROL0_MASK 0xFFC000u
+#define PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT 14
+#define PMU_LOWPWR_CTRL_SET_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL0_MASK)
+#define PMU_LOWPWR_CTRL_SET_CONTROL1_MASK 0xFF000000u
+#define PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT 24
+#define PMU_LOWPWR_CTRL_SET_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_SET_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_SET_CONTROL1_MASK)
+/* LOWPWR_CTRL_CLR Bit Fields */
+#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK 0x3u
+#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT 0
+#define PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_CLR_STOP_MODE_CONFIG_MASK)
+#define PMU_LOWPWR_CTRL_CLR_RSVD0_MASK 0xFCu
+#define PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT 2
+#define PMU_LOWPWR_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_CLR_RSVD0_MASK)
+#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_MASK 0x100u
+#define PMU_LOWPWR_CTRL_CLR_L1_PWRGATE_SHIFT 8
+#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_MASK 0x200u
+#define PMU_LOWPWR_CTRL_CLR_L2_PWRGATE_SHIFT 9
+#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_MASK 0x400u
+#define PMU_LOWPWR_CTRL_CLR_CPU_PWRGATE_SHIFT 10
+#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_MASK 0x800u
+#define PMU_LOWPWR_CTRL_CLR_DISPLAY_PWRGATE_SHIFT 11
+#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_MASK 0x1000u
+#define PMU_LOWPWR_CTRL_CLR_MIX_PWRGATE_SHIFT 12
+#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_MASK 0x2000u
+#define PMU_LOWPWR_CTRL_CLR_GPU_PWRGATE_SHIFT 13
+#define PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK 0xFFC000u
+#define PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT 14
+#define PMU_LOWPWR_CTRL_CLR_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL0_MASK)
+#define PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK 0xFF000000u
+#define PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT 24
+#define PMU_LOWPWR_CTRL_CLR_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_CLR_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_CLR_CONTROL1_MASK)
+/* LOWPWR_CTRL_TOG Bit Fields */
+#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK 0x3u
+#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT 0
+#define PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_SHIFT))&PMU_LOWPWR_CTRL_TOG_STOP_MODE_CONFIG_MASK)
+#define PMU_LOWPWR_CTRL_TOG_RSVD0_MASK 0xFCu
+#define PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT 2
+#define PMU_LOWPWR_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_RSVD0_SHIFT))&PMU_LOWPWR_CTRL_TOG_RSVD0_MASK)
+#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_MASK 0x100u
+#define PMU_LOWPWR_CTRL_TOG_L1_PWRGATE_SHIFT 8
+#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_MASK 0x200u
+#define PMU_LOWPWR_CTRL_TOG_L2_PWRGATE_SHIFT 9
+#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_MASK 0x400u
+#define PMU_LOWPWR_CTRL_TOG_CPU_PWRGATE_SHIFT 10
+#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_MASK 0x800u
+#define PMU_LOWPWR_CTRL_TOG_DISPLAY_PWRGATE_SHIFT 11
+#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_MASK 0x1000u
+#define PMU_LOWPWR_CTRL_TOG_MIX_PWRGATE_SHIFT 12
+#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_MASK 0x2000u
+#define PMU_LOWPWR_CTRL_TOG_GPU_PWRGATE_SHIFT 13
+#define PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK 0xFFC000u
+#define PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT 14
+#define PMU_LOWPWR_CTRL_TOG_CONTROL0(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL0_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL0_MASK)
+#define PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK 0xFF000000u
+#define PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT 24
+#define PMU_LOWPWR_CTRL_TOG_CONTROL1(x) (((uint32_t)(((uint32_t)(x))<<PMU_LOWPWR_CTRL_TOG_CONTROL1_SHIFT))&PMU_LOWPWR_CTRL_TOG_CONTROL1_MASK)
+
+
+/* HW_ANADIG_TEMPSENSE0 Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK 0x3FE00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_HIGH_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK 0x7FC0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT 18
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_PANIC_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK 0xF8000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT 27
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_RSVD1_MASK)
+/* HW_ANADIG_TEMPSENSE0_SET Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_LOW_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK 0x3FE00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_HIGH_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK 0x7FC0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT 18
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_PANIC_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK 0xF8000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT 27
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_SET_RSVD1_MASK)
+/* HW_ANADIG_TEMPSENSE0_CLR Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_LOW_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK 0x3FE00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_HIGH_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK 0x7FC0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT 18
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_PANIC_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK 0xF8000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT 27
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK)
+/* HW_ANADIG_TEMPSENSE0_TOG Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_LOW_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK 0x3FE00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_HIGH_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK 0x7FC0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT 18
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_PANIC_ALARM_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK 0xF8000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT 27
+#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_RSVD1_MASK)
+/* HW_ANADIG_TEMPSENSE1 Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_MASK 0x200u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_POWER_DOWN_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK 0x400u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_SHIFT 10
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK 0x800u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_SHIFT 11
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK 0xF000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT 12
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK 0xFFFF0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT 16
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_FREQ_MASK)
+/* HW_ANADIG_TEMPSENSE1_SET Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_TEMP_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_MASK 0x200u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_POWER_DOWN_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_MASK 0x400u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_TEMP_SHIFT 10
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_MASK 0x800u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_FINISHED_SHIFT 11
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK 0xF000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT 12
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK 0xFFFF0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT 16
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_SET_MEASURE_FREQ_MASK)
+/* HW_ANADIG_TEMPSENSE1_CLR Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_TEMP_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_MASK 0x200u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_POWER_DOWN_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_MASK 0x400u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_TEMP_SHIFT 10
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_MASK 0x800u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_FINISHED_SHIFT 11
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK 0xF000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT 12
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK 0xFFFF0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT 16
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_MEASURE_FREQ_MASK)
+/* HW_ANADIG_TEMPSENSE1_TOG Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK 0x1FFu
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_TEMP_VALUE_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_MASK 0x200u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_POWER_DOWN_SHIFT 9
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_MASK 0x400u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_TEMP_SHIFT 10
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_MASK 0x800u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_FINISHED_SHIFT 11
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK 0xF000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT 12
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK 0xFFFF0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT 16
+#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_MEASURE_FREQ_MASK)
+/* HW_ANADIG_TEMPSENSE_TRIM Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK 0x1Fu
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_VREF_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK 0x60u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT 5
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_MASK 0x80u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_EN_READ_SHIFT 7
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK 0x1FF00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT 8
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_VREF_VBE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK 0xE0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT 17
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD1_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK 0xF00000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT 20
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_BUF_SLOPE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK 0x1F000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT 24
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_RSVD2_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK 0xE0000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT 29
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_T_MUX_ADDR_MASK)
+/* HW_ANADIG_TEMPSENSE_TRIM_SET Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK 0x1Fu
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_VREF_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK 0x60u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT 5
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_MASK 0x80u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_EN_READ_SHIFT 7
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK 0x1FF00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT 8
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_VREF_VBE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK 0xE0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT 17
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD1_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK 0xF00000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT 20
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_BUF_SLOPE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK 0x1F000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT 24
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_RSVD2_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK 0xE0000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT 29
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_T_MUX_ADDR_MASK)
+/* HW_ANADIG_TEMPSENSE_TRIM_CLR Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK 0x1Fu
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_VREF_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK 0x60u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT 5
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_MASK 0x80u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_EN_READ_SHIFT 7
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK 0x1FF00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT 8
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_VREF_VBE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK 0xE0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT 17
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD1_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK 0xF00000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT 20
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_BUF_SLOPE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK 0x1F000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT 24
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_RSVD2_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK 0xE0000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT 29
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_T_MUX_ADDR_MASK)
+/* HW_ANADIG_TEMPSENSE_TRIM_TOG Bit Fields */
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK 0x1Fu
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT 0
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_VREF_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK 0x60u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT 5
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD0_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_MASK 0x80u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_EN_READ_SHIFT 7
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK 0x1FF00u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT 8
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_VREF_VBE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK 0xE0000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT 17
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD1_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK 0xF00000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT 20
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_BUF_SLOPE_SEL_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK 0x1F000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT 24
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_RSVD2_MASK)
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK 0xE0000000u
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29
+#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK)
+
+
+#define CCM_GPR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i))
+#define CCM_OBSERVE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i))
+#define CCM_SCTRL(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i))
+#define CCM_CCGR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i))
+#define CCM_ROOT_TARGET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i))
+
+#define CCM_GPR_SET(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 4)
+#define CCM_OBSERVE_SET(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4)
+#define CCM_SCTRL_SET(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4)
+#define CCM_CCGR_SET(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 4)
+#define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4)
+
+#define CCM_GPR_CLR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 8)
+#define CCM_OBSERVE_CLR(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8)
+#define CCM_SCTRL_CLR(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8)
+#define CCM_CCGR_CLR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 8)
+#define CCM_ROOT_TARGET_CLR(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8)
+
+#define CCM_GPR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 12)
+#define CCM_OBSERVE_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12)
+#define CCM_SCTRL_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12)
+#define CCM_CCGR_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 12)
+#define CCM_ROOT_TARGET_TOGGLE(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12)
+
+#define HW_CCM_GPR_WR(i, v) writel((v), CCM_GPR(i))
+#define HW_CCM_CCM_OBSERVE_WR(i, v) writel((v), CCM_OBSERVE(i))
+#define HW_CCM_SCTRL_WR(i, v) writel((v), CCM_SCTRL(i))
+#define HW_CCM_CCGR_WR(i, v) writel((v), CCM_CCGR(i))
+#define HW_CCM_ROOT_TARGET_WR(i, v) writel((v), CCM_ROOT_TARGET(i))
+
+#define HW_CCM_GPR_RD(i) readl(CCM_GPR(i))
+#define HW_CCM_CCM_OBSERVE_RD(i) readl(CCM_OBSERVE(i))
+#define HW_CCM_SCTRL_RD(i) readl(CCM_SCTRL(i))
+#define HW_CCM_CCGR_RD(i) readl(CCM_CCGR(i))
+#define HW_CCM_ROOT_TARGET_RD(i) readl(CCM_ROOT_TARGET(i))
+
+#define HW_CCM_GPR_SET(i, v) writel((v), CCM_GPR_SET(i))
+#define HW_CCM_CCM_OBSERVE_SET(i, v) writel((v), CCM_CCM_OBSERVE_SET(i))
+#define HW_CCM_SCTRL_SET(i, v) writel((v), CCM_SCTRL_SET(i))
+#define HW_CCM_CCGR_SET(i, v) writel((v), CCM_CCGR_SET(i))
+#define HW_CCM_ROOT_TARGET_SET(i, v) writel((v), CCM_ROOT_TARGET_SET(i))
+
+#define HW_CCM_GPR_CLR(i, v) writel((v), CCM_GPR_CLR(i))
+#define HW_CCM_CCM_OBSERVE_CLR(i, v) writel((v), CCM_CCM_OBSERVE_CLR(i))
+#define HW_CCM_SCTRL_CLR(i, v) writel((v), CCM_SCTRL_CLR(i))
+#define HW_CCM_CCGR_CLR(i, v) writel((v), CCM_CCGR_CLR(i))
+#define HW_CCM_ROOT_TARGET_CLR(i, v) writel((v), CCM_ROOT_TARGET_CLR(i))
+
+#define HW_CCM_GPR_TOGGLE(i, v) writel((v), CCM_GPR_TOGGLE(i))
+#define HW_CCM_CCM_OBSERVE_TOGGLE(i, v) writel((v), CCM_CCM_OBSERVE_TOGGLE(i))
+#define HW_CCM_SCTRL_TOGGLE(i, v) writel((v), CCM_SCTRL_TOGGLE(i))
+#define HW_CCM_CCGR_TOGGLE(i, v) writel((v), CCM_CCGR_TOGGLE(i))
+#define HW_CCM_ROOT_TARGET_TOGGLE(i, v) writel((v), CCM_ROOT_TARGET_TOGGLE(i))
+
+#define CCM_CLK_ON_MSK 0x03
+
+#define CCM_ROOT_TGT_POST_DIV_SHIFT 0
+#define CCM_ROOT_TGT_PRE_DIV_SHIFT 15
+#define CCM_ROOT_TGT_MUX_SHIFT 24
+#define CCM_ROOT_TGT_ENABLE_SHIFT 28
+#define CCM_ROOT_TGT_POST_DIV_MSK 0x3F
+#define CCM_ROOT_TGT_PRE_DIV_MSK (0x07 << CCM_ROOT_TGT_PRE_DIV_SHIFT)
+#define CCM_ROOT_TGT_MUX_MSK (0x07 << CCM_ROOT_TGT_MUX_SHIFT)
+#define CCM_ROOT_TGT_ENABLE_MSK (0x01 << CCM_ROOT_TGT_ENABLE_SHIFT)
+
+#define CCM_ROOT_TGT_POST_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_POST_DIV_SHIFT) & CCM_ROOT_TGT_POST_DIV_MSK)
+#define CCM_ROOT_TGT_PRE_DIV(x) ((((x) - 1) << CCM_ROOT_TGT_PRE_DIV_SHIFT) & CCM_ROOT_TGT_PRE_DIV_MSK)
+#define CCM_ROOT_TGT_MUX_TO(x) ((((x) - 1) << CCM_ROOT_TGT_MUX_SHIFT) & CCM_ROOT_TGT_MUX_MSK)
+
+/*
+ * Field values definition for clock slice TARGET register
+ */
+
+#define CLK_ROOT_ON 0x10000000
+#define CLK_ROOT_OFF 0x0
+#define CLK_ROOT_ENABLE_MASK 0x10000000
+#define CLK_ROOT_ENABLE_SHIFT 28
+
+#define CLK_ROOT_ALT0 0x00000000
+#define CLK_ROOT_ALT1 0x01000000
+#define CLK_ROOT_ALT2 0x02000000
+#define CLK_ROOT_ALT3 0x03000000
+#define CLK_ROOT_ALT4 0x04000000
+#define CLK_ROOT_ALT5 0x05000000
+#define CLK_ROOT_ALT6 0x06000000
+#define CLK_ROOT_ALT7 0x07000000
+
+
+#define DRAM_CLK_ROOT_POST_DIV_MASK 0x00000007
+#define CLK_ROOT_POST_DIV_MASK 0x0000003f
+#define CLK_ROOT_POST_DIV_SHIFT 0
+#define CLK_ROOT_POST_DIV(n) ((n << CLK_ROOT_POST_DIV_SHIFT) & CLK_ROOT_POST_DIV_MASK)
+
+#define CLK_ROOT_AUTO_DIV_MASK 0x00000700
+#define CLK_ROOT_AUTO_DIV_SHIFT 8
+#define CLK_ROOT_AUTO_DIV(n) ((n << CLK_ROOT_AUTO_DIV_SHIFT) & CLK_ROOT_AUTO_DIV_MASK)
+
+#define CLK_ROOT_AUTO_EN_MASK 0x00001000
+#define CLK_ROOT_AUTO_EN 0x00001000
+
+#define CLK_ROOT_PRE_DIV_MASK 0x00070000
+#define CLK_ROOT_PRE_DIV_SHIFT 16
+#define CLK_ROOT_PRE_DIV(n) ((n << CLK_ROOT_PRE_DIV_SHIFT) & CLK_ROOT_PRE_DIV_MASK)
+
+#define CLK_ROOT_MUX_MASK 0x07000000
+#define CLK_ROOT_MUX_SHIFT 24
+
+#define CLK_ROOT_EN_MASK 0x10000000
+
+#define CLK_ROOT_AUTO_ON 0x00001000
+#define CLK_ROOT_AUTO_OFF 0x0
+
+/* ARM_A7_CLK_ROOT */
+#define ARM_A7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_ARM_MAIN_800M_CLK 0x01000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x03000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define ARM_A7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* ARM_M4_CLK_ROOT */
+#define ARM_M4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x02000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define ARM_M4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* ARM_M0_CLK_ROOT */
+#define ARM_M0_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x03000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x02000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define ARM_M0_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* MAIN_AXI_CLK_ROOT */
+#define MAIN_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define MAIN_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+
+/* DISP_AXI_CLK_ROOT */
+#define DISP_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x04000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define DISP_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+
+/* ENET_AXI_CLK_ROOT */
+#define ENET_AXI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x07000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x03000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define ENET_AXI_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+
+/* NAND_USDHC_BUS_CLK_ROOT */
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x03000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x01000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x04000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
+#define NAND_USDHC_BUS_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000
+
+/* AHB_CLK_ROOT */
+#define AHB_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define AHB_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000
+#define AHB_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define AHB_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000
+#define AHB_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define AHB_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define AHB_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000
+
+/* DRAM_PHYM_CLK_ROOT */
+#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000
+#define DRAM_PHYM_CLK_ROOT_FROM_PLL_DRAM_PHYM_ALT_CLK_ROOT 0x01000000
+
+/* DRAM_CLK_ROOT */
+#define DRAM_CLK_ROOT_FROM_PLL_DRAM_MAIN_1066M_CLK 0x00000000
+#define DRAM_CLK_ROOT_FROM_PLL_DRAM_ALT_CLK_ROOT 0x01000000
+
+/* DRAM_PHYM_ALT_CLK_ROOT */
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x05000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define DRAM_PHYM_ALT_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000
+
+/* DRAM_ALT_CLK_ROOT */
+#define DRAM_ALT_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x01000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x02000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x05000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x07000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x04000000
+#define DRAM_ALT_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+
+/* USB_HSIC_CLK_ROOT */
+#define USB_HSIC_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x03000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x05000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define USB_HSIC_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x02000000
+
+/* PCIE_CTRL_CLK_ROOT */
+#define PCIE_CTRL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x06000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x03000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x07000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000
+#define PCIE_CTRL_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x01000000
+
+/* PCIE_PHY_CLK_ROOT */
+#define PCIE_PHY_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define PCIE_PHY_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x07000000
+#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x02000000
+#define PCIE_PHY_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_1 0x03000000
+#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_2 0x04000000
+#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_3 0x05000000
+#define PCIE_PHY_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
+
+/* EPDC_PIXEL_CLK_ROOT */
+#define EPDC_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD1_332M_CLK 0x01000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x04000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x05000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x06000000
+#define EPDC_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+
+/* LCDIF_PIXEL_CLK_ROOT */
+#define LCDIF_PIXEL_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define LCDIF_PIXEL_CLK_ROOT_FROM_EXT_CLK_3 0x03000000
+
+/* MIPI_DSI_EXTSER_CLK_ROOT */
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x01000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000
+#define MIPI_DSI_EXTSER_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+
+/* MIPI_CSI_WARP_CLK_ROOT */
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x05000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD0_196M_CLK 0x04000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x02000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x07000000
+#define MIPI_CSI_WARP_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+
+/* MIPI_DPHY_REF_CLK_ROOT */
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD5_CLK 0x03000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_REF_1M_CLK 0x04000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define MIPI_DPHY_REF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
+
+/* SAI1_CLK_ROOT */
+#define SAI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define SAI1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define SAI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define SAI1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
+#define SAI1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
+#define SAI1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define SAI1_CLK_ROOT_FROM_EXT_CLK_2 0x07000000
+
+/* SAI2_CLK_ROOT */
+#define SAI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define SAI2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define SAI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define SAI2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
+#define SAI2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
+#define SAI2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define SAI2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000
+
+/* SAI3_CLK_ROOT */
+#define SAI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define SAI3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define SAI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define SAI3_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
+#define SAI3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
+#define SAI3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define SAI3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
+
+/* SPDIF_CLK_ROOT */
+#define SPDIF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define SPDIF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define SPDIF_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define SPDIF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
+#define SPDIF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
+#define SPDIF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define SPDIF_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
+
+/* ENET1_REF_CLK_ROOT */
+#define ENET1_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define ENET1_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define ENET1_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000
+
+/* ENET1_TIME_CLK_ROOT */
+#define ENET1_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define ENET1_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
+#define ENET1_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000
+#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000
+#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000
+#define ENET1_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
+
+/* ENET2_REF_CLK_ROOT */
+#define ENET2_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x04000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define ENET2_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define ENET2_REF_CLK_ROOT_FROM_EXT_CLK_4 0x07000000
+
+/* ENET2_TIME_CLK_ROOT */
+#define ENET2_TIME_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ENET2_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define ENET2_TIME_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x02000000
+#define ENET2_TIME_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_1 0x03000000
+#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_2 0x04000000
+#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_3 0x05000000
+#define ENET2_TIME_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
+
+/* ENET_PHY_REF_CLK_ROOT */
+#define ENET_PHY_REF_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x04000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x07000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x03000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+
+/* EIM_CLK_ROOT */
+#define EIM_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define EIM_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define EIM_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x04000000
+#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define EIM_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x05000000
+#define EIM_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
+#define EIM_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* NAND_CLK_ROOT */
+#define NAND_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define NAND_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define NAND_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000
+#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x03000000
+#define NAND_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000
+#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000
+#define NAND_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
+#define NAND_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+
+/* QSPI_CLK_ROOT */
+#define QSPI_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define QSPI_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
+#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD3_CLK 0x04000000
+#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x01000000
+#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000
+#define QSPI_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define QSPI_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
+
+/* USDHC1_CLK_ROOT */
+#define USDHC1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define USDHC1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000
+#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
+#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000
+#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000
+#define USDHC1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define USDHC1_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
+
+/* USDHC2_CLK_ROOT */
+#define USDHC2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define USDHC2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000
+#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
+#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000
+#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000
+#define USDHC2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define USDHC2_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
+
+/* USDHC3_CLK_ROOT */
+#define USDHC3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define USDHC3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x01000000
+#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
+#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x04000000
+#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD6_CLK 0x06000000
+#define USDHC3_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define USDHC3_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x03000000
+
+/* CAN1_CLK_ROOT */
+#define CAN1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define CAN1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000
+#define CAN1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define CAN1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000
+#define CAN1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000
+#define CAN1_CLK_ROOT_FROM_EXT_CLK_1 0x06000000
+#define CAN1_CLK_ROOT_FROM_EXT_CLK_4 0x07000000
+
+/* CAN2_CLK_ROOT */
+#define CAN2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define CAN2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x03000000
+#define CAN2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define CAN2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x04000000
+#define CAN2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000
+#define CAN2_CLK_ROOT_FROM_EXT_CLK_1 0x06000000
+#define CAN2_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
+
+/* I2C1_CLK_ROOT */
+#define I2C1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define I2C1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define I2C1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define I2C1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000
+#define I2C1_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
+#define I2C1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define I2C1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000
+#define I2C1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000
+
+/* I2C2_CLK_ROOT */
+#define I2C2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define I2C2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define I2C2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define I2C2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000
+#define I2C2_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
+#define I2C2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define I2C2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000
+#define I2C2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000
+
+/* I2C3_CLK_ROOT */
+#define I2C3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define I2C3_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define I2C3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define I2C3_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000
+#define I2C3_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
+#define I2C3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define I2C3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000
+#define I2C3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000
+
+/* I2C4_CLK_ROOT */
+#define I2C4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define I2C4_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define I2C4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x01000000
+#define I2C4_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x07000000
+#define I2C4_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
+#define I2C4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define I2C4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000
+#define I2C4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x06000000
+
+/* UART1_CLK_ROOT */
+#define UART1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define UART1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
+#define UART1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define UART1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define UART1_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define UART1_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
+
+/* UART2_CLK_ROOT */
+#define UART2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define UART2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
+#define UART2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define UART2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define UART2_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define UART2_CLK_ROOT_FROM_EXT_CLK_3 0x06000000
+
+/* UART3_CLK_ROOT */
+#define UART3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define UART3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
+#define UART3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define UART3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define UART3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define UART3_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
+
+/* UART4_CLK_ROOT */
+#define UART4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define UART4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
+#define UART4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define UART4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define UART4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define UART4_CLK_ROOT_FROM_EXT_CLK_3 0x06000000
+
+/* UART5_CLK_ROOT */
+#define UART5_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define UART5_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
+#define UART5_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define UART5_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define UART5_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define UART5_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
+
+/* UART6_CLK_ROOT */
+#define UART6_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define UART6_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
+#define UART6_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define UART6_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define UART6_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define UART6_CLK_ROOT_FROM_EXT_CLK_3 0x06000000
+
+/* UART7_CLK_ROOT */
+#define UART7_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define UART7_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x03000000
+#define UART7_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define UART7_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+#define UART7_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+#define UART7_CLK_ROOT_FROM_EXT_CLK_4 0x06000000
+
+/* ECSPI1_CLK_ROOT */
+#define ECSPI1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define ECSPI1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* ECSPI2_CLK_ROOT */
+#define ECSPI2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define ECSPI2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* ECSPI3_CLK_ROOT */
+#define ECSPI3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define ECSPI3_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* ECSPI4_CLK_ROOT */
+#define ECSPI4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_480M_CLK 0x04000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x03000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_SYS_PFD4_CLK 0x05000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_250M_CLK 0x06000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x02000000
+#define ECSPI4_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* PWM1_CLK_ROOT */
+#define PWM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define PWM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define PWM1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define PWM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define PWM1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define PWM1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
+#define PWM1_CLK_ROOT_FROM_EXT_CLK_1 0x05000000
+
+/* PWM2_CLK_ROOT */
+#define PWM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define PWM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define PWM2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define PWM2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define PWM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define PWM2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
+#define PWM2_CLK_ROOT_FROM_EXT_CLK_1 0x05000000
+
+/* PWM3_CLK_ROOT */
+#define PWM3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define PWM3_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define PWM3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define PWM3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define PWM3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define PWM3_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
+#define PWM3_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+
+/* PWM4_CLK_ROOT */
+#define PWM4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define PWM4_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define PWM4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define PWM4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define PWM4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define PWM4_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
+#define PWM4_CLK_ROOT_FROM_EXT_CLK_2 0x05000000
+
+/* FLEXTIMER1_CLK_ROOT */
+#define FLEXTIMER1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define FLEXTIMER1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define FLEXTIMER1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define FLEXTIMER1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define FLEXTIMER1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define FLEXTIMER1_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
+#define FLEXTIMER1_CLK_ROOT_FROM_EXT_CLK_3 0x05000000
+
+/* FLEXTIMER2_CLK_ROOT */
+#define FLEXTIMER2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define FLEXTIMER2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define FLEXTIMER2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define FLEXTIMER2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x04000000
+#define FLEXTIMER2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x07000000
+#define FLEXTIMER2_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
+#define FLEXTIMER2_CLK_ROOT_FROM_EXT_CLK_3 0x05000000
+
+/* SIM1_CLK_ROOT */
+#define SIM1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define SIM1_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define SIM1_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define SIM1_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define SIM1_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
+#define SIM1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define SIM1_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000
+
+/* SIM2_CLK_ROOT */
+#define SIM2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define SIM2_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define SIM2_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define SIM2_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define SIM2_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x06000000
+#define SIM2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x05000000
+#define SIM2_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x04000000
+
+/* GPT1_CLK_ROOT */
+#define GPT1_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define GPT1_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000
+#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define GPT1_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define GPT1_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define GPT1_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define GPT1_CLK_ROOT_FROM_REF_1M_CLK 0x05000000
+#define GPT1_CLK_ROOT_FROM_EXT_CLK_1 0x07000000
+
+/* GPT2_CLK_ROOT */
+#define GPT2_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define GPT2_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000
+#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define GPT2_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define GPT2_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define GPT2_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define GPT2_CLK_ROOT_FROM_REF_1M_CLK 0x05000000
+#define GPT2_CLK_ROOT_FROM_EXT_CLK_2 0x07000000
+
+/* GPT3_CLK_ROOT */
+#define GPT3_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define GPT3_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000
+#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define GPT3_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define GPT3_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define GPT3_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define GPT3_CLK_ROOT_FROM_REF_1M_CLK 0x05000000
+#define GPT3_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
+
+/* GPT4_CLK_ROOT */
+#define GPT4_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define GPT4_CLK_ROOT_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000
+#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
+#define GPT4_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x03000000
+#define GPT4_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x06000000
+#define GPT4_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x04000000
+#define GPT4_CLK_ROOT_FROM_REF_1M_CLK 0x05000000
+#define GPT4_CLK_ROOT_FROM_EXT_CLK_4 0x07000000
+
+/* TRACE_CLK_ROOT */
+#define TRACE_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define TRACE_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define TRACE_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define TRACE_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define TRACE_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000
+#define TRACE_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000
+#define TRACE_CLK_ROOT_FROM_EXT_CLK_1 0x06000000
+#define TRACE_CLK_ROOT_FROM_EXT_CLK_3 0x07000000
+
+/* WDOG_CLK_ROOT */
+#define WDOG_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define WDOG_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define WDOG_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD1_166M_CLK 0x07000000
+#define WDOG_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define WDOG_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000
+#define WDOG_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x05000000
+#define WDOG_CLK_ROOT_FROM_REF_1M_CLK 0x06000000
+
+/* CSI_MCLK_CLK_ROOT */
+#define CSI_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define CSI_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* AUDIO_MCLK_CLK_ROOT */
+#define AUDIO_MCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x03000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_120M_CLK 0x02000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_135M_CLK 0x01000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x04000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define AUDIO_MCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x07000000
+
+/* WRCLK_CLK_ROOT */
+#define WRCLK_CLK_ROOT_FROM_OSC_24M_CLK 0x00000000
+#define WRCLK_CLK_ROOT_FROM_PLL_DRAM_MAIN_533M_CLK 0x02000000
+#define WRCLK_CLK_ROOT_FROM_PLL_SYS_MAIN_240M_CLK 0x04000000
+#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD2_270M_CLK 0x05000000
+#define WRCLK_CLK_ROOT_FROM_PLL_SYS_PFD7_CLK 0x07000000
+#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_500M_CLK 0x06000000
+#define WRCLK_CLK_ROOT_FROM_PLL_ENET_MAIN_40M_CLK 0x01000000
+#define WRCLK_CLK_ROOT_FROM_PLL_USB_MAIN_480M_CLK 0x03000000
+
+/* IPP_DO_CLKO1 */
+#define IPP_DO_CLKO1_FROM_OSC_24M_CLK 0x00000000
+#define IPP_DO_CLKO1_FROM_PLL_DRAM_MAIN_533M_CLK 0x06000000
+#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_480M_CLK 0x01000000
+#define IPP_DO_CLKO1_FROM_PLL_SYS_MAIN_240M_CLK 0x02000000
+#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD0_196M_CLK 0x03000000
+#define IPP_DO_CLKO1_FROM_PLL_SYS_PFD3_CLK 0x04000000
+#define IPP_DO_CLKO1_FROM_PLL_ENET_MAIN_500M_CLK 0x05000000
+#define IPP_DO_CLKO1_FROM_REF_1M_CLK 0x07000000
+
+/* IPP_DO_CLKO2 */
+#define IPP_DO_CLKO2_FROM_OSC_24M_CLK 0x00000000
+#define IPP_DO_CLKO2_FROM_PLL_SYS_MAIN_240M_CLK 0x01000000
+#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD0_392M_CLK 0x02000000
+#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD1_166M_CLK 0x03000000
+#define IPP_DO_CLKO2_FROM_PLL_SYS_PFD4_CLK 0x04000000
+#define IPP_DO_CLKO2_FROM_PLL_AUDIO_MAIN_CLK 0x05000000
+#define IPP_DO_CLKO2_FROM_PLL_VIDEO_MAIN_CLK 0x06000000
+#define IPP_DO_CLKO2_FROM_OSC_32K_CLK 0x07000000
+
+#endif
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
new file mode 100644
index 0000000..4dc11ee
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -0,0 +1,1307 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MX7_IMX_REGS_H__
+#define __ASM_ARCH_MX7_IMX_REGS_H__
+
+#define ARCH_MXC
+
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+#define ROM_SW_INFO_ADDR 0x000001E8
+#define ROMCP_ARB_BASE_ADDR 0x00000000
+#define ROMCP_ARB_END_ADDR 0x00017FFF
+#define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR
+#define CAAM_ARB_BASE_ADDR 0x00100000
+#define CAAM_ARB_END_ADDR 0x00107FFF
+#define GIC400_ARB_BASE_ADDR 0x31000000
+#define GIC400_ARB_END_ADDR 0x31007FFF
+#define APBH_DMA_ARB_BASE_ADDR 0x33000000
+#define APBH_DMA_ARB_END_ADDR 0x33007FFF
+#define M4_BOOTROM_BASE_ADDR 0x00180000
+
+#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
+#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
+#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
+
+/* GPV - PL301 configuration ports */
+#define GPV0_BASE_ADDR 0x32000000
+#define GPV1_BASE_ADDR 0x32100000
+#define GPV2_BASE_ADDR 0x32200000
+#define GPV3_BASE_ADDR 0x32300000
+#define GPV4_BASE_ADDR 0x32400000
+#define GPV5_BASE_ADDR 0x32500000
+#define GPV6_BASE_ADDR 0x32600000
+#define GPV7_BASE_ADDR 0x32700000
+
+#define OCRAM_ARB_BASE_ADDR 0x00900000
+#define OCRAM_ARB_END_ADDR 0x0091FFFF
+#define OCRAM_EPDC_BASE_ADDR 0x00920000
+#define OCRAM_EPDC_END_ADDR 0x0093FFFF
+#define OCRAM_PXP_BASE_ADDR 0x00940000
+#define OCRAM_PXP_END_ADDR 0x00947FFF
+#define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR
+#define IRAM_SIZE 0x00020000
+
+#define AIPS1_ARB_BASE_ADDR 0x30000000
+#define AIPS1_ARB_END_ADDR 0x303FFFFF
+#define AIPS2_ARB_BASE_ADDR 0x30400000
+#define AIPS2_ARB_END_ADDR 0x307FFFFF
+#define AIPS3_ARB_BASE_ADDR 0x30800000
+#define AIPS3_ARB_END_ADDR 0x30BFFFFF
+
+#define WEIM_ARB_BASE_ADDR 0x28000000
+#define WEIM_ARB_END_ADDR 0x2FFFFFFF
+
+#define QSPI0_ARB_BASE_ADDR 0x60000000
+#define QSPI0_ARB_END_ADDR 0x6FFFFFFF
+#define PCIE_ARB_BASE_ADDR 0x40000000
+#define PCIE_ARB_END_ADDR 0x4FFFFFFF
+#define PCIE_REG_BASE_ADDR 0x33800000
+#define PCIE_REG_END_ADDR 0x33803FFF
+
+#define MMDC0_ARB_BASE_ADDR 0x80000000
+#define MMDC0_ARB_END_ADDR 0xBFFFFFFF
+#define MMDC1_ARB_BASE_ADDR 0xC0000000
+#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
+
+/* Cortex-A9 MPCore private memory region */
+#define ARM_PERIPHBASE 0x31000000
+#define SCU_BASE_ADDR ARM_PERIPHBASE
+#define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200)
+#define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600)
+
+
+/* Defines for Blocks connected via AIPS (SkyBlue) */
+#define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
+#define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
+#define AIPS_TZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR
+
+/* DAP base-address */
+#define ARM_IPS_BASE_ADDR AIPS1_ARB_BASE_ADDR
+
+/* AIPS_TZ#1- On Platform */
+#define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x1F0000)
+/* AIPS_TZ#1- Off Platform */
+#define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000)
+
+#define GPIO1_BASE_ADDR AIPS1_OFF_BASE_ADDR
+#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000)
+#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000)
+#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000)
+#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000)
+#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000)
+#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000)
+#define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000)
+#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000)
+#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000)
+#define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000)
+#define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000)
+#define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000)
+#define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000)
+#define GPT1_BASE_ADDR GPT_IPS_BASE_ADDR
+#define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000)
+#define GPT3_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xF0000)
+#define GPT4_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x100000)
+#define ROMCP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x110000)
+#define KPP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x120000)
+#define IOMUXC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x130000)
+#define IOMUXC_BASE_ADDR IOMUXC_IPS_BASE_ADDR
+#define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x140000)
+#define OCOTP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x150000)
+#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x160000)
+#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x170000)
+#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x180000)
+#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000)
+#define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000)
+#define SEMA41_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1B0000)
+#define SEMA42_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C0000)
+#define RDC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1D0000)
+#define CSU_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1E0000)
+
+/* AIPS_TZ#2- On Platform */
+#define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x1F0000)
+/* AIPS_TZ#2- Off Platform */
+#define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x200000)
+#define ADC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000)
+#define ADC2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000)
+#define ECSPI4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000)
+#define FTM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000)
+#define FTM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000)
+#define PWM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000)
+#define PWM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000)
+#define PWM3_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x80000)
+#define PWM4_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x90000)
+#define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xA0000)
+#define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xB0000)
+#define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000)
+#define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000)
+#define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000)
+#define EPDC_BASE_ADDR EPDC_IPS_BASE_ADDR
+#define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000)
+#define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000)
+#define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000)
+#define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000)
+#define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000)
+#define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000)
+#define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000)
+#define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000)
+#define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000)
+#define IP2APB_PERFMON2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1D0000)
+#define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000)
+#define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000)
+
+/* AIPS_TZ#3 - Global enable (0) */
+#define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000)
+#define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000)
+#define ECSPI3_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x40000)
+#define UART1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x60000)
+#define UART3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x80000)
+#define UART2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x90000)
+#define SAI1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xA0000)
+#define SAI2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xB0000)
+#define SAI3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xC0000)
+#define SPBA_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xF0000)
+#define CAAM_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x100000)
+
+/* AIPS_TZ#3- On Platform */
+#define AIPS3_ON_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x1F0000)
+/* AIPS_TZ#3- Off Platform */
+#define AIPS3_OFF_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x200000)
+#define CAN1_IPS_BASE_ADDR AIPS3_OFF_BASE_ADDR
+#define CAN2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x10000)
+#define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000)
+#define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000)
+#define I2C3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x40000)
+#define I2C4_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x50000)
+#define UART4_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x60000)
+#define UART5_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x70000)
+#define UART6_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x80000)
+#define UART7_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x90000)
+#define MUCPU_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xA0000)
+#define MUDSP_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xB0000)
+#define HS_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xC0000)
+#define USBOH2_PL301_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xD0000)
+#define USBOTG1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x110000)
+#define USBOTG2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x120000)
+#define USBHSIC_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x130000)
+#define USDHC1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x140000)
+#define USDHC2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x150000)
+#define USDHC3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x160000)
+#define EMVSIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000)
+#define EMVSIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000)
+#define SIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000)
+#define SIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000)
+#define QSPI1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1B0000)
+#define WEIM_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1C0000)
+#define SDMA_PORT_IPS_HOST_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1D0000)
+#define ENET_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1E0000)
+#define ENET2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1F0000)
+
+#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
+#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
+#define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR
+
+#define SDMA_IPS_HOST_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR
+#define SDMA_IPS_HOST_IPS_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR
+
+#define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR
+#define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR
+
+#define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR
+
+#define FEC_QUIRK_ENET_MAC
+#define SNVS_LPGPR 0x68
+
+#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
+#include <asm/types.h>
+
+extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
+
+/* System Reset Controller (SRC) */
+struct src {
+ u32 scr;
+ u32 a7rcr0;
+ u32 a7rcr1;
+ u32 m4rcr;
+ u32 reserved1;
+ u32 ercr;
+ u32 reserved2;
+ u32 hsicphy_rcr;
+ u32 usbophy1_rcr;
+ u32 usbophy2_rcr;
+ u32 mipiphy_rcr;
+ u32 pciephy_rcr;
+ u32 reserved3[10];
+ u32 sbmr1;
+ u32 srsr;
+ u32 reserved4[2];
+ u32 sisr;
+ u32 simr;
+ u32 sbmr2;
+ u32 gpr1;
+ u32 gpr2;
+ u32 gpr3;
+ u32 gpr4;
+ u32 gpr5;
+ u32 gpr6;
+ u32 gpr7;
+ u32 gpr8;
+ u32 gpr9;
+ u32 gpr10;
+ u32 reserved5[985];
+ u32 ddrc_rcr;
+};
+
+/* GPR0 Bit Fields */
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u
+#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6
+/* GPR1 Bit Fields */
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK)
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK 0x8u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_SHIFT 3
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK 0x30u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT 4
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK)
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK 0x40u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_SHIFT 6
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK 0x180u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT 7
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK)
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK 0x200u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_SHIFT 9
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK 0xC00u
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT 10
+#define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK)
+#define IOMUXC_GPR_GPR1_GPR_IRQ_MASK 0x1000u
+#define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT 12
+#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u
+#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13
+#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u
+#define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_SHIFT 14
+#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u
+#define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_SHIFT 15
+#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK 0x10000u
+#define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_SHIFT 16
+#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK 0x20000u
+#define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_SHIFT 17
+#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u
+#define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_SHIFT 18
+#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u
+#define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_SHIFT 22
+#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u
+#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT 23
+#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK 0x30000000u
+#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT 28
+#define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK)
+#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u
+#define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_SHIFT 30
+/* GPR2 Bit Fields */
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK 0x2u
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_SHIFT 1
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK 0x4u
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_SHIFT 2
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK 0x8u
+#define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_SHIFT 3
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_SHIFT 4
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK 0x20u
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_SHIFT 5
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK 0x40u
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_SHIFT 6
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK 0x80u
+#define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_SHIFT 7
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_SHIFT 8
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK 0x200u
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_SHIFT 9
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK 0x400u
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_SHIFT 10
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK 0x800u
+#define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_SHIFT 11
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_SHIFT 12
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK 0x2000u
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_SHIFT 13
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK 0x4000u
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_SHIFT 14
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK 0x8000u
+#define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_SHIFT 15
+#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK 0xFF0000u
+#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT 16
+#define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK)
+#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK 0x1000000u
+#define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_SHIFT 24
+#define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK 0x2000000u
+#define IOMUXC_GPR_GPR2_GPR_MQS_EN_SHIFT 25
+#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK 0x4000000u
+#define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_SHIFT 26
+#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u
+#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_SHIFT 27
+#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK 0x10000000u
+#define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_SHIFT 28
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK 0x20000000u
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_SHIFT 29
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK 0x40000000u
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_SHIFT 30
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u
+#define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_SHIFT 31
+/* GPR3 Bit Fields */
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_SHIFT 1
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_SHIFT 2
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_SHIFT 3
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_SHIFT 4
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_SHIFT 5
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_SHIFT 6
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_SHIFT 7
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_SHIFT 8
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_SHIFT 9
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_SHIFT 10
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_SHIFT 11
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_SHIFT 12
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_SHIFT 13
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_SHIFT 14
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u
+#define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_SHIFT 15
+#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_SHIFT 16
+#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_SHIFT 17
+#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_SHIFT 18
+#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_SHIFT 19
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_SHIFT 20
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_SHIFT 21
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_SHIFT 22
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_SHIFT 23
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_SHIFT 24
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_SHIFT 25
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_SHIFT 26
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_SHIFT 27
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_SHIFT 28
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_SHIFT 29
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_SHIFT 30
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u
+#define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_SHIFT 31
+/* GPR4 Bit Fields */
+#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK 0x1u
+#define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT 0
+#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK 0x2u
+#define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT 1
+#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK 0x4u
+#define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT 2
+#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK 0x8u
+#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT 3
+#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK 0x10u
+#define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_SHIFT 4
+#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK 0x20u
+#define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_SHIFT 5
+#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK 0x40u
+#define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_SHIFT 6
+#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK 0x80u
+#define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_SHIFT 7
+#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK 0x10000u
+#define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_SHIFT 16
+#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK 0x20000u
+#define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_SHIFT 17
+#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK 0x40000u
+#define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_SHIFT 18
+#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK 0x80000u
+#define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_SHIFT 19
+#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK 0x100000u
+#define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_SHIFT 20
+#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK 0x200000u
+#define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_SHIFT 21
+#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK 0x400000u
+#define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_SHIFT 22
+#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK 0x800000u
+#define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_SHIFT 23
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK 0x6000000u
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT 25
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK)
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK 0x18000000u
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT 27
+#define IOMUXC_GPR_GPR4_cpu_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK)
+/* GPR5 Bit Fields */
+#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u
+#define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_SHIFT 4
+#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u
+#define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_SHIFT 5
+#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK 0x40u
+#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT 6
+#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK 0x80u
+#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT 7
+#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u
+#define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_SHIFT 12
+#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK 0x80000u
+#define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_SHIFT 19
+#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK 0x100000u
+#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT 20
+#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u
+#define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_SHIFT 21
+#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK 0x400000u
+#define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_SHIFT 22
+#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u
+#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_SHIFT 24
+#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u
+#define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_SHIFT 25
+#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u
+#define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_SHIFT 26
+#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u
+#define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_SHIFT 27
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_SHIFT 28
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_SHIFT 29
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_SHIFT 30
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u
+#define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_SHIFT 31
+/* GPR6 Bit Fields */
+#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK 0x1u
+#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT 0
+#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK 0x2u
+#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_SHIFT 1
+#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u
+#define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_SHIFT 2
+#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u
+#define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_SHIFT 3
+/* GPR7 Bit Fields */
+#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u
+#define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0
+#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u
+#define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_SHIFT 1
+#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u
+#define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_SHIFT 2
+#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u
+#define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_SHIFT 3
+#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u
+#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT 4
+#define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK)
+#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u
+#define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_SHIFT 6
+#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u
+#define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_SHIFT 7
+#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u
+#define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_SHIFT 8
+#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u
+#define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_SHIFT 9
+#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u
+#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT 10
+#define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK)
+#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u
+#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_SHIFT 12
+#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u
+#define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_SHIFT 13
+/* GPR8 Bit Fields */
+#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u
+#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT 3
+#define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT))&IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK)
+#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u
+#define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_SHIFT 8
+/* GPR9 Bit Fields */
+#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u
+#define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0
+#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK 0x3Eu
+#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT 1
+#define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT))&IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK)
+/* GPR10 Bit Fields */
+#define IOMUXC_GPR_GPR10_GPR0_BF0_MASK 0x1u
+#define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT 0
+#define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK 0x2u
+#define IOMUXC_GPR_GPR10_GPR_DBG_EN_SHIFT 1
+#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u
+#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT 2
+#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u
+#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_SHIFT 3
+#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u
+#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT 4
+#define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK)
+/* GPR11 Bit Fields */
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT 1
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK)
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_SHIFT 6
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT 7
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK)
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT 10
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT 11
+#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK)
+/* GPR12 Bit Fields */
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_SHIFT 1
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_SHIFT 3
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_SHIFT 4
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_SHIFT 5
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT 12
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK)
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK)
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21
+#define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK)
+/* GPR13 Bit Fields */
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK 0x1u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK 0x2u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT 1
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK 0x4u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_SHIFT 2
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK 0x8u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_SHIFT 3
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK 0x10u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT 4
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK 0x20u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT 5
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK 0x40u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_SHIFT 6
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK 0x80u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_SHIFT 7
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_SHIFT 8
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_SHIFT 9
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT 10
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT 11
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_SHIFT 12
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u
+#define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_SHIFT 13
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK 0x4000u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_SHIFT 14
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u
+#define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_SHIFT 15
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK)
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT 24
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK)
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u
+#define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31
+/* GPR14 Bit Fields */
+#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u
+#define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0
+#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u
+#define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_SHIFT 1
+/* GPR15 Bit Fields */
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_SHIFT 1
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT 2
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK)
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT 16
+#define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK)
+/* GPR16 Bit Fields */
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK)
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_SHIFT 2
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_SHIFT 3
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_SHIFT 4
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK 0x20u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_SHIFT 5
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK 0x3C0u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT 6
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK)
+#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_SHIFT 10
+#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK 0x800u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_SHIFT 11
+#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK 0x1000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_SHIFT 12
+#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK 0xE000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT 13
+#define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK)
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK 0x10000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_SHIFT 16
+#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_SHIFT 17
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT 19
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK)
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_SHIFT 21
+#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK 0x400000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_SHIFT 22
+#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u
+#define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_SHIFT 23
+/* GPR17 Bit Fields */
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK)
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT 8
+#define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK)
+/* GPR18 Bit Fields */
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT 3
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT 5
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT 8
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_SHIFT 14
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT 16
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT 24
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK)
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_SHIFT 26
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_SHIFT 27
+#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK 0x10000000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_SHIFT 28
+#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u
+#define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_SHIFT 29
+/* GPR19 Bit Fields */
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT 8
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK)
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u
+#define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_SHIFT 16
+#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u
+#define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_SHIFT 17
+/* GPR20 Bit Fields */
+#define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK 0x3Fu
+#define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT 0
+#define IOMUXC_GPR_GPR20_GPR_LVDS_P(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK)
+#define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK 0x3F00u
+#define IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT 8
+#define IOMUXC_GPR_GPR20_GPR_LVDS_M(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK)
+#define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK 0x30000u
+#define IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT 16
+#define IOMUXC_GPR_GPR20_GPR_LVDS_S(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK)
+#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK 0x1000000u
+#define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_SHIFT 24
+#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u
+#define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_SHIFT 25
+#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u
+#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT 27
+#define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK)
+/* GPR21 Bit Fields */
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK 0x7u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT 0
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK)
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK 0x38u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT 3
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK)
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK 0x1C0u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT 6
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK)
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK 0xE00u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT 9
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK)
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK 0x7000u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT 12
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK)
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK 0x38000u
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT 15
+#define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK)
+#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK 0x40000u
+#define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18
+#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK 0x80000u
+#define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19
+/* GPR22 Bit Fields */
+#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK 0xFF0000u
+#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT 16
+#define IOMUXC_GPR_GPR22_ddrc_mrr_data_out(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT))&IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK)
+#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u
+#define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_SHIFT 24
+#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u
+#define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_SHIFT 25
+#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u
+#define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_SHIFT 26
+#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u
+#define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_SHIFT 27
+#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u
+#define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_SHIFT 28
+#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u
+#define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_SHIFT 29
+#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u
+#define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_SHIFT 31
+
+#define IMX7D_GPR5_CSI1_MUX_CTRL_MASK (0x1 << 4)
+#define IMX7D_GPR5_CSI1_MUX_CTRL_PARALLEL_CSI (0x0 << 4)
+#define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI (0x1 << 4)
+
+struct iomuxc {
+ u32 gpr[23];
+ /* mux and pad registers */
+};
+
+struct iomuxc_gpr_base_regs {
+ u32 gpr[23]; /* 0x000 */
+};
+
+/* ECSPI registers */
+struct cspi_regs {
+ u32 rxdata;
+ u32 txdata;
+ u32 ctrl;
+ u32 cfg;
+ u32 intr;
+ u32 dma;
+ u32 stat;
+ u32 period;
+};
+
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN (1 << 0)
+#define MXC_CSPICTRL_MODE (1 << 1)
+#define MXC_CSPICTRL_XCH (1 << 2)
+#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
+#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS 0xfff
+#define MXC_CSPICTRL_TC (1 << 7)
+#define MXC_CSPICTRL_RXOVF (1 << 6)
+#define MXC_CSPIPERIOD_32KHZ (1 << 15)
+#define MAX_SPI_BYTES 32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN 18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_PHA 0 /* SCLK phase control */
+#define MXC_CSPICON_POL 4 /* SCLK polarity */
+#define MXC_CSPICON_SSPOL 12 /* SS polarity */
+#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
+
+#define MXC_SPI_BASE_ADDRESSES \
+ ECSPI1_BASE_ADDR, \
+ ECSPI2_BASE_ADDR, \
+ ECSPI3_BASE_ADDR, \
+ ECSPI4_BASE_ADDR
+
+struct ocotp_regs {
+ u32 ctrl;
+ u32 ctrl_set;
+ u32 ctrl_clr;
+ u32 ctrl_tog;
+ u32 timing;
+ u32 rsvd0[3];
+ u32 data0;
+ u32 rsvd1[3];
+ u32 data1;
+ u32 rsvd2[3];
+ u32 data2;
+ u32 rsvd3[3];
+ u32 data3;
+ u32 rsvd4[3];
+ u32 read_ctrl;
+ u32 rsvd5[3];
+ u32 read_fuse_data0;
+ u32 rsvd6[3];
+ u32 read_fuse_data1;
+ u32 rsvd7[3];
+ u32 read_fuse_data2;
+ u32 rsvd8[3];
+ u32 read_fuse_data3;
+ u32 rsvd9[3];
+ u32 sw_sticky;
+ u32 rsvd10[3];
+ u32 scs;
+ u32 scs_set;
+ u32 scs_clr;
+ u32 scs_tog;
+ u32 crc_addr;
+ u32 rsvd11[3];
+ u32 crc_value;
+ u32 rsvd12[3];
+ u32 version;
+ u32 rsvd13[0xc3];
+
+ struct fuse_bank { /* offset 0x400 */
+ u32 fuse_regs[0x10];
+ } bank[16];
+};
+
+struct fuse_bank0_regs {
+ u32 lock;
+ u32 rsvd0[3];
+ u32 tester0;
+ u32 rsvd1[3];
+ u32 tester1;
+ u32 rsvd2[3];
+ u32 tester2;
+ u32 rsvd3[3];
+};
+
+struct fuse_bank1_regs {
+ u32 tester3;
+ u32 rsvd0[3];
+ u32 tester4;
+ u32 rsvd1[3];
+ u32 tester5;
+ u32 rsvd2[3];
+ u32 cfg0;
+ u32 rsvd3[3];
+};
+
+struct fuse_bank2_regs {
+ u32 cfg1;
+ u32 rsvd0[3];
+ u32 cfg2;
+ u32 rsvd1[3];
+ u32 cfg3;
+ u32 rsvd2[3];
+ u32 cfg4;
+ u32 rsvd3[3];
+};
+
+struct fuse_bank3_regs {
+ u32 mem_trim0;
+ u32 rsvd0[3];
+ u32 mem_trim1;
+ u32 rsvd1[3];
+ u32 ana0;
+ u32 rsvd2[3];
+ u32 ana1;
+ u32 rsvd3[3];
+};
+
+struct fuse_bank8_regs {
+ u32 sjc_resp_low;
+ u32 rsvd0[3];
+ u32 sjc_resp_high;
+ u32 rsvd1[3];
+ u32 usb_id;
+ u32 rsvd2[3];
+ u32 field_return;
+ u32 rsvd3[3];
+};
+
+struct fuse_bank9_regs {
+ u32 mac_addr0;
+ u32 rsvd0[3];
+ u32 mac_addr1;
+ u32 rsvd1[3];
+ u32 mac_addr2;
+ u32 rsvd2[7];
+};
+
+struct aipstz_regs {
+ u32 mprot0;
+ u32 mprot1;
+ u32 rsvd[0xe];
+ u32 opacr0;
+ u32 opacr1;
+ u32 opacr2;
+ u32 opacr3;
+ u32 opacr4;
+};
+
+struct wdog_regs {
+ u16 wcr; /* Control */
+ u16 wsr; /* Service */
+ u16 wrsr; /* Reset Status */
+ u16 wicr; /* Interrupt Control */
+ u16 wmcr; /* Miscellaneous Control */
+};
+
+struct dbg_monitor_regs {
+ u32 ctrl[4]; /* Control */
+ u32 master_en[4]; /* Master enable */
+ u32 irq[4]; /* IRQ */
+ u32 trap_addr_low[4]; /* Trap address low */
+ u32 trap_addr_high[4]; /* Trap address high */
+ u32 trap_id[4]; /* Trap ID */
+ u32 snvs_addr[4]; /* SNVS address */
+ u32 snvs_data[4]; /* SNVS data */
+ u32 snvs_info[4]; /* SNVS info */
+ u32 version[4]; /* Version */
+};
+
+struct rdc_regs {
+ u32 vir; /* Version information */
+ u32 reserved1[8];
+ u32 stat; /* Status */
+ u32 intctrl; /* Interrupt and Control */
+ u32 intstat; /* Interrupt Status */
+ u32 reserved2[116];
+ u32 mda[27]; /* Master Domain Assignment */
+ u32 reserved3[101];
+ u32 pdap[118]; /* Peripheral Domain Access Permissions */
+ u32 reserved4[138];
+ struct {
+ u32 mrsa; /* Memory Region Start Address */
+ u32 mrea; /* Memory Region End Address */
+ u32 mrc; /* Memory Region Control */
+ u32 mrvs; /* Memory Region Violation Status */
+ } mem_region[52];
+};
+
+struct rdc_sema_regs {
+ u8 gate[64]; /* Gate */
+ u16 rstgt; /* Reset Gate */
+};
+
+/* eLCDIF controller registers */
+struct mxs_lcdif_regs {
+ u32 hw_lcdif_ctrl; /* 0x00 */
+ u32 hw_lcdif_ctrl_set;
+ u32 hw_lcdif_ctrl_clr;
+ u32 hw_lcdif_ctrl_tog;
+ u32 hw_lcdif_ctrl1; /* 0x10 */
+ u32 hw_lcdif_ctrl1_set;
+ u32 hw_lcdif_ctrl1_clr;
+ u32 hw_lcdif_ctrl1_tog;
+ u32 hw_lcdif_ctrl2; /* 0x20 */
+ u32 hw_lcdif_ctrl2_set;
+ u32 hw_lcdif_ctrl2_clr;
+ u32 hw_lcdif_ctrl2_tog;
+ u32 hw_lcdif_transfer_count; /* 0x30 */
+ u32 reserved1[3];
+ u32 hw_lcdif_cur_buf; /* 0x40 */
+ u32 reserved2[3];
+ u32 hw_lcdif_next_buf; /* 0x50 */
+ u32 reserved3[3];
+ u32 hw_lcdif_timing; /* 0x60 */
+ u32 reserved4[3];
+ u32 hw_lcdif_vdctrl0; /* 0x70 */
+ u32 hw_lcdif_vdctrl0_set;
+ u32 hw_lcdif_vdctrl0_clr;
+ u32 hw_lcdif_vdctrl0_tog;
+ u32 hw_lcdif_vdctrl1; /* 0x80 */
+ u32 reserved5[3];
+ u32 hw_lcdif_vdctrl2; /* 0x90 */
+ u32 reserved6[3];
+ u32 hw_lcdif_vdctrl3; /* 0xa0 */
+ u32 reserved7[3];
+ u32 hw_lcdif_vdctrl4; /* 0xb0 */
+ u32 reserved8[3];
+ u32 hw_lcdif_dvictrl0; /* 0xc0 */
+ u32 reserved9[3];
+ u32 hw_lcdif_dvictrl1; /* 0xd0 */
+ u32 reserved10[3];
+ u32 hw_lcdif_dvictrl2; /* 0xe0 */
+ u32 reserved11[3];
+ u32 hw_lcdif_dvictrl3; /* 0xf0 */
+ u32 reserved12[3];
+ u32 hw_lcdif_dvictrl4; /* 0x100 */
+ u32 reserved13[3];
+ u32 hw_lcdif_csc_coeffctrl0; /* 0x110 */
+ u32 reserved14[3];
+ u32 hw_lcdif_csc_coeffctrl1; /* 0x120 */
+ u32 reserved15[3];
+ u32 hw_lcdif_csc_coeffctrl2; /* 0x130 */
+ u32 reserved16[3];
+ u32 hw_lcdif_csc_coeffctrl3; /* 0x140 */
+ u32 reserved17[3];
+ u32 hw_lcdif_csc_coeffctrl4; /* 0x150 */
+ u32 reserved18[3];
+ u32 hw_lcdif_csc_offset; /* 0x160 */
+ u32 reserved19[3];
+ u32 hw_lcdif_csc_limit; /* 0x170 */
+ u32 reserved20[3];
+ u32 hw_lcdif_data; /* 0x180 */
+ u32 reserved21[3];
+ u32 hw_lcdif_bm_error_stat; /* 0x190 */
+ u32 reserved22[3];
+ u32 hw_lcdif_crc_stat; /* 0x1a0 */
+ u32 reserved23[3];
+ u32 hw_lcdif_lcdif_stat; /* 0x1b0 */
+ u32 reserved24[3];
+ u32 hw_lcdif_version; /* 0x1c0 */
+ u32 reserved25[3];
+ u32 hw_lcdif_debug0; /* 0x1d0 */
+ u32 reserved26[3];
+ u32 hw_lcdif_debug1; /* 0x1e0 */
+ u32 reserved27[3];
+ u32 hw_lcdif_debug2; /* 0x1f0 */
+ u32 reserved28[3];
+ u32 hw_lcdif_thres; /* 0x200 */
+ u32 reserved29[3];
+ u32 hw_lcdif_as_ctrl; /* 0x210 */
+ u32 reserved30[3];
+ u32 hw_lcdif_as_buf; /* 0x220 */
+ u32 reserved31[3];
+ u32 hw_lcdif_as_next_buf; /* 0x230 */
+ u32 reserved32[3];
+ u32 hw_lcdif_as_clrkeylow; /* 0x240 */
+ u32 reserved33[3];
+ u32 hw_lcdif_as_clrkeyhigh; /* 0x250 */
+ u32 reserved34[3];
+ u32 hw_lcdif_as_sync_delay; /* 0x260 */
+ u32 reserved35[3];
+ u32 hw_lcdif_as_debug3; /* 0x270 */
+ u32 reserved36[3];
+ u32 hw_lcdif_as_debug4; /* 0x280 */
+ u32 reserved37[3];
+ u32 hw_lcdif_as_debug5; /* 0x290 */
+};
+
+#define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR
+
+#define LCDIF_CTRL_SFTRST (1 << 31)
+#define LCDIF_CTRL_CLKGATE (1 << 30)
+#define LCDIF_CTRL_YCBCR422_INPUT (1 << 29)
+#define LCDIF_CTRL_READ_WRITEB (1 << 28)
+#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27)
+#define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26)
+#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21)
+#define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21
+#define LCDIF_CTRL_DVI_MODE (1 << 20)
+#define LCDIF_CTRL_BYPASS_COUNT (1 << 19)
+#define LCDIF_CTRL_VSYNC_MODE (1 << 18)
+#define LCDIF_CTRL_DOTCLK_MODE (1 << 17)
+#define LCDIF_CTRL_DATA_SELECT (1 << 16)
+#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14)
+#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14
+#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12)
+#define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10)
+#define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10)
+#define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_OFFSET 8
+#define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8)
+#define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8)
+#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7)
+#define LCDIF_CTRL_LCDIF_MASTER (1 << 5)
+#define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3)
+#define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2)
+#define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1)
+#define LCDIF_CTRL_RUN (1 << 0)
+
+#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27)
+#define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26)
+#define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25)
+#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24)
+#define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23)
+#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22)
+#define LCDIF_CTRL1_FIFO_CLEAR (1 << 21)
+#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20)
+#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)
+#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16
+#define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15)
+#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14)
+#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13)
+#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12)
+#define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11)
+#define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10)
+#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9)
+#define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8)
+#define LCDIF_CTRL1_BUSY_ENABLE (1 << 2)
+#define LCDIF_CTRL1_MODE86 (1 << 1)
+#define LCDIF_CTRL1_RESET (1 << 0)
+
+#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21)
+#define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21)
+#define LCDIF_CTRL2_BURST_LEN_8 (1 << 20)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16)
+#define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12)
+#define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12)
+#define LCDIF_CTRL2_READ_PACK_DIR (1 << 10)
+#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9)
+#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8)
+#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4)
+#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4
+#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1)
+#define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1
+
+#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)
+#define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16
+#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)
+#define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0
+
+#define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff
+#define LCDIF_CUR_BUF_ADDR_OFFSET 0
+
+#define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff
+#define LCDIF_NEXT_BUF_ADDR_OFFSET 0
+
+#define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24)
+#define LCDIF_TIMING_CMD_HOLD_OFFSET 24
+#define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16)
+#define LCDIF_TIMING_CMD_SETUP_OFFSET 16
+#define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8)
+#define LCDIF_TIMING_DATA_HOLD_OFFSET 8
+#define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0)
+#define LCDIF_TIMING_DATA_SETUP_OFFSET 0
+
+#define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29)
+#define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28)
+#define LCDIF_VDCTRL0_VSYNC_POL (1 << 27)
+#define LCDIF_VDCTRL0_HSYNC_POL (1 << 26)
+#define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25)
+#define LCDIF_VDCTRL0_ENABLE_POL (1 << 24)
+#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21)
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20)
+#define LCDIF_VDCTRL0_HALF_LINE (1 << 19)
+#define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18)
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff
+#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0
+
+#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
+#define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
+
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
+#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18
+#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
+#define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
+
+#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29)
+#define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28)
+#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)
+#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16
+#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)
+#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0
+
+#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)
+#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29
+#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18)
+#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
+#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
+
+
+extern void check_cpu_temperature(void);
+
+extern void pcie_power_up(void);
+extern void pcie_power_off(void);
+
+/* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB
+ * If boot from the other mode, USB0_PWD will keep reset value
+ */
+#define is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \
+ readl(USBOTG2_IPS_BASE_ADDR + 0x158))
+#define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140)
+
+/* Boot device type */
+#define BOOT_TYPE_SD 0x1
+#define BOOT_TYPE_MMC 0x2
+#define BOOT_TYPE_NAND 0x3
+#define BOOT_TYPE_QSPI 0x4
+#define BOOT_TYPE_WEIM 0x5
+#define BOOT_TYPE_SPINOR 0x6
+
+struct bootrom_sw_info {
+ u8 reserved_1;
+ u8 boot_dev_instance;
+ u8 boot_dev_type;
+ u8 reserved_2;
+ u32 arm_core_freq;
+ u32 axi_freq;
+ u32 ddr_freq;
+ u32 gpt1_freq;
+ u32 reserved_3[3];
+};
+
+#endif /* __ASSEMBLER__*/
+#endif /* __ASM_ARCH_MX7_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-mx7/sys_proto.h b/arch/arm/include/asm/arch-mx7/sys_proto.h
new file mode 100644
index 0000000..ca7608b
--- /dev/null
+++ b/arch/arm/include/asm/arch-mx7/sys_proto.h
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/imx-common/sys_proto.h>
+
+void set_wdog_reset(struct wdog_regs *wdog);
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index 6109b92..b1513e9 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -56,8 +56,6 @@ struct watchdog {
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
-#define BIT(x) (1 << (x))
-
#define WD_UNLOCK1 0xAAAA
#define WD_UNLOCK2 0x5555
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/include/asm/arch-rmobile/rcar-base.h
index d594cd7..53ead26 100644
--- a/arch/arm/include/asm/arch-rmobile/rcar-base.h
+++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h
@@ -28,6 +28,9 @@
#define SCIF3_BASE 0xE6EA8000
#define SCIF4_BASE 0xE6EE0000
#define SCIF5_BASE 0xE6EE8000
+#define SCIFA0_BASE 0xE6C40000
+#define SCIFA1_BASE 0xE6C50000
+#define SCIFA2_BASE 0xE6C60000
/* Module stop status register */
#define MSTPSR0 0xE6150030
diff --git a/arch/arm/include/asm/arch-spear/spr_misc.h b/arch/arm/include/asm/arch-spear/spr_misc.h
index b55026e..6f2e19e 100644
--- a/arch/arm/include/asm/arch-spear/spr_misc.h
+++ b/arch/arm/include/asm/arch-spear/spr_misc.h
@@ -253,5 +253,6 @@ struct misc_regs {
#define SOC_SPEAR320 203
extern int get_socrev(void);
+int fsmc_nand_switch_ecc(uint32_t eccstrength);
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h
index acbec46..a129dd4 100644
--- a/arch/arm/include/asm/arch-sunxi/spl.h
+++ b/arch/arm/include/asm/arch-sunxi/spl.h
@@ -1,20 +1,50 @@
/*
- * This is a copy of omap3/spl.h:
- *
- * (C) Copyright 2012
- * Texas Instruments, <www.ti.com>
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SPL_H_
#define _ASM_ARCH_SPL_H_
-#define BOOT_DEVICE_NONE 0
-#define BOOT_DEVICE_XIP 1
-#define BOOT_DEVICE_NAND 2
-#define BOOT_DEVICE_ONE_NAND 3
-#define BOOT_DEVICE_MMC2 5 /*emmc*/
-#define BOOT_DEVICE_MMC1 6
-#define BOOT_DEVICE_XIPWAIT 7
-#define BOOT_DEVICE_MMC2_2 0xff
+#define BOOT0_MAGIC "eGON.BT0"
+#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */
+#define SPL_HEADER_VERSION 1
+
+/* Note: A80 will require special handling here: SPL_ADDR 0x10000 */
+#define SPL_ADDR 0x0
+
+/* boot head definition from sun4i boot code */
+struct boot_file_head {
+ uint32_t b_instruction; /* one intruction jumping to real code */
+ uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */
+ uint32_t check_sum; /* generated by PC */
+ uint32_t length; /* generated by PC */
+ /*
+ * We use a simplified header, only filling in what is needed
+ * by the boot ROM. To be compatible with Allwinner tools we
+ * would need to implement the proper fields here instead of
+ * padding.
+ *
+ * Actually we want the ability to recognize our "sunxi" variant
+ * of the SPL. To do so, let's place a special signature into the
+ * "pub_head_size" field. We can reasonably expect Allwinner's
+ * boot0 to always have the upper 16 bits of this set to 0 (after
+ * all the value shouldn't be larger than the limit imposed by
+ * SRAM size).
+ * If the signature is present (at 0x14), then we know it's safe
+ * to use the remaining 8 bytes (at 0x18) for our own purposes.
+ * (E.g. sunxi-tools "fel" utility can pass information there.)
+ */
+ union {
+ uint32_t pub_head_size;
+ uint8_t spl_signature[4];
+ };
+ uint32_t fel_script_address;
+ uint32_t reserved; /* padding, align to 32 bytes */
+};
+
+#define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0)
+
#endif
diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index d570d7f..e56031d 100644
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -44,6 +44,9 @@ enum {
/* return the current oscillator clock frequency */
enum clock_osc_freq clock_get_osc_freq(void);
+/* return the clk_m frequency */
+unsigned int clk_m_get_rate(unsigned int parent_rate);
+
/**
* Start PLL using the provided configuration parameters.
*
@@ -338,8 +341,8 @@ void arch_timer_init(void);
void tegra30_set_up_pllp(void);
-/* Number of PLL-based clocks (i.e. not OSC or 32KHz) */
-#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 2)
+/* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */
+#define CLOCK_ID_PLL_COUNT (CLOCK_ID_COUNT - 3)
struct clk_pll_info {
u32 m_shift:5; /* DIVM_SHIFT */
diff --git a/arch/arm/include/asm/arch-tegra/dc.h b/arch/arm/include/asm/arch-tegra/dc.h
index 6ffb468..3a87f0b 100644
--- a/arch/arm/include/asm/arch-tegra/dc.h
+++ b/arch/arm/include/asm/arch-tegra/dc.h
@@ -364,8 +364,6 @@ struct dc_ctlr {
struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80d */
};
-#define BIT(pos) (1U << pos)
-
/* DC_CMD_DISPLAY_COMMAND 0x032 */
#define CTRL_MODE_SHIFT 5
#define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT)
diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h
index 7334e0c..daf5698 100644
--- a/arch/arm/include/asm/arch-tegra/gpio.h
+++ b/arch/arm/include/asm/arch-tegra/gpio.h
@@ -28,15 +28,6 @@ struct tegra_gpio_config {
};
/**
- * tegra_spl_gpio_direction_output() - set the output value of a GPIO
- *
- * This function is only used from SPL on seaboard, which needs to enable a
- * GPIO to get the UART running. It could be done in U-Boot rather than SPL,
- * but for now, this gets it working
- */
-int tegra_spl_gpio_direction_output(int gpio, int value);
-
-/**
* Configure a list of GPIOs
*
* @param config List of GPIO configurations
diff --git a/arch/arm/include/asm/arch-tegra114/clock-tables.h b/arch/arm/include/asm/arch-tegra114/clock-tables.h
index d8fa0e1..3f910f5 100644
--- a/arch/arm/include/asm/arch-tegra114/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra114/clock-tables.h
@@ -38,6 +38,7 @@ enum clock_id {
/* These are the base clocks (inputs to the Tegra SOC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
+ CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of PLLs */
CLOCK_ID_DISPLAY2, /* placeholder */
diff --git a/arch/arm/include/asm/arch-tegra114/clock.h b/arch/arm/include/asm/arch-tegra114/clock.h
index abbefcd..9bee397 100644
--- a/arch/arm/include/asm/arch-tegra114/clock.h
+++ b/arch/arm/include/asm/arch-tegra114/clock.h
@@ -25,4 +25,7 @@
#define OSC_FREQ_SHIFT 28
#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
+/* CLK_RST_CONTROLLER_PLLC_MISC_0 */
+#define PLLC_IDDQ (1 << 26)
+
#endif /* _TEGRA114_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/clock-tables.h b/arch/arm/include/asm/arch-tegra124/clock-tables.h
index 3c67e72..9466b4f 100644
--- a/arch/arm/include/asm/arch-tegra124/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra124/clock-tables.h
@@ -30,6 +30,7 @@ enum clock_id {
/* These are the base clocks (inputs to the Tegra SoC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
+ CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of PLLs */
diff --git a/arch/arm/include/asm/arch-tegra124/clock.h b/arch/arm/include/asm/arch-tegra124/clock.h
index e202cc5..ff99b9d 100644
--- a/arch/arm/include/asm/arch-tegra124/clock.h
+++ b/arch/arm/include/asm/arch-tegra124/clock.h
@@ -16,6 +16,9 @@
#define OSC_FREQ_SHIFT 28
#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
+/* CLK_RST_CONTROLLER_PLLC_MISC_0 */
+#define PLLC_IDDQ (1 << 26)
+
/* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */
#define SOR0_CLK_SEL0 (1 << 14)
#define SOR0_CLK_SEL1 (1 << 15)
diff --git a/arch/arm/include/asm/arch-tegra20/clock-tables.h b/arch/arm/include/asm/arch-tegra20/clock-tables.h
index 894be08..812e876 100644
--- a/arch/arm/include/asm/arch-tegra20/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra20/clock-tables.h
@@ -29,6 +29,7 @@ enum clock_id {
/* These are the base clocks (inputs to the Tegra SOC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
+ CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of clocks */
CLOCK_ID_NONE = -1,
diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/include/asm/arch-tegra210/clock-tables.h
index 175040d..a612485 100644
--- a/arch/arm/include/asm/arch-tegra210/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra210/clock-tables.h
@@ -30,6 +30,7 @@ enum clock_id {
/* These are the base clocks (inputs to the Tegra SoC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
+ CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of PLLs */
diff --git a/arch/arm/include/asm/arch-tegra30/clock-tables.h b/arch/arm/include/asm/arch-tegra30/clock-tables.h
index cb619f1..f7c7af8 100644
--- a/arch/arm/include/asm/arch-tegra30/clock-tables.h
+++ b/arch/arm/include/asm/arch-tegra30/clock-tables.h
@@ -38,6 +38,7 @@ enum clock_id {
/* These are the base clocks (inputs to the Tegra SOC) */
CLOCK_ID_32KHZ,
CLOCK_ID_OSC,
+ CLOCK_ID_CLK_M,
CLOCK_ID_COUNT, /* number of PLLs */
CLOCK_ID_DISPLAY2, /* Tegra3, placeholder */
diff --git a/arch/arm/include/asm/arch-u8500/clock.h b/arch/arm/include/asm/arch-u8500/clock.h
deleted file mode 100644
index 1b2fdb7..0000000
--- a/arch/arm/include/asm/arch-u8500/clock.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_CLOCK
-#define __ASM_ARCH_CLOCK
-
-struct prcmu {
- unsigned int armclkfix_mgt;
- unsigned int armclk_mgt;
- unsigned int svammdspclk_mgt;
- unsigned int siammdspclk_mgt;
- unsigned int reserved;
- unsigned int sgaclk_mgt;
- unsigned int uartclk_mgt;
- unsigned int msp02clk_mgt;
- unsigned int i2cclk_mgt;
- unsigned int sdmmcclk_mgt;
- unsigned int slimclk_mgt;
- unsigned int per1clk_mgt;
- unsigned int per2clk_mgt;
- unsigned int per3clk_mgt;
- unsigned int per5clk_mgt;
- unsigned int per6clk_mgt;
- unsigned int per7clk_mgt;
- unsigned int lcdclk_mgt;
- unsigned int reserved1;
- unsigned int bmlclk_mgt;
- unsigned int hsitxclk_mgt;
- unsigned int hsirxclk_mgt;
- unsigned int hdmiclk_mgt;
- unsigned int apeatclk_mgt;
- unsigned int apetraceclk_mgt;
- unsigned int mcdeclk_mgt;
- unsigned int ipi2cclk_mgt;
- unsigned int dsialtclk_mgt;
- unsigned int spare2clk_mgt;
- unsigned int dmaclk_mgt;
- unsigned int b2r2clk_mgt;
- unsigned int tvclk_mgt;
- unsigned int unused[82];
- unsigned int tcr;
- unsigned int unused1[23];
- unsigned int ape_softrst;
-};
-
-extern void u8500_clock_enable(int periph, int kern, int cluster);
-
-void db8500_clocks_init(void);
-
-#endif /* __ASM_ARCH_CLOCK */
diff --git a/arch/arm/include/asm/arch-u8500/db8500_gpio.h b/arch/arm/include/asm/arch-u8500/db8500_gpio.h
deleted file mode 100644
index 7c85a89..0000000
--- a/arch/arm/include/asm/arch-u8500/db8500_gpio.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Structures and registers for GPIO access in the Nomadik SoC
- *
- * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
- * The purpose is that GPIO config found in kernel should work by simply
- * copy-paste it to U-boot.
- *
- * Ported to U-boot by:
- * Copyright (C) 2010 Joakim Axelsson <joakim.axelsson AT stericsson.com>
- * Copyright (C) 2008 STMicroelectronics
- * Author: Prafulla WADASKAR <prafulla.wadaskar@st.com>
- * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __DB8500_GPIO_H__
-#define __DB8500_GPIO_H__
-
-/* Alternate functions: function C is set in hw by setting both A and B */
-enum db8500_gpio_alt {
- DB8500_GPIO_ALT_GPIO = 0,
- DB8500_GPIO_ALT_A = 1,
- DB8500_GPIO_ALT_B = 2,
- DB8500_GPIO_ALT_C = (DB8500_GPIO_ALT_A | DB8500_GPIO_ALT_B)
-};
-
-enum db8500_gpio_pull {
- DB8500_GPIO_PULL_NONE,
- DB8500_GPIO_PULL_UP,
- DB8500_GPIO_PULL_DOWN
-};
-
-void db8500_gpio_set_pull(unsigned gpio, enum db8500_gpio_pull pull);
-void db8500_gpio_make_input(unsigned gpio);
-int db8500_gpio_get_input(unsigned gpio);
-void db8500_gpio_make_output(unsigned gpio, int val);
-void db8500_gpio_set_output(unsigned gpio, int val);
-
-#endif /* __DB8500_GPIO_H__ */
diff --git a/arch/arm/include/asm/arch-u8500/db8500_pincfg.h b/arch/arm/include/asm/arch-u8500/db8500_pincfg.h
deleted file mode 100644
index 6495701..0000000
--- a/arch/arm/include/asm/arch-u8500/db8500_pincfg.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Code ported from Nomadik GPIO driver in ST-Ericsson Linux kernel code.
- * The purpose is that GPIO config found in kernel should work by simply
- * copy-paste it to U-boot. Ported 2010 to U-boot by:
- * Author: Joakim Axelsson <joakim.axelsson AT stericsson.com>
- *
- * License terms: GNU General Public License, version 2
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- *
- *
- * Based on arch/arm/mach-pxa/include/mach/mfp.h:
- * Copyright (C) 2007 Marvell International Ltd.
- * eric miao <eric.miao@marvell.com>
- */
-
-#ifndef __DB8500_PINCFG_H
-#define __DB8500_PINCFG_H
-
-#include "db8500_gpio.h"
-
-/*
- * U-boot info:
- * SLPM (sleep mode) config will be ignored by U-boot but it is still
- * possible to configure it in order to keep cut-n-paste compability
- * with Linux kernel config.
- *
- * pin configurations are represented by 32-bit integers:
- *
- * bit 0.. 8 - Pin Number (512 Pins Maximum)
- * bit 9..10 - Alternate Function Selection
- * bit 11..12 - Pull up/down state
- * bit 13 - Sleep mode behaviour (not used in U-boot)
- * bit 14 - Direction
- * bit 15 - Value (if output)
- * bit 16..18 - SLPM pull up/down state (not used in U-boot)
- * bit 19..20 - SLPM direction (not used in U-boot)
- * bit 21..22 - SLPM Value (if output) (not used in U-boot)
- *
- * to facilitate the definition, the following macros are provided
- *
- * PIN_CFG_DEFAULT - default config (0):
- * pull up/down = disabled
- * sleep mode = input/wakeup
- * direction = input
- * value = low
- * SLPM direction = same as normal
- * SLPM pull = same as normal
- * SLPM value = same as normal
- *
- * PIN_CFG - default config with alternate function
- * PIN_CFG_PULL - default config with alternate function and pull up/down
- */
-
-/* Sleep mode */
-enum db8500_gpio_slpm {
- DB8500_GPIO_SLPM_INPUT,
- DB8500_GPIO_SLPM_WAKEUP_ENABLE = DB8500_GPIO_SLPM_INPUT,
- DB8500_GPIO_SLPM_NOCHANGE,
- DB8500_GPIO_SLPM_WAKEUP_DISABLE = DB8500_GPIO_SLPM_NOCHANGE,
-};
-
-#define PIN_NUM_MASK 0x1ff
-#define PIN_NUM(x) ((x) & PIN_NUM_MASK)
-
-#define PIN_ALT_SHIFT 9
-#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
-#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
-#define PIN_GPIO (DB8500_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
-#define PIN_ALT_A (DB8500_GPIO_ALT_A << PIN_ALT_SHIFT)
-#define PIN_ALT_B (DB8500_GPIO_ALT_B << PIN_ALT_SHIFT)
-#define PIN_ALT_C (DB8500_GPIO_ALT_C << PIN_ALT_SHIFT)
-
-#define PIN_PULL_SHIFT 11
-#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
-#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
-#define PIN_PULL_NONE (DB8500_GPIO_PULL_NONE << PIN_PULL_SHIFT)
-#define PIN_PULL_UP (DB8500_GPIO_PULL_UP << PIN_PULL_SHIFT)
-#define PIN_PULL_DOWN (DB8500_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
-
-#define PIN_SLPM_SHIFT 13
-#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
-#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
-#define PIN_SLPM_MAKE_INPUT (DB8500_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
-#define PIN_SLPM_NOCHANGE (DB8500_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
-/* These two replace the above in DB8500v2+ */
-#define PIN_SLPM_WAKEUP_ENABLE \
- (DB8500_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
-#define PIN_SLPM_WAKEUP_DISABLE \
- (DB8500_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
-
-#define PIN_DIR_SHIFT 14
-#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
-#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
-#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
-#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
-
-#define PIN_VAL_SHIFT 15
-#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
-#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
-#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
-#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
-
-#define PIN_SLPM_PULL_SHIFT 16
-#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL(x) \
- (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL_NONE \
- ((1 + DB8500_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL_UP \
- ((1 + DB8500_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
-#define PIN_SLPM_PULL_DOWN \
- ((1 + DB8500_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
-
-#define PIN_SLPM_DIR_SHIFT 19
-#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
-#define PIN_SLPM_DIR(x) \
- (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
-#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
-#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
-
-#define PIN_SLPM_VAL_SHIFT 21
-#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
-#define PIN_SLPM_VAL(x) \
- (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
-#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
-#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
-
-/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
-#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
-#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
-#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
-#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
-#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
-
-#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
-#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
-#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
-#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
-#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
-
-#define PIN_CFG_DEFAULT (0)
-
-#define PIN_CFG(num, alt) \
- (PIN_CFG_DEFAULT |\
- (PIN_NUM(num) | PIN_##alt))
-
-#define PIN_CFG_INPUT(num, alt, pull) \
- (PIN_CFG_DEFAULT |\
- (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
-
-#define PIN_CFG_OUTPUT(num, alt, val) \
- (PIN_CFG_DEFAULT |\
- (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
-
-#define PIN_CFG_PULL(num, alt, pull) \
- ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
- (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
-
-/**
- * db8500_gpio_config_pins - configure several pins at once
- * @cfgs: array of pin configurations
- * @num: number of elments in the array
- *
- * Configures several GPIO pins.
- */
-void db8500_gpio_config_pins(unsigned long *cfgs, size_t num);
-
-#endif
diff --git a/arch/arm/include/asm/arch-u8500/gpio.h b/arch/arm/include/asm/arch-u8500/gpio.h
deleted file mode 100644
index afa5942..0000000
--- a/arch/arm/include/asm/arch-u8500/gpio.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _UX500_GPIO_h
-#define _UX500_GPIO_h
-
-#include <asm/types.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/u8500.h>
-
-#define GPIO_TOTAL_PINS 268
-
-#define GPIO_PINS_PER_BLOCK 32
-#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1)
-#define GPIO_BLOCK(pin) (((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1)
-
-
-struct gpio_register {
- u32 gpio_dat; /* data register : 0x000 */
- u32 gpio_dats; /* data Set register : 0x004 */
- u32 gpio_datc; /* data Clear register : 0x008 */
- u32 gpio_pdis; /* Pull disable register : 0x00C */
- u32 gpio_dir; /* data direction register : 0x010 */
- u32 gpio_dirs; /* data dir Set register : 0x014 */
- u32 gpio_dirc; /* data dir Clear register : 0x018 */
- u32 gpio_slpm; /* Sleep mode register : 0x01C */
- u32 gpio_afsa; /* AltFun A Select reg : 0x020 */
- u32 gpio_afsb; /* AltFun B Select reg : 0x024 */
- u32 gpio_lowemi;/* low EMI Select reg : 0x028 */
- u32 reserved_1[(0x040 - 0x02C) >> 2]; /*0x028-0x3C Reserved*/
- u32 gpio_rimsc; /* rising edge intr set/clear : 0x040 */
- u32 gpio_fimsc; /* falling edge intr set/clear register : 0x044 */
- u32 gpio_mis; /* masked interrupt status register : 0x048 */
- u32 gpio_ic; /* Interrupt Clear register : 0x04C */
- u32 gpio_rwimsc;/* Rising-edge Wakeup IMSC register : 0x050 */
- u32 gpio_fwimsc;/* Falling-edge Wakeup IMSC register : 0x054 */
- u32 gpio_wks; /* Wakeup Status register : 0x058 */
-};
-
-/* Error values returned by functions */
-enum gpio_error {
- GPIO_OK = 0,
- GPIO_UNSUPPORTED_HW = -2,
- GPIO_UNSUPPORTED_FEATURE = -3,
- GPIO_INVALID_PARAMETER = -4,
- GPIO_REQUEST_NOT_APPLICABLE = -5,
- GPIO_REQUEST_PENDING = -6,
- GPIO_NOT_CONFIGURED = -7,
- GPIO_INTERNAL_ERROR = -8,
- GPIO_INTERNAL_EVENT = 1,
- GPIO_REMAINING_EVENT = 2,
- GPIO_NO_MORE_PENDING_EVENT = 3,
- GPIO_INVALID_CLIENT = -25,
- GPIO_INVALID_PIN = -26,
- GPIO_PIN_BUSY = -27,
- GPIO_PIN_NOT_ALLOCATED = -28,
- GPIO_WRONG_CLIENT = -29,
- GPIO_UNSUPPORTED_ALTFUNC = -30,
-};
-
-/*GPIO DEVICE ID */
-enum gpio_device_id {
- GPIO_DEVICE_ID_0,
- GPIO_DEVICE_ID_1,
- GPIO_DEVICE_ID_2,
- GPIO_DEVICE_ID_3,
- GPIO_DEVICE_ID_INVALID
-};
-
-/*
- * Alternate Function:
- * refered in altfun_table to pointout particular altfun to be enabled
- * when using GPIO_ALT_FUNCTION A/B/C enable/disable operation
- */
-enum gpio_alt_function {
- GPIO_ALT_UART_0_MODEM,
- GPIO_ALT_UART_0_NO_MODEM,
- GPIO_ALT_UART_1,
- GPIO_ALT_UART_2,
- GPIO_ALT_I2C_0,
- GPIO_ALT_I2C_1,
- GPIO_ALT_I2C_2,
- GPIO_ALT_I2C_3,
- GPIO_ALT_MSP_0,
- GPIO_ALT_MSP_1,
- GPIO_ALT_MSP_2,
- GPIO_ALT_MSP_3,
- GPIO_ALT_MSP_4,
- GPIO_ALT_MSP_5,
- GPIO_ALT_SSP_0,
- GPIO_ALT_SSP_1,
- GPIO_ALT_MM_CARD0,
- GPIO_ALT_SD_CARD0,
- GPIO_ALT_DMA_0,
- GPIO_ALT_DMA_1,
- GPIO_ALT_HSI0,
- GPIO_ALT_CCIR656_INPUT,
- GPIO_ALT_CCIR656_OUTPUT,
- GPIO_ALT_LCD_PANEL,
- GPIO_ALT_MDIF,
- GPIO_ALT_SDRAM,
- GPIO_ALT_HAMAC_AUDIO_DBG,
- GPIO_ALT_HAMAC_VIDEO_DBG,
- GPIO_ALT_CLOCK_RESET,
- GPIO_ALT_TSP,
- GPIO_ALT_IRDA,
- GPIO_ALT_USB_MINIMUM,
- GPIO_ALT_USB_I2C,
- GPIO_ALT_OWM,
- GPIO_ALT_PWL,
- GPIO_ALT_FSMC,
- GPIO_ALT_COMP_FLASH,
- GPIO_ALT_SRAM_NOR_FLASH,
- GPIO_ALT_FSMC_ADDLINE_0_TO_15,
- GPIO_ALT_SCROLL_KEY,
- GPIO_ALT_MSHC,
- GPIO_ALT_HPI,
- GPIO_ALT_USB_OTG,
- GPIO_ALT_SDIO,
- GPIO_ALT_HSMMC,
- GPIO_ALT_FSMC_ADD_DATA_0_TO_25,
- GPIO_ALT_HSI1,
- GPIO_ALT_NOR,
- GPIO_ALT_NAND,
- GPIO_ALT_KEYPAD,
- GPIO_ALT_VPIP,
- GPIO_ALT_CAM,
- GPIO_ALT_CCP1,
- GPIO_ALT_EMMC,
- GPIO_ALT_POP_EMMC,
- GPIO_ALT_FUNMAX /* Add new alt func before this */
-};
-
-/* Defines pin assignment(Software mode or Alternate mode) */
-enum gpio_mode {
- GPIO_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */
- GPIO_MODE_SOFTWARE, /* Pin connected to GPIO (SW controlled) */
- GPIO_ALTF_A, /* Pin connected to altfunc 1 (HW periph 1) */
- GPIO_ALTF_B, /* Pin connected to altfunc 2 (HW periph 2) */
- GPIO_ALTF_C, /* Pin connected to altfunc 3 (HW periph 3) */
- GPIO_ALTF_FIND, /* Pin connected to altfunc 3 (HW periph 3) */
- GPIO_ALTF_DISABLE /* Pin connected to altfunc 3 (HW periph 3) */
-};
-
-/* Defines GPIO pin direction */
-enum gpio_direction {
- GPIO_DIR_LEAVE_UNCHANGED, /* Parameter will be ignored */
- GPIO_DIR_INPUT, /* GPIO set as input */
- GPIO_DIR_OUTPUT /* GPIO set as output */
-};
-
-/* Interrupt trigger mode */
-enum gpio_trig {
- GPIO_TRIG_LEAVE_UNCHANGED, /* Parameter will be ignored */
- GPIO_TRIG_DISABLE, /* Trigger no IT */
- GPIO_TRIG_RISING_EDGE, /* Trigger an IT on rising edge */
- GPIO_TRIG_FALLING_EDGE, /* Trigger an IT on falling edge */
- GPIO_TRIG_BOTH_EDGES, /* Trigger an IT on rising and falling edge */
- GPIO_TRIG_HIGH_LEVEL, /* Trigger an IT on high level */
- GPIO_TRIG_LOW_LEVEL /* Trigger an IT on low level */
-};
-
-/* Configuration parameters for one GPIO pin.*/
-struct gpio_config {
- enum gpio_mode mode;
- enum gpio_direction direction;
- enum gpio_trig trig;
- char *dev_name; /* Who owns the gpio pin */
-};
-
-/* GPIO pin data*/
-enum gpio_data {
- GPIO_DATA_LOW,
- GPIO_DATA_HIGH
-};
-
-/* GPIO behaviour in sleep mode */
-enum gpio_sleep_mode {
- GPIO_SLEEP_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */
- GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT, /* GPIO is an input with pull
- up/down enabled when in sleep
- mode. */
- GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO /* GPIO pin is controlled by
- GPIO IP. So mode, direction
- and data values for GPIO pin
- in sleep mode are determined
- by configuration set to GPIO
- pin before entering to sleep
- mode. */
-};
-
-/* GPIO ability to wake the system up from sleep mode.*/
-enum gpio_wake {
- GPIO_WAKE_LEAVE_UNCHANGED, /* Parameter will be ignored */
- GPIO_WAKE_DISABLE, /* No wake of system from sleep mode. */
- GPIO_WAKE_LOW_LEVEL, /* Wake the system up on a LOW level. */
- GPIO_WAKE_HIGH_LEVEL, /* Wake the system up on a HIGH level. */
- GPIO_WAKE_RISING_EDGE, /* Wake the system up on a RISING edge. */
- GPIO_WAKE_FALLING_EDGE, /* Wake the system up on a FALLING edge. */
- GPIO_WAKE_BOTH_EDGES /* Wake the system up on both RISE and FALL. */
-};
-
-/* Configuration parameters for one GPIO pin in sleep mode.*/
-struct gpio_sleep_config {
- enum gpio_sleep_mode sleep_mode;/* GPIO behaviour in sleep mode. */
- enum gpio_wake wake; /* GPIO ability to wake up system. */
-};
-
-extern int gpio_setpinconfig(int pin_id, struct gpio_config *pin_config);
-extern int gpio_resetpinconfig(int pin_id, char *dev_name);
-extern int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name);
-extern int gpio_readpin(int pin_id, enum gpio_data *value);
-extern int gpio_altfuncenable(enum gpio_alt_function altfunc,
- char *dev_name);
-extern int gpio_altfuncdisable(enum gpio_alt_function altfunc,
- char *dev_name);
-
-struct gpio_altfun_data {
- u16 altfun;
- u16 start;
- u16 end;
- u16 cont;
- u8 type;
-};
-#endif
diff --git a/arch/arm/include/asm/arch-u8500/hardware.h b/arch/arm/include/asm/arch-u8500/hardware.h
deleted file mode 100644
index e6a899d..0000000
--- a/arch/arm/include/asm/arch-u8500/hardware.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/* Peripheral clusters */
-
-#define U8500_PER3_BASE 0x80000000
-#define U8500_PER2_BASE 0x80110000
-#define U8500_PER1_BASE 0x80120000
-#define U8500_PER4_BASE 0x80150000
-
-#define U8500_PER6_BASE 0xa03c0000
-#define U8500_PER7_BASE 0xa03d0000
-#define U8500_PER5_BASE 0xa03e0000
-
-/* GPIO */
-
-#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000)
-#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xE000 + 0x80)
-
-#define U8500_GPIO2_BASE (U8500_PER3_BASE + 0xE000)
-#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xE000 + 0x80)
-#define U8500_GPIO4_BASE (U8500_PER3_BASE + 0xE000 + 0x100)
-#define U8500_GPIO5_BASE (U8500_PER3_BASE + 0xE000 + 0x180)
-
-#define U8500_GPIO6_BASE (U8500_PER2_BASE + 0xE000)
-#define U8500_GPIO7_BASE (U8500_PER2_BASE + 0xE000 + 0x80)
-
-#define U8500_GPIO8_BASE (U8500_PER5_BASE + 0x1E000)
-
-/* Per7 */
-#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000)
-
-/* Per6 */
-#define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000)
-#define U8500_MTU1_BASE_V1 (U8500_PER6_BASE + 0x7000)
-#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
-
-/* Per5 */
-#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000)
-
-/* Per4 */
-#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
-#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
-
-/* Per3 */
-#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000)
-#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000)
-
-/* Per2 */
-#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000)
-
-/* Per1 */
-#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000)
-#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000)
-#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000)
-
-/* Last page of Boot ROM */
-#define U8500_BOOTROM_BASE 0x90000000
-#define U8500_ASIC_ID_LOC_ED_V1 (U8500_BOOTROM_BASE + 0x1FFF4)
-#define U8500_ASIC_ID_LOC_V2 (U8500_BOOTROM_BASE + 0x1DBF4)
-
-/* AB8500 specifics */
-
-/* address bank */
-#define AB8500_REGU_CTRL2 0x0004
-#define AB8500_MISC 0x0010
-
-/* registers */
-#define AB8500_REGU_VRF1VAUX3_REGU_REG 0x040A
-#define AB8500_REGU_VRF1VAUX3_SEL_REG 0x0421
-#define AB8500_REV_REG 0x1080
-
-#define AB8500_GPIO_SEL2_REG 0x1001
-#define AB8500_GPIO_DIR2_REG 0x1011
-#define AB8500_GPIO_DIR4_REG 0x1013
-#define AB8500_GPIO_SEL4_REG 0x1003
-#define AB8500_GPIO_OUT2_REG 0x1021
-#define AB8500_GPIO_OUT4_REG 0x1023
-
-#define LDO_VAUX3_ENABLE_MASK 0x3
-#define LDO_VAUX3_ENABLE_VAL 0x1
-#define LDO_VAUX3_SEL_MASK 0xf
-#define LDO_VAUX3_SEL_2V9 0xd
-#define LDO_VAUX3_V2_SEL_MASK 0x7
-#define LDO_VAUX3_V2_SEL_2V91 0x7
-
-
-#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-u8500/prcmu.h b/arch/arm/include/asm/arch-u8500/prcmu.h
deleted file mode 100644
index e7f0450..0000000
--- a/arch/arm/include/asm/arch-u8500/prcmu.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (C) 2009 ST-Ericsson SA
- *
- * Copied from the Linux version:
- * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __MACH_PRCMU_FW_V1_H
-#define __MACH_PRCMU_FW_V1_H
-
-#define AP_EXECUTE 2
-#define I2CREAD 1
-#define I2C_WR_OK 1
-#define I2C_RD_OK 2
-#define I2CWRITE 0
-
-#define PRCMU_BASE U8500_PRCMU_BASE
-#define PRCMU_BASE_TCDM U8500_PRCMU_TCDM_BASE
-#define PRCM_UARTCLK_MGT_REG (PRCMU_BASE + 0x018)
-#define PRCM_MSPCLK_MGT_REG (PRCMU_BASE + 0x01C)
-#define PRCM_I2CCLK_MGT_REG (PRCMU_BASE + 0x020)
-#define PRCM_SDMMCCLK_MGT_REG (PRCMU_BASE + 0x024)
-#define PRCM_PER1CLK_MGT_REG (PRCMU_BASE + 0x02C)
-#define PRCM_PER2CLK_MGT_REG (PRCMU_BASE + 0x030)
-#define PRCM_PER3CLK_MGT_REG (PRCMU_BASE + 0x034)
-#define PRCM_PER5CLK_MGT_REG (PRCMU_BASE + 0x038)
-#define PRCM_PER6CLK_MGT_REG (PRCMU_BASE + 0x03C)
-#define PRCM_PER7CLK_MGT_REG (PRCMU_BASE + 0x040)
-#define PRCM_MBOX_CPU_VAL (PRCMU_BASE + 0x0FC)
-#define PRCM_MBOX_CPU_SET (PRCMU_BASE + 0x100)
-
-#define PRCM_ARM_IT1_CLEAR (PRCMU_BASE + 0x48C)
-#define PRCM_ARM_IT1_VAL (PRCMU_BASE + 0x494)
-#define PRCM_TCR (PRCMU_BASE + 0x1C8)
-#define PRCM_REQ_MB5 (PRCMU_BASE_TCDM + 0xE44)
-#define PRCM_ACK_MB5 (PRCMU_BASE_TCDM + 0xDF4)
-#define PRCM_XP70_CUR_PWR_STATE (PRCMU_BASE_TCDM + 0xFFC)
-/* Mailbox 5 Requests */
-#define PRCM_REQ_MB5_I2COPTYPE_REG (PRCM_REQ_MB5 + 0x0)
-#define PRCM_REQ_MB5_BIT_FIELDS (PRCM_REQ_MB5 + 0x1)
-#define PRCM_REQ_MB5_I2CSLAVE (PRCM_REQ_MB5 + 0x2)
-#define PRCM_REQ_MB5_I2CVAL (PRCM_REQ_MB5 + 0x3)
-
-/* Mailbox 5 ACKs */
-#define PRCM_ACK_MB5_STATUS (PRCM_ACK_MB5 + 0x1)
-#define PRCM_ACK_MB5_SLAVE (PRCM_ACK_MB5 + 0x2)
-#define PRCM_ACK_MB5_VAL (PRCM_ACK_MB5 + 0x3)
-
-#define LOW_POWER_WAKEUP 1
-#define EXE_WAKEUP 0
-
-#define REQ_MB5 5
-
-#define ab8500_read prcmu_i2c_read
-#define ab8500_write prcmu_i2c_write
-
-int prcmu_i2c_read(u8 reg, u16 slave);
-int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
-
-void u8500_prcmu_enable(u32 *reg);
-void db8500_prcmu_init(void);
-
-#endif /* __MACH_PRCMU_FW_V1_H */
diff --git a/arch/arm/include/asm/arch-u8500/sys_proto.h b/arch/arm/include/asm/arch-u8500/sys_proto.h
deleted file mode 100644
index 03a3cd3..0000000
--- a/arch/arm/include/asm/arch-u8500/sys_proto.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-void gpio_init(void);
-int u8500_mmc_power_init(void);
-
-#endif /* _SYS_PROTO_H_ */
diff --git a/arch/arm/include/asm/arch-u8500/u8500.h b/arch/arm/include/asm/arch-u8500/u8500.h
deleted file mode 100644
index 16ad081..0000000
--- a/arch/arm/include/asm/arch-u8500/u8500.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2009
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __U8500_H
-#define __U8500_H
-
-/*
- * base register values for U8500
- */
-#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock
- Management Unit */
-#define CFG_SDRAMC_BASE 0x903CF000 /* SDRAMC cnf registers */
-#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */
-
-/*
- * U8500 GPIO register base for 9 banks
- */
-#define U8500_GPIO_0_BASE 0x8012E000
-#define U8500_GPIO_1_BASE 0x8012E080
-#define U8500_GPIO_2_BASE 0x8000E000
-#define U8500_GPIO_3_BASE 0x8000E080
-#define U8500_GPIO_4_BASE 0x8000E100
-#define U8500_GPIO_5_BASE 0x8000E180
-#define U8500_GPIO_6_BASE 0x8011E000
-#define U8500_GPIO_7_BASE 0x8011E080
-#define U8500_GPIO_8_BASE 0xA03FE000
-
-#endif /* __U8500_H */
diff --git a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
index 6730cde..9022c46 100644
--- a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
@@ -11,18 +11,6 @@
#ifndef __ASM_ARCH_VF610_DDRMC_H
#define __ASM_ARCH_VF610_DDRMC_H
-struct ddrmc_lvl_info {
- u16 wrlvl_reg_en;
- u16 wrlvl_dl_0;
- u16 wrlvl_dl_1;
- u16 rdlvl_gt_reg_en;
- u16 rdlvl_gt_dl_0;
- u16 rdlvl_gt_dl_1;
- u16 rdlvl_reg_en;
- u16 rdlvl_dl_0;
- u16 rdlvl_dl_1;
-};
-
struct ddr3_jedec_timings {
u8 tinit;
u32 trst_pwron;
@@ -32,6 +20,7 @@ struct ddr3_jedec_timings {
u8 trc;
u8 trrd;
u8 tccd;
+ u8 tbst_int_interval;
u8 tfaw;
u8 trp;
u8 twtr;
@@ -43,30 +32,51 @@ struct ddr3_jedec_timings {
u8 tckesr;
u8 tcke;
u8 trcd_int;
+ u8 tras_lockout;
u8 tdal;
+ u8 bstlen;
u16 tdll;
u8 trp_ab;
u16 tref;
u8 trfc;
+ u16 tref_int;
u8 tpdex;
u8 txpdll;
u8 txsnr;
u16 txsr;
u8 cksrx;
u8 cksre;
+ u8 freq_chg_en;
u16 zqcl;
u16 zqinit;
u8 zqcs;
u8 ref_per_zq;
+ u8 zqcs_rotate;
u8 aprebit;
+ u8 cmd_age_cnt;
+ u8 age_cnt;
+ u8 q_fullness;
+ u8 odt_rd_mapcs0;
+ u8 odt_wr_mapcs0;
u8 wlmrd;
u8 wldqsen;
};
-void ddrmc_setup_iomux(void);
+struct ddrmc_cr_setting {
+ u32 setting;
+ int cr_rnum; /* CR register ; -1 for last entry */
+};
+
+struct ddrmc_phy_setting {
+ u32 setting;
+ int phy_rnum; /* PHY register ; -1 for last entry */
+};
+
+void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count);
void ddrmc_phy_init(void);
void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
- struct ddrmc_lvl_info *lvl,
- int col_diff, int row_diff);
+ struct ddrmc_cr_setting *board_cr_settings,
+ struct ddrmc_phy_setting *board_phy_settings,
+ int col_diff, int row_diff);
#endif
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 4366985..9758323 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -148,7 +148,7 @@
#define DDRMC_CR18_TCKE(v) ((v) & 0x7)
#define DDRMC_CR20_AP_EN (1 << 24)
#define DDRMC_CR21_TRCD_INT(v) (((v) & 0xff) << 16)
-#define DDRMC_CR21_TRAS_LOCKOUT (1 << 8)
+#define DDRMC_CR21_TRAS_LOCKOUT(v) ((v) << 8)
#define DDRMC_CR21_CCMAP_EN 1
#define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16)
#define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24)
@@ -200,8 +200,8 @@
#define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24)
#define DDRMC_CR82_INT_MASK 0x10000000
-#define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24)
-#define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16)
+#define DDRMC_CR87_ODT_WR_MAPCS0(v) ((v) << 24)
+#define DDRMC_CR87_ODT_RD_MAPCS0(v) ((v) << 16)
#define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16)
#define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
#define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16)
diff --git a/arch/arm/include/asm/imx-common/boot_mode.h b/arch/arm/include/asm/imx-common/boot_mode.h
index de0205c..a8239f2 100644
--- a/arch/arm/include/asm/imx-common/boot_mode.h
+++ b/arch/arm/include/asm/imx-common/boot_mode.h
@@ -9,6 +9,27 @@
#define MAKE_CFGVAL(cfg1, cfg2, cfg3, cfg4) \
((cfg4) << 24) | ((cfg3) << 16) | ((cfg2) << 8) | (cfg1)
+enum boot_device {
+ WEIM_NOR_BOOT,
+ ONE_NAND_BOOT,
+ PATA_BOOT,
+ SATA_BOOT,
+ I2C_BOOT,
+ SPI_NOR_BOOT,
+ SD1_BOOT,
+ SD2_BOOT,
+ SD3_BOOT,
+ SD4_BOOT,
+ MMC1_BOOT,
+ MMC2_BOOT,
+ MMC3_BOOT,
+ MMC4_BOOT,
+ NAND_BOOT,
+ QSPI_BOOT,
+ UNKNOWN_BOOT,
+ BOOT_DEV_NUM = UNKNOWN_BOOT,
+};
+
struct boot_mode {
const char *name;
unsigned cfg_val;
diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h
index 6954ee9..5673fb4 100644
--- a/arch/arm/include/asm/imx-common/sys_proto.h
+++ b/arch/arm/include/asm/imx-common/sys_proto.h
@@ -17,9 +17,12 @@
/* returns MXC_CPU_ value */
#define cpu_type(rev) (((rev) >> 12) & 0xff)
+#define soc_type(rev) (((rev) >> 12) & 0xf0)
/* both macros return/take MXC_CPU_ constants */
#define get_cpu_type() (cpu_type(get_cpu_rev()))
+#define get_soc_type() (soc_type(get_cpu_rev()))
#define is_cpu_type(cpu) (get_cpu_type() == cpu)
+#define is_soc_type(soc) (get_soc_type() == soc)
#define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
@@ -32,6 +35,10 @@ u32 imx_ddr_size(void);
void sdelay(unsigned long);
void set_chipselect_size(int const);
+void init_aips(void);
+void init_src(void);
+void imx_set_wdog_powerdown(bool enable);
+
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
diff --git a/arch/arm/include/asm/imx-common/syscounter.h b/arch/arm/include/asm/imx-common/syscounter.h
new file mode 100644
index 0000000..bdbe26c
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/syscounter.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_SYSTEM_COUNTER_H
+#define _ASM_ARCH_SYSTEM_COUNTER_H
+
+/* System Counter */
+struct sctr_regs {
+ u32 cntcr;
+ u32 cntsr;
+ u32 cntcv1;
+ u32 cntcv2;
+ u32 resv1[4];
+ u32 cntfid0;
+ u32 cntfid1;
+ u32 cntfid2;
+ u32 resv2[1001];
+ u32 counterid[1];
+};
+
+#define SC_CNTCR_ENABLE (1 << 0)
+#define SC_CNTCR_HDBG (1 << 1)
+#define SC_CNTCR_FREQ0 (1 << 8)
+#define SC_CNTCR_FREQ1 (1 << 9)
+
+#endif
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index e72184b..d51be0b 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -150,7 +150,6 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_INTELMOTE2 775
#define MACH_TYPE_TRIZEPS4 776
#define MACH_TYPE_PNX4008 782
-#define MACH_TYPE_CPUAT91 787
#define MACH_TYPE_IQ81340SC 799
#define MACH_TYPE_IQ81340MC 801
#define MACH_TYPE_MICRO9 811
@@ -197,7 +196,6 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_SMDK2412 1009
#define MACH_TYPE_SMDK2413 1022
#define MACH_TYPE_AML_M5900 1024
-#define MACH_TYPE_BALLOON3 1029
#define MACH_TYPE_ECBAT91 1072
#define MACH_TYPE_ONEARM 1075
#define MACH_TYPE_SMDK2443 1084
@@ -404,7 +402,6 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_IGEP0020 2344
#define MACH_TYPE_NUC932EVB 2356
#define MACH_TYPE_OPENRD_CLIENT 2361
-#define MACH_TYPE_U8500 2368
#define MACH_TYPE_MX51_EFIKASB 2370
#define MACH_TYPE_MARVELL_JASPER 2382
#define MACH_TYPE_FLINT 2383
@@ -976,7 +973,6 @@ extern unsigned int __machine_arch_type;
#define MACH_TYPE_RHINO 3360
#define MACH_TYPE_ARMLEX4210 3361
#define MACH_TYPE_SWARCOEXTMODEM 3362
-#define MACH_TYPE_SNOWBALL 3363
#define MACH_TYPE_PCM049 3364
#define MACH_TYPE_VIGOR 3365
#define MACH_TYPE_OSLO_AMUNDSEN 3366
@@ -2768,18 +2764,6 @@ extern unsigned int __machine_arch_type;
# define machine_is_pnx4008() (0)
#endif
-#ifdef CONFIG_MACH_CPUAT91
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CPUAT91
-# endif
-# define machine_is_cpuat91() (machine_arch_type == MACH_TYPE_CPUAT91)
-#else
-# define machine_is_cpuat91() (0)
-#endif
-
#ifdef CONFIG_MACH_IQ81340SC
# ifdef machine_arch_type
# undef machine_arch_type
@@ -3332,18 +3316,6 @@ extern unsigned int __machine_arch_type;
# define machine_is_aml_m5900() (0)
#endif
-#ifdef CONFIG_MACH_BALLOON3
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_BALLOON3
-# endif
-# define machine_is_balloon3() (machine_arch_type == MACH_TYPE_BALLOON3)
-#else
-# define machine_is_balloon3() (0)
-#endif
-
#ifdef CONFIG_MACH_ECBAT91
# ifdef machine_arch_type
# undef machine_arch_type
@@ -5048,30 +5020,6 @@ extern unsigned int __machine_arch_type;
# define machine_is_omap_zoom2() (0)
#endif
-#ifdef CONFIG_MACH_CPUAT9260
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_CPUAT9260
-# endif
-# define machine_is_cpuat9260() (machine_arch_type == MACH_TYPE_CPUAT9260)
-#else
-# define machine_is_cpuat9260() (0)
-#endif
-
-#ifdef CONFIG_MACH_EUKREA_CPUIMX27
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_EUKREA_CPUIMX27
-# endif
-# define machine_is_eukrea_cpuimx27() (machine_arch_type == MACH_TYPE_EUKREA_CPUIMX27)
-#else
-# define machine_is_eukrea_cpuimx27() (0)
-#endif
-
#ifdef CONFIG_MACH_ACS5K
# ifdef machine_arch_type
# undef machine_arch_type
@@ -5804,18 +5752,6 @@ extern unsigned int __machine_arch_type;
# define machine_is_openrd_client() (0)
#endif
-#ifdef CONFIG_MACH_U8500
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_U8500
-# endif
-# define machine_is_u8500() (machine_arch_type == MACH_TYPE_U8500)
-#else
-# define machine_is_u8500() (0)
-#endif
-
#ifdef CONFIG_MACH_MX51_EFIKASB
# ifdef machine_arch_type
# undef machine_arch_type
@@ -12668,18 +12604,6 @@ extern unsigned int __machine_arch_type;
# define machine_is_swarcoextmodem() (0)
#endif
-#ifdef CONFIG_MACH_SNOWBALL
-# ifdef machine_arch_type
-# undef machine_arch_type
-# define machine_arch_type __machine_arch_type
-# else
-# define machine_arch_type MACH_TYPE_SNOWBALL
-# endif
-# define machine_is_snowball() (machine_arch_type == MACH_TYPE_SNOWBALL)
-#else
-# define machine_is_snowball() (0)
-#endif
-
#ifdef CONFIG_MACH_PCM049
# ifdef machine_arch_type
# undef machine_arch_type
diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h
index 43cc494..ca3abd7 100644
--- a/arch/arm/include/asm/u-boot.h
+++ b/arch/arm/include/asm/u-boot.h
@@ -20,27 +20,8 @@
#ifndef _U_BOOT_H_
#define _U_BOOT_H_ 1
-#ifdef CONFIG_SYS_GENERIC_BOARD
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
-#else
-
-#ifndef __ASSEMBLY__
-typedef struct bd_info {
- ulong bi_arch_number; /* unique id for this board */
- ulong bi_boot_params; /* where this board expects params */
- unsigned long bi_arm_freq; /* arm frequency */
- unsigned long bi_dsp_freq; /* dsp core frequency */
- unsigned long bi_ddr_freq; /* ddr frequency */
- struct /* RAM configuration */
- {
- ulong start;
- ulong size;
- } bi_dram[CONFIG_NR_DRAM_BANKS];
-} bd_t;
-#endif
-
-#endif /* !CONFIG_SYS_GENERIC_BOARD */
/* For image.h:image_check_target_arch() */
#ifndef CONFIG_ARM64
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index f717103..2bdfaba 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -22,9 +22,6 @@ obj-y += relocate_64.o
else
obj-y += relocate.o
endif
-ifndef CONFIG_SYS_GENERIC_BOARD
-obj-y += board.o
-endif
obj-$(CONFIG_CPU_V7M) += cmd_boot.o
obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
deleted file mode 100644
index 37ea6e9..0000000
--- a/arch/arm/lib/board.c
+++ /dev/null
@@ -1,687 +0,0 @@
-/*
- * (C) Copyright 2002-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * To match the U-Boot user interface on ARM platforms to the U-Boot
- * standard (as on PPC platforms), some messages with debug character
- * are removed from the default U-Boot build.
- *
- * Define DEBUG here if you want additional info as shown below
- * printed upon startup:
- *
- * U-Boot code: 00F00000 -> 00F3C774 BSS: -> 00FC3274
- * IRQ Stack: 00ebff7c
- * FIQ Stack: 00ebef7c
- */
-
-#include <common.h>
-#include <command.h>
-#include <environment.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <version.h>
-#include <net.h>
-#include <serial.h>
-#include <nand.h>
-#include <onenand_uboot.h>
-#include <mmc.h>
-#include <scsi.h>
-#include <status_led.h>
-#include <libfdt.h>
-#include <fdtdec.h>
-#include <post.h>
-#include <logbuff.h>
-#include <asm/sections.h>
-
-#ifdef CONFIG_BITBANGMII
-#include <miiphy.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-ulong monitor_flash_len;
-
-#ifdef CONFIG_HAS_DATAFLASH
-extern int AT91F_DataflashInit(void);
-extern void dataflash_print_info(void);
-#endif
-
-#if defined(CONFIG_HARD_I2C) || \
- defined(CONFIG_SYS_I2C)
-#include <i2c.h>
-#endif
-
-/************************************************************************
- * Coloured LED functionality
- ************************************************************************
- * May be supplied by boards if desired
- */
-__weak void coloured_LED_init(void) {}
-__weak void red_led_on(void) {}
-__weak void red_led_off(void) {}
-__weak void green_led_on(void) {}
-__weak void green_led_off(void) {}
-__weak void yellow_led_on(void) {}
-__weak void yellow_led_off(void) {}
-__weak void blue_led_on(void) {}
-__weak void blue_led_off(void) {}
-
-/*
- ************************************************************************
- * Init Utilities *
- ************************************************************************
- * Some of this code should be moved into the core functions,
- * or dropped completely,
- * but let's get it working (again) first...
- */
-
-#if defined(CONFIG_ARM_DCC) && !defined(CONFIG_BAUDRATE)
-#define CONFIG_BAUDRATE 115200
-#endif
-
-static int init_baudrate(void)
-{
- gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
- return 0;
-}
-
-static int display_banner(void)
-{
- printf("\n\n%s\n\n", version_string);
- debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
- (ulong)&_start,
- (ulong)&__bss_start, (ulong)&__bss_end);
-#ifdef CONFIG_MODEM_SUPPORT
- debug("Modem Support enabled\n");
-#endif
-#ifdef CONFIG_USE_IRQ
- debug("IRQ Stack: %08lx\n", IRQ_STACK_START);
- debug("FIQ Stack: %08lx\n", FIQ_STACK_START);
-#endif
-
- return (0);
-}
-
-/*
- * WARNING: this code looks "cleaner" than the PowerPC version, but
- * has the disadvantage that you either get nothing, or everything.
- * On PowerPC, you might see "DRAM: " before the system hangs - which
- * gives a simple yet clear indication which part of the
- * initialization if failing.
- */
-static int display_dram_config(void)
-{
- int i;
-
-#ifdef DEBUG
- puts("RAM Configuration:\n");
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
- printf("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
- print_size(gd->bd->bi_dram[i].size, "\n");
- }
-#else
- ulong size = 0;
-
- for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
- size += gd->bd->bi_dram[i].size;
-
- puts("DRAM: ");
- print_size(size, "\n");
-#endif
-
- return (0);
-}
-
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
-static int init_func_i2c(void)
-{
- puts("I2C: ");
-#ifdef CONFIG_SYS_I2C
- i2c_init_all();
-#else
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
- puts("ready\n");
- return (0);
-}
-#endif
-
-#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI)
-#include <pci.h>
-static int arm_pci_init(void)
-{
- pci_init();
- return 0;
-}
-#endif /* CONFIG_CMD_PCI || CONFIG_PCI */
-
-/*
- * Breathe some life into the board...
- *
- * Initialize a serial port as console, and carry out some hardware
- * tests.
- *
- * The first part of initialization is running from Flash memory;
- * its main purpose is to initialize the RAM so that we
- * can relocate the monitor code to RAM.
- */
-
-/*
- * All attempts to come up with a "common" initialization sequence
- * that works for all boards and architectures failed: some of the
- * requirements are just _too_ different. To get rid of the resulting
- * mess of board dependent #ifdef'ed code we now make the whole
- * initialization sequence configurable to the user.
- *
- * The requirements for any new initalization function is simple: it
- * receives a pointer to the "global data" structure as it's only
- * argument, and returns an integer return code, where 0 means
- * "continue" and != 0 means "fatal error, hang the system".
- */
-typedef int (init_fnc_t) (void);
-
-__weak void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
-}
-
-__weak int arch_cpu_init(void)
-{
- return 0;
-}
-
-__weak int power_init_board(void)
-{
- return 0;
-}
-
- /* Record the board_init_f() bootstage (after arch_cpu_init()) */
-static int mark_bootstage(void)
-{
- bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
-
- return 0;
-}
-
-init_fnc_t *init_sequence[] = {
- arch_cpu_init, /* basic arch cpu dependent setup */
- mark_bootstage,
-#ifdef CONFIG_OF_CONTROL
- fdtdec_check_fdt,
-#endif
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
- board_early_init_f,
-#endif
- timer_init, /* initialize timer */
-#ifdef CONFIG_BOARD_POSTCLK_INIT
- board_postclk_init,
-#endif
-#ifdef CONFIG_FSL_ESDHC
- get_clocks,
-#endif
- env_init, /* initialize environment */
- init_baudrate, /* initialze baudrate settings */
- serial_init, /* serial communications setup */
- console_init_f, /* stage 1 init of console */
- display_banner, /* say that we are here */
- print_cpuinfo, /* display cpu info (and speed) */
-#if defined(CONFIG_DISPLAY_BOARDINFO)
- checkboard, /* display board info */
-#endif
-#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C)
- init_func_i2c,
-#endif
- dram_init, /* configure available RAM banks */
- NULL,
-};
-
-void board_init_f(ulong bootflag)
-{
- bd_t *bd;
- init_fnc_t **init_fnc_ptr;
- gd_t *id;
- ulong addr, addr_sp;
-#ifdef CONFIG_PRAM
- ulong reg;
-#endif
- void *new_fdt = NULL;
- size_t fdt_size = 0;
-
- memset((void *)gd, 0, sizeof(gd_t));
-
- gd->mon_len = (ulong)&__bss_end - (ulong)_start;
-#ifdef CONFIG_OF_EMBED
- /* Get a pointer to the FDT */
- gd->fdt_blob = __dtb_dt_begin;
-#elif defined CONFIG_OF_SEPARATE
- /* FDT is at end of image */
- gd->fdt_blob = &_end;
-#endif
- /* Allow the early environment to override the fdt address */
- gd->fdt_blob = (void *)getenv_ulong("fdtcontroladdr", 16,
- (uintptr_t)gd->fdt_blob);
-
- for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
- if ((*init_fnc_ptr)() != 0) {
- hang ();
- }
- }
-
-#ifdef CONFIG_OF_CONTROL
- /* For now, put this check after the console is ready */
- if (fdtdec_prepare_fdt()) {
- panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
- "doc/README.fdt-control");
- }
-#endif
-
- debug("monitor len: %08lX\n", gd->mon_len);
- /*
- * Ram is setup, size stored in gd !!
- */
- debug("ramsize: %08lX\n", gd->ram_size);
-#if defined(CONFIG_SYS_MEM_TOP_HIDE)
- /*
- * Subtract specified amount of memory to hide so that it won't
- * get "touched" at all by U-Boot. By fixing up gd->ram_size
- * the Linux kernel should now get passed the now "corrected"
- * memory size and won't touch it either. This should work
- * for arch/ppc and arch/powerpc. Only Linux board ports in
- * arch/powerpc with bootwrapper support, that recalculate the
- * memory size from the SDRAM controller setup will have to
- * get fixed.
- */
- gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
-#endif
-
- addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize();
-
-#ifdef CONFIG_LOGBUFFER
-#ifndef CONFIG_ALT_LB_ADDR
- /* reserve kernel log buffer */
- addr -= (LOGBUFF_RESERVE);
- debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN,
- addr);
-#endif
-#endif
-
-#ifdef CONFIG_PRAM
- /*
- * reserve protected RAM
- */
- reg = getenv_ulong("pram", 10, CONFIG_PRAM);
- addr -= (reg << 10); /* size is in kB */
- debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
-#endif /* CONFIG_PRAM */
-
-#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
- /* reserve TLB table */
- gd->arch.tlb_size = PGTABLE_SIZE;
- addr -= gd->arch.tlb_size;
-
- /* round down to next 64 kB limit */
- addr &= ~(0x10000 - 1);
-
- gd->arch.tlb_addr = addr;
- debug("TLB table from %08lx to %08lx\n", addr, addr + gd->arch.tlb_size);
-#endif
-
- /* round down to next 4 kB limit */
- addr &= ~(4096 - 1);
- debug("Top of RAM usable for U-Boot at: %08lx\n", addr);
-
-#ifdef CONFIG_LCD
-#ifdef CONFIG_FB_ADDR
- gd->fb_base = CONFIG_FB_ADDR;
-#else
- /* reserve memory for LCD display (always full pages) */
- addr = lcd_setmem(addr);
- gd->fb_base = addr;
-#endif /* CONFIG_FB_ADDR */
-#endif /* CONFIG_LCD */
-
- /*
- * reserve memory for U-Boot code, data & bss
- * round down to next 4 kB limit
- */
- addr -= gd->mon_len;
- addr &= ~(4096 - 1);
-
- debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr);
-
-#ifndef CONFIG_SPL_BUILD
- /*
- * reserve memory for malloc() arena
- */
- addr_sp = addr - TOTAL_MALLOC_LEN;
- debug("Reserving %dk for malloc() at: %08lx\n",
- TOTAL_MALLOC_LEN >> 10, addr_sp);
- /*
- * (permanently) allocate a Board Info struct
- * and a permanent copy of the "global" data
- */
- addr_sp -= sizeof (bd_t);
- bd = (bd_t *) addr_sp;
- gd->bd = bd;
- debug("Reserving %zu Bytes for Board Info at: %08lx\n",
- sizeof (bd_t), addr_sp);
-
-#ifdef CONFIG_MACH_TYPE
- gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
-#endif
-
- addr_sp -= sizeof (gd_t);
- id = (gd_t *) addr_sp;
- debug("Reserving %zu Bytes for Global Data at: %08lx\n",
- sizeof (gd_t), addr_sp);
-
-#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)
- /*
- * If the device tree is sitting immediate above our image then we
- * must relocate it. If it is embedded in the data section, then it
- * will be relocated with other data.
- */
- if (gd->fdt_blob) {
- fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
-
- addr_sp -= fdt_size;
- new_fdt = (void *)addr_sp;
- debug("Reserving %zu Bytes for FDT at: %08lx\n",
- fdt_size, addr_sp);
- }
-#endif
-
-#ifndef CONFIG_ARM64
- /* setup stackpointer for exeptions */
- gd->irq_sp = addr_sp;
-#ifdef CONFIG_USE_IRQ
- addr_sp -= (CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ);
- debug("Reserving %zu Bytes for IRQ stack at: %08lx\n",
- CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp);
-#endif
- /* leave 3 words for abort-stack */
- addr_sp -= 12;
-
- /* 8-byte alignment for ABI compliance */
- addr_sp &= ~0x07;
-#else /* CONFIG_ARM64 */
- /* 16-byte alignment for ABI compliance */
- addr_sp &= ~0x0f;
-#endif /* CONFIG_ARM64 */
-#else
- addr_sp += 128; /* leave 32 words for abort-stack */
- gd->irq_sp = addr_sp;
-#endif
-
- debug("New Stack Pointer is: %08lx\n", addr_sp);
-
-#ifdef CONFIG_POST
- post_bootmode_init();
- post_run(NULL, POST_ROM | post_bootmode_get(0));
-#endif
-
- /* Ram ist board specific, so move it to board code ... */
- dram_init_banksize();
- display_dram_config(); /* and display it */
-
- gd->relocaddr = addr;
- gd->start_addr_sp = addr_sp;
- gd->reloc_off = addr - (ulong)&_start;
- debug("relocation Offset is: %08lx\n", gd->reloc_off);
- if (new_fdt) {
- memcpy(new_fdt, gd->fdt_blob, fdt_size);
- gd->fdt_blob = new_fdt;
- }
- memcpy(id, (void *)gd, sizeof(gd_t));
-}
-
-#if !defined(CONFIG_SYS_NO_FLASH)
-static char *failed = "*** failed ***\n";
-#endif
-
-/*
- * Tell if it's OK to load the environment early in boot.
- *
- * If CONFIG_OF_CONFIG is defined, we'll check with the FDT to see
- * if this is OK (defaulting to saying it's not OK).
- *
- * NOTE: Loading the environment early can be a bad idea if security is
- * important, since no verification is done on the environment.
- *
- * @return 0 if environment should not be loaded, !=0 if it is ok to load
- */
-static int should_load_env(void)
-{
-#ifdef CONFIG_OF_CONTROL
- return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 1);
-#elif defined CONFIG_DELAY_ENVIRONMENT
- return 0;
-#else
- return 1;
-#endif
-}
-
-#if defined(CONFIG_DISPLAY_BOARDINFO_LATE) && defined(CONFIG_OF_CONTROL)
-static void display_fdt_model(const void *blob)
-{
- const char *model;
-
- model = (char *)fdt_getprop(blob, 0, "model", NULL);
- printf("Model: %s\n", model ? model : "<unknown>");
-}
-#endif
-
-/************************************************************************
- *
- * This is the next part if the initialization sequence: we are now
- * running from RAM and have a "normal" C environment, i. e. global
- * data can be written, BSS has been cleared, the stack size in not
- * that critical any more, etc.
- *
- ************************************************************************
- */
-
-void board_init_r(gd_t *id, ulong dest_addr)
-{
- ulong malloc_start;
-#if !defined(CONFIG_SYS_NO_FLASH)
- ulong flash_size;
-#endif
-
- gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
- bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_R, "board_init_r");
-
- monitor_flash_len = (ulong)&__rel_dyn_end - (ulong)_start;
-
- /* Enable caches */
- enable_caches();
-
- debug("monitor flash len: %08lX\n", monitor_flash_len);
- board_init(); /* Setup chipselects */
- /*
- * TODO: printing of the clock inforamtion of the board is now
- * implemented as part of bdinfo command. Currently only support for
- * davinci SOC's is added. Remove this check once all the board
- * implement this.
- */
-#ifdef CONFIG_CLOCKS
- set_cpu_clk_info(); /* Setup clock information */
-#endif
- serial_initialize();
-
- debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
-
-#ifdef CONFIG_LOGBUFFER
- logbuff_init_ptrs();
-#endif
-#ifdef CONFIG_POST
- post_output_backlog();
-#endif
-
- /* The Malloc area is immediately below the monitor copy in DRAM */
- malloc_start = dest_addr - TOTAL_MALLOC_LEN;
- mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
-
-#ifdef CONFIG_ARCH_EARLY_INIT_R
- arch_early_init_r();
-#endif
- power_init_board();
-
-#if !defined(CONFIG_SYS_NO_FLASH)
- puts("Flash: ");
-
- flash_size = flash_init();
- if (flash_size > 0) {
-# ifdef CONFIG_SYS_FLASH_CHECKSUM
- print_size(flash_size, "");
- /*
- * Compute and print flash CRC if flashchecksum is set to 'y'
- *
- * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
- */
- if (getenv_yesno("flashchecksum") == 1) {
- printf(" CRC: %08X", crc32(0,
- (const unsigned char *) CONFIG_SYS_FLASH_BASE,
- flash_size));
- }
- putc('\n');
-# else /* !CONFIG_SYS_FLASH_CHECKSUM */
- print_size(flash_size, "\n");
-# endif /* CONFIG_SYS_FLASH_CHECKSUM */
- } else {
- puts(failed);
- hang();
- }
-#endif
-
-#if defined(CONFIG_CMD_NAND)
- puts("NAND: ");
- nand_init(); /* go init the NAND */
-#endif
-
-#if defined(CONFIG_CMD_ONENAND)
- onenand_init();
-#endif
-
-#ifdef CONFIG_GENERIC_MMC
- puts("MMC: ");
- mmc_initialize(gd->bd);
-#endif
-
-#ifdef CONFIG_CMD_SCSI
- puts("SCSI: ");
- scsi_init();
-#endif
-
-#ifdef CONFIG_HAS_DATAFLASH
- AT91F_DataflashInit();
- dataflash_print_info();
-#endif
-
- /* initialize environment */
- if (should_load_env())
- env_relocate();
- else
- set_default_env(NULL);
-
-#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
- arm_pci_init();
-#endif
-
- stdio_init(); /* get the devices list going. */
-
- jumptable_init();
-
-#if defined(CONFIG_API)
- /* Initialize API */
- api_init();
-#endif
-
- console_init_r(); /* fully init console as a device */
-
-#ifdef CONFIG_DISPLAY_BOARDINFO_LATE
-# ifdef CONFIG_OF_CONTROL
- /* Put this here so it appears on the LCD, now it is ready */
- display_fdt_model(gd->fdt_blob);
-# else
- checkboard();
-# endif
-#endif
-
-#if defined(CONFIG_ARCH_MISC_INIT)
- /* miscellaneous arch dependent initialisations */
- arch_misc_init();
-#endif
-#if defined(CONFIG_MISC_INIT_R)
- /* miscellaneous platform dependent initialisations */
- misc_init_r();
-#endif
-
- /* set up exceptions */
- interrupt_init();
- /* enable exceptions */
- enable_interrupts();
-
- /* Initialize from environment */
- load_addr = getenv_ulong("loadaddr", 16, load_addr);
-
-#ifdef CONFIG_BOARD_LATE_INIT
- board_late_init();
-#endif
-
-#ifdef CONFIG_BITBANGMII
- bb_miiphy_init();
-#endif
-#if defined(CONFIG_CMD_NET)
- puts("Net: ");
- eth_initialize();
-#if defined(CONFIG_RESET_PHY_R)
- debug("Reset Ethernet PHY\n");
- reset_phy();
-#endif
-#endif
-
-#ifdef CONFIG_POST
- post_run(NULL, POST_RAM | post_bootmode_get(0));
-#endif
-
-#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
- /*
- * Export available size of memory for Linux,
- * taking into account the protected RAM at top of memory
- */
- {
- ulong pram = 0;
- uchar memsz[32];
-
-#ifdef CONFIG_PRAM
- pram = getenv_ulong("pram", 10, CONFIG_PRAM);
-#endif
-#ifdef CONFIG_LOGBUFFER
-#ifndef CONFIG_ALT_LB_ADDR
- /* Also take the logbuffer into account (pram is in kB) */
- pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
-#endif
-#endif
- sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram);
- setenv("mem", (char *)memsz);
- }
-#endif
-
- /* main_loop() can return to retry autoboot, if so just run it again. */
- for (;;) {
- main_loop();
- }
-
- /* NOTREACHED - no way out of command loop except booting */
-}
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index f9f148d..fdaf328 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -8,14 +8,6 @@ config TARGET_AT91RM9200EK
bool "Atmel AT91RM9200 evaluation kit"
select CPU_ARM920T
-config TARGET_EB_CPUX9K2
- bool "Support eb_cpux9k2"
- select CPU_ARM920T
-
-config TARGET_CPUAT91
- bool "Support cpuat91"
- select CPU_ARM920T
-
config TARGET_AT91SAM9260EK
bool "Atmel at91sam9260 reference board"
select CPU_ARM926EJS
@@ -51,10 +43,6 @@ config TARGET_PM9263
bool "Ronetix pm9263 board"
select CPU_ARM926EJS
-config TARGET_STAMP9G20
- bool "Support stamp9g20"
- select CPU_ARM926EJS
-
config TARGET_AT91SAM9M10G45EK
bool "Atmel AT91SAM9M10G45-EK board"
select CPU_ARM926EJS
@@ -103,22 +91,10 @@ config TARGET_SAMA5D4EK
select CPU_V7
select SUPPORT_SPL
-config TARGET_VL_MA2SC
- bool "Support vl_ma2sc"
- select CPU_ARM926EJS
-
config TARGET_MEESC
bool "Support meesc"
select CPU_ARM926EJS
-config TARGET_OTC570
- bool "Support otc570"
- select CPU_ARM926EJS
-
-config TARGET_CPU9260
- bool "Support cpu9260"
- select CPU_ARM926EJS
-
config TARGET_CORVUS
bool "Support corvus"
select CPU_ARM926EJS
@@ -151,15 +127,10 @@ source "board/atmel/sama5d3_xplained/Kconfig"
source "board/atmel/sama5d3xek/Kconfig"
source "board/atmel/sama5d4_xplained/Kconfig"
source "board/atmel/sama5d4ek/Kconfig"
-source "board/BuS/eb_cpux9k2/Kconfig"
-source "board/eukrea/cpuat91/Kconfig"
source "board/bluewater/snapper9260/Kconfig"
-source "board/BuS/vl_ma2sc/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"
-source "board/esd/otc570/Kconfig"
-source "board/eukrea/cpu9260/Kconfig"
source "board/mini-box/picosam9g45/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
@@ -167,6 +138,5 @@ source "board/ronetix/pm9g45/Kconfig"
source "board/siemens/corvus/Kconfig"
source "board/siemens/taurus/Kconfig"
source "board/siemens/smartweb/Kconfig"
-source "board/taskit/stamp9g20/Kconfig"
endif
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 681270d..a8d3e2f 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -4,50 +4,20 @@ choice
prompt "DaVinci board select"
optional
-config TARGET_ENBW_CMC
- bool "EnBW CMC board"
-
config TARGET_IPAM390
bool "IPAM390 board"
select SUPPORT_SPL
-config TARGET_DA830EVM
- bool "DA830 EVM board"
-
config TARGET_DA850EVM
bool "DA850 EVM board"
select SUPPORT_SPL
-config TARGET_OMAPL138_LCDK
- bool "OMAPL138 LCDK"
- select SUPPORT_SPL
-
-config TARGET_DAVINCI_DM355EVM
- bool "DM355 EVM board"
-
-config TARGET_DAVINCI_DM355LEOPARD
- bool "DM355 Leopard board"
-
-config TARGET_DAVINCI_DM365EVM
- bool "DM365 EVM board"
-
-config TARGET_DAVINCI_DM6467EVM
- bool "DM6467 EVM board"
-
-config TARGET_DAVINCI_DVEVM
- bool "DVEVM board"
-
config TARGET_EA20
bool "EA20 board"
-config TARGET_DAVINCI_SCHMOOGIE
- bool "Schmoogie board"
-
-config TARGET_DAVINCI_SFFSDR
- bool "SFFSDR board"
-
-config TARGET_DAVINCI_SONATA
- bool "Sonata board"
+config TARGET_OMAPL138_LCDK
+ bool "OMAPL138 LCDK"
+ select SUPPORT_SPL
config TARGET_CALIMAIN
bool "Calimain board"
@@ -57,18 +27,9 @@ endchoice
config SYS_SOC
default "davinci"
-source "board/enbw/enbw_cmc/Kconfig"
source "board/Barix/ipam390/Kconfig"
source "board/davinci/da8xxevm/Kconfig"
-source "board/davinci/dm355evm/Kconfig"
-source "board/davinci/dm355leopard/Kconfig"
-source "board/davinci/dm365evm/Kconfig"
-source "board/davinci/dm6467evm/Kconfig"
-source "board/davinci/dvevm/Kconfig"
source "board/davinci/ea20/Kconfig"
-source "board/davinci/schmoogie/Kconfig"
-source "board/davinci/sffsdr/Kconfig"
-source "board/davinci/sonata/Kconfig"
source "board/omicron/calimain/Kconfig"
endif
diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c
index ff61147..74c3d5d 100644
--- a/arch/arm/mach-davinci/cpu.c
+++ b/arch/arm/mach-davinci/cpu.c
@@ -28,8 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define PLLC_PLLDIV8 0x170
#define PLLC_PLLDIV9 0x174
-#define BIT(x) (1 << (x))
-
/* SOC-specific pll info */
#ifdef CONFIG_SOC_DM355
#define ARM_PLLDIV PLLC_PLLDIV1
diff --git a/arch/arm/mach-exynos/clock.c b/arch/arm/mach-exynos/clock.c
index 1c6baa1..18eadf5 100644
--- a/arch/arm/mach-exynos/clock.c
+++ b/arch/arm/mach-exynos/clock.c
@@ -1661,6 +1661,9 @@ unsigned long get_mmc_clk(int dev_index)
{
enum periph_id id;
+ if (cpu_is_exynos4())
+ return exynos4_get_mmc_clk(dev_index);
+
switch (dev_index) {
case 0:
id = PERIPH_ID_SDMMC0;
@@ -1679,12 +1682,7 @@ unsigned long get_mmc_clk(int dev_index)
return -1;
}
- if (cpu_is_exynos5())
- return clock_get_periph_rate(id);
- else if (cpu_is_exynos4())
- return exynos4_get_mmc_clk(dev_index);
-
- return 0;
+ return clock_get_periph_rate(id);
}
void set_mmc_clk(int dev_index, unsigned int div)
diff --git a/arch/arm/mach-keystone/include/mach/clock_defs.h b/arch/arm/mach-keystone/include/mach/clock_defs.h
index 8ad371f..f8d61d6 100644
--- a/arch/arm/mach-keystone/include/mach/clock_defs.h
+++ b/arch/arm/mach-keystone/include/mach/clock_defs.h
@@ -11,8 +11,6 @@
#include <asm/arch/hardware.h>
-#define BIT(x) (1 << (x))
-
/* PLL Control Registers */
struct pllctl_regs {
u32 ctl; /* 00 */
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index 53f28ec..f98a24e 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -24,8 +24,6 @@ typedef volatile unsigned int *dv_reg_p;
#endif
-#define BIT(x) (1 << (x))
-
#define KS2_DDRPHY_PIR_OFFSET 0x04
#define KS2_DDRPHY_PGCR0_OFFSET 0x08
#define KS2_DDRPHY_PGCR1_OFFSET 0x0C
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 1261885..aab5d19 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -4,15 +4,6 @@ choice
prompt "Marvell Kirkwood board select"
optional
-config TARGET_OPENRD
- bool "Marvell OpenRD Board"
-
-config TARGET_MV88F6281GTW_GE
- bool "MV88f6281GTW_GE Board"
-
-config TARGET_RD6281A
- bool "RD6281A Board"
-
config TARGET_DREAMPLUG
bool "DreamPlug Board"
@@ -34,9 +25,6 @@ config TARGET_DNS325
config TARGET_ICONNECT
bool "iconnect Board"
-config TARGET_TK71
- bool "TK71 Board"
-
config TARGET_KM_KIRKWOOD
bool "KM_KIRKWOOD Board"
@@ -46,9 +34,6 @@ config TARGET_NET2BIG_V2
config TARGET_NETSPACE_V2
bool "LaCie netspace_v2 Board"
-config TARGET_WIRELESS_SPACE
- bool "LaCie Wireless_space Board"
-
config TARGET_IB62X0
bool "ib62x0 Board"
@@ -66,9 +51,6 @@ endchoice
config SYS_SOC
default "kirkwood"
-source "board/Marvell/openrd/Kconfig"
-source "board/Marvell/mv88f6281gtw_ge/Kconfig"
-source "board/Marvell/rd6281a/Kconfig"
source "board/Marvell/dreamplug/Kconfig"
source "board/Marvell/guruplug/Kconfig"
source "board/Marvell/sheevaplug/Kconfig"
@@ -76,11 +58,9 @@ source "board/buffalo/lsxl/Kconfig"
source "board/cloudengines/pogo_e02/Kconfig"
source "board/d-link/dns325/Kconfig"
source "board/iomega/iconnect/Kconfig"
-source "board/karo/tk71/Kconfig"
source "board/keymile/km_arm/Kconfig"
source "board/LaCie/net2big_v2/Kconfig"
source "board/LaCie/netspace_v2/Kconfig"
-source "board/LaCie/wireless_space/Kconfig"
source "board/raidsonic/ib62x0/Kconfig"
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index ea83e21..efd4d04 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -214,32 +214,40 @@ static void setup_usb_phys(void)
int arch_cpu_init(void)
{
-#ifndef CONFIG_SPL_BUILD
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMADA_38X)
+ /*
+ * Only with disabled MMU its possible to switch the base
+ * register address on Armada 38x. Without this the SDRAM
+ * located at >= 0x4000.0000 is also not accessible, as its
+ * still locked to cache.
+ */
+ mmu_disable();
+#endif
+
+ /* Linux expects the internal registers to be at 0xf1000000 */
+ writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
+ set_cbar(SOC_REGS_PHY_BASE + 0xC000);
+
+#if !defined(CONFIG_SPL_BUILD)
+ /*
+ * From this stage on, the SoC detection is working. As we have
+ * configured the internal register base to the value used
+ * in the macros / defines in the U-Boot header (soc.h).
+ */
if (mvebu_soc_family() == MVEBU_SOC_A38X) {
struct pl310_regs *const pl310 =
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
/*
- * Only with disabled MMU its possible to switch the base
- * register address on Armada 38x. Without this the SDRAM
- * located at >= 0x4000.0000 is also not accessible, as its
- * still locked to cache.
- *
- * So to fully release / unlock this area from cache, we need
- * to first flush all caches, then disable the MMU and
- * disable the L2 cache.
+ * To fully release / unlock this area from cache, we need
+ * to flush all caches and disable the L2 cache.
*/
icache_disable();
dcache_disable();
- mmu_disable();
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
}
#endif
- /* Linux expects the internal registers to be at 0xf1000000 */
- writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
- set_cbar(SOC_REGS_PHY_BASE + 0xC000);
-
/*
* We need to call mvebu_mbus_probe() before calling
* update_sdram_window_sizes() as it disables all previously
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index a8a6b27..02c21bc 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -11,8 +11,6 @@
#ifndef _MVEBU_SOC_H
#define _MVEBU_SOC_H
-#define BIT(x) (1 << (x))
-
#define SOC_MV78460_ID 0x7846
#define SOC_88F6810_ID 0x6810
#define SOC_88F6820_ID 0x6820
diff --git a/arch/arm/mach-mvebu/timer.c b/arch/arm/mach-mvebu/timer.c
index c516c41..5449a89 100644
--- a/arch/arm/mach-mvebu/timer.c
+++ b/arch/arm/mach-mvebu/timer.c
@@ -41,7 +41,7 @@
#define timestamp gd->arch.tbl
#define lastdec gd->arch.lastinc
-static int init_done;
+static int init_done __attribute__((section(".data"))) = 0;
/* Timer reload and current value registers */
struct kwtmr_val {
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
deleted file mode 100644
index ba72a41..0000000
--- a/arch/arm/mach-nomadik/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if ARCH_NOMADIK
-
-choice
- prompt "Nomadik board select"
- optional
-
-config NOMADIK_NHK8815
- bool "ST 8815 Nomadik Hardware Kit"
-
-endchoice
-
-config SYS_SOC
- default "nomadik"
-
-source "board/st/nhk8815/Kconfig"
-
-endif
diff --git a/arch/arm/mach-nomadik/Makefile b/arch/arm/mach-nomadik/Makefile
deleted file mode 100644
index cdf1345..0000000
--- a/arch/arm/mach-nomadik/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = timer.o gpio.o
-obj-y += reset.o
diff --git a/arch/arm/mach-nomadik/gpio.c b/arch/arm/mach-nomadik/gpio.c
deleted file mode 100644
index eff5b2b..0000000
--- a/arch/arm/mach-nomadik/gpio.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/gpio.h>
-
-static unsigned long gpio_base[4] = {
- NOMADIK_GPIO0_BASE,
- NOMADIK_GPIO1_BASE,
- NOMADIK_GPIO2_BASE,
- NOMADIK_GPIO3_BASE
-};
-
-enum gpio_registers {
- GPIO_DAT = 0x00, /* data register */
- GPIO_DATS = 0x04, /* data set */
- GPIO_DATC = 0x08, /* data clear */
- GPIO_PDIS = 0x0c, /* pull disable */
- GPIO_DIR = 0x10, /* direction */
- GPIO_DIRS = 0x14, /* direction set */
- GPIO_DIRC = 0x18, /* direction clear */
- GPIO_AFSLA = 0x20, /* alternate function select A */
- GPIO_AFSLB = 0x24, /* alternate function select B */
-};
-
-static inline unsigned long gpio_to_base(int gpio)
-{
- return gpio_base[gpio / 32];
-}
-
-static inline u32 gpio_to_bit(int gpio)
-{
- return 1 << (gpio & 0x1f);
-}
-
-void nmk_gpio_af(int gpio, int alternate_function)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
- u32 afunc, bfunc;
-
- /* alternate function is 0..3, with one bit per register */
- afunc = readl(base + GPIO_AFSLA) & ~bit;
- bfunc = readl(base + GPIO_AFSLB) & ~bit;
- if (alternate_function & 1) afunc |= bit;
- if (alternate_function & 2) bfunc |= bit;
- writel(afunc, base + GPIO_AFSLA);
- writel(bfunc, base + GPIO_AFSLB);
-}
-
-void nmk_gpio_dir(int gpio, int dir)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
-
- if (dir)
- writel(bit, base + GPIO_DIRS);
- else
- writel(bit, base + GPIO_DIRC);
-}
-
-void nmk_gpio_set(int gpio, int val)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
-
- if (val)
- writel(bit, base + GPIO_DATS);
- else
- writel(bit, base + GPIO_DATC);
-}
-
-int nmk_gpio_get(int gpio)
-{
- unsigned long base = gpio_to_base(gpio);
- u32 bit = gpio_to_bit(gpio);
-
- return readl(base + GPIO_DAT) & bit;
-}
diff --git a/arch/arm/mach-nomadik/include/mach/gpio.h b/arch/arm/mach-nomadik/include/mach/gpio.h
deleted file mode 100644
index 311758a..0000000
--- a/arch/arm/mach-nomadik/include/mach/gpio.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __NMK_GPIO_H__
-#define __NMK_GPIO_H__
-
-/*
- * These functions are called from the soft-i2c driver, but
- * are also used by board files to set output bits.
- */
-
-enum nmk_af { /* alternate function settings */
- GPIO_GPIO = 0,
- GPIO_ALT_A,
- GPIO_ALT_B,
- GPIO_ALT_C
-};
-
-extern void nmk_gpio_af(int gpio, int alternate_function);
-extern void nmk_gpio_dir(int gpio, int dir);
-extern void nmk_gpio_set(int gpio, int val);
-extern int nmk_gpio_get(int gpio);
-
-#endif /* __NMK_GPIO_H__ */
diff --git a/arch/arm/mach-nomadik/include/mach/mtu.h b/arch/arm/mach-nomadik/include/mach/mtu.h
deleted file mode 100644
index f89f242..0000000
--- a/arch/arm/mach-nomadik/include/mach/mtu.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_MTU_H
-#define __ASM_ARCH_MTU_H
-
-/*
- * The MTU device hosts four different counters, with 4 set of
- * registers. These are register names.
- */
-
-#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
-#define MTU_RIS 0x04 /* Raw interrupt status */
-#define MTU_MIS 0x08 /* Masked interrupt status */
-#define MTU_ICR 0x0C /* Interrupt clear register */
-
-/* per-timer registers take 0..3 as argument */
-#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
-#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
-#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
-#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
-
-/* bits for the control register */
-#define MTU_CRn_ENA 0x80
-#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
-#define MTU_CRn_PRESCALE_MASK 0x0c
-#define MTU_CRn_PRESCALE_1 0x00
-#define MTU_CRn_PRESCALE_16 0x04
-#define MTU_CRn_PRESCALE_256 0x08
-#define MTU_CRn_32BITS 0x02
-#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
-
-/* Other registers are usual amba/primecell registers, currently not used */
-#define MTU_ITCR 0xff0
-#define MTU_ITOP 0xff4
-
-#define MTU_PERIPH_ID0 0xfe0
-#define MTU_PERIPH_ID1 0xfe4
-#define MTU_PERIPH_ID2 0xfe8
-#define MTU_PERIPH_ID3 0xfeC
-
-#define MTU_PCELL0 0xff0
-#define MTU_PCELL1 0xff4
-#define MTU_PCELL2 0xff8
-#define MTU_PCELL3 0xffC
-
-#endif /* __ASM_ARCH_MTU_H */
diff --git a/arch/arm/mach-nomadik/reset.S b/arch/arm/mach-nomadik/reset.S
deleted file mode 100644
index ec95472..0000000
--- a/arch/arm/mach-nomadik/reset.S
+++ /dev/null
@@ -1,14 +0,0 @@
-#include <config.h>
-/*
- * Processor reset for Nomadik
- */
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- ldr r0, =NOMADIK_SRC_BASE /* System and Reset Controller */
- ldr r1, =0x1
- str r1, [r0, #0x18]
-
-_loop_forever:
- b _loop_forever
diff --git a/arch/arm/mach-nomadik/timer.c b/arch/arm/mach-nomadik/timer.c
deleted file mode 100644
index 775d0b7..0000000
--- a/arch/arm/mach-nomadik/timer.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2009 Alessandro Rubini
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/mtu.h>
-
-/*
- * The timer is a decrementer, we'll left it free running at 2.4MHz.
- * We have 2.4 ticks per microsecond and an overflow in almost 30min
- */
-#define TIMER_CLOCK (24 * 100 * 1000)
-#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */
-#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */
-#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ)
-#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ)
-
-/* macro to read the decrementing 32 bit timer as an increasing count */
-#define READ_TIMER() (0 - readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0)))
-
-/* Configure a free-running, auto-wrap counter with no prescaler */
-int timer_init(void)
-{
- ulong val;
-
- writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS,
- CONFIG_SYS_TIMERBASE + MTU_CR(0));
-
- /* Reset the timer */
- writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0));
- /*
- * The load-register isn't really immediate: it changes on clock
- * edges, so we must wait for our newly-written value to appear.
- * Since we might miss reading 0, wait for any change in value.
- */
- val = READ_TIMER();
- while (READ_TIMER() == val)
- ;
-
- return 0;
-}
-
-/* Return how many HZ passed since "base" */
-ulong get_timer(ulong base)
-{
- return TICKS_TO_HZ(READ_TIMER()) - base;
-}
-
-/* Delay x useconds */
-void __udelay(unsigned long usec)
-{
- ulong ini, end;
-
- ini = READ_TIMER();
- end = ini + USEC_TO_COUNT(usec);
- while ((signed)(end - READ_TIMER()) > 0)
- ;
-}
-
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-ulong get_tbclk(void)
-{
- return CONFIG_SYS_HZ;
-}
diff --git a/arch/arm/mach-rockchip/board-spl.c b/arch/arm/mach-rockchip/board-spl.c
index a241d96..28c3949 100644
--- a/arch/arm/mach-rockchip/board-spl.c
+++ b/arch/arm/mach-rockchip/board-spl.c
@@ -217,6 +217,13 @@ void board_init_f(ulong dummy)
debug("DRAM init failed: %d\n", ret);
return;
}
+
+ /*
+ * Now that DRAM is initialized setup base pointer for simple malloc
+ * into RAM.
+ */
+ gd->malloc_base = CONFIG_SPL_STACK_R_ADDR;
+ gd->malloc_ptr = 0;
}
static int setup_led(void)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 089280a..a413ea4 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -50,8 +50,8 @@ config SYS_SOC
default "socfpga"
config SYS_CONFIG_NAME
- default "socfpga_arria5" if TARGET_SOCFPGA_ARRIA5_SOCDK
- default "socfpga_cyclone5" if TARGET_SOCFPGA_CYCLONE5_SOCDK
+ default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
+ default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index f9dfcd0..f75c6c6 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -461,6 +461,11 @@ void reset_cmplx_set_enable(int cpu, int which, int reset)
writel(mask, &clkrst->crc_cpu_cmplx_clr);
}
+unsigned int __weak clk_m_get_rate(unsigned int parent_rate)
+{
+ return parent_rate;
+}
+
unsigned clock_get_rate(enum clock_id clkid)
{
struct clk_pll *pll;
@@ -472,6 +477,9 @@ unsigned clock_get_rate(enum clock_id clkid)
if (clkid == CLOCK_ID_OSC)
return parent_rate;
+ if (clkid == CLOCK_ID_CLK_M)
+ return clk_m_get_rate(parent_rate);
+
pll = get_pll(clkid);
if (!pll)
return 0;
@@ -483,7 +491,16 @@ unsigned clock_get_rate(enum clock_id clkid)
* PLLU uses p_mask/p_shift for VCO on all but T210,
* T210 uses normal DIVP. Handled in pllinfo table.
*/
- divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
+#ifdef CONFIG_TEGRA210
+ /*
+ * PLLP's primary output (pllP_out0) on T210 is the VCO, and divp is
+ * not applied. pllP_out2 does have divp applied. All other pllP_outN
+ * are divided down from pllP_out0. We only support pllP_out0 in
+ * U-Boot at the time of writing this comment.
+ */
+ if (clkid != CLOCK_ID_PERIPH)
+#endif
+ divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
do_div(rate, divm);
return rate;
}
@@ -613,8 +630,10 @@ void clock_init(void)
pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
+ pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);
debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
+ debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);
debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
diff --git a/arch/arm/mach-tegra/tegra114/clock.c b/arch/arm/mach-tegra/tegra114/clock.c
index 5e805a7..e6ef873 100644
--- a/arch/arm/mach-tegra/tegra114/clock.c
+++ b/arch/arm/mach-tegra/tegra114/clock.c
@@ -629,6 +629,11 @@ void clock_early_init(void)
tegra30_set_up_pllp();
+ /* clear IDDQ before accessing any other PLLC registers */
+ pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
+ clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
+ udelay(2);
+
/*
* PLLC output frequency set to 600Mhz
* PLLD output frequency set to 925Mhz
@@ -679,8 +684,8 @@ void arch_timer_init(void)
struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
u32 freq, val;
- freq = clock_get_rate(CLOCK_ID_OSC);
- debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+ freq = clock_get_rate(CLOCK_ID_CLK_M);
+ debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
/* ARM CNTFRQ */
asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c
index 61e8ab7..1e71146 100644
--- a/arch/arm/mach-tegra/tegra124/clock.c
+++ b/arch/arm/mach-tegra/tegra124/clock.c
@@ -809,6 +809,11 @@ void clock_early_init(void)
tegra30_set_up_pllp();
+ /* clear IDDQ before accessing any other PLLC registers */
+ pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL];
+ clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ);
+ udelay(2);
+
/*
* PLLC output frequency set to 600Mhz
* PLLD output frequency set to 925Mhz
@@ -859,8 +864,8 @@ void arch_timer_init(void)
struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
u32 freq, val;
- freq = clock_get_rate(CLOCK_ID_OSC);
- debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+ freq = clock_get_rate(CLOCK_ID_CLK_M);
+ debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
/* ARM CNTFRQ */
asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig
index bd34db7..b07363a 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -18,6 +18,14 @@ config TARGET_P2371_0000
HDMI, USB micro-B port, Ethernet via USB3, USB3 host port, SATA,
a GPIO expansion header, and an analog audio jack.
+config TARGET_P2371_2180
+ bool "NVIDIA Tegra210 P2371-2180 board"
+ help
+ P2371-2180 is a P2180 CPU board married to a P2597 I/O board. The
+ combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB
+ micro-B port, Ethernet via USB3, USB3 host port, SATA, PCIe, and
+ two GPIO expansion headers.
+
config TARGET_P2571
bool "NVIDIA Tegra210 P2571 base board"
help
@@ -30,6 +38,7 @@ config SYS_SOC
source "board/nvidia/e2220-1170/Kconfig"
source "board/nvidia/p2371-0000/Kconfig"
+source "board/nvidia/p2371-2180/Kconfig"
source "board/nvidia/p2571/Kconfig"
endif
diff --git a/arch/arm/mach-tegra/tegra210/clock.c b/arch/arm/mach-tegra/tegra210/clock.c
index 830a33f..6d75d37 100644
--- a/arch/arm/mach-tegra/tegra210/clock.c
+++ b/arch/arm/mach-tegra/tegra210/clock.c
@@ -998,18 +998,27 @@ void clock_early_init(void)
udelay(2);
}
+unsigned int clk_m_get_rate(unsigned parent_rate)
+{
+ struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+ u32 value, div;
+
+ value = readl(&clkrst->crc_spare_reg0);
+ div = ((value >> 2) & 0x3) + 1;
+
+ return parent_rate / div;
+}
+
void arch_timer_init(void)
{
struct sysctr_ctlr *sysctr = (struct sysctr_ctlr *)NV_PA_TSC_BASE;
u32 freq, val;
- freq = clock_get_rate(CLOCK_ID_OSC);
- debug("%s: osc freq is %dHz [0x%08X]\n", __func__, freq, freq);
+ freq = clock_get_rate(CLOCK_ID_CLK_M);
+ debug("%s: clk_m freq is %dHz [0x%08X]\n", __func__, freq, freq);
- /* ARM CNTFRQ */
-#ifndef CONFIG_ARM64
- asm("mcr p15, 0, %0, c14, c0, 0\n" : : "r" (freq));
-#endif
+ if (current_el() == 3)
+ asm("msr cntfrq_el0, %0\n" : : "r" (freq));
/* Only Tegra114+ has the System Counter regs */
debug("%s: setting CNTFID0 to 0x%08X\n", __func__, freq);
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 7b49ad3..22ab798 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -6,49 +6,68 @@ config SYS_CONFIG_NAME
config UNIPHIER_SMP
bool
-choice
- prompt "UniPhier SoC select"
- default MACH_PH1_PRO4
-
-config MACH_PH1_SLD3
- bool "PH1-sLD3"
+config ARCH_UNIPHIER_PH1_SLD3
+ bool "UniPhier PH1-sLD3 SoC"
select UNIPHIER_SMP
+ help
+ This enables support for UniPhier PH1-sLD3 SoC.
-config MACH_PH1_LD4
- bool "PH1-LD4"
+config ARCH_UNIPHIER_PH1_LD4
+ bool "UniPhier PH1-LD4 SoC"
+ depends on !ARCH_UNIPHIER_PH1_SLD3
+ help
+ This enables support for UniPhier PH1-LD4 SoC.
-config MACH_PH1_PRO4
- bool "PH1-Pro4"
+config ARCH_UNIPHIER_PH1_PRO4
+ bool "UniPhier PH1-Pro4 SoC"
select UNIPHIER_SMP
+ depends on !ARCH_UNIPHIER_PH1_SLD3 && \
+ !ARCH_UNIPHIER_PH1_LD4 && \
+ !ARCH_UNIPHIER_PH1_SLD8
+ help
+ This enables support for UniPhier PH1-Pro4 SoC.
-config MACH_PH1_SLD8
- bool "PH1-sLD8"
-
-endchoice
+config ARCH_UNIPHIER_PH1_SLD8
+ bool "UniPhier PH1-sLD8 SoC"
+ depends on !ARCH_UNIPHIER_PH1_SLD3
+ help
+ This enables support for UniPhier PH1-sLD8 SoC.
-choice
- prompt "UniPhier Support Card select"
- optional
+config ARCH_UNIPHIER_PH1_PRO5
+ bool "UniPhier PH1-Pro5 SoC"
+ select UNIPHIER_SMP
+ depends on !ARCH_UNIPHIER_PH1_SLD3 && \
+ !ARCH_UNIPHIER_PH1_LD4 && \
+ !ARCH_UNIPHIER_PH1_SLD8
+ help
+ This enables support for UniPhier PH1-Pro5 SoC.
-config PFC_MICRO_SUPPORT_CARD
- bool "Support card with PFC CPLD"
+config ARCH_UNIPHIER_PROXSTREAM2
+ bool "UniPhier ProXstream2 SoC"
+ select UNIPHIER_SMP
+ depends on !ARCH_UNIPHIER_PH1_SLD3 && \
+ !ARCH_UNIPHIER_PH1_LD4 && \
+ !ARCH_UNIPHIER_PH1_SLD8
help
- This option provides support for the expansion board with PFC
- original address mapping.
+ This enables support for UniPhier ProXstream2 SoC.
- Say Y to use the on-board UART, Ether, LED devices.
+config ARCH_UNIPHIER_PH1_LD6B
+ bool "UniPhier PH1-LD6b SoC"
+ select UNIPHIER_SMP
+ depends on !ARCH_UNIPHIER_PH1_SLD3 && \
+ !ARCH_UNIPHIER_PH1_LD4 && \
+ !ARCH_UNIPHIER_PH1_SLD8
+ help
+ This enables support for UniPhier PH1-LD6b SoC.
-config DCC_MICRO_SUPPORT_CARD
- bool "Support card with DCC CPLD"
+config MICRO_SUPPORT_CARD
+ bool "Use Micro Support Card"
help
- This option provides support for the expansion board with DCC-
- arranged address mapping that is compatible with legacy UniPhier
- reference boards.
+ This option provides support for the expansion board, available
+ on some UniPhier reference boards.
Say Y to use the on-board UART, Ether, LED devices.
-endchoice
-
config CMD_PINMON
bool "Enable boot mode pins monitor command"
default y
@@ -63,22 +82,4 @@ config CMD_DDRPHY_DUMP
The command "ddrphy" shows the resulting parameters of DDR PHY
training; it is useful for the evaluation of DDR PHY training.
-choice
- prompt "DDR3 Frequency select"
-
-config DDR_FREQ_1600
- bool "DDR3 1600"
- depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_PRO4
-
-config DDR_FREQ_1333
- bool "DDR3 1333"
- depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_SLD8
-
-endchoice
-
-config DDR_FREQ
- int
- default 1333 if DDR_FREQ_1333
- default 1600 if DDR_FREQ_1600
-
endif
diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 103db6d..b597a13 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -6,9 +6,12 @@ ifdef CONFIG_SPL_BUILD
obj-y += lowlevel_init.o
obj-y += init_page_table.o
-obj-y += spl.o
-obj-y += memconf.o
-obj-y += ddrphy_training.o
+obj-y += boards.o
+
+obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ umc/ ddrphy/
+obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
+
+obj-$(CONFIG_DEBUG_LL) += debug_ll.o
else
@@ -25,14 +28,12 @@ obj-y += cache_uniphier.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o
obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
+obj-y += pinctrl/ clk/
+
endif
obj-y += timer.o
+obj-y += soc_info.o
+obj-y += boot-mode/
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += support_card.o
-
-obj-$(CONFIG_MACH_PH1_SLD3) += ph1-sld3/
-obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/
-obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/
-obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/
+obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
diff --git a/arch/arm/mach-uniphier/bcu/Makefile b/arch/arm/mach-uniphier/bcu/Makefile
new file mode 100644
index 0000000..5b95bda
--- /dev/null
+++ b/arch/arm/mach-uniphier/bcu/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += bcu-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += bcu-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += bcu-ph1-ld4.o
diff --git a/arch/arm/mach-uniphier/ph1-ld4/bcu_init.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c
index a7bc15e..e9d3761 100644
--- a/arch/arm/mach-uniphier/ph1-ld4/bcu_init.c
+++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c
@@ -4,13 +4,13 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
#include <linux/io.h>
#include <mach/bcu-regs.h>
+#include <mach/init.h>
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
-void bcu_init(void)
+int ph1_ld4_bcu_init(const struct uniphier_board_data *bd)
{
int shift;
@@ -21,7 +21,7 @@ void bcu_init(void)
writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
/* Specify DDR channel */
- shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
+ shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4;
writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
shift -= 32;
@@ -29,4 +29,6 @@ void bcu_init(void)
shift -= 32;
writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
+
+ return 0;
}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/bcu_init.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c
index ccc6897..cb6f862 100644
--- a/arch/arm/mach-uniphier/ph1-sld3/bcu_init.c
+++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c
@@ -4,13 +4,13 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
#include <linux/io.h>
#include <mach/bcu-regs.h>
+#include <mach/init.h>
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
-void bcu_init(void)
+int ph1_sld3_bcu_init(const struct uniphier_board_data *bd)
{
int shift;
@@ -25,7 +25,7 @@ void bcu_init(void)
writel(0x24440000, BCSCR5);
/* Specify DDR channel */
- shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4;
+ shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4;
writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
shift -= 32;
@@ -33,4 +33,6 @@ void bcu_init(void)
shift -= 32;
writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
+
+ return 0;
}
diff --git a/arch/arm/mach-uniphier/board_common.c b/arch/arm/mach-uniphier/board_common.c
index 5f2d5f6..198004b 100644
--- a/arch/arm/mach-uniphier/board_common.c
+++ b/arch/arm/mach-uniphier/board_common.c
@@ -1,32 +1,15 @@
/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <mach/led.h>
+#include <mach/micro-support-card.h>
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
int board_init(void)
{
- led_write(U, B, O, O);
+ led_puts("Uboo");
return 0;
}
-
-#if CONFIG_NR_DRAM_BANKS >= 2
-void dram_init_banksize(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE;
- gd->bd->bi_dram[0].size = CONFIG_SDRAM0_SIZE;
- gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE;
- gd->bd->bi_dram[1].size = CONFIG_SDRAM1_SIZE;
-}
-#endif
diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c
index 7108740..5e0d246 100644
--- a/arch/arm/mach-uniphier/board_early_init_f.c
+++ b/arch/arm/mach-uniphier/board_early_init_f.c
@@ -1,27 +1,72 @@
/*
- * Copyright (C) 2012-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/led.h>
-#include <mach/board.h>
-
-void pin_init(void);
-void clkrst_init(void);
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+#include <mach/soc_info.h>
int board_early_init_f(void)
{
- led_write(U, 0, , );
-
- pin_init();
-
- led_write(U, 1, , );
+ led_puts("U0");
- clkrst_init();
+ switch (uniphier_get_soc_type()) {
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+ case SOC_UNIPHIER_PH1_SLD3:
+ ph1_sld3_pin_init();
+ led_puts("U1");
+ ph1_ld4_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
+ case SOC_UNIPHIER_PH1_LD4:
+ ph1_ld4_pin_init();
+ led_puts("U1");
+ ph1_ld4_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+ case SOC_UNIPHIER_PH1_PRO4:
+ ph1_pro4_pin_init();
+ led_puts("U1");
+ ph1_pro4_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+ case SOC_UNIPHIER_PH1_SLD8:
+ ph1_sld8_pin_init();
+ led_puts("U1");
+ ph1_ld4_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+ case SOC_UNIPHIER_PH1_PRO5:
+ ph1_pro5_pin_init();
+ led_puts("U1");
+ ph1_pro5_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
+ case SOC_UNIPHIER_PROXSTREAM2:
+ proxstream2_pin_init();
+ led_puts("U1");
+ proxstream2_clk_init();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ case SOC_UNIPHIER_PH1_LD6B:
+ ph1_ld6b_pin_init();
+ led_puts("U1");
+ proxstream2_clk_init();
+ break;
+#endif
+ default:
+ break;
+ }
- led_write(U, 2, , );
+ led_puts("U2");
return 0;
}
diff --git a/arch/arm/mach-uniphier/board_early_init_r.c b/arch/arm/mach-uniphier/board_early_init_r.c
index 579fe70..28c7f82 100644
--- a/arch/arm/mach-uniphier/board_early_init_r.c
+++ b/arch/arm/mach-uniphier/board_early_init_r.c
@@ -1,15 +1,14 @@
/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <mach/board.h>
+#include <mach/micro-support-card.h>
int board_early_init_r(void)
{
- uniphier_board_late_init();
+ support_card_late_init();
return 0;
}
diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
new file mode 100644
index 0000000..812c58f
--- /dev/null
+++ b/arch/arm/mach-uniphier/boards.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <libfdt.h>
+#include <linux/kernel.h>
+#include <mach/init.h>
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+static const struct uniphier_board_data ph1_sld3_data = {
+ .dram_ch0_base = 0x80000000,
+ .dram_ch0_size = 0x20000000,
+ .dram_ch0_width = 32,
+ .dram_ch1_base = 0xc0000000,
+ .dram_ch1_size = 0x20000000,
+ .dram_ch1_width = 16,
+ .dram_ch2_base = 0xc0000000,
+ .dram_ch2_size = 0x10000000,
+ .dram_ch2_width = 16,
+ .dram_freq = 1600,
+};
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
+static const struct uniphier_board_data ph1_ld4_data = {
+ .dram_ch0_base = 0x80000000,
+ .dram_ch0_size = 0x10000000,
+ .dram_ch0_width = 16,
+ .dram_ch1_base = 0x90000000,
+ .dram_ch1_size = 0x10000000,
+ .dram_ch1_width = 16,
+ .dram_freq = 1600,
+};
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+static const struct uniphier_board_data ph1_pro4_data = {
+ .dram_ch0_base = 0x80000000,
+ .dram_ch0_size = 0x20000000,
+ .dram_ch0_width = 32,
+ .dram_ch1_base = 0xa0000000,
+ .dram_ch1_size = 0x20000000,
+ .dram_ch1_width = 32,
+ .dram_freq = 1600,
+};
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+static const struct uniphier_board_data ph1_sld8_data = {
+ .dram_ch0_base = 0x80000000,
+ .dram_ch0_size = 0x10000000,
+ .dram_ch0_width = 16,
+ .dram_ch1_base = 0x90000000,
+ .dram_ch1_size = 0x10000000,
+ .dram_ch1_width = 16,
+ .dram_freq = 1333,
+};
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+static const struct uniphier_board_data ph1_pro5_data = {
+ .dram_ch0_base = 0x80000000,
+ .dram_ch0_size = 0x20000000,
+ .dram_ch0_width = 32,
+ .dram_ch1_base = 0xa0000000,
+ .dram_ch1_size = 0x20000000,
+ .dram_ch1_width = 32,
+ .dram_freq = 1866,
+};
+#endif
+
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+static const struct uniphier_board_data proxstream2_data = {
+ .dram_ch0_base = 0x80000000,
+ .dram_ch0_size = 0x40000000,
+ .dram_ch0_width = 32,
+ .dram_ch1_base = 0xc0000000,
+ .dram_ch1_size = 0x20000000,
+ .dram_ch1_width = 32,
+ .dram_ch2_base = 0xe0000000,
+ .dram_ch2_size = 0x20000000,
+ .dram_ch2_width = 16,
+ .dram_freq = 1866,
+};
+#endif
+
+struct uniphier_board_id {
+ const char *compatible;
+ const struct uniphier_board_data *param;
+};
+
+static const struct uniphier_board_id uniphier_boards[] = {
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+ { "socionext,ph1-sld3", &ph1_sld3_data, },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
+ { "socionext,ph1-ld4", &ph1_ld4_data, },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+ { "socionext,ph1-pro4", &ph1_pro4_data, },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+ { "socionext,ph1-sld8", &ph1_sld8_data, },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+ { "socionext,ph1-pro5", &ph1_pro5_data, },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
+ { "socionext,proxstream2", &proxstream2_data, },
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ { "socionext,ph1-ld6b", &proxstream2_data, },
+#endif
+};
+
+const struct uniphier_board_data *uniphier_get_board_param(const void *fdt)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) {
+ if (!fdt_node_check_compatible(fdt, 0,
+ uniphier_boards[i].compatible))
+ return uniphier_boards[i].param;
+ }
+
+ return NULL;
+}
diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile
new file mode 100644
index 0000000..30c8874
--- /dev/null
+++ b/arch/arm/mach-uniphier/boot-mode/Makefile
@@ -0,0 +1,9 @@
+obj-y += boot-mode.o
+
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += boot-mode-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += boot-mode-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += boot-mode-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += boot-mode-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += boot-mode-ph1-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += boot-mode-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += boot-mode-proxstream2.o
diff --git a/arch/arm/mach-uniphier/ph1-pro4/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c
index 54a2510..f974d9f 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c
@@ -44,22 +44,31 @@ struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
- { /* sentinel */ }
};
-int get_boot_mode_sel(void)
+static int get_boot_mode_sel(void)
{
return (readl(SG_PINMON0) >> 1) & 0x1f;
}
-u32 spl_boot_device(void)
+u32 ph1_ld4_boot_device(void)
{
int boot_mode;
- if (boot_is_swapped())
- return BOOT_DEVICE_NOR;
-
boot_mode = get_boot_mode_sel();
return boot_device_table[boot_mode].type;
}
+
+void ph1_ld4_boot_mode_show(void)
+{
+ int mode_sel, i;
+
+ mode_sel = get_boot_mode_sel();
+
+ puts("Boot Mode Pin:\n");
+
+ for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+ printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+ boot_device_table[i].info);
+}
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c
new file mode 100644
index 0000000..c68cb59
--- /dev/null
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-pro5.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/boot-device.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+static struct boot_device_info boot_device_table[] = {
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128MB, Addr 4)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128MB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ { /* sentinel */ }
+};
+
+static int get_boot_mode_sel(void)
+{
+ return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 ph1_pro5_boot_device(void)
+{
+ int boot_mode;
+
+ boot_mode = get_boot_mode_sel();
+
+ return boot_device_table[boot_mode].type;
+}
+
+void ph1_pro5_boot_mode_show(void)
+{
+ int mode_sel, i;
+
+ mode_sel = get_boot_mode_sel();
+
+ puts("Boot Mode Pin:\n");
+
+ for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+ printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+ boot_device_table[i].info);
+}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c
index 40000af..c943e12 100644
--- a/arch/arm/mach-uniphier/ph1-sld3/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c
@@ -11,7 +11,7 @@
#include <mach/sg-regs.h>
#include <mach/sbc-regs.h>
-struct boot_device_info boot_device_table[] = {
+static struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "External Master"},
{BOOT_DEVICE_NONE, "Reserved"},
@@ -76,22 +76,31 @@ struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
{BOOT_DEVICE_NONE, "Reserved"},
- { /* sentinel */ }
};
-int get_boot_mode_sel(void)
+static int get_boot_mode_sel(void)
{
return readl(SG_PINMON0) & 0x3f;
}
-u32 spl_boot_device(void)
+u32 ph1_sld3_boot_device(void)
{
int boot_mode;
- if (boot_is_swapped())
- return BOOT_DEVICE_NOR;
-
boot_mode = get_boot_mode_sel();
return boot_device_table[boot_mode].type;
}
+
+void ph1_sld3_boot_mode_show(void)
+{
+ int mode_sel, i;
+
+ mode_sel = get_boot_mode_sel();
+
+ puts("Boot Mode Pin:\n");
+
+ for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+ printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+ boot_device_table[i].info);
+}
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
new file mode 100644
index 0000000..10a47c6
--- /dev/null
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/boot-device.h>
+#include <mach/init.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+static struct boot_device_info boot_device_table[] = {
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 4)"},
+ {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 4)"},
+ {BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
+ {BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
+ {BOOT_DEVICE_SPI, "SPI 3Byte CS1"},
+ {BOOT_DEVICE_SPI, "SPI 4Byte CS1"},
+ {BOOT_DEVICE_SPI, "SPI 4Byte CS0"},
+ {BOOT_DEVICE_SPI, "SPI 3Byte CS0"},
+ {BOOT_DEVICE_NONE, "Reserved"},
+};
+
+int get_boot_mode_sel(void)
+{
+ return (readl(SG_PINMON0) >> 1) & 0x1f;
+}
+
+u32 proxstream2_boot_device(void)
+{
+ int boot_mode;
+
+ boot_mode = get_boot_mode_sel();
+
+ return boot_device_table[boot_mode].type;
+}
+
+void proxstream2_boot_mode_show(void)
+{
+ int mode_sel, i;
+
+ mode_sel = get_boot_mode_sel();
+
+ puts("Boot Mode Pin:\n");
+
+ for (i = 0; i < ARRAY_SIZE(boot_device_table); i++)
+ printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
+ boot_device_table[i].info);
+}
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
new file mode 100644
index 0000000..c6cafa7
--- /dev/null
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/boot-device.h>
+#include <mach/sbc-regs.h>
+#include <mach/soc_info.h>
+
+u32 spl_boot_device(void)
+{
+ if (boot_is_swapped())
+ return BOOT_DEVICE_NOR;
+
+ switch (uniphier_get_soc_type()) {
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+ case SOC_UNIPHIER_PH1_SLD3:
+ return ph1_sld3_boot_device();
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+ case SOC_UNIPHIER_PH1_LD4:
+ case SOC_UNIPHIER_PH1_PRO4:
+ case SOC_UNIPHIER_PH1_SLD8:
+ return ph1_ld4_boot_device();
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+ case SOC_UNIPHIER_PH1_PRO5:
+ return ph1_pro5_boot_device();
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ case SOC_UNIPHIER_PROXSTREAM2:
+ case SOC_UNIPHIER_PH1_LD6B:
+ return proxstream2_boot_device();
+#endif
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+}
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
new file mode 100644
index 0000000..4f397b9
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -0,0 +1,7 @@
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += clk-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += clk-ph1-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += clk-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += clk-proxstream2.o
diff --git a/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c
index 2de81f0..8b95fbb 100644
--- a/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c
+++ b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c
@@ -5,9 +5,10 @@
*/
#include <linux/io.h>
+#include <mach/init.h>
#include <mach/sc-regs.h>
-void clkrst_init(void)
+void ph1_ld4_clk_init(void)
{
u32 tmp;
diff --git a/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c
index 46cace7..2e1b20a 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c
+++ b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c
@@ -5,9 +5,10 @@
*/
#include <linux/io.h>
+#include <mach/init.h>
#include <mach/sc-regs.h>
-void clkrst_init(void)
+void ph1_pro4_clk_init(void)
{
u32 tmp;
diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c b/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c
new file mode 100644
index 0000000..f78edbb
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/clk-ph1-pro5.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+void ph1_pro5_clk_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp = readl(SC_RSTCTRL2);
+ tmp |= SC_RSTCTRL2_NRST_USB3B1;
+ writel(tmp, SC_RSTCTRL2);
+ readl(SC_RSTCTRL2); /* dummy read */
+#endif
+
+ /* privide clocks */
+ tmp = readl(SC_CLKCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+ SC_CLKCTRL_CEN_GIO;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+}
diff --git a/arch/arm/mach-uniphier/clk/clk-proxstream2.c b/arch/arm/mach-uniphier/clk/clk-proxstream2.c
new file mode 100644
index 0000000..b494021
--- /dev/null
+++ b/arch/arm/mach-uniphier/clk/clk-proxstream2.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+void proxstream2_clk_init(void)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ tmp = readl(SC_RSTCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_RSTCTRL_NRST_ETHER;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_RSTCTRL_NRST_NAND;
+#endif
+ writel(tmp, SC_RSTCTRL);
+ readl(SC_RSTCTRL); /* dummy read */
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp = readl(SC_RSTCTRL2);
+ tmp |= SC_RSTCTRL2_NRST_USB3B1;
+ writel(tmp, SC_RSTCTRL2);
+ readl(SC_RSTCTRL2); /* dummy read */
+#endif
+
+ /* privide clocks */
+ tmp = readl(SC_CLKCTRL);
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+ SC_CLKCTRL_CEN_GIO;
+#endif
+#ifdef CONFIG_UNIPHIER_ETH
+ tmp |= SC_CLKCTRL_CEN_ETHER;
+#endif
+#ifdef CONFIG_NAND_DENALI
+ tmp |= SC_CLKCTRL_CEN_NAND;
+#endif
+ writel(tmp, SC_CLKCTRL);
+ readl(SC_CLKCTRL); /* dummy read */
+}
diff --git a/arch/arm/mach-uniphier/cmd_pinmon.c b/arch/arm/mach-uniphier/cmd_pinmon.c
index 8be2ed4..b15ee9d 100644
--- a/arch/arm/mach-uniphier/cmd_pinmon.c
+++ b/arch/arm/mach-uniphier/cmd_pinmon.c
@@ -1,6 +1,5 @@
/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -8,20 +7,42 @@
#include <common.h>
#include <mach/boot-device.h>
#include <mach/sbc-regs.h>
+#include <mach/soc_info.h>
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- int mode_sel, i;
-
printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF");
- mode_sel = get_boot_mode_sel();
-
- puts("Boot Mode Pin:\n");
-
- for (i = 0; boot_device_table[i].info; i++)
- printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i,
- boot_device_table[i].info);
+ switch (uniphier_get_soc_type()) {
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+ case SOC_UNIPHIER_PH1_SLD3:
+ ph1_sld3_boot_mode_show();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+ case SOC_UNIPHIER_PH1_LD4:
+ case SOC_UNIPHIER_PH1_PRO4:
+ case SOC_UNIPHIER_PH1_SLD8:
+ ph1_ld4_boot_mode_show();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+ case SOC_UNIPHIER_PH1_PRO5:
+ ph1_pro5_boot_mode_show();
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ case SOC_UNIPHIER_PROXSTREAM2:
+ case SOC_UNIPHIER_PH1_LD6B:
+ proxstream2_boot_mode_show();
+ break;
+#endif
+ default:
+ break;
+ }
return 0;
}
diff --git a/arch/arm/mach-uniphier/ddrphy/Makefile b/arch/arm/mach-uniphier/ddrphy/Makefile
new file mode 100644
index 0000000..e2d109d
--- /dev/null
+++ b/arch/arm/mach-uniphier/ddrphy/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ddrphy-training.o ddrphy-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ddrphy-training.o ddrphy-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ddrphy-training.o ddrphy-ph1-sld8.o
diff --git a/arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c
index 2add8fa..991d929 100644
--- a/arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c
+++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c
@@ -8,7 +8,7 @@
#include <linux/io.h>
#include <mach/ddrphy-regs.h>
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
u32 tmp;
@@ -67,4 +67,6 @@ void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
writel(0x0300C473, &phy->pgcr[1]);
writel(0x0000005D, &phy->zq[0].cr[1]);
+
+ return 0;
}
diff --git a/arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c
index 61ddcf4..bc47ba3 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c
+++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c
@@ -8,7 +8,7 @@
#include <linux/io.h>
#include <mach/ddrphy-regs.h>
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
u32 tmp;
@@ -67,4 +67,6 @@ void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
writel(0x0300C473, &phy->pgcr[1]);
writel(0x0000005D, &phy->zq[0].cr[1]);
+
+ return 0;
}
diff --git a/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c
index 21efe62..39024a0 100644
--- a/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c
+++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c
@@ -9,7 +9,7 @@
#include <linux/io.h>
#include <mach/ddrphy-regs.h>
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
+int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{
u32 tmp;
@@ -72,4 +72,6 @@ void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
writel(0x0300C473, &phy->pgcr[1]);
writel(0x0000005D, &phy->zq[0].cr[1]);
+
+ return 0;
}
diff --git a/arch/arm/mach-uniphier/ddrphy_training.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c
index a98b814..a98b814 100644
--- a/arch/arm/mach-uniphier/ddrphy_training.c
+++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c
diff --git a/arch/arm/mach-uniphier/debug_ll.S b/arch/arm/mach-uniphier/debug_ll.S
new file mode 100644
index 0000000..d8c9fe4
--- /dev/null
+++ b/arch/arm/mach-uniphier/debug_ll.S
@@ -0,0 +1,185 @@
+/*
+ * On-chip UART initializaion for low-level debugging
+ *
+ * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/serial_reg.h>
+#include <linux/linkage.h>
+#include <mach/bcu-regs.h>
+#include <mach/sc-regs.h>
+#include <mach/sg-regs.h>
+
+#if !defined(CONFIG_DEBUG_SEMIHOSTING)
+#include CONFIG_DEBUG_LL_INCLUDE
+#endif
+
+#define BAUDRATE 115200
+#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
+
+ENTRY(debug_ll_init)
+ ldr r0, =SG_REVISION
+ ldr r1, [r0]
+ and r1, r1, #SG_REVISION_TYPE_MASK
+ mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
+
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+#define PH1_SLD3_UART_CLK 36864000
+ cmp r1, #0x25
+ bne ph1_sld3_end
+
+ sg_set_pinsel 64, 1, 4, 4, r0, r1 @ TXD0 -> TXD0
+
+ ldr r0, =BCSCR5
+ ldr r1, =0x24440000
+ str r1, [r0]
+
+ ldr r0, =SC_CLKCTRL
+ ldr r1, [r0]
+ orr r1, r1, #SC_CLKCTRL_CEN_PERI
+ str r1, [r0]
+
+ ldr r3, =DIV_ROUND(PH1_SLD3_UART_CLK, 16 * BAUDRATE)
+
+ b init_uart
+ph1_sld3_end:
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
+#define PH1_LD4_UART_CLK 36864000
+ cmp r1, #0x26
+ bne ph1_ld4_end
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0
+
+ ldr r3, =DIV_ROUND(PH1_LD4_UART_CLK, 16 * BAUDRATE)
+
+ b init_uart
+ph1_ld4_end:
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+#define PH1_PRO4_UART_CLK 73728000
+ cmp r1, #0x28
+ bne ph1_pro4_end
+
+ sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
+
+ ldr r0, =SG_LOADPINCTRL
+ mov r1, #1
+ str r1, [r0]
+
+ ldr r0, =SC_CLKCTRL
+ ldr r1, [r0]
+ orr r1, r1, #SC_CLKCTRL_CEN_PERI
+ str r1, [r0]
+
+ ldr r3, =DIV_ROUND(PH1_PRO4_UART_CLK, 16 * BAUDRATE)
+
+ b init_uart
+ph1_pro4_end:
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+#define PH1_SLD8_UART_CLK 80000000
+ cmp r1, #0x29
+ bne ph1_sld8_end
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0
+
+ ldr r3, =DIV_ROUND(PH1_SLD8_UART_CLK, 16 * BAUDRATE)
+
+ b init_uart
+ph1_sld8_end:
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+#define PH1_PRO5_UART_CLK 73728000
+ cmp r1, #0x2A
+ bne ph1_pro5_end
+
+ sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
+ sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1
+ sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2
+ sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3
+
+ ldr r0, =SG_LOADPINCTRL
+ mov r1, #1
+ str r1, [r0]
+
+ ldr r0, =SC_CLKCTRL
+ ldr r1, [r0]
+ orr r1, r1, #SC_CLKCTRL_CEN_PERI
+ str r1, [r0]
+
+ ldr r3, =DIV_ROUND(PH1_PRO5_UART_CLK, 16 * BAUDRATE)
+
+ b init_uart
+ph1_pro5_end:
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
+#define PROXSTREAM2_UART_CLK 88900000
+ cmp r1, #0x2E
+ bne proxstream2_end
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0
+ sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1
+ sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2
+ sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3
+
+ ldr r0, =SC_CLKCTRL
+ ldr r1, [r0]
+ orr r1, r1, #SC_CLKCTRL_CEN_PERI
+ str r1, [r0]
+
+ ldr r3, =DIV_ROUND(PROXSTREAM2_UART_CLK, 16 * BAUDRATE)
+
+ b init_uart
+proxstream2_end:
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+#define PH1_LD6B_UART_CLK 88900000
+ cmp r1, #0x2F
+ bne ph1_ld6b_end
+
+ ldr r0, =SG_IECTRL
+ ldr r1, [r0]
+ orr r1, r1, #1
+ str r1, [r0]
+
+ sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0
+ sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1
+ sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2
+
+ ldr r0, =SC_CLKCTRL
+ ldr r1, [r0]
+ orr r1, r1, #SC_CLKCTRL_CEN_PERI
+ str r1, [r0]
+
+ ldr r3, =DIV_ROUND(PH1_LD6B_UART_CLK, 16 * BAUDRATE)
+
+ b init_uart
+ph1_ld6b_end:
+#endif
+
+init_uart:
+ addruart r0, r1, r2
+ mov r1, #UART_LCR_WLEN8 << 8
+ str r1, [r0, #0x10]
+ str r3, [r0, #0x24]
+
+ mov pc, lr
+ENDPROC(debug_ll_init)
diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c
index 4b8c938..32cc448 100644
--- a/arch/arm/mach-uniphier/dram_init.c
+++ b/arch/arm/mach-uniphier/dram_init.c
@@ -1,16 +1,59 @@
/*
- * Copyright (C) 2012-2015 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <libfdt.h>
+#include <linux/err.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const void *get_memory_reg_prop(const void *fdt, int *lenp)
+{
+ int offset;
+
+ offset = fdt_path_offset(fdt, "/memory");
+ if (offset < 0)
+ return NULL;
+
+ return fdt_getprop(fdt, offset, "reg", lenp);
+}
int dram_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
- gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ const fdt32_t *val;
+ int len;
+
+ val = get_memory_reg_prop(gd->fdt_blob, &len);
+ if (len < sizeof(*val))
+ return -EINVAL;
+
+ gd->ram_size = fdt32_to_cpu(*(val + 1));
+
+ debug("DRAM size = %08lx\n", gd->ram_size);
return 0;
}
+
+void dram_init_banksize(void)
+{
+ const fdt32_t *val;
+ int len, i;
+
+ val = get_memory_reg_prop(gd->fdt_blob, &len);
+ if (len < 0)
+ return;
+
+ len /= sizeof(*val);
+ len /= 2;
+
+ for (i = 0; i < len; i++) {
+ gd->bd->bi_dram[i].start = fdt32_to_cpu(*val++);
+ gd->bd->bi_dram[i].size = fdt32_to_cpu(*val++);
+
+ debug("DRAM bank %d: start = %08lx, size = %08lx\n",
+ i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);
+ }
+}
diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile
new file mode 100644
index 0000000..393ea96
--- /dev/null
+++ b/arch/arm/mach-uniphier/early-clk/Makefile
@@ -0,0 +1,7 @@
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += early-clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += early-clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += early-clk-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += early-clk-ph1-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += early-clk-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += early-clk-proxstream2.o
diff --git a/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c
index 60204b5..f646c9b 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c
+++ b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c
@@ -7,9 +7,10 @@
#include <common.h>
#include <spl.h>
#include <linux/io.h>
+#include <mach/init.h>
#include <mach/sc-regs.h>
-void early_clkrst_init(void)
+int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd)
{
u32 tmp;
@@ -27,4 +28,6 @@ void early_clkrst_init(void)
tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
+
+ return 0;
}
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c
new file mode 100644
index 0000000..007d3b8
--- /dev/null
+++ b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-pro5.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.m@jp.panasonic.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ /*
+ * deassert reset
+ * UMCA2: Ch1 (DDR3)
+ * UMCA1, UMC31: Ch0 (WIO1)
+ * UMCA0, UMC30: Ch0 (WIO0)
+ */
+ tmp = readl(SC_RSTCTRL4);
+ tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
+ SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
+ SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
+ writel(tmp, SC_RSTCTRL4);
+ readl(SC_RSTCTRL); /* dummy read */
+
+ /* privide clocks */
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
+ writel(tmp, SC_CLKCTRL);
+ tmp = readl(SC_CLKCTRL4);
+ tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
+ SC_CLKCTRL4_CEN_UMC0;
+ writel(tmp, SC_CLKCTRL4);
+ readl(SC_CLKCTRL4); /* dummy read */
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c b/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c
new file mode 100644
index 0000000..c303f16
--- /dev/null
+++ b/arch/arm/mach-uniphier/early-clk/early-clk-proxstream2.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sc-regs.h>
+
+int proxstream2_early_clk_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+
+ /* deassert reset */
+ if (spl_boot_device() != BOOT_DEVICE_NAND) {
+ tmp = readl(SC_RSTCTRL);
+ tmp &= ~SC_RSTCTRL_NRST_NAND;
+ writel(tmp, SC_RSTCTRL);
+ };
+
+ tmp = readl(SC_RSTCTRL4);
+ tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
+ SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
+ SC_RSTCTRL4_NRST_UMC32 | SC_RSTCTRL4_NRST_UMC31 |
+ SC_RSTCTRL4_NRST_UMC30;
+ writel(tmp, SC_RSTCTRL4);
+ readl(SC_RSTCTRL4); /* dummy read */
+
+ /* privide clocks */
+ tmp = readl(SC_CLKCTRL);
+ tmp |= SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
+ writel(tmp, SC_CLKCTRL);
+
+ tmp = readl(SC_CLKCTRL4);
+ tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC2 |
+ SC_CLKCTRL4_CEN_UMC1 | SC_CLKCTRL4_CEN_UMC0;
+ writel(tmp, SC_CLKCTRL4);
+ readl(SC_CLKCTRL4); /* dummy read */
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile
new file mode 100644
index 0000000..e497d28
--- /dev/null
+++ b/arch/arm/mach-uniphier/early-pinctrl/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-pinctrl-ph1-sld3.o
diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c
new file mode 100644
index 0000000..1bb9375
--- /dev/null
+++ b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_UNIPHIER_SERIAL
+ sg_set_pinsel(63, 0, 4, 4); /* RXD0 */
+ sg_set_pinsel(64, 1, 4, 4); /* TXD0 */
+
+ sg_set_pinsel(65, 0, 4, 4); /* RXD1 */
+ sg_set_pinsel(66, 1, 4, 4); /* TXD1 */
+
+ sg_set_pinsel(96, 2, 4, 4); /* RXD2 */
+ sg_set_pinsel(102, 2, 4, 4); /* TXD2 */
+#endif
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/include/mach/board.h b/arch/arm/mach-uniphier/include/mach/board.h
deleted file mode 100644
index e3cba5b..0000000
--- a/arch/arm/mach-uniphier/include/mach/board.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2012-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_BOARD_H
-#define ARCH_BOARD_H
-
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) || \
- defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-void support_card_reset(void);
-void support_card_init(void);
-void support_card_late_init(void);
-int check_support_card(void);
-#else
-#define support_card_reset() do {} while (0)
-#define support_card_init() do {} while (0)
-#define support_card_late_init() do {} while (0)
-static inline int check_support_card(void)
-{
- return 0;
-}
-#endif
-
-static inline void uniphier_board_reset(void)
-{
- support_card_reset();
-}
-
-static inline void uniphier_board_init(void)
-{
- support_card_init();
-}
-
-static inline void uniphier_board_late_init(void)
-{
- support_card_late_init();
-}
-
-#endif /* ARCH_BOARD_H */
diff --git a/arch/arm/mach-uniphier/include/mach/boot-device.h b/arch/arm/mach-uniphier/include/mach/boot-device.h
index 7a10f1c..2ab5a53 100644
--- a/arch/arm/mach-uniphier/include/mach/boot-device.h
+++ b/arch/arm/mach-uniphier/include/mach/boot-device.h
@@ -1,6 +1,5 @@
/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -8,13 +7,19 @@
#ifndef _ASM_BOOT_DEVICE_H_
#define _ASM_BOOT_DEVICE_H_
-int get_boot_mode_sel(void);
-
struct boot_device_info {
u32 type;
char *info;
};
-extern struct boot_device_info boot_device_table[];
+u32 ph1_sld3_boot_device(void);
+u32 ph1_ld4_boot_device(void);
+u32 ph1_pro5_boot_device(void);
+u32 proxstream2_boot_device(void);
+
+void ph1_sld3_boot_mode_show(void);
+void ph1_ld4_boot_mode_show(void);
+void ph1_pro5_boot_mode_show(void);
+void proxstream2_boot_mode_show(void);
#endif /* _ASM_BOOT_DEVICE_H_ */
diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
index fce0c01..adcc972 100644
--- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
@@ -156,7 +156,8 @@ struct ddrphy {
/* SoC-specific parameters */
#define NR_DATX8_PER_DDRPHY 2
-#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
#define NR_DDRPHY_PER_CH 1
#else
#define NR_DDRPHY_PER_CH 2
@@ -167,7 +168,9 @@ struct ddrphy {
#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy))
#ifndef __ASSEMBLY__
-void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
+int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size);
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank);
int ddrphy_training(struct ddrphy __iomem *phy);
#endif
diff --git a/arch/arm/mach-uniphier/include/mach/debug-uart.S b/arch/arm/mach-uniphier/include/mach/debug-uart.S
deleted file mode 100644
index d2b431f..0000000
--- a/arch/arm/mach-uniphier/include/mach/debug-uart.S
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/serial_reg.h>
-
-#if !defined(CONFIG_DEBUG_SEMIHOSTING)
-#include CONFIG_DEBUG_LL_INCLUDE
-#endif
-
-#define BAUDRATE 115200
-#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
-#define DIVISOR DIV_ROUND(UART_CLK, 16 * BAUDRATE)
-
- .macro init_debug_uart, ra, rb, rc
- addruart \ra, \rb, \rc
- mov \rb, #UART_LCR_WLEN8 << 8
- str \rb, [\ra, #0x10]
- ldr \rb, =DIVISOR
- str \rb, [\ra, #0x24]
- .endm
diff --git a/arch/arm/mach-uniphier/include/mach/init.h b/arch/arm/mach-uniphier/include/mach/init.h
new file mode 100644
index 0000000..5108edd
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/init.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MACH_INIT_H
+#define __MACH_INIT_H
+
+struct uniphier_board_data {
+ unsigned long dram_ch0_base;
+ unsigned long dram_ch0_size;
+ unsigned long dram_ch0_width;
+ unsigned long dram_ch1_base;
+ unsigned long dram_ch1_size;
+ unsigned long dram_ch1_width;
+ unsigned long dram_ch2_base;
+ unsigned long dram_ch2_size;
+ unsigned long dram_ch2_width;
+ unsigned int dram_freq;
+};
+
+const struct uniphier_board_data *uniphier_get_board_param(const void *fdt);
+
+int ph1_sld3_init(const struct uniphier_board_data *bd);
+int ph1_ld4_init(const struct uniphier_board_data *bd);
+int ph1_pro4_init(const struct uniphier_board_data *bd);
+int ph1_sld8_init(const struct uniphier_board_data *bd);
+int ph1_pro5_init(const struct uniphier_board_data *bd);
+int proxstream2_init(const struct uniphier_board_data *bd);
+
+#if defined(CONFIG_MICRO_SUPPORT_CARD)
+int ph1_sld3_sbc_init(const struct uniphier_board_data *bd);
+int ph1_ld4_sbc_init(const struct uniphier_board_data *bd);
+int ph1_pro4_sbc_init(const struct uniphier_board_data *bd);
+int proxstream2_sbc_init(const struct uniphier_board_data *bd);
+#else
+static inline int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+
+static inline int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+
+static inline int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+
+static inline int proxstream2_sbc_init(const struct uniphier_board_data *bd)
+{
+ return 0;
+}
+#endif
+
+int ph1_sld3_bcu_init(const struct uniphier_board_data *bd);
+int ph1_ld4_bcu_init(const struct uniphier_board_data *bd);
+
+int memconf_init(const struct uniphier_board_data *bd);
+int ph1_sld3_memconf_init(const struct uniphier_board_data *bd);
+int proxstream2_memconf_init(const struct uniphier_board_data *bd);
+
+int ph1_sld3_pll_init(const struct uniphier_board_data *bd);
+int ph1_ld4_pll_init(const struct uniphier_board_data *bd);
+int ph1_pro4_pll_init(const struct uniphier_board_data *bd);
+int ph1_sld8_pll_init(const struct uniphier_board_data *bd);
+
+int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd);
+int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd);
+
+int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd);
+int ph1_pro5_early_clk_init(const struct uniphier_board_data *bd);
+int proxstream2_early_clk_init(const struct uniphier_board_data *bd);
+
+int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd);
+
+int ph1_ld4_umc_init(const struct uniphier_board_data *bd);
+int ph1_pro4_umc_init(const struct uniphier_board_data *bd);
+int ph1_sld8_umc_init(const struct uniphier_board_data *bd);
+
+void ph1_sld3_pin_init(void);
+void ph1_ld4_pin_init(void);
+void ph1_pro4_pin_init(void);
+void ph1_sld8_pin_init(void);
+void ph1_pro5_pin_init(void);
+void proxstream2_pin_init(void);
+void ph1_ld6b_pin_init(void);
+
+void ph1_ld4_clk_init(void);
+void ph1_pro4_clk_init(void);
+void ph1_pro5_clk_init(void);
+void proxstream2_clk_init(void);
+
+#define pr_err(fmt, args...) printf(fmt, ##args)
+
+#endif /* __MACH_INIT_H */
diff --git a/arch/arm/mach-uniphier/include/mach/led.h b/arch/arm/mach-uniphier/include/mach/led.h
deleted file mode 100644
index f7749b4..0000000
--- a/arch/arm/mach-uniphier/include/mach/led.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_LED_H
-#define ARCH_LED_H
-
-#include <config.h>
-
-#define LED_CHAR_0 0x7e
-#define LED_CHAR_1 0x0c
-#define LED_CHAR_2 0xb6
-#define LED_CHAR_3 0x9e
-#define LED_CHAR_4 0xcc
-#define LED_CHAR_5 0xda
-#define LED_CHAR_6 0xfa
-#define LED_CHAR_7 0x4e
-#define LED_CHAR_8 0xfe
-#define LED_CHAR_9 0xde
-
-#define LED_CHAR_A 0xee
-#define LED_CHAR_B 0xf8
-#define LED_CHAR_C 0x72
-#define LED_CHAR_D 0xbc
-#define LED_CHAR_E 0xf2
-#define LED_CHAR_F 0xe2
-#define LED_CHAR_G 0x7a
-#define LED_CHAR_H 0xe8
-#define LED_CHAR_I 0x08
-#define LED_CHAR_J 0x3c
-#define LED_CHAR_K 0xea
-#define LED_CHAR_L 0x70
-#define LED_CHAR_M 0x6e
-#define LED_CHAR_N 0xa8
-#define LED_CHAR_O 0xb8
-#define LED_CHAR_P 0xe6
-#define LED_CHAR_Q 0xce
-#define LED_CHAR_R 0xa0
-#define LED_CHAR_S 0xc8
-#define LED_CHAR_T 0x8c
-#define LED_CHAR_U 0x7c
-#define LED_CHAR_V 0x54
-#define LED_CHAR_W 0xfc
-#define LED_CHAR_X 0xec
-#define LED_CHAR_Y 0xdc
-#define LED_CHAR_Z 0xa4
-
-#define LED_CHAR_SPACE 0x00
-#define LED_CHAR_DOT 0x01
-
-#define LED_CHAR_ (LED_CHAR_SPACE)
-
-/** Macro to translate 4 characters into integer to display led */
-#define LED_C2I(C0, C1, C2, C3) \
- (~( \
- (LED_CHAR_##C0 << 24) | \
- (LED_CHAR_##C1 << 16) | \
- (LED_CHAR_##C2 << 8) | \
- (LED_CHAR_##C3) \
- ))
-
-#if defined(CONFIG_SUPPORT_CARD_LED_BASE)
-
-#define LED_ADDR CONFIG_SUPPORT_CARD_LED_BASE
-
-#ifdef __ASSEMBLY__
-
-#define led_write(C0, C1, C2, C3) raw_led_write LED_C2I(C0, C1, C2, C3)
-.macro raw_led_write data
- ldr r0, =\data
- ldr r1, =LED_ADDR
- str r0, [r1]
-.endm
-
-#else /* __ASSEMBLY__ */
-
-#include <linux/io.h>
-
-#define led_write(C0, C1, C2, C3) \
-do { \
- raw_led_write(LED_C2I(C0, C1, C2, C3)); \
-} while (0)
-
-static inline void raw_led_write(u32 data)
-{
- writel(data, LED_ADDR);
-}
-
-#endif /* __ASSEMBLY__ */
-
-#else /* CONFIG_SUPPORT_CARD_LED_BASE */
-
-#define led_write(C0, C1, C2, C3)
-#define raw_led_write(x)
-
-#endif /* CONFIG_SUPPORT_CARD_LED_BASE */
-
-#endif /* ARCH_LED_H */
diff --git a/arch/arm/mach-uniphier/include/mach/micro-support-card.h b/arch/arm/mach-uniphier/include/mach/micro-support-card.h
new file mode 100644
index 0000000..5da0ada
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/micro-support-card.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef ARCH_BOARD_H
+#define ARCH_BOARD_H
+
+#if defined(CONFIG_MICRO_SUPPORT_CARD)
+void support_card_reset(void);
+void support_card_init(void);
+void support_card_late_init(void);
+int check_support_card(void);
+void led_puts(const char *s);
+#else
+static inline void support_card_reset(void)
+{
+}
+
+static inline void support_card_init(void)
+{
+}
+
+static inline void support_card_late_init(void)
+{
+}
+
+static inline int check_support_card(void)
+{
+ return 0;
+}
+
+static inline void led_puts(const char *s)
+{
+}
+#endif
+
+#endif /* ARCH_BOARD_H */
diff --git a/arch/arm/mach-uniphier/include/mach/platdevice.h b/arch/arm/mach-uniphier/include/mach/platdevice.h
deleted file mode 100644
index cdf7d13..0000000
--- a/arch/arm/mach-uniphier/include/mach/platdevice.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef ARCH_PLATDEVICE_H
-#define ARCH_PLATDEVICE_H
-
-#include <dm/platdata.h>
-#include <dm/platform_data/serial-uniphier.h>
-
-#define SERIAL_DEVICE(n, ba, clk) \
-static struct uniphier_serial_platform_data serial_device##n = { \
- .base = ba, \
- .uartclk = clk \
-}; \
-U_BOOT_DEVICE(serial##n) = { \
- .name = DRIVER_NAME, \
- .platdata = &serial_device##n \
-};
-
-#endif /* ARCH_PLATDEVICE_H */
diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h
index df50294..474b82d 100644
--- a/arch/arm/mach-uniphier/include/mach/sc-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h
@@ -9,12 +9,16 @@
#ifndef ARCH_SC_REGS_H
#define ARCH_SC_REGS_H
-#if defined(CONFIG_MACH_PH1_SLD3)
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
#define SC_BASE_ADDR 0xf1840000
#else
#define SC_BASE_ADDR 0x61840000
#endif
+#define SC_DPLLOSCCTRL (SC_BASE_ADDR | 0x1110)
+#define SC_DPLLOSCCTRL_DPLLST (0x1 << 1)
+#define SC_DPLLOSCCTRL_DPLLEN (0x1 << 0)
+
#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
@@ -43,6 +47,7 @@
#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
#define SC_RSTCTRL_NRST_STDMAC (0x1 << 10)
#define SC_RSTCTRL_NRST_GIO (0x1 << 6)
+/* Pro4 or older */
#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
@@ -53,6 +58,16 @@
#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
+/* Pro5 or newer */
+#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
+#define SC_RSTCTRL4_NRST_UMCSB (0x1 << 12) /* UMC system bus */
+#define SC_RSTCTRL4_NRST_UMCA2 (0x1 << 10) /* UMC ch2 standby */
+#define SC_RSTCTRL4_NRST_UMCA1 (0x1 << 9) /* UMC ch1 standby */
+#define SC_RSTCTRL4_NRST_UMCA0 (0x1 << 8) /* UMC ch0 standby */
+#define SC_RSTCTRL4_NRST_UMC32 (0x1 << 6) /* UMC ch2 */
+#define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */
+#define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */
+
#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
#define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */
#define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */
@@ -60,11 +75,19 @@
#define SC_CLKCTRL_CEN_MIO (0x1 << 11)
#define SC_CLKCTRL_CEN_STDMAC (0x1 << 10)
#define SC_CLKCTRL_CEN_GIO (0x1 << 6)
+/* Pro4 or older */
#define SC_CLKCTRL_CEN_UMC (0x1 << 4)
#define SC_CLKCTRL_CEN_NAND (0x1 << 2)
#define SC_CLKCTRL_CEN_SBC (0x1 << 1)
#define SC_CLKCTRL_CEN_PERI (0x1 << 0)
+/* Pro5 or newer */
+#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
+#define SC_CLKCTRL4_CEN_UMCSB (0x1 << 12) /* UMC system bus */
+#define SC_CLKCTRL4_CEN_UMC2 (0x1 << 2) /* UMC ch2 */
+#define SC_CLKCTRL4_CEN_UMC1 (0x1 << 1) /* UMC ch1 */
+#define SC_CLKCTRL4_CEN_UMC0 (0x1 << 0) /* UMC ch0 */
+
/* System reset control register */
#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)
#define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010)
diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h b/arch/arm/mach-uniphier/include/mach/sg-regs.h
index 43a6c35..678d437 100644
--- a/arch/arm/mach-uniphier/include/mach/sg-regs.h
+++ b/arch/arm/mach-uniphier/include/mach/sg-regs.h
@@ -25,53 +25,43 @@
/* Memory Configuration */
#define SG_MEMCONF (SG_CTRL_BASE | 0x0400)
+#define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0))
#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0))
#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0))
#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0))
#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0))
+#define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
+#define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2))
#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2))
#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2))
#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2))
#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2))
+#define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
+#define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16))
#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16))
#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16))
#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16))
#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16))
+#define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
+/* PH1-LD6b, ProXstream2 only */
+#define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
/* Pin Control */
#define SG_PINCTRL_BASE (SG_CTRL_BASE | 0x1000)
-#if defined(CONFIG_MACH_PH1_PRO4)
-# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 8)
-#elif defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \
- defined(CONFIG_MACH_PH1_SLD8)
-# define SG_PINCTRL(n) (SG_PINCTRL_BASE + (n) * 4)
-#endif
-
-#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_PRO4)
-#define SG_PINSELBITS 4
-#elif defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8)
-#define SG_PINSELBITS 8
-#endif
-
-#define SG_PINSEL_ADDR(n) (SG_PINCTRL((n) * (SG_PINSELBITS) / 32))
-#define SG_PINSEL_MASK(n) (~(((1 << (SG_PINSELBITS)) - 1) << \
- ((n) * (SG_PINSELBITS) % 32)))
-#define SG_PINSEL_MODE(n, mode) ((mode) << ((n) * (SG_PINSELBITS) % 32))
-
-/* Only for PH1-Pro4 */
+/* PH1-Pro4, PH1-Pro5 */
#define SG_LOADPINCTRL (SG_CTRL_BASE | 0x1700)
/* Input Enable */
@@ -98,11 +88,11 @@
#ifdef __ASSEMBLY__
- .macro set_pinsel, n, value, ra, rd
- ldr \ra, =SG_PINSEL_ADDR(\n)
+ .macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
+ ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
ldr \rd, [\ra]
- and \rd, \rd, #SG_PINSEL_MASK(\n)
- orr \rd, \rd, #SG_PINSEL_MODE(\n, \value)
+ and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
+ orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
str \rd, [\ra]
.endm
@@ -111,10 +101,18 @@
#include <linux/types.h>
#include <linux/io.h>
-static inline void sg_set_pinsel(int n, int value)
+static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
+ unsigned mux_bits, unsigned reg_stride)
{
- writel((readl(SG_PINSEL_ADDR(n)) & SG_PINSEL_MASK(n))
- | SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
+ unsigned shift = pin * mux_bits % 32;
+ unsigned reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
+ u32 mask = (1U << mux_bits) - 1;
+ u32 tmp;
+
+ tmp = readl(reg);
+ tmp &= ~(mask << shift);
+ tmp |= (mask & muxval) << shift;
+ writel(tmp, reg);
}
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-uniphier/include/mach/soc_info.h b/arch/arm/mach-uniphier/include/mach/soc_info.h
new file mode 100644
index 0000000..623e7ef
--- /dev/null
+++ b/arch/arm/mach-uniphier/include/mach/soc_info.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __MACH_SOC_INFO_H__
+#define __MACH_SOC_INFO_H__
+
+enum uniphier_soc_id {
+ SOC_UNIPHIER_PH1_SLD3,
+ SOC_UNIPHIER_PH1_LD4,
+ SOC_UNIPHIER_PH1_PRO4,
+ SOC_UNIPHIER_PH1_SLD8,
+ SOC_UNIPHIER_PH1_PRO5,
+ SOC_UNIPHIER_PROXSTREAM2,
+ SOC_UNIPHIER_PH1_LD6B,
+ SOC_UNIPHIER_UNKNOWN,
+};
+
+#define UNIPHIER_NR_ENABLED_SOCS \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD4) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + \
+ IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+
+#define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1)
+
+#if UNIPHIER_MULTI_SOC
+enum uniphier_soc_id uniphier_get_soc_type(void);
+#else
+static inline enum uniphier_soc_id uniphier_get_soc_type(void)
+{
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+ return SOC_UNIPHIER_PH1_SLD3;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
+ return SOC_UNIPHIER_PH1_LD4;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+ return SOC_UNIPHIER_PH1_PRO4;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+ return SOC_UNIPHIER_PH1_SLD8;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+ return SOC_UNIPHIER_PH1_PRO5;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
+ return SOC_UNIPHIER_PROXSTREAM2;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ return SOC_UNIPHIER_PH1_LD6B;
+#endif
+
+ return SOC_UNIPHIER_UNKNOWN;
+}
+#endif
+
+#endif /* __MACH_SOC_INFO_H__ */
diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile
new file mode 100644
index 0000000..98833b5
--- /dev/null
+++ b/arch/arm/mach-uniphier/init/Makefile
@@ -0,0 +1,9 @@
+obj-y += init.o
+
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += init-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += init-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += init-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += init-ph1-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += init-ph1-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += init-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += init-proxstream2.o
diff --git a/arch/arm/mach-uniphier/init/init-ph1-ld4.c b/arch/arm/mach-uniphier/init/init-ph1-ld4.c
new file mode 100644
index 0000000..8d0ef03
--- /dev/null
+++ b/arch/arm/mach-uniphier/init/init-ph1-ld4.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+
+int ph1_ld4_init(const struct uniphier_board_data *bd)
+{
+ ph1_ld4_bcu_init(bd);
+
+ ph1_ld4_sbc_init(bd);
+
+ support_card_reset();
+
+ ph1_ld4_pll_init(bd);
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+
+ led_puts("L1");
+
+ ph1_ld4_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ {
+ int res;
+
+ res = ph1_ld4_umc_init(bd);
+ if (res < 0) {
+ while (1)
+ ;
+ }
+ }
+
+ led_puts("L5");
+
+ ph1_ld4_enable_dpll_ssc(bd);
+
+ led_puts("L6");
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/init/init-ph1-pro4.c b/arch/arm/mach-uniphier/init/init-ph1-pro4.c
new file mode 100644
index 0000000..b9ce08d
--- /dev/null
+++ b/arch/arm/mach-uniphier/init/init-ph1-pro4.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+
+int ph1_pro4_init(const struct uniphier_board_data *bd)
+{
+ ph1_pro4_sbc_init(bd);
+
+ support_card_reset();
+
+ ph1_pro4_pll_init(bd);
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+
+ led_puts("L1");
+
+ ph1_ld4_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ {
+ int res;
+
+ res = ph1_pro4_umc_init(bd);
+ if (res < 0) {
+ while (1)
+ ;
+ }
+ }
+
+ led_puts("L5");
+
+ ph1_ld4_enable_dpll_ssc(bd);
+
+ led_puts("L6");
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/init/init-ph1-pro5.c b/arch/arm/mach-uniphier/init/init-ph1-pro5.c
new file mode 100644
index 0000000..92b3f21
--- /dev/null
+++ b/arch/arm/mach-uniphier/init/init-ph1-pro5.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+
+int ph1_pro5_init(const struct uniphier_board_data *bd)
+{
+ ph1_pro4_sbc_init(bd);
+
+ support_card_reset();
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+
+ led_puts("L1");
+
+ ph1_pro5_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ led_puts("L5");
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/init/init-ph1-sld3.c b/arch/arm/mach-uniphier/init/init-ph1-sld3.c
new file mode 100644
index 0000000..1146fda
--- /dev/null
+++ b/arch/arm/mach-uniphier/init/init-ph1-sld3.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+
+int ph1_sld3_init(const struct uniphier_board_data *bd)
+{
+ ph1_sld3_bcu_init(bd);
+
+ ph1_sld3_sbc_init(bd);
+
+ support_card_reset();
+
+ ph1_sld3_pll_init(bd);
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+ ph1_sld3_memconf_init(bd);
+
+ led_puts("L1");
+
+ ph1_ld4_early_clk_init(bd);
+
+ led_puts("L2");
+
+ ph1_sld3_early_pin_init(bd);
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ led_puts("L5");
+
+ ph1_sld3_enable_dpll_ssc(bd);
+
+ led_puts("L6");
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/init/init-ph1-sld8.c b/arch/arm/mach-uniphier/init/init-ph1-sld8.c
new file mode 100644
index 0000000..741e88c
--- /dev/null
+++ b/arch/arm/mach-uniphier/init/init-ph1-sld8.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2013-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+
+int ph1_sld8_init(const struct uniphier_board_data *bd)
+{
+ ph1_ld4_bcu_init(bd);
+
+ ph1_ld4_sbc_init(bd);
+
+ support_card_reset();
+
+ ph1_sld8_pll_init(bd);
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+
+ led_puts("L1");
+
+ ph1_ld4_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ {
+ int res;
+
+ res = ph1_sld8_umc_init(bd);
+ if (res < 0) {
+ while (1)
+ ;
+ }
+ }
+
+ led_puts("L5");
+
+ ph1_ld4_enable_dpll_ssc(bd);
+
+ led_puts("L6");
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/init/init-proxstream2.c b/arch/arm/mach-uniphier/init/init-proxstream2.c
new file mode 100644
index 0000000..8d03b8f
--- /dev/null
+++ b/arch/arm/mach-uniphier/init/init-proxstream2.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <linux/compiler.h>
+#include <mach/init.h>
+#include <mach/micro-support-card.h>
+
+int proxstream2_init(const struct uniphier_board_data *bd)
+{
+ proxstream2_sbc_init(bd);
+
+ support_card_reset();
+
+ support_card_init();
+
+ led_puts("L0");
+
+ memconf_init(bd);
+ proxstream2_memconf_init(bd);
+
+ led_puts("L1");
+
+ proxstream2_early_clk_init(bd);
+
+ led_puts("L2");
+
+ led_puts("L3");
+
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
+ preloader_console_init();
+#endif
+
+ led_puts("L4");
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c
new file mode 100644
index 0000000..bbfc8e5
--- /dev/null
+++ b/arch/arm/mach-uniphier/init/init.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <mach/init.h>
+#include <mach/soc_info.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void spl_board_init(void)
+{
+ const struct uniphier_board_data *param;
+
+ param = uniphier_get_board_param(gd->fdt_blob);
+ if (!param)
+ hang();
+
+ switch (uniphier_get_soc_type()) {
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
+ case SOC_UNIPHIER_PH1_SLD3:
+ ph1_sld3_init(param);
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
+ case SOC_UNIPHIER_PH1_LD4:
+ ph1_ld4_init(param);
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+ case SOC_UNIPHIER_PH1_PRO4:
+ ph1_pro4_init(param);
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
+ case SOC_UNIPHIER_PH1_SLD8:
+ ph1_sld8_init(param);
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
+ case SOC_UNIPHIER_PH1_PRO5:
+ ph1_pro5_init(param);
+ break;
+#endif
+#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) || \
+ defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
+ case SOC_UNIPHIER_PROXSTREAM2:
+ case SOC_UNIPHIER_PH1_LD6B:
+ proxstream2_init(param);
+ break;
+#endif
+ default:
+ break;
+ }
+}
diff --git a/arch/arm/mach-uniphier/init_page_table.S b/arch/arm/mach-uniphier/init_page_table.S
index ac2959a..2d3ad15 100644
--- a/arch/arm/mach-uniphier/init_page_table.S
+++ b/arch/arm/mach-uniphier/init_page_table.S
@@ -1,7 +1,5 @@
/*
- * Copyright (C) 2015 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -23,7 +21,7 @@
ENTRY(init_page_table)
section = 0
.rept NR_SECTIONS
- .if section == TEXT_SECTION || section == STACK_SECTION
+ .if section == 0 || section == 1 || section == STACK_SECTION
attr = NORMAL
.else
attr = DEVICE
diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S
index fd34a4a..66cad42 100644
--- a/arch/arm/mach-uniphier/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/lowlevel_init.S
@@ -8,7 +8,6 @@
#include <linux/linkage.h>
#include <linux/sizes.h>
#include <asm/system.h>
-#include <mach/led.h>
#include <mach/arm-mpcore.h>
#include <mach/sbc-regs.h>
#include <mach/ssc-regs.h>
@@ -28,7 +27,7 @@ ENTRY(lowlevel_init)
mcr p15, 0, r0, c1, c0, 0
#ifdef CONFIG_DEBUG_LL
- bl setup_lowlevel_debug
+ bl debug_ll_init
#endif
/*
diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c
deleted file mode 100644
index 59ed0b5..0000000
--- a/arch/arm/mach-uniphier/memconf.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/sizes.h>
-#include <linux/io.h>
-#include <mach/sg-regs.h>
-
-static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
-{
- int size_mb = size / num;
- u32 ret;
-
- switch (size_mb) {
- case SZ_64M:
- ret = SG_MEMCONF_CH0_SZ_64M;
- break;
- case SZ_128M:
- ret = SG_MEMCONF_CH0_SZ_128M;
- break;
- case SZ_256M:
- ret = SG_MEMCONF_CH0_SZ_256M;
- break;
- case SZ_512M:
- ret = SG_MEMCONF_CH0_SZ_512M;
- break;
- case SZ_1G:
- ret = SG_MEMCONF_CH0_SZ_1G;
- break;
- default:
- BUG();
- break;
- }
-
- switch (num) {
- case 1:
- ret |= SG_MEMCONF_CH0_NUM_1;
- break;
- case 2:
- ret |= SG_MEMCONF_CH0_NUM_2;
- break;
- default:
- BUG();
- break;
- }
- return ret;
-}
-
-static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
-{
- int size_mb = size / num;
- u32 ret;
-
- switch (size_mb) {
- case SZ_64M:
- ret = SG_MEMCONF_CH1_SZ_64M;
- break;
- case SZ_128M:
- ret = SG_MEMCONF_CH1_SZ_128M;
- break;
- case SZ_256M:
- ret = SG_MEMCONF_CH1_SZ_256M;
- break;
- case SZ_512M:
- ret = SG_MEMCONF_CH1_SZ_512M;
- break;
- case SZ_1G:
- ret = SG_MEMCONF_CH1_SZ_1G;
- break;
- default:
- BUG();
- break;
- }
-
- switch (num) {
- case 1:
- ret |= SG_MEMCONF_CH1_NUM_1;
- break;
- case 2:
- ret |= SG_MEMCONF_CH1_NUM_2;
- break;
- default:
- BUG();
- break;
- }
- return ret;
-}
-
-void memconf_init(void)
-{
- u32 tmp;
-
- /* Set DDR size */
- tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
- tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
-#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
- tmp |= SG_MEMCONF_SPARSEMEM;
-#endif
- writel(tmp, SG_MEMCONF);
-}
diff --git a/arch/arm/mach-uniphier/memconf/Makefile b/arch/arm/mach-uniphier/memconf/Makefile
new file mode 100644
index 0000000..42057a2
--- /dev/null
+++ b/arch/arm/mach-uniphier/memconf/Makefile
@@ -0,0 +1,4 @@
+obj-y += memconf.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += memconf-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += memconf-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += memconf-proxstream2.o
diff --git a/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c
new file mode 100644
index 0000000..e13f56d1
--- /dev/null
+++ b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+int ph1_sld3_memconf_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+ unsigned long size_per_word;
+
+ tmp = readl(SG_MEMCONF);
+
+ tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
+
+ switch (bd->dram_ch2_width) {
+ case 16:
+ tmp |= SG_MEMCONF_CH2_NUM_1;
+ size_per_word = bd->dram_ch2_size;
+ break;
+ case 32:
+ tmp |= SG_MEMCONF_CH2_NUM_2;
+ size_per_word = bd->dram_ch2_size >> 1;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch2 width\n");
+ return -EINVAL;
+ }
+
+ /* Set DDR size */
+ switch (size_per_word) {
+ case SZ_64M:
+ tmp |= SG_MEMCONF_CH2_SZ_64M;
+ break;
+ case SZ_128M:
+ tmp |= SG_MEMCONF_CH2_SZ_128M;
+ break;
+ case SZ_256M:
+ tmp |= SG_MEMCONF_CH2_SZ_256M;
+ break;
+ case SZ_512M:
+ tmp |= SG_MEMCONF_CH2_SZ_512M;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch2 size\n");
+ return -EINVAL;
+ }
+
+ writel(tmp, SG_MEMCONF);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c
new file mode 100644
index 0000000..d7bf0d4
--- /dev/null
+++ b/arch/arm/mach-uniphier/memconf/memconf-proxstream2.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+int proxstream2_memconf_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp;
+ unsigned long size_per_word;
+
+ tmp = readl(SG_MEMCONF);
+
+ tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK);
+
+ switch (bd->dram_ch2_width) {
+ case 16:
+ tmp |= SG_MEMCONF_CH2_NUM_1;
+ size_per_word = bd->dram_ch2_size;
+ break;
+ case 32:
+ tmp |= SG_MEMCONF_CH2_NUM_2;
+ size_per_word = bd->dram_ch2_size >> 1;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch2 width\n");
+ return -EINVAL;
+ }
+
+ /* Set DDR size */
+ switch (size_per_word) {
+ case SZ_64M:
+ tmp |= SG_MEMCONF_CH2_SZ_64M;
+ break;
+ case SZ_128M:
+ tmp |= SG_MEMCONF_CH2_SZ_128M;
+ break;
+ case SZ_256M:
+ tmp |= SG_MEMCONF_CH2_SZ_256M;
+ break;
+ case SZ_512M:
+ tmp |= SG_MEMCONF_CH2_SZ_512M;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch2 size\n");
+ return -EINVAL;
+ }
+
+ if (size_per_word)
+ tmp &= ~SG_MEMCONF_CH2_DISABLE;
+ else
+ tmp |= SG_MEMCONF_CH2_DISABLE;
+
+ writel(tmp, SG_MEMCONF);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/memconf/memconf.c b/arch/arm/mach-uniphier/memconf/memconf.c
new file mode 100644
index 0000000..d490736
--- /dev/null
+++ b/arch/arm/mach-uniphier/memconf/memconf.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+int memconf_init(const struct uniphier_board_data *bd)
+{
+ u32 tmp = 0;
+ unsigned long size_per_word;
+
+ tmp = readl(SG_MEMCONF);
+
+ tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK);
+
+ switch (bd->dram_ch0_width) {
+ case 16:
+ tmp |= SG_MEMCONF_CH0_NUM_1;
+ size_per_word = bd->dram_ch0_size;
+ break;
+ case 32:
+ tmp |= SG_MEMCONF_CH0_NUM_2;
+ size_per_word = bd->dram_ch0_size >> 1;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch0 width\n");
+ return -EINVAL;
+ }
+
+ /* Set DDR size */
+ switch (size_per_word) {
+ case SZ_64M:
+ tmp |= SG_MEMCONF_CH0_SZ_64M;
+ break;
+ case SZ_128M:
+ tmp |= SG_MEMCONF_CH0_SZ_128M;
+ break;
+ case SZ_256M:
+ tmp |= SG_MEMCONF_CH0_SZ_256M;
+ break;
+ case SZ_512M:
+ tmp |= SG_MEMCONF_CH0_SZ_512M;
+ break;
+ case SZ_1G:
+ tmp |= SG_MEMCONF_CH0_SZ_1G;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch0 size\n");
+ return -EINVAL;
+ }
+
+ tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK);
+
+ switch (bd->dram_ch1_width) {
+ case 16:
+ tmp |= SG_MEMCONF_CH1_NUM_1;
+ size_per_word = bd->dram_ch1_size;
+ break;
+ case 32:
+ tmp |= SG_MEMCONF_CH1_NUM_2;
+ size_per_word = bd->dram_ch1_size >> 1;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch1 width\n");
+ return -EINVAL;
+ }
+
+ switch (size_per_word) {
+ case SZ_64M:
+ tmp |= SG_MEMCONF_CH1_SZ_64M;
+ break;
+ case SZ_128M:
+ tmp |= SG_MEMCONF_CH1_SZ_128M;
+ break;
+ case SZ_256M:
+ tmp |= SG_MEMCONF_CH1_SZ_256M;
+ break;
+ case SZ_512M:
+ tmp |= SG_MEMCONF_CH1_SZ_512M;
+ break;
+ case SZ_1G:
+ tmp |= SG_MEMCONF_CH1_SZ_1G;
+ break;
+ default:
+ pr_err("error: unsupported DRAM Ch1 size\n");
+ return -EINVAL;
+ }
+
+ if (bd->dram_ch0_base + bd->dram_ch0_size < bd->dram_ch1_base)
+ tmp |= SG_MEMCONF_SPARSEMEM;
+ else
+ tmp &= ~SG_MEMCONF_SPARSEMEM;
+
+ writel(tmp, SG_MEMCONF);
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/support_card.c b/arch/arm/mach-uniphier/micro-support-card.c
index ea85b20..4c34748 100644
--- a/arch/arm/mach-uniphier/support_card.c
+++ b/arch/arm/mach-uniphier/micro-support-card.c
@@ -5,15 +5,17 @@
*/
#include <common.h>
+#include <linux/ctype.h>
#include <linux/io.h>
-#include <mach/board.h>
+#include <mach/micro-support-card.h>
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
+#define MICRO_SUPPORT_CARD_BASE 0x43f00000
+#define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000)
+#define LED_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x90000)
+#define NS16550A_BASE ((MICRO_SUPPORT_CARD_BASE) + 0xb0000)
+#define MICRO_SUPPORT_CARD_RESET ((MICRO_SUPPORT_CARD_BASE) + 0xd0034)
+#define MICRO_SUPPORT_CARD_REVISION ((MICRO_SUPPORT_CARD_BASE) + 0xd00E0)
-#define PFC_MICRO_SUPPORT_CARD_RESET \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034)
-#define PFC_MICRO_SUPPORT_CARD_REVISION \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0)
/*
* 0: reset deassert, 1: reset
*
@@ -22,65 +24,22 @@
*/
void support_card_reset_deassert(void)
{
- writel(0, PFC_MICRO_SUPPORT_CARD_RESET);
+ writel(0, MICRO_SUPPORT_CARD_RESET);
}
void support_card_reset(void)
{
- writel(3, PFC_MICRO_SUPPORT_CARD_RESET);
+ writel(3, MICRO_SUPPORT_CARD_RESET);
}
static int support_card_show_revision(void)
{
u32 revision;
- revision = readl(PFC_MICRO_SUPPORT_CARD_REVISION);
- printf("(PFC CPLD version %d.%d)\n", revision >> 4, revision & 0xf);
+ revision = readl(MICRO_SUPPORT_CARD_REVISION);
+ printf("(CPLD version %d.%d)\n", revision >> 4, revision & 0xf);
return 0;
}
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-
-#define DCC_MICRO_SUPPORT_CARD_RESET_LAN \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x00401300)
-#define DCC_MICRO_SUPPORT_CARD_RESET_UART \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x00401304)
-#define DCC_MICRO_SUPPORT_CARD_RESET_I2C \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x00401308)
-#define DCC_MICRO_SUPPORT_CARD_REVISION \
- ((CONFIG_SUPPORT_CARD_BASE) + 0x005000E0)
-
-void support_card_reset_deassert(void)
-{
- writel(1, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
- writel(1, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
- writel(1, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
-}
-
-void support_card_reset(void)
-{
- writel(0, DCC_MICRO_SUPPORT_CARD_RESET_LAN); /* LAN and LED */
- writel(0, DCC_MICRO_SUPPORT_CARD_RESET_UART); /* UART */
- writel(0, DCC_MICRO_SUPPORT_CARD_RESET_I2C); /* I2C */
-}
-
-static int support_card_show_revision(void)
-{
- u32 revision;
-
- revision = readl(DCC_MICRO_SUPPORT_CARD_REVISION);
-
- if (revision >= 0x67) {
- printf("(DCC CPLD version 3.%d.%d)\n",
- revision >> 4, revision & 0xf);
- return 0;
- } else {
- printf("(DCC CPLD unknown version)\n");
- return -1;
- }
-}
-#endif
int check_support_card(void)
{
@@ -104,7 +63,7 @@ void support_card_init(void)
int board_eth_init(bd_t *bis)
{
- return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+ return smc911x_initialize(0, SMC911X_BASE);
}
#endif
@@ -146,27 +105,10 @@ static int mem_is_flash(const struct memory_bank *mem)
return ret;
}
-#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
- /* {address, size} */
-static const struct memory_bank memory_banks_boot_swap_off[] = {
- {0x02000000, 0x01f00000},
-};
-
-static const struct memory_bank memory_banks_boot_swap_on[] = {
- {0x00000000, 0x01f00000},
-};
-#endif
-
-#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
-static const struct memory_bank memory_banks_boot_swap_off[] = {
- {0x04000000, 0x02000000},
-};
-
-static const struct memory_bank memory_banks_boot_swap_on[] = {
- {0x00000000, 0x02000000},
- {0x04000000, 0x02000000},
+/* {address, size} */
+static const struct memory_bank memory_banks[] = {
+ {0x42000000, 0x01f00000},
};
-#endif
static const struct memory_bank
*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT];
@@ -187,13 +129,8 @@ static void detect_num_flash_banks(void)
cfi_flash_num_flash_banks = 0;
- if (boot_is_swapped()) {
- memory_bank = memory_banks_boot_swap_on;
- end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_on);
- } else {
- memory_bank = memory_banks_boot_swap_off;
- end = memory_bank + ARRAY_SIZE(memory_banks_boot_swap_off);
- }
+ memory_bank = memory_banks;
+ end = memory_bank + ARRAY_SIZE(memory_banks);
for (; memory_bank < end; memory_bank++) {
if (cfi_flash_num_flash_banks >=
@@ -222,3 +159,73 @@ void support_card_late_init(void)
{
detect_num_flash_banks();
}
+
+static const u8 ledval_num[] = {
+ 0x7e, /* 0 */
+ 0x0c, /* 1 */
+ 0xb6, /* 2 */
+ 0x9e, /* 3 */
+ 0xcc, /* 4 */
+ 0xda, /* 5 */
+ 0xfa, /* 6 */
+ 0x4e, /* 7 */
+ 0xfe, /* 8 */
+ 0xde, /* 9 */
+};
+
+static const u8 ledval_alpha[] = {
+ 0xee, /* A */
+ 0xf8, /* B */
+ 0x72, /* C */
+ 0xbc, /* D */
+ 0xf2, /* E */
+ 0xe2, /* F */
+ 0x7a, /* G */
+ 0xe8, /* H */
+ 0x08, /* I */
+ 0x3c, /* J */
+ 0xea, /* K */
+ 0x70, /* L */
+ 0x6e, /* M */
+ 0xa8, /* N */
+ 0xb8, /* O */
+ 0xe6, /* P */
+ 0xce, /* Q */
+ 0xa0, /* R */
+ 0xc8, /* S */
+ 0x8c, /* T */
+ 0x7c, /* U */
+ 0x54, /* V */
+ 0xfc, /* W */
+ 0xec, /* X */
+ 0xdc, /* Y */
+ 0xa4, /* Z */
+};
+
+static u8 char2ledval(char c)
+{
+ if (isdigit(c))
+ return ledval_num[c - '0'];
+ else if (isalpha(c))
+ return ledval_alpha[toupper(c) - 'A'];
+
+ return 0;
+}
+
+void led_puts(const char *s)
+{
+ int i;
+ u32 val = 0;
+
+ if (!s)
+ return;
+
+ for (i = 0; i < 4; i++) {
+ val <<= 8;
+ val |= char2ledval(*s);
+ if (*s != '\0')
+ s++;
+ }
+
+ writel(~val, LED_BASE);
+}
diff --git a/arch/arm/mach-uniphier/ph1-ld4/Makefile b/arch/arm/mach-uniphier/ph1-ld4/Makefile
deleted file mode 100644
index 1410b12..0000000
--- a/arch/arm/mach-uniphier/ph1-ld4/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
- early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
-endif
-
-obj-y += boot-mode.o
diff --git a/arch/arm/mach-uniphier/ph1-ld4/boot-mode.c b/arch/arm/mach-uniphier/ph1-ld4/boot-mode.c
deleted file mode 100644
index d359b56..0000000
--- a/arch/arm/mach-uniphier/ph1-ld4/boot-mode.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-pro4/boot-mode.c"
diff --git a/arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c
deleted file mode 100644
index d7ef16b..0000000
--- a/arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-pro4/early_clkrst_init.c"
diff --git a/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c
deleted file mode 100644
index e5e86bb..0000000
--- a/arch/arm/mach-uniphier/ph1-ld4/early_pinctrl.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <mach/sg-regs.h>
-
-void early_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(85, 1); /* HSDOUT3 -> RXD0 */
- sg_set_pinsel(88, 1); /* HDDOUT6 -> TXD0 */
-
- sg_set_pinsel(69, 23); /* PCIOWR -> TXD1 */
- sg_set_pinsel(70, 23); /* PCIORD -> RXD1 */
-
- sg_set_pinsel(128, 13); /* XIRQ6 -> TXD2 */
- sg_set_pinsel(129, 13); /* XIRQ7 -> RXD2 */
-
- sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */
- sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
-#endif
-}
diff --git a/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S
deleted file mode 100644
index 7928c5c..0000000
--- a/arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <mach/sg-regs.h>
-
-#define UART_CLK 36864000
-#include <mach/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
- init_debug_uart r0, r1, r2
-
- /* UART Port 0 */
- set_pinsel 85, 1, r0, r1
- set_pinsel 88, 1, r0, r1
-
- ldr r0, =SG_IECTRL
- ldr r1, [r0]
- orr r1, r1, #1
- str r1, [r0]
-
- mov pc, lr
-ENDPROC(setup_lowlevel_debug)
diff --git a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c
deleted file mode 100644
index 20cc7b3..0000000
--- a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <mach/sg-regs.h>
-
-void pin_init(void)
-{
- u32 tmp;
-
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(158, 0); /* XNFRE -> XNFRE_GB */
- sg_set_pinsel(159, 0); /* XNFWE -> XNFWE_GB */
- sg_set_pinsel(160, 0); /* XFALE -> NFALE_GB */
- sg_set_pinsel(161, 0); /* XFCLE -> NFCLE_GB */
- sg_set_pinsel(162, 0); /* XNFWP -> XFNWP_GB */
- sg_set_pinsel(163, 0); /* XNFCE0 -> XNFCE0_GB */
- sg_set_pinsel(164, 0); /* NANDRYBY0 -> NANDRYBY0_GB */
- sg_set_pinsel(22, 0); /* MMCCLK -> XFNCE1_GB */
- sg_set_pinsel(23, 0); /* MMCCMD -> NANDRYBY1_GB */
- sg_set_pinsel(24, 0); /* MMCDAT0 -> NFD0_GB */
- sg_set_pinsel(25, 0); /* MMCDAT1 -> NFD1_GB */
- sg_set_pinsel(26, 0); /* MMCDAT2 -> NFD2_GB */
- sg_set_pinsel(27, 0); /* MMCDAT3 -> NFD3_GB */
- sg_set_pinsel(28, 0); /* MMCDAT4 -> NFD4_GB */
- sg_set_pinsel(29, 0); /* MMCDAT5 -> NFD5_GB */
- sg_set_pinsel(30, 0); /* MMCDAT6 -> NFD6_GB */
- sg_set_pinsel(31, 0); /* MMCDAT7 -> NFD7_GB */
-#endif
-
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- sg_set_pinsel(53, 0); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(54, 0); /* USB0OD -> USB0OD */
- sg_set_pinsel(55, 0); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(56, 0); /* USB1OD -> USB1OD */
- /* sg_set_pinsel(67, 23); */ /* PCOE -> USB2VBUS */
- /* sg_set_pinsel(68, 23); */ /* PCWAIT -> USB2OD */
-#endif
-
- tmp = readl(SG_IECTRL);
- tmp |= 0x41;
- writel(tmp, SG_IECTRL);
-}
diff --git a/arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c
deleted file mode 100644
index 837b2a8..0000000
--- a/arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-pro4/pll_spectrum.c"
diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c b/arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c
deleted file mode 100644
index 5b5958b..0000000
--- a/arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
-
-void sbc_init(void)
-{
- u32 tmp;
-
- /* system bus output enable */
- tmp = readl(PC0CTRL);
- tmp &= 0xfffffcff;
- writel(tmp, PC0CTRL);
-
- /* XECS1: sub/boot memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
- /* XECS0: boot/sub memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-
- /* XECS3: peripherals */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
-
- /* base address regsiters */
- writel(0x0000bc01, SBBASE0);
- writel(0x0400bc01, SBBASE1);
- writel(0x0800bf01, SBBASE3);
-
- /* enable access to sub memory when boot swap is on */
- if (boot_is_swapped())
- sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
-
- sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
-}
diff --git a/arch/arm/mach-uniphier/ph1-ld4/sg_init.c b/arch/arm/mach-uniphier/ph1-ld4/sg_init.c
deleted file mode 100644
index dab56e9..0000000
--- a/arch/arm/mach-uniphier/ph1-ld4/sg_init.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <mach/sg-regs.h>
-
-void sg_init(void)
-{
- u32 tmp;
-
- /* Input ports must be enabled before deasserting reset of cores */
- tmp = readl(SG_IECTRL);
- tmp |= 0x1;
- writel(tmp, SG_IECTRL);
-}
diff --git a/arch/arm/mach-uniphier/ph1-pro4/Makefile b/arch/arm/mach-uniphier/ph1-pro4/Makefile
deleted file mode 100644
index 229f443..0000000
--- a/arch/arm/mach-uniphier/ph1-pro4/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += sg_init.o pll_init.o early_clkrst_init.o \
- early_pinctrl.o pll_spectrum.o umc_init.o ddrphy_init.o
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
-endif
-
-obj-y += boot-mode.o
diff --git a/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c
deleted file mode 100644
index e78d6ab..0000000
--- a/arch/arm/mach-uniphier/ph1-pro4/early_pinctrl.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <mach/sg-regs.h>
-
-void early_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(127, 0); /* RXD0 -> RXD0 */
- sg_set_pinsel(128, 0); /* TXD0 -> TXD0 */
- sg_set_pinsel(129, 0); /* RXD1 -> RXD1 */
- sg_set_pinsel(130, 0); /* TXD1 -> TXD1 */
- sg_set_pinsel(131, 0); /* RXD2 -> RXD2 */
- sg_set_pinsel(132, 0); /* TXD2 -> TXD2 */
- sg_set_pinsel(88, 2); /* CH6CLK -> RXD3 */
- sg_set_pinsel(89, 2); /* CH6VAL -> TXD3 */
-#endif
-
- writel(1, SG_LOADPINCTRL);
-}
diff --git a/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S
deleted file mode 100644
index fcaf6d1..0000000
--- a/arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
-
-#define UART_CLK 73728000
-#include <mach/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
- ldr r0, =SC_CLKCTRL
- ldr r1, [r0]
- orr r1, r1, #SC_CLKCTRL_CEN_PERI
- str r1, [r0]
-
- init_debug_uart r0, r1, r2
-
- /* UART Port 0 */
- set_pinsel 127, 0, r0, r1
- set_pinsel 128, 0, r0, r1
-
- ldr r0, =SG_LOADPINCTRL
- mov r1, #1
- str r1, [r0]
-
- ldr r0, =SG_IECTRL
- ldr r1, [r0]
- orr r1, r1, #1
- str r1, [r0]
-
- mov pc, lr
-ENDPROC(setup_lowlevel_debug)
diff --git a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c
deleted file mode 100644
index 2a5a296..0000000
--- a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <mach/sg-regs.h>
-
-void pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(40, 0); /* NFD0 -> NFD0 */
- sg_set_pinsel(41, 0); /* NFD1 -> NFD1 */
- sg_set_pinsel(42, 0); /* NFD2 -> NFD2 */
- sg_set_pinsel(43, 0); /* NFD3 -> NFD3 */
- sg_set_pinsel(44, 0); /* NFD4 -> NFD4 */
- sg_set_pinsel(45, 0); /* NFD5 -> NFD5 */
- sg_set_pinsel(46, 0); /* NFD6 -> NFD6 */
- sg_set_pinsel(47, 0); /* NFD7 -> NFD7 */
- sg_set_pinsel(48, 0); /* NFALE -> NFALE */
- sg_set_pinsel(49, 0); /* NFCLE -> NFCLE */
- sg_set_pinsel(50, 0); /* XNFRE -> XNFRE */
- sg_set_pinsel(51, 0); /* XNFWE -> XNFWE */
- sg_set_pinsel(52, 0); /* XNFWP -> XNFWP */
- sg_set_pinsel(53, 0); /* XNFCE0 -> XNFCE0 */
- sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */
- /* sg_set_pinsel(131, 1); */ /* RXD2 -> NRYBY1 */
- /* sg_set_pinsel(132, 1); */ /* TXD2 -> XNFCE1 */
-#endif
-
-#ifdef CONFIG_USB_XHCI_UNIPHIER
- sg_set_pinsel(180, 0); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(181, 0); /* USB0OD -> USB0OD */
- sg_set_pinsel(182, 0); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(183, 0); /* USB1OD -> USB1OD */
-#endif
-
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */
- sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */
- sg_set_pinsel(187, 0); /* USB3VBUS -> USB3VBUS */
- sg_set_pinsel(188, 0); /* USB3OD -> USB3OD */
-#endif
-
- writel(1, SG_LOADPINCTRL);
-}
diff --git a/arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c b/arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c
deleted file mode 100644
index 877ba79..0000000
--- a/arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
-
-void sbc_init(void)
-{
- /* XECS0: boot/sub memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
-
- /* XECS1: sub/boot memory (boot swap = off/on) */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
-
- /* XECS3: peripherals */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
-
- writel(0x0000bc01, SBBASE0); /* boot memory */
- writel(0x0400bc01, SBBASE1); /* sub memory */
- writel(0x0800bf01, SBBASE3); /* peripherals */
-
- /* enable access to sub memory when boot swap is on */
- if (boot_is_swapped())
- sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
-
- sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
- writel(0x00000001, SG_LOADPINCTRL);
-}
diff --git a/arch/arm/mach-uniphier/ph1-pro4/sg_init.c b/arch/arm/mach-uniphier/ph1-pro4/sg_init.c
deleted file mode 100644
index d6ccffb..0000000
--- a/arch/arm/mach-uniphier/ph1-pro4/sg_init.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <mach/sg-regs.h>
-
-void sg_init(void)
-{
- u32 tmp;
-
- /* Input ports must be enabled before deasserting reset of cores */
- tmp = readl(SG_IECTRL);
- tmp |= 1 << 6;
- writel(tmp, SG_IECTRL);
-}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/Makefile b/arch/arm/mach-uniphier/ph1-sld3/Makefile
deleted file mode 100644
index aff5d64..0000000
--- a/arch/arm/mach-uniphier/ph1-sld3/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
-obj-y += bcu_init.o memconf.o sg_init.o pll_init.o early_clkrst_init.o \
- early_pinctrl.o pll_spectrum.o umc_init.o
-obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
-obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
-else
-obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
-endif
-
-obj-y += boot-mode.o
diff --git a/arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c
deleted file mode 100644
index 3a3dab7..0000000
--- a/arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-pro4/clkrst_init.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c
deleted file mode 100644
index d7ef16b..0000000
--- a/arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-pro4/early_clkrst_init.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c
deleted file mode 100644
index f113e65..0000000
--- a/arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <mach/sg-regs.h>
-
-void early_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(63, 0); /* RXD0 */
- sg_set_pinsel(64, 1); /* TXD0 */
-
- sg_set_pinsel(65, 0); /* RXD1 */
- sg_set_pinsel(66, 1); /* TXD1 */
-
- sg_set_pinsel(96, 2); /* RXD2 */
- sg_set_pinsel(102, 2); /* TXD2 */
-#endif
-}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S
deleted file mode 100644
index 41f67b7..0000000
--- a/arch/arm/mach-uniphier/ph1-sld3/lowlevel_debug.S
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <mach/bcu-regs.h>
-#include <mach/sc-regs.h>
-#include <mach/sg-regs.h>
-
-#define UART_CLK 36864000
-#include <mach/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
- ldr r0, =BCSCR5
- ldr r1, =0x24440000
- str r1, [r0]
-
- ldr r0, =SC_CLKCTRL
- ldr r1, [r0]
- orr r1, r1, #SC_CLKCTRL_CEN_PERI
- str r1, [r0]
-
- init_debug_uart r0, r1, r2
-
- set_pinsel 63, 0, r0, r1
- set_pinsel 64, 1, r0, r1
-
- mov pc, lr
-ENDPROC(setup_lowlevel_debug)
diff --git a/arch/arm/mach-uniphier/ph1-sld3/memconf.c b/arch/arm/mach-uniphier/ph1-sld3/memconf.c
deleted file mode 100644
index 553a9e3..0000000
--- a/arch/arm/mach-uniphier/ph1-sld3/memconf.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/types.h>
-#include <linux/sizes.h>
-#include <mach/sg-regs.h>
-
-static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
-{
- int size_mb = size / num;
- u32 ret;
-
- switch (size_mb) {
- case SZ_64M:
- ret = SG_MEMCONF_CH2_SZ_64M;
- break;
- case SZ_128M:
- ret = SG_MEMCONF_CH2_SZ_128M;
- break;
- case SZ_256M:
- ret = SG_MEMCONF_CH2_SZ_256M;
- break;
- case SZ_512M:
- ret = SG_MEMCONF_CH2_SZ_512M;
- break;
- default:
- BUG();
- break;
- }
-
- switch (num) {
- case 1:
- ret |= SG_MEMCONF_CH2_NUM_1;
- break;
- case 2:
- ret |= SG_MEMCONF_CH2_NUM_2;
- break;
- default:
- BUG();
- break;
- }
- return ret;
-}
-
-u32 memconf_additional_val(void)
-{
- return sg_memconf_val_ch2(CONFIG_SDRAM2_SIZE, CONFIG_DDR_NUM_CH2);
-}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/pinctrl.c b/arch/arm/mach-uniphier/ph1-sld3/pinctrl.c
deleted file mode 100644
index 5ecbe4c..0000000
--- a/arch/arm/mach-uniphier/ph1-sld3/pinctrl.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <mach/sg-regs.h>
-
-void pin_init(void)
-{
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- sg_set_pinsel(13, 0); /* USB0OC */
- sg_set_pinsel(14, 1); /* USB0VBUS */
-
- sg_set_pinsel(15, 0); /* USB1OC */
- sg_set_pinsel(16, 1); /* USB1VBUS */
-
- sg_set_pinsel(17, 0); /* USB2OC */
- sg_set_pinsel(18, 1); /* USB2VBUS */
-
- sg_set_pinsel(19, 0); /* USB3OC */
- sg_set_pinsel(20, 1); /* USB3VBUS */
-#endif
-}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c b/arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c
deleted file mode 100644
index f5e2446..0000000
--- a/arch/arm/mach-uniphier/ph1-sld3/sbc_init_3cs.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
-
-void sbc_init(void)
-{
- /* only address/data multiplex mode is supported */
-
- /* XECS0 : boot/sub memory (boot swap = off/on) */
- writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL00);
- writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL01);
- writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL02);
-
- /* XECS1 : sub/boot memory (boot swap = off/on) */
- writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12);
-
- /* XECS2 : peripherals */
- writel(SBCTRL0_ADMULTIPLX_PERI_VALUE, SBCTRL20);
- writel(SBCTRL1_ADMULTIPLX_PERI_VALUE, SBCTRL21);
- writel(SBCTRL2_ADMULTIPLX_PERI_VALUE, SBCTRL22);
-
- /* base address regsiters */
- writel(0x0000bc01, SBBASE0);
- writel(0x0400bc01, SBBASE1);
- writel(0x0800bf01, SBBASE2);
-
- sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */
-}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/sg_init.c b/arch/arm/mach-uniphier/ph1-sld3/sg_init.c
deleted file mode 100644
index ca3cb9c..0000000
--- a/arch/arm/mach-uniphier/ph1-sld3/sg_init.c
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-void sg_init(void)
-{
-}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/umc_init.c b/arch/arm/mach-uniphier/ph1-sld3/umc_init.c
deleted file mode 100644
index 91ee3de..0000000
--- a/arch/arm/mach-uniphier/ph1-sld3/umc_init.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-int umc_init(void)
-{
- /* add UMC init code here */
- printf("Implement memory init code\n");
-
- return 0;
-}
diff --git a/arch/arm/mach-uniphier/ph1-sld8/Makefile b/arch/arm/mach-uniphier/ph1-sld8/Makefile
deleted file mode 100644
index 8eb575e..0000000
--- a/arch/arm/mach-uniphier/ph1-sld8/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-include $(src)/../ph1-ld4/Makefile
diff --git a/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c b/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c
deleted file mode 100644
index 69b172e..0000000
--- a/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-ld4/bcu_init.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c b/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c
deleted file mode 100644
index d359b56..0000000
--- a/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-pro4/boot-mode.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c
deleted file mode 100644
index 8d3435d..0000000
--- a/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-ld4/clkrst_init.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c
deleted file mode 100644
index dd236b7..0000000
--- a/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-ld4/early_clkrst_init.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c
deleted file mode 100644
index 28cc429..0000000
--- a/arch/arm/mach-uniphier/ph1-sld8/early_pinctrl.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <mach/sg-regs.h>
-
-void early_pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_UNIPHIER_SERIAL
- sg_set_pinsel(70, 3); /* HDDOUT0 -> TXD0 */
- sg_set_pinsel(71, 3); /* HSDOUT1 -> RXD0 */
-
- sg_set_pinsel(114, 0); /* TXD1 -> TXD1 */
- sg_set_pinsel(115, 0); /* RXD1 -> RXD1 */
-
- sg_set_pinsel(112, 1); /* SBO1 -> TXD2 */
- sg_set_pinsel(113, 1); /* SBI1 -> RXD2 */
-
- sg_set_pinsel(110, 1); /* SBO0 -> TXD3 */
- sg_set_pinsel(111, 1); /* SBI0 -> RXD3 */
-#endif
-}
diff --git a/arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S b/arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S
deleted file mode 100644
index 73f0f63..0000000
--- a/arch/arm/mach-uniphier/ph1-sld8/lowlevel_debug.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * On-chip UART initializaion for low-level debugging
- *
- * Copyright (C) 2014 Panasonic Corporation
- * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/linkage.h>
-#include <mach/sg-regs.h>
-
-#define UART_CLK 80000000
-#include <mach/debug-uart.S>
-
-ENTRY(setup_lowlevel_debug)
- init_debug_uart r0, r1, r2
-
- /* UART Port 0 */
- set_pinsel 70, 3, r0, r1
- set_pinsel 71, 3, r0, r1
-
- ldr r0, =SG_IECTRL
- ldr r1, [r0]
- orr r1, r1, #1
- str r1, [r0]
-
- mov pc, lr
-ENDPROC(setup_lowlevel_debug)
diff --git a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c
deleted file mode 100644
index 130c831..0000000
--- a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <linux/io.h>
-#include <mach/sg-regs.h>
-
-void pin_init(void)
-{
- /* Comment format: PAD Name -> Function Name */
-
-#ifdef CONFIG_SYS_I2C_UNIPHIER
- {
- u32 tmp;
- tmp = readl(SG_IECTRL);
- tmp |= 0xc00; /* enable SCL0, SDA0, SCL1, SDA1 */
- writel(tmp, SG_IECTRL);
- }
-#endif
-
-#ifdef CONFIG_NAND_DENALI
- sg_set_pinsel(15, 0); /* XNFRE_GB -> XNFRE_GB */
- sg_set_pinsel(16, 0); /* XNFWE_GB -> XNFWE_GB */
- sg_set_pinsel(17, 0); /* XFALE_GB -> NFALE_GB */
- sg_set_pinsel(18, 0); /* XFCLE_GB -> NFCLE_GB */
- sg_set_pinsel(19, 0); /* XNFWP_GB -> XFNWP_GB */
- sg_set_pinsel(20, 0); /* XNFCE0_GB -> XNFCE0_GB */
- sg_set_pinsel(21, 0); /* NANDRYBY0_GB -> NANDRYBY0_GB */
- sg_set_pinsel(22, 0); /* XFNCE1_GB -> XFNCE1_GB */
- sg_set_pinsel(23, 0); /* NANDRYBY1_GB -> NANDRYBY1_GB */
- sg_set_pinsel(24, 0); /* NFD0_GB -> NFD0_GB */
- sg_set_pinsel(25, 0); /* NFD1_GB -> NFD1_GB */
- sg_set_pinsel(26, 0); /* NFD2_GB -> NFD2_GB */
- sg_set_pinsel(27, 0); /* NFD3_GB -> NFD3_GB */
- sg_set_pinsel(28, 0); /* NFD4_GB -> NFD4_GB */
- sg_set_pinsel(29, 0); /* NFD5_GB -> NFD5_GB */
- sg_set_pinsel(30, 0); /* NFD6_GB -> NFD6_GB */
- sg_set_pinsel(31, 0); /* NFD7_GB -> NFD7_GB */
-#endif
-
-#ifdef CONFIG_USB_EHCI_UNIPHIER
- sg_set_pinsel(41, 0); /* USB0VBUS -> USB0VBUS */
- sg_set_pinsel(42, 0); /* USB0OD -> USB0OD */
- sg_set_pinsel(43, 0); /* USB1VBUS -> USB1VBUS */
- sg_set_pinsel(44, 0); /* USB1OD -> USB1OD */
- /* sg_set_pinsel(114, 1); */ /* TXD1 -> USB2VBUS (shared with UART) */
- /* sg_set_pinsel(115, 1); */ /* RXD1 -> USB2OD */
-#endif
-}
diff --git a/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c
deleted file mode 100644
index 9b8c485..0000000
--- a/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-ld4/pll_spectrum.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c b/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c
deleted file mode 100644
index 225c0d2..0000000
--- a/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-ld4/sbc_init.c"
diff --git a/arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c b/arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c
deleted file mode 100644
index c2267c7..0000000
--- a/arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-#include <mach/sbc-regs.h>
-#include <mach/sg-regs.h>
-
-void sbc_init(void)
-{
- u32 tmp;
-
- /* system bus output enable */
- tmp = readl(PC0CTRL);
- tmp &= 0xfffffcff;
- writel(tmp, PC0CTRL);
-
- /*
- * SBCTRL0* does not need settings because PH1-sLD8 has no support for
- * XECS0. The boot swap must be enabled to boot from the support card.
- */
-
- if (boot_is_swapped()) {
- /* XECS1 : boot memory if boot swap is on */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
- }
-
- /* XECS4 : sub memory */
- writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
- writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
- writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
- writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
-
- /* XECS5 : peripherals */
- writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
- writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
- writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
- writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
-
- /* base address regsiters */
- writel(0x0000bc01, SBBASE0); /* boot memory */
- writel(0x0900bfff, SBBASE1); /* dummy */
- writel(0x0400bc01, SBBASE4); /* sub memory */
- writel(0x0800bf01, SBBASE5); /* peripherals */
-
- sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
- sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
-
- /* dummy read to assure write process */
- readl(SG_PINCTRL(0));
-}
diff --git a/arch/arm/mach-uniphier/ph1-sld8/sg_init.c b/arch/arm/mach-uniphier/ph1-sld8/sg_init.c
deleted file mode 100644
index a808289..0000000
--- a/arch/arm/mach-uniphier/ph1-sld8/sg_init.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../ph1-ld4/sg_init.c"
diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile
new file mode 100644
index 0000000..8517595
--- /dev/null
+++ b/arch/arm/mach-uniphier/pinctrl/Makefile
@@ -0,0 +1,7 @@
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pinctrl-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += pinctrl-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += pinctrl-ph1-ld6b.o
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
new file mode 100644
index 0000000..160d3ef
--- /dev/null
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void ph1_ld4_pin_init(void)
+{
+ u32 tmp;
+
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(158, 0, 8, 4); /* XNFRE -> XNFRE_GB */
+ sg_set_pinsel(159, 0, 8, 4); /* XNFWE -> XNFWE_GB */
+ sg_set_pinsel(160, 0, 8, 4); /* XFALE -> NFALE_GB */
+ sg_set_pinsel(161, 0, 8, 4); /* XFCLE -> NFCLE_GB */
+ sg_set_pinsel(162, 0, 8, 4); /* XNFWP -> XFNWP_GB */
+ sg_set_pinsel(163, 0, 8, 4); /* XNFCE0 -> XNFCE0_GB */
+ sg_set_pinsel(164, 0, 8, 4); /* NANDRYBY0 -> NANDRYBY0_GB */
+ sg_set_pinsel(22, 0, 8, 4); /* MMCCLK -> XFNCE1_GB */
+ sg_set_pinsel(23, 0, 8, 4); /* MMCCMD -> NANDRYBY1_GB */
+ sg_set_pinsel(24, 0, 8, 4); /* MMCDAT0 -> NFD0_GB */
+ sg_set_pinsel(25, 0, 8, 4); /* MMCDAT1 -> NFD1_GB */
+ sg_set_pinsel(26, 0, 8, 4); /* MMCDAT2 -> NFD2_GB */
+ sg_set_pinsel(27, 0, 8, 4); /* MMCDAT3 -> NFD3_GB */
+ sg_set_pinsel(28, 0, 8, 4); /* MMCDAT4 -> NFD4_GB */
+ sg_set_pinsel(29, 0, 8, 4); /* MMCDAT5 -> NFD5_GB */
+ sg_set_pinsel(30, 0, 8, 4); /* MMCDAT6 -> NFD6_GB */
+ sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */
+#endif
+
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ sg_set_pinsel(53, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(54, 0, 8, 4); /* USB0OD -> USB0OD */
+ sg_set_pinsel(55, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(56, 0, 8, 4); /* USB1OD -> USB1OD */
+ /* sg_set_pinsel(67, 23, 8, 4); */ /* PCOE -> USB2VBUS */
+ /* sg_set_pinsel(68, 23, 8, 4); */ /* PCWAIT -> USB2OD */
+#endif
+
+ tmp = readl(SG_IECTRL);
+ tmp |= 0x41;
+ writel(tmp, SG_IECTRL);
+}
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c
new file mode 100644
index 0000000..4f950d3
--- /dev/null
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld6b.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void ph1_ld6b_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(30, 0, 8, 4); /* XNFRE -> XNFRE */
+ sg_set_pinsel(31, 0, 8, 4); /* XNFWE -> XNFWE */
+ sg_set_pinsel(32, 0, 8, 4); /* NFALE -> NFALE */
+ sg_set_pinsel(33, 0, 8, 4); /* NFCLE -> NFCLE */
+ sg_set_pinsel(34, 0, 8, 4); /* XNFWP -> XNFWP */
+ sg_set_pinsel(35, 0, 8, 4); /* XNFCE0 -> XNFCE0 */
+ sg_set_pinsel(36, 0, 8, 4); /* NRYBY0 -> NRYBY0 */
+ sg_set_pinsel(37, 0, 8, 4); /* XNFCE1 -> NRYBY1 */
+ sg_set_pinsel(38, 0, 8, 4); /* NRYBY1 -> XNFCE1 */
+ sg_set_pinsel(39, 0, 8, 4); /* NFD0 -> NFD0 */
+ sg_set_pinsel(40, 0, 8, 4); /* NFD1 -> NFD1 */
+ sg_set_pinsel(41, 0, 8, 4); /* NFD2 -> NFD2 */
+ sg_set_pinsel(42, 0, 8, 4); /* NFD3 -> NFD3 */
+ sg_set_pinsel(43, 0, 8, 4); /* NFD4 -> NFD4 */
+ sg_set_pinsel(44, 0, 8, 4); /* NFD5 -> NFD5 */
+ sg_set_pinsel(45, 0, 8, 4); /* NFD6 -> NFD6 */
+ sg_set_pinsel(46, 0, 8, 4); /* NFD7 -> NFD7 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ sg_set_pinsel(56, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(57, 0, 8, 4); /* USB0OD -> USB0OD */
+ sg_set_pinsel(58, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(59, 0, 8, 4); /* USB1OD -> USB1OD */
+ sg_set_pinsel(60, 0, 8, 4); /* USB2VBUS -> USB2VBUS */
+ sg_set_pinsel(61, 0, 8, 4); /* USB2OD -> USB2OD */
+ sg_set_pinsel(62, 0, 8, 4); /* USB3VBUS -> USB3VBUS */
+ sg_set_pinsel(63, 0, 8, 4); /* USB3OD -> USB3OD */
+#endif
+}
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
new file mode 100644
index 0000000..f50644c
--- /dev/null
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void ph1_pro4_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(40, 0, 4, 8); /* NFD0 -> NFD0 */
+ sg_set_pinsel(41, 0, 4, 8); /* NFD1 -> NFD1 */
+ sg_set_pinsel(42, 0, 4, 8); /* NFD2 -> NFD2 */
+ sg_set_pinsel(43, 0, 4, 8); /* NFD3 -> NFD3 */
+ sg_set_pinsel(44, 0, 4, 8); /* NFD4 -> NFD4 */
+ sg_set_pinsel(45, 0, 4, 8); /* NFD5 -> NFD5 */
+ sg_set_pinsel(46, 0, 4, 8); /* NFD6 -> NFD6 */
+ sg_set_pinsel(47, 0, 4, 8); /* NFD7 -> NFD7 */
+ sg_set_pinsel(48, 0, 4, 8); /* NFALE -> NFALE */
+ sg_set_pinsel(49, 0, 4, 8); /* NFCLE -> NFCLE */
+ sg_set_pinsel(50, 0, 4, 8); /* XNFRE -> XNFRE */
+ sg_set_pinsel(51, 0, 4, 8); /* XNFWE -> XNFWE */
+ sg_set_pinsel(52, 0, 4, 8); /* XNFWP -> XNFWP */
+ sg_set_pinsel(53, 0, 4, 8); /* XNFCE0 -> XNFCE0 */
+ sg_set_pinsel(54, 0, 4, 8); /* NRYBY0 -> NRYBY0 */
+ /* sg_set_pinsel(131, 1, 4, 8); */ /* RXD2 -> NRYBY1 */
+ /* sg_set_pinsel(132, 1, 4, 8); */ /* TXD2 -> XNFCE1 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ sg_set_pinsel(180, 0, 4, 8); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(181, 0, 4, 8); /* USB0OD -> USB0OD */
+ sg_set_pinsel(182, 0, 4, 8); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */
+#endif
+
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ sg_set_pinsel(184, 0, 4, 8); /* USB2VBUS -> USB2VBUS */
+ sg_set_pinsel(185, 0, 4, 8); /* USB2OD -> USB2OD */
+ sg_set_pinsel(187, 0, 4, 8); /* USB3VBUS -> USB3VBUS */
+ sg_set_pinsel(188, 0, 4, 8); /* USB3OD -> USB3OD */
+#endif
+
+ writel(1, SG_LOADPINCTRL);
+}
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c
new file mode 100644
index 0000000..a6cc082
--- /dev/null
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void ph1_pro5_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(19, 0, 4, 8); /* XNFRE -> XNFRE */
+ sg_set_pinsel(20, 0, 4, 8); /* XNFWE -> XNFWE */
+ sg_set_pinsel(21, 0, 4, 8); /* NFALE -> NFALE */
+ sg_set_pinsel(22, 0, 4, 8); /* NFCLE -> NFCLE */
+ sg_set_pinsel(23, 0, 4, 8); /* XNFWP -> XNFWP */
+ sg_set_pinsel(24, 0, 4, 8); /* XNFCE0 -> XNFCE0 */
+ sg_set_pinsel(25, 0, 4, 8); /* NRYBY0 -> NRYBY0 */
+ sg_set_pinsel(26, 0, 4, 8); /* XNFCE1 -> XNFCE1 */
+ sg_set_pinsel(27, 0, 4, 8); /* NRYBY1 -> NRYBY1 */
+ sg_set_pinsel(28, 0, 4, 8); /* NFD0 -> NFD0 */
+ sg_set_pinsel(29, 0, 4, 8); /* NFD1 -> NFD1 */
+ sg_set_pinsel(30, 0, 4, 8); /* NFD2 -> NFD2 */
+ sg_set_pinsel(31, 0, 4, 8); /* NFD3 -> NFD3 */
+ sg_set_pinsel(32, 0, 4, 8); /* NFD4 -> NFD4 */
+ sg_set_pinsel(33, 0, 4, 8); /* NFD5 -> NFD5 */
+ sg_set_pinsel(34, 0, 4, 8); /* NFD6 -> NFD6 */
+ sg_set_pinsel(35, 0, 4, 8); /* NFD7 -> NFD7 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ sg_set_pinsel(124, 0, 4, 8); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(125, 0, 4, 8); /* USB0OD -> USB0OD */
+ sg_set_pinsel(126, 0, 4, 8); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(127, 0, 4, 8); /* USB1OD -> USB1OD */
+#endif
+
+ writel(1, SG_LOADPINCTRL);
+}
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c
new file mode 100644
index 0000000..f1b2bbb
--- /dev/null
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void ph1_sld3_pin_init(void)
+{
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ sg_set_pinsel(13, 0, 4, 4); /* USB0OC */
+ sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */
+
+ sg_set_pinsel(15, 0, 4, 4); /* USB1OC */
+ sg_set_pinsel(16, 1, 4, 4); /* USB1VBUS */
+
+ sg_set_pinsel(17, 0, 4, 4); /* USB2OC */
+ sg_set_pinsel(18, 1, 4, 4); /* USB2VBUS */
+
+ sg_set_pinsel(19, 0, 4, 4); /* USB3OC */
+ sg_set_pinsel(20, 1, 4, 4); /* USB3VBUS */
+#endif
+}
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
new file mode 100644
index 0000000..f936a53
--- /dev/null
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void ph1_sld8_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(15, 0, 8, 4); /* XNFRE_GB -> XNFRE_GB */
+ sg_set_pinsel(16, 0, 8, 4); /* XNFWE_GB -> XNFWE_GB */
+ sg_set_pinsel(17, 0, 8, 4); /* XFALE_GB -> NFALE_GB */
+ sg_set_pinsel(18, 0, 8, 4); /* XFCLE_GB -> NFCLE_GB */
+ sg_set_pinsel(19, 0, 8, 4); /* XNFWP_GB -> XFNWP_GB */
+ sg_set_pinsel(20, 0, 8, 4); /* XNFCE0_GB -> XNFCE0_GB */
+ sg_set_pinsel(21, 0, 8, 4); /* NANDRYBY0_GB -> NANDRYBY0_GB */
+ sg_set_pinsel(22, 0, 8, 4); /* XFNCE1_GB -> XFNCE1_GB */
+ sg_set_pinsel(23, 0, 8, 4); /* NANDRYBY1_GB -> NANDRYBY1_GB */
+ sg_set_pinsel(24, 0, 8, 4); /* NFD0_GB -> NFD0_GB */
+ sg_set_pinsel(25, 0, 8, 4); /* NFD1_GB -> NFD1_GB */
+ sg_set_pinsel(26, 0, 8, 4); /* NFD2_GB -> NFD2_GB */
+ sg_set_pinsel(27, 0, 8, 4); /* NFD3_GB -> NFD3_GB */
+ sg_set_pinsel(28, 0, 8, 4); /* NFD4_GB -> NFD4_GB */
+ sg_set_pinsel(29, 0, 8, 4); /* NFD5_GB -> NFD5_GB */
+ sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */
+ sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */
+#endif
+
+#ifdef CONFIG_USB_EHCI_UNIPHIER
+ sg_set_pinsel(41, 0, 8, 4); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(42, 0, 8, 4); /* USB0OD -> USB0OD */
+ sg_set_pinsel(43, 0, 8, 4); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(44, 0, 8, 4); /* USB1OD -> USB1OD */
+ /* sg_set_pinsel(114, 1, 8, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
+ /* sg_set_pinsel(115, 1, 8, 4); */ /* RXD1 -> USB2OD */
+#endif
+}
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c
new file mode 100644
index 0000000..96abd02
--- /dev/null
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-proxstream2.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sg-regs.h>
+
+void proxstream2_pin_init(void)
+{
+ /* Comment format: PAD Name -> Function Name */
+
+#ifdef CONFIG_NAND_DENALI
+ sg_set_pinsel(30, 8, 8, 4); /* XNFRE -> XNFRE */
+ sg_set_pinsel(31, 8, 8, 4); /* XNFWE -> XNFWE */
+ sg_set_pinsel(32, 8, 8, 4); /* NFALE -> NFALE */
+ sg_set_pinsel(33, 8, 8, 4); /* NFCLE -> NFCLE */
+ sg_set_pinsel(34, 8, 8, 4); /* XNFWP -> XNFWP */
+ sg_set_pinsel(35, 8, 8, 4); /* XNFCE0 -> XNFCE0 */
+ sg_set_pinsel(36, 8, 8, 4); /* NRYBY0 -> NRYBY0 */
+ sg_set_pinsel(37, 8, 8, 4); /* XNFCE1 -> NRYBY1 */
+ sg_set_pinsel(38, 8, 8, 4); /* NRYBY1 -> XNFCE1 */
+ sg_set_pinsel(39, 8, 8, 4); /* NFD0 -> NFD0 */
+ sg_set_pinsel(40, 8, 8, 4); /* NFD1 -> NFD1 */
+ sg_set_pinsel(41, 8, 8, 4); /* NFD2 -> NFD2 */
+ sg_set_pinsel(42, 8, 8, 4); /* NFD3 -> NFD3 */
+ sg_set_pinsel(43, 8, 8, 4); /* NFD4 -> NFD4 */
+ sg_set_pinsel(44, 8, 8, 4); /* NFD5 -> NFD5 */
+ sg_set_pinsel(45, 8, 8, 4); /* NFD6 -> NFD6 */
+ sg_set_pinsel(46, 8, 8, 4); /* NFD7 -> NFD7 */
+#endif
+
+#ifdef CONFIG_USB_XHCI_UNIPHIER
+ sg_set_pinsel(56, 8, 8, 4); /* USB0VBUS -> USB0VBUS */
+ sg_set_pinsel(57, 8, 8, 4); /* USB0OD -> USB0OD */
+ sg_set_pinsel(58, 8, 8, 4); /* USB1VBUS -> USB1VBUS */
+ sg_set_pinsel(59, 8, 8, 4); /* USB1OD -> USB1OD */
+ sg_set_pinsel(60, 8, 8, 4); /* USB2VBUS -> USB2VBUS */
+ sg_set_pinsel(61, 8, 8, 4); /* USB2OD -> USB2OD */
+ sg_set_pinsel(62, 8, 8, 4); /* USB3VBUS -> USB3VBUS */
+ sg_set_pinsel(63, 8, 8, 4); /* USB3OD -> USB3OD */
+#endif
+}
diff --git a/arch/arm/mach-uniphier/pll/Makefile b/arch/arm/mach-uniphier/pll/Makefile
new file mode 100644
index 0000000..d33f99e
--- /dev/null
+++ b/arch/arm/mach-uniphier/pll/Makefile
@@ -0,0 +1,8 @@
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pll-init-ph1-sld3.o \
+ pll-spectrum-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pll-init-ph1-ld4.o \
+ pll-spectrum-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += pll-init-ph1-pro4.o \
+ pll-spectrum-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += pll-init-ph1-sld8.o \
+ pll-spectrum-ph1-ld4.o
diff --git a/arch/arm/mach-uniphier/ph1-ld4/pll_init.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c
index f8ec2b6..a272a90 100644
--- a/arch/arm/mach-uniphier/ph1-ld4/pll_init.c
+++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c
@@ -5,13 +5,15 @@
*/
#include <common.h>
+#include <linux/err.h>
#include <linux/io.h>
+#include <mach/init.h>
#include <mach/sc-regs.h>
#include <mach/sg-regs.h>
#undef DPLL_SSC_RATE_1PER
-static void dpll_init(void)
+static int dpll_init(unsigned int dram_freq)
{
u32 tmp;
@@ -22,13 +24,17 @@ static void dpll_init(void)
*/
tmp = readl(SC_DPLLCTRL);
tmp &= ~0x000f0000;
-#if CONFIG_DDR_FREQ == 1600
- tmp |= 0x000c0000;
-#elif CONFIG_DDR_FREQ == 1333
- tmp |= 0x000d0000;
-#else
-# error "Unknown frequency"
-#endif
+ switch (dram_freq) {
+ case 1333:
+ tmp |= 0x000d0000;
+ break;
+ case 1600:
+ tmp |= 0x000c0000;
+ break;
+ default:
+ pr_err("Unsupported frequency");
+ return -EINVAL;
+ }
#if defined(DPLL_SSC_RATE_1PER)
tmp &= ~SC_DPLLCTRL_SSC_RATE;
@@ -40,6 +46,8 @@ static void dpll_init(void)
tmp = readl(SC_DPLLCTRL2);
tmp |= SC_DPLLCTRL2_NRSTDS;
writel(tmp, SC_DPLLCTRL2);
+
+ return 0;
}
static void upll_init(void)
@@ -174,9 +182,13 @@ static void vpll_init(void)
writel(tmp, SC_VPLL27BCTRL);
}
-void pll_init(void)
+int ph1_ld4_pll_init(const struct uniphier_board_data *bd)
{
- dpll_init();
+ int ret;
+
+ ret = dpll_init(bd->dram_freq);
+ if (ret)
+ return ret;
upll_init();
vpll_init();
@@ -186,4 +198,6 @@ void pll_init(void)
* so 20 usec can be saved here.
*/
udelay(480);
+
+ return 0;
}
diff --git a/arch/arm/mach-uniphier/ph1-pro4/pll_init.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c
index d693368..906c22f 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/pll_init.c
+++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c
@@ -5,13 +5,15 @@
*/
#include <common.h>
+#include <linux/err.h>
#include <linux/io.h>
+#include <mach/init.h>
#include <mach/sc-regs.h>
#include <mach/sg-regs.h>
#undef DPLL_SSC_RATE_1PER
-static void dpll_init(void)
+static int dpll_init(unsigned int dram_freq)
{
u32 tmp;
@@ -22,13 +24,17 @@ static void dpll_init(void)
*/
tmp = readl(SC_DPLLCTRL);
tmp &= ~(0x000f0000);
-#if CONFIG_DDR_FREQ == 1600
- tmp |= 0x000c0000;
-#elif CONFIG_DDR_FREQ == 1333
- tmp |= 0x000d0000;
-#else
-# error "Unsupported frequency"
-#endif
+ switch (dram_freq) {
+ case 1333:
+ tmp |= 0x000d0000;
+ break;
+ case 1600:
+ tmp |= 0x000c0000;
+ break;
+ default:
+ pr_err("Unsupported frequency");
+ return -EINVAL;
+ }
/*
* Set Moduration rate
@@ -44,6 +50,8 @@ static void dpll_init(void)
tmp = readl(SC_DPLLCTRL2);
tmp |= SC_DPLLCTRL2_NRSTDS;
writel(tmp, SC_DPLLCTRL2);
+
+ return 0;
}
static void vpll_init(void)
@@ -54,12 +62,10 @@ static void vpll_init(void)
tmp = readl(SG_PINMON0);
clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
-#if defined(CONFIG_MACH_PH1_PRO4)
/* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
return;
-#endif
/* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
tmp = readl(SC_VPLL27ACTRL);
@@ -138,9 +144,13 @@ static void vpll_init(void)
writel(tmp, SC_VPLL27BCTRL);
}
-void pll_init(void)
+int ph1_pro4_pll_init(const struct uniphier_board_data *bd)
{
- dpll_init();
+ int ret;
+
+ ret = dpll_init(bd->dram_freq);
+ if (ret)
+ return ret;
vpll_init();
/*
@@ -148,4 +158,6 @@ void pll_init(void)
* We wait 1 usec in vpll_init() so 1 usec can be saved here.
*/
udelay(499);
+
+ return 0;
}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/pll_init.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c
index ebd1c31..6294a45 100644
--- a/arch/arm/mach-uniphier/ph1-sld3/pll_init.c
+++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c
@@ -4,7 +4,10 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-void pll_init(void)
+#include <mach/init.h>
+
+int ph1_sld3_pll_init(const struct uniphier_board_data *bd)
{
/* add pll init code here */
+ return 0;
}
diff --git a/arch/arm/mach-uniphier/ph1-sld8/pll_init.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c
index 109cb5f..f249abe 100644
--- a/arch/arm/mach-uniphier/ph1-sld8/pll_init.c
+++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <linux/io.h>
+#include <mach/init.h>
#include <mach/sc-regs.h>
#include <mach/sg-regs.h>
@@ -186,7 +187,7 @@ static void vpll_init(void)
writel(tmp, SC_VPLL27BCTRL);
}
-void pll_init(void)
+int ph1_sld8_pll_init(const struct uniphier_board_data *bd)
{
dpll_init();
upll_init();
@@ -198,4 +199,6 @@ void pll_init(void)
* so 20 usec can be saved here.
*/
udelay(480);
+
+ return 0;
}
diff --git a/arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c
index fcf2ad2..cad0ed8 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c
+++ b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c
@@ -4,15 +4,17 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <common.h>
#include <linux/io.h>
+#include <mach/init.h>
#include <mach/sc-regs.h>
-void enable_dpll_ssc(void)
+int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd)
{
u32 tmp;
tmp = readl(SC_DPLLCTRL);
tmp |= SC_DPLLCTRL_SSC_EN;
writel(tmp, SC_DPLLCTRL);
+
+ return 0;
}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c
index fcf2ad2..43dc973 100644
--- a/arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c
+++ b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c
@@ -6,13 +6,16 @@
#include <common.h>
#include <linux/io.h>
+#include <mach/init.h>
#include <mach/sc-regs.h>
-void enable_dpll_ssc(void)
+int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd)
{
u32 tmp;
tmp = readl(SC_DPLLCTRL);
tmp |= SC_DPLLCTRL_SSC_EN;
writel(tmp, SC_DPLLCTRL);
+
+ return 0;
}
diff --git a/arch/arm/mach-uniphier/print_misc_info.c b/arch/arm/mach-uniphier/print_misc_info.c
index 22ea512..5140b0c 100644
--- a/arch/arm/mach-uniphier/print_misc_info.c
+++ b/arch/arm/mach-uniphier/print_misc_info.c
@@ -5,7 +5,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include <mach/board.h>
+#include <mach/micro-support-card.h>
int misc_init_f(void)
{
diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile
new file mode 100644
index 0000000..db622d2
--- /dev/null
+++ b/arch/arm/mach-uniphier/sbc/Makefile
@@ -0,0 +1,7 @@
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += sbc-ph1-sld3.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += sbc-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += sbc-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += sbc-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += sbc-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) += sbc-proxstream2.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B) += sbc-proxstream2.o
diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c
index 8e25792..929f50a 100644
--- a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c
@@ -6,10 +6,11 @@
#include <common.h>
#include <linux/io.h>
+#include <mach/init.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
-void sbc_init(void)
+int ph1_ld4_sbc_init(const struct uniphier_board_data *bd)
{
u32 tmp;
@@ -30,20 +31,22 @@ void sbc_init(void)
if (boot_is_swapped()) {
/*
* Boot Swap On: boot from external NOR/SRAM
- * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
+ * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
*
- * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
- * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
+ * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
+ * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
} else {
/*
* Boot Swap Off: boot from mask ROM
- * 0x00000000-0x01ffffff: mask ROM
- * 0x02000000-0x03efffff: memory bank (31MB)
- * 0x03f00000-0x03ffffff: peripherals (1MB)
+ * 0x40000000-0x41ffffff: mask ROM
+ * 0x42000000-0x43efffff: memory bank (31MB)
+ * 0x43f00000-0x43ffffff: peripherals (1MB)
*/
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
}
+
+ return 0;
}
diff --git a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c
index 533739c..1032c54 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c
@@ -6,10 +6,11 @@
#include <common.h>
#include <linux/io.h>
+#include <mach/init.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
-void sbc_init(void)
+int ph1_pro4_sbc_init(const struct uniphier_board_data *bd)
{
/*
* Only CS1 is connected to support card.
@@ -23,20 +24,22 @@ void sbc_init(void)
if (boot_is_swapped()) {
/*
* Boot Swap On: boot from external NOR/SRAM
- * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
+ * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
*
- * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
- * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
+ * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
+ * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
} else {
/*
* Boot Swap Off: boot from mask ROM
- * 0x00000000-0x01ffffff: mask ROM
- * 0x02000000-0x03efffff: memory bank (31MB)
- * 0x03f00000-0x03ffffff: peripherals (1MB)
+ * 0x40000000-0x41ffffff: mask ROM
+ * 0x42000000-0x43efffff: memory bank (31MB)
+ * 0x43f00000-0x43ffffff: peripherals (1MB)
*/
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
}
+
+ return 0;
}
diff --git a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c
index d66f89e..fb707be 100644
--- a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c
+++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c
@@ -6,10 +6,11 @@
#include <common.h>
#include <linux/io.h>
+#include <mach/init.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
-void sbc_init(void)
+int ph1_sld3_sbc_init(const struct uniphier_board_data *bd)
{
/* only address/data multiplex mode is supported */
@@ -24,22 +25,24 @@ void sbc_init(void)
if (boot_is_swapped()) {
/*
* Boot Swap On: boot from external NOR/SRAM
- * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
+ * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
*
- * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
- * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
+ * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
+ * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
} else {
/*
* Boot Swap Off: boot from mask ROM
- * 0x00000000-0x01ffffff: mask ROM
- * 0x02000000-0x03efffff: memory bank (31MB)
- * 0x03f00000-0x03ffffff: peripherals (1MB)
+ * 0x40000000-0x41ffffff: mask ROM
+ * 0x42000000-0x43efffff: memory bank (31MB)
+ * 0x43f00000-0x43ffffff: peripherals (1MB)
*/
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
}
- sg_set_pinsel(99, 1); /* GPIO26 -> EA24 */
+ sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */
+
+ return 0;
}
diff --git a/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c b/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c
new file mode 100644
index 0000000..9c3aeb7
--- /dev/null
+++ b/arch/arm/mach-uniphier/sbc/sbc-proxstream2.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <mach/init.h>
+#include <mach/sbc-regs.h>
+#include <mach/sg-regs.h>
+
+int proxstream2_sbc_init(const struct uniphier_board_data *bd)
+{
+ /* necessary for ROM boot ?? */
+ /* system bus output enable */
+ writel(0x17, PC0CTRL);
+
+ /*
+ * Only CS1 is connected to support card.
+ * BKSZ[1:0] should be set to "01".
+ */
+ writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
+ writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
+ writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
+ writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
+
+ if (boot_is_swapped()) {
+ /*
+ * Boot Swap On: boot from external NOR/SRAM
+ * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff.
+ *
+ * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank
+ * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals
+ */
+ writel(0x0000bc01, SBBASE0);
+ } else {
+ /*
+ * Boot Swap Off: boot from mask ROM
+ * 0x40000000-0x41ffffff: mask ROM
+ * 0x42000000-0x43efffff: memory bank (31MB)
+ * 0x43f00000-0x43ffffff: peripherals (1MB)
+ */
+ writel(0x0000be01, SBBASE0); /* dummy */
+ writel(0x0200be01, SBBASE1);
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-uniphier/soc_info.c b/arch/arm/mach-uniphier/soc_info.c
new file mode 100644
index 0000000..3e8e7f4
--- /dev/null
+++ b/arch/arm/mach-uniphier/soc_info.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/io.h>
+#include <linux/types.h>
+#include <mach/sg-regs.h>
+#include <mach/soc_info.h>
+
+#if UNIPHIER_MULTI_SOC
+enum uniphier_soc_id uniphier_get_soc_type(void)
+{
+ u32 revision = readl(SG_REVISION);
+ enum uniphier_soc_id ret;
+
+ switch ((revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT) {
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3
+ case 0x25:
+ ret = SOC_UNIPHIER_PH1_SLD3;
+ break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD4
+ case 0x26:
+ ret = SOC_UNIPHIER_PH1_LD4;
+ break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_PRO4
+ case 0x28:
+ ret = SOC_UNIPHIER_PH1_PRO4;
+ break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD8
+ case 0x29:
+ ret = SOC_UNIPHIER_PH1_SLD8;
+ break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_PRO5
+ case 0x2A:
+ ret = SOC_UNIPHIER_PH1_PRO5;
+ break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PROXSTREAM2
+ case 0x2E:
+ ret = SOC_UNIPHIER_PROXSTREAM2;
+ break;
+#endif
+#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD6B
+ case 0x2F:
+ ret = SOC_UNIPHIER_PH1_LD6B;
+ break;
+#endif
+ default:
+ ret = SOC_UNIPHIER_UNKNOWN;
+ break;
+ }
+
+ return ret;
+}
+#endif
diff --git a/arch/arm/mach-uniphier/spl.c b/arch/arm/mach-uniphier/spl.c
deleted file mode 100644
index a34d3a1..0000000
--- a/arch/arm/mach-uniphier/spl.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2013-2015 Panasonic Corporation
- * Copyright (C) 2015 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/compiler.h>
-#include <mach/led.h>
-#include <mach/board.h>
-
-void __weak bcu_init(void)
-{
-};
-void sbc_init(void);
-void sg_init(void);
-void pll_init(void);
-void pin_init(void);
-void memconf_init(void);
-void early_clkrst_init(void);
-void early_pin_init(void);
-int umc_init(void);
-void enable_dpll_ssc(void);
-
-void spl_board_init(void)
-{
- bcu_init();
-
- sbc_init();
-
- sg_init();
-
- uniphier_board_reset();
-
- pll_init();
-
- uniphier_board_init();
-
- led_write(L, 0, , );
-
- memconf_init();
-
- led_write(L, 1, , );
-
- early_clkrst_init();
-
- led_write(L, 2, , );
-
- early_pin_init();
-
- led_write(L, 3, , );
-
-#ifdef CONFIG_SPL_SERIAL_SUPPORT
- preloader_console_init();
-#endif
-
- led_write(L, 4, , );
-
- {
- int res;
-
- res = umc_init();
- if (res < 0) {
- while (1)
- ;
- }
- }
- led_write(L, 5, , );
-
- enable_dpll_ssc();
-
- led_write(L, 6, , );
-}
diff --git a/arch/arm/mach-uniphier/umc/Makefile b/arch/arm/mach-uniphier/umc/Makefile
new file mode 100644
index 0000000..dd35e77
--- /dev/null
+++ b/arch/arm/mach-uniphier/umc/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o
diff --git a/arch/arm/mach-uniphier/ph1-ld4/umc_init.c b/arch/arm/mach-uniphier/umc/umc-ph1-ld4.c
index a7a4157..8124685 100644
--- a/arch/arm/mach-uniphier/ph1-ld4/umc_init.c
+++ b/arch/arm/mach-uniphier/umc/umc-ph1-ld4.c
@@ -5,7 +5,10 @@
*/
#include <common.h>
+#include <linux/err.h>
#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach/init.h>
#include <mach/umc-regs.h>
#include <mach/ddrphy-regs.h>
@@ -136,14 +139,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
- ddrphy_init(phy0_0, freq, size_ch0);
+ ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0);
ddrphy_prepare_training(phy0_0, 0);
ddrphy_training(phy0_0);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
- ddrphy_init(phy1_0, freq, size_ch1);
+ ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1);
ddrphy_prepare_training(phy1_0, 1);
ddrphy_training(phy1_0);
@@ -156,16 +159,17 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
return 0;
}
-int umc_init(void)
+int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
{
- return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
- CONFIG_SDRAM1_SIZE / 0x08000000);
+ if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
+ (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
+ (bd->dram_freq == 1333 || bd->dram_freq == 1600) &&
+ bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
+ return umc_init_sub(bd->dram_freq,
+ bd->dram_ch0_size / SZ_128M,
+ bd->dram_ch1_size / SZ_128M);
+ } else {
+ pr_err("Unsupported DDR configuration\n");
+ return -EINVAL;
+ }
}
-
-#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
- (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
- CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
-/* OK */
-#else
-#error Unsupported DDR configuration.
-#endif
diff --git a/arch/arm/mach-uniphier/ph1-pro4/umc_init.c b/arch/arm/mach-uniphier/umc/umc-ph1-pro4.c
index bd8b9d8..8c9f057 100644
--- a/arch/arm/mach-uniphier/ph1-pro4/umc_init.c
+++ b/arch/arm/mach-uniphier/umc/umc-ph1-pro4.c
@@ -5,7 +5,10 @@
*/
#include <common.h>
+#include <linux/err.h>
#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach/init.h>
#include <mach/umc-regs.h>
#include <mach/ddrphy-regs.h>
@@ -107,28 +110,28 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
- ddrphy_init(phy0_0, freq, size_ch0);
+ ph1_pro4_ddrphy_init(phy0_0, freq, size_ch0);
ddrphy_prepare_training(phy0_0, 0);
ddrphy_training(phy0_0);
writel(0x00000103, dramcont0 + UMC_DIOCTLA);
- ddrphy_init(phy0_1, freq, size_ch0);
+ ph1_pro4_ddrphy_init(phy0_1, freq, size_ch0);
ddrphy_prepare_training(phy0_1, 1);
ddrphy_training(phy0_1);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
- ddrphy_init(phy1_0, freq, size_ch1);
+ ph1_pro4_ddrphy_init(phy1_0, freq, size_ch1);
ddrphy_prepare_training(phy1_0, 0);
ddrphy_training(phy1_0);
writel(0x00000103, dramcont1 + UMC_DIOCTLA);
- ddrphy_init(phy1_1, freq, size_ch1);
+ ph1_pro4_ddrphy_init(phy1_1, freq, size_ch1);
ddrphy_prepare_training(phy1_1, 1);
ddrphy_training(phy1_1);
@@ -141,17 +144,18 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
return 0;
}
-int umc_init(void)
+int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
{
- return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
- CONFIG_SDRAM1_SIZE / 0x08000000);
+ if (((bd->dram_ch0_size == SZ_512M && bd->dram_ch0_width == 32) ||
+ (bd->dram_ch0_size == SZ_256M && bd->dram_ch0_width == 16)) &&
+ ((bd->dram_ch1_size == SZ_512M && bd->dram_ch1_width == 32) ||
+ (bd->dram_ch1_size == SZ_256M && bd->dram_ch1_width == 16)) &&
+ bd->dram_freq == 1600) {
+ return umc_init_sub(bd->dram_freq,
+ bd->dram_ch0_size / SZ_128M,
+ bd->dram_ch1_size / SZ_128M);
+ } else {
+ pr_err("Unsupported DDR configuration\n");
+ return -EINVAL;
+ }
}
-
-#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \
- (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \
- ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \
- (CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1))
-/* OK */
-#else
- #error Unsupported DDR configuration.
-#endif
diff --git a/arch/arm/mach-uniphier/ph1-sld8/umc_init.c b/arch/arm/mach-uniphier/umc/umc-ph1-sld8.c
index 7baea7e..bc60a34 100644
--- a/arch/arm/mach-uniphier/ph1-sld8/umc_init.c
+++ b/arch/arm/mach-uniphier/umc/umc-ph1-sld8.c
@@ -5,7 +5,10 @@
*/
#include <common.h>
+#include <linux/err.h>
#include <linux/io.h>
+#include <linux/sizes.h>
+#include <mach/init.h>
#include <mach/umc-regs.h>
#include <mach/ddrphy-regs.h>
@@ -116,14 +119,14 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
writel(0x00000101, dramcont0 + UMC_DIOCTLA);
- ddrphy_init(phy0_0, freq, size_ch0);
+ ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0);
ddrphy_prepare_training(phy0_0, 0);
ddrphy_training(phy0_0);
writel(0x00000101, dramcont1 + UMC_DIOCTLA);
- ddrphy_init(phy1_0, freq, size_ch1);
+ ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1);
ddrphy_prepare_training(phy1_0, 1);
ddrphy_training(phy1_0);
@@ -136,16 +139,17 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
return 0;
}
-int umc_init(void)
+int ph1_sld8_umc_init(const struct uniphier_board_data *bd)
{
- return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000,
- CONFIG_SDRAM1_SIZE / 0x08000000);
+ if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) &&
+ (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) &&
+ bd->dram_freq == 1333 &&
+ bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) {
+ return umc_init_sub(bd->dram_freq,
+ bd->dram_ch0_size / SZ_128M,
+ bd->dram_ch1_size / SZ_128M);
+ } else {
+ pr_err("Unsupported DDR configuration\n");
+ return -EINVAL;
+ }
}
-
-#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \
- (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \
- CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1
-/* OK */
-#else
-#error Unsupported DDR configuration.
-#endif
diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
deleted file mode 100644
index d2e76f4..0000000
--- a/arch/arm/mach-versatile/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if ARCH_VERSATILE
-
-config SYS_BOARD
- default "versatile"
-
-config SYS_VENDOR
- default "armltd"
-
-config SYS_SOC
- default "versatile"
-
-config SYS_CONFIG_NAME
- default "versatile"
-
-endif
diff --git a/arch/arm/mach-zynq/include/mach/gpio.h b/arch/arm/mach-zynq/include/mach/gpio.h
index 9e1e7da..0789c49 100644
--- a/arch/arm/mach-zynq/include/mach/gpio.h
+++ b/arch/arm/mach-zynq/include/mach/gpio.h
@@ -71,6 +71,4 @@
/* GPIO upper 16 bit mask */
#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
-#define BIT(x) (1<<x)
-
#endif /* _ZYNQ_GPIO_H */
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 23ecc89..ce58d86 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -8,6 +8,9 @@ choice
prompt "Target select"
optional
+config TARGET_LWMON5
+ bool "Support lwmon5"
+
config TARGET_T3CORP
bool "Support t3corp"
@@ -165,6 +168,7 @@ source "board/gdsys/405ex/Kconfig"
source "board/gdsys/dlvision/Kconfig"
source "board/gdsys/gdppc440etx/Kconfig"
source "board/gdsys/intip/Kconfig"
+source "board/lwmon5/Kconfig"
source "board/mosaixtech/icon/Kconfig"
source "board/mpl/mip405/Kconfig"
source "board/mpl/pip405/Kconfig"
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 2527ef8..4090975 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -106,6 +106,12 @@ struct arch_global_data {
#ifdef CONFIG_SYS_FPGA_COUNT
unsigned fpga_state[CONFIG_SYS_FPGA_COUNT];
#endif
+#if defined(CONFIG_WD_MAX_RATE)
+ unsigned long long wdt_last; /* trace watch-dog triggering rate */
+#endif
+#if defined(CONFIG_LWMON5)
+ unsigned long kbd_status;
+#endif
};
#include <asm-generic/global_data.h>
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 65b9125..08f72ac 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -153,6 +153,10 @@
};
};
+ reset@1 {
+ compatible = "sandbox,reset";
+ };
+
spi@0 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/x86/cpu/quark/dram.c b/arch/x86/cpu/quark/dram.c
index 9cac846..1b89376 100644
--- a/arch/x86/cpu/quark/dram.c
+++ b/arch/x86/cpu/quark/dram.c
@@ -7,8 +7,10 @@
#include <common.h>
#include <errno.h>
#include <fdtdec.h>
+#include <asm/mtrr.h>
#include <asm/post.h>
#include <asm/arch/mrc.h>
+#include <asm/arch/msg_port.h>
#include <asm/arch/quark.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -111,6 +113,14 @@ int dram_init(void)
gd->ram_size = mrc_params.mem_size;
post_code(POST_DRAM);
+ /* variable range MTRR#2: RAM area */
+ disable_caches();
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM),
+ 0 | MTRR_TYPE_WRBACK);
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM),
+ (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID);
+ enable_caches();
+
return 0;
}
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 637c370..77d644a 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -6,10 +6,9 @@
#include <common.h>
#include <mmc.h>
-#include <netdev.h>
-#include <phy.h>
#include <asm/io.h>
#include <asm/irq.h>
+#include <asm/mtrr.h>
#include <asm/pci.h>
#include <asm/post.h>
#include <asm/processor.h>
@@ -36,6 +35,55 @@ static void unprotect_spi_flash(void)
qrk_pci_write_config_dword(QUARK_LEGACY_BRIDGE, 0xd8, bc);
}
+static void quark_setup_mtrr(void)
+{
+ u32 base, mask;
+ int i;
+
+ disable_caches();
+
+ /* mark the VGA RAM area as uncacheable */
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_A0000,
+ MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_B0000,
+ MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
+
+ /* mark other fixed range areas as cacheable */
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_00000,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_64K_40000,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_80000,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_FIX_16K_90000,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+ for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_FC000; i++)
+ msg_port_write(MSG_PORT_HOST_BRIDGE, i,
+ MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+
+ /* variable range MTRR#0: ROM area */
+ mask = ~(CONFIG_SYS_MONITOR_LEN - 1);
+ base = CONFIG_SYS_TEXT_BASE & mask;
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ROM),
+ base | MTRR_TYPE_WRBACK);
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ROM),
+ mask | MTRR_PHYS_MASK_VALID);
+
+ /* variable range MTRR#1: eSRAM area */
+ mask = ~(ESRAM_SIZE - 1);
+ base = CONFIG_ESRAM_BASE & mask;
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_ESRAM),
+ base | MTRR_TYPE_WRBACK);
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_ESRAM),
+ mask | MTRR_PHYS_MASK_VALID);
+
+ /* enable both variable and fixed range MTRRs */
+ msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_DEF_TYPE,
+ MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN);
+
+ enable_caches();
+}
+
static void quark_setup_bars(void)
{
/* GPIO - D31:F0:R44h */
@@ -75,8 +123,6 @@ static void quark_setup_bars(void)
static void quark_pcie_early_init(void)
{
- u32 pcie_cfg;
-
/*
* Step1: Assert PCIe signal PERST#
*
@@ -86,23 +132,18 @@ static void quark_pcie_early_init(void)
board_assert_perst();
/* Step2: PHY common lane reset */
- pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
- pcie_cfg |= PCIE_PHY_LANE_RST;
- msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
+ msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_PHY_LANE_RST);
/* wait 1 ms for PHY common lane reset */
mdelay(1);
/* Step3: PHY sideband interface reset and controller main reset */
- pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
- pcie_cfg |= (PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST);
- msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
+ msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG,
+ PCIE_PHY_SB_RST | PCIE_CTLR_MAIN_RST);
/* wait 80ms for PLL to lock */
mdelay(80);
/* Step4: Controller sideband interface reset */
- pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
- pcie_cfg |= PCIE_CTLR_SB_RST;
- msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
+ msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_SB_RST);
/* wait 20ms for controller sideband interface reset */
mdelay(20);
@@ -110,66 +151,80 @@ static void quark_pcie_early_init(void)
board_deassert_perst();
/* Step6: Controller primary interface reset */
- pcie_cfg = msg_port_alt_read(MSG_PORT_SOC_UNIT, PCIE_CFG);
- pcie_cfg |= PCIE_CTLR_PRI_RST;
- msg_port_alt_write(MSG_PORT_SOC_UNIT, PCIE_CFG, pcie_cfg);
+ msg_port_alt_setbits(MSG_PORT_SOC_UNIT, PCIE_CFG, PCIE_CTLR_PRI_RST);
/* Mixer Load Lane 0 */
- pcie_cfg = msg_port_io_read(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0);
- pcie_cfg &= ~((1 << 6) | (1 << 7));
- msg_port_io_write(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0, pcie_cfg);
+ msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L0,
+ (1 << 6) | (1 << 7));
/* Mixer Load Lane 1 */
- pcie_cfg = msg_port_io_read(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1);
- pcie_cfg &= ~((1 << 6) | (1 << 7));
- msg_port_io_write(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1, pcie_cfg);
+ msg_port_io_clrbits(MSG_PORT_PCIE_AFE, PCIE_RXPICTRL0_L1,
+ (1 << 6) | (1 << 7));
}
static void quark_usb_early_init(void)
{
- u32 usb;
-
/* The sequence below comes from Quark firmware writer guide */
- usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT);
- usb &= ~(1 << 1);
- usb |= ((1 << 6) | (1 << 7));
- msg_port_alt_write(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT, usb);
+ msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_GLOBAL_PORT,
+ 1 << 1, (1 << 6) | (1 << 7));
- usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_COMPBG);
- usb &= ~((1 << 8) | (1 << 9));
- usb |= ((1 << 7) | (1 << 10));
- msg_port_alt_write(MSG_PORT_USB_AFE, USB2_COMPBG, usb);
+ msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_COMPBG,
+ (1 << 8) | (1 << 9), (1 << 7) | (1 << 10));
- usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL2);
- usb |= (1 << 29);
- msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL2, usb);
+ msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
- usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL1);
- usb |= (1 << 1);
- msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL1, usb);
+ msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL1, 1 << 1);
- usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL1);
- usb &= ~((1 << 3) | (1 << 4) | (1 << 5));
- usb |= (1 << 6);
- msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL1, usb);
+ msg_port_alt_clrsetbits(MSG_PORT_USB_AFE, USB2_PLL1,
+ (1 << 3) | (1 << 4) | (1 << 5), 1 << 6);
- usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL2);
- usb &= ~(1 << 29);
- msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL2, usb);
+ msg_port_alt_clrbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 29);
- usb = msg_port_alt_read(MSG_PORT_USB_AFE, USB2_PLL2);
- usb |= (1 << 24);
- msg_port_alt_write(MSG_PORT_USB_AFE, USB2_PLL2, usb);
+ msg_port_alt_setbits(MSG_PORT_USB_AFE, USB2_PLL2, 1 << 24);
}
-static void quark_enable_legacy_seg(void)
+static void quark_thermal_early_init(void)
{
- u32 hmisc2;
+ /* The sequence below comes from Quark firmware writer guide */
+
+ /* thermal sensor mode config */
+ msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
+ (1 << 3) | (1 << 4) | (1 << 5), 1 << 5);
+ msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG1,
+ (1 << 8) | (1 << 9) | (1 << 10) | (1 << 11) |
+ (1 << 12), 1 << 9);
+ msg_port_alt_setbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 14);
+ msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 17);
+ msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG1, 1 << 18);
+ msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG2, 0xffff, 0x011f);
+ msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff, 0x17);
+ msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG3,
+ (1 << 8) | (1 << 9), 1 << 8);
+ msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG3, 0xff000000);
+ msg_port_alt_clrsetbits(MSG_PORT_SOC_UNIT, TS_CFG4,
+ 0x7ff800, 0xc8 << 11);
+
+ /* thermal monitor catastrophic trip set point (105 celsius) */
+ msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff, 155);
+
+ /* thermal monitor catastrophic trip clear point (0 celsius) */
+ msg_port_clrsetbits(MSG_PORT_RMU, TS_TRIP, 0xff0000, 50 << 16);
+
+ /* take thermal sensor out of reset */
+ msg_port_alt_clrbits(MSG_PORT_SOC_UNIT, TS_CFG4, 1 << 0);
+
+ /* enable thermal monitor */
+ msg_port_setbits(MSG_PORT_RMU, TS_MODE, 1 << 15);
+
+ /* lock all thermal configuration */
+ msg_port_setbits(MSG_PORT_RMU, RMU_CTRL, (1 << 5) | (1 << 6));
+}
- hmisc2 = msg_port_read(MSG_PORT_HOST_BRIDGE, HMISC2);
- hmisc2 |= (HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
- msg_port_write(MSG_PORT_HOST_BRIDGE, HMISC2, hmisc2);
+static void quark_enable_legacy_seg(void)
+{
+ msg_port_setbits(MSG_PORT_HOST_BRIDGE, HMISC2,
+ HMISC2_SEGE | HMISC2_SEGF | HMISC2_SEGAB);
}
int arch_cpu_init(void)
@@ -186,6 +241,13 @@ int arch_cpu_init(void)
return ret;
/*
+ * Quark SoC does not support MSR MTRRs. Fixed and variable range MTRRs
+ * are accessed indirectly via the message port and not the traditional
+ * MSR mechanism. Only UC, WT and WB cache types are supported.
+ */
+ quark_setup_mtrr();
+
+ /*
* Quark SoC has some non-standard BARs (excluding PCI standard BARs)
* which need be initialized with suggested values
*/
@@ -205,6 +267,9 @@ int arch_cpu_init(void)
/* Initialize USB2 PHY */
quark_usb_early_init();
+ /* Initialize thermal sensor */
+ quark_thermal_early_init();
+
/* Turn on legacy segments (A/B/E/F) decode to system RAM */
quark_enable_legacy_seg();
@@ -225,27 +290,57 @@ void reset_cpu(ulong addr)
x86_full_reset();
}
-int cpu_mmc_init(bd_t *bis)
+static void quark_pcie_init(void)
{
- return pci_mmc_init("Quark SDHCI", mmc_supported,
- ARRAY_SIZE(mmc_supported));
+ u32 val;
+
+ /* PCIe upstream non-posted & posted request size */
+ qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_CCFG,
+ CCFG_UPRS | CCFG_UNRS);
+ qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_CCFG,
+ CCFG_UPRS | CCFG_UNRS);
+
+ /* PCIe packet fast transmit mode (IPF) */
+ qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MPC2, MPC2_IPF);
+ qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MPC2, MPC2_IPF);
+
+ /* PCIe message bus idle counter (SBIC) */
+ qrk_pci_read_config_dword(QUARK_PCIE0, PCIE_RP_MBC, &val);
+ val |= MBC_SBIC;
+ qrk_pci_write_config_dword(QUARK_PCIE0, PCIE_RP_MBC, val);
+ qrk_pci_read_config_dword(QUARK_PCIE1, PCIE_RP_MBC, &val);
+ val |= MBC_SBIC;
+ qrk_pci_write_config_dword(QUARK_PCIE1, PCIE_RP_MBC, val);
}
-int cpu_eth_init(bd_t *bis)
+static void quark_usb_init(void)
{
- u32 base;
- int ret0, ret1;
+ u32 bar;
- qrk_pci_read_config_dword(QUARK_EMAC0, PCI_BASE_ADDRESS_0, &base);
- ret0 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
+ /* Change USB EHCI packet buffer OUT/IN threshold */
+ qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar);
+ writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01);
- qrk_pci_read_config_dword(QUARK_EMAC1, PCI_BASE_ADDRESS_0, &base);
- ret1 = designware_initialize(base, PHY_INTERFACE_MODE_RMII);
+ /* Disable USB device interrupts */
+ qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar);
+ writel(0x7f, bar + USBD_INT_MASK);
+ writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK);
+ writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS);
+}
- if (ret0 < 0 && ret1 < 0)
- return -1;
- else
- return 0;
+int arch_early_init_r(void)
+{
+ quark_pcie_init();
+
+ quark_usb_init();
+
+ return 0;
+}
+
+int cpu_mmc_init(bd_t *bis)
+{
+ return pci_mmc_init("Quark SDHCI", mmc_supported,
+ ARRAY_SIZE(mmc_supported));
}
void cpu_irq_init(void)
@@ -275,3 +370,23 @@ int arch_misc_init(void)
{
return pirq_init();
}
+
+void board_final_cleanup(void)
+{
+ struct quark_rcba *rcba;
+ u32 base, val;
+
+ qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, &base);
+ base &= ~MEM_BAR_EN;
+ rcba = (struct quark_rcba *)base;
+
+ /* Initialize 'Component ID' to zero */
+ val = readl(&rcba->esd);
+ val &= ~0xff0000;
+ writel(val, &rcba->esd);
+
+ /* Lock HMBOUND for security */
+ msg_port_setbits(MSG_PORT_HOST_BRIDGE, HM_BOUND, HM_BOUND_LOCK);
+
+ return;
+}
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index f119bf7..a4e1676 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -92,6 +92,18 @@
PCI_BDF(0, 21, 0) INTA PIRQE
PCI_BDF(0, 21, 1) INTB PIRQF
PCI_BDF(0, 21, 2) INTC PIRQG
+ PCI_BDF(0, 23, 0) INTA PIRQA
+ PCI_BDF(0, 23, 1) INTB PIRQB
+
+ /* PCIe root ports downstream interrupts */
+ PCI_BDF(1, 0, 0) INTA PIRQA
+ PCI_BDF(1, 0, 0) INTB PIRQB
+ PCI_BDF(1, 0, 0) INTC PIRQC
+ PCI_BDF(1, 0, 0) INTD PIRQD
+ PCI_BDF(2, 0, 0) INTA PIRQB
+ PCI_BDF(2, 0, 0) INTB PIRQC
+ PCI_BDF(2, 0, 0) INTC PIRQD
+ PCI_BDF(2, 0, 0) INTD PIRQA
>;
};
};
diff --git a/arch/x86/include/asm/arch-quark/msg_port.h b/arch/x86/include/asm/arch-quark/msg_port.h
index 2e78a66..313e23f 100644
--- a/arch/x86/include/asm/arch-quark/msg_port.h
+++ b/arch/x86/include/asm/arch-quark/msg_port.h
@@ -101,6 +101,37 @@ u32 msg_port_io_read(u8 port, u32 reg);
*/
void msg_port_io_write(u8 port, u32 reg, u32 value);
+/* clrbits, setbits, clrsetbits macros for message port access */
+
+#define msg_port_normal_read msg_port_read
+#define msg_port_normal_write msg_port_write
+
+#define msg_port_generic_clrsetbits(type, port, reg, clr, set) \
+ msg_port_##type##_write(port, reg, \
+ (msg_port_##type##_read(port, reg) \
+ & ~(clr)) | (set))
+
+#define msg_port_clrbits(port, reg, clr) \
+ msg_port_generic_clrsetbits(normal, port, reg, clr, 0)
+#define msg_port_setbits(port, reg, set) \
+ msg_port_generic_clrsetbits(normal, port, reg, 0, set)
+#define msg_port_clrsetbits(port, reg, clr, set) \
+ msg_port_generic_clrsetbits(normal, port, reg, clr, set)
+
+#define msg_port_alt_clrbits(port, reg, clr) \
+ msg_port_generic_clrsetbits(alt, port, reg, clr, 0)
+#define msg_port_alt_setbits(port, reg, set) \
+ msg_port_generic_clrsetbits(alt, port, reg, 0, set)
+#define msg_port_alt_clrsetbits(port, reg, clr, set) \
+ msg_port_generic_clrsetbits(alt, port, reg, clr, set)
+
+#define msg_port_io_clrbits(port, reg, clr) \
+ msg_port_generic_clrsetbits(io, port, reg, clr, 0)
+#define msg_port_io_setbits(port, reg, set) \
+ msg_port_generic_clrsetbits(io, port, reg, 0, set)
+#define msg_port_io_clrsetbits(port, reg, clr, set) \
+ msg_port_generic_clrsetbits(io, port, reg, clr, set)
+
#endif /* __ASSEMBLY__ */
#endif /* _QUARK_MSG_PORT_H_ */
diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h
index 5d81976..7a864c7 100644
--- a/arch/x86/include/asm/arch-quark/quark.h
+++ b/arch/x86/include/asm/arch-quark/quark.h
@@ -32,18 +32,71 @@
/* Host Memory I/O Boundary */
#define HM_BOUND 0x08
+#define HM_BOUND_LOCK 0x00000001
/* Extended Configuration Space */
#define HEC_REG 0x09
+/* MTRR Registers */
+#define MTRR_CAP 0x40
+#define MTRR_DEF_TYPE 0x41
+
+#define MTRR_FIX_64K_00000 0x42
+#define MTRR_FIX_64K_40000 0x43
+#define MTRR_FIX_16K_80000 0x44
+#define MTRR_FIX_16K_90000 0x45
+#define MTRR_FIX_16K_A0000 0x46
+#define MTRR_FIX_16K_B0000 0x47
+#define MTRR_FIX_4K_C0000 0x48
+#define MTRR_FIX_4K_C4000 0x49
+#define MTRR_FIX_4K_C8000 0x4a
+#define MTRR_FIX_4K_CC000 0x4b
+#define MTRR_FIX_4K_D0000 0x4c
+#define MTRR_FIX_4K_D4000 0x4d
+#define MTRR_FIX_4K_D8000 0x4e
+#define MTRR_FIX_4K_DC000 0x4f
+#define MTRR_FIX_4K_E0000 0x50
+#define MTRR_FIX_4K_E4000 0x51
+#define MTRR_FIX_4K_E8000 0x52
+#define MTRR_FIX_4K_EC000 0x53
+#define MTRR_FIX_4K_F0000 0x54
+#define MTRR_FIX_4K_F4000 0x55
+#define MTRR_FIX_4K_F8000 0x56
+#define MTRR_FIX_4K_FC000 0x57
+
+#define MTRR_SMRR_PHYBASE 0x58
+#define MTRR_SMRR_PHYMASK 0x59
+
+#define MTRR_VAR_PHYBASE(n) (0x5a + 2 * (n))
+#define MTRR_VAR_PHYMASK(n) (0x5b + 2 * (n))
+
+#ifndef __ASSEMBLY__
+
+/* variable range MTRR usage */
+enum {
+ MTRR_VAR_ROM,
+ MTRR_VAR_ESRAM,
+ MTRR_VAR_RAM
+};
+
+#endif /* __ASSEMBLY__ */
+
/* Port 0x04: Remote Management Unit Message Port Registers */
/* ACPI PBLK Base Address Register */
#define PBLK_BA 0x70
+/* Control Register */
+#define RMU_CTRL 0x71
+
/* SPI DMA Base Address Register */
#define SPI_DMA_BA 0x7a
+/* Thermal Sensor Register */
+#define TS_MODE 0xb0
+#define TS_TEMP 0xb1
+#define TS_TRIP 0xb2
+
/* Port 0x05: Memory Manager Message Port Registers */
/* eSRAM Block Page Control */
@@ -64,6 +117,12 @@
/* Port 0x31: SoC Unit Port Registers */
+/* Thermal Sensor Config */
+#define TS_CFG1 0x31
+#define TS_CFG2 0x32
+#define TS_CFG3 0x33
+#define TS_CFG4 0x34
+
/* PCIe Controller Config */
#define PCIE_CFG 0x36
#define PCIE_CTLR_PRI_RST 0x00010000
@@ -88,6 +147,20 @@
/* 64KiB of RMU binary in flash */
#define RMU_BINARY_SIZE 0x10000
+/* PCIe Root Port Configuration Registers */
+
+#define PCIE_RP_CCFG 0xd0
+#define CCFG_UPRS (1 << 14)
+#define CCFG_UNRS (1 << 15)
+#define CCFG_UNSD (1 << 23)
+#define CCFG_UPSD (1 << 24)
+
+#define PCIE_RP_MPC2 0xd4
+#define MPC2_IPF (1 << 11)
+
+#define PCIE_RP_MBC 0xf4
+#define MBC_SBIC (3 << 16)
+
/* Legacy Bridge PCI Configuration Registers */
#define LB_GBA 0x44
#define LB_PM1BLK 0x48
@@ -100,6 +173,14 @@
#define LB_BC 0xd8
#define LB_RCBA 0xf0
+/* USB EHCI memory-mapped registers */
+#define EHCI_INSNREG01 0x94
+
+/* USB device memory-mapped registers */
+#define USBD_INT_MASK 0x410
+#define USBD_EP_INT_STS 0x414
+#define USBD_EP_INT_MASK 0x418
+
#ifndef __ASSEMBLY__
/* Root Complex Register Block */
diff --git a/arch/x86/lib/fsp/fsp_dram.c b/arch/x86/lib/fsp/fsp_dram.c
index 28552fa..e51ca96 100644
--- a/arch/x86/lib/fsp/fsp_dram.c
+++ b/arch/x86/lib/fsp/fsp_dram.c
@@ -72,9 +72,10 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *entries)
entries[num_entries].type = E820_RAM;
else if (res_desc->type == RES_MEM_RESERVED)
entries[num_entries].type = E820_RESERVED;
+
+ num_entries++;
}
hdr = get_next_hob(hdr);
- num_entries++;
}
/* Mark PCIe ECAM address range as reserved */