diff options
Diffstat (limited to 'arch')
46 files changed, 1608 insertions, 119 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 2528f50..02e887a 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -34,6 +34,7 @@ config M68K config MICROBLAZE bool "MicroBlaze architecture" select SUPPORT_OF_CONTROL + imply CMD_IRQ config MIPS bool "MIPS architecture" @@ -43,6 +44,7 @@ config MIPS config NDS32 bool "NDS32 architecture" + select SUPPORT_OF_CONTROL config NIOS2 bool "Nios II architecture" @@ -68,6 +70,12 @@ config SANDBOX select DM_SPI select DM_GPIO select DM_MMC + imply CMD_GETTIME + imply CMD_HASH + imply CMD_IO + imply CMD_IOTRACE + imply LZMA + imply CMD_LZMADEC config SH bool "SuperH architecture" @@ -86,6 +94,10 @@ config X86 select DM_SPI_FLASH select USB_EHCI_HCD select DM_MMC if MMC + imply CMD_FPGA_LOADMK + imply CMD_GETTIME + imply CMD_IO + imply CMD_IRQ config XTENSA bool "Xtensa architecture" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a17ba2c..2a3a36e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -281,6 +281,7 @@ choice config ARCH_AT91 bool "Atmel AT91" + select SPL_BOARD_INIT if SPL config TARGET_EDB93XX bool "Support edb93xx" @@ -502,6 +503,7 @@ config TARGET_BCM28155_AP config TARGET_BCMCYGNUS bool "Support bcmcygnus" select CPU_V7 + imply CMD_HASH config TARGET_BCMNSP bool "Support bcmnsp" @@ -553,6 +555,7 @@ config ARCH_KEYSTONE config ARCH_OMAP2PLUS bool "TI OMAP2+" select CPU_V7 + select SPL_BOARD_INIT if SPL select SUPPORT_SPL imply FIT @@ -674,6 +677,7 @@ config ARCH_ZYNQ select CPU_V7 select SUPPORT_SPL select OF_CONTROL + select SPL_BOARD_INIT if SPL select SPL_OF_CONTROL if SPL select DM select DM_ETH @@ -701,6 +705,7 @@ config ARCH_ZYNQMP select DM_SERIAL select SUPPORT_SPL select CLK + select SPL_BOARD_INIT if SPL select SPL_CLK select DM_USB if USB @@ -943,6 +948,7 @@ config ARCH_UNIPHIER select OF_CONTROL select OF_LIBFDT select PINCTRL + select SPL_BOARD_INIT if SPL select SPL_DM if SPL select SPL_LIBCOMMON_SUPPORT if SPL select SPL_LIBGENERIC_SUPPORT if SPL diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 0ff9045..4fd60d4 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -7,6 +7,7 @@ config MX6 select ARM_ERRATA_751472 if !MX6UL select ARM_ERRATA_761320 if !MX6UL select ARM_ERRATA_794072 if !MX6UL + imply CMD_FUSE config MX6D bool diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig index 8dfb4c9..80c1290 100644 --- a/arch/arm/cpu/armv7/mx7/Kconfig +++ b/arch/arm/cpu/armv7/mx7/Kconfig @@ -6,10 +6,12 @@ config MX7 select CPU_V7_HAS_VIRT select CPU_V7_HAS_NONSEC select ARCH_SUPPORT_PSCI + imply CMD_FUSE default y config MX7D select ROM_UNIFIED_SECTIONS + imply CMD_FUSE bool choice diff --git a/arch/arm/imx-common/Kconfig b/arch/arm/imx-common/Kconfig index 25cbd12..cd8b8d2 100644 --- a/arch/arm/imx-common/Kconfig +++ b/arch/arm/imx-common/Kconfig @@ -55,3 +55,9 @@ config CMD_DEKBLOB Freescale secure boot mechanism. This command encapsulates and creates a blob of data. See also CMD_BLOB and doc/README.mxc_hab for more information. + +config CMD_HDMIDETECT + bool "Support the 'hdmidet' command" + help + This enables the 'hdmidet' command which detects if an HDMI monitor + is connected. diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index b0ca4bc..b0b3b93 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -8,12 +8,8 @@ #define __FSL_SECURE_BOOT_H #ifdef CONFIG_CHAIN_OF_TRUST -#define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_FSL_SEC_MON -#define CONFIG_SHA_HW_ACCEL -#define CONFIG_SHA_PROG_HW_ACCEL -#define CONFIG_SPL_BOARD_INIT #ifdef CONFIG_SPL_BUILD /* * Define the key hash for U-Boot here if public/private key pair used to @@ -30,7 +26,6 @@ #define CONFIG_KEY_REVOCATION #ifndef CONFIG_SPL_BUILD -#define CONFIG_CMD_HASH #ifndef CONFIG_SYS_RAMBOOT /* The key used for verification of next level images * is picked up from an Extension Table which has diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 46981a5..5b6c5ea 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -17,6 +17,8 @@ config ARCH_EXYNOS5 bool "Exynos5 SoC family" select CPU_V7 select BOARD_EARLY_INIT_F + select SHA_HW_ACCEL + imply CMD_HASH help Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index 3ea8dc3..cababdb 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig @@ -6,19 +6,23 @@ choice config TARGET_K2HK_EVM bool "TI Keystone 2 Kepler/Hawking EVM" + select SPL_BOARD_INIT if SPL imply DM_I2C config TARGET_K2E_EVM bool "TI Keystone 2 Edison EVM" + select SPL_BOARD_INIT if SPL imply DM_I2C config TARGET_K2L_EVM bool "TI Keystone 2 Lamar EVM" + select SPL_BOARD_INIT if SPL imply DM_I2C config TARGET_K2G_EVM bool "TI Keystone 2 Galileo EVM" select BOARD_LATE_INIT + select SPL_BOARD_INIT if SPL select TI_I2C_BOARD_DETECT imply DM_I2C diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index c7beb58..ba60071 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -95,7 +95,7 @@ /* * IDE Support on SATA ports */ -#ifdef CONFIG_CMD_IDE +#ifdef CONFIG_IDE #define __io #define CONFIG_MVSATA_IDE #define CONFIG_IDE_PREINIT @@ -110,12 +110,12 @@ #define CONFIG_SYS_ATA_STRIDE 4 /* Controller supports 48-bits LBA addressing */ #define CONFIG_LBA48 -/* CONFIG_CMD_IDE requires some #defines for ATA registers */ +/* CONFIG_IDE requires some #defines for ATA registers */ #define CONFIG_SYS_IDE_MAXBUS 2 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* ATA registers base is at SATA controller base */ #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE -#endif /* CONFIG_CMD_IDE */ +#endif /* CONFIG_IDE */ /* * I2C related stuff diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 740dbdf..6be2ab5 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -14,6 +14,7 @@ config ROCKCHIP_RK3036 config ROCKCHIP_RK3188 bool "Support Rockchip RK3188" select CPU_V7 + select SPL_BOARD_INIT if SPL select SUPPORT_SPL select SUPPORT_TPL select SPL @@ -30,6 +31,7 @@ config ROCKCHIP_RK3188 config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7 + select SPL_BOARD_INIT if SPL select SUPPORT_SPL select SPL help diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 2563e79..45e5379 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -39,6 +39,7 @@ config TARGET_SOCFPGA_ARRIA5 config TARGET_SOCFPGA_ARRIA10 bool + select SPL_BOARD_INIT if SPL config TARGET_SOCFPGA_CYCLONE5 bool diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index c67ffa5..940257b 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -49,6 +49,7 @@ config TEGRA_ARMV7_COMMON bool "Tegra 32-bit common options" select CPU_V7 select SPL + select SPL_BOARD_INIT if SPL select SUPPORT_SPL select TEGRA_COMMON select TEGRA_GPIO @@ -126,4 +127,20 @@ source "arch/arm/mach-tegra/tegra124/Kconfig" source "arch/arm/mach-tegra/tegra210/Kconfig" source "arch/arm/mach-tegra/tegra186/Kconfig" +config CMD_ENTERRCM + bool "Enable 'enterrcm' command" + default y + help + Tegra's boot ROM supports a mode whereby code may be downloaded and + flash-programmed over a USB connection. On dev boards, this is + typically entered by holding down a "force recovery" button and + resetting the CPU. However, not all boards have such a button (one + example is the Compulab Trimslice), so a method to enter RCM from + software is useful. + + Even on boards other than Trimslice, controlling this over a UART + may be useful, e.g. to allow simple remote control without the need + for mechanical button actuators, or hooking up relays/... to the + button. + endif diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig index 4fcd01d..d72ff46 100644 --- a/arch/nds32/Kconfig +++ b/arch/nds32/Kconfig @@ -11,8 +11,12 @@ choice config TARGET_ADP_AG101P bool "Support adp-ag101p" +config TARGET_ADP_AE3XX + bool "Support adp-ae3xx" + endchoice source "board/AndesTech/adp-ag101p/Kconfig" +source "board/AndesTech/adp-ae3xx/Kconfig" endmenu diff --git a/arch/nds32/cpu/n1213/Makefile b/arch/nds32/cpu/n1213/Makefile index 7d5ae96..3a9ada1 100644 --- a/arch/nds32/cpu/n1213/Makefile +++ b/arch/nds32/cpu/n1213/Makefile @@ -12,3 +12,4 @@ extra-y = start.o obj-$(if $(filter ag101,$(SOC)),y) += ag101/ +obj-$(if $(filter ae3xx,$(SOC)),y) += ae3xx/ diff --git a/arch/nds32/cpu/n1213/ae3xx/Makefile b/arch/nds32/cpu/n1213/ae3xx/Makefile new file mode 100644 index 0000000..07fa942 --- /dev/null +++ b/arch/nds32/cpu/n1213/ae3xx/Makefile @@ -0,0 +1,18 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com> +# +# Copyright (C) 2011 Andes Technology Corporation +# Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> +# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := cpu.o timer.o +obj-y += lowlevel_init.o + +ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG +obj-y += watchdog.o +endif diff --git a/arch/nds32/cpu/n1213/ae3xx/cpu.c b/arch/nds32/cpu/n1213/ae3xx/cpu.c new file mode 100644 index 0000000..26f878f --- /dev/null +++ b/arch/nds32/cpu/n1213/ae3xx/cpu.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* CPU specific code */ +#include <common.h> +#include <command.h> +#include <watchdog.h> +#include <asm/cache.h> + +#include <faraday/ftwdt010_wdt.h> + +/* + * cleanup_before_linux() is called just before we call linux + * it prepares the processor for linux + * + * we disable interrupt and caches. + */ +int cleanup_before_linux(void) +{ + disable_interrupts(); + + /* turn off I/D-cache */ + cache_flush(); + icache_disable(); + dcache_disable(); + return 0; +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + disable_interrupts(); + panic("AE3XX wdt not support yet.\n"); +} diff --git a/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S b/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S new file mode 100644 index 0000000..d4bc2bc --- /dev/null +++ b/arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.pic + +.text + +#include <common.h> +#include <config.h> + +#include <asm/macro.h> +#include <generated/asm-offsets.h> + +/* + * parameters for the SDRAM controller + */ +#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1) +#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2) +#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1) +#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2) +#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR) +#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR) + +#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1 +#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2 +#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1 +#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2 + +#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR +#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR + + +/* + * for Orca and Emerald + */ +#define BOARD_ID_REG 0x104 +#define BOARD_ID_FAMILY_MASK 0xfff000 +#define BOARD_ID_FAMILY_V5 0x556000 +#define BOARD_ID_FAMILY_K7 0x74b000 + +/* + * parameters for the static memory controller + */ +#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR) +#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR) + +#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG +#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING + +/* + * for Orca and Emerald + */ +#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4) +#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 + +/* + * parameters for the pmu controoler + */ +#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0) + +/* + * numeric 7 segment display + */ +.macro led, num + write32 CONFIG_DEBUG_LED, \num +.endm + +/* + * Waiting for SDRAM to set up + */ +.macro wait_sdram + li $r0, CONFIG_FTSDMC021_BASE +1: + lwi $r1, [$r0+FTSDMC021_CR2] + bnez $r1, 1b +.endm + +.globl mem_init +mem_init: + move $r11, $lp + li $r0, SMC_BANK0_CR_A + lwi $r1, [$r0+#0x00] + ori $r1, $r1, 0x8f0 + xori $r1, $r1, 0x8f0 + /* 16-bit mode */ + ori $r1, $r1, 0x60 + li $r2, 0x00153153 + swi $r1, [$r0+#0x00] + swi $r2, [$r0+#0x04] + move $lp, $r11 + ret + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +.globl lowlevel_init +lowlevel_init: + move $r10, $lp + jal remap + +#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) + jal enable_fpu +#endif + ret $r10 + +remap: + move $r11, $lp +relo_base: + mfusr $r0, $pc + +#ifdef CONFIG_MEM_REMAP + li $r4, 0x00000000 + li $r5, 0x80000000 + la $r6, _end@GOTOFF +1: + lmw.bim $r12, [$r5], $r19 + smw.bim $r12, [$r4], $r19 + blt $r5, $r6, 1b +#endif /* #ifdef CONFIG_MEM_REMAP */ + move $lp, $r11 +2: + ret + + /* + * enable_fpu: + * Some of Andes CPU version support FPU coprocessor, if so, + * and toolchain support FPU instruction set, we should enable it. + */ +#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) +enable_fpu: + mfsr $r0, $CPU_VER /* enable FPU if it exists */ + srli $r0, $r0, 3 + andi $r0, $r0, 1 + beqz $r0, 1f /* skip if no COP */ + mfsr $r0, $FUCOP_EXIST + srli $r0, $r0, 31 + beqz $r0, 1f /* skip if no FPU */ + mfsr $r0, $FUCOP_CTL + ori $r0, $r0, 1 + mtsr $r0, $FUCOP_CTL +1: + ret +#endif + +#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/arch/nds32/cpu/n1213/ae3xx/timer.c b/arch/nds32/cpu/n1213/ae3xx/timer.c new file mode 100644 index 0000000..a284bf5 --- /dev/null +++ b/arch/nds32/cpu/n1213/ae3xx/timer.c @@ -0,0 +1,16 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert@faraday-tech.com> + * + * Copyright (C) 2011 Andes Technology Corporation + * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef CONFIG_TIMER +#include <common.h> +#include <asm/io.h> +#include <faraday/fttmr010.h> +#error "AE3XX timer only support DM flow" +#endif /* CONFIG_TIMER */ diff --git a/arch/nds32/cpu/n1213/ae3xx/watchdog.S b/arch/nds32/cpu/n1213/ae3xx/watchdog.S new file mode 100644 index 0000000..956c5f8 --- /dev/null +++ b/arch/nds32/cpu/n1213/ae3xx/watchdog.S @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch-ag101/ag101.h> +#include <linux/linkage.h> + +.text + +#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG +ENTRY(turnoff_watchdog) +#error "AE3XX not support wdt yet" +ENDPROC(turnoff_watchdog) +#endif diff --git a/arch/nds32/cpu/n1213/ag101/Makefile b/arch/nds32/cpu/n1213/ag101/Makefile index c21ce02..07fa942 100644 --- a/arch/nds32/cpu/n1213/ag101/Makefile +++ b/arch/nds32/cpu/n1213/ag101/Makefile @@ -11,10 +11,7 @@ # obj-y := cpu.o timer.o - -ifndef CONFIG_SKIP_LOWLEVEL_INIT obj-y += lowlevel_init.o -endif ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG obj-y += watchdog.o diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c index 31d7271..9da0b31 100644 --- a/arch/nds32/cpu/n1213/ag101/cpu.c +++ b/arch/nds32/cpu/n1213/ag101/cpu.c @@ -31,16 +31,10 @@ int cleanup_before_linux(void) { disable_interrupts(); -#ifdef CONFIG_MMU /* turn off I/D-cache */ + cache_flush(); icache_disable(); dcache_disable(); - - /* flush I/D-cache */ - invalidate_icac(); - invalidate_dcac(); -#endif - return 0; } diff --git a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S index abdd340..452d814 100644 --- a/arch/nds32/cpu/n1213/ag101/lowlevel_init.S +++ b/arch/nds32/cpu/n1213/ag101/lowlevel_init.S @@ -86,25 +86,7 @@ bnez $r1, 1b .endm -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -.globl lowlevel_init -lowlevel_init: - move $r10, $lp - - led 0x0 - jal mem_init - - led 0x10 - jal remap - -#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) - led 0x1f - jal enable_fpu -#endif - - led 0x20 - ret $r10 - +.globl mem_init mem_init: move $r11, $lp @@ -124,9 +106,7 @@ mem_init: lwi $r1, [$r0+#0x00] ori $r1, $r1, 0x8f0 xori $r1, $r1, 0x8f0 - /* - * check board - */ + /* check board */ li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG lwi $r3, [$r3] li $r4, BOARD_ID_FAMILY_MASK @@ -134,29 +114,21 @@ mem_init: li $r4, BOARD_ID_FAMILY_K7 xor $r4, $r3, $r4 beqz $r4, use_flash_16bit_boot - /* - * 32-bit mode - */ + /* 32-bit mode */ use_flash_32bit_boot: ori $r1, $r1, 0x50 li $r2, 0x00151151 j sdram_b0_cr - /* - * 16-bit mode - */ + /* 16-bit mode */ use_flash_16bit_boot: ori $r1, $r1, 0x60 li $r2, 0x00153153 - /* - * SRAM bank0 config - */ + /* SRAM bank0 config */ sdram_b0_cr: swi $r1, [$r0+#0x00] swi $r2, [$r0+#0x04] - /* - * config AHB Controller - */ + /* config AHB Controller */ led 0x02 /* @@ -192,6 +164,21 @@ sdram_b0_cr: move $lp, $r11 ret + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + +.globl lowlevel_init +lowlevel_init: + move $r10, $lp + led 0x10 + jal remap +#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP)) + led 0x1f + jal enable_fpu +#endif + led 0x20 + ret $r10 + remap: move $r11, $lp #ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */ @@ -203,9 +190,7 @@ relo_base: mfusr $r0, $pc #endif /* __NDS32_N1213_43U1H__ */ - /* - * Remapping - */ + /* Remapping */ led 0x1a write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001800 write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001880 diff --git a/arch/nds32/cpu/n1213/ag101/timer.c b/arch/nds32/cpu/n1213/ag101/timer.c index 758b354..0c03a10 100644 --- a/arch/nds32/cpu/n1213/ag101/timer.c +++ b/arch/nds32/cpu/n1213/ag101/timer.c @@ -8,7 +8,7 @@ * * SPDX-License-Identifier: GPL-2.0+ */ - +#ifndef CONFIG_TIMER #include <common.h> #include <asm/io.h> #include <faraday/fttmr010.h> @@ -189,3 +189,4 @@ ulong get_tbclk(void) return CONFIG_SYS_CLK_FREQ; #endif } +#endif /* CONFIG_TIMER */ diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S index 99971fd..f9f9999 100644 --- a/arch/nds32/cpu/n1213/start.S +++ b/arch/nds32/cpu/n1213/start.S @@ -114,11 +114,39 @@ reset_gp: set_ivb: li $r0, 0x0 - /* turn on BTB */ mtsr $r0, $misc_ctl /* set IVIC, vector size: 4 bytes, base: 0x0 */ mtsr $r0, $ivb +/* + * MMU_CTL NTC0 Cacheable/Write-Back + */ + li $r0, ~0x3 + mfsr $r1, $mr8 + and $r1, $r1, $r0 + mtsr $r1, $mr8 +#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)) + li $r0, 0x4 + mfsr $r1, $mr0 + or $r1, $r1, $r0 + mtsr $r1, $mr0 +#endif + +#if !defined(CONFIG_SYS_ICACHE_OFF) + li $r0, 0x1 + mfsr $r1, $mr8 + or $r1, $r1, $r0 + mtsr $r1, $mr8 +#endif + +#if !defined(CONFIG_SYS_DCACHE_OFF) + li $r0, 0x2 + mfsr $r1, $mr8 + or $r1, $r1, $r0 + mtsr $r1, $mr8 +#endif + + jal mem_init #ifndef CONFIG_SKIP_LOWLEVEL_INIT jal lowlevel_init @@ -133,7 +161,6 @@ update_gp: ori $gp, $gp, lo12(_GLOBAL_OFFSET_TABLE_-4) add5.pc $gp #endif - /* * do critical initializations first (shall be in short time) * do self_relocation ASAP. @@ -161,11 +188,14 @@ update_gp: */ call_board_init_f: li $sp, CONFIG_SYS_INIT_SP_ADDR - li $r10, GD_SIZE /* get GD size */ - sub $sp, $sp, $r10 /* GD start addr */ - move $r10, $sp + move $r0, $sp + bal board_init_f_alloc_reserve + move $sp, $r0 + bal board_init_f_init_reserve +#ifdef CONFIG_DEBUG_UART + bal debug_uart_init +#endif li $r0, 0x00000000 - #ifdef __PIC__ #ifdef __NDS32_N1213_43U1H__ /* __NDS32_N1213_43U1H__ implies NDS32 V0 ISA */ @@ -201,12 +231,10 @@ stack_setup: la $r1, _end@GOTOFF move $r2, $r6 /* r2 <- scratch for copy_loop */ - copy_loop: - lwi.p $r7, [$r0], #4 - swi.p $r7, [$r2], #4 + lmw.bim $r11, [$r0], $r18 + smw.bim $r11, [$r2], $r18 blt $r0, $r1, copy_loop - /* * fix relocations related issues */ @@ -246,6 +274,8 @@ clbss_l: * initialization, now running from RAM. */ call_board_init_r: + bal invalidate_icache_all + bal flush_dcache_all la $r0, board_init_r@GOTOFF move $lp, $r0 /* offset of board_init_r() */ add $lp, $lp, $r9 /* real address of board_init_r() */ diff --git a/arch/nds32/dts/Makefile b/arch/nds32/dts/Makefile new file mode 100644 index 0000000..1d6b195 --- /dev/null +++ b/arch/nds32/dts/Makefile @@ -0,0 +1,15 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +dtb-$(CONFIG_TARGET_ADP_AG101P) += ag101p.dtb +dtb-$(CONFIG_TARGET_ADP_AE3XX) += ae3xx.dtb +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/nds32/dts/ae3xx.dts b/arch/nds32/dts/ae3xx.dts new file mode 100644 index 0000000..9062760 --- /dev/null +++ b/arch/nds32/dts/ae3xx.dts @@ -0,0 +1,65 @@ +/dts-v1/; +/ { + compatible = "nds32 ae3xx"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + aliases { + uart0 = &serial0; + } ; + + chosen { + /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug memblock=debug loglevel=7"; */ + bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; + stdout-path = "uart0:38400n8"; + tick-timer = &timer0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "andestech,n13"; + reg = <0>; + /* FIXME: to fill correct frqeuency */ + clock-frequency = <60000000>; + }; + }; + + intc: interrupt-controller { + compatible = "andestech,atnointc010"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@f0300000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0xf0300000 0x1000>; + interrupts = <7 4>; + clock-frequency = <14745600>; + reg-shift = <2>; + reg-offset = <32>; + no-loopback-test = <1>; + }; + + timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + interrupts = <2 4>; + clock-frequency = <30000000>; + }; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0x88000000 0x1000>; + bank-width = <2>; + device-width = <1>; + }; + +}; diff --git a/arch/nds32/dts/ag101p.dts b/arch/nds32/dts/ag101p.dts new file mode 100644 index 0000000..91314b5 --- /dev/null +++ b/arch/nds32/dts/ag101p.dts @@ -0,0 +1,57 @@ +/dts-v1/; +/ { + compatible = "nds32 ag101p"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + + aliases { + uart0 = &serial0; + } ; + + chosen { + /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug bootmem_debug memblock=debug loglevel=7"; */ + bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug loglevel=7"; + stdout-path = "uart0:38400n8"; + tick-timer = &timer0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x40000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "andestech,n13"; + reg = <0>; + /* FIXME: to fill correct frqeuency */ + clock-frequency = <60000000>; + }; + }; + + intc: interrupt-controller { + compatible = "andestech,atnointc010"; + #interrupt-cells = <1>; + interrupt-controller; + }; + + serial0: serial@99600000 { + compatible = "andestech,uart16550", "ns16550a"; + reg = <0x99600000 0x1000>; + interrupts = <7 4>; + clock-frequency = <14745600>; + reg-shift = <2>; + no-loopback-test = <1>; + }; + + timer0: timer@98400000 { + compatible = "andestech,attmr010"; + reg = <0x98400000 0x1000>; + interrupts = <19 4>; + clock-frequency = <15000000>; + }; + +}; diff --git a/arch/nds32/include/asm/arch-ae3xx/ae3xx.h b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h new file mode 100644 index 0000000..b074e84 --- /dev/null +++ b/arch/nds32/include/asm/arch-ae3xx/ae3xx.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2016 Andes Technology Corporation + * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com> + * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AE3XX_H +#define __AE3XX_H + +/* Hardware register bases */ + +/* Static Memory Controller (SRAM) */ +#define CONFIG_FTSMC020_BASE 0xe0400000 +/* DMA Controller */ +#define CONFIG_FTDMAC020_BASE 0xf0c00000 +/* AHB-to-APB Bridge */ +#define CONFIG_FTAPBBRG020S_01_BASE 0xf0000000 +/* Reserved */ +#define CONFIG_RESERVED_01_BASE 0xe0500000 +/* Reserved */ +#define CONFIG_RESERVED_02_BASE 0xf0800000 +/* Reserved */ +#define CONFIG_RESERVED_03_BASE 0xf0900000 +/* Ethernet */ +#define CONFIG_FTMAC100_BASE 0xe0100000 +/* Reserved */ +#define CONFIG_RESERVED_04_BASE 0xf1000000 + +/* APB Device definitions */ + +/* UART1 */ +#define CONFIG_FTUART010_01_BASE 0xf0200000 +/* UART2 */ +#define CONFIG_FTUART010_02_BASE 0xf0300000 +/* Counter/Timers */ +#define CONFIG_FTTMR010_BASE 0xf0400000 +/* Watchdog Timer */ +#define CONFIG_FTWDT010_BASE 0xf0500000 +/* Real Time Clock */ +#define CONFIG_FTRTC010_BASE 0xf0600000 +/* GPIO */ +#define CONFIG_FTGPIO010_BASE 0xf0700000 +/* I2C */ +#define CONFIG_FTIIC010_BASE 0xf0a00000 +/* SD Controller */ +#define CONFIG_FTSDC010_BASE 0xf0e00000 + +/* The following address was not defined in Linux */ + +/* Synchronous Serial Port Controller (SSP) 01 */ +#define CONFIG_FTSSP010_01_BASE 0xf0d00000 +#endif /* __AE3XX_H */ diff --git a/arch/nds32/include/asm/bootm.h b/arch/nds32/include/asm/bootm.h new file mode 100644 index 0000000..6b10c07 --- /dev/null +++ b/arch/nds32/include/asm/bootm.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2013, Google Inc. + * + * Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef NDS32_BOOTM_H +#define NDS32_BOOTM_H + +extern void udc_disconnect(void); + +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) +# define BOOTM_ENABLE_TAGS 1 +#else +# define BOOTM_ENABLE_TAGS 0 +#endif + +#ifdef CONFIG_SETUP_MEMORY_TAGS +# define BOOTM_ENABLE_MEMORY_TAGS 1 +#else +# define BOOTM_ENABLE_MEMORY_TAGS 0 +#endif + +#ifdef CONFIG_CMDLINE_TAG + #define BOOTM_ENABLE_CMDLINE_TAG 1 +#else + #define BOOTM_ENABLE_CMDLINE_TAG 0 +#endif + +#ifdef CONFIG_INITRD_TAG + #define BOOTM_ENABLE_INITRD_TAG 1 +#else + #define BOOTM_ENABLE_INITRD_TAG 0 +#endif + +#ifdef CONFIG_SERIAL_TAG + #define BOOTM_ENABLE_SERIAL_TAG 1 +void get_board_serial(struct tag_serialnr *serialnr); +#else + #define BOOTM_ENABLE_SERIAL_TAG 0 +static inline void get_board_serial(struct tag_serialnr *serialnr) +{ +} +#endif + +#ifdef CONFIG_REVISION_TAG + #define BOOTM_ENABLE_REVISION_TAG 1 +u32 get_board_rev(void); +#else + #define BOOTM_ENABLE_REVISION_TAG 0 +static inline u32 get_board_rev(void) +{ + return 0; +} +#endif + +#endif diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h index 9038821..7e9aac8 100644 --- a/arch/nds32/include/asm/cache.h +++ b/arch/nds32/include/asm/cache.h @@ -16,6 +16,7 @@ void icache_disable(void); int dcache_status(void); void dcache_enable(void); void dcache_disable(void); +void cache_flush(void); #define DEFINE_GET_SYS_REG(reg) \ static inline unsigned long GET_##reg(void) \ @@ -30,10 +31,24 @@ void dcache_disable(void); enum cache_t {ICACHE, DCACHE}; DEFINE_GET_SYS_REG(ICM_CFG); DEFINE_GET_SYS_REG(DCM_CFG); -#define ICM_CFG_OFF_ISZ 6 /* I-cache line size */ -#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) -#define DCM_CFG_OFF_DSZ 6 /* D-cache line size */ -#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) +/* I-cache sets (# of cache lines) per way */ +#define ICM_CFG_OFF_ISET 0 +/* I-cache ways */ +#define ICM_CFG_OFF_IWAY 3 +#define ICM_CFG_MSK_ISET (0x7 << ICM_CFG_OFF_ISET) +#define ICM_CFG_MSK_IWAY (0x7 << ICM_CFG_OFF_IWAY) +/* D-cache sets (# of cache lines) per way */ +#define DCM_CFG_OFF_DSET 0 +/* D-cache ways */ +#define DCM_CFG_OFF_DWAY 3 +#define DCM_CFG_MSK_DSET (0x7 << DCM_CFG_OFF_DSET) +#define DCM_CFG_MSK_DWAY (0x7 << DCM_CFG_OFF_DWAY) +/* I-cache line size */ +#define ICM_CFG_OFF_ISZ 6 +#define ICM_CFG_MSK_ISZ (0x7UL << ICM_CFG_OFF_ISZ) +/* D-cache line size */ +#define DCM_CFG_OFF_DSZ 6 +#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ) /* * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes. diff --git a/arch/nds32/include/asm/config.h b/arch/nds32/include/asm/config.h index 054cc48..7289217 100644 --- a/arch/nds32/include/asm/config.h +++ b/arch/nds32/include/asm/config.h @@ -8,5 +8,6 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#define CONFIG_LMB #endif diff --git a/arch/nds32/include/asm/mach-types.h b/arch/nds32/include/asm/mach-types.h index 1959d7e..99904f9 100644 --- a/arch/nds32/include/asm/mach-types.h +++ b/arch/nds32/include/asm/mach-types.h @@ -13,6 +13,7 @@ extern unsigned int __machine_arch_type; /* see arch/arm/kernel/arch.c for a description of these */ #define MACH_TYPE_ADPAG101P 1 +#define MACH_TYPE_ADPAE3XX 2 #ifdef CONFIG_ARCH_ADPAG101P # ifdef machine_arch_type diff --git a/arch/nds32/lib/Makefile b/arch/nds32/lib/Makefile index 1a0d26f..c88ad72 100644 --- a/arch/nds32/lib/Makefile +++ b/arch/nds32/lib/Makefile @@ -11,4 +11,5 @@ obj-y += cache.o obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_CMD_GO) += boot.o obj-y += interrupts.o diff --git a/arch/nds32/lib/boot.c b/arch/nds32/lib/boot.c new file mode 100644 index 0000000..f9c1c6b --- /dev/null +++ b/arch/nds32/lib/boot.c @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <rick@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <common.h> +#include <command.h> + +DECLARE_GLOBAL_DATA_PTR; + +unsigned long do_go_exec(ulong (*entry)(int, char * const []), + int argc, char * const argv[]) +{ + cleanup_before_linux(); + + return entry(argc, argv); +} diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c index 8b0b28f..4c95a41 100644 --- a/arch/nds32/lib/bootm.c +++ b/arch/nds32/lib/bootm.c @@ -11,9 +11,16 @@ #include <image.h> #include <u-boot/zlib.h> #include <asm/byteorder.h> +#include <asm/bootm.h> DECLARE_GLOBAL_DATA_PTR; +int arch_fixup_fdt(void *blob) +{ + return 0; +} + + #if defined(CONFIG_SETUP_MEMORY_TAGS) || \ defined(CONFIG_CMDLINE_TAG) || \ defined(CONFIG_INITRD_TAG) || \ @@ -67,6 +74,15 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) debug("## Transferring control to Linux (at address %08lx) ...\n", (ulong)theKernel); + if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { +#ifdef CONFIG_OF_LIBFDT + debug("using: FDT\n"); + if (image_setup_linux(images)) { + printf("FDT creation failed! hanging..."); + hang(); + } +#endif + } else if (BOOTM_ENABLE_TAGS) { #if defined(CONFIG_SETUP_MEMORY_TAGS) || \ defined(CONFIG_CMDLINE_TAG) || \ defined(CONFIG_INITRD_TAG) || \ @@ -101,16 +117,17 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) udc_disconnect(); } #endif - + } cleanup_before_linux(); - - theKernel(0, machid, bd->bi_boot_params); + if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) + theKernel(0, machid, (unsigned long)images->ft_addr); + else + theKernel(0, machid, bd->bi_boot_params); /* does not return */ return 1; } - #if defined(CONFIG_SETUP_MEMORY_TAGS) || \ defined(CONFIG_CMDLINE_TAG) || \ defined(CONFIG_INITRD_TAG) || \ @@ -130,7 +147,6 @@ static void setup_start_tag(bd_t *bd) params = tag_next(params); } - #ifdef CONFIG_SETUP_MEMORY_TAGS static void setup_memory_tags(bd_t *bd) { @@ -148,7 +164,6 @@ static void setup_memory_tags(bd_t *bd) } #endif /* CONFIG_SETUP_MEMORY_TAGS */ - static void setup_commandline_tag(bd_t *bd, char *commandline) { char *p; @@ -176,7 +191,6 @@ static void setup_commandline_tag(bd_t *bd, char *commandline) params = tag_next(params); } - #ifdef CONFIG_INITRD_TAG static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end) { @@ -224,7 +238,6 @@ void setup_revision_tag(struct tag **in_params) } #endif /* CONFIG_REVISION_TAG */ - static void setup_end_tag(bd_t *bd) { params->hdr.tag = ATAG_NONE; diff --git a/arch/nds32/lib/cache.c b/arch/nds32/lib/cache.c index 866dc1a..8469481 100644 --- a/arch/nds32/lib/cache.c +++ b/arch/nds32/lib/cache.c @@ -7,32 +7,56 @@ */ #include <common.h> +#if (!defined(CONFIG_SYS_ICACHE_OFF) || !defined(CONFIG_SYS_DCACHE_OFF)) +static inline unsigned long CACHE_SET(unsigned char cache) +{ + if (cache == ICACHE) + return 64 << ((GET_ICM_CFG() & ICM_CFG_MSK_ISET) \ + >> ICM_CFG_OFF_ISET); + else + return 64 << ((GET_DCM_CFG() & DCM_CFG_MSK_DSET) \ + >> DCM_CFG_OFF_DSET); +} + +static inline unsigned long CACHE_WAY(unsigned char cache) +{ + if (cache == ICACHE) + return 1 + ((GET_ICM_CFG() & ICM_CFG_MSK_IWAY) \ + >> ICM_CFG_OFF_IWAY); + else + return 1 + ((GET_DCM_CFG() & DCM_CFG_MSK_DWAY) \ + >> DCM_CFG_OFF_DWAY); +} static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache) { if (cache == ICACHE) return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \ - >> ICM_CFG_OFF_ISZ) - 1); + >> ICM_CFG_OFF_ISZ) - 1); else return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \ - >> DCM_CFG_OFF_DSZ) - 1); + >> DCM_CFG_OFF_DSZ) - 1); } +#endif -void flush_dcache_range(unsigned long start, unsigned long end) +#ifndef CONFIG_SYS_ICACHE_OFF +void invalidate_icache_all(void) { - unsigned long line_size; + unsigned long end, line_size; + line_size = CACHE_LINE_SIZE(ICACHE); + end = line_size * CACHE_WAY(ICACHE) * CACHE_SET(ICACHE); + do { + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end)); - line_size = CACHE_LINE_SIZE(DCACHE); + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end)); - while (end > start) { - asm volatile ( - "\n\tcctl %0, L1D_VA_WB" - "\n\tcctl %0, L1D_VA_INVAL" - : - : "r" (start) - ); - start += line_size; - } + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end)); + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL" : : "r" (end)); + } while (end > 0); } void invalidate_icache_range(unsigned long start, unsigned long end) @@ -50,27 +74,6 @@ void invalidate_icache_range(unsigned long start, unsigned long end) } } -void invalidate_dcache_range(unsigned long start, unsigned long end) -{ - unsigned long line_size; - - line_size = CACHE_LINE_SIZE(DCACHE); - while (end > start) { - asm volatile ( - "\n\tcctl %0, L1D_VA_INVAL" - : - : "r"(start) - ); - start += line_size; - } -} - -void flush_cache(unsigned long addr, unsigned long size) -{ - flush_dcache_range(addr, addr + size); - invalidate_icache_range(addr, addr + size); -} - void icache_enable(void) { asm volatile ( @@ -107,6 +110,81 @@ int icache_status(void) return ret; } +#else +void invalidate_icache_all(void) +{ +} + +void invalidate_icache_range(unsigned long start, unsigned long end) +{ +} + +void icache_enable(void) +{ +} + +void icache_disable(void) +{ +} + +int icache_status(void) +{ + return 0; +} + +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void dcache_wbinval_all(void) +{ + unsigned long end, line_size; + line_size = CACHE_LINE_SIZE(DCACHE); + end = line_size * CACHE_WAY(DCACHE) * CACHE_SET(DCACHE); + do { + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end)); + __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end)); + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end)); + __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end)); + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end)); + __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end)); + end -= line_size; + __asm__ volatile ("\n\tcctl %0, L1D_IX_WB" : : "r" (end)); + __asm__ volatile ("\n\tcctl %0, L1D_IX_INVAL" : : "r" (end)); + + } while (end > 0); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(DCACHE); + + while (end > start) { + asm volatile ( + "\n\tcctl %0, L1D_VA_WB" + "\n\tcctl %0, L1D_VA_INVAL" : : "r" (start) + ); + start += line_size; + } +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + unsigned long line_size; + + line_size = CACHE_LINE_SIZE(DCACHE); + while (end > start) { + asm volatile ( + "\n\tcctl %0, L1D_VA_INVAL" : : "r"(start) + ); + start += line_size; + } +} + void dcache_enable(void) { asm volatile ( @@ -131,7 +209,6 @@ void dcache_disable(void) int dcache_status(void) { int ret; - asm volatile ( "mfsr $p0, $mr8\n\t" "andi %0, $p0, 0x02\n\t" @@ -139,6 +216,52 @@ int dcache_status(void) : : "memory" ); - return ret; } + +#else +void dcache_wbinval_all(void) +{ +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ +} + +void dcache_enable(void) +{ +} + +void dcache_disable(void) +{ +} + +int dcache_status(void) +{ + return 0; +} + +#endif + + +void flush_dcache_all(void) +{ + dcache_wbinval_all(); +} + +void cache_flush(void) +{ + flush_dcache_all(); + invalidate_icache_all(); +} + + +void flush_cache(unsigned long addr, unsigned long size) +{ + flush_dcache_range(addr, addr + size); + invalidate_icache_range(addr, addr + size); +} diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 01e9008..f37a9cb 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -33,6 +33,8 @@ config MPC85xx select SYS_FSL_DDR select SYS_FSL_DDR_BE imply USB_EHCI_HCD if USB + imply CMD_HASH + imply CMD_IRQ config MPC86xx bool "MPC86xx" @@ -45,9 +47,12 @@ config 8xx config 4xx bool "PPC4xx" select CREATE_ARCH_SYMLINK + imply CMD_IRQ endchoice +source "arch/powerpc/lib/Kconfig" + source "arch/powerpc/cpu/mpc512x/Kconfig" source "arch/powerpc/cpu/mpc5xx/Kconfig" source "arch/powerpc/cpu/mpc5xxx/Kconfig" diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig index 5d49228..6ba0dd4 100644 --- a/arch/powerpc/cpu/mpc5xxx/Kconfig +++ b/arch/powerpc/cpu/mpc5xxx/Kconfig @@ -59,6 +59,7 @@ config TARGET_O3DNT config TARGET_DIGSY_MTC bool "Support digsy_mtc" + imply CMD_IRQ config TARGET_PCM030 bool "Support pcm030" diff --git a/arch/powerpc/cpu/mpc5xxx/ide.c b/arch/powerpc/cpu/mpc5xxx/ide.c index 9003b77..d1f4349 100644 --- a/arch/powerpc/cpu/mpc5xxx/ide.c +++ b/arch/powerpc/cpu/mpc5xxx/ide.c @@ -8,7 +8,7 @@ */ #include <common.h> -#if defined(CONFIG_CMD_IDE) +#if defined(CONFIG_IDE) #include <mpc5xxx.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 02e43bc..0772b7c 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -49,6 +49,7 @@ config TARGET_MPC8349EMDS config TARGET_MPC8349ITX bool "Support MPC8349ITX" + imply CMD_IRQ config TARGET_MPC837XEMDS bool "Support MPC837XEMDS" diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 31c0964..88d56a9 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -4,6 +4,14 @@ menu "mpc85xx CPU" config SYS_CPU default "mpc85xx" +config CMD_ERRATA + bool "Enable the 'errata' command" + depends on MPC85xx + default y + help + This enables the 'errata' command which displays a list of errata + work-arounds which are enabled for the current board. + choice prompt "Target select" optional @@ -124,6 +132,7 @@ config TARGET_P1010RDB_PA select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select SUPPORT_TPL + imply CMD_EEPROM config TARGET_P1010RDB_PB bool "Support P1010RDB_PB" @@ -131,6 +140,7 @@ config TARGET_P1010RDB_PB select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select SUPPORT_TPL + imply CMD_EEPROM config TARGET_P1022DS bool "Support P1022DS" @@ -141,54 +151,63 @@ config TARGET_P1022DS config TARGET_P1023RDB bool "Support P1023RDB" select ARCH_P1023 + imply CMD_EEPROM config TARGET_P1020MBG bool "Support P1020MBG-PC" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1020 + imply CMD_EEPROM config TARGET_P1020RDB_PC bool "Support P1020RDB-PC" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1020 + imply CMD_EEPROM config TARGET_P1020RDB_PD bool "Support P1020RDB-PD" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1020 + imply CMD_EEPROM config TARGET_P1020UTM bool "Support P1020UTM" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1020 + imply CMD_EEPROM config TARGET_P1021RDB bool "Support P1021RDB" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1021 + imply CMD_EEPROM config TARGET_P1024RDB bool "Support P1024RDB" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1024 + imply CMD_EEPROM config TARGET_P1025RDB bool "Support P1025RDB" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1025 + imply CMD_EEPROM config TARGET_P2020RDB bool "Support P2020RDB-PC" select SUPPORT_SPL select SUPPORT_TPL select ARCH_P2020 + imply CMD_EEPROM config TARGET_P1_TWR bool "Support p1_twr" @@ -211,6 +230,7 @@ config TARGET_T1024QDS select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select PHYS_64BIT + imply CMD_EEPROM config TARGET_T1023RDB bool "Support T1023RDB" @@ -218,6 +238,7 @@ config TARGET_T1023RDB select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select PHYS_64BIT + imply CMD_EEPROM config TARGET_T1024RDB bool "Support T1024RDB" @@ -225,12 +246,14 @@ config TARGET_T1024RDB select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select PHYS_64BIT + imply CMD_EEPROM config TARGET_T1040QDS bool "Support T1040QDS" select ARCH_T1040 select BOARD_LATE_INIT if CHAIN_OF_TRUST select PHYS_64BIT + imply CMD_EEPROM config TARGET_T1040RDB bool "Support T1040RDB" @@ -377,6 +400,7 @@ config ARCH_B4420 select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 select FSL_IFC + imply CMD_EEPROM config ARCH_B4860 bool @@ -402,6 +426,7 @@ config ARCH_B4860 select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 select FSL_IFC + imply CMD_EEPROM config ARCH_BSC9131 bool @@ -415,6 +440,7 @@ config ARCH_BSC9131 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_IFC + imply CMD_EEPROM config ARCH_BSC9132 bool @@ -432,6 +458,7 @@ config ARCH_BSC9132 select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_IFC + imply CMD_EEPROM config ARCH_C29X bool @@ -565,6 +592,7 @@ config ARCH_P1010 select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_IFC + imply CMD_EEPROM config ARCH_P1011 bool @@ -649,6 +677,7 @@ config ARCH_P1024 select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC + imply CMD_EEPROM config ARCH_P1025 bool @@ -678,6 +707,7 @@ config ARCH_P2020 select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC + imply CMD_EEPROM config ARCH_P2041 bool @@ -821,6 +851,7 @@ config ARCH_T1023 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 select FSL_IFC + imply CMD_EEPROM config ARCH_T1024 bool @@ -838,6 +869,7 @@ config ARCH_T1024 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 select FSL_IFC + imply CMD_EEPROM config ARCH_T1040 bool diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 38121c1..77e8fd4 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -137,6 +137,12 @@ config CMD_CHIP_CONFIG and control the CPU and peripehrals clocks. The programmed configuration is then used when the board boots. +config CMD_ECCTEST + bool "Enable the 'ecctest' command" + help + This command tests memory ECC by single and double error bit + injection. + source "board/amcc/acadia/Kconfig" source "board/amcc/bamboo/Kconfig" source "board/amcc/bubinga/Kconfig" diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 62ce816..76921ee 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -99,9 +99,7 @@ #define CONFIG_SPL_UBOOT_KEY_HASH NULL #endif /* ifdef CONFIG_SPL_BUILD */ -#define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_FSL_SEC_MON -#define CONFIG_SHA_PROG_HW_ACCEL #ifndef CONFIG_SPL_BUILD /* diff --git a/arch/powerpc/lib/Kconfig b/arch/powerpc/lib/Kconfig new file mode 100644 index 0000000..987cec9 --- /dev/null +++ b/arch/powerpc/lib/Kconfig @@ -0,0 +1,8 @@ +config CMD_IMMAP + bool "Enable various commands to dump IMMR information" + help + This enables various commands such as: + + siuinfo - print System Interface Unit (SIU) registers + memcinfo - print Memory Controller registers + sitinfo - print System Integration Timers (SIT) registers diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 4f68613..e09bd9a 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -33,9 +33,10 @@ obj-$(CONFIG_BAT_RW) += bat_rw.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cache.o obj-y += extable.o +obj-$(CONFIG_CMD_IMMAP) += immap.o obj-y += interrupts.o obj-$(CONFIG_CMD_KGDB) += kgdb.o -obj-$(CONFIG_CMD_IDE) += ide.o +obj-$(CONFIG_IDE) += ide.o obj-y += stack.o obj-y += time.o diff --git a/arch/powerpc/lib/immap.c b/arch/powerpc/lib/immap.c new file mode 100644 index 0000000..1414f9a --- /dev/null +++ b/arch/powerpc/lib/immap.c @@ -0,0 +1,703 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * MPC8xx/MPC8260 Internal Memory Map Functions + */ + +#include <common.h> +#include <command.h> + +#if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) + +#if defined(CONFIG_8xx) +#include <asm/8xx_immap.h> +#include <commproc.h> +#include <asm/iopin_8xx.h> +#elif defined(CONFIG_MPC8260) +#include <asm/immap_8260.h> +#include <asm/cpm_8260.h> +#include <asm/iopin_8260.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static void +unimplemented ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + printf ("Sorry, but the '%s' command has not been implemented\n", + cmdtp->name); +} + +int +do_siuinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + +#if defined(CONFIG_8xx) + volatile sysconf8xx_t *sc = &immap->im_siu_conf; +#elif defined(CONFIG_MPC8260) + volatile sysconf8260_t *sc = &immap->im_siu_conf; +#endif + + printf ("SIUMCR= %08x SYPCR = %08x\n", sc->sc_siumcr, sc->sc_sypcr); +#if defined(CONFIG_8xx) + printf ("SWT = %08x\n", sc->sc_swt); + printf ("SIPEND= %08x SIMASK= %08x\n", sc->sc_sipend, sc->sc_simask); + printf ("SIEL = %08x SIVEC = %08x\n", sc->sc_siel, sc->sc_sivec); + printf ("TESR = %08x SDCR = %08x\n", sc->sc_tesr, sc->sc_sdcr); +#elif defined(CONFIG_MPC8260) + printf ("BCR = %08x\n", sc->sc_bcr); + printf ("P_ACR = %02x P_ALRH= %08x P_ALRL= %08x\n", + sc->sc_ppc_acr, sc->sc_ppc_alrh, sc->sc_ppc_alrl); + printf ("L_ACR = %02x L_ALRH= %08x L_ALRL= %08x\n", + sc->sc_lcl_acr, sc->sc_lcl_alrh, sc->sc_lcl_alrl); + printf ("PTESR1= %08x PTESR2= %08x\n", sc->sc_tescr1, sc->sc_tescr2); + printf ("LTESR1= %08x LTESR2= %08x\n", sc->sc_ltescr1, sc->sc_ltescr2); + printf ("PDTEA = %08x PDTEM = %02x\n", sc->sc_pdtea, sc->sc_pdtem); + printf ("LDTEA = %08x LDTEM = %02x\n", sc->sc_ldtea, sc->sc_ldtem); +#endif + return 0; +} + +int +do_memcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + +#if defined(CONFIG_8xx) + volatile memctl8xx_t *memctl = &immap->im_memctl; + int nbanks = 8; +#elif defined(CONFIG_MPC8260) + volatile memctl8260_t *memctl = &immap->im_memctl; + int nbanks = 12; +#endif + volatile uint *p = &memctl->memc_br0; + int i; + + for (i = 0; i < nbanks; i++, p += 2) { + if (i < 10) { + printf ("BR%d = %08x OR%d = %08x\n", + i, p[0], i, p[1]); + } else { + printf ("BR%d = %08x OR%d = %08x\n", + i, p[0], i, p[1]); + } + } + + printf ("MAR = %08x", memctl->memc_mar); +#if defined(CONFIG_8xx) + printf (" MCR = %08x\n", memctl->memc_mcr); +#elif defined(CONFIG_MPC8260) + putc ('\n'); +#endif + printf ("MAMR = %08x MBMR = %08x", + memctl->memc_mamr, memctl->memc_mbmr); +#if defined(CONFIG_8xx) + printf ("\nMSTAT = %04x\n", memctl->memc_mstat); +#elif defined(CONFIG_MPC8260) + printf (" MCMR = %08x\n", memctl->memc_mcmr); +#endif + printf ("MPTPR = %04x MDR = %08x\n", + memctl->memc_mptpr, memctl->memc_mdr); +#if defined(CONFIG_MPC8260) + printf ("PSDMR = %08x LSDMR = %08x\n", + memctl->memc_psdmr, memctl->memc_lsdmr); + printf ("PURT = %02x PSRT = %02x\n", + memctl->memc_purt, memctl->memc_psrt); + printf ("LURT = %02x LSRT = %02x\n", + memctl->memc_lurt, memctl->memc_lsrt); + printf ("IMMR = %08x\n", memctl->memc_immr); +#endif + return 0; +} + +int +do_sitinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +#ifdef CONFIG_MPC8260 +int +do_icinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} +#endif + +int +do_carinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + +#if defined(CONFIG_8xx) + volatile car8xx_t *car = &immap->im_clkrst; +#elif defined(CONFIG_MPC8260) + volatile car8260_t *car = &immap->im_clkrst; +#endif + +#if defined(CONFIG_8xx) + printf ("SCCR = %08x\n", car->car_sccr); + printf ("PLPRCR= %08x\n", car->car_plprcr); + printf ("RSR = %08x\n", car->car_rsr); +#elif defined(CONFIG_MPC8260) + printf ("SCCR = %08x\n", car->car_sccr); + printf ("SCMR = %08x\n", car->car_scmr); + printf ("RSR = %08x\n", car->car_rsr); + printf ("RMR = %08x\n", car->car_rmr); +#endif + return 0; +} + +static int counter; + +static void +header(void) +{ + char *data = "\ + -------------------------------- --------------------------------\ + 00000000001111111111222222222233 00000000001111111111222222222233\ + 01234567890123456789012345678901 01234567890123456789012345678901\ + -------------------------------- --------------------------------\ + "; + int i; + + if (counter % 2) + putc('\n'); + counter = 0; + + for (i = 0; i < 4; i++, data += 79) + printf("%.79s\n", data); +} + +static void binary (char *label, uint value, int nbits) +{ + uint mask = 1 << (nbits - 1); + int i, second = (counter++ % 2); + + if (second) + putc (' '); + puts (label); + for (i = 32 + 1; i != nbits; i--) + putc (' '); + + while (mask != 0) { + if (value & mask) + putc ('1'); + else + putc ('0'); + mask >>= 1; + } + + if (second) + putc ('\n'); +} + +#if defined(CONFIG_8xx) +#define PA_NBITS 16 +#define PA_NB_ODR 8 +#define PB_NBITS 18 +#define PB_NB_ODR 16 +#define PC_NBITS 12 +#define PD_NBITS 13 +#elif defined(CONFIG_MPC8260) +#define PA_NBITS 32 +#define PA_NB_ODR 32 +#define PB_NBITS 28 +#define PB_NB_ODR 28 +#define PC_NBITS 32 +#define PD_NBITS 28 +#endif + +int +do_iopinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + +#if defined(CONFIG_8xx) + volatile iop8xx_t *iop = &immap->im_ioport; + volatile ushort *l, *r; +#elif defined(CONFIG_MPC8260) + volatile iop8260_t *iop = &immap->im_ioport; + volatile uint *l, *r; +#endif + volatile uint *R; + + counter = 0; + header (); + + /* + * Ports A & B + */ + +#if defined(CONFIG_8xx) + l = &iop->iop_padir; + R = &immap->im_cpm.cp_pbdir; +#elif defined(CONFIG_MPC8260) + l = &iop->iop_pdira; + R = &iop->iop_pdirb; +#endif + binary ("PA_DIR", *l++, PA_NBITS); + binary ("PB_DIR", *R++, PB_NBITS); + binary ("PA_PAR", *l++, PA_NBITS); + binary ("PB_PAR", *R++, PB_NBITS); +#if defined(CONFIG_MPC8260) + binary ("PA_SOR", *l++, PA_NBITS); + binary ("PB_SOR", *R++, PB_NBITS); +#endif + binary ("PA_ODR", *l++, PA_NB_ODR); + binary ("PB_ODR", *R++, PB_NB_ODR); + binary ("PA_DAT", *l++, PA_NBITS); + binary ("PB_DAT", *R++, PB_NBITS); + + header (); + + /* + * Ports C & D + */ + +#if defined(CONFIG_8xx) + l = &iop->iop_pcdir; + r = &iop->iop_pddir; +#elif defined(CONFIG_MPC8260) + l = &iop->iop_pdirc; + r = &iop->iop_pdird; +#endif + binary ("PC_DIR", *l++, PC_NBITS); + binary ("PD_DIR", *r++, PD_NBITS); + binary ("PC_PAR", *l++, PC_NBITS); + binary ("PD_PAR", *r++, PD_NBITS); +#if defined(CONFIG_8xx) + binary ("PC_SO ", *l++, PC_NBITS); + binary (" ", 0, 0); + r++; +#elif defined(CONFIG_MPC8260) + binary ("PC_SOR", *l++, PC_NBITS); + binary ("PD_SOR", *r++, PD_NBITS); + binary ("PC_ODR", *l++, PC_NBITS); + binary ("PD_ODR", *r++, PD_NBITS); +#endif + binary ("PC_DAT", *l++, PC_NBITS); + binary ("PD_DAT", *r++, PD_NBITS); +#if defined(CONFIG_8xx) + binary ("PC_INT", *l++, PC_NBITS); +#endif + + header (); + return 0; +} + +/* + * set the io pins + * this needs a clean up for smaller tighter code + * use *uint and set the address based on cmd + port + */ +int +do_iopset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + uint rcode = 0; + iopin_t iopin; + static uint port = 0; + static uint pin = 0; + static uint value = 0; + static enum { + DIR, + PAR, + SOR, + ODR, + DAT, +#if defined(CONFIG_8xx) + INT +#endif + } cmd = DAT; + + if (argc != 5) { + puts ("iopset PORT PIN CMD VALUE\n"); + return 1; + } + port = argv[1][0] - 'A'; + if (port > 3) + port -= 0x20; + if (port > 3) + rcode = 1; + pin = simple_strtol (argv[2], NULL, 10); + if (pin > 31) + rcode = 1; + + + switch (argv[3][0]) { + case 'd': + if (argv[3][1] == 'a') + cmd = DAT; + else if (argv[3][1] == 'i') + cmd = DIR; + else + rcode = 1; + break; + case 'p': + cmd = PAR; + break; + case 'o': + cmd = ODR; + break; + case 's': + cmd = SOR; + break; +#if defined(CONFIG_8xx) + case 'i': + cmd = INT; + break; +#endif + default: + printf ("iopset: unknown command %s\n", argv[3]); + rcode = 1; + } + if (argv[4][0] == '1') + value = 1; + else if (argv[4][0] == '0') + value = 0; + else + rcode = 1; + if (rcode == 0) { + iopin.port = port; + iopin.pin = pin; + iopin.flag = 0; + switch (cmd) { + case DIR: + if (value) + iopin_set_out (&iopin); + else + iopin_set_in (&iopin); + break; + case PAR: + if (value) + iopin_set_ded (&iopin); + else + iopin_set_gen (&iopin); + break; + case SOR: + if (value) + iopin_set_opt2 (&iopin); + else + iopin_set_opt1 (&iopin); + break; + case ODR: + if (value) + iopin_set_odr (&iopin); + else + iopin_set_act (&iopin); + break; + case DAT: + if (value) + iopin_set_high (&iopin); + else + iopin_set_low (&iopin); + break; +#if defined(CONFIG_8xx) + case INT: + if (value) + iopin_set_falledge (&iopin); + else + iopin_set_anyedge (&iopin); + break; +#endif + } + + } + return rcode; +} + +int +do_dmainfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +int +do_fccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +static void prbrg (int n, uint val) +{ + uint extc = (val >> 14) & 3; + uint cd = (val & CPM_BRG_CD_MASK) >> 1; + uint div16 = (val & CPM_BRG_DIV16) != 0; + +#if defined(CONFIG_8xx) + ulong clock = gd->cpu_clk; +#elif defined(CONFIG_MPC8260) + ulong clock = gd->arch.brg_clk; +#endif + + printf ("BRG%d:", n); + + if (val & CPM_BRG_RST) + puts (" RESET"); + else + puts (" "); + + if (val & CPM_BRG_EN) + puts (" ENABLED"); + else + puts (" DISABLED"); + + printf (" EXTC=%d", extc); + + if (val & CPM_BRG_ATB) + puts (" ATB"); + else + puts (" "); + + printf (" DIVIDER=%4d", cd); + if (extc == 0 && cd != 0) { + uint baudrate; + + if (div16) + baudrate = (clock / 16) / (cd + 1); + else + baudrate = clock / (cd + 1); + + printf ("=%6d bps", baudrate); + } else { + puts (" "); + } + + if (val & CPM_BRG_DIV16) + puts (" DIV16"); + else + puts (" "); + + putc ('\n'); +} + +int +do_brginfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + +#if defined(CONFIG_8xx) + volatile cpm8xx_t *cp = &immap->im_cpm; + volatile uint *p = &cp->cp_brgc1; +#elif defined(CONFIG_MPC8260) + volatile uint *p = &immap->im_brgc1; +#endif + int i = 1; + + while (i <= 4) + prbrg (i++, *p++); + +#if defined(CONFIG_MPC8260) + p = &immap->im_brgc5; + while (i <= 8) + prbrg (i++, *p++); +#endif + return 0; +} + +int +do_i2cinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; + +#if defined(CONFIG_8xx) + volatile i2c8xx_t *i2c = &immap->im_i2c; + volatile cpm8xx_t *cp = &immap->im_cpm; + volatile iic_t *iip = (iic_t *) & cp->cp_dparam[PROFF_IIC]; +#elif defined(CONFIG_MPC8260) + volatile i2c8260_t *i2c = &immap->im_i2c; + volatile iic_t *iip; + uint dpaddr; + + dpaddr = immap->im_dprambase16[PROFF_I2C_BASE / sizeof(u16)]; + if (dpaddr == 0) + iip = NULL; + else + iip = (iic_t *) & immap->im_dprambase[dpaddr]; +#endif + + printf ("I2MOD = %02x I2ADD = %02x\n", i2c->i2c_i2mod, i2c->i2c_i2add); + printf ("I2BRG = %02x I2COM = %02x\n", i2c->i2c_i2brg, i2c->i2c_i2com); + printf ("I2CER = %02x I2CMR = %02x\n", i2c->i2c_i2cer, i2c->i2c_i2cmr); + + if (iip == NULL) + puts ("i2c parameter ram not allocated\n"); + else { + printf ("RBASE = %08x TBASE = %08x\n", + iip->iic_rbase, iip->iic_tbase); + printf ("RFCR = %02x TFCR = %02x\n", + iip->iic_rfcr, iip->iic_tfcr); + printf ("MRBLR = %04x\n", iip->iic_mrblr); + printf ("RSTATE= %08x RDP = %08x\n", + iip->iic_rstate, iip->iic_rdp); + printf ("RBPTR = %04x RBC = %04x\n", + iip->iic_rbptr, iip->iic_rbc); + printf ("RXTMP = %08x\n", iip->iic_rxtmp); + printf ("TSTATE= %08x TDP = %08x\n", + iip->iic_tstate, iip->iic_tdp); + printf ("TBPTR = %04x TBC = %04x\n", + iip->iic_tbptr, iip->iic_tbc); + printf ("TXTMP = %08x\n", iip->iic_txtmp); + } + return 0; +} + +int +do_sccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +int +do_smcinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +int +do_spiinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +int +do_muxinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +int +do_siinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +int +do_mccinfo (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unimplemented (cmdtp, flag, argc, argv); + return 0; +} + +/***************************************************/ + +U_BOOT_CMD( + siuinfo, 1, 1, do_siuinfo, + "print System Interface Unit (SIU) registers", + "" +); + +U_BOOT_CMD( + memcinfo, 1, 1, do_memcinfo, + "print Memory Controller registers", + "" +); + +U_BOOT_CMD( + sitinfo, 1, 1, do_sitinfo, + "print System Integration Timers (SIT) registers", + "" +); + +#ifdef CONFIG_MPC8260 +U_BOOT_CMD( + icinfo, 1, 1, do_icinfo, + "print Interrupt Controller registers", + "" +); +#endif + +U_BOOT_CMD( + carinfo, 1, 1, do_carinfo, + "print Clocks and Reset registers", + "" +); + +U_BOOT_CMD( + iopinfo, 1, 1, do_iopinfo, + "print I/O Port registers", + "" +); + +U_BOOT_CMD( + iopset, 5, 0, do_iopset, + "set I/O Port registers", + "PORT PIN CMD VALUE\nPORT: A-D, PIN: 0-31, CMD: [dat|dir|odr|sor], VALUE: 0|1" +); + +U_BOOT_CMD( + dmainfo, 1, 1, do_dmainfo, + "print SDMA/IDMA registers", + "" +); + +U_BOOT_CMD( + fccinfo, 1, 1, do_fccinfo, + "print FCC registers", + "" +); + +U_BOOT_CMD( + brginfo, 1, 1, do_brginfo, + "print Baud Rate Generator (BRG) registers", + "" +); + +U_BOOT_CMD( + i2cinfo, 1, 1, do_i2cinfo, + "print I2C registers", + "" +); + +U_BOOT_CMD( + sccinfo, 1, 1, do_sccinfo, + "print SCC registers", + "" +); + +U_BOOT_CMD( + smcinfo, 1, 1, do_smcinfo, + "print SMC registers", + "" +); + +U_BOOT_CMD( + spiinfo, 1, 1, do_spiinfo, + "print Serial Peripheral Interface (SPI) registers", + "" +); + +U_BOOT_CMD( + muxinfo, 1, 1, do_muxinfo, + "print CPM Multiplexing registers", + "" +); + +U_BOOT_CMD( + siinfo, 1, 1, do_siinfo, + "print Serial Interface (SI) registers", + "" +); + +U_BOOT_CMD( + mccinfo, 1, 1, do_mccinfo, + "print MCC registers", + "" +); + +#endif |