diff options
Diffstat (limited to 'arch')
28 files changed, 14427 insertions, 14 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 277c3ba..38a6187 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -108,6 +108,7 @@ source "board/intel/Kconfig" # platform-specific options below source "arch/x86/cpu/baytrail/Kconfig" +source "arch/x86/cpu/braswell/Kconfig" source "arch/x86/cpu/broadwell/Kconfig" source "arch/x86/cpu/coreboot/Kconfig" source "arch/x86/cpu/ivybridge/Kconfig" @@ -558,6 +559,48 @@ config VGA_BIOS_ADDR address of 0xfff90000 indicates that the image will be put at offset 0x90000 from the beginning of a 1MB flash device. +config HAVE_VBT + bool "Add a Video BIOS Table (VBT) image" + depends on HAVE_FSP + help + Select this option if you have a Video BIOS Table (VBT) image that + you would like to add to your ROM. This is normally required if you + are using an Intel FSP firmware that is complaint with spec 1.1 or + later to initialize the integrated graphics device (IGD). + + Video BIOS Table, or VBT, provides platform and board specific + configuration information to the driver that is not discoverable + or available through other means. By other means the most used + method here is to read EDID table from the attached monitor, over + Display Data Channel (DDC) using two pin I2C serial interface. VBT + configuration is related to display hardware and is available via + the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM). + +config VBT_FILE + string "Video BIOS Table (VBT) image filename" + depends on HAVE_VBT + default "vbt.bin" + help + The filename of the file to use as Video BIOS Table (VBT) image + in the board directory. + +config VBT_ADDR + hex "Video BIOS Table (VBT) image location" + depends on HAVE_VBT + default 0xfff90000 + help + The location of Video BIOS Table (VBT) image in the SPI flash. For + example, base address of 0xfff90000 indicates that the image will + be put at offset 0x90000 from the beginning of a 1MB flash device. + +config VIDEO_FSP + bool "Enable FSP framebuffer driver support" + depends on HAVE_VBT && DM_VIDEO + help + Turn on this option to enable a framebuffer driver when U-Boot is + using Video BIOS Table (VBT) image for FSP firmware to initialize + the integrated graphics device. + config ROM_TABLE_ADDR hex default 0xf0000 diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 999429e..94cdff1 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -27,6 +27,7 @@ endif obj-y += intel_common/ obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/ +obj-$(CONFIG_INTEL_BRASWELL) += braswell/ obj-$(CONFIG_INTEL_BROADWELL) += broadwell/ obj-$(CONFIG_SYS_COREBOOT) += coreboot/ obj-$(CONFIG_EFI_APP) += efi/ diff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig new file mode 100644 index 0000000..0e214a7 --- /dev/null +++ b/arch/x86/cpu/braswell/Kconfig @@ -0,0 +1,39 @@ +# +# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +config INTEL_BRASWELL + bool + select HAVE_FSP + select ARCH_MISC_INIT + select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED + imply HAVE_INTEL_ME + imply HAVE_VBT + imply ENABLE_MRC_CACHE + imply ENV_IS_IN_SPI_FLASH + imply AHCI_PCI + imply ICH_SPI + imply MMC + imply MMC_PCI + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply SCSI + imply SPI_FLASH + imply SYS_NS16550 + imply USB + imply USB_XHCI_HCD + imply VIDEO_FSP + +if INTEL_BRASWELL + +config FSP_ADDR + hex + default 0xfff20000 + +config FSP_LOCKDOWN_SPI + bool + default y + +endif diff --git a/arch/x86/cpu/braswell/Makefile b/arch/x86/cpu/braswell/Makefile new file mode 100644 index 0000000..ddf6d28 --- /dev/null +++ b/arch/x86/cpu/braswell/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += braswell.o cpu.o early_uart.o fsp_configs.o diff --git a/arch/x86/cpu/braswell/braswell.c b/arch/x86/cpu/braswell/braswell.c new file mode 100644 index 0000000..37099aa --- /dev/null +++ b/arch/x86/cpu/braswell/braswell.c @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/mrccache.h> +#include <asm/post.h> + +int arch_cpu_init(void) +{ + post_code(POST_CPU_INIT); + + return x86_cpu_init_f(); +} + +int arch_misc_init(void) +{ +#ifdef CONFIG_ENABLE_MRC_CACHE + /* + * We intend not to check any return value here, as even MRC cache + * is not saved successfully, it is not a severe error that will + * prevent system from continuing to boot. + */ + mrccache_save(); +#endif + + return 0; +} + +void reset_cpu(ulong addr) +{ + /* cold reset */ + x86_full_reset(); +} diff --git a/arch/x86/cpu/braswell/cpu.c b/arch/x86/cpu/braswell/cpu.c new file mode 100644 index 0000000..6ff9036 --- /dev/null +++ b/arch/x86/cpu/braswell/cpu.c @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Derived from arch/x86/cpu/baytrail/cpu.c + */ + +#include <common.h> +#include <cpu.h> +#include <dm.h> +#include <asm/cpu.h> +#include <asm/cpu_x86.h> +#include <asm/io.h> +#include <asm/lapic.h> +#include <asm/msr.h> +#include <asm/turbo.h> + +static const unsigned int braswell_bus_freq_table[] = { + 83333333, + 100000000, + 133333333, + 116666666, + 80000000, + 93333333, + 90000000, + 88900000, + 87500000 +}; + +static unsigned int braswell_bus_freq(void) +{ + msr_t clk_info = msr_read(MSR_BSEL_CR_OVERCLOCK_CONTROL); + + if ((clk_info.lo & 0xf) < (ARRAY_SIZE(braswell_bus_freq_table))) + return braswell_bus_freq_table[clk_info.lo & 0xf]; + + return 0; +} + +static unsigned long braswell_tsc_freq(void) +{ + msr_t platform_info; + ulong bclk = braswell_bus_freq(); + + if (!bclk) + return 0; + + platform_info = msr_read(MSR_PLATFORM_INFO); + + return bclk * ((platform_info.lo >> 8) & 0xff); +} + +static int braswell_get_info(struct udevice *dev, struct cpu_info *info) +{ + info->cpu_freq = braswell_tsc_freq(); + info->features = (1 << CPU_FEAT_L1_CACHE) | (1 << CPU_FEAT_MMU); + + return 0; +} + +static int braswell_get_count(struct udevice *dev) +{ + int ecx = 0; + + /* + * Use the algorithm described in Intel 64 and IA-32 Architectures + * Software Developer's Manual Volume 3 (3A, 3B & 3C): System + * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping + * of CPUID Extended Topology Leaf. + */ + while (1) { + struct cpuid_result leaf_b; + + leaf_b = cpuid_ext(0xb, ecx); + + /* + * Braswell doesn't have hyperthreading so just determine the + * number of cores by from level type (ecx[15:8] == * 2) + */ + if ((leaf_b.ecx & 0xff00) == 0x0200) + return leaf_b.ebx & 0xffff; + + ecx++; + } + + return 0; +} + +static void braswell_set_max_freq(void) +{ + msr_t perf_ctl; + msr_t msr; + + /* Enable speed step */ + msr = msr_read(MSR_IA32_MISC_ENABLES); + msr.lo |= (1 << 16); + msr_write(MSR_IA32_MISC_ENABLES, msr); + + /* Enable Burst Mode */ + msr = msr_read(MSR_IA32_MISC_ENABLES); + msr.hi = 0; + msr_write(MSR_IA32_MISC_ENABLES, msr); + + /* + * Set guaranteed ratio [21:16] from IACORE_TURBO_RATIOS to + * bits [15:8] of the PERF_CTL + */ + msr = msr_read(MSR_IACORE_TURBO_RATIOS); + perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; + + /* + * Set guaranteed vid [22:16] from IACORE_TURBO_VIDS to + * bits [7:0] of the PERF_CTL + */ + msr = msr_read(MSR_IACORE_TURBO_VIDS); + perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; + + perf_ctl.hi = 0; + msr_write(MSR_IA32_PERF_CTL, perf_ctl); +} + +static int braswell_probe(struct udevice *dev) +{ + debug("Init Braswell core\n"); + + /* + * On Braswell the turbo disable bit is actually scoped at the + * building-block level, not package. For non-BSP cores that are + * within a building block, enable turbo. The cores within the BSP's + * building block will just see it already enabled and move on. + */ + if (lapicid()) + turbo_enable(); + + /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ + msr_clrsetbits_64(MSR_PMG_CST_CONFIG_CONTROL, 0x3f080f, 0xe0008), + msr_clrsetbits_64(MSR_POWER_MISC, + ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK, 0); + + /* Disable C1E */ + msr_clrsetbits_64(MSR_POWER_CTL, 2, 0); + msr_setbits_64(MSR_POWER_MISC, 0x44); + + /* Set this core to max frequency ratio */ + braswell_set_max_freq(); + + return 0; +} + +static const struct udevice_id braswell_ids[] = { + { .compatible = "intel,braswell-cpu" }, + { } +}; + +static const struct cpu_ops braswell_ops = { + .get_desc = cpu_x86_get_desc, + .get_info = braswell_get_info, + .get_count = braswell_get_count, + .get_vendor = cpu_x86_get_vendor, +}; + +U_BOOT_DRIVER(cpu_x86_braswell_drv) = { + .name = "cpu_x86_braswell", + .id = UCLASS_CPU, + .of_match = braswell_ids, + .bind = cpu_x86_bind, + .probe = braswell_probe, + .ops = &braswell_ops, +}; diff --git a/arch/x86/cpu/braswell/early_uart.c b/arch/x86/cpu/braswell/early_uart.c new file mode 100644 index 0000000..c70a885 --- /dev/null +++ b/arch/x86/cpu/braswell/early_uart.c @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> + +#define PCI_DEV_CONFIG(segbus, dev, fn) ( \ + (((segbus) & 0xfff) << 20) | \ + (((dev) & 0x1f) << 15) | \ + (((fn) & 0x07) << 12)) + +/* Platform Controller Unit */ +#define LPC_DEV 0x1f +#define LPC_FUNC 0 + +/* Enable UART */ +#define UART_CONT 0x80 + +/* UART PAD definitions */ +#define UART_RXD_COMMUITY 1 +#define UART_TXD_COMMUITY 1 +#define UART_RXD_FAMILY 4 +#define UART_TXD_FAMILY 4 +#define UART_RXD_PAD 2 +#define UART_TXD_PAD 7 +#define UART_RXD_FUNC 3 +#define UART_TXD_FUNC 3 + +/* IO Memory */ +#define IO_BASE_ADDRESS 0xfed80000 + +static inline uint32_t gpio_pconf0(int community, int family, int pad) +{ + return IO_BASE_ADDRESS + community * 0x8000 + 0x4400 + + family * 0x400 + pad * 8; +} + +static void gpio_select_func(int community, int family, int pad, int func) +{ + uint32_t pconf0_addr = gpio_pconf0(community, family, pad); + + clrsetbits_le32(pconf0_addr, 0xf << 16, func << 16); +} + +static void x86_pci_write_config32(int dev, unsigned int where, u32 value) +{ + unsigned long addr; + + addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3); + writel(value, addr); +} + +/* This can be called after memory-mapped PCI is working */ +int setup_internal_uart(int enable) +{ + /* Enable or disable the legacy UART hardware */ + x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, + enable); + + /* All done for the disable part, so just return */ + if (!enable) + return 0; + + /* + * Set up the pads to the UART function. This allows the signals to + * leave the chip + */ + gpio_select_func(UART_RXD_COMMUITY, UART_RXD_FAMILY, + UART_RXD_PAD, UART_RXD_FUNC); + gpio_select_func(UART_TXD_COMMUITY, UART_TXD_FAMILY, + UART_TXD_PAD, UART_TXD_FUNC); + + return 0; +} + +void board_debug_uart_init(void) +{ + setup_internal_uart(1); +} diff --git a/arch/x86/cpu/braswell/fsp_configs.c b/arch/x86/cpu/braswell/fsp_configs.c new file mode 100644 index 0000000..249f851 --- /dev/null +++ b/arch/x86/cpu/braswell/fsp_configs.c @@ -0,0 +1,164 @@ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <asm/fsp/fsp_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * Override the FSP's Azalia configuration data + * + * @azalia: pointer to be updated to point to a ROM address where Azalia + * configuration data is stored + */ +__weak void update_fsp_azalia_configs(struct azalia_config **azalia) +{ + *azalia = NULL; +} + +/** + * Override the FSP's GPIO configuration data + * + * @family: pointer to be updated to point to a ROM address where GPIO + * family configuration data is stored + * @pad: pointer to be updated to point to a ROM address where GPIO + * pad configuration data is stored + */ +__weak void update_fsp_gpio_configs(struct gpio_family **family, + struct gpio_pad **pad) +{ + *family = NULL; + *pad = NULL; +} + +/** + * Override the FSP's configuration data. + * If the device tree does not specify an integer setting, use the default + * provided in Intel's Braswell release FSP/BraswellFsp.bsf file. + */ +void update_fsp_configs(struct fsp_config_data *config, + struct fspinit_rtbuf *rt_buf) +{ + struct upd_region *fsp_upd = &config->fsp_upd; + struct memory_upd *memory_upd = &fsp_upd->memory_upd; + struct silicon_upd *silicon_upd = &fsp_upd->silicon_upd; + const void *blob = gd->fdt_blob; + int node; + + /* Initialize runtime buffer for fsp_init() */ + rt_buf->common.stack_top = config->common.stack_top - 32; + rt_buf->common.boot_mode = config->common.boot_mode; + rt_buf->common.upd_data = &config->fsp_upd; + + node = fdt_node_offset_by_compatible(blob, 0, "intel,braswell-fsp"); + if (node < 0) { + debug("%s: Cannot find FSP node\n", __func__); + return; + } + + node = fdt_node_offset_by_compatible(blob, node, + "intel,braswell-fsp-memory"); + if (node < 0) { + debug("%s: Cannot find FSP memory node\n", __func__); + return; + } + + /* Override memory UPD contents */ + memory_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node, + "fsp,mrc-init-tseg-size", MRC_INIT_TSEG_SIZE_4MB); + memory_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node, + "fsp,mrc-init-mmio-size", MRC_INIT_MMIO_SIZE_2048MB); + memory_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node, + "fsp,mrc-init-spd-addr1", 0xa0); + memory_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node, + "fsp,mrc-init-spd-addr2", 0xa2); + memory_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node, + "fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_32MB); + memory_upd->aperture_size = fdtdec_get_int(blob, node, + "fsp,aperture-size", APERTURE_SIZE_256MB); + memory_upd->gtt_size = fdtdec_get_int(blob, node, + "fsp,gtt-size", GTT_SIZE_1MB); + memory_upd->legacy_seg_decode = fdtdec_get_bool(blob, node, + "fsp,legacy-seg-decode"); + memory_upd->enable_dvfs = fdtdec_get_bool(blob, node, + "fsp,enable-dvfs"); + memory_upd->memory_type = fdtdec_get_int(blob, node, + "fsp,memory-type", DRAM_TYPE_DDR3); + memory_upd->enable_ca_mirror = fdtdec_get_bool(blob, node, + "fsp,enable-ca-mirror"); + + node = fdt_node_offset_by_compatible(blob, node, + "intel,braswell-fsp-silicon"); + if (node < 0) { + debug("%s: Cannot find FSP silicon node\n", __func__); + return; + } + + /* Override silicon UPD contents */ + silicon_upd->sdcard_mode = fdtdec_get_int(blob, node, + "fsp,sdcard-mode", SDCARD_MODE_PCI); + silicon_upd->enable_hsuart0 = fdtdec_get_bool(blob, node, + "fsp,enable-hsuart0"); + silicon_upd->enable_hsuart1 = fdtdec_get_bool(blob, node, + "fsp,enable-hsuart1"); + silicon_upd->enable_azalia = fdtdec_get_bool(blob, node, + "fsp,enable-azalia"); + if (silicon_upd->enable_azalia) + update_fsp_azalia_configs(&silicon_upd->azalia_cfg_ptr); + silicon_upd->enable_sata = fdtdec_get_bool(blob, node, + "fsp,enable-sata"); + silicon_upd->enable_xhci = fdtdec_get_bool(blob, node, + "fsp,enable-xhci"); + silicon_upd->lpe_mode = fdtdec_get_int(blob, node, + "fsp,lpe-mode", LPE_MODE_PCI); + silicon_upd->enable_dma0 = fdtdec_get_bool(blob, node, + "fsp,enable-dma0"); + silicon_upd->enable_dma1 = fdtdec_get_bool(blob, node, + "fsp,enable-dma1"); + silicon_upd->enable_i2c0 = fdtdec_get_bool(blob, node, + "fsp,enable-i2c0"); + silicon_upd->enable_i2c1 = fdtdec_get_bool(blob, node, + "fsp,enable-i2c1"); + silicon_upd->enable_i2c2 = fdtdec_get_bool(blob, node, + "fsp,enable-i2c2"); + silicon_upd->enable_i2c3 = fdtdec_get_bool(blob, node, + "fsp,enable-i2c3"); + silicon_upd->enable_i2c4 = fdtdec_get_bool(blob, node, + "fsp,enable-i2c4"); + silicon_upd->enable_i2c5 = fdtdec_get_bool(blob, node, + "fsp,enable-i2c5"); + silicon_upd->enable_i2c6 = fdtdec_get_bool(blob, node, + "fsp,enable-i2c6"); +#ifdef CONFIG_HAVE_VBT + silicon_upd->graphics_config_ptr = CONFIG_VBT_ADDR; +#endif + update_fsp_gpio_configs(&silicon_upd->gpio_familiy_ptr, + &silicon_upd->gpio_pad_ptr); + /* + * For Braswell B0 stepping, disable_punit_pwr_config must be set to 1 + * otherwise it just hangs in fsp_init(). + */ + if (gd->arch.x86_mask == 2) + silicon_upd->disable_punit_pwr_config = 1; + silicon_upd->emmc_mode = fdtdec_get_int(blob, node, + "fsp,emmc-mode", EMMC_MODE_PCI); + silicon_upd->sata_speed = fdtdec_get_int(blob, node, + "fsp,sata-speed", SATA_SPEED_GEN3); + silicon_upd->pmic_i2c_bus = fdtdec_get_int(blob, node, + "fsp,pmic-i2c-bus", 0); + silicon_upd->enable_isp = fdtdec_get_bool(blob, node, + "fsp,enable-isp"); + silicon_upd->isp_pci_dev_config = fdtdec_get_int(blob, node, + "fsp,isp-pci-dev-config", ISP_PCI_DEV_CONFIG_2); + silicon_upd->turbo_mode = fdtdec_get_bool(blob, node, + "fsp,turbo-mode"); + silicon_upd->pnp_settings = fdtdec_get_int(blob, node, + "fsp,pnp-settings", PNP_SETTING_POWER_AND_PERF); + silicon_upd->sd_detect_chk = fdtdec_get_bool(blob, node, + "fsp,sd-detect-chk"); +} diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index 94f31c4..4429429 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -34,16 +34,6 @@ int bridge_silicon_revision(struct udevice *dev) return bridge_id | stepping; } -/* - * Reserve everything between A segment and 1MB: - * - * 0xa0000 - 0xbffff: legacy VGA - * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) - * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI - */ -static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 384; - static int get_pcie_bar(struct udevice *dev, u32 *base, u32 *len) { u32 pciexbar_reg; diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 6589495..6d0c4b6 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -3,6 +3,7 @@ # dtb-y += bayleybay.dtb \ + cherryhill.dtb \ chromebook_link.dtb \ chromebox_panther.dtb \ chromebook_samus.dtb \ diff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts new file mode 100644 index 0000000..1ccb605 --- /dev/null +++ b/arch/x86/dts/cherryhill.dts @@ -0,0 +1,215 @@ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include <asm/arch-braswell/fsp/fsp_configs.h> +#include <dt-bindings/interrupt-router/intel-irq.h> + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +/ { + model = "Intel Cherry Hill"; + compatible = "intel,cherryhill", "intel,braswell"; + + aliases { + serial0 = &serial; + spi0 = &spi; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,braswell-cpu"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,braswell-cpu"; + reg = <1>; + intel,apic-id = <2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,braswell-cpu"; + reg = <2>; + intel,apic-id = <4>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,braswell-cpu"; + reg = <3>; + intel,apic-id = <6>; + }; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,pch9"; + #address-cells = <1>; + #size-cells = <1>; + + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "ibase"; + intel,ibase-offset = <0x50>; + intel,pirq-link = <8 8>; + intel,pirq-mask = <0xdee0>; + intel,pirq-routing = < + /* Braswell PCI devices */ + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQA + PCI_BDF(0, 11, 0) INTA PIRQA + PCI_BDF(0, 16, 0) INTA PIRQA + PCI_BDF(0, 17, 0) INTA PIRQA + PCI_BDF(0, 18, 0) INTA PIRQA + PCI_BDF(0, 19, 0) INTA PIRQA + PCI_BDF(0, 20, 0) INTA PIRQA + PCI_BDF(0, 21, 0) INTA PIRQA + PCI_BDF(0, 24, 0) INTA PIRQA + PCI_BDF(0, 24, 1) INTC PIRQC + PCI_BDF(0, 24, 2) INTD PIRQD + PCI_BDF(0, 24, 3) INTB PIRQB + PCI_BDF(0, 24, 4) INTA PIRQA + PCI_BDF(0, 24, 5) INTC PIRQC + PCI_BDF(0, 24, 6) INTD PIRQD + PCI_BDF(0, 24, 7) INTB PIRQB + PCI_BDF(0, 26, 0) INTA PIRQA + PCI_BDF(0, 27, 0) INTA PIRQA + PCI_BDF(0, 28, 0) INTA PIRQA + PCI_BDF(0, 28, 1) INTB PIRQB + PCI_BDF(0, 28, 2) INTC PIRQC + PCI_BDF(0, 28, 3) INTD PIRQD + PCI_BDF(0, 30, 0) INTA PIRQA + PCI_BDF(0, 30, 3) INTA PIRQA + PCI_BDF(0, 30, 4) INTA PIRQA + PCI_BDF(0, 31, 0) INTB PIRQB + PCI_BDF(0, 31, 3) INTB PIRQB + + /* + * PCIe root ports downstream + * interrupts + */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(1, 0, 0) INTB PIRQB + PCI_BDF(1, 0, 0) INTC PIRQC + PCI_BDF(1, 0, 0) INTD PIRQD + PCI_BDF(2, 0, 0) INTA PIRQB + PCI_BDF(2, 0, 0) INTB PIRQC + PCI_BDF(2, 0, 0) INTC PIRQD + PCI_BDF(2, 0, 0) INTD PIRQA + PCI_BDF(3, 0, 0) INTA PIRQC + PCI_BDF(3, 0, 0) INTB PIRQD + PCI_BDF(3, 0, 0) INTC PIRQA + PCI_BDF(3, 0, 0) INTD PIRQB + PCI_BDF(4, 0, 0) INTA PIRQD + PCI_BDF(4, 0, 0) INTB PIRQA + PCI_BDF(4, 0, 0) INTC PIRQB + PCI_BDF(4, 0, 0) INTD PIRQC + >; + }; + + spi: spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich9-spi"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "macronix,mx25u6435f", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x005e0000 0x00010000>; + }; + }; + }; + }; + }; + + fsp { + compatible = "intel,braswell-fsp"; + fsp,memory-upd { + compatible = "intel,braswell-fsp-memory"; + fsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_4MB>; + fsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>; + fsp,mrc-init-spd-addr1 = <0xa0>; + fsp,mrc-init-spd-addr2 = <0xa2>; + fsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_32MB>; + fsp,aperture-size = <APERTURE_SIZE_256MB>; + fsp,gtt-size = <GTT_SIZE_1MB>; + fsp,enable-dvfs; + fsp,memory-type = <DRAM_TYPE_DDR3>; + }; + fsp,silicon-upd { + compatible = "intel,braswell-fsp-silicon"; + fsp,sdcard-mode = <SDCARD_MODE_PCI>; + fsp,enable-hsuart1; + fsp,enable-sata; + fsp,enable-xhci; + fsp,lpe-mode = <LPE_MODE_PCI>; + fsp,enable-dma0; + fsp,enable-dma1; + fsp,enable-i2c0; + fsp,enable-i2c1; + fsp,enable-i2c2; + fsp,enable-i2c3; + fsp,enable-i2c4; + fsp,enable-i2c5; + fsp,enable-i2c6; + fsp,emmc-mode = <EMMC_MODE_PCI>; + fsp,sata-speed = <SATA_SPEED_GEN3>; + fsp,pmic-i2c-bus = <0>; + fsp,enable-isp; + fsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>; + fsp,turbo-mode; + fsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>; + fsp,sd-detect-chk; + }; + }; + + microcode { + update@0 { +#include "microcode/m01406c2220.dtsi" + }; + update@1 { +#include "microcode/m01406c3363.dtsi" + }; + update@2 { +#include "microcode/m01406c440a.dtsi" + }; + }; + +}; diff --git a/arch/x86/dts/microcode/m01406c2220.dtsi b/arch/x86/dts/microcode/m01406c2220.dtsi new file mode 100644 index 0000000..cf17dea --- /dev/null +++ b/arch/x86/dts/microcode/m01406c2220.dtsi @@ -0,0 +1,4308 @@ +/* + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x220>; +intel,date-code = <0x1142015>; +intel,processor-signature = <0x406c2>; +intel,checksum = <0x21a02433>; +intel,loader-revision = <1>; +intel,processor-flags = <0x1>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x20020000 0x15201401 0xc2060400 + 0x3324a021 0x01000000 0x01000000 0xd00b0100 + 0x000c0100 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x20020000 + 0x00000000 0x00000000 0x14011520 0xe1420000 + 0x01000000 0xc2060400 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x17ce1b3d 0x74fb4eb5 0x2f27d633 0x14060671 + 0x6b4d57b0 0xaa1ad327 0x6022d785 0x5fa91aad + 0xef44e4c3 0xf91d4958 0x230883b7 0x7382ab6e + 0xf14324ef 0xf94c28d7 0x9131d196 0xebcf2faa + 0xc049cb37 0xd1577abd 0x5edbe45a 0x17e1ca1e + 0xbe9a92c3 0x1c8e1790 0xb3c08b8a 0xca799851 + 0x3f2a8c92 0x1b7e15d8 0x1f44ecb2 0xaeda1838 + 0x0ace8669 0xae9d497e 0x424c680c 0x21b3a3ed + 0xd924acfe 0xddc126a2 0x26363596 0x21cd999b + 0x193f9df3 0x037d1953 0xf97a3dc5 0x4c94ad7e + 0x98b360f0 0xeb90461f 0x438e6d2e 0x30851a0e + 0xfd623681 0x18782d3c 0x702938c5 0x462df0dd + 0xf7d67cc1 0x161076a0 0xf06e5db3 0xd861a76b + 0xa40b06bc 0xed37c69b 0x2b25f98b 0x2b67887d + 0xbf0131b5 0x571b7c25 0x34eb3752 0x992e406e + 0x031ba8e7 0xccfc5b1d 0x33f487e9 0xeccc3098 + 0xe452737b 0xb38cc286 0x817bc58f 0x852a7fde + 0xcbcd1b19 0xab11894a 0xa1f278d7 0x360829c9 + 0x11000000 0x67a4c01f 0x3f863221 0xf4b82fe4 + 0xf464c489 0x36b8d097 0xfa9ab17e 0x9bccf4e6 + 0x9f836ffd 0x647c263c 0x03c7bede 0xf20172e9 + 0x8bd6e772 0x8621aca5 0xbdf4eade 0xac27528a + 0xb562042b 0x23d0304c 0x964558ea 0xb5c03c97 + 0xe0bd0467 0xe8a6d50a 0xe5d4b902 0xb164253e + 0x8306959c 0xd1cd57d5 0xf7d1d586 0x4eb5152b + 0xf488caca 0xaa47f32f 0x366676b3 0x96b27e47 + 0xc8f4fdda 0x9f6854bb 0x89921eb5 0xbb7fe720 + 0x59709d36 0x01a5880c 0xee526518 0x586055d6 + 0xfac43c7a 0x7ce6da62 0x301be309 0xf48c261e + 0xdd7d6b27 0x6783c81a 0xf9151492 0x92a57bd1 + 0x94607cfc 0xd70700ed 0x18136034 0x16d26594 + 0xeadd5210 0xf2fa345f 0xba7e9be4 0x548b8db1 + 0xd9d81a27 0xb361bae3 0xe2c5c033 0xd34d0488 + 0x07925cd2 0xaf57a669 0xf7f634b6 0x58408a6f + 0x2c8b4c46 0xe71e9a53 0x65bc42be 0x77db4bf1 + 0x4c839bf5 0xd6dbc641 0x4fbf6fef 0x6b71eb34 + 0x808898b9 0x7ecea348 0x608a1d5e 0x81225ea2 + 0x487a3d44 0xc2443f3e 0xff580d9a 0xefd915b1 + 0xe867848b 0x73c48e53 0x84d211d4 0x77a45152 + 0x146f95fc 0x088157cb 0x9661fa65 0x6b998636 + 0xd8d8748d 0x16bb32b5 0x3eb3be6a 0x29a2aa6e + 0xcbd08ca6 0x74317789 0xe9e8f1ea 0x7c555679 + 0xd7f19a7b 0xcead34da 0xe584403c 0xbfae80e2 + 0x4e9a7a52 0x0eefa659 0x00eb4354 0xe6f0cf6d + 0x69374a24 0xdb59e992 0x2d4a51eb 0x4cdb46ca + 0x03613349 0x24d146ab 0x1cca9b58 0x6db9989a + 0x534dedef 0xab90d703 0x75a8331b 0xec865e24 + 0x8415faf2 0x851022e8 0x4ee795cd 0x7af2b1a8 + 0x65ec359a 0x0a16c7d8 0x76d51f56 0x7e1e10ec + 0xbab138d8 0x0d69389e 0x0a50fc3a 0x7746732d + 0x98f692d2 0xf97254ff 0xd31185d4 0x1a7104b4 + 0x1382fbff 0x4660f775 0x187ed97f 0x880cb07a + 0x566157d2 0x1ec58c53 0xc1fff1e3 0x30cde9d6 + 0x933993eb 0x365c5318 0x30a5df05 0x91744f18 + 0xac99ae3a 0xacb5cc81 0x6af06584 0xcbfcb5dc + 0x10e3cdd1 0x8d31a621 0x36851aa8 0x718c1d81 + 0x4a574346 0x70fb532a 0xc97b70e3 0x4e61d0d1 + 0x9e5e2563 0xd86da543 0xb6c07a52 0x417e59f2 + 0xee4c48d6 0xca38e12e 0x9188a73d 0x6624af3c + 0x62a1d33f 0xcf8afe37 0xd0173727 0x378470e3 + 0x35067424 0x0775c48c 0x7cab8eb0 0xfeb84d6c + 0x187fbb8c 0xe2cab639 0xedfc3f59 0xbace1601 + 0xbc2535e9 0x74b7d16e 0xbc351b20 0xf4a41f6f + 0x996a0c11 0xec1e5d06 0x8dae9d53 0xe92082ce + 0x8bfb678f 0xb4ae58e4 0xbecbf0de 0xfdbd1df9 + 0x0cf5ffe2 0x362f4eb5 0x90cc7b4e 0x813a329d + 0xd6b5c9fc 0x19dea293 0x4bc51036 0x10570f4b + 0xd904d7b6 0x348da9e4 0x2fd7a32d 0xfc79b430 + 0x0b9c30dd 0xe0289eb6 0xc6ef55ef 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Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x363>; +intel,date-code = <0x12182015>; +intel,processor-signature = <0x406c3>; +intel,checksum = <0x3ecdece5>; +intel,loader-revision = <1>; +intel,processor-flags = <0x1>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x63030000 0x15201812 0xc3060400 + 0xe5eccd3e 0x01000000 0x01000000 0xd00b0100 + 0x000c0100 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x63030000 + 0x00000000 0x00000000 0x18121520 0xf1420000 + 0x01000000 0xc3060400 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x6abbab24 0x789752cb 0x83003819 0x616df082 + 0xf0952c2c 0x7fbf7fbe 0xe1ca9540 0x47bb7ec7 + 0xef44e4c3 0xf91d4958 0x230883b7 0x7382ab6e + 0xf14324ef 0xf94c28d7 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Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x40a>; +intel,date-code = <0x12182015>; +intel,processor-signature = <0x406c4>; +intel,checksum = <0x5807e19a>; +intel,loader-revision = <1>; +intel,processor-flags = <0x1>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x0a040000 0x15201812 0xc4060400 + 0x9ae10758 0x01000000 0x01000000 0xd00b0100 + 0x000c0100 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x0a040000 + 0x00000000 0x00000000 0x18121520 0xe1420000 + 0x01000000 0xc4060400 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x624800aa 0xf01ac54c 0x5a84228f 0xcc79131d + 0x9feff6a3 0x4a87b5a3 0xac874956 0x7dfe6197 + 0xef44e4c3 0xf91d4958 0x230883b7 0x7382ab6e + 0xf14324ef 0xf94c28d7 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0xd41e4d6a + 0xae016134 0x87b7b2c9 0xd994b3e9 0x71e42004 + 0xb845d3af 0x592dbebb 0x620899c0 0x8d3b090d + 0x9d0e6a42 0xce95d950 0x4b7117d0 0x4e32208e + 0x379df4c7 0x73c8403d 0x9c035976 0x9fa4ab3f + 0x0e4abd10 0xea5abdc0 0xc74b08f5 0x8ad84f2f + 0xe6ea941f 0xedd37fd7 0x8800959d 0x4eaf1dd9 + 0xc03f8601 0x3f05cec7 0xa7dc9585 0xfc497aa7 + 0x5ab6ec8d 0xf920b15a 0x0528a3a0 0xb03478f9 + 0xf58d945c 0xf6d56911 0x9d6b8f61 0x62eced7e + 0x8c387967 0xb9c3664c 0x703321a1 0xb0779fb6 + 0x0a5ca536 0x216262ca 0x8471e2dc 0x456035c2 + 0x1f9a3f80 0x62f7b45b 0xe0fb6e10 0xd817b0a1 + 0xb04007a7 0x8a2a3997 0xc13b2ff7 0xac042c3c + 0x0af1158f 0xb080446d 0x22561f86 0x3c449de0 + 0xbe156e20 0x7745c38a 0x19cadbff 0xcf505afc + 0xc2f94af9 0x720e8b00 0x1d740186 0xc411e6a7 + 0x16f99b0a 0x0b949e35 0xbc306cf9 0x67f417b4 + 0xce3e2635 0xd8f3a3fa 0x4b6fd9e6 0x63cfad21 + 0xaaf1456d 0x6c520541 0xca2dcac8 0xab62863d + 0x150a0ae3 0xa9e92a07 0x85e51d1f 0x327253e7 + 0xa0d5d35e 0x331b43ce 0x207a336a 0x3407a0b3 + 0x975a2429 0x95d42c04 0x9ff5ef17 0xfefb14c7 + 0xa3d8f8ac 0x6a112cd8 0x2d276889 0x5f2f6ef9 + 0x611636e3 0xecc81a74 0x4d482888 0xa46a478d + 0x7de65d9d 0x921e2a1f 0x48cca90f 0x64013e1f + 0x45aa6b87 0x5da46878 0x39a21b74 0xa72250de + 0xebbaa970 0xef8d31f9 0x59a9e1e2 0xd3403b97 + 0x1780ddca 0x731fa40f 0x6c2ba0fe 0x4f053afb + 0x2cf0e873 0xb6a733a8 0xc2a2e53e 0xd2241962 + 0xcb981a05 0x4af04278 0x053d4e34 0x63d071b8 + 0x731b063a 0xeed8b331 0x05221e90 0x6705a444 + 0x2c504d6d 0x231c42ec 0x8debbfaa 0x07829ed7 + 0x50ee8337 0x17ed0270 0x4a04c200 0xf5e650bd + 0x5bbe5f66 0x72d412d3 0x40253020 0xa949f29d + >; diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index a4321d3..7e37d4f 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -67,6 +67,12 @@ pos = <CONFIG_VGA_BIOS_ADDR>; }; #endif +#ifdef CONFIG_HAVE_VBT + intel-vbt { + filename = CONFIG_VBT_FILE; + pos = <CONFIG_VBT_ADDR>; + }; +#endif #ifdef CONFIG_HAVE_REFCODE intel-refcode { pos = <CONFIG_X86_REFCODE_ADDR>; diff --git a/arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h b/arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h new file mode 100644 index 0000000..4b8521d --- /dev/null +++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSP_CONFIGS_H__ +#define __FSP_CONFIGS_H__ + +#ifndef __ASSEMBLY__ +struct fsp_config_data { + struct fsp_cfg_common common; + struct upd_region fsp_upd; +}; + +struct fspinit_rtbuf { + struct common_buf common; /* FSP common runtime data structure */ +}; +#endif + +/* FSP user configuration settings */ + +#define MRC_INIT_TSEG_SIZE_1MB 1 +#define MRC_INIT_TSEG_SIZE_2MB 2 +#define MRC_INIT_TSEG_SIZE_4MB 4 +#define MRC_INIT_TSEG_SIZE_8MB 8 + +#define MRC_INIT_MMIO_SIZE_1024MB 0x400 +#define MRC_INIT_MMIO_SIZE_1536MB 0x600 +#define MRC_INIT_MMIO_SIZE_2048MB 0x800 + +#define IGD_DVMT50_PRE_ALLOC_32MB 0x01 +#define IGD_DVMT50_PRE_ALLOC_64MB 0x02 +#define IGD_DVMT50_PRE_ALLOC_96MB 0x03 +#define IGD_DVMT50_PRE_ALLOC_128MB 0x04 +#define IGD_DVMT50_PRE_ALLOC_160MB 0x05 +#define IGD_DVMT50_PRE_ALLOC_192MB 0x06 +#define IGD_DVMT50_PRE_ALLOC_224MB 0x07 +#define IGD_DVMT50_PRE_ALLOC_256MB 0x08 +#define IGD_DVMT50_PRE_ALLOC_288MB 0x09 +#define IGD_DVMT50_PRE_ALLOC_320MB 0x0a +#define IGD_DVMT50_PRE_ALLOC_352MB 0x0b +#define IGD_DVMT50_PRE_ALLOC_384MB 0x0c +#define IGD_DVMT50_PRE_ALLOC_416MB 0x0d +#define IGD_DVMT50_PRE_ALLOC_448MB 0x0e +#define IGD_DVMT50_PRE_ALLOC_480MB 0x0f +#define IGD_DVMT50_PRE_ALLOC_512MB 0x10 + +#define APERTURE_SIZE_128MB 1 +#define APERTURE_SIZE_256MB 2 +#define APERTURE_SIZE_512MB 3 + +#define GTT_SIZE_1MB 1 +#define GTT_SIZE_2MB 2 + +#define DRAM_TYPE_DDR3 0 +#define DRAM_TYPE_LPDDR3 1 + +#define SDCARD_MODE_DISABLED 0 +#define SDCARD_MODE_PCI 1 +#define SDCARD_MODE_ACPI 2 + +#define LPE_MODE_DISABLED 0 +#define LPE_MODE_PCI 1 +#define LPE_MODE_ACPI 2 + +#define CHV_SVID_CONFIG_0 0 +#define CHV_SVID_CONFIG_1 1 +#define CHV_SVID_CONFIG_2 2 +#define CHV_SVID_CONFIG_3 3 + +#define EMMC_MODE_DISABLED 0 +#define EMMC_MODE_PCI 1 +#define EMMC_MODE_ACPI 2 + +#define SATA_SPEED_GEN1 1 +#define SATA_SPEED_GEN2 2 +#define SATA_SPEED_GEN3 3 + +#define ISP_PCI_DEV_CONFIG_1 1 +#define ISP_PCI_DEV_CONFIG_2 2 +#define ISP_PCI_DEV_CONFIG_3 3 + +#define PNP_SETTING_DISABLED 0 +#define PNP_SETTING_POWER 1 +#define PNP_SETTING_PERF 2 +#define PNP_SETTING_POWER_AND_PERF 3 + +#endif /* __FSP_CONFIGS_H__ */ diff --git a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h new file mode 100644 index 0000000..ecb01fa --- /dev/null +++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h @@ -0,0 +1,172 @@ +/* + * Copyright (C) 2015, Intel Corporation + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: Intel + */ + +#ifndef __FSP_VPD_H__ +#define __FSP_VPD_H__ + +struct __packed memory_upd { + u64 signature; /* Offset 0x0020 */ + u8 revision; /* Offset 0x0028 */ + u8 unused2[7]; /* Offset 0x0029 */ + u16 mrc_init_tseg_size; /* Offset 0x0030 */ + u16 mrc_init_mmio_size; /* Offset 0x0032 */ + u8 mrc_init_spd_addr1; /* Offset 0x0034 */ + u8 mrc_init_spd_addr2; /* Offset 0x0035 */ + u8 mem_ch0_config; /* Offset 0x0036 */ + u8 mem_ch1_config; /* Offset 0x0037 */ + u32 memory_spd_ptr; /* Offset 0x0038 */ + u8 igd_dvmt50_pre_alloc; /* Offset 0x003c */ + u8 aperture_size; /* Offset 0x003d */ + u8 gtt_size; /* Offset 0x003e */ + u8 legacy_seg_decode; /* Offset 0x003f */ + u8 enable_dvfs; /* Offset 0x0040 */ + u8 memory_type; /* Offset 0x0041 */ + u8 enable_ca_mirror; /* Offset 0x0042 */ + u8 reserved[189]; /* Offset 0x0043 */ +}; + +struct __packed azalia_verb_table_header { + u32 vendor_device_id; + u16 sub_system_id; + u8 revision_id; + u8 front_panel_support; + u16 number_of_rear_jacks; + u16 number_of_front_jacks; +}; + +struct __packed azalia_verb_table { + struct azalia_verb_table_header header; + u32 *data; +}; + +struct __packed azalia_config { + u8 pme_enable:1; + u8 docking_supported:1; + u8 docking_attached:1; + u8 hdmi_codec_enable:1; + u8 azalia_v_ci_enable:1; + u8 reserved:3; + u8 verb_table_num; + struct azalia_verb_table *verb_table; + u16 reset_wait_timer_ms; +}; + +struct gpio_family { + u32 confg; + u32 confg_changes; + u32 misc; + u32 mmio_addr; + wchar_t *name; +}; + +struct gpio_pad { + u32 confg0; + u32 confg0_changes; + u32 confg1; + u32 confg1_changes; + u32 community; + u32 mmio_addr; + wchar_t *name; + u32 misc; +}; + +struct __packed silicon_upd { + u64 signature; /* Offset 0x0100 */ + u8 revision; /* Offset 0x0108 */ + u8 unused3[7]; /* Offset 0x0109 */ + u8 sdcard_mode; /* Offset 0x0110 */ + u8 enable_hsuart0; /* Offset 0x0111 */ + u8 enable_hsuart1; /* Offset 0x0112 */ + u8 enable_azalia; /* Offset 0x0113 */ + struct azalia_config *azalia_cfg_ptr; /* Offset 0x0114 */ + u8 enable_sata; /* Offset 0x0118 */ + u8 enable_xhci; /* Offset 0x0119 */ + u8 lpe_mode; /* Offset 0x011a */ + u8 enable_dma0; /* Offset 0x011b */ + u8 enable_dma1; /* Offset 0x011c */ + u8 enable_i2c0; /* Offset 0x011d */ + u8 enable_i2c1; /* Offset 0x011e */ + u8 enable_i2c2; /* Offset 0x011f */ + u8 enable_i2c3; /* Offset 0x0120 */ + u8 enable_i2c4; /* Offset 0x0121 */ + u8 enable_i2c5; /* Offset 0x0122 */ + u8 enable_i2c6; /* Offset 0x0123 */ + u32 graphics_config_ptr; /* Offset 0x0124 */ + struct gpio_family *gpio_familiy_ptr; /* Offset 0x0128 */ + struct gpio_pad *gpio_pad_ptr; /* Offset 0x012c */ + u8 disable_punit_pwr_config; /* Offset 0x0130 */ + u8 chv_svid_config; /* Offset 0x0131 */ + u8 disable_dptf; /* Offset 0x0132 */ + u8 emmc_mode; /* Offset 0x0133 */ + u8 usb3_clk_ssc; /* Offset 0x0134 */ + u8 disp_clk_ssc; /* Offset 0x0135 */ + u8 sata_clk_ssc; /* Offset 0x0136 */ + u8 usb2_port0_pe_txi_set; /* Offset 0x0137 */ + u8 usb2_port0_txi_set; /* Offset 0x0138 */ + u8 usb2_port0_tx_emphasis_en; /* Offset 0x0139 */ + u8 usb2_port0_tx_pe_half; /* Offset 0x013a */ + u8 usb2_port1_pe_txi_set; /* Offset 0x013b */ + u8 usb2_port1_txi_set; /* Offset 0x013c */ + u8 usb2_port1_tx_emphasis_en; /* Offset 0x013d */ + u8 usb2_port1_tx_pe_half; /* Offset 0x013e */ + u8 usb2_port2_pe_txi_set; /* Offset 0x013f */ + u8 usb2_port2_txi_set; /* Offset 0x0140 */ + u8 usb2_port2_tx_emphasis_en; /* Offset 0x0141 */ + u8 usb2_port2_tx_pe_half; /* Offset 0x0142 */ + u8 usb2_port3_pe_txi_set; /* Offset 0x0143 */ + u8 usb2_port3_txi_set; /* Offset 0x0144 */ + u8 usb2_port3_tx_emphasis_en; /* Offset 0x0145 */ + u8 usb2_port3_tx_pe_half; /* Offset 0x0146 */ + u8 usb2_port4_pe_txi_set; /* Offset 0x0147 */ + u8 usb2_port4_txi_set; /* Offset 0x0148 */ + u8 usb2_port4_tx_emphasis_en; /* Offset 0x0149 */ + u8 usb2_port4_tx_pe_half; /* Offset 0x014a */ + u8 usb3_lane0_ow2tap_gen2_deemph3p5; /* Offset 0x014b */ + u8 usb3_lane1_ow2tap_gen2_deemph3p5; /* Offset 0x014c */ + u8 usb3_lane2_ow2tap_gen2_deemph3p5; /* Offset 0x014d */ + u8 usb3_lane3_ow2tap_gen2_deemph3p5; /* Offset 0x014e */ + u8 sata_speed; /* Offset 0x014f */ + u8 usb_ssic_port; /* Offset 0x0150 */ + u8 usb_hsic_port; /* Offset 0x0151 */ + u8 pcie_rootport_speed; /* Offset 0x0152 */ + u8 enable_ssic; /* Offset 0x0153 */ + u32 logo_ptr; /* Offset 0x0154 */ + u32 logo_size; /* Offset 0x0158 */ + u8 rtc_lock; /* Offset 0x015c */ + u8 pmic_i2c_bus; /* Offset 0x015d */ + u8 enable_isp; /* Offset 0x015e */ + u8 isp_pci_dev_config; /* Offset 0x015f */ + u8 turbo_mode; /* Offset 0x0160 */ + u8 pnp_settings; /* Offset 0x0161 */ + u8 sd_detect_chk; /* Offset 0x0162 */ + u8 reserved[411]; /* Offset 0x0163 */ +}; + +#define MEMORY_UPD_ID 0x244450554d454d24 /* '$MEMUPD$' */ +#define SILICON_UPD_ID 0x244450555f495324 /* '$SI_UPD$' */ + +struct __packed upd_region { + u64 signature; /* Offset 0x0000 */ + u8 revision; /* Offset 0x0008 */ + u8 unused0[7]; /* Offset 0x0009 */ + u32 memory_upd_offset; /* Offset 0x0010 */ + u32 silicon_upd_offset; /* Offset 0x0014 */ + u64 unused1; /* Offset 0x0018 */ + struct memory_upd memory_upd; /* Offset 0x0020 */ + struct silicon_upd silicon_upd; /* Offset 0x0100 */ + u16 terminator; /* Offset 0x02fe */ +}; + +#define VPD_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */ + +struct __packed vpd_region { + u64 sign; /* Offset 0x0000 */ + u32 img_rev; /* Offset 0x0008 */ + u32 upd_offset; /* Offset 0x000c */ +}; + +#endif /* __FSP_VPD_H__ */ diff --git a/arch/x86/include/asm/arch-braswell/gpio.h b/arch/x86/include/asm/arch-braswell/gpio.h new file mode 100644 index 0000000..5f1252f --- /dev/null +++ b/arch/x86/include/asm/arch-braswell/gpio.h @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + * + * From coreboot src/soc/intel/braswell/include/soc/gpio.h + */ + +#ifndef _BRASWELL_GPIO_H_ +#define _BRASWELL_GPIO_H_ + +#include <asm/arch/iomap.h> + +enum mode_list { + M0, + M1, + M2, + M3, + M4, + M5, + M6, + M7, + M8, + M9, + M10, + M11, + M12, + M13, +}; + +enum int_select { + L0, + L1, + L2, + L3, + L4, + L5, + L6, + L7, + L8, + L9, + L10, + L11, + L12, + L13, + L14, + L15, +}; + +enum gpio_en { + NATIVE = 0xff, + GPIO = 0, /* Native, no need to set PAD_VALUE */ + GPO = 1, /* GPO, output only in PAD_VALUE */ + GPI = 2, /* GPI, input only in PAD_VALUE */ + HI_Z = 3, + NA_GPO = 0, +}; + +enum gpio_state { + LOW, + HIGH, +}; + +enum en_dis { + DISABLE, /* Disable */ + ENABLE, /* Enable */ +}; + +enum int_type { + INT_DIS, + TRIG_EDGE_LOW, + TRIG_EDGE_HIGH, + TRIG_EDGE_BOTH, + TRIG_LEVEL, +}; + +enum mask { + MASKABLE, + NON_MASKABLE, +}; + +enum glitch_cfg { + GLITCH_DISABLE, + EN_EDGE_DETECT, + EN_RX_DATA, + EN_EDGE_RX_DATA, +}; + +enum inv_rx_tx { + NO_INVERSION = 0, + INV_RX_ENABLE = 1, + INV_TX_ENABLE = 2, + INV_RX_TX_ENABLE = 3, + INV_RX_DATA = 4, + INV_TX_DATA = 8, +}; + +enum voltage { + VOLT_3_3, /* Working on 3.3 Volts */ + VOLT_1_8, /* Working on 1.8 Volts */ +}; + +enum hs_mode { + DISABLE_HS, /* Disable high speed mode */ + ENABLE_HS, /* Enable high speed mode */ +}; + +enum odt_up_dn { + PULL_UP, /* On Die Termination Up */ + PULL_DOWN, /* On Die Termination Down */ +}; + +enum odt_en { + DISABLE_OD, /* On Die Termination Disable */ + ENABLE_OD, /* On Die Termination Enable */ +}; + +enum pull_type { + P_NONE = 0, /* Pull None */ + P_20K_L = 1, /* Pull Down 20K */ + P_5K_L = 2, /* Pull Down 5K */ + P_1K_L = 4, /* Pull Down 1K */ + P_20K_H = 9, /* Pull Up 20K */ + P_5K_H = 10, /* Pull Up 5K */ + P_1K_H = 12 /* Pull Up 1K */ +}; + +enum bit { + ONE_BIT = 1, + TWO_BIT = 3, + THREE_BIT = 7, + FOUR_BIT = 15, + FIVE_BIT = 31, + SIX_BIT = 63, + SEVEN_BIT = 127, + EIGHT_BIT = 255 +}; + +enum gpe_config { + GPE, + SMI, + SCI, +}; + +enum community { + SOUTHWEST = 0x0000, + NORTH = 0x8000, + EAST = 0x10000, + SOUTHEAST = 0x18000, + VIRTUAL = 0x20000, +}; + +#define NA 0xff +#define TERMINATOR 0xffffffff + +#define GPIO_FAMILY_CONF(family_name, park_mode, hysctl, vp18_mode, hs_mode, \ + odt_up_dn, odt_en, curr_src_str, rcomp, family_no, community_offset) { \ + .confg = ((((park_mode) != NA) ? park_mode << 26 : 0) | \ + (((hysctl) != NA) ? hysctl << 24 : 0) | \ + (((vp18_mode) != NA) ? vp18_mode << 21 : 0) | \ + (((hs_mode) != NA) ? hs_mode << 19 : 0) | \ + (((odt_up_dn) != NA) ? odt_up_dn << 18 : 0) | \ + (((odt_en) != NA) ? odt_en << 17 : 0) | \ + (curr_src_str)), \ + .confg_changes = ((((park_mode) != NA) ? ONE_BIT << 26 : 0) | \ + (((hysctl) != NA) ? TWO_BIT << 24 : 0) | \ + (((vp18_mode) != NA) ? ONE_BIT << 21 : 0) | \ + (((hs_mode) != NA) ? ONE_BIT << 19 : 0) | \ + (((odt_up_dn) != NA) ? ONE_BIT << 18 : 0) | \ + (((odt_en) != NA) ? ONE_BIT << 17 : 0) | \ + (THREE_BIT)), \ + .misc = ((rcomp == ENABLE) ? 1 : 0) , \ + .mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \ + ((family_no != NA) ? (IO_BASE_ADDRESS + community_offset +\ + (0x80 * family_no) + 0x1080) : 0) , \ + .name = 0 \ +} + +#define GPIO_PAD_CONF(pad_name, mode_select, mode, gpio_config, gpio_state, \ + gpio_light_mode, int_type, int_sel, term, open_drain, current_source,\ + int_mask, glitch, inv_rx_tx, wake_mask, wake_mask_bit, gpe, \ + mmio_offset, community_offset) { \ + .confg0 = ((((int_sel) != NA) ? (int_sel << 28) : 0) | \ + (((glitch) != NA) ? (glitch << 26) : 0) | \ + (((term) != NA) ? (term << 20) : 0) | \ + (((mode_select) == GPIO) ? ((mode << 16) | (1 << 15)) : \ + ((mode << 16))) | \ + (((gpio_config) != NA) ? (gpio_config << 8) : 0) | \ + (((gpio_light_mode) != NA) ? (gpio_light_mode << 7) : 0) | \ + (((gpio_state) == HIGH) ? 2 : 0)), \ + .confg0_changes = ((((int_sel) != NA) ? (FOUR_BIT << 28) : 0) | \ + (((glitch) != NA) ? (TWO_BIT << 26) : 0) | \ + (((term) != NA) ? (FOUR_BIT << 20) : 0) | \ + (FIVE_BIT << 15) | \ + (((gpio_config) != NA) ? (THREE_BIT << 8) : 0) | \ + (((gpio_light_mode) != NA) ? (ONE_BIT << 7) : 0) | \ + (((gpio_state) != NA) ? ONE_BIT << 1 : 0)), \ + .confg1 = ((((current_source) != NA) ? (current_source << 27) : 0) | \ + (((inv_rx_tx) != NA) ? inv_rx_tx << 4 : 0) | \ + (((open_drain) != NA) ? open_drain << 3 : 0) | \ + (((int_type) != NA) ? int_type : 0)), \ + .confg1_changes = ((((current_source) != NA) ? (ONE_BIT << 27) : 0) | \ + (((inv_rx_tx) != NA) ? FOUR_BIT << 4 : 0) | \ + (((open_drain) != NA) ? ONE_BIT << 3 : 0) | \ + (((int_type) != NA) ? THREE_BIT : 0)), \ + .community = community_offset, \ + .mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \ + ((mmio_offset != NA) ? (IO_BASE_ADDRESS + \ + community_offset + mmio_offset) : 0), \ + .name = 0, \ + .misc = ((((gpe) != NA) ? (gpe << 0) : 0) | \ + (((wake_mask) != NA) ? (wake_mask << 2) : 0) | \ + (((int_mask) != NA) ? (int_mask << 3) : 0)) | \ + (((wake_mask_bit) != NA) ? (wake_mask_bit << 4) : (NA << 4)) \ +} + +#endif /* _BRASWELL_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-braswell/iomap.h b/arch/x86/include/asm/arch-braswell/iomap.h new file mode 100644 index 0000000..7df2dc5 --- /dev/null +++ b/arch/x86/include/asm/arch-braswell/iomap.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BRASWELL_IOMAP_H_ +#define _BRASWELL_IOMAP_H_ + +/* Memory Mapped IO bases */ + +/* Power Management Controller */ +#define PMC_BASE_ADDRESS 0xfed03000 +#define PMC_BASE_SIZE 0x400 + +/* Power Management Unit */ +#define PUNIT_BASE_ADDRESS 0xfed05000 +#define PUNIT_BASE_SIZE 0x800 + +/* Intel Legacy Block */ +#define ILB_BASE_ADDRESS 0xfed08000 +#define ILB_BASE_SIZE 0x400 + +/* SPI Bus */ +#define SPI_BASE_ADDRESS 0xfed01000 +#define SPI_BASE_SIZE 0x400 + +/* Root Complex Base Address */ +#define RCBA_BASE_ADDRESS 0xfed1c000 +#define RCBA_BASE_SIZE 0x400 + +/* IO Memory */ +#define IO_BASE_ADDRESS 0xfed80000 +#define IO_BASE_SIZE 0x4000 + +/* MODPHY */ +#define MPHY_BASE_ADDRESS 0xfef00000 +#define MPHY_BASE_SIZE 0x100000 + +/* IO Port bases */ + +#define ACPI_BASE_ADDRESS 0x400 +#define ACPI_BASE_SIZE 0x80 + +#define GPIO_BASE_ADDRESS 0x500 +#define GPIO_BASE_SIZE 0x100 + +#define SMBUS_BASE_ADDRESS 0xefa0 + +#endif /* _BRASWELL_IOMAP_H_ */ diff --git a/arch/x86/include/asm/fsp/fsp_api.h b/arch/x86/include/asm/fsp/fsp_api.h index afafb30..43f0cdb 100644 --- a/arch/x86/include/asm/fsp/fsp_api.h +++ b/arch/x86/include/asm/fsp/fsp_api.h @@ -43,7 +43,8 @@ struct common_buf { u32 stack_top; u32 boot_mode; /* Current system boot mode */ void *upd_data; /* User platform configuraiton data region */ - u32 reserved[7]; /* Reserved */ + u32 tolum_size; /* Top of low usable memory size (FSP 1.1) */ + u32 reserved[6]; /* Reserved */ }; enum fsp_phase { diff --git a/arch/x86/include/asm/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h index 7c22bcd..244f86e 100644 --- a/arch/x86/include/asm/fsp/fsp_hob.h +++ b/arch/x86/include/asm/fsp/fsp_hob.h @@ -127,6 +127,26 @@ struct hob_guid { /* GUID specific data goes here */ }; +enum pixel_format { + pixel_rgbx_8bpc, /* RGB 8 bit per color */ + pixel_bgrx_8bpc, /* BGR 8 bit per color */ + pixel_bitmask, +}; + +struct __packed hob_graphics_info { + phys_addr_t fb_base; /* framebuffer base address */ + u32 fb_size; /* framebuffer size */ + u32 version; + u32 width; + u32 height; + enum pixel_format pixel_format; + u32 red_mask; + u32 green_mask; + u32 blue_mask; + u32 reserved_mask; + u32 pixels_per_scanline; +}; + /** * get_next_hob() - return a pointer to the next HOB in the HOB list * @@ -242,4 +262,18 @@ static inline u16 get_guid_hob_data_size(const struct hob_header *hdr) { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \ } +/* The following GUIDs are newly introduced in FSP spec 1.1 */ + +#define FSP_HOB_RESOURCE_OWNER_BOOTLOADER_TOLUM_GUID \ + { \ + 0x73ff4f56, 0xaa8e, 0x4451, \ + { 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44 } \ + } + +#define FSP_GRAPHICS_INFO_HOB_GUID \ + { \ + 0x39f62cce, 0x6825, 0x4669, \ + { 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 } \ + } + #endif diff --git a/arch/x86/include/asm/fsp/fsp_infoheader.h b/arch/x86/include/asm/fsp/fsp_infoheader.h index 4a4d627..60ce61d 100644 --- a/arch/x86/include/asm/fsp/fsp_infoheader.h +++ b/arch/x86/include/asm/fsp/fsp_infoheader.h @@ -26,7 +26,14 @@ struct __packed fsp_header { u32 fsp_tempram_init; /* tempram_init offset */ u32 fsp_init; /* fsp_init offset */ u32 fsp_notify; /* fsp_notify offset */ - u32 reserved2; + u32 fsp_mem_init; /* fsp_mem_init offset */ + u32 fsp_tempram_exit; /* fsp_tempram_exit offset */ + u32 fsp_silicon_init; /* fsp_silicon_init offset */ }; +#define FSP_HEADER_REVISION_1 1 +#define FSP_HEADER_REVISION_2 2 + +#define FSP_ATTR_GRAPHICS_SUPPORT (1 << 0) + #endif diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 61d811f..97a50b0 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -191,6 +191,18 @@ void *fsp_get_nvs_data(const void *hob_list, u32 *len); void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len); /** + * This function retrieves graphics information. + * + * @hob_list: A HOB list pointer. + * @len: A pointer to the graphics info HOB length. + * If the HOB is located, the length will be updated. + * + * @retval NULL: Failed to find the graphics info HOB. + * @retval others: A pointer to struct hob_graphics_info. + */ +void *fsp_get_graphics_info(const void *hob_list, u32 *len); + +/** * This function overrides the default configurations of FSP. * * @config: A pointer to the FSP configuration data structure diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 93a80fe..fcb6853 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -77,6 +77,7 @@ struct arch_global_data { uint8_t x86_mask; uint32_t x86_device; uint64_t tsc_base; /* Initial value returned by rdtsc() */ + unsigned long clock_rate; /* Clock rate of timer in Hz */ void *new_fdt; /* Relocated FDT */ uint32_t bist; /* Built-in self test value */ enum pei_boot_mode_t pei_boot_mode; diff --git a/arch/x86/lib/fsp/Makefile b/arch/x86/lib/fsp/Makefile index 3ea4880..afe83dd3 100644 --- a/arch/x86/lib/fsp/Makefile +++ b/arch/x86/lib/fsp/Makefile @@ -8,4 +8,5 @@ obj-y += cmd_fsp.o obj-y += fsp_car.o obj-y += fsp_common.o obj-y += fsp_dram.o +obj-$(CONFIG_VIDEO_FSP) += fsp_graphics.o obj-y += fsp_support.o diff --git a/arch/x86/lib/fsp/cmd_fsp.c b/arch/x86/lib/fsp/cmd_fsp.c index 2554663..2a99cfe 100644 --- a/arch/x86/lib/fsp/cmd_fsp.c +++ b/arch/x86/lib/fsp/cmd_fsp.c @@ -38,17 +38,37 @@ static int do_hdr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) for (i = 0; i < sizeof(hdr->sign); i++) printf("%c", *sign++); printf(", size %d, rev %d\n", hdr->hdr_len, hdr->hdr_rev); - printf("Image : rev %d.%d, id ", - (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff); + printf("Image : rev "); + if (hdr->hdr_rev == FSP_HEADER_REVISION_1) { + printf("%d.%d", + (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff); + } else { + printf("%d.%d.%d.%d", + (hdr->img_rev >> 24) & 0xff, (hdr->img_rev >> 16) & 0xff, + (hdr->img_rev >> 8) & 0xff, hdr->img_rev & 0xff); + } + printf(", id "); for (i = 0; i < ARRAY_SIZE(hdr->img_id); i++) printf("%c", hdr->img_id[i]); printf(", addr 0x%08x, size %d\n", img_addr, hdr->img_size); + if (hdr->hdr_rev == FSP_HEADER_REVISION_2) { + printf("GFX :%ssupported\n", + hdr->img_attr & FSP_ATTR_GRAPHICS_SUPPORT ? " " : " un"); + } printf("VPD : addr 0x%08x, size %d\n", hdr->cfg_region_off + img_addr, hdr->cfg_region_size); printf("\nNumber of APIs Supported : %d\n", hdr->api_num); printf("\tTempRamInit : 0x%08x\n", hdr->fsp_tempram_init + img_addr); printf("\tFspInit : 0x%08x\n", hdr->fsp_init + img_addr); printf("\tFspNotify : 0x%08x\n", hdr->fsp_notify + img_addr); + if (hdr->hdr_rev == FSP_HEADER_REVISION_2) { + printf("\tMemoryInit : 0x%08x\n", + hdr->fsp_mem_init + img_addr); + printf("\tTempRamExit : 0x%08x\n", + hdr->fsp_tempram_exit + img_addr); + printf("\tSiliconInit : 0x%08x\n", + hdr->fsp_silicon_init + img_addr); + } return 0; } diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c new file mode 100644 index 0000000..a19b067 --- /dev/null +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <vbe.h> +#include <video.h> +#include <asm/fsp/fsp_support.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct pixel { + u8 pos; + u8 size; +}; + +static const struct fsp_framebuffer { + struct pixel red; + struct pixel green; + struct pixel blue; + struct pixel rsvd; +} fsp_framebuffer_format_map[] = { + [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} }, + [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, +}; + +static int save_vesa_mode(struct vesa_mode_info *vesa) +{ + const struct hob_graphics_info *ginfo; + const struct fsp_framebuffer *fbinfo; + + ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL); + + /* + * If there is no graphics info structure, bail out and keep + * running on the serial console. + */ + if (!ginfo) { + debug("FSP graphics hand-off block not found\n"); + return -ENXIO; + } + + vesa->x_resolution = ginfo->width; + vesa->y_resolution = ginfo->height; + vesa->bits_per_pixel = 32; + vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4; + vesa->phys_base_ptr = ginfo->fb_base; + + if (ginfo->pixel_format >= pixel_bitmask) { + debug("FSP set unknown framebuffer format: %d\n", + ginfo->pixel_format); + return -EINVAL; + } + fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format]; + vesa->red_mask_size = fbinfo->red.size; + vesa->red_mask_pos = fbinfo->red.pos; + vesa->green_mask_size = fbinfo->green.size; + vesa->green_mask_pos = fbinfo->green.pos; + vesa->blue_mask_size = fbinfo->blue.size; + vesa->blue_mask_pos = fbinfo->blue.pos; + vesa->reserved_mask_size = fbinfo->rsvd.size; + vesa->reserved_mask_pos = fbinfo->rsvd.pos; + + return 0; +} + +static int fsp_video_probe(struct udevice *dev) +{ + struct video_uc_platdata *plat = dev_get_uclass_platdata(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct vesa_mode_info *vesa = &mode_info.vesa; + int ret; + + printf("Video: "); + + /* Initialize vesa_mode_info structure */ + ret = save_vesa_mode(vesa); + if (ret) + goto err; + + /* + * The framebuffer base address in the FSP graphics info HOB reflects + * the value assigned by the FSP. After PCI enumeration the framebuffer + * base address may be relocated. Let's get the updated one from device. + * + * For IGD, it seems to be always on BAR2. + */ + vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2); + + ret = vbe_setup_video_priv(vesa, uc_priv, plat); + if (ret) + goto err; + + printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize, + vesa->bits_per_pixel); + + return 0; + +err: + printf("No video mode configured in FSP!\n"); + return ret; +} + +static const struct udevice_id fsp_video_ids[] = { + { .compatible = "fsp-fb" }, + { } +}; + +U_BOOT_DRIVER(fsp_video) = { + .name = "fsp_video", + .id = UCLASS_VIDEO, + .of_match = fsp_video_ids, + .probe = fsp_video_probe, +}; + +static struct pci_device_id fsp_video_supported[] = { + { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) }, + { }, +}; + +U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported); diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index ab8340c..e0c49be 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -425,3 +425,10 @@ void *fsp_get_bootloader_tmp_mem(const void *hob_list, u32 *len) return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid); } + +void *fsp_get_graphics_info(const void *hob_list, u32 *len) +{ + const struct efi_guid guid = FSP_GRAPHICS_INFO_HOB_GUID; + + return fsp_get_guid_hob_data(hob_list, len, (struct efi_guid *)&guid); +} |