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-rw-r--r--board/amcc/acadia/Makefile51
-rw-r--r--board/amcc/acadia/acadia.c103
-rw-r--r--board/amcc/acadia/config.mk30
-rw-r--r--board/amcc/acadia/cpr.c195
-rw-r--r--board/amcc/acadia/memory.c103
-rw-r--r--board/amcc/acadia/u-boot.lds137
-rw-r--r--board/amcc/bamboo/bamboo.c82
-rw-r--r--board/amcc/bamboo/bamboo.h10
-rw-r--r--board/amcc/bamboo/u-boot.lds14
-rw-r--r--board/amcc/ebony/init.S77
-rw-r--r--board/amcc/katmai/cmd_katmai.c105
-rw-r--r--board/amcc/katmai/init.S12
-rw-r--r--board/amcc/katmai/katmai.c1
-rw-r--r--board/amcc/luan/init.S170
-rw-r--r--board/amcc/luan/luan.c99
-rw-r--r--board/amcc/luan/u-boot.lds13
-rw-r--r--board/amcc/ocotea/init.S82
-rw-r--r--board/amcc/sequoia/sdram.c29
-rw-r--r--board/amcc/sequoia/sequoia.c8
-rw-r--r--board/amcc/yucca/init.S83
-rw-r--r--board/amcc/yucca/yucca.c316
21 files changed, 810 insertions, 910 deletions
diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile
new file mode 100644
index 0000000..abcbf3e
--- /dev/null
+++ b/board/amcc/acadia/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS = $(BOARD).o cpr.o memory.o
+SOBJS =
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
new file mode 100644
index 0000000..baf598c
--- /dev/null
+++ b/board/amcc/acadia/acadia.c
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+
+extern void board_pll_init_f(void);
+
+static void acadia_gpio_init(void)
+{
+ /*
+ * GPIO0 setup (select GPIO or alternate function)
+ */
+ out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
+ out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
+ out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
+ out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
+ out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
+ out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
+ out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
+
+ /*
+ * Ultra (405EZ) was nice enough to add another GPIO controller
+ */
+ out32(GPIO1_OSRH, CFG_GPIO1_OSRH); /* output select */
+ out32(GPIO1_OSRL, CFG_GPIO1_OSRL);
+ out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H); /* input select */
+ out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L);
+ out32(GPIO1_TSRH, CFG_GPIO1_TSRH); /* three-state select */
+ out32(GPIO1_TSRL, CFG_GPIO1_TSRL);
+ out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */
+}
+
+int board_early_init_f(void)
+{
+ unsigned int reg;
+
+ /* don't reinit PLL when booting via I2C bootstrap option */
+ mfsdr(SDR_PINSTP, reg);
+ if (reg != 0xf0000000)
+ board_pll_init_f();
+
+ acadia_gpio_init();
+
+ /* USB Host core needs this bit set */
+ mfsdr(sdrultra1, reg);
+ mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE);
+
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000010);
+ mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */
+ mtdcr(uictr, 0x00000010); /* set int trigger levels */
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+
+ return 0;
+}
+
+int misc_init_f(void)
+{
+ /* Set EPLD to take PHY out of reset */
+ out8(CFG_CPLD_BASE + 0x05, 0x00);
+ udelay(100000);
+
+ return 0;
+}
+
+/*
+ * Check Board Identity:
+ */
+int checkboard(void)
+{
+ char *s = getenv("serial#");
+
+ printf("Board: Acadia - AMCC PPC405EZ Evaluation Board");
+ if (s != NULL) {
+ puts(", serial# ");
+ puts(s);
+ }
+ putc('\n');
+
+ return (0);
+}
diff --git a/board/amcc/acadia/config.mk b/board/amcc/acadia/config.mk
new file mode 100644
index 0000000..c8566ec
--- /dev/null
+++ b/board/amcc/acadia/config.mk
@@ -0,0 +1,30 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xFFFC0000
+endif
+
+ifeq ($(debug),1)
+PLATFORM_CPPFLAGS += -DDEBUG
+endif
diff --git a/board/amcc/acadia/cpr.c b/board/amcc/acadia/cpr.c
new file mode 100644
index 0000000..9dcce35
--- /dev/null
+++ b/board/amcc/acadia/cpr.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <ppc405.h>
+
+/* test-only: move into cpu directory!!! */
+
+#if defined(PLLMR0_200_133_66)
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------------------
+ * | CLK | FREQ (MHz) | DIV RATIO |
+ * ----------------------------------
+ * | CPU | 200.0 | 4 (0x02)|
+ * | PLB | 133.3 | 6 (0x06)|
+ * | OPB | 66.6 | 12 (0x0C)|
+ * | EBC | 66.6 | 12 (0x0C)|
+ * | SPI | 66.6 | 12 (0x0C)|
+ * | UART0 | 10.0 | 40 (0x28)|
+ * | UART1 | 10.0 | 40 (0x28)|
+ * | DAC | 2.0 | 200 (0xC8)|
+ * | ADC | 2.0 | 200 (0xC8)|
+ * | PWM | 100.0 | 4 (0x04)|
+ * | EMAC | 25.0 | 16 (0x10)|
+ * -----------------------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(cprpllc, 0x0000033c);
+ mtcpr(cprplld, 0x0c010200);
+ mtcpr(cprprimad, 0x04060c0c);
+ mtcpr(cprperd0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(cprclkupd, 0x40000000);
+}
+
+#elif defined(PLLMR0_266_160_80)
+
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------------------
+ * | CLK | FREQ (MHz) | DIV RATIO |
+ * ----------------------------------
+ * | CPU | 266.64 | 3 |
+ * | PLB | 159.98 | 5 (0x05)|
+ * | OPB | 79.99 | 10 (0x0A)|
+ * | EBC | 79.99 | 10 (0x0A)|
+ * | SPI | 79.99 | 10 (0x0A)|
+ * | UART0 | 28.57 | 7 (0x07)|
+ * | UART1 | 28.57 | 7 (0x07)|
+ * | DAC | 28.57 | 7 (0xA7)|
+ * | ADC | 4 | 50 (0x32)|
+ * | PWM | 28.57 | 7 (0x07)|
+ * | EMAC | 4 | 50 (0x32)|
+ * -----------------------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(cprpllc, 0x20000238);
+ mtcpr(cprplld, 0x03010400);
+ mtcpr(cprprimad, 0x03050a0a);
+ mtcpr(cprperc0, 0x00000000);
+ mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(cprperd1, 0x07323200);
+ mtcpr(cprclkupd, 0x40000000);
+}
+
+#elif defined(PLLMR0_333_166_83)
+
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------------------
+ * | CLK | FREQ (MHz) | DIV RATIO |
+ * ----------------------------------
+ * | CPU | 333.33 | 2 |
+ * | PLB | 166.66 | 4 (0x04)|
+ * | OPB | 83.33 | 8 (0x08)|
+ * | EBC | 83.33 | 8 (0x08)|
+ * | SPI | 83.33 | 8 (0x08)|
+ * | UART0 | 16.66 | 5 (0x05)|
+ * | UART1 | 16.66 | 5 (0x05)|
+ * | DAC | ???? | 166 (0xA6)|
+ * | ADC | ???? | 166 (0xA6)|
+ * | PWM | 41.66 | 3 (0x03)|
+ * | EMAC | ???? | 3 (0x03)|
+ * -----------------------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(cprpllc, 0x0000033C);
+ mtcpr(cprplld, 0x0a010000);
+ mtcpr(cprprimad, 0x02040808);
+ mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(cprperd1, 0xA6A60300);
+ mtcpr(cprclkupd, 0x40000000);
+}
+
+#elif defined(PLLMR0_100_100_12)
+
+void board_pll_init_f(void)
+{
+ /*
+ * set PLL clocks based on input sysclk is 33M
+ *
+ * ----------------------
+ * | CLK | FREQ (MHz) |
+ * ----------------------
+ * | CPU | 100.00 |
+ * | PLB | 100.00 |
+ * | OPB | 12.00 |
+ * | EBC | 49.00 |
+ * ----------------------
+ */
+
+ /* Initialize PLL */
+ mtcpr(cprpllc, 0x000003BC);
+ mtcpr(cprplld, 0x06060600);
+ mtcpr(cprprimad, 0x02020004);
+ mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */
+ mtcpr(cprperd1, 0xC8C81600);
+ mtcpr(cprclkupd, 0x40000000);
+}
+#endif /* CPU_<speed>_405EZ */
+
+#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL)
+/*
+ * Get timebase clock frequency
+ */
+unsigned long get_tbclk(void)
+{
+ unsigned long cpr_plld;
+ unsigned long cpr_primad;
+ unsigned long primad_cpudv;
+ unsigned long pllFbkDiv;
+ unsigned long freqProcessor;
+
+ /*
+ * Read PLL Mode registers
+ */
+ mfcpr(cprplld, cpr_plld);
+
+ /*
+ * Read CPR_PRIMAD register
+ */
+ mfcpr(cprprimad, cpr_primad);
+
+ /*
+ * Determine CPU clock frequency
+ */
+ primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24);
+ if (primad_cpudv == 0)
+ primad_cpudv = 16;
+
+ /*
+ * Determine FBK_DIV.
+ */
+ pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24);
+ if (pllFbkDiv == 0)
+ pllFbkDiv = 256;
+
+ freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv;
+
+ return (freqProcessor);
+}
+#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
new file mode 100644
index 0000000..5375d36
--- /dev/null
+++ b/board/amcc/acadia/memory.c
@@ -0,0 +1,103 @@
+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* define DEBUG for debugging output (obviously ;-)) */
+#if 0
+#define DEBUG
+#endif
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+/*
+ * sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
+ */
+void sdram_init(void)
+{
+ return;
+}
+
+static void cram_bcr_write(u32 wr_val)
+{
+ wr_val <<= 2;
+
+ /* set CRAM_CRE to 1 */
+ gpio_write_bit(CFG_GPIO_CRAM_CRE, 1);
+
+ /* Write BCR to CRAM on CS1 */
+ out32(wr_val + 0x00200000, 0);
+ debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
+
+ /* Write BCR to CRAM on CS2 */
+ out32(wr_val + 0x02200000, 0);
+ debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
+
+ sync();
+ eieio();
+
+ /* set CRAM_CRE back to 0 (normal operation) */
+ gpio_write_bit(CFG_GPIO_CRAM_CRE, 0);
+
+ return;
+}
+
+long int initdram(int board_type)
+{
+ u32 val;
+
+ /* 1. EBC need to program READY, CLK, ADV for ASync mode */
+ gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+ gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+ gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+ gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
+
+ /* 2. EBC in Async mode */
+ mtebc(pb1ap, 0x078F1EC0);
+ mtebc(pb2ap, 0x078F1EC0);
+ mtebc(pb1cr, 0x000BC000);
+ mtebc(pb2cr, 0x020BC000);
+
+ /* 3. Set CRAM in Sync mode */
+ cram_bcr_write(0x7012); /* CRAM burst setting */
+
+ /* 4. EBC in Sync mode */
+ mtebc(pb1ap, 0x9C0201C0);
+ mtebc(pb2ap, 0x9C0201C0);
+
+ /* Set GPIO pins back to alternate function */
+ gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
+ gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
+
+ /* Config EBC to use RDY */
+ mfsdr(sdrultra0, val);
+ mtsdr(sdrultra0, val | 0x04000000);
+
+ return (CFG_MBYTES_RAM << 20);
+}
+
+int testdram(void)
+{
+ return (0);
+}
diff --git a/board/amcc/acadia/u-boot.lds b/board/amcc/acadia/u-boot.lds
new file mode 100644
index 0000000..b08c999
--- /dev/null
+++ b/board/amcc/acadia/u-boot.lds
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ .resetvec 0xFFFFFFFC :
+ {
+ *(.resetvec)
+ } = 0xffff
+
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/ppc4xx/start.o (.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ *(.rodata.str1.4)
+ *(.eh_frame)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index c93ba6e..6260b01 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -23,6 +23,7 @@
#include <common.h>
#include <asm/processor.h>
+#include <asm/gpio.h>
#include <spd_sdram.h>
#include <ppc440.h>
#include "bamboo.h"
@@ -276,87 +277,6 @@ int board_early_init_f(void)
return 0;
}
-#if (CONFIG_COMMANDS & CFG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
-
-/*----------------------------------------------------------------------------+
- | nand_reset.
- | Reset Nand flash
- | This routine will abort previous cmd
- +----------------------------------------------------------------------------*/
-int nand_reset(ulong addr)
-{
- int wait=0, stat=0;
-
- out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
- out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
-
- while ((stat != 0xc0) && (wait != 0xffff)) {
- stat = in8(addr + NAND_DATA_REG);
- wait++;
- }
-
- if (stat == 0xc0) {
- return 0;
- } else {
- printf("NAND Reset timeout.\n");
- return -1;
- }
-}
-
-void board_nand_set_device(int cs, ulong addr)
-{
- /* Set NandFlash Core Configuration Register */
- out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
-
- switch (cs) {
- case 1:
- /* -------
- * NAND0
- * -------
- * K9F1208U0A : 4 addr cyc, 1 col + 3 Row
- * Set NDF1CR - Enable External CS1 in NAND FLASH controller
- */
- out32(addr + NAND_CR1_REG, 0x80002222);
- break;
-
- case 2:
- /* -------
- * NAND1
- * -------
- * K9K2G0B : 5 addr cyc, 2 col + 3 Row
- * Set NDF2CR : Enable External CS2 in NAND FLASH controller
- */
- out32(addr + NAND_CR2_REG, 0xC0007777);
- break;
- }
-
- /* Perform Reset Command */
- if (nand_reset(addr) != 0)
- return;
-}
-
-void nand_init(void)
-{
- board_nand_set_device(1, CFG_NAND_ADDR);
-
- nand_probe(CFG_NAND_ADDR);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-
-#if 0 /* NAND1 not supported yet */
- board_nand_set_device(2, CFG_NAND2_ADDR);
-
- nand_probe(CFG_NAND2_ADDR);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-#endif
-}
-#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
-
int checkboard(void)
{
char *s = getenv("serial#");
diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h
index 1ce6366..4474862 100644
--- a/board/amcc/bamboo/bamboo.h
+++ b/board/amcc/bamboo/bamboo.h
@@ -264,19 +264,9 @@
#define TRUE 1
#define FALSE 0
-#define GPIO_GROUP_MAX 2
-#define GPIO_MAX 32
-#define GPIO_ALT1_SEL 0x40000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 0 */
-#define GPIO_ALT2_SEL 0x80000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 1 */
-#define GPIO_ALT3_SEL 0xC0000000 /* GPIO_OUT value put in GPIO_TSx for the GPIO nb 2 */
-#define GPIO_MASK 0xC0000000 /* GPIO_MASK */
-#define GPIO_IN_SEL 0x40000000 /* GPIO_IN value put in GPIO_ISx for the GPIO nb 0 */
- /* For the other GPIO number, you must shift */
-
#define GPIO0 0
#define GPIO1 1
-
/*#define MAX_SELECTION_NB CORE_NB */
#define MAX_CORE_SELECT_NB 22
diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds
index 176900e..f6d7183 100644
--- a/board/amcc/bamboo/u-boot.lds
+++ b/board/amcc/bamboo/u-boot.lds
@@ -68,19 +68,7 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
board/amcc/bamboo/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
+ board/amcc/bamboo/bamboo.o (.text)
*(.text)
*(.fixup)
diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S
index cc8f8b4..c86076e 100644
--- a/board/amcc/ebony/init.S
+++ b/board/amcc/ebony/init.S
@@ -22,53 +22,7 @@
#include <ppc_asm.tmpl>
#include <config.h>
-
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
+#include <asm-ppc/mmu.h>
/**************************************************************************
* TLB TABLE
@@ -81,16 +35,23 @@
*
*************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
+ .section .bootpg,"ax"
+ .globl tlbtab
tlbtab:
- tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
- tlbtab_end
+ tlbtab_start
+
+ tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
+ tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
+ tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
+ tlbtab_end
diff --git a/board/amcc/katmai/cmd_katmai.c b/board/amcc/katmai/cmd_katmai.c
index 684f6a5..439be4f 100644
--- a/board/amcc/katmai/cmd_katmai.c
+++ b/board/amcc/katmai/cmd_katmai.c
@@ -27,6 +27,9 @@
#include <i2c.h>
#include <asm/byteorder.h>
+#define CONFIG_STRESS /* enable 667 MHz CPU freq selection */
+#define DEBUG
+
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
uchar chip;
@@ -49,55 +52,28 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
else
chip = IIC0_ALT_BOOTPROM_ADDR;
- do {
- printf("enter sys clock frequency 33 or 66 Mhz or quit to abort\n");
- nbytes = readline (" ? ");
-
- if (strcmp(console_buffer, "quit") == 0)
- return 0;
-
- if ((strcmp(console_buffer, "33") != 0) &
- (strcmp(console_buffer, "66") != 0))
- nbytes=0;
-
- strcpy(sysClock, console_buffer);
-
- } while (nbytes == 0);
+ /* on Katmai SysClk is always 33MHz */
+ strcpy(sysClock, "33");
do {
- if (strcmp(sysClock, "66") == 0) {
- printf("enter cpu clock frequency 400, 533 Mhz or quit to abort\n");
- } else {
#ifdef CONFIG_STRESS
- printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n");
+ printf("enter cpu clock frequency 400, 500, 533, 667 Mhz or quit to abort\n");
#else
- printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n");
+ printf("enter cpu clock frequency 400, 500, 533 Mhz or quit to abort\n");
#endif
- }
nbytes = readline (" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
- if (strcmp(sysClock, "66") == 0) {
- if ((strcmp(console_buffer, "400") != 0) &
- (strcmp(console_buffer, "533") != 0)
-#ifdef CONFIG_STRESS
- & (strcmp(console_buffer, "667") != 0)
-#endif
- ) {
- nbytes = 0;
- }
- } else {
- if ((strcmp(console_buffer, "400") != 0) &
- (strcmp(console_buffer, "500") != 0) &
- (strcmp(console_buffer, "533") != 0)
+ if ((strcmp(console_buffer, "400") != 0) &&
+ (strcmp(console_buffer, "500") != 0) &&
+ (strcmp(console_buffer, "533") != 0)
#ifdef CONFIG_STRESS
- & (strcmp(console_buffer, "667") != 0)
+ && (strcmp(console_buffer, "667") != 0)
#endif
- ) {
- nbytes = 0;
- }
+ ) {
+ nbytes = 0;
}
strcpy(cpuClock, console_buffer);
@@ -124,13 +100,13 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0;
if (strcmp(cpuClock, "400") == 0) {
- if ((strcmp(console_buffer, "100") != 0) &
+ if ((strcmp(console_buffer, "100") != 0) &&
(strcmp(console_buffer, "133") != 0))
nbytes = 0;
}
#ifdef CONFIG_STRESS
if (strcmp(cpuClock, "667") == 0) {
- if ((strcmp(console_buffer, "133") != 0) &
+ if ((strcmp(console_buffer, "133") != 0) &&
(strcmp(console_buffer, "166") != 0))
nbytes = 0;
}
@@ -147,9 +123,9 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if (strcmp(console_buffer, "quit") == 0)
return 0;
- if ((strcmp(console_buffer, "33") != 0) &
- (strcmp(console_buffer, "66") != 0) &
- (strcmp(console_buffer, "100") != 0) &
+ if ((strcmp(console_buffer, "33") != 0) &&
+ (strcmp(console_buffer, "66") != 0) &&
+ (strcmp(console_buffer, "100") != 0) &&
(strcmp(console_buffer, "133") != 0)) {
nbytes = 0;
}
@@ -176,11 +152,11 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
} while (nbytes == 0);
if (strcmp(sysClock, "33") == 0) {
- if ((strcmp(cpuClock, "400") == 0) &
+ if ((strcmp(cpuClock, "400") == 0) &&
(strcmp(plbClock, "100") == 0))
data = 0x8678c206;
- if ((strcmp(cpuClock, "400") == 0) &
+ if ((strcmp(cpuClock, "400") == 0) &&
(strcmp(plbClock, "133") == 0))
data = 0x8678c2c6;
@@ -189,42 +165,16 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
if ((strcmp(cpuClock, "533") == 0))
data = 0x87790252;
-
#ifdef CONFIG_STRESS
- if ((strcmp(cpuClock, "667") == 0) &
+ if ((strcmp(cpuClock, "667") == 0) &&
(strcmp(plbClock, "133") == 0))
data = 0x87794256;
- if ((strcmp(cpuClock, "667") == 0) &
+ if ((strcmp(cpuClock, "667") == 0) &&
(strcmp(plbClock, "166") == 0))
data = 0x87794206;
-
-#endif
- }
- if (strcmp(sysClock, "66") == 0) {
- if ((strcmp(cpuClock, "400") == 0) &
- (strcmp(plbClock, "100") == 0))
- data = 0x84706206;
-
- if ((strcmp(cpuClock, "400") == 0) &
- (strcmp(plbClock, "133") == 0))
- data = 0x847062c6;
-
- if ((strcmp(cpuClock, "533") == 0))
- data = 0x85708206;
-
-#ifdef CONFIG_STRESS
- if ((strcmp(cpuClock, "667") == 0) &
- (strcmp(plbClock, "133") == 0))
- data = 0x8570a256;
-
- if ((strcmp(cpuClock, "667") == 0) &
- (strcmp(plbClock, "166") == 0))
- data = 0x8570a206;
-
#endif
}
-
#ifdef DEBUG
printf(" pin strap0 to write in i2c = %x\n", data);
#endif /* DEBUG */
@@ -233,19 +183,20 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
printf("Error writing strap0 in %s\n", argv[2]);
if (strcmp(pcixClock, "33") == 0)
- data = 0x00000701;
+ data = 0x000007E1;
if (strcmp(pcixClock, "66") == 0)
- data = 0x00000601;
+ data = 0x000006E1;
if (strcmp(pcixClock, "100") == 0)
- data = 0x00000501;
+ data = 0x000005E1;
if (strcmp(pcixClock, "133") == 0)
- data = 0x00000401;
+ data = 0x000004E1;
if (strcmp(plbClock, "166") == 0)
- data |= 0x05950000;
+/* data |= 0x05950000; */ /* this set's DDR2 clock == PLB clock */
+ data |= 0x05A50000; /* this set's DDR2 clock == 2 * PLB clock */
else
data |= 0x05A50000;
diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S
index f5900bc..5202ae6 100644
--- a/board/amcc/katmai/init.S
+++ b/board/amcc/katmai/init.S
@@ -46,6 +46,11 @@
.globl tlbtabA
tlbtabA:
tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
/*
@@ -81,6 +86,11 @@ tlbtabA:
.globl tlbtabB
tlbtabB:
tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
/*
@@ -93,7 +103,7 @@ tlbtabB:
tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
- tlbentry(CFG_ACE_BASE, SZ_1K, 0xE0000000, 4,AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_ACE_BASE, SZ_1K, CFG_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index fbf1a98..286bdc1 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -27,6 +27,7 @@
#include <asm/processor.h>
#include <i2c.h>
#include <asm-ppc/io.h>
+#include <asm-ppc/gpio.h>
#include "../cpu/ppc4xx/440spe_pcie.h"
diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S
index 7830ebd..d5ee117 100644
--- a/board/amcc/luan/init.S
+++ b/board/amcc/luan/init.S
@@ -1,73 +1,31 @@
/*
-*
-* See file CREDITS for list of people who contributed to this
-* project.
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation; either version 2 of
-* the License, or (at your option) any later version.
-*
-* This program is distributed in the hope that it will be useful,
-* but WITHOUT ANY WARRANTY; without even the implied warranty of
-* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*
-* You should have received a copy of the GNU General Public License
-* along with this program; if not, write to the Free Software
-* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-* MA 02111-1307 USA
-*/
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
#include <ppc_asm.tmpl>
#include <config.h>
-
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
+#include <asm-ppc/mmu.h>
/**************************************************************************
* TLB TABLE
@@ -80,53 +38,37 @@
*
*************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
+ .section .bootpg,"ax"
+ .globl tlbtab
tlbtab:
- tlbtab_start
-
-#if (CFG_LARGE_FLASH == 0xffc00000) /* if booting from large flash */
- /* large flash */
- tlbentry( 0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
- tlbentry( 0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
- tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
- tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
-
- tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
- tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I|SA_W )
-#else /* else booting from small flash */
- tlbentry( 0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
- tlbentry( 0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-
- tlbentry( 0xff800000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
- tlbentry( 0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
- tlbentry( 0xffa00000, SZ_1M, 0xffa00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
- tlbentry( 0xffb00000, SZ_1M, 0xffb00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-#endif
-
- tlbentry( CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I )
-
-#if (CFG_SRAM_BASE != 0) /* if SRAM up high and SDRAM at zero */
- tlbentry( 0x00000000, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-#elif (CFG_SMALL_FLASH == 0xff900000) /* else SRAM at 0 */
- tlbentry( 0x00000000, SZ_1M, 0xff800000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-#elif (CFG_SMALL_FLASH == 0xfff00000)
- tlbentry( 0x00000000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G/*|SA_I*/ )
-#else
- #error DONT KNOW SRAM LOCATION
-#endif
-
- /* internal ram (l2 cache) */
- tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I )
-
- /* peripherals at f0000000 */
- tlbentry( CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I )
-
- /* PCI */
-#if (CONFIG_COMMANDS & CFG_CMD_PCI)
- tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I )
-#endif
- tlbtab_end
+ tlbtab_start
+
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G)
+
+ tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+ tlbentry(CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ /* internal ram (l2 cache) */
+ tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I)
+
+ /* peripherals at f0000000 */
+ tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I)
+
+ /* PCI */
+ tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I)
+ tlbtab_end
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index 06a57f6..778aafc 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -106,105 +106,6 @@ int checkboard(void)
/*************************************************************************
- * long int fixed_sdram()
- *
- ************************************************************************/
-static long int fixed_sdram(void)
-{ /* DDR2 init from BDI2000 script */
- mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - zero DCEN bit */
- mtdcr( 0x11, 0x84000000 );
- mtdcr( 0x10, 0x00000020 ); /* MCIF0_MCOPT1 - no ECC, 64 bits, 4 banks, DDR2 */
- mtdcr( 0x11, 0x2D122000 );
- mtdcr( 0x10, 0x00000026 ); /* MCIF0_CODT - die termination on */
- mtdcr( 0x11, 0x00800026 );
- mtdcr( 0x10, 0x00000081 ); /* MCIF0_WRDTR - Write DQS Adv 90 + Fractional DQS Delay */
- mtdcr( 0x11, 0x82000800 );
- mtdcr( 0x10, 0x00000080 ); /* MCIF0_CLKTR - advance addr clock by 180 deg */
- mtdcr( 0x11, 0x80000000 );
- mtdcr( 0x10, 0x00000040 ); /* MCIF0_MB0CF - turn on CS0, N x 10 coll */
- mtdcr( 0x11, 0x00000201 );
- mtdcr( 0x10, 0x00000044 ); /* MCIF0_MB1CF - turn on CS0, N x 10 coll */
- mtdcr( 0x11, 0x00000201 );
- mtdcr( 0x10, 0x00000030 ); /* MCIF0_RTR - refresh every 7.8125uS */
- mtdcr( 0x11, 0x08200000 );
- mtdcr( 0x10, 0x00000085 ); /* MCIF0_SDTR1 - timing register 1 */
- mtdcr( 0x11, 0x80201000 );
- mtdcr( 0x10, 0x00000086 ); /* MCIF0_SDTR2 - timing register 2 */
- mtdcr( 0x11, 0x42103242 );
- mtdcr( 0x10, 0x00000087 ); /* MCIF0_SDTR3 - timing register 3 */
- mtdcr( 0x11, 0x0C100D14 );
- mtdcr( 0x10, 0x00000088 ); /* MCIF0_MMODE - CAS is 4 cycles */
- mtdcr( 0x11, 0x00000642 );
- mtdcr( 0x10, 0x00000089 ); /* MCIF0_MEMODE - diff DQS disabled */
- mtdcr( 0x11, 0x00000400 ); /* ODT term disabled */
-
- mtdcr( 0x10, 0x00000050 ); /* MCIF0_INITPLR0 - NOP */
- mtdcr( 0x11, 0x81b80000 );
- mtdcr( 0x10, 0x00000051 ); /* MCIF0_INITPLR1 - PRE */
- mtdcr( 0x11, 0x82100400 );
- mtdcr( 0x10, 0x00000052 ); /* MCIF0_INITPLR2 - EMR2 */
- mtdcr( 0x11, 0x80820000 );
- mtdcr( 0x10, 0x00000053 ); /* MCIF0_INITPLR3 - EMR3 */
- mtdcr( 0x11, 0x80830000 );
- mtdcr( 0x10, 0x00000054 ); /* MCIF0_INITPLR4 - EMR DLL ENABLE */
- mtdcr( 0x11, 0x80810000 );
- mtdcr( 0x10, 0x00000055 ); /* MCIF0_INITPLR5 - MR DLL RESET */
- mtdcr( 0x11, 0x80800542 );
- mtdcr( 0x10, 0x00000056 ); /* MCIF0_INITPLR6 - PRE */
- mtdcr( 0x11, 0x82100400 );
- mtdcr( 0x10, 0x00000057 ); /* MCIF0_INITPLR7 - refresh */
- mtdcr( 0x11, 0x99080000 );
- mtdcr( 0x10, 0x00000058 ); /* MCIF0_INITPLR8 */
- mtdcr( 0x11, 0x99080000 );
- mtdcr( 0x10, 0x00000059 ); /* MCIF0_INITPLR9 */
- mtdcr( 0x11, 0x99080000 );
- mtdcr( 0x10, 0x0000005A ); /* MCIF0_INITPLR10 */
- mtdcr( 0x11, 0x99080000 );
- mtdcr( 0x10, 0x0000005B ); /* MCIF0_INITPLR11 - MR */
- mtdcr( 0x11, 0x80800442 );
- mtdcr( 0x10, 0x0000005C ); /* MCIF0_INITPLR12 - EMR OCD Default */
- mtdcr( 0x11, 0x80810380 );
- mtdcr( 0x10, 0x0000005D ); /* MCIF0_INITPLR13 - EMR OCD exit */
- mtdcr( 0x11, 0x80810000 );
- udelay( 10*1000 );
-
- mtdcr( 0x10, 0x00000021 ); /* MCIF0_MCOPT2 - execute preloaded init */
- mtdcr( 0x11, 0x28000000 ); /* set DC_EN */
- udelay( 100*1000 );
-
- mtdcr( 0x40, 0x0000F800 ); /* MQ0_B0BAS: base addr 00000000 / 256MB */
- mtdcr( 0x41, 0x1000F800 ); /* MQ0_B1BAS: base addr 10000000 / 256MB */
-
- mtdcr( 0x10, 0x00000078 ); /* MCIF0_RDCC - auto set read stage */
- mtdcr( 0x11, 0x00000000 );
- mtdcr( 0x10, 0x00000070 ); /* MCIF0_RQDC - read DQS delay control */
- mtdcr( 0x11, 0x8000003A ); /* enabled, frac DQS delay */
- mtdcr( 0x10, 0x00000074 ); /* MCIF0_RFDC - two clock feedback delay */
- mtdcr( 0x11, 0x00000200 );
-
- return 512 << 20;
-}
-
-
-/*************************************************************************
- * long int initdram
- *
- ************************************************************************/
-long int initdram( int board_type )
-{
- long dram_size = 0;
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = spd_sdram (0);
-#else
- dram_size = fixed_sdram ();
-#endif
-
- return dram_size;
-}
-
-
-/*************************************************************************
* int testdram()
*
************************************************************************/
diff --git a/board/amcc/luan/u-boot.lds b/board/amcc/luan/u-boot.lds
index d122f49..72ce685 100644
--- a/board/amcc/luan/u-boot.lds
+++ b/board/amcc/luan/u-boot.lds
@@ -68,19 +68,6 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
board/amcc/luan/init.o (.text)
- cpu/ppc4xx/kgdb.o (.text)
- cpu/ppc4xx/traps.o (.text)
- cpu/ppc4xx/interrupts.o (.text)
- cpu/ppc4xx/serial.o (.text)
- cpu/ppc4xx/cpu_init.o (.text)
- cpu/ppc4xx/speed.o (.text)
- common/dlmalloc.o (.text)
- lib_generic/crc32.o (.text)
- lib_ppc/extable.o (.text)
- lib_generic/zlib.o (.text)
-
-/* . = env_offset;*/
-/* common/environment.o(.text)*/
*(.text)
*(.fixup)
diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S
index 7e0b132..d211c71 100644
--- a/board/amcc/ocotea/init.S
+++ b/board/amcc/ocotea/init.S
@@ -22,55 +22,7 @@
#include <ppc_asm.tmpl>
#include <config.h>
-
-/* General */
-#define TLB_VALID 0x00000200
-#define _256M 0x10000000
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_8M 0x00000060
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
+#include <asm-ppc/mmu.h>
/**************************************************************************
* TLB TABLE
@@ -83,19 +35,23 @@
*
*************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
+ .section .bootpg,"ax"
+ .globl tlbtab
tlbtab:
- tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
- tlbtab_end
+ tlbtab_start
+
+ tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
+ tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
+ tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
+ tlbtab_end
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index 77f1438..d045df1 100644
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -6,7 +6,7 @@
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
*
- * (C) Copyright 2006
+ * (C) Copyright 2006-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
@@ -371,6 +371,14 @@ void denali_core_search_data_eye(unsigned long memory_size)
}
#endif /* CONFIG_DDR_DATA_EYE */
+#if defined(CONFIG_NAND_SPL)
+/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
+ * for the 4k NAND boot image so define bus_frequency to 133MHz here
+ * which is save for the refresh counter setup.
+ */
+#define get_bus_freq(val) 133000000
+#endif
+
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
@@ -379,16 +387,18 @@ void denali_core_search_data_eye(unsigned long memory_size)
long int initdram (int board_type)
{
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+ ulong speed = get_bus_freq(0);
+
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_00, 0x0000190A);
mtsdram(DDR0_01, 0x01000000);
mtsdram(DDR0_03, 0x02030602);
- mtsdram(DDR0_04, 0x13030300);
- mtsdram(DDR0_05, 0x0202050E);
- mtsdram(DDR0_06, 0x0104C823);
+ mtsdram(DDR0_04, 0x0A020200);
+ mtsdram(DDR0_05, 0x02020308);
+ mtsdram(DDR0_06, 0x0102C812);
mtsdram(DDR0_07, 0x000D0100);
- mtsdram(DDR0_08, 0x02360001);
+ mtsdram(DDR0_08, 0x02430001);
mtsdram(DDR0_09, 0x00011D5F);
mtsdram(DDR0_10, 0x00000300);
mtsdram(DDR0_11, 0x0027C800);
@@ -402,13 +412,16 @@ long int initdram (int board_type)
mtsdram(DDR0_22, 0x00267F0B);
mtsdram(DDR0_23, 0x00000000);
mtsdram(DDR0_24, 0x01010002);
- mtsdram(DDR0_26, 0x5B260181);
+ if (speed > 133333334)
+ mtsdram(DDR0_26, 0x5B26050C);
+ else
+ mtsdram(DDR0_26, 0x5B260408);
mtsdram(DDR0_27, 0x0000682B);
mtsdram(DDR0_28, 0x00000000);
mtsdram(DDR0_31, 0x00000000);
mtsdram(DDR0_42, 0x01000006);
- mtsdram(DDR0_43, 0x050A0200);
- mtsdram(DDR0_44, 0x00000005);
+ mtsdram(DDR0_43, 0x030A0200);
+ mtsdram(DDR0_44, 0x00000003);
mtsdram(DDR0_02, 0x00000001);
wait_for_dlllock();
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index b2b82c7..930fa71 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -336,6 +336,10 @@ int misc_init_r(void)
}
#endif /* CONFIG_440EPX */
+ mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
+ reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
+ mtsdr(SDR0_SRST1, reg);
+
/*
* Clear PLB4A0_ACR[WRP]
* This fix will make the MAL burst disabling patch for the Linux
@@ -359,8 +363,8 @@ int checkboard(void)
printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
#endif
- rev = *(u8 *)(CFG_CPLD + 0);
- val = *(u8 *)(CFG_CPLD + 5) & 0x01;
+ rev = *(u8 *)(CFG_BCSR_BASE + 0);
+ val = *(u8 *)(CFG_BCSR_BASE + 5) & 0x01;
printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
if (s != NULL) {
diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
index c9eca68..c92dcf7 100644
--- a/board/amcc/yucca/init.S
+++ b/board/amcc/yucca/init.S
@@ -1,4 +1,7 @@
/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
*
* See file CREDITS for list of people who contributed to this
@@ -19,56 +22,10 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
-/* port to AMCC 440SPE evaluatioon board - SG April 12,2005 */
#include <ppc_asm.tmpl>
#include <config.h>
-
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
-#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn))
-#define TLB2(a) ((a) & 0x00000fbf)
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ;\
-0: mflr r0 ;\
- mtlr r1 ;\
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
+#include <asm-ppc/mmu.h>
/**************************************************************************
* TLB TABLE
@@ -89,12 +46,18 @@
.globl tlbtabA
tlbtabA:
tlbtab_start
- tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
- tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
@@ -126,12 +89,18 @@ tlbtabA:
.globl tlbtabB
tlbtabB:
tlbtab_start
- tlbentry(0xfff00000, SZ_16M, 0xfff00000, 4, AC_R|AC_W|AC_X|SA_G)
- tlbentry(CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CFG_SDRAM_BASE + 0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CFG_SDRAM_BASE + 0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry(CFG_SDRAM_BASE + 0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index e9b34dd..90eaab1 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -44,8 +44,6 @@ int compare_to_true(char *str );
char *remove_l_w_space(char *in_str );
char *remove_t_w_space(char *in_str );
int get_console_port(void);
-unsigned long ppcMfcpr(unsigned long cpr_reg);
-unsigned long ppcMfsdr(unsigned long sdr_reg);
int ppc440spe_init_pcie_rootport(int port);
void ppc440spe_setup_pcie(struct pci_controller *hose, int port);
@@ -221,7 +219,7 @@ int board_early_init_f (void)
|
+-------------------------------------------------------------------*/
/* Read Pin Strap Register in PPC440SP */
- sdr0_pinstp = ppcMfsdr(SDR0_PINSTP);
+ mfsdr(SDR0_PINSTP, sdr0_pinstp);
bootstrap_settings = sdr0_pinstp & SDR0_PINSTP_BOOTSTRAP_MASK;
switch (bootstrap_settings) {
@@ -246,7 +244,7 @@ int board_early_init_f (void)
* Boot Settings in IIC EEprom address 0x50 or 0x54
* Read Serial Device Strap Register1 in PPC440SPe
*/
- sdr0_sdstp1 = ppcMfsdr(SDR0_SDSTP1);
+ mfsdr(SDR0_SDSTP1, sdr0_sdstp1);
boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_ERPN_MASK;
ebc_data_width = sdr0_sdstp1 & SDR0_SDSTP1_EBCW_MASK;
@@ -564,277 +562,6 @@ int checkboard (void)
return 0;
}
-static long int yucca_probe_for_dimms(void)
-{
- int dimm_installed[MAXDIMMS];
- int dimm_num, result;
- int dimms_found = 0;
- uchar dimm_addr = IIC0_DIMM0_ADDR;
- uchar dimm_spd_data[MAX_SPD_BYTES];
-
- for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
- /* check if there is a chip at the dimm address */
- switch (dimm_num) {
- case 0:
- dimm_addr = IIC0_DIMM0_ADDR;
- break;
- case 1:
- dimm_addr = IIC0_DIMM1_ADDR;
- break;
- }
-
- result = i2c_probe(dimm_addr);
-
- memset(dimm_spd_data, 0, MAX_SPD_BYTES * sizeof(char));
- if (result == 0) {
- /* read first byte of SPD data, if there is any data */
- result = i2c_read(dimm_addr, 0, 1, dimm_spd_data, 1);
-
- if (result == 0) {
- result = dimm_spd_data[0];
- result = result > MAX_SPD_BYTES ?
- MAX_SPD_BYTES : result;
- result = i2c_read(dimm_addr, 0, 1,
- dimm_spd_data, result);
- }
- }
-
- if ((result == 0) &&
- (dimm_spd_data[64] == MICRON_SPD_JEDEC_ID)) {
- dimm_installed[dimm_num] = TRUE;
- dimms_found++;
- debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
- } else {
- dimm_installed[dimm_num] = FALSE;
- debug("DIMM slot %d: Not populated or cannot sucessfully probe the DIMM\n", dimm_num);
- }
- }
-
- if (dimms_found == 0) {
- printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
- hang();
- }
-
- if (dimm_installed[0] != TRUE) {
- printf("\nERROR - DIMM slot 0 must be populated before DIMM slot 1.\n");
- printf(" Unsupported configuration. Move DIMM module from DIMM slot 1 to slot 0.\n\n");
- hang();
- }
-
- return dimms_found;
-}
-
-/*************************************************************************
- * init SDRAM controller with fixed value
- * the initialization values are for 2x MICRON DDR2
- * PN: MT18HTF6472DY-53EB2
- * 512MB, DDR2, 533, CL4, ECC, REG
- ************************************************************************/
-static long int fixed_sdram(void)
-{
- long int yucca_dimms = 0;
-
- yucca_dimms = yucca_probe_for_dimms();
-
- /* SDRAM0_MCOPT2 (0X21) Clear DCEN BIT */
- mtdcr( 0x10, 0x00000021 );
- mtdcr( 0x11, 0x84000000 );
-
- /* SDRAM0_MCOPT1 (0X20) ECC OFF / 64 bits / 4 banks / DDR2 */
- mtdcr( 0x10, 0x00000020 );
- mtdcr( 0x11, 0x2D122000 );
-
- /* SET MCIF0_CODT Die Termination On */
- mtdcr( 0x10, 0x00000026 );
- if (yucca_dimms == 2)
- mtdcr( 0x11, 0x2A800021 );
- else if (yucca_dimms == 1)
- mtdcr( 0x11, 0x02800021 );
-
- /* On-Die Termination for Bank 0 */
- mtdcr( 0x10, 0x00000022 );
- if (yucca_dimms == 2)
- mtdcr( 0x11, 0x18000000 );
- else if (yucca_dimms == 1)
- mtdcr( 0x11, 0x06000000 );
-
- /* On-Die Termination for Bank 1 */
- mtdcr( 0x10, 0x00000023 );
- if (yucca_dimms == 2)
- mtdcr( 0x11, 0x18000000 );
- else if (yucca_dimms == 1)
- mtdcr( 0x11, 0x01800000 );
-
- /* On-Die Termination for Bank 2 */
- mtdcr( 0x10, 0x00000024 );
- if (yucca_dimms == 2)
- mtdcr( 0x11, 0x01800000 );
- else if (yucca_dimms == 1)
- mtdcr( 0x11, 0x00000000 );
-
- /* On-Die Termination for Bank 3 */
- mtdcr( 0x10, 0x00000025 );
- if (yucca_dimms == 2)
- mtdcr( 0x11, 0x01800000 );
- else if (yucca_dimms == 1)
- mtdcr( 0x11, 0x00000000 );
-
- /* Refresh Time register (0x30) Refresh every 7.8125uS */
- mtdcr( 0x10, 0x00000030 );
- mtdcr( 0x11, 0x08200000 );
-
- /* SET MCIF0_MMODE CL 4 */
- mtdcr( 0x10, 0x00000088 );
- mtdcr( 0x11, 0x00000642 );
-
- /* MCIF0_MEMODE */
- mtdcr( 0x10, 0x00000089 );
- mtdcr( 0x11, 0x00000004 );
-
- /*SET MCIF0_MB0CF */
- mtdcr( 0x10, 0x00000040 );
- mtdcr( 0x11, 0x00000201 );
-
- /* SET MCIF0_MB1CF */
- mtdcr( 0x10, 0x00000044 );
- mtdcr( 0x11, 0x00000201 );
-
- /* SET MCIF0_MB2CF */
- mtdcr( 0x10, 0x00000048 );
- if (yucca_dimms == 2)
- mtdcr( 0x11, 0x00000201 );
- else if (yucca_dimms == 1)
- mtdcr( 0x11, 0x00000000 );
-
- /* SET MCIF0_MB3CF */
- mtdcr( 0x10, 0x0000004c );
- if (yucca_dimms == 2)
- mtdcr( 0x11, 0x00000201 );
- else if (yucca_dimms == 1)
- mtdcr( 0x11, 0x00000000 );
-
- /* SET MCIF0_INITPLR0 # NOP */
- mtdcr( 0x10, 0x00000050 );
- mtdcr( 0x11, 0xB5380000 );
-
- /* SET MCIF0_INITPLR1 # PRE */
- mtdcr( 0x10, 0x00000051 );
- mtdcr( 0x11, 0x82100400 );
-
- /* SET MCIF0_INITPLR2 # EMR2 */
- mtdcr( 0x10, 0x00000052 );
- mtdcr( 0x11, 0x80820000 );
-
- /* SET MCIF0_INITPLR3 # EMR3 */
- mtdcr( 0x10, 0x00000053 );
- mtdcr( 0x11, 0x80830000 );
-
- /* SET MCIF0_INITPLR4 # EMR DLL ENABLE */
- mtdcr( 0x10, 0x00000054 );
- mtdcr( 0x11, 0x80810000 );
-
- /* SET MCIF0_INITPLR5 # MR DLL RESET */
- mtdcr( 0x10, 0x00000055 );
- mtdcr( 0x11, 0x80800542 );
-
- /* SET MCIF0_INITPLR6 # PRE */
- mtdcr( 0x10, 0x00000056 );
- mtdcr( 0x11, 0x82100400 );
-
- /* SET MCIF0_INITPLR7 # Refresh */
- mtdcr( 0x10, 0x00000057 );
- mtdcr( 0x11, 0x8A080000 );
-
- /* SET MCIF0_INITPLR8 # Refresh */
- mtdcr( 0x10, 0x00000058 );
- mtdcr( 0x11, 0x8A080000 );
-
- /* SET MCIF0_INITPLR9 # Refresh */
- mtdcr( 0x10, 0x00000059 );
- mtdcr( 0x11, 0x8A080000 );
-
- /* SET MCIF0_INITPLR10 # Refresh */
- mtdcr( 0x10, 0x0000005A );
- mtdcr( 0x11, 0x8A080000 );
-
- /* SET MCIF0_INITPLR11 # MR */
- mtdcr( 0x10, 0x0000005B );
- mtdcr( 0x11, 0x80800442 );
-
- /* SET MCIF0_INITPLR12 # EMR OCD Default*/
- mtdcr( 0x10, 0x0000005C );
- mtdcr( 0x11, 0x80810380 );
-
- /* SET MCIF0_INITPLR13 # EMR OCD Exit */
- mtdcr( 0x10, 0x0000005D );
- mtdcr( 0x11, 0x80810000 );
-
- /* 0x80: Adv Addr clock by 180 deg */
- mtdcr( 0x10, 0x00000080 );
- mtdcr( 0x11, 0x80000000 );
-
- /* 0x21: Exit self refresh, set DC_EN */
- mtdcr( 0x10, 0x00000021 );
- mtdcr( 0x11, 0x28000000 );
-
- /* 0x81: Write DQS Adv 90 + Fractional DQS Delay */
- mtdcr( 0x10, 0x00000081 );
- mtdcr( 0x11, 0x80000800 );
-
- /* MCIF0_SDTR1 */
- mtdcr( 0x10, 0x00000085 );
- mtdcr( 0x11, 0x80201000 );
-
- /* MCIF0_SDTR2 */
- mtdcr( 0x10, 0x00000086 );
- mtdcr( 0x11, 0x42103242 );
-
- /* MCIF0_SDTR3 */
- mtdcr( 0x10, 0x00000087 );
- mtdcr( 0x11, 0x0C100D14 );
-
- /* SET MQ0_B0BAS base addr 00000000 / 256MB */
- mtdcr( 0x40, 0x0000F800 );
-
- /* SET MQ0_B1BAS base addr 10000000 / 256MB */
- mtdcr( 0x41, 0x0400F800 );
-
- /* SET MQ0_B2BAS base addr 20000000 / 256MB */
- if (yucca_dimms == 2)
- mtdcr( 0x42, 0x0800F800 );
- else if (yucca_dimms == 1)
- mtdcr( 0x42, 0x00000000 );
-
- /* SET MQ0_B3BAS base addr 30000000 / 256MB */
- if (yucca_dimms == 2)
- mtdcr( 0x43, 0x0C00F800 );
- else if (yucca_dimms == 1)
- mtdcr( 0x43, 0x00000000 );
-
- /* SDRAM_RQDC */
- mtdcr( 0x10, 0x00000070 );
- mtdcr( 0x11, 0x8000003F );
-
- /* SDRAM_RDCC */
- mtdcr( 0x10, 0x00000078 );
- mtdcr( 0x11, 0x80000000 );
-
- /* SDRAM_RFDC */
- mtdcr( 0x10, 0x00000074 );
- mtdcr( 0x11, 0x00000220 );
-
- return (yucca_dimms * 512) << 20;
-}
-
-long int initdram (int board_type)
-{
- long dram_size = 0;
-
- dram_size = fixed_sdram();
-
- return dram_size;
-}
-
#if defined(CFG_DRAM_TEST)
int testdram (void)
{
@@ -1267,42 +994,3 @@ int onboard_pci_arbiter_selected(int core_pci)
#endif
return (BOARD_OPTION_NOT_SELECTED);
}
-
-/*---------------------------------------------------------------------------+
- | ppcMfcpr.
- +---------------------------------------------------------------------------*/
-unsigned long ppcMfcpr(unsigned long cpr_reg)
-{
- unsigned long msr;
- unsigned long cpr_cfgaddr_temp;
- unsigned long cpr_value;
-
- msr = (mfmsr () & ~(MSR_EE));
- cpr_cfgaddr_temp = mfdcr(CPR0_CFGADDR);
- mtdcr(CPR0_CFGADDR, cpr_reg);
- cpr_value = mfdcr(CPR0_CFGDATA);
- mtdcr(CPR0_CFGADDR, cpr_cfgaddr_temp);
- mtmsr(msr);
-
- return (cpr_value);
-}
-
-/*----------------------------------------------------------------------------+
-| Indirect Access of the System DCR's (SDR)
-| ppcMfsdr
-+----------------------------------------------------------------------------*/
-unsigned long ppcMfsdr(unsigned long sdr_reg)
-{
- unsigned long msr;
- unsigned long sdr_cfgaddr_temp;
- unsigned long sdr_value;
-
- msr = (mfmsr () & ~(MSR_EE));
- sdr_cfgaddr_temp = mfdcr(SDR0_CFGADDR);
- mtdcr(SDR0_CFGADDR, sdr_reg);
- sdr_value = mfdcr(SDR0_CFGDATA);
- mtdcr(SDR0_CFGADDR, sdr_cfgaddr_temp);
- mtmsr(msr);
-
- return (sdr_value);
-}
generated by cgit v0.10.2 at 2024-07-17 09:45:16 (GMT)