diff options
Diffstat (limited to 'board/amcc')
| -rw-r--r-- | board/amcc/bamboo/README | 77 | ||||
| -rw-r--r-- | board/amcc/ebony/README | 136 | ||||
| -rw-r--r-- | board/amcc/ocotea/README.ocotea | 73 | ||||
| -rw-r--r-- | board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot | 99 |
4 files changed, 385 insertions, 0 deletions
diff --git a/board/amcc/bamboo/README b/board/amcc/bamboo/README new file mode 100644 index 0000000..e139c6d --- /dev/null +++ b/board/amcc/bamboo/README @@ -0,0 +1,77 @@ +The 2 important dipswitches are configured as shown below: + +SW1 (for 33MHz SysClk) +---------------------- +S1 S2 S3 S4 S5 S6 S7 S8 +OFF OFF OFF OFF OFF OFF OFF ON + +SW7 (for Op-Code Flash and Boot Option H) +----------------------------------------- +S1 S2 S3 S4 S5 S6 S7 S8 +OFF OFF OFF ON OFF OFF OFF OFF + +The EEPROM at location 0x52 is loaded with these 16 bytes: +C47042A6 05D7A190 40082350 0d050000 + +SDR0_SDSTP0[ENG]: 1 : PLL's VCO is the source for PLL forward divisors +SDR0_SDSTP0[SRC]: 1 : Feedback originates from PLLOUTB +SDR0_SDSTP0[SEL]: 0 : Feedback selection is PLL output +SDR0_SDSTP0[TUNE]: 1000111000 : 10 <= M <= 22, 600MHz < VCO <= 900MHz +SDR0_SDSTP0[FBDV]: 4 : PLL feedback divisor +SDR0_SDSTP0[FBDVA]: 2 : PLL forward divisor A +SDR0_SDSTP0[FBDVB]: 5 : PLL forward divisor B +SDR0_SDSTP0[PRBDV0]: 1 : PLL primary divisor B +SDR0_SDSTP0[OPBDV0]: 2 : OPB clock divisor +SDR0_SDSTP0[LFBDV]: 1 : PLL local feedback divisor +SDR0_SDSTP0[PERDV0]: 3 : Peripheral clock divisor 0 +SDR0_SDSTP0[MALDV0]: 2 : MAL clock divisor 0 +SDR0_SDSTP0[PCIDV0]: 2 : Sync PCI clock divisor 0 +SDR0_SDSTP0[PLLTIMER]: 7 : PLL locking timer +SDR0_SDSTP0[RW]: 1 : EBC ROM width: 16-bit +SDR0_SDSTP0[RL]: 0 : EBC ROM location: EBC +SDR0_SDSTP0[PAE]: 0 : PCI internal arbiter: disabled +SDR0_SDSTP0[PHCE]: 0 : PCI host configuration: disabled +SDR0_SDSTP0[ZM]: 3 : ZMII mode: RMII mode 100 +SDR0_SDSTP0[CTE]: 0 : CPU trace: disabled +SDR0_SDSTP0[Nto1]: 0 : CPU/PLB ratio N/P: not N to 1 +SDR0_SDSTP0[PAME]: 1 : PCI asynchronous mode: enabled +SDR0_SDSTP0[MEM]: 1 : Multiplex: EMAC +SDR0_SDSTP0[NE]: 0 : NDFC: disabled +SDR0_SDSTP0[NBW]: 0 : NDFC boot width: 8-bit +SDR0_SDSTP0[NBW]: 0 : NDFC boot page selection +SDR0_SDSTP0[NBAC]: 0 : NDFC boot address selection cycle: 3 Addr. Cycles, 1 Col. + 2 Row (512 page size) +SDR0_SDSTP0[NARE]: 0 : NDFC auto read : disabled +SDR0_SDSTP0[NRB]: 0 : NDFC Ready/Busy : Ready +SDR0_SDSTP0[NDRSC]: 33333 : NDFC device reset counter +SDR0_SDSTP0[NCG0]: 0 : NDFC/EBC chip select gating CS0 : EBC +SDR0_SDSTP0[NCG1]: 0 : NDFC/EBC chip select gating CS1 : EBC +SDR0_SDSTP0[NCG2]: 0 : NDFC/EBC chip select gating CS2 : EBC +SDR0_SDSTP0[NCG3]: 0 : NDFC/EBC chip select gating CS3 : EBC +SDR0_SDSTP0[NCRDC]: 3333 : NDFC device read count + +PPC440EP Clocking Configuration + +SysClk is 33.0MHz, M is 20, VCO is 660.0MHz, CPU is 330.0MHz, PLB is 132.0MHz +OPB is 66.0MHz, EBC is 44.0MHz, MAL is 66.0MHz, Sync PCI is 66.0MHz + +The above information is reported by Eugene O'Brien +<Eugene.O'Brien@advantechamt.com>. Thanks a lot. + +2007-08-06, Stefan Roese <sr@denx.de> +--------------------------------------------------------------------- + +The configuration for the AMCC 440EP eval board "Bamboo" was changed +to only use 384 kbytes of FLASH for the U-Boot image. This way the +redundant environment can be saved in the remaining 2 sectors of the +same flash chip. + +Caution: With an upgrade from an earlier U-Boot version the current +environment will be erased since the environment is now saved in +different sectors. By using the following command the environment can +be saved after upgrading the U-Boot image and *before* resetting the +board: + +setenv recover_env 'prot off FFF80000 FFF9FFFF;era FFF80000 FFF9FFFF;' \ + 'cp.b FFF60000 FFF80000 20000' + +2006-07-27, Stefan Roese <sr@denx.de> diff --git a/board/amcc/ebony/README b/board/amcc/ebony/README new file mode 100644 index 0000000..4df00b3 --- /dev/null +++ b/board/amcc/ebony/README @@ -0,0 +1,136 @@ + AMCC Ebony Board + + Last Update: September 12, 2002 +======================================================================= + +This file contains some handy info regarding U-Boot and the AMCC +Ebony evaluation board. See the README.ppc440 for additional +information. + + +SWITCH SETTINGS & JUMPERS +========================== + +Here's what I've been using successfully. If you feel inclined to +change things ... please read the docs! + +DIPSW U46 U80 +------------------------ +SW 1 off on +SW 2 on on +SW 3 on on +SW 4 off on +SW 5 on off +SW 6 on on +SW 7 on off +SW 8 on off + +J41: strapped +J42: open + +All others are factory default. + + +I2C probe +===================== + +The i2c utilities have been tested on both Rev B. and Rev C. and +look good. The CONFIG_SYS_I2C_NOPROBES macro is defined to prevent +probing the CDCV850 clock controller at address 0x69 (since reading +it causes the i2c implementation to misbehave. The output of +'i2c probe' should look like this (assuming you are only using a single +SO-DIMM: + +=> i2c probe +Valid chip addresses: 50 53 54 +Excluded chip addresses: 69 + + +GETTING OUT OF I2C TROUBLE +=========================== + +If you're like me ... you may have screwed up your bootstrap serial +eeprom ... or worse, your SPD eeprom when experimenting with the +i2c commands. If so, here are some ideas on how to get out of +trouble: + +Serial bootstrap eeprom corruption: +----------------------------------- +Power down the board and set the following straps: + +J41 - open +J42 - strapped + +This will select the default sys0 and sys1 settings (the serial +eeproms are not used). Then power up the board and fix the serial +eeprom using the 'i2c mm' command. Here are the values I currently +use: + +=> i2c md 50 0 10 +0000: bf a2 04 01 ae 94 11 00 00 00 00 00 00 00 00 00 ................ + +=> i2c md 54 0 10 +0000: 8f b3 24 01 4d 14 11 00 00 00 00 00 00 00 00 00 ..$.M........... + +Once you have the eeproms set correctly change the +J41/J42 straps as you desire. + +SPD eeprom corruption: +------------------------ +I've corrupted the SPD eeprom several times ... perhaps too much coffee +and not enough presence of mind ;-). By default, the ebony code uses +the SPD to initialize the DDR SDRAM control registers. So if the SPD +eeprom is corrupted, U-Boot will never get into ram. Here's how I got +out of this situation: + +0. First, _before_ playing with the i2c utilities, do an 'i2c probe', then +use 'i2c md' to capture the various device contents to a file. Some day +you may be glad you did this ... trust me :-). Otherwise try the +following: + +1. In the include/configs/EBONY.h file find the line that defines +the CONFIG_SPD_EEPROM macro and undefine it. E.g: + +#undef CONFIG_SPD_EEPROM + +This will make the code use default SDRAM control register +settings without using the SPD eeprom. + +2. Rebuild U-Boot + +3. Load the new U-Boot image and reboot ebony. + +4. Repair the SPD eeprom using the 'i2c mm' command. Here's the eeprom +contents that work with the default SO-DIMM that comes with the +ebony board (micron 8VDDT164AG-265A1). Note: these are probably +_not_ the factory settings ... but they work. + +=> i2c md 53 0 10 80 +0000: 80 08 07 0c 0a 01 40 00 04 75 75 00 80 08 00 01 ......@..uu..... +0010: 0e 04 0c 01 02 20 00 a0 75 00 00 50 3c 50 2d 20 ..... ..u..P<P- +0020: 90 90 50 50 00 00 00 00 00 41 4b 34 32 75 00 00 ..PP.....AK42u.. +0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9c ................ +0040: 2c 00 00 00 00 00 00 00 08 38 56 44 44 54 31 36 ,........8VDDT16 +0050: 36 34 41 47 2d 32 36 35 41 31 20 01 00 01 2c 63 64AG-265A1 ...,c +0060: 22 25 ab 00 00 00 00 00 00 00 00 00 00 00 00 00 "%.............. +0070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ + + +PCI DOUBLE-ENUMERATION WOES +=========================== + +If you're not using PCI-X cards and are simply using 32-bit and/or +33 MHz cards via extenders and the like, you may notice that the +initial pci scan reports various devices twice ... and configuration +does not succeed (one or more devices are enumerated twice). To correct +this we replaced the 2K ohm resistor on the IDSEL line(s) with a +22 ohm resistor and the problem went away. This change hasn't broken +anything yet -- use at your own risk. + +We never tested anything other than 33 MHz/32-bit cards. If you have +the chance to do this, please let me know how things turn out :-) + + +Regards, +--Scott +<smcnutt@artesyncp.com> diff --git a/board/amcc/ocotea/README.ocotea b/board/amcc/ocotea/README.ocotea new file mode 100644 index 0000000..be79b03 --- /dev/null +++ b/board/amcc/ocotea/README.ocotea @@ -0,0 +1,73 @@ + AMCC Ocotea Board + + Last Update: March 2, 2004 +======================================================================= + +This file contains some handy info regarding U-Boot and the AMCC +Ocotea 440gx evaluation board. See the README.ppc440 for additional +information. + + +SWITCH SETTINGS & JUMPERS +========================== + +Here's what I've been using successfully. If you feel inclined to +change things ... please read the docs! + +DIPSW U46 U80 +------------------------ +SW 1 off off +SW 2 on off +SW 3 off off +SW 4 off off +SW 5 off off +SW 6 on on +SW 7 on off +SW 8 on off + +J41: strapped +J42: open + +All others are factory default. + + +I2C Information +===================== + +See README.ebony for information. + +PCI +=========================== + +Untested at the time of writing. + +PPC440GX Ethernet EMACs +=========================== + +All EMAC ports have been tested and are known to work +with EPS Group 4. + +Special note about the Cicada CIS8201: + The CIS8201 Gigabit PHY comes up in GMII mode by default. + One must hit an extended register to allow use of RGMII mode. + This has been done in the 440gx_enet.c file with a #ifdef/endif + pair. + +AMCC does not store the EMAC ethernet addresses within their PIBS bootloader. +The addresses contained in the config header file are from my particular +board and you _*should*_ change them to reflect your board either in the +config file and/or in your environment variables. I found the addresses on +labels on the bottom side of the board. + + +BDI2k or JTAG Debugging +=========================== + +For ease of debugging you can swap the small boot flash and external SRAM +by changing U46:3 to on. You can then use the sram as your boot flash by +loading the sram via the jtag debugger. + + +Regards, +--Travis +<tsawyer@sandburst.com> diff --git a/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot b/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot new file mode 100644 index 0000000..25dd2a2 --- /dev/null +++ b/board/amcc/ocotea/README.ocotea-PIBS-to-U-Boot @@ -0,0 +1,99 @@ +------------------------------------------ +Installation of U-Boot using PIBS firmware +------------------------------------------ + +This document describes how to install U-Boot on the Ocotea PPC440GX +Evaluation Board. We do not erase the PIBS firmware but install U-Boot in the +soldered FLASH. After this you should be able to switch between PIBS and +U-Boot via the switch U46 SW1. Please check that SW1 is off (= open) before +continuing. + +Connect to the serial port 0 (J11 lower) of the Ocotea board using the cu +program. See the hints for configuring cu above. Make sure you can +communicate with the PIBS firmware: reset the board and hit ENTER a couple of +times until you see the PIBS prompt (PIBS $). Then proceed as follows: + + +Read MAC Addresses from PIBS +---------------------------- + +To read the configured MAC addresses available on your Ocotea board please use +the following commands: + +PIBS $ echo $hwdaddr0 +000173017FE3 +PIBS $ echo $hwdaddr1 +000173017FE4 +PIBS $ echo $hwdaddr2 +000173017FE1 +PIBS $ echo $hwdaddr3 +000173017FE2 + +In U-Boot this is stored in the following environment variables: + +* Ethernet Address 0: ethaddr = 000173017FE3 (==> 00:01:73:01:7F:E3) +* Ethernet Address 1: eth1addr = 000173017FE4 (==> 00:01:73:01:7F:E4) +* Ethernet Address 2: eth2addr = 000173017FE1 (==> 00:01:73:01:7F:E1) +* Ethernet Address 3: eth3addr = 000173017FE2 (==> 00:01:73:01:7F:E2) + + +Configure the network interface (ent0 == emac0) +----------------------------------------------- + +To download the U-Boot image we need to configure the ethernet interface with +the following commands: + +PIBS $ ifconfig ent0 192.168.160.142 netmask 255.255.0.0 up +PIBS $ set ipdstaddr0=192.168.1.1 +status: writing PIBS variable value to FLASH +PIBS $ set bootfilename=/tftpboot/ocotea/u-boot.bin +status: writing PIBS variable value to FLASH + +Please insert correct parameters for your configuration (ip-addresses and +file-location). + + +Program U-Boot into soldered User-FLASH +--------------------------------------- + +Please make sure to use a newer version of U-Boot (at least 1.1.3), since +older versions don't support running from user-FLASH. + +To program U-Boot into the soldered user-FLASH use the following command: + +PIBS $ storefile bin eth 0xffbc0000 + +This commands loads the file vis ethernet into ram and copies it into the +user-FLASH. + + +Switch to U-Boot +---------------- + +Now you can turn your board off and switch SW1 (U46) to on (= closed). After +powering the board you should see the following message: + +U-Boot 1.1.3 (Apr 5 2005 - 22:59:57) + +AMCC PowerPC 440 GX Rev. C +Board: AMCC 440GX Evaluation Board + VCO: 1066 MHz + CPU: 533 MHz + PLB: 152 MHz + OPB: 76 MHz + EPB: 76 MHz +I2C: ready +DRAM: 256 MB +FLASH: 5 MB +PCI: Bus Dev VenId DevId Class Int +In: serial +Out: serial +Err: serial +KGDB: kgdb ready +ready +Net: ppc_440x_eth0, ppc_440x_eth1, ppc_440x_eth2, ppc_440x_eth3 +BEDBUG:ready +=> + + +April 06 2005, Stefan Roese <sr@denx.de> |