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-rw-r--r--board/cray/L1/L1.c9
-rw-r--r--board/cray/L1/Makefile2
-rw-r--r--board/cray/L1/flash.c119
-rw-r--r--board/cray/L1/init.S106
-rw-r--r--board/cray/L1/u-boot.lds5
-rw-r--r--board/cray/L1/u-boot.lds.debug6
6 files changed, 126 insertions, 121 deletions
diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c
index b1e2783..af0456d 100644
--- a/board/cray/L1/L1.c
+++ b/board/cray/L1/L1.c
@@ -25,9 +25,6 @@
#include <asm/processor.h>
#include <405gp_i2c.h>
#include <command.h>
-#include <cmd_nvedit.h>
-#include <cmd_bootm.h>
-#include <cmd_boot.h>
#include <rtc.h>
#include <post.h>
#include <net.h>
@@ -249,7 +246,7 @@ int testdram (void)
*p = 0xaaaaaaaa;
for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
+ printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
(uint) p, *p, 0xaaaaaaaa);
return 1;
}
@@ -259,7 +256,7 @@ int testdram (void)
*p = 0x55555555;
for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
+ printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
(uint) p, *p, 0x55555555);
return 1;
}
@@ -269,7 +266,7 @@ int testdram (void)
*p = (unsigned)p;
for (p = pstart; p < pend; p++) {
if (*p != (unsigned)p) {
- printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
+ printf ("SDRAM test fails at: %08x, was %08x expected %08x\n",
(uint) p, *p, (uint)p);
return 1;
}
diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile
index e7dc0a8..bfe0922 100644
--- a/board/cray/L1/Makefile
+++ b/board/cray/L1/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
-SOBJS = init.o
+SOBJS = init.o
# HACK: depend needs bootscript.c, which needs tools/mkimage, which is not
# built in the depend stage. So... put bootscript.o here, not in OBJS
diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c
index 829dbae..f313274 100644
--- a/board/cray/L1/flash.c
+++ b/board/cray/L1/flash.c
@@ -99,7 +99,6 @@ unsigned long flash_init (void)
}
-
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
@@ -116,10 +115,10 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
void flash_print_info (flash_info_t *info)
{
int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *flash;
+ int k;
+ int size;
+ int erased;
+ volatile unsigned long *flash;
if (info->flash_id == FLASH_UNKNOWN) {
printf ("missing or unknown FLASH type\n");
@@ -143,24 +142,24 @@ void flash_print_info (flash_info_t *info)
printf (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i) {
- /*
- * Check if whole sector is erased
- */
- if (i != (info->sector_count-1))
- size = info->start[i+1] - info->start[i];
- else
- size = info->start[0] + info->size - info->start[i];
- erased = 1;
- flash = (volatile unsigned long *)info->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++)
- {
- if (*flash++ != 0xffffffff)
- {
- erased = 0;
- break;
- }
- }
+ /*
+ * Check if whole sector is erased
+ */
+ if (i != (info->sector_count-1))
+ size = info->start[i+1] - info->start[i];
+ else
+ size = info->start[0] + info->size - info->start[i];
+ erased = 1;
+ flash = (volatile unsigned long *)info->start[i];
+ size = size >> 2; /* divide by 4 for longword access */
+ for (k=0; k<size; k++)
+ {
+ if (*flash++ != 0xffffffff)
+ {
+ erased = 0;
+ break;
+ }
+ }
if ((i % 5) == 0)
printf ("\n ");
@@ -189,7 +188,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
short i;
FLASH_WORD_SIZE value;
ulong base = (ulong)addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)addr;
/* Write auto select command: read Manufacturer ID */
addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
@@ -232,7 +231,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
addr2 = (volatile FLASH_WORD_SIZE *)(info->start[i]);
- info->protect[i] = addr2[2] & 1;
+ info->protect[i] = addr2[2] & 1;
}
/*
@@ -254,15 +253,15 @@ int wait_for_DQ7(flash_info_t *info, int sect)
start = get_timer (0);
last = start;
while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
- if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return -1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return -1;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
}
return 0;
}
@@ -427,42 +426,42 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
- volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
+ volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *)(info->start[0]);
+ volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *)dest;
+ volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *)&data;
ulong start;
int flag;
- int i;
+ int i;
/* Check if Flash is (sufficiently) erased */
if ((*((volatile FLASH_WORD_SIZE *)dest) &
- (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
+ (FLASH_WORD_SIZE)data) != (FLASH_WORD_SIZE)data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
- for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
- {
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
- addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
- addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
-
- dest2[i] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
- if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
+ for (i=0; i<4/sizeof(FLASH_WORD_SIZE); i++)
+ {
+ addr2[ADDR0] = (FLASH_WORD_SIZE)0x00AA00AA;
+ addr2[ADDR1] = (FLASH_WORD_SIZE)0x00550055;
+ addr2[ADDR0] = (FLASH_WORD_SIZE)0x00A000A0;
+
+ dest2[i] = data2[i];
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
+ (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ }
return (0);
}
diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S
index acc5205..72a10d3 100644
--- a/board/cray/L1/init.S
+++ b/board/cray/L1/init.S
@@ -52,53 +52,53 @@
/* control registers to set that up are determined by what we've */
/* empirically discovered work there. */
- .globl ext_bus_cntlr_init
+ .globl ext_bus_cntlr_init
ext_bus_cntlr_init:
- mflr r4 /* save link register */
- bl ..getAddr
+ mflr r4 /* save link register */
+ bl ..getAddr
..getAddr:
- mflr r3 /* get address of ..getAddr */
- mtlr r4 /* restore link register */
- addi r4,0,14 /* set ctr to 10; used to prefetch */
- mtctr r4 /* 10 cache lines to fit this function */
- /* in cache (gives us 8x10=80 instrctns) */
+ mflr r3 /* get address of ..getAddr */
+ mtlr r4 /* restore link register */
+ addi r4,0,14 /* set ctr to 10; used to prefetch */
+ mtctr r4 /* 10 cache lines to fit this function */
+ /* in cache (gives us 8x10=80 instrctns) */
..ebcloop:
- icbt r0,r3 /* prefetch cache line for addr in r3 */
- addi r3,r3,32 /* move to next cache line */
- bdnz ..ebcloop /* continue for 10 cache lines */
+ icbt r0,r3 /* prefetch cache line for addr in r3 */
+ addi r3,r3,32 /* move to next cache line */
+ bdnz ..ebcloop /* continue for 10 cache lines */
- /*------------------------------------------------------------------- */
- /* Delay to ensure all accesses to ROM are complete before changing */
+ /*------------------------------------------------------------------- */
+ /* Delay to ensure all accesses to ROM are complete before changing */
/* bank 0 timings. 200usec should be enough. */
- /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
- /*------------------------------------------------------------------- */
+ /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+ /*------------------------------------------------------------------- */
addis r3,0,0x0
- ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
- mtctr r3
+ ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
+ mtctr r3
..spinlp:
- bdnz ..spinlp /* spin loop */
+ bdnz ..spinlp /* spin loop */
- /*---------------------------------------------------------------------- */
- /* Peripheral Bank 0 (Flash) initialization */
- /*---------------------------------------------------------------------- */
+ /*---------------------------------------------------------------------- */
+ /* Peripheral Bank 0 (Flash) initialization */
+ /*---------------------------------------------------------------------- */
/* 0x7F8FFE80 slowest boot */
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
- addis r4,0,0x9B01
- ori r4,r4,0x5480
- mtdcr ebccfgd,r4
-
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
- addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
- ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
- mtdcr ebccfgd,r4
-
- blr
-
- /*---------------------------------------------------------------------- */
- /* Peripheral Bank 1 (NVRAM/RTC) initialization */
+ addi r4,0,pb0ap
+ mtdcr ebccfga,r4
+ addis r4,0,0x9B01
+ ori r4,r4,0x5480
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb0cr
+ mtdcr ebccfga,r4
+ addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
+ ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
+ mtdcr ebccfgd,r4
+
+ blr
+
+ /*---------------------------------------------------------------------- */
+ /* Peripheral Bank 1 (NVRAM/RTC) initialization */
/* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */
/* and we do DMA on it. The ConfigurationRegister part is threfore */
/* almost arbitrary, except that our linux driver needs to know the */
@@ -119,21 +119,21 @@ ext_bus_cntlr_init:
/* ByteEnableMode BEM=0 */
/* ParityEnable PEN=0 */
/* all reserved bits=0 */
- /*---------------------------------------------------------------------- */
- /*---------------------------------------------------------------------- */
- addi r4,0,pb1ap
- mtdcr ebccfga,r4
- addis r4,0,0x0185 /* hiword */
- ori r4,r4,0x4380 /* loword */
- mtdcr ebccfgd,r4
-
- addi r4,0,pb1cr
- mtdcr ebccfga,r4
- addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
- ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
- mtdcr ebccfgd,r4
-
- blr
+ /*---------------------------------------------------------------------- */
+ /*---------------------------------------------------------------------- */
+ addi r4,0,pb1ap
+ mtdcr ebccfga,r4
+ addis r4,0,0x0185 /* hiword */
+ ori r4,r4,0x4380 /* loword */
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb1cr
+ mtdcr ebccfga,r4
+ addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
+ ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
+ mtdcr ebccfgd,r4
+
+ blr
/*----------------------------------------------------------------------------- */
/* Function: sdram_init */
@@ -141,7 +141,7 @@ ext_bus_cntlr_init:
/* NOTE: for CrayL1 we have ECC memory, so enable it. */
/*....now done in C in L1.c:init_sdram for readability. */
/*----------------------------------------------------------------------------- */
- .globl sdram_init
+ .globl sdram_init
sdram_init:
blr
diff --git a/board/cray/L1/u-boot.lds b/board/cray/L1/u-boot.lds
index a709158..88c880e 100644
--- a/board/cray/L1/u-boot.lds
+++ b/board/cray/L1/u-boot.lds
@@ -121,6 +121,11 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug
index f4f9743..d483424 100644
--- a/board/cray/L1/u-boot.lds.debug
+++ b/board/cray/L1/u-boot.lds.debug
@@ -106,6 +106,11 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
@@ -128,4 +133,3 @@ SECTIONS
_end = . ;
PROVIDE (end = .);
}
-
generated by cgit v0.10.2 at 2024-11-21 09:57:10 (GMT)