summaryrefslogtreecommitdiff
path: root/board/esd/vme8349/pci.c
diff options
context:
space:
mode:
Diffstat (limited to 'board/esd/vme8349/pci.c')
-rw-r--r--board/esd/vme8349/pci.c33
1 files changed, 25 insertions, 8 deletions
diff --git a/board/esd/vme8349/pci.c b/board/esd/vme8349/pci.c
index d15203c..94fd32a 100644
--- a/board/esd/vme8349/pci.c
+++ b/board/esd/vme8349/pci.c
@@ -2,6 +2,9 @@
* pci.c -- esd VME8349 PCI board support.
* Copyright (c) 2006 Wind River Systems, Inc.
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
+ * Copyright (c) 2009 esd gmbh.
+ *
+ * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
*
* Based on MPC8349 PCI support but w/o PIB related code.
*
@@ -32,6 +35,7 @@
#include <pci.h>
#include <i2c.h>
#include <asm/fsl_i2c.h>
+#include "vme8349pin.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -93,17 +97,22 @@ pci_init_board(void)
udelay(2000);
/*
- * Assert/deassert PCI reset
+ * Assert/deassert VME reset
*/
- setbits_be32(&immr->gpio[0].dat, 0x00800000);
- setbits_be32(&immr->gpio[0].dir, 0x00800000);
- setbits_be32(&immr->gpio[1].dir, 0x08800000);
+ clrsetbits_be32(&immr->gpio[1].dat,
+ GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
+ GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N);
+ setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
+ GPIO2_TSI_POWERUP_RESET_N |
+ GPIO2_VME_RESET_N |
+ GPIO2_L_RESET_EN_N);
+ clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
udelay(200);
- setbits_be32(&immr->gpio[1].dat, 0x08000000);
+ setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
udelay(200);
- setbits_be32(&immr->gpio[1].dat, 0x08800000);
+ setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
udelay(600000);
- clrbits_be32(&immr->gpio[1].dat, 0x00100000);
+ clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
/* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
@@ -114,6 +123,14 @@ pci_init_board(void)
udelay(2000);
- if (monarch == 0)
+ if (monarch == 0) {
mpc83xx_pci_init(1, reg, 0);
+ } else {
+ /*
+ * Release PCI RST Output signal
+ */
+ out_be32(&immr->pci_ctrl[0].gcr, 0);
+ udelay(2000);
+ out_be32(&immr->pci_ctrl[0].gcr, 1);
+ }
}