diff options
Diffstat (limited to 'board/freescale/ls1043aqds')
| -rw-r--r-- | board/freescale/ls1043aqds/README | 37 | ||||
| -rw-r--r-- | board/freescale/ls1043aqds/ddr.c | 1 | ||||
| -rw-r--r-- | board/freescale/ls1043aqds/ddr.h | 30 | ||||
| -rw-r--r-- | board/freescale/ls1043aqds/ls1043aqds.c | 16 |
4 files changed, 21 insertions, 63 deletions
diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README index a6fd7a3..913537d 100644 --- a/board/freescale/ls1043aqds/README +++ b/board/freescale/ls1043aqds/README @@ -8,41 +8,8 @@ debugging environment. LS1043A SoC Overview -------------------- -The LS1043A integrated multicore processor combines four ARM Cortex-A53 -processor cores with datapath acceleration optimized for L2/3 packet -processing, single pass security offload and robust traffic management -and quality of service. - -The LS1043A SoC includes the following function and features: - - Four 64-bit ARM Cortex-A53 CPUs - - 1 MB unified L2 Cache - - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving - support - - Data Path Acceleration Architecture (DPAA) incorporating acceleration the - the following functions: - - Packet parsing, classification, and distribution (FMan) - - Queue management for scheduling, packet sequencing, and congestion - management (QMan) - - Hardware buffer management for buffer allocation and de-allocation (BMan) - - Cryptography acceleration (SEC) - - Ethernet interfaces by FMan - - Up to 1 x XFI supporting 10G interface - - Up to 1 x QSGMII - - Up to 4 x SGMII supporting 1000Mbps - - Up to 2 x SGMII supporting 2500Mbps - - Up to 2 x RGMII supporting 1000Mbps - - High-speed peripheral interfaces - - Three PCIe 2.0 controllers, one supporting x4 operation - - One serial ATA (SATA 3.0) controllers - - Additional peripheral interfaces - - Three high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Quad Serial Peripheral Interface (QSPI) Controller - - Serial peripheral interface (SPI) controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller supporting NAND and NOR flash - - QorIQ platform's trust architecture 2.1 +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A +SoC overview. LS1043AQDS board Overview ----------------------- diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 3d3c533..0fd835d 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -116,6 +116,7 @@ phys_size_t initdram(int board_type) dram_size = fsl_ddr_sdram(); #endif + erratum_a008850_post(); #ifdef CONFIG_FSL_DEEP_SLEEP fsl_dp_ddr_restore(); diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h index 8adb660..ad709ba 100644 --- a/board/freescale/ls1043aqds/ddr.h +++ b/board/freescale/ls1043aqds/ddr.h @@ -7,6 +7,8 @@ #ifndef __DDR_H__ #define __DDR_H__ +extern void erratum_a008850_post(void); + struct board_specific_parameters { u32 n_ranks; u32 datarate_mhz_high; @@ -32,21 +34,21 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ #ifdef CONFIG_SYS_FSL_DDR4 - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E0A,}, - {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, - {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E0A,}, + {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, + {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,}, #elif defined(CONFIG_SYS_FSL_DDR3) - {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, - {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, #else #error DDR type not defined #endif diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index fba6b88..7e47ef0 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -238,8 +238,8 @@ int board_early_init_f(void) out_be32(&scfg->rcwpmuxcr0, 0x3333); out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); usb_pwrfault = - (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) | - (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) | (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); #endif @@ -307,14 +307,6 @@ int misc_init_r(void) int board_init(void) { - struct ccsr_cci400 *cci = (struct ccsr_cci400 *) - CONFIG_SYS_CCI400_ADDR; - - /* Set CCI-400 control override register to enable barrier - * transaction */ - out_le32(&cci->ctrl_ord, - CCI400_CTRLORD_EN_BARRIER); - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); board_retimer_init(); @@ -325,10 +317,6 @@ int board_init(void) #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif - -#ifdef CONFIG_ENV_IS_NOWHERE - gd->env_addr = (ulong)&default_environment[0]; -#endif return 0; } |