1 files changed, 0 insertions, 68 deletions
diff --git a/board/freescale/mpc8548cds/init.S b/board/freescale/mpc8548cds/init.S
index ed0fc44..51e1cc4 100644
--- a/board/freescale/mpc8548cds/init.S
+++ b/board/freescale/mpc8548cds/init.S
@@ -182,71 +182,3 @@ tlb1_entry:
 
 2:
 	entry_end
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
- * 0xa000_0000     0xbfff_ffff     PCIe MEM                512M
- * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
- * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe10f_ffff     PCI1 IO                 1M
- * 0xe280_0000     0xe20f_ffff     PCI2 IO                 1M
- * 0xe300_0000     0xe30f_ffff     PCIe IO                 1M
- * 0xf000_0000     0xf3ff_ffff     SDRAM                   64M
- * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
- * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M
- * 0xff80_0000     0xffff_ffff     FLASH (boot bank)       8M
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- *
- * LAW 0 is reserved for boot mapping
- */
-
-	.section .bootpg, "ax"
-	.globl	law_entry
-law_entry:
-	entry_start
-
-	.long (4f-3f)/8
-3:
-	.long  0
-	.long  (LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
-
-#ifdef CFG_PCI1_MEM_PHYS
-	.long	(CFG_PCI1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
-	.long	(CFG_PCI1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
-#endif
-
-#ifdef CFG_PCI2_MEM_PHYS
-	.long	(CFG_PCI2_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
-	.long	(CFG_PCI2_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
-#endif
-
-#ifdef CFG_PCIE1_MEM_PHYS
-	.long	(CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-
-	.long	(CFG_PCIE1_IO_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
-#endif
-
-	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-	.long	(CFG_LBC_CACHE_BASE>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
-
-#ifdef CFG_RIO_MEM_PHYS
-	.long	(CFG_RIO_MEM_PHYS>>12) & 0xfffff
-	.long	LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
-#endif
-4:
-	entry_end